619 lines
16 KiB
Verilog
619 lines
16 KiB
Verilog
`timescale 1ns / 1ps
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//////////////////////////////////////////////////////////////////////////////////
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// Company:
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// Engineer:
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//
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// Create Date: 21:57:50 08/25/2009
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// Design Name:
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// Module Name: mcu_cmd
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// Project Name:
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// Target Devices:
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// Tool versions:
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// Description:
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//
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// Dependencies:
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//
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// Revision:
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// Revision 0.01 - File Created
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// Additional Comments:
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//
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//////////////////////////////////////////////////////////////////////////////////
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module mcu_cmd(
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input clk,
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input cmd_ready,
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input param_ready,
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input [7:0] cmd_data,
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input [7:0] param_data,
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output [2:0] mcu_mapper,
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output mcu_rrq,
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output mcu_write,
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output mcu_wrq,
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input mcu_rq_rdy,
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output [7:0] mcu_data_out,
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input [7:0] mcu_data_in,
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output [7:0] spi_data_out,
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input [31:0] spi_byte_cnt,
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input [2:0] spi_bit_cnt,
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output [23:0] addr_out,
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output [23:0] saveram_mask_out,
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output [23:0] rom_mask_out,
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output reg ramsel_out,
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// SD "DMA" extension
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output SD_DMA_EN,
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input SD_DMA_STATUS,
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input SD_DMA_NEXTADDR,
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input [7:0] SD_DMA_SRAM_DATA,
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input SD_DMA_SRAM_WE,
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output [1:0] SD_DMA_TGT,
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output SD_DMA_PARTIAL,
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output [10:0] SD_DMA_PARTIAL_START,
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output [10:0] SD_DMA_PARTIAL_END,
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// DAC
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output [10:0] dac_addr_out,
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input DAC_STATUS,
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output dac_play_out,
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output dac_reset_out,
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// MSU data
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output [13:0] msu_addr_out,
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input [6:0] MSU_STATUS,
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output [5:0] msu_status_reset_out,
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output [5:0] msu_status_set_out,
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output msu_status_reset_we,
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input [31:0] msu_addressrq,
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input [15:0] msu_trackrq,
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input [7:0] msu_volumerq,
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output [13:0] msu_ptr_out,
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output msu_reset_out,
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// BS-X
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output [7:0] bsx_regs_reset_out,
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output [7:0] bsx_regs_set_out,
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output bsx_regs_reset_we,
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// generic RTC
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output [55:0] rtc_data_out,
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output rtc_pgm_we,
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// S-RTC
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output srtc_reset,
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// uPD77C25
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output reg [23:0] dspx_pgm_data_out,
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output reg [10:0] dspx_pgm_addr_out,
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output reg dspx_pgm_we_out,
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output reg [15:0] dspx_dat_data_out,
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output reg [10:0] dspx_dat_addr_out,
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output reg dspx_dat_we_out,
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output reg dspx_reset_out,
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// feature enable
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output reg [3:0] featurebits_out,
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// SNES control signal/clock freqs
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input [31:0] snes_cpuclk_freq,
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input [31:0] snes_sysclk_freq,
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input [31:0] snes_read_freq,
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input [31:0] snes_write_freq,
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input [31:0] snes_pard_freq,
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input [31:0] snes_pawr_freq,
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input [31:0] snes_refresh_freq,
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input [31:0] snes_romsel_freq,
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output reg [12:0] mcu_bram_addr,
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input [7:0] mcu_bram_data_in,
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output reg [7:0] mcu_bram_data_out,
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output reg mcu_bram_we
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);
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initial begin
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dspx_pgm_addr_out = 11'b00000000000;
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dspx_dat_addr_out = 10'b0000000000;
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dspx_reset_out = 1'b1;
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ramsel_out = 1'b0;
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end
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reg [2:0] MAPPER_BUF;
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reg [23:0] ADDR_OUT_BUF;
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reg [10:0] DAC_ADDR_OUT_BUF;
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reg [7:0] DAC_VOL_OUT_BUF;
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reg DAC_VOL_LATCH_BUF;
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reg DAC_PLAY_OUT_BUF;
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reg DAC_RESET_OUT_BUF;
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reg [13:0] MSU_ADDR_OUT_BUF;
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reg [13:0] MSU_PTR_OUT_BUF;
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reg [5:0] msu_status_set_out_buf;
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reg [5:0] msu_status_reset_out_buf;
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reg msu_status_reset_we_buf;
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reg MSU_RESET_OUT_BUF;
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reg [7:0] bsx_regs_set_out_buf;
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reg [7:0] bsx_regs_reset_out_buf;
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reg bsx_regs_reset_we_buf;
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reg [55:0] rtc_data_out_buf;
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reg rtc_pgm_we_buf;
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reg srtc_reset_buf;
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reg [31:0] SNES_SYSCLK_FREQ_BUF;
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reg [7:0] MCU_DATA_OUT_BUF;
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reg [7:0] MCU_DATA_IN_BUF;
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reg [1:0] mcu_nextaddr_buf;
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wire mcu_nextaddr;
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reg DAC_STATUSr;
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reg SD_DMA_STATUSr;
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reg [6:0] MSU_STATUSr;
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always @(posedge clk) begin
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DAC_STATUSr <= DAC_STATUS;
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SD_DMA_STATUSr <= SD_DMA_STATUS;
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MSU_STATUSr <= MSU_STATUS;
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end
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reg SD_DMA_PARTIALr;
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assign SD_DMA_PARTIAL = SD_DMA_PARTIALr;
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reg SD_DMA_ENr;
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assign SD_DMA_EN = SD_DMA_ENr;
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reg [1:0] SD_DMA_TGTr;
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assign SD_DMA_TGT = SD_DMA_TGTr;
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reg [10:0] SD_DMA_PARTIAL_STARTr;
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reg [10:0] SD_DMA_PARTIAL_ENDr;
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assign SD_DMA_PARTIAL_START = SD_DMA_PARTIAL_STARTr;
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assign SD_DMA_PARTIAL_END = SD_DMA_PARTIAL_ENDr;
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reg [23:0] SAVERAM_MASK;
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reg [23:0] ROM_MASK;
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assign spi_data_out = MCU_DATA_IN_BUF;
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initial begin
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ADDR_OUT_BUF = 0;
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DAC_ADDR_OUT_BUF = 0;
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MSU_ADDR_OUT_BUF = 0;
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SD_DMA_ENr = 0;
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MAPPER_BUF = 1;
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end
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// command interpretation
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always @(posedge clk) begin
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if (cmd_ready) begin
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case (cmd_data[7:4])
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4'h3: // select mapper
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MAPPER_BUF <= cmd_data[2:0];
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4'h4: begin// SD DMA
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SD_DMA_ENr <= 1;
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SD_DMA_TGTr <= cmd_data[1:0];
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SD_DMA_PARTIALr <= cmd_data[2];
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end
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4'h8: SD_DMA_TGTr <= 2'b00;
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4'h9: SD_DMA_TGTr <= cmd_data[1:0]; // not implemented
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endcase
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end else if (param_ready) begin
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casex (cmd_data[7:0])
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8'h1x:
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case (spi_byte_cnt)
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32'h2:
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ROM_MASK[23:16] <= param_data;
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32'h3:
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ROM_MASK[15:8] <= param_data;
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32'h4:
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ROM_MASK[7:0] <= param_data;
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endcase
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8'h2x:
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case (spi_byte_cnt)
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32'h2:
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SAVERAM_MASK[23:16] <= param_data;
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32'h3:
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SAVERAM_MASK[15:8] <= param_data;
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32'h4:
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SAVERAM_MASK[7:0] <= param_data;
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endcase
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8'h4x:
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SD_DMA_ENr <= 1'b0;
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8'h6x:
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case (spi_byte_cnt)
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32'h2:
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SD_DMA_PARTIAL_STARTr[10:9] <= param_data[1:0];
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32'h3:
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SD_DMA_PARTIAL_STARTr[8:0] <= {param_data, 1'b0};
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32'h4:
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SD_DMA_PARTIAL_ENDr[10:9] <= param_data[1:0];
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32'h5:
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SD_DMA_PARTIAL_ENDr[8:0] <= {param_data, 1'b0};
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endcase
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8'h9x:
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MCU_DATA_OUT_BUF <= param_data;
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8'he0:
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case (spi_byte_cnt)
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32'h2: begin
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msu_status_set_out_buf <= param_data[5:0];
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end
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32'h3: begin
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msu_status_reset_out_buf <= param_data[5:0];
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msu_status_reset_we_buf <= 1'b1;
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end
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32'h4:
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msu_status_reset_we_buf <= 1'b0;
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endcase
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8'he1: // pause DAC
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DAC_PLAY_OUT_BUF <= 1'b0;
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8'he2: // resume DAC
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DAC_PLAY_OUT_BUF <= 1'b1;
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8'he3: // reset DAC (set DAC playback address = 0)
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case (spi_byte_cnt)
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32'h2:
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DAC_RESET_OUT_BUF <= 1'b1;
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32'h3:
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DAC_RESET_OUT_BUF <= 1'b0;
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endcase
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8'he4: // reset MSU read buffer pointer
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case (spi_byte_cnt)
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32'h2: begin
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MSU_PTR_OUT_BUF[13:8] <= param_data[5:0];
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MSU_PTR_OUT_BUF[7:0] <= 8'h0;
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end
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32'h3: begin
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MSU_PTR_OUT_BUF[7:0] <= param_data;
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MSU_RESET_OUT_BUF <= 1'b1;
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end
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32'h4:
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MSU_RESET_OUT_BUF <= 1'b0;
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endcase
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8'he5:
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case (spi_byte_cnt)
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32'h2:
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rtc_data_out_buf[55:48] <= param_data;
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32'h3:
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rtc_data_out_buf[47:40] <= param_data;
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32'h4:
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rtc_data_out_buf[39:32] <= param_data;
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32'h5:
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rtc_data_out_buf[31:24] <= param_data;
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32'h6:
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rtc_data_out_buf[23:16] <= param_data;
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32'h7:
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rtc_data_out_buf[15:8] <= param_data;
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32'h8: begin
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rtc_data_out_buf[7:0] <= param_data;
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rtc_pgm_we_buf <= 1'b1;
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end
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32'h9:
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rtc_pgm_we_buf <= 1'b0;
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endcase
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8'he6:
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case (spi_byte_cnt)
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32'h2: begin
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bsx_regs_set_out_buf <= param_data[7:0];
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end
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32'h3: begin
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bsx_regs_reset_out_buf <= param_data[7:0];
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bsx_regs_reset_we_buf <= 1'b1;
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end
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32'h4:
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bsx_regs_reset_we_buf <= 1'b0;
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endcase
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8'he7:
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case (spi_byte_cnt)
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32'h2: begin
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srtc_reset_buf <= 1'b1;
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end
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32'h3: begin
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srtc_reset_buf <= 1'b0;
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end
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endcase
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8'he8: begin // set BRAM address
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case (spi_byte_cnt)
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32'h2: mcu_bram_addr[12:8] <= param_data[4:0];
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32'h3: mcu_bram_addr[7:0] <= param_data[7:0];
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endcase
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end
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8'he9: begin // write BRAM
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case (spi_byte_cnt)
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32'h2: begin
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mcu_bram_data_out <= param_data;
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mcu_bram_we <= 1'b1;
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end
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32'h3: mcu_bram_we <= 1'b0;
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32'h4: mcu_bram_addr <= mcu_bram_addr + 1;
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endcase
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end
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8'hee:
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ramsel_out <= param_data[0];
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8'hf5:
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if (spi_byte_cnt == 32'h3) mcu_bram_addr <= mcu_bram_addr + 1;
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endcase
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end
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end
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always @(posedge clk) begin
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if(param_ready && cmd_data[7:4] == 4'h0) begin
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case (cmd_data[1:0])
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2'b01: begin
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case (spi_byte_cnt)
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32'h2: begin
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DAC_ADDR_OUT_BUF[10:8] <= param_data[2:0];
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DAC_ADDR_OUT_BUF[7:0] <= 8'b0;
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end
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32'h3:
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DAC_ADDR_OUT_BUF[7:0] <= param_data;
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endcase
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end
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2'b10: begin
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case (spi_byte_cnt)
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32'h2: begin
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MSU_ADDR_OUT_BUF[13:8] <= param_data[5:0];
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MSU_ADDR_OUT_BUF[7:0] <= 8'b0;
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end
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32'h3:
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MSU_ADDR_OUT_BUF[7:0] <= param_data;
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endcase
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end
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default:
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case (spi_byte_cnt)
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32'h2: begin
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ADDR_OUT_BUF[23:16] <= param_data;
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ADDR_OUT_BUF[15:0] <= 16'b0;
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end
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32'h3:
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ADDR_OUT_BUF[15:8] <= param_data;
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32'h4:
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ADDR_OUT_BUF[7:0] <= param_data;
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endcase
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endcase
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end else if (SD_DMA_NEXTADDR | (mcu_nextaddr & (cmd_data[7:5] == 3'h4)
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&& (cmd_data[3])
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&& (spi_byte_cnt >= (32'h1+cmd_data[4])))
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)
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begin
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case (SD_DMA_TGTr)
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2'b00: ADDR_OUT_BUF <= ADDR_OUT_BUF + 1;
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2'b01: DAC_ADDR_OUT_BUF <= DAC_ADDR_OUT_BUF + 1;
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2'b10: MSU_ADDR_OUT_BUF <= MSU_ADDR_OUT_BUF + 1;
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endcase
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end
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end
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// value fetch during last SPI bit
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always @(posedge clk) begin
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if (cmd_data[7:4] == 4'h8 && mcu_nextaddr_buf == 2'b01)
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MCU_DATA_IN_BUF <= mcu_data_in;
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else if (spi_bit_cnt == 3'h7) begin
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if (cmd_data[7:0] == 8'hF0)
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MCU_DATA_IN_BUF <= 8'hA5;
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else if (cmd_data[7:0] == 8'hF1)
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case (spi_byte_cnt[0])
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1'b1: // buffer status (1st byte)
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MCU_DATA_IN_BUF <= {SD_DMA_STATUSr, DAC_STATUSr, MSU_STATUSr[6], 5'b0};
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1'b0: // control status (2nd byte)
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MCU_DATA_IN_BUF <= {2'b0, MSU_STATUSr[5:0]};
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endcase
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else if (cmd_data[7:0] == 8'hF2)
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case (spi_byte_cnt)
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32'h1:
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MCU_DATA_IN_BUF <= msu_addressrq[31:24];
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32'h2:
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MCU_DATA_IN_BUF <= msu_addressrq[23:16];
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32'h3:
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MCU_DATA_IN_BUF <= msu_addressrq[15:8];
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32'h4:
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MCU_DATA_IN_BUF <= msu_addressrq[7:0];
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endcase
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else if (cmd_data[7:0] == 8'hF3)
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case (spi_byte_cnt)
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32'h1:
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MCU_DATA_IN_BUF <= msu_trackrq[15:8];
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32'h2:
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MCU_DATA_IN_BUF <= msu_trackrq[7:0];
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endcase
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else if (cmd_data[7:0] == 8'hF4)
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MCU_DATA_IN_BUF <= msu_volumerq;
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else if (cmd_data[7:0] == 8'hF5)
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MCU_DATA_IN_BUF <= mcu_bram_data_in;
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else if (cmd_data[7:0] == 8'hF7)
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case (spi_byte_cnt)
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32'h1:
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SNES_SYSCLK_FREQ_BUF <= snes_romsel_freq;
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32'h2:
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MCU_DATA_IN_BUF <= SNES_SYSCLK_FREQ_BUF[31:24];
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32'h3:
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MCU_DATA_IN_BUF <= SNES_SYSCLK_FREQ_BUF[23:16];
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32'h4:
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MCU_DATA_IN_BUF <= SNES_SYSCLK_FREQ_BUF[15:8];
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32'h5:
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MCU_DATA_IN_BUF <= SNES_SYSCLK_FREQ_BUF[7:0];
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endcase
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else if (cmd_data[7:0] == 8'hF8)
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case (spi_byte_cnt)
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32'h1:
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SNES_SYSCLK_FREQ_BUF <= snes_cpuclk_freq;
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32'h2:
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MCU_DATA_IN_BUF <= SNES_SYSCLK_FREQ_BUF[31:24];
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32'h3:
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MCU_DATA_IN_BUF <= SNES_SYSCLK_FREQ_BUF[23:16];
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32'h4:
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MCU_DATA_IN_BUF <= SNES_SYSCLK_FREQ_BUF[15:8];
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32'h5:
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MCU_DATA_IN_BUF <= SNES_SYSCLK_FREQ_BUF[7:0];
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endcase
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else if (cmd_data[7:0] == 8'hF9)
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case (spi_byte_cnt)
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32'h1:
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SNES_SYSCLK_FREQ_BUF <= snes_read_freq;
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32'h2:
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MCU_DATA_IN_BUF <= SNES_SYSCLK_FREQ_BUF[31:24];
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32'h3:
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MCU_DATA_IN_BUF <= SNES_SYSCLK_FREQ_BUF[23:16];
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32'h4:
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MCU_DATA_IN_BUF <= SNES_SYSCLK_FREQ_BUF[15:8];
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32'h5:
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MCU_DATA_IN_BUF <= SNES_SYSCLK_FREQ_BUF[7:0];
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endcase
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else if (cmd_data[7:0] == 8'hFA)
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case (spi_byte_cnt)
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32'h1:
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SNES_SYSCLK_FREQ_BUF <= snes_write_freq;
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32'h2:
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MCU_DATA_IN_BUF <= SNES_SYSCLK_FREQ_BUF[31:24];
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32'h3:
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MCU_DATA_IN_BUF <= SNES_SYSCLK_FREQ_BUF[23:16];
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|
32'h4:
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|
MCU_DATA_IN_BUF <= SNES_SYSCLK_FREQ_BUF[15:8];
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32'h5:
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MCU_DATA_IN_BUF <= SNES_SYSCLK_FREQ_BUF[7:0];
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|
endcase
|
|
else if (cmd_data[7:0] == 8'hFB)
|
|
case (spi_byte_cnt)
|
|
32'h1:
|
|
SNES_SYSCLK_FREQ_BUF <= snes_pard_freq;
|
|
32'h2:
|
|
MCU_DATA_IN_BUF <= SNES_SYSCLK_FREQ_BUF[31:24];
|
|
32'h3:
|
|
MCU_DATA_IN_BUF <= SNES_SYSCLK_FREQ_BUF[23:16];
|
|
32'h4:
|
|
MCU_DATA_IN_BUF <= SNES_SYSCLK_FREQ_BUF[15:8];
|
|
32'h5:
|
|
MCU_DATA_IN_BUF <= SNES_SYSCLK_FREQ_BUF[7:0];
|
|
endcase
|
|
else if (cmd_data[7:0] == 8'hFC)
|
|
case (spi_byte_cnt)
|
|
32'h1:
|
|
SNES_SYSCLK_FREQ_BUF <= snes_pawr_freq;
|
|
32'h2:
|
|
MCU_DATA_IN_BUF <= SNES_SYSCLK_FREQ_BUF[31:24];
|
|
32'h3:
|
|
MCU_DATA_IN_BUF <= SNES_SYSCLK_FREQ_BUF[23:16];
|
|
32'h4:
|
|
MCU_DATA_IN_BUF <= SNES_SYSCLK_FREQ_BUF[15:8];
|
|
32'h5:
|
|
MCU_DATA_IN_BUF <= SNES_SYSCLK_FREQ_BUF[7:0];
|
|
endcase
|
|
else if (cmd_data[7:0] == 8'hFD)
|
|
case (spi_byte_cnt)
|
|
32'h1:
|
|
SNES_SYSCLK_FREQ_BUF <= snes_refresh_freq;
|
|
32'h2:
|
|
MCU_DATA_IN_BUF <= SNES_SYSCLK_FREQ_BUF[31:24];
|
|
32'h3:
|
|
MCU_DATA_IN_BUF <= SNES_SYSCLK_FREQ_BUF[23:16];
|
|
32'h4:
|
|
MCU_DATA_IN_BUF <= SNES_SYSCLK_FREQ_BUF[15:8];
|
|
32'h5:
|
|
MCU_DATA_IN_BUF <= SNES_SYSCLK_FREQ_BUF[7:0];
|
|
endcase
|
|
else if (cmd_data[7:0] == 8'hFE)
|
|
case (spi_byte_cnt)
|
|
32'h1:
|
|
SNES_SYSCLK_FREQ_BUF <= snes_sysclk_freq;
|
|
32'h2:
|
|
MCU_DATA_IN_BUF <= SNES_SYSCLK_FREQ_BUF[31:24];
|
|
32'h3:
|
|
MCU_DATA_IN_BUF <= SNES_SYSCLK_FREQ_BUF[23:16];
|
|
32'h4:
|
|
MCU_DATA_IN_BUF <= SNES_SYSCLK_FREQ_BUF[15:8];
|
|
32'h5:
|
|
MCU_DATA_IN_BUF <= SNES_SYSCLK_FREQ_BUF[7:0];
|
|
endcase
|
|
else if (cmd_data[7:0] == 8'hFF)
|
|
MCU_DATA_IN_BUF <= param_data;
|
|
end
|
|
end
|
|
|
|
// nextaddr pulse generation
|
|
always @(posedge clk) begin
|
|
mcu_nextaddr_buf <= {mcu_nextaddr_buf[0], mcu_rq_rdy};
|
|
end
|
|
|
|
parameter ST_RQ = 2'b01;
|
|
parameter ST_IDLE = 2'b10;
|
|
|
|
reg [1:0] rrq_state;
|
|
initial rrq_state = ST_IDLE;
|
|
reg mcu_rrq_r;
|
|
|
|
reg [1:0] wrq_state;
|
|
initial wrq_state = ST_IDLE;
|
|
reg mcu_wrq_r;
|
|
|
|
always @(posedge clk) begin
|
|
case(rrq_state)
|
|
ST_IDLE: begin
|
|
if((param_ready | cmd_ready) && cmd_data[7:4] == 4'h8) begin
|
|
mcu_rrq_r <= 1'b1;
|
|
rrq_state <= ST_RQ;
|
|
end else
|
|
rrq_state <= ST_IDLE;
|
|
end
|
|
ST_RQ: begin
|
|
mcu_rrq_r <= 1'b0;
|
|
rrq_state <= ST_IDLE;
|
|
end
|
|
endcase
|
|
end
|
|
|
|
always @(posedge clk) begin
|
|
case(wrq_state)
|
|
ST_IDLE: begin
|
|
if(param_ready && cmd_data[7:4] == 4'h9) begin
|
|
mcu_wrq_r <= 1'b1;
|
|
wrq_state <= ST_RQ;
|
|
end else
|
|
wrq_state <= ST_IDLE;
|
|
end
|
|
ST_RQ: begin
|
|
mcu_wrq_r <= 1'b0;
|
|
wrq_state <= ST_IDLE;
|
|
end
|
|
endcase
|
|
end
|
|
|
|
// trigger for nextaddr
|
|
assign mcu_nextaddr = mcu_nextaddr_buf == 2'b01;
|
|
|
|
assign mcu_rrq = mcu_rrq_r;
|
|
assign mcu_wrq = mcu_wrq_r;
|
|
assign mcu_write = SD_DMA_STATUS
|
|
?(SD_DMA_TGTr == 2'b00
|
|
?SD_DMA_SRAM_WE
|
|
:1'b1
|
|
)
|
|
: 1'b1;
|
|
|
|
assign addr_out = ADDR_OUT_BUF;
|
|
assign dac_addr_out = DAC_ADDR_OUT_BUF;
|
|
assign msu_addr_out = MSU_ADDR_OUT_BUF;
|
|
assign dac_play_out = DAC_PLAY_OUT_BUF;
|
|
assign dac_reset_out = DAC_RESET_OUT_BUF;
|
|
assign msu_status_reset_we = msu_status_reset_we_buf;
|
|
assign msu_status_reset_out = msu_status_reset_out_buf;
|
|
assign msu_status_set_out = msu_status_set_out_buf;
|
|
assign msu_reset_out = MSU_RESET_OUT_BUF;
|
|
assign msu_ptr_out = MSU_PTR_OUT_BUF;
|
|
|
|
assign bsx_regs_reset_we = bsx_regs_reset_we_buf;
|
|
assign bsx_regs_reset_out = bsx_regs_reset_out_buf;
|
|
assign bsx_regs_set_out = bsx_regs_set_out_buf;
|
|
|
|
assign rtc_data_out = rtc_data_out_buf;
|
|
assign rtc_pgm_we = rtc_pgm_we_buf;
|
|
|
|
assign srtc_reset = srtc_reset_buf;
|
|
|
|
assign mcu_data_out = SD_DMA_STATUS ? SD_DMA_SRAM_DATA : MCU_DATA_OUT_BUF;
|
|
assign mcu_mapper = MAPPER_BUF;
|
|
assign rom_mask_out = ROM_MASK;
|
|
assign saveram_mask_out = SAVERAM_MASK;
|
|
|
|
endmodule
|