Logo
Explore More informations Help
Sign In
godzil/sd2snes
1
0
Fork 0
You've already forked sd2snes
Code Issues Pull Requests Actions Packages Projects Releases Wiki Activity
sd2snes/verilog/sd2sneslite
History
Maximilian Rehkopf e33b2b2bc7 FPGA: simple SNES address input filtering
2012-07-09 01:37:57 +02:00
..
address.v
FPGA: adjust menu memory mapping to make more room for file database
2012-06-10 20:07:45 +02:00
avr_cmd.v
feature reduced FPGA config for uC flash embedding
2010-12-31 02:49:04 +01:00
data.v
FPGA: merge recent changes into sd2sneslite
2011-10-08 17:05:22 +02:00
dcm.v
FPGA: merge recent changes into sd2sneslite
2011-10-08 17:05:22 +02:00
main.ucf
FPGA: simple SNES address input filtering
2012-07-09 01:37:57 +02:00
main.v
FPGA: simple SNES address input filtering
2012-07-09 01:37:57 +02:00
sd2sneslite.xise
FPGA: adjust menu memory mapping to make more room for file database
2012-06-10 20:07:45 +02:00
spi.v
FPGA: clean up (port size mismatches, unused regs/wires, ...)
2011-10-09 14:13:35 +02:00
Powered by Gitea Page: 58ms Template: 3ms
English
Bahasa Indonesia Deutsch English Español Français Gaeilge Italiano Latviešu Magyar nyelv Nederlands Polski Português de Portugal Português do Brasil Suomi Svenska Türkçe Čeština Ελληνικά Български Русский Українська فارسی മലയാളം 日本語 简体中文 繁體中文(台灣) 繁體中文(香港) 한국어
Licenses API