65 lines
1.8 KiB
Verilog
65 lines
1.8 KiB
Verilog
`timescale 1 ns / 1 ns
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//////////////////////////////////////////////////////////////////////////////////
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// Company: Rehkopf
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// Engineer: Rehkopf
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//
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// Create Date: 01:13:46 05/09/2009
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// Design Name:
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// Module Name: address
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// Project Name:
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// Target Devices:
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// Tool versions:
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// Description: Address logic w/ SaveRAM masking
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//
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// Dependencies:
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//
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// Revision:
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// Additional Comments:
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//
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//////////////////////////////////////////////////////////////////////////////////
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module address(
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input CLK,
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input [2:0] MAPPER, // MCU detected mapper
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input [23:0] SNES_ADDR, // requested address from SNES
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output [23:0] ROM_ADDR, // Address to request from SRAM0
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output ROM_SEL, // enable SRAM0 (active low)
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output IS_SAVERAM, // address/CS mapped as SRAM?
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output IS_ROM, // address mapped as ROM?
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output IS_WRITABLE, // address somehow mapped as writable area?
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input [23:0] SAVERAM_MASK,
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input [23:0] ROM_MASK,
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input use_msu1,
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output msu_enable,
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output cx4_enable
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);
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wire [23:0] SRAM_SNES_ADDR;
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/* Cx4 mapper:
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- LoROM (extended to 00-7d, 80-ff)
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- MMIO @ 6000-7fff
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*/
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assign IS_ROM = (SNES_ADDR[15]);
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assign SRAM_SNES_ADDR = ({2'b00, SNES_ADDR[22:16], SNES_ADDR[14:0]}
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& ROM_MASK);
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assign ROM_ADDR = SRAM_SNES_ADDR;
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assign ROM_SEL = 1'b0;
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wire msu_enable_w = use_msu1 & (!SNES_ADDR[22] && ((SNES_ADDR[15:0] & 16'hfff8) == 16'h2000));
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reg [5:0] msu_enable_r;
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initial msu_enable_r = 6'b000000;
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always @(posedge CLK) msu_enable_r <= {msu_enable_r[4:0], msu_enable_w};
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assign msu_enable = &msu_enable_r[5:2];
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wire cx4_enable_w = (!SNES_ADDR[22] && (SNES_ADDR[15:13] == 3'b011));
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reg [5:0] cx4_enable_r;
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initial cx4_enable_r = 6'b000000;
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always @(posedge CLK) cx4_enable_r <= {cx4_enable_r[4:0], cx4_enable_w};
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assign cx4_enable = &cx4_enable_r[5:2];
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endmodule
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