74 lines
2.2 KiB
Verilog
74 lines
2.2 KiB
Verilog
`timescale 1ns / 1ps
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//////////////////////////////////////////////////////////////////////////////////
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// Company:
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// Engineer:
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//
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// Create Date: 23:03:06 05/13/2009
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// Design Name:
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// Module Name: data
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// Project Name:
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// Target Devices:
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// Tool versions:
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// Description:
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//
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// Dependencies:
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//
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// Revision:
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// Revision 0.01 - File Created
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// Additional Comments:
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//
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//////////////////////////////////////////////////////////////////////////////////
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module data(
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input CLK,
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input SNES_READ,
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input SNES_WRITE,
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input AVR_READ,
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input AVR_WRITE,
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inout [7:0] SNES_DATA,
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inout [15:0] SRAM_DATA,
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input [7:0] AVR_IN_DATA,
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output [7:0] AVR_OUT_DATA,
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input MODE,
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input SNES_DATA_TO_MEM,
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input AVR_DATA_TO_MEM,
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input SRAM_DATA_TO_SNES_MEM,
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input SRAM_DATA_TO_AVR_MEM,
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input AVR_ENA,
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input SRAM_ADDR0
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);
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reg [7:0] SNES_IN_MEM;
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reg [7:0] SNES_OUT_MEM;
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reg [7:0] AVR_IN_MEM;
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reg [7:0] AVR_OUT_MEM;
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wire [7:0] FROM_SRAM_BYTE;
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assign SNES_DATA = SNES_READ ? 8'bZ : SNES_OUT_MEM;
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assign FROM_SRAM_BYTE = (SRAM_ADDR0 ? SRAM_DATA[7:0] : SRAM_DATA[15:8]);
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assign AVR_OUT_DATA = !AVR_ENA ? (FROM_SRAM_BYTE)
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: (AVR_OUT_MEM);
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assign SRAM_DATA[7:0] = SRAM_ADDR0 ? (!AVR_ENA ? (!AVR_WRITE ? AVR_IN_DATA : 8'bZ)
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: (MODE ? (!AVR_WRITE ? AVR_IN_MEM : 8'bZ)
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: (!SNES_WRITE ? SNES_IN_MEM : 8'bZ)))
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: 8'bZ;
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assign SRAM_DATA[15:8] = SRAM_ADDR0 ? 8'bZ : (!AVR_ENA ? (!AVR_WRITE ? AVR_IN_DATA : 8'bZ)
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: (MODE ? (!AVR_WRITE ? AVR_IN_MEM : 8'bZ)
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: (!SNES_WRITE ? SNES_IN_MEM : 8'bZ)));
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always @(posedge CLK) begin
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if(SNES_DATA_TO_MEM)
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SNES_IN_MEM <= SNES_DATA;
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if(AVR_DATA_TO_MEM)
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AVR_IN_MEM <= AVR_IN_DATA;
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if(SRAM_DATA_TO_SNES_MEM)
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SNES_OUT_MEM <= FROM_SRAM_BYTE;
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if(SRAM_DATA_TO_AVR_MEM)
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AVR_OUT_MEM <= FROM_SRAM_BYTE;
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end
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endmodule
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