248 lines
7.3 KiB
Verilog
248 lines
7.3 KiB
Verilog
`timescale 1ns / 1ps
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//////////////////////////////////////////////////////////////////////////////////
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// Company:
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// Engineer:
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//
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// Create Date: 02:43:54 02/06/2011
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// Design Name:
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// Module Name: bsx
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// Project Name:
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// Target Devices:
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// Tool versions:
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// Description:
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//
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// Dependencies:
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//
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// Revision:
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// Revision 0.01 - File Created
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// Additional Comments:
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//
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//////////////////////////////////////////////////////////////////////////////////
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module bsx(
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input clkin,
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input reg_oe,
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input reg_we,
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input [23:0] snes_addr,
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input [7:0] reg_data_in,
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output [7:0] reg_data_out,
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input [7:0] reg_reset_bits,
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input [7:0] reg_set_bits,
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output [14:0] regs_out,
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input pgm_we,
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input use_bsx,
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output data_ovr,
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output flash_writable,
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input [55:0] rtc_data
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);
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wire [3:0] reg_addr = snes_addr[19:16]; // 00-0f:5000-5fff
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wire [4:0] base_addr = snes_addr[4:0]; // 88-9f -> 08-1f
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wire [15:0] flash_addr = snes_addr[15:0];
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reg flash_ovr_r;
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reg flash_we_r;
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reg [7:0] flash_cmd0;
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reg [15:0] flash_cmd5555;
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wire cart_enable = (use_bsx) && ((snes_addr[23:12] & 12'hf0f) == 12'h005);
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wire base_enable = (use_bsx) && (!snes_addr[22] && (snes_addr[15:0] >= 16'h2188)
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&& (snes_addr[15:0] <= 16'h219f));
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wire flash_enable = (snes_addr[23:16] == 8'hc0);
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wire is_flash_special_address = (flash_addr == 16'h0002
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|| flash_addr == 16'h5555
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|| flash_addr == 16'h2aaa
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|| flash_addr == 16'h0000
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|| (flash_addr >= 16'hff00
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&& flash_addr <= 16'hff13));
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wire flash_ovr = (use_bsx)
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&& (flash_enable & flash_ovr_r)
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&& is_flash_special_address;
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assign flash_writable = (use_bsx)
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&& flash_enable
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&& flash_we_r
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&& !is_flash_special_address;
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assign data_ovr = cart_enable | base_enable | flash_ovr;
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reg [3:0] reg_oe_sreg;
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always @(posedge clkin) reg_oe_sreg <= {reg_oe_sreg[2:0], reg_oe};
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wire reg_oe_falling = (reg_oe_sreg[3:0] == 4'b1000);
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reg [1:0] reg_we_sreg;
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always @(posedge clkin) reg_we_sreg <= {reg_we_sreg[0], reg_we};
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wire reg_we_rising = (reg_we_sreg[1:0] == 2'b01);
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reg [1:0] pgm_we_sreg;
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always @(posedge clkin) pgm_we_sreg <= {pgm_we_sreg[0], pgm_we};
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wire pgm_we_rising = (pgm_we_sreg[1:0] == 2'b01);
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reg [14:0] regs_tmpr;
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reg [14:0] regs_outr;
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reg [7:0] reg_data_outr;
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reg [7:0] base_regs[31:8];
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reg [4:0] bsx_counter;
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reg [7:0] flash_vendor_data[7:0];
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assign regs_out = regs_outr;
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assign reg_data_out = reg_data_outr;
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wire [7:0] rtc_sec = rtc_data[3:0] + (rtc_data[7:4] << 3) + (rtc_data[7:4] << 1);
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wire [7:0] rtc_min = rtc_data[11:8] + (rtc_data[15:12] << 3) + (rtc_data[15:12] << 1);
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wire [7:0] rtc_hour = rtc_data[19:16] + (rtc_data[23:20] << 3) + (rtc_data[23:20] << 1);
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wire [7:0] rtc_day = rtc_data[27:24] + (rtc_data[31:28] << 3) + (rtc_data[31:28] << 1);
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/* The following signals are currently unused.
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They are kept in case more Satellaview date registers are discovered. */
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wire [7:0] rtc_month = rtc_data[35:32] + (rtc_data[39:36] << 3) + (rtc_data[39:36] << 1);
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wire [7:0] rtc_year1 = rtc_data[43:40] + (rtc_data[47:44] << 3) + (rtc_data[47:44] << 1);
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wire [7:0] rtc_year100 = rtc_data[51:48] + (rtc_data[55:52] << 3) + (rtc_data[55:52] << 1);
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initial begin
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regs_tmpr <= 15'b000000100000000;
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regs_outr <= 15'b000000100000000;
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bsx_counter <= 0;
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base_regs[8] <= 0;
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base_regs[9] <= 0;
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base_regs[10] <= 0;
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base_regs[11] <= 8'h9f;
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base_regs[12] <= 8'h10;
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base_regs[13] <= 8'h9f;
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base_regs[14] <= 0;
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base_regs[15] <= 0;
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base_regs[16] <= 0;
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base_regs[17] <= 8'h9f;
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base_regs[18] <= 8'h01;
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base_regs[19] <= 8'h9f;
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base_regs[20] <= 0;
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base_regs[21] <= 0;
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base_regs[22] <= 8'h02;
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base_regs[23] <= 8'hff;
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base_regs[24] <= 8'h80;
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base_regs[25] <= 8'h01;
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base_regs[26] <= 0;
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base_regs[27] <= 0;
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base_regs[28] <= 0;
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base_regs[29] <= 0;
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base_regs[30] <= 0;
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base_regs[31] <= 0;
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flash_vendor_data[3'h0] <= 8'h4d;
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flash_vendor_data[3'h1] <= 8'h00;
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flash_vendor_data[3'h2] <= 8'h50;
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flash_vendor_data[3'h3] <= 8'h00;
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flash_vendor_data[3'h4] <= 8'h00;
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flash_vendor_data[3'h5] <= 8'h00;
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flash_vendor_data[3'h6] <= 8'h2a;
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flash_vendor_data[3'h7] <= 8'h00;
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flash_ovr_r <= 1'b0;
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flash_we_r <= 1'b0;
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end
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always @(posedge clkin) begin
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if(reg_oe_falling) begin
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if(cart_enable)
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reg_data_outr <= {regs_outr[reg_addr], 7'b0};
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else if(base_enable) begin
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case(base_addr)
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5'b10010: begin
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if(bsx_counter < 18) begin
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bsx_counter <= bsx_counter + 1;
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case (bsx_counter)
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5:
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reg_data_outr <= 8'h1;
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6:
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reg_data_outr <= 8'h1;
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10:
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reg_data_outr <= rtc_sec;
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11:
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reg_data_outr <= rtc_min;
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12:
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reg_data_outr <= rtc_hour;
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default:
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reg_data_outr <= 8'h0;
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endcase
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end else begin
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reg_data_outr <= 8'h0;
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bsx_counter <= 0;
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end
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end
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5'b10011:
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reg_data_outr <= base_regs[base_addr] & 8'h3f;
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default:
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reg_data_outr <= base_regs[base_addr];
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endcase
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end else if (flash_enable) begin
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casex (flash_addr)
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16'h0002:
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reg_data_outr <= 8'h80;
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16'h5555:
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reg_data_outr <= 8'h80;
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16'b1111111100000xxx:
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reg_data_outr <= flash_vendor_data[flash_addr&16'h0007];
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default:
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reg_data_outr <= 8'h00;
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endcase
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end
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end else if(pgm_we_rising) begin
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regs_tmpr[8:1] <= (regs_tmpr[8:1] | reg_set_bits[7:0]) & ~reg_reset_bits[7:0];
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regs_outr[8:1] <= (regs_outr[8:1] | reg_set_bits[7:0]) & ~reg_reset_bits[7:0];
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end else if(reg_we_rising && cart_enable) begin
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if(reg_addr == 4'he && reg_data_in[7])
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regs_outr <= regs_tmpr | 15'b100000000000000;
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else
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regs_tmpr[reg_addr] <= reg_data_in[7];
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end else if(reg_we_rising && base_enable) begin
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case(base_addr)
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5'h0f: begin
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base_regs[base_addr-1] <= base_regs[base_addr]-(base_regs[base_addr-1] >> 1);
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base_regs[base_addr] <= base_regs[base_addr] >> 1;
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end
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5'h11: begin
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bsx_counter <= 0;
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base_regs[base_addr] <= reg_data_in;
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end
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5'h12: begin
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base_regs[8'h10] <= 8'h80;
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end
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default:
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base_regs[base_addr] <= reg_data_in;
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endcase
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end else if(reg_we_rising && flash_enable) begin
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case(flash_addr)
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16'h0000: begin
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flash_cmd0 <= reg_data_in;
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if(flash_cmd0 == 8'h38 && reg_data_in == 8'hd0)
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flash_ovr_r <= 1;
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end
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16'h5555: begin
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flash_cmd5555 <= {flash_cmd5555[7:0], reg_data_in};
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if(flash_cmd5555 == 16'haa55) begin
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case (reg_data_in)
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8'hf0: begin
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flash_ovr_r <= 0;
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flash_we_r <= 0;
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end
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8'ha0: begin
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flash_ovr_r <= 1;
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flash_we_r <= 1;
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end
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8'h70: begin
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flash_we_r <= 0;
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end
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endcase
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end
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end
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16'h2aaa: begin
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flash_cmd5555 <= {flash_cmd5555[7:0], reg_data_in};
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end
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endcase
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end
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end
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endmodule
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