161 lines
3.6 KiB
Verilog
161 lines
3.6 KiB
Verilog
`timescale 1ns / 1ps
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//////////////////////////////////////////////////////////////////////////////////
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// Company:
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// Engineer:
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//
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// Create Date: 19:26:11 07/23/2010
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// Design Name:
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// Module Name: dac_test
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// Project Name:
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// Target Devices:
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// Tool versions:
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// Description:
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//
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// Dependencies:
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//
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// Revision:
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// Revision 0.01 - File Created
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// Additional Comments:
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//
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//////////////////////////////////////////////////////////////////////////////////
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module dac(
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input clkin,
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input sysclk,
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input we,
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input[10:0] pgm_address,
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input[7:0] pgm_data,
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input[7:0] volume,
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input vol_latch,
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input play,
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input reset,
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output sdout,
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output lrck,
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output mclk,
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output DAC_STATUS
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);
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reg[8:0] dac_address_r;
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wire[8:0] dac_address = dac_address_r;
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wire[31:0] dac_data;
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assign DAC_STATUS = dac_address_r[8];
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reg[7:0] vol_reg;
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reg[7:0] vol_target_reg;
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reg[1:0] vol_latch_reg;
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reg vol_valid;
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reg[2:0] sysclk_sreg;
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wire sysclk_rising = (sysclk_sreg[2:1] == 2'b01);
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reg [25:0] interpol_count;
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always @(posedge clkin) begin
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sysclk_sreg <= {sysclk_sreg[1:0], sysclk};
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end
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dac_buf snes_dac_buf (
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.clka(clkin),
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.wea(~we), // Bus [0 : 0]
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.addra(pgm_address), // Bus [10 : 0]
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.dina(pgm_data), // Bus [7 : 0]
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.clkb(clkin),
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.addrb(dac_address), // Bus [8 : 0]
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.doutb(dac_data)); // Bus [31 : 0]
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reg [8:0] cnt;
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reg [15:0] smpcnt;
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reg [1:0] samples;
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reg [15:0] smpshift;
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assign mclk = cnt[2]; // mclk = clk/8
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assign lrck = cnt[8]; // lrck = mclk/128
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wire sclk = cnt[3]; // sclk = lrck*32
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reg [2:0] lrck_sreg;
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reg [2:0] sclk_sreg;
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wire lrck_rising = ({lrck_sreg[2:1]} == 2'b01);
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wire lrck_falling = ({lrck_sreg[2:1]} == 2'b10);
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wire sclk_rising = ({sclk_sreg[2:1]} == 2'b01);
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wire vol_latch_rising = (vol_latch_reg[1:0] == 2'b01);
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reg sdout_reg;
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assign sdout = sdout_reg;
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reg [1:0] reset_sreg;
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wire reset_rising = (reset_sreg[1:0] == 2'b01);
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reg play_r;
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initial begin
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cnt = 9'h100;
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smpcnt = 16'b0;
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lrck_sreg = 2'b11;
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sclk_sreg = 1'b0;
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dac_address_r = 10'b0;
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vol_valid = 1'b0;
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vol_latch_reg = 1'b0;
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vol_reg = 8'h0;
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vol_target_reg = 8'hff;
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samples <= 2'b00;
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end
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always @(posedge clkin) begin
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if(reset_rising) begin
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dac_address_r <= 0;
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interpol_count <= 0;
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end else if(sysclk_rising) begin
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if(interpol_count > 59378938) begin
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interpol_count <= interpol_count + 122500 - 59501439;
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dac_address_r <= dac_address_r + play_r;
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end else begin
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interpol_count <= interpol_count + 122500;
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end
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end
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end
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always @(posedge clkin) begin
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cnt <= cnt + 1;
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lrck_sreg <= {lrck_sreg[1:0], lrck};
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sclk_sreg <= {sclk_sreg[1:0], sclk};
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vol_latch_reg <= {vol_latch_reg[0], vol_latch};
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play_r <= play;
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reset_sreg <= {reset_sreg[0], reset};
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end
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always @(posedge clkin) begin
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if (vol_latch_rising) begin
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vol_valid <= 1'b1;
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end
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else if(vol_valid) begin
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vol_target_reg <= volume;
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vol_valid <= 1'b0;
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end
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end
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// ramp volume only every 4 samples
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always @(posedge clkin) begin
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if (lrck_rising && &samples[1:0]) begin
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if(vol_reg > vol_target_reg)
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vol_reg <= vol_reg - 1;
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else if(vol_reg < vol_target_reg)
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vol_reg <= vol_reg + 1;
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end
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end
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always @(posedge clkin) begin
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if (lrck_rising) begin // right channel
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smpshift <= (({16'h0, dac_data[31:16]^16'h8000} * vol_reg) >> 8) ^ 16'h8000;
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samples <= samples + 1;
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end else if (lrck_falling) begin // left channel
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smpshift <= (({16'h0, dac_data[15:0]^16'h8000} * vol_reg) >> 8) ^ 16'h8000;
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end else begin
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if (sclk_rising) begin
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smpcnt <= smpcnt + 1;
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sdout_reg <= smpshift[15];
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smpshift <= {smpshift[14:0], 1'b0};
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end
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end
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end
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endmodule
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