133 lines
2.7 KiB
Verilog
133 lines
2.7 KiB
Verilog
`timescale 1ns / 1ps
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////////////////////////////////////////////////////////////////////////////////
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// Company:
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// Engineer:
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//
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// Create Date: 04:03:25 12/21/2009
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// Design Name: main
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// Module Name: /home/ikari/prj/sd2snes/verilog/sd2snes/tf_main_3.v
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// Project Name: sd2snes
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// Target Device:
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// Tool versions:
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// Description:
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//
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// Verilog Test Fixture created by ISE for module: main
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//
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// Dependencies:
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//
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// Revision:
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// Revision 0.01 - File Created
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// Additional Comments:
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//
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////////////////////////////////////////////////////////////////////////////////
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module tf_main_3;
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// Inputs
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reg CLKIN;
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reg [23:0] SNES_ADDR;
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reg SNES_READ;
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reg SNES_WRITE;
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reg SNES_CS;
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reg SNES_CPU_CLK;
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reg SNES_REFRESH;
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reg SPI_MOSI;
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reg SPI_SS;
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reg AVR_ENA;
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// Outputs
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wire SNES_DATABUS_OE;
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wire SNES_DATABUS_DIR;
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wire IRQ_DIR;
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wire [19:0] SRAM_ADDR;
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wire [3:0] SRAM_CE2;
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wire SRAM_OE;
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wire SRAM_WE;
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wire SRAM_BHE;
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wire SRAM_BLE;
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// Bidirs
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wire [7:0] SNES_DATA;
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wire SNES_IRQ;
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wire [15:0] SRAM_DATA;
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wire SPI_MISO;
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wire SPI_SCK;
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wire SPI_DMA_CTRL;
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reg SPI_DMA_CTRLdir;
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reg SPI_DMA_CTRLr;
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reg SPI_MISOdir;
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reg SPI_MISOr;
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// Instantiate the Unit Under Test (UUT)
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main uut (
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.CLKIN(CLKIN),
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.SNES_ADDR(SNES_ADDR),
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.SNES_READ(SNES_READ),
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.SNES_WRITE(SNES_WRITE),
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.SNES_CS(SNES_CS),
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.SNES_DATA(SNES_DATA),
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.SNES_CPU_CLK(SNES_CPU_CLK),
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.SNES_REFRESH(SNES_REFRESH),
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.SNES_IRQ(SNES_IRQ),
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.SNES_DATABUS_OE(SNES_DATABUS_OE),
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.SNES_DATABUS_DIR(SNES_DATABUS_DIR),
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.IRQ_DIR(IRQ_DIR),
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.SRAM_DATA(SRAM_DATA),
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.SRAM_ADDR(SRAM_ADDR),
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.SRAM_CE2(SRAM_CE2),
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.SRAM_OE(SRAM_OE),
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.SRAM_WE(SRAM_WE),
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.SRAM_BHE(SRAM_BHE),
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.SRAM_BLE(SRAM_BLE),
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.SPI_MOSI(SPI_MOSI),
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.SPI_MISO(SPI_MISO),
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.SPI_SS(SPI_SS),
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.SPI_SCK(SPI_SCK),
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.AVR_ENA(AVR_ENA),
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.SPI_DMA_CTRL(SPI_DMA_CTRL)
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);
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initial begin
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// Initialize Inputs
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CLKIN = 0;
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SNES_ADDR = 0;
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SNES_READ = 0;
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SNES_WRITE = 0;
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SNES_CS = 0;
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SNES_CPU_CLK = 0;
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SNES_REFRESH = 0;
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SPI_MOSI = 0;
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SPI_SS = 0;
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AVR_ENA = 0;
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SPI_DMA_CTRLr = 1;
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SPI_DMA_CTRLdir = 0;
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SPI_MISOr = 0;
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SPI_MISOdir = 0;
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// Wait 100 ns for global reset to finish
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#100;
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#600; // dcm?
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// Add stimulus here
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SPI_DMA_CTRLr = 1;
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SPI_DMA_CTRLdir = 1;
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#100 SPI_DMA_CTRLr = 0;
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#100 SPI_DMA_CTRLr = 1'bZ;
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SPI_DMA_CTRLdir = 0;
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SPI_MISOdir = 1;
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#260 SPI_MISOr = 1;
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#80 SPI_MISOr = 0;
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#80 SPI_MISOr = 0;
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#80 SPI_MISOr = 1;
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#80 SPI_MISOr = 0;
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#80 SPI_MISOr = 1;
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#80 SPI_MISOr = 0;
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#80 SPI_MISOr = 1;
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end
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assign SPI_DMA_CTRL = SPI_DMA_CTRLdir ? SPI_DMA_CTRLr : 1'bZ;
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assign SPI_MISO = SPI_MISOdir ? SPI_MISOr : 1'bZ;
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always #35 CLKIN = ~CLKIN;
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endmodule
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