diff --git a/README.md b/README.md
index 5420b8b..8ecdd5a 100644
--- a/README.md
+++ b/README.md
@@ -2,25 +2,13 @@ socz80-altera
 ===============
 
 This is a port of Will Sowerbutts' socz80 retro microcomputer (http://sowerbutts.com/socz80) for Altera FPGA boards, currently supporting DE0, DE0-nano, DE2 and DE2-70 from Terasic.
-Original version come from https://github.com/slp/socz80-altera
 
 Building
 ========
 
-Make sure you have the Altera Quartus II software (I've used version 13.0 from Web Edition) binaries on your $PATH. Then run "make" for building the SOF file, and "make load" for loading it on your board.
+Make sure you have the Altera Quartus II software (I've used version 13.1 from Web Edition) binaries on your $PATH. Then run "make" for building the SOF file, and "make load" for loading it on your board.
 
 Software
 ========
 
 This project only contains the VHDL files for building the core and its depencies. You can find some software for this microcomputer and instructions about what you can do with it inside the tarball of the original project (http://sowerbutts.com/socz80/socz80-2014-04-30.tar.gz).
-
-TODO
-====
-
-* Make it work on the DE0. Z80 + SRAM, ROM and UART are working, but SDRAM need more tweak. I also need to publish the changes.
-* Add support for the integrated SD Card
-* Video Out and PS2 for a keyboard could be also a nice entry.
-* Currently the 4 hex digit are used to show the CPU PC, but I will also create an IO device to show on them the value you want
-* Also add all the SW switch and Button 1 and 2 to GPI and the LED to GPO minus the one used to display the CPU status. and Button 0 is used for Reset.
-* The original design was developed for a Papilo Pro board, which featres a reasonable amount of non volatile memory onboard. The DE0 have a flash device, it may be nice to allow to map it to memory. Not sure if allow write to it is a good idea.
-* Also the two GPIO header could be added to the IO mapping.
diff --git a/board/de0_nano/de0_nano.tcl b/board/de0_nano/de0_nano.tcl
index 46e512d..6e9e367 100644
--- a/board/de0_nano/de0_nano.tcl
+++ b/board/de0_nano/de0_nano.tcl
@@ -201,4 +201,4 @@ if {$make_assignments} {
 	if {$need_to_close_project} {
 		project_close
 	}
-}
\ No newline at end of file
+}
diff --git a/vhdl/board/de0/DE0_SEG7.vhd b/vhdl/board/de0/DE0_SEG7.vhd
index 354a47d..767540b 100644
--- a/vhdl/board/de0/DE0_SEG7.vhd
+++ b/vhdl/board/de0/DE0_SEG7.vhd
@@ -41,4 +41,4 @@ begin
                "0100001" when in_value = X"D" else
                "0000110" when in_value = X"E" else
                "0001110";
-end architecture;
\ No newline at end of file
+end architecture;
diff --git a/vhdl/board/de0_nano/SDRAM_Controller.vhd b/vhdl/board/de0_nano/SDRAM_Controller.vhd
index 8669446..bbb5db7 100644
--- a/vhdl/board/de0_nano/SDRAM_Controller.vhd
+++ b/vhdl/board/de0_nano/SDRAM_Controller.vhd
@@ -469,4 +469,4 @@ main_proc: process(clk)
          end if;
       end if;      
    end process;
-end Behavioral;
\ No newline at end of file
+end Behavioral;
diff --git a/vhdl/board/de0_nano/top_level_de0_nano.vhd b/vhdl/board/de0_nano/top_level_de0_nano.vhd
index 7c71da8..beeb818 100644
--- a/vhdl/board/de0_nano/top_level_de0_nano.vhd
+++ b/vhdl/board/de0_nano/top_level_de0_nano.vhd
@@ -462,4 +462,4 @@ begin
                locked => open
            );
 
-end Behavioral;
\ No newline at end of file
+end Behavioral;