Disable back-to-back on writes.

This commit is contained in:
Sergio L. Pascual 2014-09-06 02:57:42 +02:00 committed by Sergio Lopez
parent e35013a1af
commit 61843094fd
3 changed files with 11 additions and 27 deletions

View File

@ -2,20 +2,22 @@ DESIGN_NAME = de0_nano
QUARTUS_OPTIONS =
all: sta
all: asm
project: $(TCL_FILE)
quartus_sh $(QUARTUS_OPTIONS) -t $(DESIGN_NAME).tcl
quartus_sh $(QUARTUS_OPTIONS) -t $(DESIGN_NAME).tcl
map: project
quartus_map $(QUARTUS_OPTIONS) $(DESIGN_NAME)
quartus_map $(QUARTUS_OPTIONS) $(DESIGN_NAME)
fit: map
quartus_fit $(QUARTUS_OPTIONS) $(DESIGN_NAME)
quartus_fit $(QUARTUS_OPTIONS) $(DESIGN_NAME)
asm: fit
quartus_asm $(QUARTUS_OPTIONS) $(DESIGN_NAME)
quartus_asm $(QUARTUS_OPTIONS) $(DESIGN_NAME)
sta: asm
quartus_sta $(QUARTUS_OPTIONS) $(DESIGN_NAME)
quartus_sta $(QUARTUS_OPTIONS) $(DESIGN_NAME)
load: asm
quartus_pgm --mode=jtag -o p\;$(DESIGN_NAME).sof

View File

@ -442,24 +442,8 @@ main_proc: process(clk)
iob_data <= iob_data_next;
when s_write_3 => -- must wait tRDL, hence the extra idle state
-- back to back transaction?
if forcing_refresh = '0' and got_transaction = '1' and can_back_to_back = '1' then
if save_wr = '1' then
-- back-to-back write?
state <= s_write_1;
ready_for_new <= '1';
got_transaction <= '0';
else
-- write-to-read switch?
state <= s_read_1;
iob_dq_hiz <= '1';
ready_for_new <= '1'; -- we will be ready for a new transaction next cycle!
got_transaction <= '0';
end if;
else
iob_dq_hiz <= '1';
state <= s_precharge;
end if;
iob_dq_hiz <= '1';
state <= s_precharge;
-------------------------------------------------------------------
-- Closing the row off (this closes all banks)

View File

@ -15,8 +15,6 @@
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
library UNISIM;
use UNISIM.VComponents.all;
entity top_level is
Port ( sysclk_32m : in std_logic;
@ -169,7 +167,7 @@ begin
console_select_sync <= console_select_clk1;
-- reset the system when requested
if (power_on_reset(0) = '1' or reset_button_sync = '1' or reset_request_uart = '1') then
if (power_on_reset(0) = '1') then
system_reset <= '1';
else
system_reset <= '0';