Disable back-to-back on writes.
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14
Makefile
14
Makefile
@ -2,20 +2,22 @@ DESIGN_NAME = de0_nano
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QUARTUS_OPTIONS =
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all: sta
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all: asm
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project: $(TCL_FILE)
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quartus_sh $(QUARTUS_OPTIONS) -t $(DESIGN_NAME).tcl
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quartus_sh $(QUARTUS_OPTIONS) -t $(DESIGN_NAME).tcl
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map: project
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quartus_map $(QUARTUS_OPTIONS) $(DESIGN_NAME)
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quartus_map $(QUARTUS_OPTIONS) $(DESIGN_NAME)
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fit: map
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quartus_fit $(QUARTUS_OPTIONS) $(DESIGN_NAME)
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quartus_fit $(QUARTUS_OPTIONS) $(DESIGN_NAME)
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asm: fit
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quartus_asm $(QUARTUS_OPTIONS) $(DESIGN_NAME)
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quartus_asm $(QUARTUS_OPTIONS) $(DESIGN_NAME)
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sta: asm
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quartus_sta $(QUARTUS_OPTIONS) $(DESIGN_NAME)
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quartus_sta $(QUARTUS_OPTIONS) $(DESIGN_NAME)
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load: asm
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quartus_pgm --mode=jtag -o p\;$(DESIGN_NAME).sof
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@ -442,24 +442,8 @@ main_proc: process(clk)
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iob_data <= iob_data_next;
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when s_write_3 => -- must wait tRDL, hence the extra idle state
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-- back to back transaction?
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if forcing_refresh = '0' and got_transaction = '1' and can_back_to_back = '1' then
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if save_wr = '1' then
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-- back-to-back write?
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state <= s_write_1;
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ready_for_new <= '1';
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got_transaction <= '0';
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else
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-- write-to-read switch?
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state <= s_read_1;
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iob_dq_hiz <= '1';
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ready_for_new <= '1'; -- we will be ready for a new transaction next cycle!
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got_transaction <= '0';
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end if;
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else
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iob_dq_hiz <= '1';
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state <= s_precharge;
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end if;
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iob_dq_hiz <= '1';
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state <= s_precharge;
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-------------------------------------------------------------------
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-- Closing the row off (this closes all banks)
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@ -15,8 +15,6 @@
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library IEEE;
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use IEEE.STD_LOGIC_1164.ALL;
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use IEEE.NUMERIC_STD.ALL;
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library UNISIM;
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use UNISIM.VComponents.all;
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entity top_level is
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Port ( sysclk_32m : in std_logic;
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@ -169,7 +167,7 @@ begin
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console_select_sync <= console_select_clk1;
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-- reset the system when requested
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if (power_on_reset(0) = '1' or reset_button_sync = '1' or reset_request_uart = '1') then
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if (power_on_reset(0) = '1') then
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system_reset <= '1';
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else
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system_reset <= '0';
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