Initial commit.

vhdl/SSRAM.vhd

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+--
+-- Inferrable Synchronous SRAM for XST synthesis
+--
+-- Version : 0220
+--
+-- Copyright (c) 2002 Daniel Wallner (jesus@opencores.org)
+--
+-- All rights reserved
+--
+-- Redistribution and use in source and synthezised forms, with or without
+-- modification, are permitted provided that the following conditions are met:
+--
+-- Redistributions of source code must retain the above copyright notice,
+-- this list of conditions and the following disclaimer.
+--
+-- Redistributions in synthesized form must reproduce the above copyright
+-- notice, this list of conditions and the following disclaimer in the
+-- documentation and/or other materials provided with the distribution.
+--
+-- Neither the name of the author nor the names of other contributors may
+-- be used to endorse or promote products derived from this software without
+-- specific prior written permission.
+--
+-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
+-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
+-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+-- POSSIBILITY OF SUCH DAMAGE.
+--
+-- Please report bugs to the author, but before you do so, please
+-- make sure that this is not a derivative work and that
+-- you have the latest version of this file.
+--
+-- The latest version of this file can be found at:
+--	http://www.opencores.org/cvsweb.shtml/t51/
+--
+-- Limitations :
+--
+-- File history :
+--	0208 : Initial release
+--	0218 : Fixed data out at write
+--	0220 : Added support for XST
+
+library IEEE;
+use IEEE.std_logic_1164.all;
+use IEEE.numeric_std.all;
+
+entity SSRAM is
+	generic(
+		AddrWidth	: integer := 11;
+		DataWidth	: integer := 8
+	);
+	port(
+		clk			: in std_logic;
+		ce  		: in std_logic;
+		we  		: in std_logic;
+		A			: in std_logic_vector(AddrWidth - 1 downto 0);
+		DIn			: in std_logic_vector(DataWidth - 1 downto 0);
+		DOut		: out std_logic_vector(DataWidth - 1 downto 0)
+	);
+end SSRAM;
+
+architecture behaviour of SSRAM is
+
+	type Memory_Image is array (natural range <>) of std_logic_vector(DataWidth - 1 downto 0);
+	signal	RAM		: Memory_Image(0 to 2 ** AddrWidth - 1);
+	signal	A_r		: std_logic_vector(AddrWidth - 1 downto 0);
+
+begin
+
+	process (Clk)
+	begin
+        if rising_edge(clk) then
+            if (ce = '1' and we = '1') then
+				RAM(to_integer(unsigned(A))) <= DIn;
+			end if;
+			A_r <= A;
+		end if;
+	end process;
+
+	DOut <= RAM(to_integer(unsigned(A_r)));
+end;