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Correct assignement of SDRAM pins and apply HiZ changes from DE2 boards and reset memory config from original.

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This commit is contained in:
Godzil 2015-02-23 02:50:16 +01:00
parent 05f9db46ab
commit b290a1b1bc
3 changed files with 29 additions and 27 deletions
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16
board/de0/de0.tcl
View File

@ -306,8 +306,8 @@ if {$make_assignments} {
set_location_assignment PIN_G7 -to DRAM_CS_N
set_location_assignment PIN_E5 -to DRAM_CLK
set_location_assignment PIN_E6 -to DRAM_CKE
set_location_assignment PIN_B5 -to DRAM_BA_0
set_location_assignment PIN_A4 -to DRAM_BA_1
set_location_assignment PIN_B5 -to DRAM_BA[0]
set_location_assignment PIN_A4 -to DRAM_BA[1]
set_location_assignment PIN_F10 -to DRAM_DQ[15]
set_location_assignment PIN_E10 -to DRAM_DQ[14]
set_location_assignment PIN_A10 -to DRAM_DQ[13]
@ -324,8 +324,8 @@ if {$make_assignments} {
set_location_assignment PIN_H10 -to DRAM_DQ[2]
set_location_assignment PIN_G10 -to DRAM_DQ[1]
set_location_assignment PIN_D10 -to DRAM_DQ[0]
set_location_assignment PIN_E7 -to DRAM_LDQM
set_location_assignment PIN_B8 -to DRAM_UDQM
set_location_assignment PIN_E7 -to DRAM_DQM[0]
set_location_assignment PIN_B8 -to DRAM_DQM[1]
set_location_assignment PIN_F7 -to DRAM_RAS_N
set_location_assignment PIN_D6 -to DRAM_WE_N
set_location_assignment PIN_B12 -to CLOCK_50_2
@ -576,8 +576,8 @@ if {$make_assignments} {
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_CLK
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_CKE
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_CAS_N
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_BA_1
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_BA_0
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_BA[1]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_BA[0]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_ADDR[0]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_ADDR[1]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_ADDR[2]
@ -592,9 +592,9 @@ if {$make_assignments} {
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_ADDR[11]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_ADDR[12]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_WE_N
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_UDQM
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQM[0]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_RAS_N
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_LDQM
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQM[1]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[0]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[1]

32
vhdl/board/de0/SDRAM_Controller.vhd
View File

@ -102,19 +102,19 @@ architecture Behavioral of SDRAM_Controller is
signal iob_cke : std_logic := '0';
signal iob_bank : std_logic_vector( 1 downto 0) := (others => '0');
--attribute IOB: string;
--attribute IOB of iob_command: signal is "true";
--attribute IOB of iob_address: signal is "true";
--attribute IOB of iob_dqm : signal is "true";
--attribute IOB of iob_cke : signal is "true";
--attribute IOB of iob_bank : signal is "true";
--attribute IOB of iob_data : signal is "true";
attribute IOB: string;
attribute IOB of iob_command: signal is "true";
attribute IOB of iob_address: signal is "true";
attribute IOB of iob_dqm : signal is "true";
attribute IOB of iob_cke : signal is "true";
attribute IOB of iob_bank : signal is "true";
attribute IOB of iob_data : signal is "true";
signal iob_data_next : std_logic_vector(15 downto 0) := (others => '0');
signal captured_data : std_logic_vector(15 downto 0) := (others => '0');
signal captured_data_last : std_logic_vector(15 downto 0) := (others => '0');
signal sdram_din : std_logic_vector(15 downto 0);
--attribute IOB of captured_data : signal is "true";
attribute IOB of captured_data : signal is "true";
type fsm_state is (s_startup,
s_idle_in_6, s_idle_in_5, s_idle_in_4, s_idle_in_3, s_idle_in_2, s_idle_in_1,
@ -205,17 +205,19 @@ begin
sdram_dqm <= iob_dqm;
sdram_ba <= iob_bank;
sdram_addr <= iob_address;
sdram_din <= sdram_data;
sdram_data <= iob_data when iob_dq_hiz = '0' else (others => 'Z');
---------------------------------------------------------------
-- Explicitly set up the tristate I/O buffers on the DQ signals
---------------------------------------------------------------
iob_dq_g: for i in 0 to 15 generate
begin
iob_dq_iob: altiobuf_bidir
generic map (number_of_channels => 1)
port map ( dataout(0) => sdram_din(i), dataio(0) => sdram_data(i), datain(0) => iob_data(i), oe(0) => iob_dq_hiz);
end generate;
--iob_dq_g: for i in 0 to 15 generate
-- begin
--iob_dq_iob: altiobuf_bidir
-- generic map (number_of_channels => 1)
-- port map ( dataout(0) => sdram_din(i), dataio(0) => sdram_data(i), datain(0) => iob_data(i), oe(0) => iob_dq_hiz);
--end generate;
capture_proc: process(clk)
begin
if rising_edge(clk) then

8
vhdl/board/de0/top_level_de0.vhd
View File

@ -67,10 +67,10 @@ architecture Behavioral of top_level is
constant clk_freq_mhz : natural := 50; -- this is the frequency which the PLL outputs, in MHz.
-- SDRAM configuration
constant sdram_line_count : natural := 4096;
constant sdram_address_width : natural := 22;
constant sdram_column_bits : natural := 8;
constant cycles_per_refresh : natural := (64000*clk_freq_mhz)/sdram_line_count-1;
constant sdram_address_width : natural := 24;
constant sdram_column_bits : natural := 9;
constant cycles_per_refresh : natural := (64000*clk_freq_mhz)/8192-1;
-- For simulation, we don't need a long init stage. but for real DRAM we need approx 101us.
-- The constant below has a different value when interpreted by the synthesis and simulator