392 lines
18 KiB
VHDL
392 lines
18 KiB
VHDL
--+-----------------------------------+-------------------------------------+--
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--| ___ ___ | (c) 2013-2014 William R Sowerbutts |--
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--| ___ ___ ___ ___( _ ) / _ \ | will@sowerbutts.com |--
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--| / __|/ _ \ / __|_ / _ \| | | | | |--
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--| \__ \ (_) | (__ / / (_) | |_| | | A Z80 FPGA computer, just for fun |--
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--| |___/\___/ \___/___\___/ \___/ | |--
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--| | http://sowerbutts.com/ |--
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--+-----------------------------------+-------------------------------------+--
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--| DRAM interface: Connect the CPU to the SDRAM on the Papilio Pro board. |--
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--| The SDRAM takes about 10 cycles to respond with data after making a |--
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--| request, so this module includes a direct-mapped cache to store |--
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--| recently read or written data in order to hide this latency. |--
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--+-------------------------------------------------------------------------+--
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--
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-- The Papilio Pro board has an 8MB SDRAM chip on the board. The socz80 MMU
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-- provides a 64MB (26-bit) phyiscal address space. The low 32MB of address space
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-- is allocated to the DRAM (the top 32MB being used for other memory devices).
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--
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-- The low 32MB is divided into two 16MB blocks. Accesses to the first block
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-- (starting at 0MB) go through the cache, while accesses to the second
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-- block (starting at 16MB) bypass the cache. There is only 8MB SDRAM on the
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-- Papilio Pro so it is aliased twice in each block, ie it appears at 0MB,
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-- 8MB, 16MB and 24MB.
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--
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-- The cache is direct mapped, ie the low bits of the address dictate which cache
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-- line to use and which byte within that line. When a cache line is written to
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-- the top bits of the address are stored in "cache tag" memory. When a cache line
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-- is read the top bits of the address are compared to the stored tag to determine
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-- if the cached data relates to the same address.
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--
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-- Each cache line consists of a 45 bits:
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-- 32 bits of cached data
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-- 4 validity bits to indicate if the cached data is valid or not
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-- 9 bits of address tag to indicate the top address bits of the
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--
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-- bit number (read these two 22222211111111110000000000
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-- lines top to bottom) 54321098765432109876543210
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--
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-- CPU address is 16 bits wide: PPPPOOOOOOOOOOOO (4 bit page, 12 bit offset)
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-- physical address is 26 bits wide: FFFFFFFFFFFFFFOOOOOOOOOOOO (14 bit frame, 12 bit offset)
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-- DRAM address is 25 bits wide: CIFFFFFFFFFFFOOOOOOOOOOOO (1 bit cache flag, 1 bit ignored, 11 bit frame, 12 bit offset)
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-- cached address is 23 bits wide: TTTTTTTTTLLLLLLLLLLLLBB (9 bit cache line tag, 12 bit cache line, 2 bit byte offset)
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--
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-- cache lines use 4096 x 36 bit BRAM
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-- cache tags use 4096 x 9 bit BRAM
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library IEEE;
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use IEEE.std_logic_1164.all;
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use IEEE.numeric_std.all;
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entity DRAM is
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generic(
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sdram_address_width : natural;
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sdram_column_bits : natural;
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sdram_startup_cycles: natural;
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cycles_per_refresh : natural
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);
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port(
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-- interface to the system
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clk : in std_logic;
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reset : in std_logic;
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cs : in std_logic;
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req_read : in std_logic;
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req_write : in std_logic;
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mem_address : in std_logic_vector(24 downto 0);
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data_in : in std_logic_vector(7 downto 0);
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data_out : out std_logic_vector(7 downto 0) := (others => '0');
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mem_wait : out std_logic;
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coldboot : out std_logic; -- this signals 1 until the SDRAM has been initialised
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-- interface to hardware SDRAM chip
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SDRAM_CLK : out std_logic;
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SDRAM_CKE : out std_logic;
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SDRAM_CS : out std_logic;
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SDRAM_nRAS : out std_logic;
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SDRAM_nCAS : out std_logic;
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SDRAM_nWE : out std_logic;
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SDRAM_DQM : out std_logic_vector( 1 downto 0);
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SDRAM_ADDR : out std_logic_vector (12 downto 0);
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SDRAM_BA : out std_logic_vector( 1 downto 0);
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SDRAM_DQ : inout std_logic_vector (15 downto 0)
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);
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end DRAM;
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architecture behaviour of DRAM is
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-- sdram controller interface
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signal cmd_address : std_logic_vector(sdram_address_width-2 downto 0) := (others => '0');
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signal cmd_wr : std_logic := '1';
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signal cmd_enable : std_logic;
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signal cmd_byte_enable : std_logic_vector(3 downto 0);
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signal cmd_data_in : std_logic_vector(31 downto 0);
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signal cmd_ready : std_logic;
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signal sdram_data_out : std_logic_vector(31 downto 0);
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signal sdram_data_out_ready : std_logic;
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signal seen_ready : std_logic := '0';
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signal last_address_word : std_logic_vector(20 downto 0);
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-- internal signals
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signal current_word : std_logic_vector(31 downto 0); -- value of current cache line
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signal current_byte_valid : std_logic_vector(3 downto 0); -- validity bits for current cache line
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signal word_changed : std_logic; -- did the address bus value change?
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signal cache_hit : std_logic;
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signal address_hit : std_logic;
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signal byte_valid_hit : std_logic;
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signal write_back : std_logic;
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-- state machine
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type controller_state is ( st_idle, -- waiting for command
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st_read, -- cache miss: issued read command to controller, waiting for data to arrive
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st_read_done, -- cache hit/completed miss: data arrived from controller, waiting for CPU to de-assert
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st_write); -- write: issued write command, waiting for CPU to de-assert
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signal current_state : controller_state;
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signal next_state : controller_state;
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-- here's the cache memory signals
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signal cache_line_memory_write_enable : std_logic;
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signal cache_line_memory_data_in : std_logic_vector(35 downto 0); -- 35 downto 32: validity bits; 31 downto 0: four data bytes
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signal cache_line_memory_data_out : std_logic_vector(35 downto 0);
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signal cache_tag_memory_write_enable : std_logic;
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signal cache_tag_memory_data_in : std_logic_vector(8 downto 0);
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signal cache_tag_memory_data_out : std_logic_vector(8 downto 0);
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-- break up the incoming physical address
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alias address_byte : std_logic_vector(1 downto 0) is mem_address(1 downto 0);
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alias address_line : std_logic_vector(11 downto 0) is mem_address(13 downto 2);
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alias address_tag : std_logic_vector(8 downto 0) is mem_address(22 downto 14);
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alias address_word : std_logic_vector(20 downto 0) is mem_address(22 downto 2);
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-- mem_address(23) and mem_address(24) are unused in this design
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alias cache_inhibit : std_logic is mem_address(24);
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begin
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-- this should be based on the generic, really
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cmd_address <= mem_address((sdram_address_width) downto 2); -- address_tag & address_line
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cmd_data_in <= data_in & data_in & data_in & data_in; -- write the same data four times
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cmd_wr <= req_write;
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coldboot <= not seen_ready;
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compute_next_state: process(req_read, req_write, current_state, cache_hit, cmd_ready, cs, sdram_data_out_ready, word_changed)
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begin
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cmd_enable <= '0';
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mem_wait <= '0';
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write_back <= '0';
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case current_state is
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when st_idle =>
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if cs = '1' and cmd_ready = '1' then
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if req_read = '1' then
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-- we can't process a read immediately if the address input just changed; delay them for one cycle.
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if word_changed = '1' then
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mem_wait <= '1';
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next_state <= st_idle;
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-- come back next cycle!
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else
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if cache_hit = '1' then
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mem_wait <= '0';
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next_state <= st_read_done;
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else
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cmd_enable <= '1';
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mem_wait <= '1';
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next_state <= st_read;
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end if;
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end if;
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elsif req_write = '1' then
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if word_changed = '1' then
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mem_wait <= '1';
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next_state <= st_idle;
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-- come back next cycle!
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else
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next_state <= st_write;
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cmd_enable <= '1';
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mem_wait <= '0'; -- no need to wait, the SDRAM controller will latch all the inputs
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write_back <= '1';
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end if;
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else
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next_state <= st_idle;
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mem_wait <= '0'; -- we know cmd_ready='1'
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end if;
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else
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next_state <= st_idle;
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mem_wait <= (not cmd_ready);
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end if;
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when st_read =>
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if cs = '1' and req_read = '1' then
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if sdram_data_out_ready = '1' then
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next_state <= st_read_done;
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else
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next_state <= st_read;
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end if;
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else
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-- this kind of implies that they gave up on us?
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next_state <= st_idle;
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end if;
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mem_wait <= (not sdram_data_out_ready) and (not cache_hit);
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when st_read_done =>
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if cs = '1' and req_read = '1' then
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next_state <= st_read_done;
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else
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next_state <= st_idle;
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end if;
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mem_wait <= (not sdram_data_out_ready) and (not cache_hit);
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when st_write =>
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if cs = '1' and req_write = '1' then
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next_state <= st_write;
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else
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next_state <= st_idle;
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end if;
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mem_wait <= (not cmd_ready); -- no need to wait once the write has been committed
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end case;
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end process;
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word_changed_check: process(last_address_word, address_word)
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begin
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if address_word = last_address_word then
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word_changed <= '0';
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else
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word_changed <= '1';
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end if;
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end process;
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cache_address_check: process(cache_tag_memory_data_out, cache_line_memory_data_out, address_tag)
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begin
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if cache_tag_memory_data_out = address_tag then
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address_hit <= '1';
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current_byte_valid <= cache_line_memory_data_out(35 downto 32);
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else
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address_hit <= '0';
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current_byte_valid <= "0000";
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end if;
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end process;
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cache_byte_valid_check: process(address_byte, current_byte_valid)
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begin
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case address_byte is
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when "00" => byte_valid_hit <= current_byte_valid(0);
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when "01" => byte_valid_hit <= current_byte_valid(1);
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when "10" => byte_valid_hit <= current_byte_valid(2);
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when "11" => byte_valid_hit <= current_byte_valid(3);
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when others => byte_valid_hit <= '0';
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end case;
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end process;
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cache_hit_check: process(byte_valid_hit, address_hit, cache_inhibit)
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begin
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if address_hit = '1' and byte_valid_hit = '1' and cache_inhibit = '0' then
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cache_hit <= '1';
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else
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cache_hit <= '0';
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end if;
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end process;
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byte_enable_decode: process(address_byte)
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begin
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case address_byte is
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when "00" => cmd_byte_enable <= "0001";
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when "01" => cmd_byte_enable <= "0010";
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when "10" => cmd_byte_enable <= "0100";
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when "11" => cmd_byte_enable <= "1000";
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when others => cmd_byte_enable <= "1000";
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end case;
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end process;
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data_out_demux: process(address_byte, sdram_data_out_ready, sdram_data_out, cache_line_memory_data_out, current_word)
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begin
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-- when the SDRAM is presenting data, feed it direct to the CPU.
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-- otherwise feed data from our cache memory.
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if sdram_data_out_ready = '1' then
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current_word <= sdram_data_out;
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else
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current_word <= cache_line_memory_data_out(31 downto 0);
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end if;
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case address_byte is
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when "00" => data_out <= current_word( 7 downto 0);
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when "01" => data_out <= current_word(15 downto 8);
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when "10" => data_out <= current_word(23 downto 16);
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when "11" => data_out <= current_word(31 downto 24);
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when others => data_out <= current_word(31 downto 24);
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end case;
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end process;
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cache_write: process(current_state, data_in, next_state, write_back, cache_line_memory_data_out, sdram_data_out, sdram_data_out_ready, address_byte, current_byte_valid)
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begin
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if (next_state = st_read) or (write_back = '1') then
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cache_tag_memory_write_enable <= '1';
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else
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cache_tag_memory_write_enable <= '0';
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end if;
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cache_line_memory_write_enable <= '0';
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cache_line_memory_data_in <= cache_line_memory_data_out;
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if next_state = st_read then
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cache_line_memory_data_in <= (others => '0'); -- set word and all valid flags to 1
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cache_line_memory_write_enable <= '1';
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end if;
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-- has our read completed?
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if current_state = st_read then
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if sdram_data_out_ready = '1' then
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cache_line_memory_data_in <= "1111" & sdram_data_out;
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cache_line_memory_write_enable <= '1';
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end if;
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elsif write_back = '1' then
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case address_byte is
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when "00" =>
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cache_line_memory_data_in <= current_byte_valid(3 downto 1) & "1" &
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cache_line_memory_data_out(31 downto 8) & data_in;
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when "01" =>
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cache_line_memory_data_in <=
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current_byte_valid(3 downto 2) & "1" & current_byte_valid(0) &
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cache_line_memory_data_out(31 downto 16) & data_in & cache_line_memory_data_out(7 downto 0);
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when "10" =>
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cache_line_memory_data_in <=
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current_byte_valid(3) & "1" & current_byte_valid(1 downto 0) &
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cache_line_memory_data_out(31 downto 24) & data_in & cache_line_memory_data_out(15 downto 0);
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when "11" =>
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cache_line_memory_data_in <=
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"1" & current_byte_valid(2 downto 0) &
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data_in & cache_line_memory_data_out(23 downto 0);
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when others => -- shut up, compiler!
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end case;
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cache_line_memory_write_enable <= '1';
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end if;
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end process;
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sdram_registers: process(clk)
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begin
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if rising_edge(clk) then
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-- state register
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current_state <= next_state;
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-- coldboot detection
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seen_ready <= seen_ready or cmd_ready;
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-- track memory address
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last_address_word <= address_word;
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end if;
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end process;
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-- underlying SDRAM controller (thanks, Hamsterworks!)
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sdram_ctrl: entity work.SDRAM_Controller
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GENERIC MAP(
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sdram_address_width => sdram_address_width,
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sdram_column_bits => sdram_column_bits,
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sdram_startup_cycles=> sdram_startup_cycles,
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cycles_per_refresh => cycles_per_refresh
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)
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PORT MAP(
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clk => clk,
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reset => reset,
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cmd_address => cmd_address,
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cmd_wr => cmd_wr,
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cmd_enable => cmd_enable,
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cmd_ready => cmd_ready,
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cmd_byte_enable => cmd_byte_enable,
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cmd_data_in => cmd_data_in,
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data_out => sdram_data_out,
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data_out_ready => sdram_data_out_ready,
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SDRAM_CLK => SDRAM_CLK,
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SDRAM_CKE => SDRAM_CKE,
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SDRAM_CS => SDRAM_CS,
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SDRAM_RAS => SDRAM_nRAS,
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SDRAM_CAS => SDRAM_nCAS,
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SDRAM_WE => SDRAM_nWE,
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SDRAM_DQM => SDRAM_DQM,
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SDRAM_BA => SDRAM_BA,
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SDRAM_ADDR => SDRAM_ADDR,
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SDRAM_DATA => SDRAM_DQ
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);
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-- block RAM used to store cache line data and byte validity (packs nicely into 36 bits)
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cacheline_memory_sram: entity work.RAM4K36
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port map (
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clk => clk,
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write => cache_line_memory_write_enable,
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address => address_line,
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data_in => cache_line_memory_data_in,
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data_out => cache_line_memory_data_out
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);
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-- block RAM used to store cache line tag memory (packs nicely into 9 bits)
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cachetag_memory_sram: entity work.RAM4K9
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port map (
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clock => clk,
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wren => cache_tag_memory_write_enable,
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address => address_line,
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data => cache_tag_memory_data_in,
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q => cache_tag_memory_data_out
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);
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end;
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