68 lines
2.0 KiB
VHDL
68 lines
2.0 KiB
VHDL
--+-----------------------------------+-------------------------------------+--
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--| ___ ___ | (c) 2013-2014 William R Sowerbutts |--
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--| ___ ___ ___ ___( _ ) / _ \ | will@sowerbutts.com |--
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--| / __|/ _ \ / __|_ / _ \| | | | | |--
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--| \__ \ (_) | (__ / / (_) | |_| | | A Z80 FPGA computer, just for fun |--
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--| |___/\___/ \___/___\___/ \___/ | |--
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--| | http://sowerbutts.com/ |--
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--+-----------------------------------+-------------------------------------+--
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--| A 4096 entry deep, 36-bit wide RAM using four RAM4K9 devices (and thus |--
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--| eight Xilinx RAMB16BWER devices) |--
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--+-------------------------------------------------------------------------+--
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library IEEE;
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use IEEE.std_logic_1164.all;
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use IEEE.numeric_std.all;
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library UNISIM;
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entity RAM4K36 is
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port(
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clk : in std_logic;
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write : in std_logic;
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address : in std_logic_vector(11 downto 0);
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data_in : in std_logic_vector(35 downto 0);
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data_out : out std_logic_vector(35 downto 0)
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);
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end RAM4K36;
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architecture behaviour of RAM4K36 is
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begin
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ram0: entity work.RAM4K9
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port map (
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clock => clk,
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wren => write,
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address => address,
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data => data_in(8 downto 0),
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q => data_out(8 downto 0)
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);
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ram1: entity work.RAM4K9
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port map (
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clock => clk,
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wren => write,
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address => address,
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data => data_in(17 downto 9),
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q => data_out(17 downto 9)
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);
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ram2: entity work.RAM4K9
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port map (
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clock => clk,
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wren => write,
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address => address,
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data => data_in(26 downto 18),
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q => data_out(26 downto 18)
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);
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ram3: entity work.RAM4K9
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port map (
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clock => clk,
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wren => write,
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address => address,
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data => data_in(35 downto 27),
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q => data_out(35 downto 27)
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);
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end;
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