97 lines
3.3 KiB
VHDL
97 lines
3.3 KiB
VHDL
--+-----------------------------------+-------------------------------------+--
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--| ___ ___ | (c) 2013-2014 William R Sowerbutts |--
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--| ___ ___ ___ ___( _ ) / _ \ | will@sowerbutts.com |--
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--| / __|/ _ \ / __|_ / _ \| | | | | |--
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--| \__ \ (_) | (__ / / (_) | |_| | | A Z80 FPGA computer, just for fun |--
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--| |___/\___/ \___/___\___/ \___/ | |--
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--| | http://sowerbutts.com/ |--
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--+-----------------------------------+-------------------------------------+--
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--| Wrap the T80 CPU core and produce more easily comprehended signals |--
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--+-------------------------------------------------------------------------+--
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library IEEE;
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use IEEE.std_logic_1164.all;
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use IEEE.numeric_std.all;
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use work.T80_Pack.all;
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entity Z80cpu is
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port (
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-- reset
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reset : in std_logic;
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-- clocking
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clk : in std_logic;
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clk_enable : in std_logic;
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-- indicates when we're in the M1 cycle (start of an instruction)
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m1_cycle : out std_logic;
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-- memory and I/O interface
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req_mem : out std_logic; -- memory request?
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req_io : out std_logic; -- i/o request?
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req_read : out std_logic; -- read?
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req_write : out std_logic; -- write?
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mem_wait : in std_logic; -- memory or i/o can force the CPU to wait
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address : out std_logic_vector(15 downto 0);
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data_in : in std_logic_vector(7 downto 0);
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data_out : out std_logic_vector(7 downto 0);
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-- interrupts
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interrupt : in std_logic;
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nmi : in std_logic
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);
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end Z80cpu;
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architecture behavioural of Z80cpu is
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signal RESET_n : std_logic;
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signal WAIT_n : std_logic;
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signal INT_n : std_logic;
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signal NMI_n : std_logic;
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signal M1_n : std_logic;
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signal MREQ_n : std_logic;
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signal IORQ_n : std_logic;
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signal RFSH_n : std_logic;
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signal RD_n : std_logic;
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signal WR_n : std_logic;
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begin
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RESET_n <= not reset;
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WAIT_n <= not mem_wait;
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INT_n <= not interrupt;
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NMI_n <= not nmi;
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m1_cycle <= not M1_n;
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req_mem <= (not MREQ_n) and (RFSH_n);
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req_io <= (not IORQ_n) and (M1_n); -- IORQ is active during M1 when handling interrupts (it's well documented, but I found out the hard way...)
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req_read <= (not RD_n) and (RFSH_n);
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req_write <= (not WR_n);
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cpu : entity work.T80se
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generic map (
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Mode => 1, -- 0 => Z80, 1 => Fast Z80, 2 => 8080, 3 => GB
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T2Write => 1, -- 0 => WR_n active in T3, /=0 => WR_n active in T2
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IOWait => 0 -- 0 => single cycle I/O, 1 => standard I/O cycle
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)
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port map (
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RESET_n => RESET_n,
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CLK_n => clk,
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CLKEN => clk_enable,
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WAIT_n => WAIT_n,
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INT_n => INT_n,
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NMI_n => NMI_n,
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BUSRQ_n => '1',
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BUSAK_n => open,
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M1_n => M1_n,
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MREQ_n => MREQ_n,
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IORQ_n => IORQ_n,
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RD_n => RD_n,
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WR_n => WR_n,
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RFSH_n => RFSH_n,
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HALT_n => open,
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A => address,
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DI => data_in,
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DO => data_out
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);
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end;
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