57 lines
1.9 KiB
VHDL
57 lines
1.9 KiB
VHDL
--+-----------------------------------+-------------------------------------+--
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--| ___ ___ | (c) 2013-2014 William R Sowerbutts |--
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--| ___ ___ ___ ___( _ ) / _ \ | will@sowerbutts.com |--
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--| / __|/ _ \ / __|_ / _ \| | | | | |--
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--| \__ \ (_) | (__ / / (_) | |_| | | A Z80 FPGA computer, just for fun |--
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--| |___/\___/ \___/___\___/ \___/ | |--
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--| | http://sowerbutts.com/ |--
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--+-----------------------------------+-------------------------------------+--
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--| An inferrable 4KB ROM to contain the monitor program |--
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--+-------------------------------------------------------------------------+--
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--
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-- MonZ80_template.vhd contains the template VHDL for the ROM but no actual
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-- data. The "ROMHERE" string is replaced by byte data by the "make_vhdl_rom"
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-- tool in software/tools which is invoked to generate "MonZ80.vhd" after
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-- the monitor program has been assembled.
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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entity MonZ80 is
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port(
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clk : in std_logic;
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a : in std_logic_vector(11 downto 0);
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d : out std_logic_vector(7 downto 0)
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);
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end MonZ80;
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architecture arch of MonZ80 is
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constant byte_rom_WIDTH: integer := 8;
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type byte_rom_type is array (0 to 4095) of std_logic_vector(byte_rom_WIDTH-1 downto 0);
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signal address_latch : std_logic_vector(11 downto 0) := (others => '0');
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-- actually memory cells
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signal byte_rom : byte_rom_type := (
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-- ROM contents follows
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%ROMHERE%
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);
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begin
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ram_process: process(clk, byte_rom)
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begin
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if rising_edge(clk) then
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-- latch the address, in order to infer a synchronous memory
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address_latch <= a;
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end if;
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end process;
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d <= byte_rom(to_integer(unsigned(address_latch)));
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end arch;
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