473 lines
23 KiB
VHDL
473 lines
23 KiB
VHDL
----------------------------------------------------------------------------------
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-- Engineer: Mike Field <hamster@snap.net.nz>
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--
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-- Create Date: 14:09:12 09/15/2013
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-- Module Name: SDRAM_Controller - Behavioral
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-- Description: Simple SDRAM controller for a Micron 48LC16M16A2-7E
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-- or Micron 48LC4M16A2-7E @ 100MHz
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-- Revision:
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-- Revision 0.1 - Initial version
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-- Revision 0.2 - Removed second clock signal that isn't needed.
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-- Revision 0.3 - Added back-to-back reads and writes.
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-- Revision 0.4 - Allow refeshes to be delayed till next PRECHARGE is issued,
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-- Unless they get really, really delayed. If a delay occurs multiple
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-- refreshes might get pushed out, but it will have avioded about
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-- 50% of the refresh overhead
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-- Revision 0.5 - Add more paramaters to the design, allowing it to work for both the
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-- Papilio Pro and Logi-Pi
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--
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-- Worst case performance (single accesses to different rows or banks) is:
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-- Writes 16 cycles = 6,250,000 writes/sec = 25.0MB/s (excluding refresh overhead)
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-- Reads 17 cycles = 5,882,352 reads/sec = 23.5MB/s (excluding refresh overhead)
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--
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-- For 1:1 mixed reads and writes into the same row it is around 88MB/s
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-- For reads or wries to the same it is can be as high as 184MB/s
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----------------------------------------------------------------------------------
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library IEEE;
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use IEEE.STD_LOGIC_1164.ALL;
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library UNISIM;
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use IEEE.NUMERIC_STD.ALL;
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library altera_mf;
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use altera_mf.altera_mf_components.all;
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entity SDRAM_Controller is
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generic (
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sdram_address_width : natural;
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sdram_column_bits : natural;
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sdram_startup_cycles: natural;
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cycles_per_refresh : natural
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);
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Port ( clk : in STD_LOGIC;
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reset : in STD_LOGIC;
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-- Interface to issue reads or write data
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cmd_ready : out STD_LOGIC; -- '1' when a new command will be acted on
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cmd_enable : in STD_LOGIC; -- Set to '1' to issue new command (only acted on when cmd_read = '1')
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cmd_wr : in STD_LOGIC; -- Is this a write?
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cmd_address : in STD_LOGIC_VECTOR(sdram_address_width-2 downto 0); -- address to read/write
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cmd_byte_enable : in STD_LOGIC_VECTOR(3 downto 0); -- byte masks for the write command
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cmd_data_in : in STD_LOGIC_VECTOR(31 downto 0); -- data for the write command
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data_out : out STD_LOGIC_VECTOR(31 downto 0); -- word read from SDRAM
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data_out_ready : out STD_LOGIC; -- is new data ready?
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-- SDRAM signals
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SDRAM_CLK : out STD_LOGIC;
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SDRAM_CKE : out STD_LOGIC;
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SDRAM_CS : out STD_LOGIC;
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SDRAM_RAS : out STD_LOGIC;
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SDRAM_CAS : out STD_LOGIC;
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SDRAM_WE : out STD_LOGIC;
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SDRAM_DQM : out STD_LOGIC_VECTOR( 1 downto 0);
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SDRAM_ADDR : out STD_LOGIC_VECTOR(12 downto 0);
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SDRAM_BA : out STD_LOGIC_VECTOR( 1 downto 0);
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SDRAM_DATA : inout STD_LOGIC_VECTOR(15 downto 0));
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end SDRAM_Controller;
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architecture Behavioral of SDRAM_Controller is
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-- From page 37 of MT48LC16M16A2 datasheet
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-- Name (Function) CS# RAS# CAS# WE# DQM Addr Data
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-- COMMAND INHIBIT (NOP) H X X X X X X
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-- NO OPERATION (NOP) L H H H X X X
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-- ACTIVE L L H H X Bank/row X
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-- READ L H L H L/H Bank/col X
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-- WRITE L H L L L/H Bank/col Valid
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-- BURST TERMINATE L H H L X X Active
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-- PRECHARGE L L H L X Code X
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-- AUTO REFRESH L L L H X X X
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-- LOAD MODE REGISTER L L L L X Op-code X
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-- Write enable X X X X L X Active
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-- Write inhibit X X X X H X High-Z
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-- Here are the commands mapped to constants
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constant CMD_UNSELECTED : std_logic_vector(3 downto 0) := "1000";
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constant CMD_NOP : std_logic_vector(3 downto 0) := "0111";
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constant CMD_ACTIVE : std_logic_vector(3 downto 0) := "0011";
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constant CMD_READ : std_logic_vector(3 downto 0) := "0101";
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constant CMD_WRITE : std_logic_vector(3 downto 0) := "0100";
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constant CMD_TERMINATE : std_logic_vector(3 downto 0) := "0110";
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constant CMD_PRECHARGE : std_logic_vector(3 downto 0) := "0010";
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constant CMD_REFRESH : std_logic_vector(3 downto 0) := "0001";
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constant CMD_LOAD_MODE_REG : std_logic_vector(3 downto 0) := "0000";
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constant MODE_REG : std_logic_vector(12 downto 0) :=
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-- Reserved, wr bust, OpMode, CAS Latency (2), Burst Type, Burst Length (2)
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"000" & "0" & "00" & "010" & "0" & "001";
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signal iob_command : std_logic_vector( 3 downto 0) := CMD_NOP;
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signal iob_address : std_logic_vector(12 downto 0) := (others => '0');
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signal iob_data : std_logic_vector(15 downto 0) := (others => '0');
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signal iob_dqm : std_logic_vector( 1 downto 0) := (others => '0');
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signal iob_cke : std_logic := '0';
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signal iob_bank : std_logic_vector( 1 downto 0) := (others => '0');
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attribute IOB: string;
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attribute IOB of iob_command: signal is "true";
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attribute IOB of iob_address: signal is "true";
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attribute IOB of iob_dqm : signal is "true";
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attribute IOB of iob_cke : signal is "true";
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attribute IOB of iob_bank : signal is "true";
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attribute IOB of iob_data : signal is "true";
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signal iob_data_next : std_logic_vector(15 downto 0) := (others => '0');
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signal captured_data : std_logic_vector(15 downto 0) := (others => '0');
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signal captured_data_last : std_logic_vector(15 downto 0) := (others => '0');
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signal sdram_din : std_logic_vector(15 downto 0);
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attribute IOB of captured_data : signal is "true";
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type fsm_state is (s_startup,
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s_idle_in_6, s_idle_in_5, s_idle_in_4, s_idle_in_3, s_idle_in_2, s_idle_in_1,
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s_idle,
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s_open_in_2, s_open_in_1,
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s_write_1, s_write_2, s_write_3,
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s_read_1, s_read_2, s_read_3, s_read_4,
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s_precharge
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);
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signal state : fsm_state := s_startup;
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attribute FSM_ENCODING : string;
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attribute FSM_ENCODING of state : signal is "ONE-HOT";
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-- dual purpose counter, it counts up during the startup phase, then is used to trigger refreshes.
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constant startup_refresh_max : unsigned(13 downto 0) := (others => '1');
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signal startup_refresh_count : unsigned(13 downto 0) := startup_refresh_max-to_unsigned(sdram_startup_cycles,14);
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-- logic to decide when to refresh
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signal pending_refresh : std_logic := '0';
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signal forcing_refresh : std_logic := '0';
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-- The incoming address is split into these three values
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signal addr_row : std_logic_vector(12 downto 0) := (others => '0');
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signal addr_col : std_logic_vector(12 downto 0) := (others => '0');
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signal addr_bank : std_logic_vector( 1 downto 0) := (others => '0');
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signal dqm_sr : std_logic_vector( 3 downto 0) := (others => '1'); -- an extra two bits in case CAS=3
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-- signals to hold the requested transaction before it is completed
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signal save_wr : std_logic := '0';
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signal save_row : std_logic_vector(12 downto 0);
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signal save_bank : std_logic_vector( 1 downto 0);
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signal save_col : std_logic_vector(12 downto 0);
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signal save_data_in : std_logic_vector(31 downto 0);
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signal save_byte_enable : std_logic_vector( 3 downto 0);
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-- control when new transactions are accepted
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signal ready_for_new : std_logic := '0';
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signal got_transaction : std_logic := '0';
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signal can_back_to_back : std_logic := '0';
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-- signal to control the Hi-Z state of the DQ bus
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signal iob_dq_hiz : std_logic := '1';
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-- signals for when to read the data off of the bus
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signal data_ready_delay : std_logic_vector( 4 downto 0);
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-- bit indexes used when splitting the address into row/colum/bank.
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constant start_of_col : natural := 0;
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constant end_of_col : natural := sdram_column_bits-2;
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constant start_of_bank : natural := sdram_column_bits-1;
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constant end_of_bank : natural := sdram_column_bits;
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constant start_of_row : natural := sdram_column_bits+1;
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constant end_of_row : natural := sdram_address_width-2;
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constant prefresh_cmd : natural := 10;
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begin
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-- Indicate the need to refresh when the counter is 2048,
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-- Force a refresh when the counter is 4096 - (if a refresh is forced,
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-- multiple refresshes will be forced until the counter is below 2048
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pending_refresh <= startup_refresh_count(11);
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forcing_refresh <= startup_refresh_count(12);
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-- tell the outside world when we can accept a new transaction;
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cmd_ready <= ready_for_new;
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----------------------------------------------------------------------------
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-- Seperate the address into row / bank / address
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----------------------------------------------------------------------------
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addr_row(end_of_row-start_of_row downto 0) <= cmd_address(end_of_row downto start_of_row); -- 12:0 <= 22:10
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addr_bank <= cmd_address(end_of_bank downto start_of_bank); -- 1:0 <= 9:8
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addr_col(sdram_column_bits-1 downto 0) <= cmd_address(end_of_col downto start_of_col) & '0'; -- 8:0 <= 7:0 & '0'
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--addr_row(12 downto 0) <= cmd_address(22 downto 10); -- 12:0 <= 22:10
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--addr_bank <= cmd_address( 9 downto 8); -- 1:0 <= 9:8
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--addr_col(8 downto 0) <= cmd_address( 7 downto 0) & '0'; -- 8:0 <= 7:0 & '0'
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-----------------------------------------------
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--!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!
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--!! Ensure that all outputs are registered. !!
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--!! Check the pinout report to be sure !!
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--!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!
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-----------------------------------------------
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sdram_cke <= iob_cke;
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sdram_CS <= iob_command(3);
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sdram_RAS <= iob_command(2);
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sdram_CAS <= iob_command(1);
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sdram_WE <= iob_command(0);
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sdram_dqm <= iob_dqm;
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sdram_ba <= iob_bank;
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sdram_addr <= iob_address;
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---------------------------------------------------------------
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-- Explicitly set up the tristate I/O buffers on the DQ signals
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---------------------------------------------------------------
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iob_dq_g: for i in 0 to 15 generate
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begin
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iob_dq_iob: altiobuf_bidir
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generic map (number_of_channels => 1)
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port map ( dataout(0) => sdram_din(i), dataio(0) => sdram_data(i), datain(0) => iob_data(i), oe(0) => iob_dq_hiz);
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end generate;
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capture_proc: process(clk)
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begin
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if rising_edge(clk) then
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captured_data <= sdram_din;
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end if;
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end process;
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main_proc: process(clk)
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begin
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if rising_edge(clk) then
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captured_data_last <= captured_data;
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------------------------------------------------
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-- Default state is to do nothing
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------------------------------------------------
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iob_command <= CMD_NOP;
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iob_address <= (others => '0');
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iob_bank <= (others => '0');
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------------------------------------------------
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-- countdown for initialisation & refresh
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------------------------------------------------
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startup_refresh_count <= startup_refresh_count+1;
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-------------------------------------------------------------------
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-- It we are ready for a new tranasction and one is being presented
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-- then accept it. Also remember what we are reading or writing,
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-- and if it can be back-to-backed with the last transaction
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-------------------------------------------------------------------
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if ready_for_new = '1' and cmd_enable = '1' then
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if save_bank = addr_bank and save_row = addr_row then
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can_back_to_back <= '1';
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else
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can_back_to_back <= '0';
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end if;
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save_row <= addr_row;
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save_bank <= addr_bank;
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save_col <= addr_col;
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save_wr <= cmd_wr;
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save_data_in <= cmd_data_in;
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save_byte_enable <= cmd_byte_enable;
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got_transaction <= '1';
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ready_for_new <= '0';
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end if;
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------------------------------------------------
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-- Handle the data coming back from the
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-- SDRAM for the Read transaction
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------------------------------------------------
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data_out_ready <= '0';
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if data_ready_delay(0) = '1' then
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data_out <= captured_data & captured_data_last;
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data_out_ready <= '1';
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end if;
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----------------------------------------------------------------------------
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-- update shift registers used to choose when to present data to/from memory
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----------------------------------------------------------------------------
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data_ready_delay <= '0' & data_ready_delay(data_ready_delay'high downto 1);
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iob_dqm <= dqm_sr(1 downto 0);
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dqm_sr <= "11" & dqm_sr(dqm_sr'high downto 2);
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case state is
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when s_startup =>
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------------------------------------------------------------------------
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-- This is the initial startup state, where we wait for at least 100us
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-- before starting the start sequence
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--
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-- The initialisation is sequence is
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-- * de-assert SDRAM_CKE
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-- * 100us wait,
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-- * assert SDRAM_CKE
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-- * wait at least one cycle,
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-- * PRECHARGE
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-- * wait 2 cycles
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-- * REFRESH,
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-- * tREF wait
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-- * REFRESH,
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-- * tREF wait
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-- * LOAD_MODE_REG
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-- * 2 cycles wait
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------------------------------------------------------------------------
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iob_CKE <= '1';
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-- All the commands during the startup are NOPS, except these
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if startup_refresh_count = startup_refresh_max-31 then
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-- ensure all rows are closed
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iob_command <= CMD_PRECHARGE;
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iob_address(prefresh_cmd) <= '1'; -- all banks
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iob_bank <= (others => '0');
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elsif startup_refresh_count = startup_refresh_max-23 then
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-- these refreshes need to be at least tREF (66ns) apart
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iob_command <= CMD_REFRESH;
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elsif startup_refresh_count = startup_refresh_max-15 then
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iob_command <= CMD_REFRESH;
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elsif startup_refresh_count = startup_refresh_max-7 then
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-- Now load the mode register
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iob_command <= CMD_LOAD_MODE_REG;
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iob_address <= MODE_REG;
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end if;
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------------------------------------------------------
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-- if startup is coomplete then go into idle mode,
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-- get prepared to accept a new command, and schedule
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-- the first refresh cycle
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------------------------------------------------------
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if startup_refresh_count = 0 then
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state <= s_idle;
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ready_for_new <= '1';
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got_transaction <= '0';
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startup_refresh_count <= to_unsigned(2048 - cycles_per_refresh+1,14);
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end if;
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when s_idle_in_6 => state <= s_idle_in_5;
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when s_idle_in_5 => state <= s_idle_in_4;
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when s_idle_in_4 => state <= s_idle_in_3;
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when s_idle_in_3 => state <= s_idle_in_2;
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when s_idle_in_2 => state <= s_idle_in_1;
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when s_idle_in_1 => state <= s_idle;
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when s_idle =>
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-- Priority is to issue a refresh if one is outstanding
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if pending_refresh = '1' or forcing_refresh = '1' then
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------------------------------------------------------------------------
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-- Start the refresh cycle.
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-- This tasks tRFC (66ns), so 6 idle cycles are needed @ 100MHz
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------------------------------------------------------------------------
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state <= s_idle_in_3;
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iob_command <= CMD_REFRESH;
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startup_refresh_count <= startup_refresh_count - cycles_per_refresh+1;
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elsif got_transaction = '1' then
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--------------------------------
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-- Start the read or write cycle.
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-- First task is to open the row
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--------------------------------
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state <= s_open_in_1;
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iob_command <= CMD_ACTIVE;
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iob_address <= save_row;
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iob_bank <= save_bank;
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end if;
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--------------------------------------------
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-- Opening the row ready for reads or writes
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--------------------------------------------
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when s_open_in_2 => state <= s_open_in_1;
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when s_open_in_1 =>
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-- still waiting for row to open
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if save_wr = '1' then
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state <= s_write_1;
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iob_dq_hiz <= '0';
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iob_data <= save_data_in(15 downto 0); -- get the DQ bus out of HiZ early
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else
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iob_dq_hiz <= '1';
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state <= s_read_1;
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end if;
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-- we will be ready for a new transaction next cycle!
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ready_for_new <= '1';
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got_transaction <= '0';
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----------------------------------
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-- Processing the read transaction
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----------------------------------
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when s_read_1 =>
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state <= s_read_2;
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iob_command <= CMD_READ;
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iob_address <= save_col;
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iob_bank <= save_bank;
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iob_address(prefresh_cmd) <= '0'; -- A10 actually matters - it selects auto precharge
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-- Schedule reading the data values off the bus
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data_ready_delay(data_ready_delay'high) <= '1';
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-- Set the data masks to read all bytes
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iob_dqm <= (others => '0');
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dqm_sr(1 downto 0) <= (others => '0');
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when s_read_2 =>
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state <= s_read_3;
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if forcing_refresh = '0' and got_transaction = '1' and can_back_to_back = '1' then
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if save_wr = '0' then
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state <= s_read_1;
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ready_for_new <= '1'; -- we will be ready for a new transaction next cycle!
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end if;
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end if;
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when s_read_3 =>
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state <= s_read_4;
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if forcing_refresh = '0' and got_transaction = '1' and can_back_to_back = '1' then
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if save_wr = '0' then
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state <= s_read_1;
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ready_for_new <= '1'; -- we will be ready for a new transaction next cycle!
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end if;
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end if;
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when s_read_4 =>
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state <= s_precharge;
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-- can we do back-to-back read?
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if forcing_refresh = '0' and got_transaction = '1' and can_back_to_back = '1' then
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if save_wr = '0' then
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state <= s_read_1;
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ready_for_new <= '1'; -- we will be ready for a new transaction next cycle!
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else
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state <= s_open_in_2; -- we have to wait for the read data to come back before we swutch the bus into HiZ
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end if;
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end if;
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------------------------------------------------------------------
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-- Processing the write transaction
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-------------------------------------------------------------------
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when s_write_1 =>
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state <= s_write_2;
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iob_command <= CMD_WRITE;
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iob_address <= save_col;
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iob_address(prefresh_cmd) <= '0'; -- A10 actually matters - it selects auto precharge
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iob_bank <= save_bank;
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iob_dqm <= NOT save_byte_enable(1 downto 0);
|
|
dqm_sr(1 downto 0) <= NOT save_byte_enable(3 downto 2);
|
|
iob_data <= save_data_in(15 downto 0);
|
|
iob_data_next <= save_data_in(31 downto 16);
|
|
|
|
when s_write_2 =>
|
|
state <= s_write_3;
|
|
iob_data <= iob_data_next;
|
|
|
|
when s_write_3 => -- must wait tRDL, hence the extra idle state
|
|
iob_dq_hiz <= '1';
|
|
state <= s_precharge;
|
|
|
|
-------------------------------------------------------------------
|
|
-- Closing the row off (this closes all banks)
|
|
-------------------------------------------------------------------
|
|
when s_precharge =>
|
|
state <= s_idle_in_3;
|
|
iob_command <= CMD_PRECHARGE;
|
|
iob_address(prefresh_cmd) <= '1'; -- A10 actually matters - it selects all banks or just one
|
|
|
|
-------------------------------------------------------------------
|
|
-- We should never get here, but if we do then reset the memory
|
|
-------------------------------------------------------------------
|
|
when others =>
|
|
state <= s_startup;
|
|
ready_for_new <= '0';
|
|
startup_refresh_count <= startup_refresh_max-to_unsigned(sdram_startup_cycles,14);
|
|
end case;
|
|
|
|
if reset = '1' then -- Sync reset
|
|
state <= s_startup;
|
|
ready_for_new <= '0';
|
|
startup_refresh_count <= startup_refresh_max-to_unsigned(sdram_startup_cycles,14);
|
|
end if;
|
|
end if;
|
|
end process;
|
|
end Behavioral;
|