From 01b1ecb46714c148f36403420ec91da7d6b64ef8 Mon Sep 17 00:00:00 2001
From: bal <devnull@localhost>
Date: Tue, 16 Apr 1985 15:24:23 +0000
Subject: [PATCH] Bug fixed for pattern 'sti $1 > 4' (ADDREG -> ADDSCR) Bug was
 present since version 1.1

---
 mach/m68k2/cg/table | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/mach/m68k2/cg/table b/mach/m68k2/cg/table
index 2a327bf7..ef2ee0a8 100644
--- a/mach/m68k2/cg/table
+++ b/mach/m68k2/cg/table
@@ -461,7 +461,7 @@ sti $1 == 2 | ADDREG ANY |	remove(MEM_ALL)
 				move(%[2],{IADDREG,%[1]}) | | |
 sti $1 == 4  | ADDREG ANY4 |	remove(MEM_ALL)
 				move(%[2],{IADDREG4,%[1]}) | | |
-sti $1 > 4 | ADDREG |		remove(ALL)
+sti $1 > 4 | ADDSCR |		remove(ALL)
 				allocate(DATAREG4={IMMEDIATE4,$1/2-1})
 				"1:"
 				"move.w (sp)+,(%[1])+"