Bug fixed in pattern sti $1 > 4 (ADDREG -> ADDSCR)
Definition of EM_BSIZE removed.
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@ -33,7 +33,6 @@
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EM_WSIZE = 2
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EM_PSIZE = 4
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EM_BSIZE = 8
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@ -444,7 +443,7 @@ sti $1 == 2 | ADDREG ANY | remove(MEM_ALL)
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move(%[2],{IADDREG,%[1]}) | | |
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sti $1 == 4 | ADDREG ANY4 | remove(MEM_ALL)
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move(%[2],{IADDREG4,%[1]}) | | |
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sti $1 > 4 | ADDREG | remove(ALL)
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sti $1 > 4 | ADDSCR | remove(ALL)
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allocate(DATAREG4={IMMEDIATE4,$1/2-1})
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"1:"
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"move.w (sp)+,(%[1])+"
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