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https://github.com/thead-yocto-mirror/gpu_bxm_4_64-kernel
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591 lines
22 KiB
C
591 lines
22 KiB
C
/**************************************************************************/ /*!
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@File
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@Title Common Device header
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@Copyright Copyright (c) Imagination Technologies Ltd. All Rights Reserved
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@Description Device related function templates and defines
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@License Dual MIT/GPLv2
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The contents of this file are subject to the MIT license as set out below.
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Permission is hereby granted, free of charge, to any person obtaining a copy
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of this software and associated documentation files (the "Software"), to deal
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in the Software without restriction, including without limitation the rights
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to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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copies of the Software, and to permit persons to whom the Software is
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furnished to do so, subject to the following conditions:
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The above copyright notice and this permission notice shall be included in
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all copies or substantial portions of the Software.
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Alternatively, the contents of this file may be used under the terms of
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the GNU General Public License Version 2 ("GPL") in which case the provisions
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of GPL are applicable instead of those above.
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If you wish to allow use of your version of this file only under the terms of
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GPL, and not to allow others to use your version of this file under the terms
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of the MIT license, indicate your decision by deleting the provisions above
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and replace them with the notice and other provisions required by GPL as set
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out in the file called "GPL-COPYING" included in this distribution. If you do
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not delete the provisions above, a recipient may use your version of this file
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under the terms of either the MIT license or GPL.
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This License is also included in this distribution in the file called
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"MIT-COPYING".
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EXCEPT AS OTHERWISE STATED IN A NEGOTIATED AGREEMENT: (A) THE SOFTWARE IS
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PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING
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BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR
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PURPOSE AND NONINFRINGEMENT; AND (B) IN NO EVENT SHALL THE AUTHORS OR
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COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
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IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
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CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
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*/ /***************************************************************************/
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#ifndef DEVICE_H
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#define DEVICE_H
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#include "devicemem_heapcfg.h"
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#include "mmu_common.h"
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#include "ra.h" /* RA_ARENA */
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#include "pvrsrv_device.h"
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#include "sync_checkpoint.h"
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#include "srvkm.h"
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#include "physheap.h"
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#include "sync_internal.h"
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#include "sysinfo.h"
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#include "dllist.h"
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#include "rgx_bvnc_defs_km.h"
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#include "lock.h"
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#include "power.h"
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#if defined(SUPPORT_GPUVIRT_VALIDATION)
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#include "virt_validation_defs.h"
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#endif
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typedef struct _PVRSRV_POWER_DEV_TAG_ *PPVRSRV_POWER_DEV;
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struct SYNC_RECORD;
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struct _CONNECTION_DATA_;
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/*************************************************************************/ /*!
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@Function AllocUFOBlockCallback
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@Description Device specific callback for allocation of a UFO block
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@Input psDeviceNode Pointer to device node to allocate
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the UFO for.
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@Output ppsMemDesc Pointer to pointer for the memdesc of
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the allocation
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@Output pui32SyncAddr FW Base address of the UFO block
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@Output puiSyncPrimBlockSize Size of the UFO block
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@Return PVRSRV_OK if allocation was successful
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*/ /**************************************************************************/
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typedef PVRSRV_ERROR (*AllocUFOBlockCallback)(struct _PVRSRV_DEVICE_NODE_ *psDeviceNode,
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DEVMEM_MEMDESC **ppsMemDesc,
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IMG_UINT32 *pui32SyncAddr,
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IMG_UINT32 *puiSyncPrimBlockSize);
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/*************************************************************************/ /*!
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@Function FreeUFOBlockCallback
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@Description Device specific callback for freeing of a UFO
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@Input psDeviceNode Pointer to device node that the UFO block was
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allocated from.
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@Input psMemDesc Pointer to pointer for the memdesc of the UFO
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block to free.
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*/ /**************************************************************************/
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typedef void (*FreeUFOBlockCallback)(struct _PVRSRV_DEVICE_NODE_ *psDeviceNode,
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DEVMEM_MEMDESC *psMemDesc);
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typedef struct _PVRSRV_DEVICE_IDENTIFIER_
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{
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/* Pdump memory and register bank names */
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IMG_CHAR *pszPDumpDevName;
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IMG_CHAR *pszPDumpRegName;
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/* Under Linux, this is the minor number of RenderNode corresponding to this Device */
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IMG_INT32 i32OsDeviceID;
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/* Services layer enumeration of the device used in pvrdebug */
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IMG_UINT32 ui32InternalID;
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} PVRSRV_DEVICE_IDENTIFIER;
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typedef struct _DEVICE_MEMORY_INFO_
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{
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/* Heap count. Doesn't include additional heaps from PVRSRVCreateDeviceMemHeap */
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IMG_UINT32 ui32HeapCount;
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/* Blueprints for creating new device memory contexts */
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IMG_UINT32 uiNumHeapConfigs;
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DEVMEM_HEAP_CONFIG *psDeviceMemoryHeapConfigArray;
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DEVMEM_HEAP_BLUEPRINT *psDeviceMemoryHeap;
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} DEVICE_MEMORY_INFO;
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typedef struct _PG_HANDLE_
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{
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union
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{
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void *pvHandle;
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IMG_UINT64 ui64Handle;
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}u;
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/* The allocation order is log2 value of the number of pages to allocate.
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* As such this is a correspondingly small value. E.g, for order 4 we
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* are talking 2^4 * PAGE_SIZE contiguous allocation.
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* DevPxAlloc API does not need to support orders higher than 4.
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*/
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#if defined(SUPPORT_GPUVIRT_VALIDATION)
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IMG_BYTE uiOrder; /* Order of the corresponding allocation */
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IMG_BYTE uiOSid; /* OSid to use for allocation arena.
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* Connection-specific. */
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IMG_BYTE uiPad1,
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uiPad2; /* Spare */
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#else
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IMG_BYTE uiOrder; /* Order of the corresponding allocation */
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IMG_BYTE uiPad1,
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uiPad2,
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uiPad3; /* Spare */
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#endif
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} PG_HANDLE;
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#define MMU_BAD_PHYS_ADDR (0xbadbad00badULL)
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#define DUMMY_PAGE ("DUMMY_PAGE")
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#define DEV_ZERO_PAGE ("DEV_ZERO_PAGE")
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#define PVR_DUMMY_PAGE_INIT_VALUE (0x0)
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#define PVR_ZERO_PAGE_INIT_VALUE (0x0)
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typedef struct __DEFAULT_PAGE__
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{
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/*Page handle for the page allocated (UMA/LMA)*/
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PG_HANDLE sPageHandle;
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POS_LOCK psPgLock;
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ATOMIC_T atRefCounter;
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/*Default page size in terms of log2 */
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IMG_UINT32 ui32Log2PgSize;
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IMG_UINT64 ui64PgPhysAddr;
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#if defined(PDUMP)
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IMG_HANDLE hPdumpPg;
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#endif
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} PVRSRV_DEF_PAGE;
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typedef enum _PVRSRV_DEVICE_STATE_
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{
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PVRSRV_DEVICE_STATE_UNDEFINED = 0,
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PVRSRV_DEVICE_STATE_INIT,
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PVRSRV_DEVICE_STATE_ACTIVE,
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PVRSRV_DEVICE_STATE_DEINIT,
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PVRSRV_DEVICE_STATE_BAD,
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} PVRSRV_DEVICE_STATE;
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typedef enum _PVRSRV_DEVICE_HEALTH_STATUS_
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{
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PVRSRV_DEVICE_HEALTH_STATUS_UNDEFINED = 0,
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PVRSRV_DEVICE_HEALTH_STATUS_OK,
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PVRSRV_DEVICE_HEALTH_STATUS_NOT_RESPONDING,
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PVRSRV_DEVICE_HEALTH_STATUS_DEAD,
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PVRSRV_DEVICE_HEALTH_STATUS_FAULT
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} PVRSRV_DEVICE_HEALTH_STATUS;
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typedef enum _PVRSRV_DEVICE_HEALTH_REASON_
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{
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PVRSRV_DEVICE_HEALTH_REASON_NONE = 0,
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PVRSRV_DEVICE_HEALTH_REASON_ASSERTED,
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PVRSRV_DEVICE_HEALTH_REASON_POLL_FAILING,
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PVRSRV_DEVICE_HEALTH_REASON_TIMEOUTS,
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PVRSRV_DEVICE_HEALTH_REASON_QUEUE_CORRUPT,
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PVRSRV_DEVICE_HEALTH_REASON_QUEUE_STALLED,
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PVRSRV_DEVICE_HEALTH_REASON_IDLING,
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PVRSRV_DEVICE_HEALTH_REASON_RESTARTING,
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PVRSRV_DEVICE_HEALTH_REASON_MISSING_INTERRUPTS
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} PVRSRV_DEVICE_HEALTH_REASON;
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typedef enum _PVRSRV_DEVICE_DEBUG_DUMP_STATUS_
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{
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PVRSRV_DEVICE_DEBUG_DUMP_NONE = 0,
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PVRSRV_DEVICE_DEBUG_DUMP_CAPTURE
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} PVRSRV_DEVICE_DEBUG_DUMP_STATUS;
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typedef struct _MMU_PX_SETUP_
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{
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#if defined(SUPPORT_GPUVIRT_VALIDATION)
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PVRSRV_ERROR (*pfnDevPxAllocGPV)(struct _PVRSRV_DEVICE_NODE_ *psDevNode, size_t uiSize,
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PG_HANDLE *psMemHandle, IMG_DEV_PHYADDR *psDevPAddr,
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IMG_UINT32 ui32OSid, IMG_PID uiPid);
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#endif
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PVRSRV_ERROR (*pfnDevPxAlloc)(struct _PVRSRV_DEVICE_NODE_ *psDevNode, size_t uiSize,
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PG_HANDLE *psMemHandle, IMG_DEV_PHYADDR *psDevPAddr,
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IMG_PID uiPid);
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void (*pfnDevPxFree)(struct _PVRSRV_DEVICE_NODE_ *psDevNode, PG_HANDLE *psMemHandle);
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PVRSRV_ERROR (*pfnDevPxMap)(struct _PVRSRV_DEVICE_NODE_ *psDevNode, PG_HANDLE *pshMemHandle,
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size_t uiSize, IMG_DEV_PHYADDR *psDevPAddr,
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void **pvPtr);
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void (*pfnDevPxUnMap)(struct _PVRSRV_DEVICE_NODE_ *psDevNode,
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PG_HANDLE *psMemHandle, void *pvPtr);
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PVRSRV_ERROR (*pfnDevPxClean)(struct _PVRSRV_DEVICE_NODE_ *psDevNode,
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PG_HANDLE *pshMemHandle,
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IMG_UINT32 uiOffset,
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IMG_UINT32 uiLength);
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IMG_UINT32 uiMMUPxLog2AllocGran;
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RA_ARENA *psPxRA;
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} MMU_PX_SETUP;
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#ifndef DI_GROUP_DEFINED
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#define DI_GROUP_DEFINED
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typedef struct DI_GROUP DI_GROUP;
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#endif
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#ifndef DI_ENTRY_DEFINED
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#define DI_ENTRY_DEFINED
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typedef struct DI_ENTRY DI_ENTRY;
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#endif
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typedef struct _PVRSRV_DEVICE_DEBUG_INFO_
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{
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DI_GROUP *psGroup;
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DI_ENTRY *psDumpDebugEntry;
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#ifdef SUPPORT_RGX
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DI_ENTRY *psFWTraceEntry;
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#if defined(SUPPORT_VALIDATION) || defined(SUPPORT_RISCV_GDB)
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DI_ENTRY *psRiscvDmiDIEntry;
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IMG_UINT64 ui64RiscvDmi;
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#endif
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#endif /* SUPPORT_RGX */
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#ifdef SUPPORT_VALIDATION
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DI_ENTRY *psRGXRegsEntry;
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#endif /* SUPPORT_VALIDATION */
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#ifdef SUPPORT_POWER_VALIDATION_VIA_DEBUGFS
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DI_ENTRY *psPowMonEntry;
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#endif
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#ifdef SUPPORT_POWER_SAMPLING_VIA_DEBUGFS
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DI_ENTRY *psPowerDataEntry;
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#endif
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} PVRSRV_DEVICE_DEBUG_INFO;
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#if defined(PVRSRV_DEBUG_LISR_EXECUTION)
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#define RGX_LISR_INIT (0U)
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#define RGX_LISR_DEVICE_NOT_POWERED (1U)
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#define RGX_LISR_NOT_TRIGGERED_BY_HW (2U)
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#define RGX_LISR_FW_IRQ_COUNTER_NOT_UPDATED (3U)
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#define RGX_LISR_PROCESSED (4U)
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typedef IMG_UINT32 LISR_STATUS;
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typedef struct _LISR_EXECUTION_INFO_
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{
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/* status of last LISR invocation */
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LISR_STATUS ui32Status;
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/* snapshot from the last LISR invocation */
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#if defined(RGX_FW_IRQ_OS_COUNTERS)
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IMG_UINT32 aui32InterruptCountSnapshot[RGX_NUM_OS_SUPPORTED];
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#else
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IMG_UINT32 aui32InterruptCountSnapshot[RGXFW_THREAD_NUM];
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#endif
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/* time of the last LISR invocation */
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IMG_UINT64 ui64Clockns;
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} LISR_EXECUTION_INFO;
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#define UPDATE_LISR_DBG_STATUS(status) psDeviceNode->sLISRExecutionInfo.ui32Status = (status)
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#define UPDATE_LISR_DBG_SNAPSHOT(idx, val) psDeviceNode->sLISRExecutionInfo.aui32InterruptCountSnapshot[idx] = (val)
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#define UPDATE_LISR_DBG_TIMESTAMP() psDeviceNode->sLISRExecutionInfo.ui64Clockns = OSClockns64()
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#define UPDATE_LISR_DBG_COUNTER() psDeviceNode->ui64nLISR++
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#define UPDATE_MISR_DBG_COUNTER() psDeviceNode->ui64nMISR++
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#else
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#define UPDATE_LISR_DBG_STATUS(status)
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#define UPDATE_LISR_DBG_SNAPSHOT(idx, val)
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#define UPDATE_LISR_DBG_TIMESTAMP()
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#define UPDATE_LISR_DBG_COUNTER()
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#define UPDATE_MISR_DBG_COUNTER()
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#endif /* defined(PVRSRV_DEBUG_LISR_EXECUTION) */
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typedef struct _PVRSRV_DEVICE_NODE_
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{
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PVRSRV_DEVICE_IDENTIFIER sDevId;
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PVRSRV_DEVICE_STATE eDevState;
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PVRSRV_DEVICE_FABRIC_TYPE eDevFabricType;
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ATOMIC_T eHealthStatus; /* Holds values from PVRSRV_DEVICE_HEALTH_STATUS */
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ATOMIC_T eHealthReason; /* Holds values from PVRSRV_DEVICE_HEALTH_REASON */
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ATOMIC_T eDebugDumpRequested; /* Holds values from PVRSRV_DEVICE_DEBUG_DUMP_STATUS */
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IMG_HANDLE *hDebugTable;
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/* device specific MMU attributes */
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MMU_DEVICEATTRIBS *psMMUDevAttrs;
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/* Device specific MMU firmware attributes, used only in some devices */
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MMU_DEVICEATTRIBS *psFirmwareMMUDevAttrs;
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MMU_PX_SETUP sDevMMUPxSetup;
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/* lock for power state transitions */
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POS_LOCK hPowerLock;
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IMG_PID uiPwrLockOwnerPID; /* Only valid between lock and corresponding unlock
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operations of hPowerLock */
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/* current system device power state */
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PVRSRV_SYS_POWER_STATE eCurrentSysPowerState;
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PPVRSRV_POWER_DEV psPowerDev;
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/* multicore configuration information */
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IMG_UINT32 ui32MultiCoreNumCores; /* total cores primary + secondaries. 0 for non-multi core */
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IMG_UINT32 ui32MultiCorePrimaryId; /* primary core id for this device */
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IMG_UINT64 *pui64MultiCoreCapabilities; /* capabilities for each core */
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/*
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callbacks the device must support:
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*/
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PVRSRV_ERROR (*pfnDevSLCFlushRange)(struct _PVRSRV_DEVICE_NODE_ *psDevNode,
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MMU_CONTEXT *psMMUContext,
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IMG_DEV_VIRTADDR sDevVAddr,
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IMG_DEVMEM_SIZE_T uiSize,
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IMG_BOOL bInvalidate);
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PVRSRV_ERROR (*pfnInvalFBSCTable)(struct _PVRSRV_DEVICE_NODE_ *psDevNode,
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MMU_CONTEXT *psMMUContext,
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IMG_UINT64 ui64FBSCEntries);
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PVRSRV_ERROR (*pfnValidateOrTweakPhysAddrs)(struct _PVRSRV_DEVICE_NODE_ *psDevNode,
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MMU_DEVICEATTRIBS *psDevAttrs,
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IMG_UINT64 *pui64Addr);
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void (*pfnMMUCacheInvalidate)(struct _PVRSRV_DEVICE_NODE_ *psDevNode,
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MMU_CONTEXT *psMMUContext,
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MMU_LEVEL eLevel,
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IMG_BOOL bUnmap);
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PVRSRV_ERROR (*pfnMMUCacheInvalidateKick)(struct _PVRSRV_DEVICE_NODE_ *psDevNode,
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IMG_UINT32 *pui32NextMMUInvalidateUpdate);
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IMG_UINT32 (*pfnMMUCacheGetInvalidateCounter)(struct _PVRSRV_DEVICE_NODE_ *psDevNode);
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void (*pfnDumpDebugInfo)(struct _PVRSRV_DEVICE_NODE_ *psDevNode);
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PVRSRV_ERROR (*pfnUpdateHealthStatus)(struct _PVRSRV_DEVICE_NODE_ *psDevNode,
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IMG_BOOL bIsTimerPoll);
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#if defined(SUPPORT_AUTOVZ)
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void (*pfnUpdateAutoVzWatchdog)(struct _PVRSRV_DEVICE_NODE_ *psDevNode);
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#endif
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PVRSRV_ERROR (*pfnValidationGPUUnitsPowerChange)(struct _PVRSRV_DEVICE_NODE_ *psDevNode, IMG_UINT32 ui32NewState);
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PVRSRV_ERROR (*pfnResetHWRLogs)(struct _PVRSRV_DEVICE_NODE_ *psDevNode);
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PVRSRV_ERROR (*pfnVerifyBVNC)(struct _PVRSRV_DEVICE_NODE_ *psDevNode, IMG_UINT64 ui64GivenBVNC, IMG_UINT64 ui64CoreIdMask);
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/* Method to drain device HWPerf packets from firmware buffer to host buffer */
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PVRSRV_ERROR (*pfnServiceHWPerf)(struct _PVRSRV_DEVICE_NODE_ *psDevNode);
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PVRSRV_ERROR (*pfnDeviceVersionString)(struct _PVRSRV_DEVICE_NODE_ *psDevNode, IMG_CHAR **ppszVersionString);
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PVRSRV_ERROR (*pfnDeviceClockSpeed)(struct _PVRSRV_DEVICE_NODE_ *psDevNode, IMG_PUINT32 pui32RGXClockSpeed);
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PVRSRV_ERROR (*pfnSoftReset)(struct _PVRSRV_DEVICE_NODE_ *psDevNode, IMG_UINT64 ui64ResetValue1, IMG_UINT64 ui64ResetValue2);
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PVRSRV_ERROR (*pfnAlignmentCheck)(struct _PVRSRV_DEVICE_NODE_ *psDevNode, IMG_UINT32 ui32FWAlignChecksSize, IMG_UINT32 aui32FWAlignChecks[]);
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IMG_BOOL (*pfnCheckDeviceFeature)(struct _PVRSRV_DEVICE_NODE_ *psDevNode, IMG_UINT64 ui64FeatureMask);
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IMG_INT32 (*pfnGetDeviceFeatureValue)(struct _PVRSRV_DEVICE_NODE_ *psDevNode, enum _RGX_FEATURE_WITH_VALUE_INDEX_ eFeatureIndex);
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PVRSRV_ERROR (*pfnGetMultiCoreInfo)(struct _PVRSRV_DEVICE_NODE_ *psDevNode, IMG_UINT32 ui32CapsSize,
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IMG_UINT32 *pui32NumCores, IMG_UINT64 *pui64Caps);
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IMG_BOOL (*pfnHasFBCDCVersion31)(struct _PVRSRV_DEVICE_NODE_ *psDevNode);
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MMU_DEVICEATTRIBS* (*pfnGetMMUDeviceAttributes)(struct _PVRSRV_DEVICE_NODE_ *psDevNode, IMG_BOOL bKernelMemoryCtx);
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PVRSRV_DEVICE_CONFIG *psDevConfig;
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/* device post-finalise compatibility check */
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PVRSRV_ERROR (*pfnInitDeviceCompatCheck) (struct _PVRSRV_DEVICE_NODE_*);
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/* initialise device-specific physheaps */
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PVRSRV_ERROR (*pfnPhysMemDeviceHeapsInit) (struct _PVRSRV_DEVICE_NODE_ *);
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/* initialise fw mmu, if FW not using GPU mmu, NULL otherwise. */
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PVRSRV_ERROR (*pfnFwMMUInit) (struct _PVRSRV_DEVICE_NODE_ *);
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/* information about the device's address space and heaps */
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DEVICE_MEMORY_INFO sDevMemoryInfo;
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/* device's shared-virtual-memory heap max virtual address */
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IMG_UINT64 ui64GeneralSVMHeapTopVA;
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ATOMIC_T iNumClockSpeedChanges;
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/* private device information */
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void *pvDevice;
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#if defined(SUPPORT_GPUVIRT_VALIDATION)
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RA_ARENA *psOSSharedArena;
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RA_ARENA *psOSidSubArena[GPUVIRT_VALIDATION_NUM_OS];
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/* Number of supported OSid for this device node given available memory */
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IMG_UINT32 ui32NumOSId;
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#endif
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/* FW_MAIN, FW_CONFIG and FW_GUEST heaps. Should be part of registered heaps? */
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PHYS_HEAP *psFWMainPhysHeap;
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PHYS_HEAP *psFWCfgPhysHeap;
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PHYS_HEAP *apsFWPremapPhysHeap[RGX_NUM_OS_SUPPORTED];
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|
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IMG_UINT32 ui32RegisteredPhysHeaps;
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PHYS_HEAP **papsRegisteredPhysHeaps;
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|
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/* PHYS_HEAP Mapping table to the platform's physical memory heap(s)
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|
* used by this device. The physical heaps are created based on
|
|
* the PHYS_HEAP_CONFIG data from the platform's system layer at device
|
|
* creation time.
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|
*
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* Contains PVRSRV_PHYS_HEAP_LAST entries for all the possible physical heaps allowed in the design.
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* It allows the system layer PhysHeaps for the device to be identified for use in creating new PMRs.
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* See PhysHeapCreatePMR()
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|
*/
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PHYS_HEAP *apsPhysHeap[PVRSRV_PHYS_HEAP_LAST];
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IMG_UINT32 ui32UserAllocHeapCount;
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|
|
|
/* RA reserved for storing the MMU mappings of firmware.
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|
* The memory backing up this RA must persist between driver or OS reboots */
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|
RA_ARENA *psFwMMUReservedMemArena;
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|
|
|
/* Flag indicating if the firmware has been initialised during the
|
|
* 1st boot of the Host driver according to the AutoVz life-cycle. */
|
|
IMG_BOOL bAutoVzFwIsUp;
|
|
|
|
struct _PVRSRV_DEVICE_NODE_ *psNext;
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|
struct _PVRSRV_DEVICE_NODE_ **ppsThis;
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|
|
|
/* Functions for notification about memory contexts */
|
|
PVRSRV_ERROR (*pfnRegisterMemoryContext)(struct _PVRSRV_DEVICE_NODE_ *psDeviceNode,
|
|
MMU_CONTEXT *psMMUContext,
|
|
IMG_HANDLE *hPrivData);
|
|
void (*pfnUnregisterMemoryContext)(IMG_HANDLE hPrivData);
|
|
|
|
/* Functions for allocation/freeing of UFOs */
|
|
AllocUFOBlockCallback pfnAllocUFOBlock; /*!< Callback for allocation of a block of UFO memory */
|
|
FreeUFOBlockCallback pfnFreeUFOBlock; /*!< Callback for freeing of a block of UFO memory */
|
|
|
|
IMG_HANDLE hSyncServerRecordNotify;
|
|
POS_LOCK hSyncServerRecordLock;
|
|
IMG_UINT32 ui32SyncServerRecordCount;
|
|
IMG_UINT32 ui32SyncServerRecordCountHighWatermark;
|
|
DLLIST_NODE sSyncServerRecordList;
|
|
struct SYNC_RECORD *apsSyncServerRecordsFreed[PVRSRV_FULL_SYNC_TRACKING_HISTORY_LEN];
|
|
IMG_UINT32 uiSyncServerRecordFreeIdx;
|
|
|
|
IMG_HANDLE hSyncCheckpointRecordNotify;
|
|
POS_LOCK hSyncCheckpointRecordLock;
|
|
IMG_UINT32 ui32SyncCheckpointRecordCount;
|
|
IMG_UINT32 ui32SyncCheckpointRecordCountHighWatermark;
|
|
DLLIST_NODE sSyncCheckpointRecordList;
|
|
struct SYNC_CHECKPOINT_RECORD *apsSyncCheckpointRecordsFreed[PVRSRV_FULL_SYNC_TRACKING_HISTORY_LEN];
|
|
IMG_UINT32 uiSyncCheckpointRecordFreeIdx;
|
|
|
|
IMG_HANDLE hSyncCheckpointNotify;
|
|
POS_SPINLOCK hSyncCheckpointListLock; /*!< Protects sSyncCheckpointSyncsList */
|
|
DLLIST_NODE sSyncCheckpointSyncsList;
|
|
|
|
PSYNC_CHECKPOINT_CONTEXT hSyncCheckpointContext;
|
|
PSYNC_PRIM_CONTEXT hSyncPrimContext;
|
|
|
|
/* With this sync-prim we make sure the MMU cache is flushed
|
|
* before we free the page table memory */
|
|
PVRSRV_CLIENT_SYNC_PRIM *psMMUCacheSyncPrim;
|
|
IMG_UINT32 ui32NextMMUInvalidateUpdate;
|
|
|
|
IMG_HANDLE hCmdCompNotify;
|
|
IMG_HANDLE hDbgReqNotify;
|
|
IMG_HANDLE hAppHintDbgReqNotify;
|
|
|
|
PVRSRV_DEF_PAGE sDummyPage;
|
|
PVRSRV_DEF_PAGE sDevZeroPage;
|
|
|
|
POSWR_LOCK hMemoryContextPageFaultNotifyListLock;
|
|
DLLIST_NODE sMemoryContextPageFaultNotifyListHead;
|
|
|
|
/* System DMA capability */
|
|
IMG_BOOL bHasSystemDMA;
|
|
IMG_HANDLE hDmaTxChan;
|
|
IMG_HANDLE hDmaRxChan;
|
|
|
|
#if defined(PDUMP)
|
|
/*
|
|
* FBC clear color register default value to use.
|
|
*/
|
|
IMG_UINT64 ui64FBCClearColour;
|
|
|
|
/* Device-level callback which is called when pdump.exe starts.
|
|
* Should be implemented in device-specific init code, e.g. rgxinit.c
|
|
*/
|
|
PVRSRV_ERROR (*pfnPDumpInitDevice)(struct _PVRSRV_DEVICE_NODE_ *psDeviceNode);
|
|
/* device-level callback to return pdump ID associated to a memory context */
|
|
IMG_UINT32 (*pfnMMUGetContextID)(IMG_HANDLE hDevMemContext);
|
|
|
|
IMG_UINT8 *pui8DeferredSyncCPSignal; /*! Deferred fence events buffer */
|
|
|
|
IMG_UINT16 ui16SyncCPReadIdx; /*! Read index in the above deferred fence events buffer */
|
|
|
|
IMG_UINT16 ui16SyncCPWriteIdx; /*! Write index in the above deferred fence events buffer */
|
|
|
|
POS_LOCK hSyncCheckpointSignalLock; /*! Guards data shared between an sleepable-contexts */
|
|
|
|
void *pvSyncCPMISR; /*! MISR to emit pending/deferred fence signals */
|
|
|
|
void *hTransition; /*!< SyncCheckpoint PdumpTransition Cookie */
|
|
|
|
DLLIST_NODE sSyncCheckpointContextListHead; /*!< List head for the sync chkpt contexts */
|
|
|
|
POS_LOCK hSyncCheckpointContextListLock; /*! lock for accessing sync chkpt contexts list */
|
|
|
|
#endif
|
|
|
|
#if defined(SUPPORT_VALIDATION)
|
|
POS_LOCK hValidationLock;
|
|
#endif
|
|
|
|
POS_LOCK hConnectionsLock; /*!< Lock protecting sConnections */
|
|
DLLIST_NODE sConnections; /*!< The list of currently active connection objects for this device node */
|
|
#if defined(PVRSRV_DEBUG_LISR_EXECUTION)
|
|
LISR_EXECUTION_INFO sLISRExecutionInfo; /*!< Information about the last execution of the LISR */
|
|
IMG_UINT64 ui64nLISR; /*!< Number of LISR calls seen */
|
|
IMG_UINT64 ui64nMISR; /*!< Number of MISR calls made */
|
|
#endif
|
|
|
|
PVRSRV_DEVICE_DEBUG_INFO sDebugInfo;
|
|
} PVRSRV_DEVICE_NODE;
|
|
|
|
/*
|
|
* Macros to be used instead of calling directly the pfns since these macros
|
|
* will expand the feature passed as argument into the bitmask/index to work
|
|
* with the macros defined in rgx_bvnc_defs_km.h
|
|
*/
|
|
#define PVRSRV_IS_FEATURE_SUPPORTED(psDevNode, Feature) \
|
|
psDevNode->pfnCheckDeviceFeature(psDevNode, RGX_FEATURE_##Feature##_BIT_MASK)
|
|
#define PVRSRV_GET_DEVICE_FEATURE_VALUE(psDevNode, Feature) \
|
|
psDevNode->pfnGetDeviceFeatureValue(psDevNode, RGX_FEATURE_##Feature##_IDX)
|
|
|
|
PVRSRV_ERROR PVRSRVDeviceFinalise(PVRSRV_DEVICE_NODE *psDeviceNode,
|
|
IMG_BOOL bInitSuccessful);
|
|
|
|
PVRSRV_ERROR PVRSRVDevInitCompatCheck(PVRSRV_DEVICE_NODE *psDeviceNode);
|
|
|
|
PVRSRV_ERROR RGXClientConnectCompatCheck_ClientAgainstFW(PVRSRV_DEVICE_NODE * psDeviceNode, IMG_UINT32 ui32ClientBuildOptions);
|
|
|
|
|
|
#endif /* DEVICE_H */
|
|
|
|
/******************************************************************************
|
|
End of file (device.h)
|
|
******************************************************************************/
|