From 230631d0f03367ec0737aefd765396cc8c9cbf04 Mon Sep 17 00:00:00 2001 From: Khem Raj Date: Fri, 9 Mar 2018 02:29:03 -0800 Subject: [PATCH] glibc: Drop glibc 2.26 bbappends Signed-off-by: Khem Raj --- ...ext_t-sigcontext-namespace-for-riscv.patch | 95 -------------- ...ecute-preconfiure-only-for-risv-targ.patch | 116 ------------------ .../glibc/glibc-initial_2.26.bbappend | 8 -- recipes-core/glibc/glibc_2.26.bbappend | 11 -- 4 files changed, 230 deletions(-) delete mode 100644 recipes-core/glibc/files/0001-Fix-mcontext_t-sigcontext-namespace-for-riscv.patch delete mode 100644 recipes-core/glibc/files/0001-sysdeps-riscv-Execute-preconfiure-only-for-risv-targ.patch delete mode 100644 recipes-core/glibc/glibc-initial_2.26.bbappend delete mode 100644 recipes-core/glibc/glibc_2.26.bbappend diff --git a/recipes-core/glibc/files/0001-Fix-mcontext_t-sigcontext-namespace-for-riscv.patch b/recipes-core/glibc/files/0001-Fix-mcontext_t-sigcontext-namespace-for-riscv.patch deleted file mode 100644 index cb08b20..0000000 --- a/recipes-core/glibc/files/0001-Fix-mcontext_t-sigcontext-namespace-for-riscv.patch +++ /dev/null @@ -1,95 +0,0 @@ -From ac9a996765adc0df6da315b23f72b9033764ed1d Mon Sep 17 00:00:00 2001 -From: Khem Raj -Date: Wed, 4 Oct 2017 23:26:06 -0700 -Subject: [PATCH] Fix mcontext_t sigcontext namespace for riscv - -implement bug 21457 for riscv as well - -Inclusion of by is removedi - -on riscv Where mcontext_t was typedefed to struct sigcontext, the contents of -struct sigcontext are inserted (with appropriate namespace handling to -prefix fields with __ when __USE_MISC is not defined) -definition of struct sigcontext comes from glibc headers - -Signed-off-by: Khem Raj ---- - sysdeps/unix/sysv/linux/riscv/register-dump.h | 2 +- - sysdeps/unix/sysv/linux/riscv/sigcontextinfo.h | 2 +- - sysdeps/unix/sysv/linux/riscv/sys/ucontext.h | 20 ++++++++++++++------ - 3 files changed, 16 insertions(+), 8 deletions(-) - -diff --git a/sysdeps/unix/sysv/linux/riscv/register-dump.h b/sysdeps/unix/sysv/linux/riscv/register-dump.h -index 188a1a9d66..8d5617b49e 100644 ---- a/sysdeps/unix/sysv/linux/riscv/register-dump.h -+++ b/sysdeps/unix/sysv/linux/riscv/register-dump.h -@@ -32,7 +32,7 @@ hexvalue (unsigned long int value, char *buf, size_t len) - #define REGDUMP_PER_LINE (80 / (__WORDSIZE/4 + 4)) - - static void --register_dump (int fd, struct ucontext *ctx) -+register_dump (int fd, ucontext_t *ctx) - { - int i; - char regvalue[__WORDSIZE/4 + 1]; -diff --git a/sysdeps/unix/sysv/linux/riscv/sigcontextinfo.h b/sysdeps/unix/sysv/linux/riscv/sigcontextinfo.h -index 365de75581..dba9f76f1a 100644 ---- a/sysdeps/unix/sysv/linux/riscv/sigcontextinfo.h -+++ b/sysdeps/unix/sysv/linux/riscv/sigcontextinfo.h -@@ -18,7 +18,7 @@ - - #include - --#define SIGCONTEXT siginfo_t *_si, struct ucontext * -+#define SIGCONTEXT siginfo_t *_si, ucontext_t * - #define SIGCONTEXT_EXTRA_ARGS _si, - #define GET_PC(ctx) ((void *) ctx->uc_mcontext.gregs[REG_PC]) - #define GET_FRAME(ctx) ((void *) ctx->uc_mcontext.gregs[REG_S0]) -diff --git a/sysdeps/unix/sysv/linux/riscv/sys/ucontext.h b/sysdeps/unix/sysv/linux/riscv/sys/ucontext.h -index 693b6f7b1b..2bc22cba73 100644 ---- a/sysdeps/unix/sysv/linux/riscv/sys/ucontext.h -+++ b/sysdeps/unix/sysv/linux/riscv/sys/ucontext.h -@@ -24,9 +24,14 @@ - #include - - #include --#include - #include - -+#ifdef __USE_MISC -+# define __ctx(fld) fld -+#else -+# define __ctx(fld) __ ## fld -+#endif -+ - #ifdef __USE_MISC - - #define NGREG 32 -@@ -47,16 +52,19 @@ typedef greg_t gregset_t[NGREG]; - /* Container for floating-point state. */ - typedef union __riscv_fp_state fpregset_t; - --/* Context to describe whole processor state. */ --typedef struct sigcontext mcontext_t; -- - #endif -+typedef struct mcontext_t -+ { -+ /* gregs[0] holds the program counter. */ -+ unsigned long __ctx(gregs)[32]; -+ unsigned long long __ctx(fpregs)[66] __attribute__((aligned(16))); -+ } mcontext_t; - - /* Userlevel context. */ --typedef struct ucontext -+typedef struct ucontext_t - { - unsigned long int uc_flags; -- struct ucontext *uc_link; -+ struct ucontext_t *uc_link; - stack_t uc_stack; - sigset_t uc_sigmask; - mcontext_t uc_mcontext; --- -2.14.2 - diff --git a/recipes-core/glibc/files/0001-sysdeps-riscv-Execute-preconfiure-only-for-risv-targ.patch b/recipes-core/glibc/files/0001-sysdeps-riscv-Execute-preconfiure-only-for-risv-targ.patch deleted file mode 100644 index 6f5773f..0000000 --- a/recipes-core/glibc/files/0001-sysdeps-riscv-Execute-preconfiure-only-for-risv-targ.patch +++ /dev/null @@ -1,116 +0,0 @@ -From 7eac5d7aba0ea86e4393eb75a995423946375dd9 Mon Sep 17 00:00:00 2001 -From: Khem Raj -Date: Tue, 3 Oct 2017 12:37:01 -0700 -Subject: [PATCH] sysdeps/riscv: Execute preconfiure only for risv target - -Signed-off-by: Khem Raj ---- - sysdeps/riscv/preconfigure | 93 ++++++++++++++++++++++++---------------------- - 1 file changed, 48 insertions(+), 45 deletions(-) - -diff --git a/sysdeps/riscv/preconfigure b/sysdeps/riscv/preconfigure -index 43e2a4fac0..da4afb278d 100644 ---- a/sysdeps/riscv/preconfigure -+++ b/sysdeps/riscv/preconfigure -@@ -1,50 +1,53 @@ --xlen=`$CC $CFLAGS $CPPFLAGS -E -dM -xc /dev/null | sed -n 's/^#define __riscv_xlen \(.*\)/\1/p'` --flen=`$CC $CFLAGS $CPPFLAGS -E -dM -xc /dev/null | sed -n 's/^#define __riscv_flen \(.*\)/\1/p'` --float_abi=`$CC $CFLAGS $CPPFLAGS -E -dM -xc /dev/null | sed -n 's/^#define __riscv_float_abi_\([^ ]*\) .*/\1/p'` -+case "$machine" in -+riscv*) -+ xlen=`$CC $CFLAGS $CPPFLAGS -E -dM -xc /dev/null | sed -n 's/^#define __riscv_xlen \(.*\)/\1/p'` -+ flen=`$CC $CFLAGS $CPPFLAGS -E -dM -xc /dev/null | sed -n 's/^#define __riscv_flen \(.*\)/\1/p'` -+ float_abi=`$CC $CFLAGS $CPPFLAGS -E -dM -xc /dev/null | sed -n 's/^#define __riscv_float_abi_\([^ ]*\) .*/\1/p'` - --case "$xlen" in --32 | 64) -- ;; --*) -- echo "Unable to determine XLEN" >&2 -- exit 1 -- ;; --esac -+ case "$xlen" in -+ 32 | 64) -+ ;; -+ *) -+ echo "Unable to determine XLEN" >&2 -+ exit 1 -+ ;; -+ esac - --case "$flen" in --64) -- float_machine=rvd -- ;; --32) -- float_machine=rvf -- ;; --"") -- float_machine= -- ;; --*) -- echo "Unable to determine FLEN" >&2 -- exit 1 -- ;; --esac -+ case "$flen" in -+ 64) -+ float_machine=rvd -+ ;; -+ 32) -+ float_machine=rvf -+ ;; -+ "") -+ float_machine= -+ ;; -+ *) -+ echo "Unable to determine FLEN" >&2 -+ exit 1 -+ ;; -+ esac - --case "$float_abi" in --soft) -- abi_flen=0 -- ;; --single) -- abi_flen=32 -- ;; --double) -- abi_flen=64 -- ;; --*) -- echo "Unable to determine floating-point ABI" >&2 -- exit 1 -- ;; --esac -+ case "$float_abi" in -+ soft) -+ abi_flen=0 -+ ;; -+ single) -+ abi_flen=32 -+ ;; -+ double) -+ abi_flen=64 -+ ;; -+ *) -+ echo "Unable to determine floating-point ABI" >&2 -+ exit 1 -+ ;; -+ esac - --base_machine=riscv --machine=riscv/rv$xlen/$float_machine -+ base_machine=riscv -+ machine=riscv/rv$xlen/$float_machine - --$as_echo "#define RISCV_ABI_XLEN $xlen" >>confdefs.h --$as_echo "#define RISCV_ABI_FLEN $abi_flen" >>confdefs.h -+ $as_echo "#define RISCV_ABI_XLEN $xlen" >>confdefs.h -+ $as_echo "#define RISCV_ABI_FLEN $abi_flen" >>confdefs.h -+esac --- -2.14.2 - diff --git a/recipes-core/glibc/glibc-initial_2.26.bbappend b/recipes-core/glibc/glibc-initial_2.26.bbappend deleted file mode 100644 index 2bebcda..0000000 --- a/recipes-core/glibc/glibc-initial_2.26.bbappend +++ /dev/null @@ -1,8 +0,0 @@ -FILESEXTRAPATHS_prepend := "${THISDIR}/files:" -GLIBC_GIT_URI = "git://github.com/riscv/riscv-glibc" -SRCBRANCH = "riscv-glibc-${PV}" -SRCREV = "8259af85ae3988d1c1f5f3d7c9499f0a18153ec9" - -SRC_URI += "file://0001-sysdeps-riscv-Execute-preconfiure-only-for-risv-targ.patch \ - file://0001-Fix-mcontext_t-sigcontext-namespace-for-riscv.patch \ - " diff --git a/recipes-core/glibc/glibc_2.26.bbappend b/recipes-core/glibc/glibc_2.26.bbappend deleted file mode 100644 index 3c9c75c..0000000 --- a/recipes-core/glibc/glibc_2.26.bbappend +++ /dev/null @@ -1,11 +0,0 @@ -FILESEXTRAPATHS_prepend := "${THISDIR}/files:" -GLIBC_GIT_URI = "git://github.com/riscv/riscv-glibc" -SRCBRANCH = "riscv-glibc-${PV}" -SRCREV = "8259af85ae3988d1c1f5f3d7c9499f0a18153ec9" - -SRC_URI += "file://0001-sysdeps-riscv-Execute-preconfiure-only-for-risv-targ.patch \ - file://0001-Fix-mcontext_t-sigcontext-namespace-for-riscv.patch \ - " -# see https://github.com/riscv/riscv-glibc/issues/20 -EXTRA_OECONF += "--disable-werror" -