From 62721a1e296b244ac856bb67bf384b6f81c419fb Mon Sep 17 00:00:00 2001 From: Maciej Pijanowski Date: Fri, 30 Apr 2021 23:56:29 +0200 Subject: [PATCH] linux-beaglev: sync dts from u-boot Signed-off-by: Maciej Pijanowski --- .../0001-sync-beaglev-dts-from-u-boot.patch | 1122 +++++++++++++++++ recipes-kernel/linux/linux-beaglev_5.10.bb | 5 + 2 files changed, 1127 insertions(+) create mode 100644 recipes-kernel/linux/linux-beaglev/0001-sync-beaglev-dts-from-u-boot.patch diff --git a/recipes-kernel/linux/linux-beaglev/0001-sync-beaglev-dts-from-u-boot.patch b/recipes-kernel/linux/linux-beaglev/0001-sync-beaglev-dts-from-u-boot.patch new file mode 100644 index 0000000..99fe35d --- /dev/null +++ b/recipes-kernel/linux/linux-beaglev/0001-sync-beaglev-dts-from-u-boot.patch @@ -0,0 +1,1122 @@ +From a8be849b25db468101358c4e907db85c05db5e96 Mon Sep 17 00:00:00 2001 +From: Maciej Pijanowski +Date: Fri, 30 Apr 2021 23:53:33 +0200 +Subject: [PATCH] sync beaglev dts from u-boot + +Signed-off-by: Maciej Pijanowski +--- + arch/riscv/boot/dts/sifive/Makefile | 1 + + arch/riscv/boot/dts/sifive/seeed5inch.dtsi | 119 +++ + .../dts/sifive/starfive_vic7100_beagle_v.dts | 680 ++++++++++++++++++ + .../boot/dts/sifive/starfive_vic7100_clk.dtsi | 109 +++ + arch/riscv/boot/dts/sifive/tda998x_1080p.dtsi | 106 +++ + include/dt-bindings/display/starfive_fb.h | 47 ++ + 6 files changed, 1062 insertions(+) + create mode 100644 arch/riscv/boot/dts/sifive/seeed5inch.dtsi + create mode 100644 arch/riscv/boot/dts/sifive/starfive_vic7100_beagle_v.dts + create mode 100644 arch/riscv/boot/dts/sifive/starfive_vic7100_clk.dtsi + create mode 100644 arch/riscv/boot/dts/sifive/tda998x_1080p.dtsi + create mode 100644 include/dt-bindings/display/starfive_fb.h + +diff --git a/arch/riscv/boot/dts/sifive/Makefile b/arch/riscv/boot/dts/sifive/Makefile +index 6d6189e6e4af..63f5384c565f 100644 +--- a/arch/riscv/boot/dts/sifive/Makefile ++++ b/arch/riscv/boot/dts/sifive/Makefile +@@ -1,2 +1,3 @@ + # SPDX-License-Identifier: GPL-2.0 + dtb-$(CONFIG_SOC_SIFIVE) += hifive-unleashed-a00.dtb ++dtb-$(CONFIG_SOC_SIFIVE) += starfive_vic7100_beagle_v.dtb +diff --git a/arch/riscv/boot/dts/sifive/seeed5inch.dtsi b/arch/riscv/boot/dts/sifive/seeed5inch.dtsi +new file mode 100644 +index 000000000000..59eece30d398 +--- /dev/null ++++ b/arch/riscv/boot/dts/sifive/seeed5inch.dtsi +@@ -0,0 +1,119 @@ ++#include ++ ++&sfivefb { ++ seeed_5_inch { ++ compatible = "starfive,display-dev"; ++ panel_name = "seeed_5_inch"; ++ panel_lcd_id = <22>; /*480p*/ ++ interface_info = "mipi_interface"; ++ refresh_en = <1>; ++ bits-per-pixel = <24>; ++ physical-width = <62>; ++ physical-height = <114>; ++ panel-width = <800>; ++ panel-height = <480>; ++ pixel-clock = <27500000>; ++ /*dyn_fps;*/ /*dynamic frame rate support*/ ++ fps = <50>; ++ /*.flags = PREFER_CMD_SEND_MONOLITHIC | CE_CMD_SEND_MONOLITHIC | RESUME_WITH_PREFER | RESUME_WITH_CE*/ ++ /*gamma-command-monolithic;*/ ++ /*ce-command-monolithic;*/ ++ /*resume-with-gamma;*/ ++ /*resume-with-ce;*/ ++ ++ /*mipi info*/ ++ mipi-byte-clock = <78000>; ++ mipi-escape-clock = <13000>; ++ lane-no = <1>; ++ display_mode = "video_mode"; /*video_mode, command_mode*/ ++ ++ /* ++ auto_stop_clklane_en; ++ im_pin_val; ++ */ ++ ++ color_bits = ; ++ /*is_18bit_loosely;*/ ++ ++ /*video mode info*/ ++ h-pulse-width = <10>; ++ h-back-porch = <20>; ++ h-front-porch = <50>; ++ v-pulse-width = <5>; ++ v-back-porch = <5>; ++ v-front-porch = <135>; ++ ++ /*seeed panel mode info*/ ++ dphy_bps = <700000000>; ++ dsi_burst_mode = <0>; ++ dsi_sync_pulse = <1>; ++ // bytes ++ dsi_hsa = <30>; ++ dsi_hbp = <211>; ++ dsi_hfp = <159>; ++ // lines ++ dsi_vsa = <5>; ++ dsi_vbp = <5>; ++ dsi_vfp = <134>; ++ ++ status = "okay"; ++ sync_pol = "vsync_high_act"; /*vsync_high_act, hsync_high_act*/ ++ lp_cmd_en; ++ /*lp_hfp_en;*/ ++ /*lp_hbp_en;*/ ++ /*lp_vact_en;*/ ++ lp_vfp_en; ++ lp_vbp_en; ++ lp_vsa_en; ++ traffic-mode = "burst_with_sync_pulses"; /*non_burst_with_sync_pulses, non_burst_with_sync_events*/ ++ ++ /*phy info*/ ++ data_tprepare = /bits/ 8 <0>; ++ data_hs_zero = /bits/ 8 <0>; ++ data_hs_exit = /bits/ 8 <0>; ++ data_hs_trail = /bits/ 8 <0>; ++ ++ /*te info*/ ++ te_source = "external_pin"; /*external_pin, dsi_te_trigger*/ ++ te_trigger_mode = "rising_edge"; /*rising_edge, high_1000us*/ ++ te_enable = <0>; ++ cm_te_effect_sync_enable = <0>; /*used in command mode*/ ++ te_count_per_sec = <64>; /*used in esd*/ ++ ++ /*ext info*/ ++ /* ++ crc_rx_en; ++ ecc_rx_en; ++ eotp_rx_en; ++ */ ++ eotp_tx_en; ++ ++ dev_read_time = <0x7FFF>; ++ /*type cmd return_count return_code*/ ++ /*id_read_cmd_info = [];*/ ++ /*pre_id_cmd = [];*/ ++ /*esd_read_cmd_info = [DCS_CMD 0A 01 9C];*/ ++ /*pre_esd_cmd = [];*/ ++ /*panel-on-command = [];*/ ++ /*panel-off-command = [];*/ ++ /*reset-sequence = <1 5>, <0 10>, <1 30>;*/ ++ /* ++ panel-gamma-warm-command = [ ++ ++ ]; ++ panel-gamma-nature-command = [ ++ ++ ]; ++ panel-gamma-cool-command = [ ++ ++ ]; ++ ++ panel-ce-std-command = [ ++ ++ ]; ++ panel-ce-vivid-command = [ ++ ++ ]; ++ */ ++ }; ++}; +diff --git a/arch/riscv/boot/dts/sifive/starfive_vic7100_beagle_v.dts b/arch/riscv/boot/dts/sifive/starfive_vic7100_beagle_v.dts +new file mode 100644 +index 000000000000..3b5b086d0ff7 +--- /dev/null ++++ b/arch/riscv/boot/dts/sifive/starfive_vic7100_beagle_v.dts +@@ -0,0 +1,680 @@ ++/dts-v1/; ++#include "starfive_vic7100_clk.dtsi" ++#include ++#include ++ ++ ++/ { ++ #address-cells = <2>; ++ #size-cells = <2>; ++ compatible = "sifive,freedom-u74-arty"; ++ model = "sifive,freedom-u74-arty"; ++ ++ chosen { ++ linux,initrd-start = <0x0 0x86100000>; ++ linux,initrd-end = <0x0 0x8c000000>; ++ stdout-path = "/soc/serial@12440000:115200"; ++ #bootargs = "debug console=ttyS0 rootwait"; ++ }; ++ aliases { ++ spi0="/soc/qspi@11860000"; ++ mshc0="/soc/sdio0@10000000"; ++ mshc1="/soc/sdio1@10010000"; ++ usb0="/soc/usb@104c0000"; ++ }; ++ cpus: cpus { ++ #address-cells = <1>; ++ #size-cells = <0>; ++ timebase-frequency = <6250000>; ++ compatible = "starfive,fu74-g000"; ++ cpu@0 { ++ clock-frequency = <0>; ++ compatible = "starfive,rocket0", "riscv"; ++ d-cache-block-size = <64>; ++ d-cache-sets = <64>; ++ d-cache-size = <32768>; ++ d-tlb-sets = <1>; ++ d-tlb-size = <32>; ++ device_type = "cpu"; ++ i-cache-block-size = <64>; ++ i-cache-sets = <64>; ++ i-cache-size = <32768>; ++ i-tlb-sets = <1>; ++ i-tlb-size = <32>; ++ mmu-type = "riscv,sv39"; ++ next-level-cache = <&cachectrl>; ++ reg = <0>; ++ riscv,isa = "rv64imafdc"; ++ starfive,itim = <&itim0>; ++ status = "okay"; ++ tlb-split; ++ cpu0intctrl: interrupt-controller { ++ #interrupt-cells = <1>; ++ compatible = "riscv,cpu-intc"; ++ interrupt-controller; ++ }; ++ }; ++ ++ cpu@1 { ++ clock-frequency = <0>; ++ compatible = "starfive,rocket0", "riscv"; ++ d-cache-block-size = <64>; ++ d-cache-sets = <64>; ++ d-cache-size = <32768>; ++ d-tlb-sets = <1>; ++ d-tlb-size = <32>; ++ device_type = "cpu"; ++ i-cache-block-size = <64>; ++ i-cache-sets = <64>; ++ i-cache-size = <32768>; ++ i-tlb-sets = <1>; ++ i-tlb-size = <32>; ++ mmu-type = "riscv,sv39"; ++ next-level-cache = <&cachectrl>; ++ reg = <1>; ++ riscv,isa = "rv64imafdc"; ++ starfive,itim = <&itim1>; ++ status = "okay"; ++ tlb-split; ++ cpu1intctrl: interrupt-controller { ++ #interrupt-cells = <1>; ++ compatible = "riscv,cpu-intc"; ++ interrupt-controller; ++ }; ++ }; ++ }; ++ memory@80000000 { ++ device_type = "memory"; ++ reg = <0x0 0x80000000 0x2 0x0>; ++ }; ++ memory@3000000000 { ++ device_type = "memory"; ++ reg = <0x30 0x0 0x0 0x0>; ++ }; ++ ++ reserved-memory { ++ #address-cells = <2>; ++ #size-cells = <2>; ++ ranges; ++ ++ linux,cma { ++ compatible = "shared-dma-pool"; ++ reusable; ++ size = <0x0 0x28000000>; ++ alignment = <0x0 0x1000>; ++ alloc-ranges = <0x0 0xa0000000 0x0 0x28000000>; ++ linux,cma-default; ++ }; ++ jpu_reserved: framebuffer@c9000000 { ++ reg = <0x0 0xc9000000 0x0 0x4000000>; ++ }; ++ nvdla_reserved:framebuffer@d0000000{ ++ reg = <0x0 0xd0000000 0x0 0x28000000>; ++ }; ++ ++ vin_reserved: framebuffer@f9000000 { ++ compatible = "shared-dma-pool"; ++ no-map; ++ reg = <0x0 0xf9000000 0x0 0x1000000>; ++ }; ++ ++ sffb_reserved: framebuffer@fb000000 { ++ compatible = "shared-dma-pool"; ++ no-map; ++ reg = <0x0 0xfb000000 0x0 0x2000000>; ++ }; ++ }; ++ ++ soc { ++ #address-cells = <2>; ++ #size-cells = <2>; ++ #clock-cells = <1>; ++ compatible = "starfive,freedom-u74-arty", "simple-bus"; ++ ranges; ++ ++ cachectrl: cache-controller@2010000 { ++ cache-block-size = <64>; ++ cache-level = <2>; ++ cache-sets = <2048>; ++ cache-size = <2097152>; ++ cache-unified; ++ compatible = "sifive,fu540-c000-ccache", "starfive,ccache0", "cache"; ++ interrupt-parent = <&plic>; ++ interrupts = <128 131 129 130>; ++ /*next-level-cache = <&L40 &L36>;*/ ++ reg = <0x0 0x2010000 0x0 0x1000 0x0 0x8000000 0x0 0x2000000>; ++ reg-names = "control", "sideband"; ++ }; ++ ++ ++ dtim: dtim@1000000 { ++ compatible = "starfive,dtim0"; ++ reg = <0x0 0x1000000 0x0 0x2000>; ++ reg-names = "mem"; ++ }; ++ ++ itim0: itim@1808000 { ++ compatible = "starfive,itim0"; ++ reg = <0x0 0x1808000 0x0 0x8000>; ++ reg-names = "mem"; ++ }; ++ ++ itim1: itim@1820000 { ++ compatible = "starfive,itim0"; ++ reg = <0x0 0x1820000 0x0 0x8000>; ++ reg-names = "mem"; ++ }; ++ ++ clint: clint@2000000 { ++ #interrupt-cells = <1>; ++ compatible = "riscv,clint0"; ++ interrupts-extended = <&cpu0intctrl 3 &cpu0intctrl 7 &cpu1intctrl 3 &cpu1intctrl 7 >; ++ reg = <0x0 0x2000000 0x0 0x10000>; ++ reg-names = "control"; ++ }; ++ plic: plic@c000000 { ++ #interrupt-cells = <1>; ++ compatible = "riscv,plic0"; ++ interrupt-controller; ++ interrupts-extended = <&cpu0intctrl 11 &cpu0intctrl 9 &cpu1intctrl 11 &cpu1intctrl 9 >; ++ reg = <0x0 0xc000000 0x0 0x4000000>; ++ reg-names = "control"; ++ riscv,max-priority = <7>; ++ riscv,ndev = <127>; ++ }; ++ ++ uart3: serial@12440000 { ++ compatible = "snps,dw-apb-uart", "starfive,uart0"; ++ interrupt-parent = <&plic>; ++ interrupts = <73>; ++ reg = <0x0 0x12440000 0x0 0x10000>; ++ reg-io-width = <4>; ++ reg-shift = <2>; ++ clocks = <&uartclk>, <&apb2clk>; ++ clock-names = "baudclk", "apb_pclk"; ++ current-clock = <100000000>; ++ current-speed = <115200>; ++ status = "okay"; ++ }; ++ uart2: serial@12430000 { ++ compatible = "snps,dw-apb-uart"; ++ interrupt-parent = <&plic>; ++ interrupts = <72>; ++ reg = <0x0 0x12430000 0x0 0x10000>; ++ reg-io-width = <4>; ++ reg-shift = <2>; ++ clocks = <&uartclk>, <&apb2clk>; ++ clock-names = "baudclk", "apb_pclk"; ++ current-clock = <100000000>; ++ current-speed = <115200>; ++ status = "disabled"; ++ }; ++ uart1: hs_serial@11880000 { ++ compatible = "snps,dw-apb-uart"; ++ interrupt-parent = <&plic>; ++ interrupts = <93>; ++ reg = <0x0 0x11880000 0x0 0x10000>; ++ reg-io-width = <4>; ++ reg-shift = <2>; ++ clocks = <&hs_uartclk>, <&apb1clk>; ++ clock-names = "baudclk","apb_pclk"; ++ current-clock = <74250000>; ++ current-speed = <115200>; ++ status = "disabled"; ++ }; ++ uart0: hs_serial@11870000 { ++ compatible = "snps,dw-apb-uart"; ++ interrupt-parent = <&plic>; ++ interrupts = <92>; ++ reg = <0x0 0x11870000 0x0 0x10000>; ++ reg-io-width = <4>; ++ reg-shift = <2>; ++ clocks = <&hs_uartclk>, <&apb1clk>; ++ clock-names = "baudclk", "apb_pclk"; ++ current-clock = <74250000>; ++ current-speed = <115200>; ++ status = "okay"; ++ }; ++ ++ dma2p: sgdma2p@100b0000 { ++ compatible = "snps,axi-dma-1.01a"; ++ reg = <0x0 0x100b0000 0x0 0x10000>; ++ clocks = <&axiclk>,<&ahb0clk>; ++ clock-names = "core-clk", "cfgr-clk"; ++ interrupt-parent = <&plic>; ++ interrupts = <2>; ++ dma-channels = <4>; ++ snps,dma-masters = <1>; ++ snps,data-width = <4>; ++ snps,block-size = <4096 4096 4096 4096>; ++ snps,priority = <0 1 2 3>; ++ snps,axi-max-burst-len = <128>; ++ status = "okay"; ++ }; ++ ++ dma1p: sgdma1p@10500000 { ++ compatible = "snps,axi-dma-1.01a"; ++ reg = <0x0 0x10500000 0x0 0x10000>; ++ clocks = <&axiclk>,<&ahb0clk>; ++ clock-names = "core-clk", "cfgr-clk"; ++ interrupt-parent = <&plic>; ++ interrupts = <1>; ++ dma-channels = <16>; ++ snps,dma-masters = <1>; ++ snps,data-width = <3>; ++ snps,block-size = <4096 4096 4096 4096 4096 4096 4096 4096 4096 4096 4096 4096 4096 4096 4096 4096>; ++ snps,priority = <0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15>; ++ snps,axi-max-burst-len = <64>; ++ status = "okay"; ++ }; ++ ++ USB30: usb@104c0000 { ++ compatible = "cdns,usb3"; ++ reg = <0x0 0x104c0000 0x0 0x10000>, // memory area for HOST registers ++ <0x0 0x104d0000 0x0 0x10000>, // memory area for DEVICE registers ++ <0x0 0x104e0000 0x0 0x10000>; // memory area for OTG/DRD registers ++ reg-names = "otg", "xhci", "dev"; ++ interrupt-parent = <&plic>; ++ interrupts = <43>, <44>, <52>; ++ interrupt-names = "otg", ++ "host", ++ "peripheral"; ++ phy-names = "cdns3,usb3-phy", "cnds3,usb2-phy"; ++ status = "okay"; ++ }; ++ ++ ++ gpio: gpio@11910000 { ++ compatible = "starfive,gpio0"; ++ interrupt-parent = <&plic>; ++ interrupts = <32>; ++ reg = <0x0 0x11910000 0x0 0x10000>; ++ reg-names = "control"; ++ interrupt-controller; ++ #gpio-cells = <2>; ++ }; ++ gpiorst:gpio-restart { ++ compatible = "gpio-restart"; ++ gpios = <&gpio 63 GPIO_ACTIVE_HIGH>; ++ }; ++ gpiopof:gpio-poweroff { ++ compatible = "gpio-poweroff"; ++ gpios = <&gpio 63 GPIO_ACTIVE_HIGH>; ++ }; ++ ++ i2c0: i2c@118b0000 { ++ #address-cells = <1>; ++ #size-cells = <0>; ++ #clock-cells = <0>; ++ compatible = "snps,designware-i2c"; ++ reg = <0x0 0x118b0000 0x0 0x10000>; ++ interrupt-parent = <&plic>; ++ interrupts = <96>; ++ clocks = <49500000>; ++ clock-frequency = <100000>; ++ i2c-sda-hold-time-ns = <300>; ++ i2c-sda-falling-time-ns = <500>; ++ i2c-scl-falling-time-ns = <500>; ++ scl-gpio = <&gpio 62 0>; ++ sda-gpio = <&gpio 61 0>; ++ ++ tda998x@70 { ++ compatible = "nxp,tda998x"; ++ reg = <0x70>; ++ }; ++ ++ imx219@10 { ++ compatible = "imx219"; ++ reg = <0x10>; ++ reset-gpio = <&gpio 58 0>; ++ }; ++ }; ++ ++ i2c1: i2c@118c0000 { ++ #address-cells = <1>; ++ #size-cells = <0>; ++ #clock-cells = <0>; ++ compatible = "snps,designware-i2c"; ++ reg = <0x0 0x118c0000 0x0 0x10000>; ++ interrupt-parent = <&plic>; ++ interrupts = <97>; ++ clocks = <49500000>; ++ clock-frequency = <400000>; ++ i2c-sda-hold-time-ns = <300>; ++ i2c-sda-falling-time-ns = <100>; ++ i2c-scl-falling-time-ns = <100>; ++ scl-gpio = <&gpio 47 0>; ++ sda-gpio = <&gpio 48 0>; ++ }; ++ ++ i2c2: i2c@12450000 { ++ #address-cells = <1>; ++ #size-cells = <0>; ++ #clock-cells = <0>; ++ compatible = "snps,designware-i2c"; ++ reg = <0x0 0x12450000 0x0 0x10000>; ++ interrupt-parent = <&plic>; ++ interrupts = <74>; ++ clocks = <50000000>; ++ clock-frequency = <100000>; ++ i2c-sda-hold-time-ns = <300>; ++ i2c-sda-falling-time-ns = <500>; ++ i2c-scl-falling-time-ns = <500>; ++ scl-gpio = <&gpio 60 0>; ++ sda-gpio = <&gpio 59 0>; ++ ++ seeed_plane_i2c@45 { ++ compatible = "seeed_panel"; ++ reg = <0x45>; ++ }; ++ }; ++ ++ trng: trng@118d0000 { ++ compatible = "starfive,vic-rng"; ++ reg = <0x0 0x118d0000 0x0 0x10000>; ++ interrupt-parent = <&plic>; ++ interrupts = <98>; ++ clocks = <&hfclk>; ++ }; ++ crypto: crypto@100d0000 { ++ compatible = "starfive,vic-sec"; ++ reg = <0x0 0x100d0000 0x0 0x20000>, ++ <0x0 0x11800234 0x0 0xc>; ++ reg-names = "secmem","secclk"; ++ interrupt-parent = <&plic>; ++ interrupts = <31>; ++ clocks = <&hfclk>; ++ }; ++ ++ /*gmac device configuration*/ ++ stmmac_axi_setup: stmmac-axi-config { ++ snps,wr_osr_lmt = <0xf>; ++ snps,rd_osr_lmt = <0xf>; ++ snps,blen = <256 128 64 32 0 0 0>; ++ }; ++ gmac:gmac@10020000{ ++ compatible = "snps,dwmac"; ++ reg = <0x0 0x10020000 0x0 0x10000>; ++ interrupt-parent = <&plic>; ++ interrupts = <6 7>; ++ interrupt-names = "macirq","eth_wake_irq"; ++ max-frame-size = <9000>; ++ phy-mode = "rgmii-txid"; ++ snps,multicast-filter-bins = <256>; ++ snps,perfect-filter-entries = <128>; ++ rx-fifo-depth = <32768>; ++ tx-fifo-depth = <16384>; ++ clocks = <&gmacclk>; ++ clock-names = "stmmaceth"; ++ snps,fixed-burst = <1>; ++ snps,no-pbl-x8 = <1>; ++ /*snps,force_sf_dma_mode;*/ ++ snps,force_thresh_dma_mode; ++ snps,axi-config = <&stmmac_axi_setup>; ++ }; ++ ++ nbdla: nvdla@0x11940000 { ++ compatible = "nvidia,nvdla_os_initial"; ++ interrupt-parent = <&plic>; ++ interrupts = <22>; ++ memory-region = <&nvdla_reserved>; ++ reg = <0x0 0x11940000 0x0 0x40000>; ++ status = "okay"; ++ }; ++ ++ jpu:coadj12@11900000 { ++ compatible = "cm,codaj12-jpu-1"; ++ reg = <0x0 0x11900000 0x0 0x300>; ++ memory-region = <&jpu_reserved>; ++ interrupt-parent = <&plic>; ++ interrupts = <24>; ++ clocks = <&jpuclk>; ++ clock-names = "jpege"; ++ reg-names = "control"; ++ status = "okay"; ++ }; ++ ++ vpu_dec:vpu_dec@118F0000 { ++ compatible = "c&m,cm511-vpu"; ++ reg = <0 0x118F0000 0 0x10000>; ++ //memory-region = <&vpu_reserved>; ++ interrupt-parent = <&plic>; ++ interrupts = <23>; ++ clocks = <&vpuclk>; ++ clock-names = "vcodec"; ++ status = "okay"; ++ }; ++ ++ vpu_enc:vpu_enc@118E0000 { ++ compatible = "cm,cm521-vpu"; ++ reg = <0x0 0x118E0000 0x0 0x4000>; ++ interrupt-parent = <&plic>; ++ interrupts = <26>; ++ clocks = <&vpuclk>; ++ clock-names = "vcodec"; ++ reg-names = "control"; ++ }; ++ ++ ptc: pwm@12490000 { ++ compatible = "starfive,pwm0"; ++ reg = <0x0 0x12490000 0x0 0x10000>; ++ reg-names = "control"; ++ sifive,approx-period = <100000000>; ++ clocks = <&pwmclk>; ++ #pwm-cells=<3>; ++ sifive,npwm = <8>; ++ ++ }; ++ ++ qspi:qspi@11860000 { ++ compatible = "cadence,qspi","cdns,qspi-nor"; ++ #address-cells = <1>; ++ #size-cells = <0>; ++ reg = <0x0 0x11860000 0x0 0x10000 0x0 0x20000000 0x0 0x20000000 >; ++ interrupts = <3>; ++ interrupt-parent = <&plic>; ++ clocks = <&qspi_clk>; ++ cdns,fifo-depth = <256>; ++ cdns,fifo-width = <4>; ++ cdns,trigger-address = <0x00000000>; ++ status = "okay"; ++ spi-max-frequency = <250000000>; ++ nor_flash:nor-flash@0 { ++ compatible = "spi-flash"; ++ reg=<0>; ++ spi-max-frequency = <31250000>; ++ page-size = <256>; ++ block-size = <16>; ++ cdns,read-delay = <4>; ++ cdns,tshsl-ns = <1>; ++ cdns,tsd2d-ns = <1>; ++ cdns,tchsh-ns = <1>; ++ cdns,tslch-ns = <1>; ++ spi-tx-bus-width = <1>; ++ spi-rx-bus-width = <1>; ++ }; ++ nand_flash:nand-flash@1 { ++ compatible = "spi-flash-nand"; ++ reg=<1>; ++ spi-max-frequency = <31250000>; ++ page-size = <2048>; ++ block-size = <17>; ++ cdns,read-delay = <4>; ++ cdns,tshsl-ns = <1>; ++ cdns,tsd2d-ns = <1>; ++ cdns,tchsh-ns = <1>; ++ cdns,tslch-ns = <1>; ++ spi-tx-bus-width = <1>; ++ spi-rx-bus-width = <1>; ++ }; ++ }; ++ ++ spi2:spi2@12410000 { ++ compatible = "snps,dw-apb-ssi"; ++ #address-cells = <1>; ++ #size-cells = <0>; ++ interrupt-parent = <&plic>; ++ interrupts = <70>; ++ reg = <0x0 0x12410000 0x0 0x10000>; ++ clocks = <&spiclk>; ++ /*num-cs = <1>; ++ cs-gpios = <&gpio 0 0>;*/ ++ spi_dev0: spi@0 { ++ compatible = "rohm,dh2228fv"; ++ spi-max-frequency = <10000000>; ++ reg = <0>; ++ status = "okay"; ++ }; ++ }; ++ ++ xrp@0 { ++ compatible = "cdns,xrp"; ++ reg = <0x0 0xf0000000 0x0 0x01ffffff ++ 0x10 0x72000000 0x0 0x00001000 ++ 0x10 0x72001000 0x0 0x00fff000 ++ 0x0 0x124b0000 0x0 0x00010000>; ++ clocks = <&hfclk>; ++ interrupt-parent = <&plic>; ++ firmware-name = "vp6_elf"; ++ dsp-irq = <19 20>; ++ dsp-irq-src = <0x20 0x21>; ++ intc-irq-mode = <1>; ++ intc-irq = <0 1>; ++ interrupts = <27 28>; ++ #address-cells = <1>; ++ #size-cells = <1>; ++ ranges = <0x40000000 0x0 0x40000000 0x01000000 ++ 0xb0000000 0x10 0x70000000 0x3000000>; ++ dsp@0 { ++ }; ++ }; ++ sdio0:sdio0@10000000{ ++ compatible = "snps,dw-mshc"; ++ reg = <0x0 0x10000000 0x0 0x10000>; ++ interrupts = <4>; ++ interrupt-parent = <&plic>; ++ clocks = <&dwmmc_biuclk>; ++ clock-names = "biu"; ++ clock-frequency = <100000000>; ++ max-frequency = <10000000>; ++ fifo-depth = <32>; ++ card-detect-delay = <300>; ++ fifo-watermark-aligned; ++ data-addr = <0>; ++ bus-width = <4>; ++ cap-sd-highspeed; ++ broken-cd; ++ no-sdio; ++ post-power-on-delay-ms = <200>; ++ }; ++ sdio1:sdio1@10010000{ ++ compatible = "snps,dw-mshc"; ++ reg = <0x0 0x10010000 0x0 0x10000>; ++ interrupts = <5>; ++ interrupt-parent = <&plic>; ++ clocks = <&dwmmc_biuclk>; ++ clock-names = "biu"; ++ clock-frequency = <100000000>; ++ max-frequency = <10000000>; ++ fifo-depth = <32>; ++ card-detect-delay = <300>; ++ fifo-watermark-aligned; ++ data-addr = <0>; ++ bus-width = <4>; ++ cap-sd-highspeed; ++ /*broken-cd;*/ ++ cap-sdio-irq; ++ cap-mmc-hw-reset; ++ non-removable; ++ enable-sdio-wakeup; ++ keep-power-in-suspend; ++ /*cap-power-off-card;*/ ++ cap-mmc-highspeed; ++ /*fixed-emmc-driver-type;*/ ++ post-power-on-delay-ms = <200>; ++ /* ++ bcmdhd_wlan: bcmdhd_wlan@1 { ++ compatible = "android,bcmdhd_wlan"; ++ gpios = <&gpio 26 0>; ++ }; ++ */ ++ }; ++ ++ sfivefb:sfivefb@12000000 { ++ compatible = "starfive,vpp-lcdc"; ++ interrupt-parent = <&plic>; ++ interrupts = <101>, <103>; ++ interrupt-names = "lcdc_irq", "vpp1_irq"; ++ reg = <0x0 0x12000000 0x0 0x10000>, ++ <0x0 0x12100000 0x0 0x10000>, ++ <0x0 0x12040000 0x0 0x10000>, ++ <0x0 0x12080000 0x0 0x10000>, ++ <0x0 0x120c0000 0x0 0x10000>, ++ <0x0 0x12240000 0x0 0x10000>, ++ <0x0 0x12250000 0x0 0x10000>, ++ <0x0 0x12260000 0x0 0x10000>; ++ reg-names = "lcdc", "dsitx", "vpp0", "vpp1", "vpp2", "clk", "rst", "sys"; ++ memory-region = <&sffb_reserved>; ++ clocks = <&uartclk>, <&apb2clk>; ++ clock-names = "baudclk", "apb_pclk"; ++ status = "okay"; ++ ddr-format = ;/*LCDC win_format*/ ++ ++ /*pp1 { ++ pp-id = <1>; ++ fifo-out; ++ src-format = ; ++ src-width = <800>; ++ src-height = <480>; ++ dst-format = ; ++ dst-width = <800>; ++ dst-height = <480>; ++ };*/ ++ }; ++ ++ vin_sysctl:vin_sysctl@19800000 { ++ compatible = "starfive,stf-vin"; ++ reg = <0x0 0x19800000 0x0 0x10000>, ++ <0x0 0x19810000 0x0 0x10000>, ++ <0x0 0x19820000 0x0 0x10000>, ++ <0x0 0x19830000 0x0 0x10000>, ++ <0x0 0x19840000 0x0 0x10000>, ++ <0x0 0x19870000 0x0 0x30000>, ++ <0x0 0x198a0000 0x0 0x30000>, ++ <0x0 0x11800000 0x0 0x10000>, ++ <0x0 0x11840000 0x0 0x10000>, ++ <0x0 0x11858000 0x0 0x10000>; ++ reg-names = "mipi0", "vclk", "vrst", "mipi1", "sctrl", "isp0", "isp1", "tclk", "trst", "iopad"; interrupt-parent = <&plic>; ++ interrupts = <119 109>; ++ memory-region = <&vin_reserved>; ++ /*defaule config for imx219 vin&isp*/ ++ format = ; ++ frame-width = <800>; ++ frame-height =<480>; ++ isp0_enable; ++ csi-lane = <2>; ++ csi-dlane-swaps = /bits/ 8 <1>,/bits/ 8 <2>,/bits/ 8 <3>,/bits/ 8 <4>; ++ csi-dlane-pn-swaps = /bits/ 8 <0>,/bits/ 8 <0>,/bits/ 8 <0>,/bits/ 8 <0>; ++ csi-clane-swap = /bits/ 8 <0>; ++ csi-clane-pn-swap = /bits/ 8 <0>; ++ csi-mipiID = <0>; ++ csi-width = <1920>; ++ csi-height = <1080>; ++ csi-dt = <0x2b>; ++ }; ++ sfc_tmp:tmpsensor@124A0000 { ++ compatible = "sfc,tempsensor"; ++ reg = <0x0 0x124A0000 0x0 0x1000>; ++ interrupt-parent = <&plic>; ++ interrupts = <122>; ++ status = "okay"; ++ }; ++ otp:otp@11810000{ ++ compatible = "starfive,fu740-otp"; ++ reg = <0x0 0x11810000 0x0 0x10000>; ++ fuse-count = <0x200>; ++ }; ++ }; ++}; ++#include "tda998x_1080p.dtsi" ++#include "seeed5inch.dtsi" +diff --git a/arch/riscv/boot/dts/sifive/starfive_vic7100_clk.dtsi b/arch/riscv/boot/dts/sifive/starfive_vic7100_clk.dtsi +new file mode 100644 +index 000000000000..f3d571420abb +--- /dev/null ++++ b/arch/riscv/boot/dts/sifive/starfive_vic7100_clk.dtsi +@@ -0,0 +1,109 @@ ++/ { ++ hfclk: hfclk { ++ #clock-cells = <0>; ++ compatible = "fixed-clock"; ++ clock-frequency = <25000000>; ++ clock-output-names = "hfclk"; ++ }; ++ rtcclk: rtcclk { ++ #clock-cells = <0>; ++ compatible = "fixed-clock"; ++ clock-frequency = <6250000>; ++ clock-output-names = "rtcclk"; ++ }; ++ i2c0clk: i2c0clk { ++ #clock-cells = <0>; ++ compatible = "fixed-clock"; ++ clock-frequency = <49500000>; ++ clock-output-names = "i2c0clk"; ++ }; ++ ++ i2c2clk: i2c2clk { ++ #clock-cells = <0>; ++ compatible = "fixed-clock"; ++ clock-frequency = <50000000>; ++ clock-output-names = "i2c2clk"; ++ }; ++ ++ axiclk: axiclk { ++ #clock-cells = <0>; ++ compatible = "fixed-clock"; ++ clock-frequency = <500000000>; ++ clock-output-names = "axiclk"; ++ }; ++ ++ ahb0clk: ahb0clk { ++ #clock-cells = <0>; ++ compatible = "fixed-clock"; ++ clock-frequency = <250000000>; ++ }; ++ ahb2clk: ahb2clk { ++ #clock-cells = <0>; ++ compatible = "fixed-clock"; ++ clock-frequency = <125000000>; ++ }; ++ apb1clk: apb1clk { ++ #clock-cells = <0>; ++ compatible = "fixed-clock"; ++ clock-frequency = <125000000>; ++ }; ++ apb2clk: apb2clk { ++ #clock-cells = <0>; ++ compatible = "fixed-clock"; ++ clock-frequency = <125000000>; ++ }; ++ jpuclk: jpuclk { ++ #clock-cells = <0>; ++ compatible = "fixed-clock"; ++ clock-frequency = <333333333>; ++ }; ++ vpuclk: vpuclk { ++ #clock-cells = <0>; ++ compatible = "fixed-clock"; ++ clock-frequency = <400000000>; ++ }; ++ gmacclk: gmacclk { ++ #clock-cells = <0>; ++ compatible = "fixed-clock"; ++ clock-frequency = <25000000>; ++ }; ++ qspi_clk: qspi-clk@0 { ++ #clock-cells = <0>; ++ compatible = "fixed-clock"; ++ clock-frequency = <50000000>; ++ }; ++ uartclk: uartclk { ++ #clock-cells = <0>; ++ compatible = "fixed-clock"; ++ clock-frequency = <100000000>; ++ }; ++ hs_uartclk: hs_uartclk { ++ #clock-cells = <0>; ++ compatible = "fixed-clock"; ++ clock-frequency = <74250000>; ++ }; ++ dwmmc_biuclk: dwmmc_biuclk { ++ #clock-cells = <0>; ++ compatible = "fixed-clock"; ++ clock-frequency = <100000000>; ++ }; ++/* ++ dwmmc_ciuclk: dwmmc_ciuclk { ++ #clock-cells = <0>; ++ compatible = "fixed-clock"; ++ clock-frequency = <100000000>; ++ }; ++*/ ++ spiclk: spiclk { ++ #clock-cells = <0>; ++ compatible = "fixed-clock"; ++ clock-frequency = <50000000>; ++ }; ++ ++ pwmclk: pwmclk { ++ #clock-cells = <0>; ++ compatible = "fixed-clock"; ++ clock-frequency = <125000000>; ++ }; ++ ++}; +diff --git a/arch/riscv/boot/dts/sifive/tda998x_1080p.dtsi b/arch/riscv/boot/dts/sifive/tda998x_1080p.dtsi +new file mode 100644 +index 000000000000..23954092e3a2 +--- /dev/null ++++ b/arch/riscv/boot/dts/sifive/tda998x_1080p.dtsi +@@ -0,0 +1,106 @@ ++#include ++ ++&sfivefb { ++ tda_998x_1080p { ++ compatible = "starfive,display-dev"; ++ panel_name = "tda_998x_1080p"; ++ panel_lcd_id = <22>; /*1080p*/ ++ interface_info = "rgb_interface"; ++ refresh_en = <1>; ++ bits-per-pixel = <16>; ++ physical-width = <62>; ++ physical-height = <114>; ++ panel-width = <1920>; ++ panel-height = <1080>; ++ pixel-clock = <78000000>; ++ /*dyn_fps;*/ /*dynamic frame rate support*/ ++ ++ /*.flags = PREFER_CMD_SEND_MONOLITHIC | CE_CMD_SEND_MONOLITHIC | RESUME_WITH_PREFER | RESUME_WITH_CE*/ ++ /*gamma-command-monolithic;*/ ++ /*ce-command-monolithic;*/ ++ /*resume-with-gamma;*/ ++ /*resume-with-ce;*/ ++ ++ /*mipi info*/ ++ mipi-byte-clock = <78000>; ++ mipi-escape-clock = <13000>; ++ lane-no = <4>; ++ display_mode = "video_mode"; /*video_mode, command_mode*/ ++ ++ /* ++ auto_stop_clklane_en; ++ im_pin_val;*/ ++ ++ ++ color_bits = ; ++ /*is_18bit_loosely;*/ ++ ++ /*video mode info*/ ++ h-pulse-width = <44>; ++ h-back-porch = <148>; ++ h-front-porch = <88>; ++ v-pulse-width = <5>; ++ v-back-porch = <36>; ++ v-front-porch = <4>; ++ status = "okay"; ++ sync_pol = "vsync_high_act"; /*vsync_high_act, hsync_high_act*/ ++ lp_cmd_en; ++ /*lp_hfp_en;*/ ++ /*lp_hbp_en;*/ ++ /*lp_vact_en;*/ ++ lp_vfp_en; ++ lp_vbp_en; ++ lp_vsa_en; ++ traffic-mode = "burst_with_sync_pulses"; /*non_burst_with_sync_pulses, non_burst_with_sync_events*/ ++ ++ /*phy info*/ ++ data_tprepare = /bits/ 8 <0>; ++ data_hs_zero = /bits/ 8 <0>; ++ data_hs_exit = /bits/ 8 <0>; ++ data_hs_trail = /bits/ 8 <0>; ++ ++ /*te info*/ ++ te_source = "external_pin"; /*external_pin, dsi_te_trigger*/ ++ te_trigger_mode = "rising_edge"; /*rising_edge, high_1000us*/ ++ te_enable = <0>; ++ cm_te_effect_sync_enable = <0>; /*used in command mode*/ ++ te_count_per_sec = <64>; /*used in esd*/ ++ ++ /*ext info*/ ++ /* ++ crc_rx_en; ++ ecc_rx_en; ++ eotp_rx_en; ++ */ ++ eotp_tx_en; ++ ++ dev_read_time = <0x7FFF>; ++ /*type cmd return_count return_code*/ ++ /*id_read_cmd_info = [];*/ ++ /*pre_id_cmd = [];*/ ++ /*esd_read_cmd_info = [DCS_CMD 0A 01 9C];*/ ++ /*pre_esd_cmd = [];*/ ++ /*panel-on-command = [];*/ ++ /*panel-off-command = [];*/ ++ /*reset-sequence = <1 5>, <0 10>, <1 30>;*/ ++ /* ++ panel-gamma-warm-command = [ ++ ++ ]; ++ panel-gamma-nature-command = [ ++ ++ ]; ++ panel-gamma-cool-command = [ ++ ++ ]; ++ ++ panel-ce-std-command = [ ++ ++ ]; ++ panel-ce-vivid-command = [ ++ ++ ]; ++ */ ++ }; ++}; ++ +diff --git a/include/dt-bindings/display/starfive_fb.h b/include/dt-bindings/display/starfive_fb.h +new file mode 100644 +index 000000000000..a7e014d61b29 +--- /dev/null ++++ b/include/dt-bindings/display/starfive_fb.h +@@ -0,0 +1,47 @@ ++#ifndef __STARFIVE_FB_H ++#define __STARFIVE_FB_H ++ ++/*color code*/ ++#define COLOR_CODE_16BIT_CONFIG1 0 //PACKET RGB565 ++#define COLOR_CODE_16BIT_CONFIG2 1 //UNPACKET RGB565 ++#define COLOR_CODE_16BIT_CONFIG3 2 //UNPACKET RGB565 ++#define COLOR_CODE_18BIT_CONFIG1 3 //PACKET RGB666 ++#define COLOR_CODE_18BIT_CONFIG2 4 //UNPACKET RGB666 ++#define COLOR_CODE_24BIT 5 //PACKET RGB888 ++#define COLOR_CODE_MAX 6 ++ ++/*command code*/ ++#define DCS_CMD 02 ++#define GEN_CMD 03 ++#define SW_PACK0 04 ++#define SW_PACK1 05 ++#define SW_PACK2 06 ++#define LW_PACK 07 ++#define SHUTDOWN_SW_PACK 08 ++ ++/*color format, need match to enum COLOR_FORMAT in starfive_vpp.h*/ ++#define COLOR_YUV422_UYVY 0 ++#define COLOR_YUV422_VYUY 1 ++#define COLOR_YUV422_YUYV 2 ++#define COLOR_YUV422_YVYU 3 ++#define COLOR_YUV420P 4 ++#define COLOR_YUV420_NV21 5 ++#define COLOR_YUV420_NV12 6 ++#define COLOR_RGB888_ARGB 7 ++#define COLOR_RGB888_ABGR 8 ++#define COLOR_RGB888_RGBA 9 ++#define COLOR_RGB888_BGRA 10 ++#define COLOR_RGB565 11 ++ ++#define SRC_COLORBAR_VIN_ISP 0 ++#define SRC_DVP_SENSOR_VIN 1 ++#define SRC_DVP_SENSOR_VIN_ISP 2 ++#define SRC_CSI2RX_VIN_ISP 3 ++#define SRC_DVP_SENSOR_VIN_OV5640 4 ++ ++#define WIN_FMT_RGB565 4 ++#define WIN_FMT_xRGB1555 5 ++#define WIN_FMT_xRGB4444 6 ++#define WIN_FMT_xRGB8888 7 ++ ++#endif +-- +2.25.1 + diff --git a/recipes-kernel/linux/linux-beaglev_5.10.bb b/recipes-kernel/linux/linux-beaglev_5.10.bb index 2e1e09d..5607969 100644 --- a/recipes-kernel/linux/linux-beaglev_5.10.bb +++ b/recipes-kernel/linux/linux-beaglev_5.10.bb @@ -5,11 +5,16 @@ require recipes-kernel/linux/linux-yocto.inc SRC_URI = "git://github.com/starfive-tech/linux.git;protocol=git;branch=Fedora" +# The dts files are only in U-Boot repo currently +SRC_URI += "file://0001-sync-beaglev-dts-from-u-boot.patch" + LINUX_VERSION ?= "5.10.6" LINUX_VERSION_EXTENSION_append = "-beaglev" SRCREV = "710cf052d6abda73584481d920b4b6befc7240ea" +LIC_FILES_CHKSUM ?= "file://COPYING;md5=6bc538ed5bd9a7fc9398086aedcd7e46" + PV = "${LINUX_VERSION}+git${SRCPV}" KCONFIG_MODE = "--alldefconfig"