diff --git a/recipes-bsp/u-boot/files/2feaab2bd04ed736c637518b3b553615f0c97890.patch b/recipes-bsp/u-boot/files/2feaab2bd04ed736c637518b3b553615f0c97890.patch new file mode 100644 index 0000000..bde1bea --- /dev/null +++ b/recipes-bsp/u-boot/files/2feaab2bd04ed736c637518b3b553615f0c97890.patch @@ -0,0 +1,47 @@ +From 2feaab2bd04ed736c637518b3b553615f0c97890 Mon Sep 17 00:00:00 2001 +From: Bin Meng +Date: Wed, 2 Jun 2021 16:30:37 +0800 +Subject: [PATCH] starfive: beaglev: Disable SIFIVE_CLINT and enable + RISCV_TIMER + +As we are running in S-mode, RISCV_TIMER has to be used. +Adjust the config file accordingly. + +Signed-off-by: Bin Meng +--- + board/starfive/vic7100/Kconfig | 1 - + configs/starfive_vic7100_beagle_v_smode_defconfig | 3 +-- + 2 files changed, 1 insertion(+), 3 deletions(-) + +diff --git a/board/starfive/vic7100/Kconfig b/board/starfive/vic7100/Kconfig +index af6c09d4a0..c49faa954b 100644 +--- a/board/starfive/vic7100/Kconfig ++++ b/board/starfive/vic7100/Kconfig +@@ -63,6 +63,5 @@ config BOARD_SPECIFIC_OPTIONS # dummy + imply SYSRESET + imply SYSRESET_GPIO + imply CMD_DHCP +- imply SIFIVE_CLINT + + endif +diff --git a/configs/starfive_vic7100_beagle_v_smode_defconfig b/configs/starfive_vic7100_beagle_v_smode_defconfig +index 9ba0867f9c..a792a45f31 100644 +--- a/configs/starfive_vic7100_beagle_v_smode_defconfig ++++ b/configs/starfive_vic7100_beagle_v_smode_defconfig +@@ -84,7 +84,6 @@ CONFIG_CMODEL_MEDLOW=y + CONFIG_RISCV_SMODE=y + CONFIG_RISCV_ISA_C=y + CONFIG_RISCV_ISA_A=y +-CONFIG_SIFIVE_CLINT=y + CONFIG_SBI=y + # CONFIG_SBI_V01 is not set + CONFIG_SBI_V02=y +@@ -1121,7 +1120,7 @@ CONFIG_TIMER=y + # CONFIG_RENESAS_OSTM_TIMER is not set + # CONFIG_NOMADIK_MTU_TIMER is not set + # CONFIG_OMAP_TIMER is not set +-# CONFIG_RISCV_TIMER is not set ++CONFIG_RISCV_TIMER=y + # CONFIG_ROCKCHIP_TIMER is not set + # CONFIG_STI_TIMER is not set + # CONFIG_STM32_TIMER is not set diff --git a/recipes-bsp/u-boot/files/977abc529f98c1c90a80ad280fe9e58ddd43c87a.patch b/recipes-bsp/u-boot/files/977abc529f98c1c90a80ad280fe9e58ddd43c87a.patch new file mode 100644 index 0000000..3265ee8 --- /dev/null +++ b/recipes-bsp/u-boot/files/977abc529f98c1c90a80ad280fe9e58ddd43c87a.patch @@ -0,0 +1,29 @@ +From 977abc529f98c1c90a80ad280fe9e58ddd43c87a Mon Sep 17 00:00:00 2001 +From: Bin Meng +Date: Wed, 2 Jun 2021 16:26:27 +0800 +Subject: [PATCH] Revert "riscv: Enable the SiFive CLINT block driver in + S-Mode(VIC7100 ONLY)" + +This reverts commit 1b3668284b76569c3add4db14524fa5ad60cbc4e. + +The SiFive CLINT driver is supposed to work in M-mode only. + +Signed-off-by: Bin Meng +--- + arch/riscv/Kconfig | 3 ++- + 1 file changed, 2 insertions(+), 1 deletion(-) + +diff --git a/arch/riscv/Kconfig b/arch/riscv/Kconfig +index c26f1316bd..13af5ddfc5 100644 +--- a/arch/riscv/Kconfig ++++ b/arch/riscv/Kconfig +@@ -175,7 +175,8 @@ config DMA_ADDR_T_64BIT + default y if 64BIT + + config SIFIVE_CLINT +- bool "Enable the SiFive CLINT block driver" ++ bool ++ depends on RISCV_MMODE || SPL_RISCV_MMODE + help + The SiFive CLINT block holds memory-mapped control and status registers + associated with software and timer interrupts. diff --git a/recipes-bsp/u-boot/u-boot-starfive_v2021.04.bb b/recipes-bsp/u-boot/u-boot-starfive_v2021.04.bb index 33f669a..0979634 100644 --- a/recipes-bsp/u-boot/u-boot-starfive_v2021.04.bb +++ b/recipes-bsp/u-boot/u-boot-starfive_v2021.04.bb @@ -3,8 +3,10 @@ require recipes-bsp/u-boot/u-boot.inc FILESEXTRAPATHS_prepend := "${THISDIR}/files:" -SRC_URI = "git://github.com/atishp04/u-boot.git;protocol=git;branch=beagleV/Fedora_VIC_7100_2021.04 \ - file://tftp-mmc-boot.txt \ +SRC_URI = "git://github.com/starfive-tech/u-boot.git;protocol=git;branch=Fedora_VIC_7100_2021.04 \ + file://tftp-mmc-boot.txt \ + file://977abc529f98c1c90a80ad280fe9e58ddd43c87a.patch \ + file://2feaab2bd04ed736c637518b3b553615f0c97890.patch \ " SRCREV = "7b70e1d44ba9702a519ca936cabf19070309123a"