From a6801638045868f96f99e31fbc4c051a637cc1a0 Mon Sep 17 00:00:00 2001 From: Khem Raj Date: Sun, 9 May 2021 20:50:47 -0700 Subject: [PATCH] linux-starfive: support TPS65086 restart apply patches from https://github.com/starfive-tech/linux/issues/8 Signed-off-by: Khem Raj --- conf/machine/beaglev-starlight-jh7100.conf | 4 +- ...er-reset-Add-TPS65086-restart-driver.patch | 165 ++ ...ps65086-make-interrupt-line-optional.patch | 36 + ...H7100-and-BeagleV-Starlight-support.patch} | 1609 +++++++++-------- recipes-kernel/linux/linux-starfive/extra.cfg | 2 + recipes-kernel/linux/linux-starfive_5.10.bb | 6 +- 6 files changed, 1050 insertions(+), 772 deletions(-) create mode 100644 recipes-kernel/linux/linux-starfive/0001-power-reset-Add-TPS65086-restart-driver.patch create mode 100644 recipes-kernel/linux/linux-starfive/0002-mfd-tps65086-make-interrupt-line-optional.patch rename recipes-kernel/linux/linux-starfive/{0001-sync-beaglev-dts-from-u-boot.patch => 0003-riscv-dts-Add-JH7100-and-BeagleV-Starlight-support.patch} (73%) diff --git a/conf/machine/beaglev-starlight-jh7100.conf b/conf/machine/beaglev-starlight-jh7100.conf index 86637bf..3b2ea4d 100644 --- a/conf/machine/beaglev-starlight-jh7100.conf +++ b/conf/machine/beaglev-starlight-jh7100.conf @@ -24,14 +24,14 @@ RISCV_SBI_PLAT = "starfive/vic7100" ## This sets u-boot as the default OpenSBI payload RISCV_SBI_PAYLOAD ?= "u-boot.bin" -RISCV_SBI_FDT ?= "starfive_vic7100_beagle_v.dtb" +RISCV_SBI_FDT ?= "jh7100-starlight.dtb" SERIAL_CONSOLES = "115200;ttyS0" MACHINE_EXTRA_RRECOMMENDS += " kernel-modules" IMAGE_FSTYPES += "wic.gz wic.bmap ext4" -KERNEL_DEVICETREE ?= "sifive/${RISCV_SBI_FDT}" +KERNEL_DEVICETREE ?= "starfive/${RISCV_SBI_FDT}" ## Do not update fstab file when using wic images WIC_CREATE_EXTRA_ARGS ?= "--no-fstab-update" diff --git a/recipes-kernel/linux/linux-starfive/0001-power-reset-Add-TPS65086-restart-driver.patch b/recipes-kernel/linux/linux-starfive/0001-power-reset-Add-TPS65086-restart-driver.patch new file mode 100644 index 0000000..8030bdf --- /dev/null +++ b/recipes-kernel/linux/linux-starfive/0001-power-reset-Add-TPS65086-restart-driver.patch @@ -0,0 +1,165 @@ +From c2aa0b4586f6fe53390905603485a6f801f689a2 Mon Sep 17 00:00:00 2001 +From: Emil Renner Berthing +Date: Mon, 3 May 2021 12:20:05 +0200 +Subject: [PATCH 1/3] power: reset: Add TPS65086 restart driver + +Signed-off-by: Emil Renner Berthing +--- + drivers/mfd/tps65086.c | 1 + + drivers/power/reset/Kconfig | 6 ++ + drivers/power/reset/Makefile | 1 + + drivers/power/reset/tps65086-restart.c | 101 +++++++++++++++++++++++++ + 4 files changed, 109 insertions(+) + create mode 100644 drivers/power/reset/tps65086-restart.c + +diff --git a/drivers/mfd/tps65086.c b/drivers/mfd/tps65086.c +index 341466ef20cc..e08823736fe9 100644 +--- a/drivers/mfd/tps65086.c ++++ b/drivers/mfd/tps65086.c +@@ -24,6 +24,7 @@ + static const struct mfd_cell tps65086_cells[] = { + { .name = "tps65086-regulator", }, + { .name = "tps65086-gpio", }, ++ { .name = "tps65086-restart", }, + }; + + static const struct regmap_range tps65086_yes_ranges[] = { +diff --git a/drivers/power/reset/Kconfig b/drivers/power/reset/Kconfig +index d55b3727e00e..fd212a6b1143 100644 +--- a/drivers/power/reset/Kconfig ++++ b/drivers/power/reset/Kconfig +@@ -190,6 +190,12 @@ config POWER_RESET_ST + help + Reset support for STMicroelectronics boards. + ++config POWER_RESET_TPS65086 ++ bool "TPS65086 restart driver" ++ depends on MFD_TPS65086 ++ help ++ Reset TPS65086 PMIC on restart. ++ + config POWER_RESET_VERSATILE + bool "ARM Versatile family reboot driver" + depends on ARM +diff --git a/drivers/power/reset/Makefile b/drivers/power/reset/Makefile +index c51eceba9ea3..d9bb7e2a6f80 100644 +--- a/drivers/power/reset/Makefile ++++ b/drivers/power/reset/Makefile +@@ -21,6 +21,7 @@ obj-$(CONFIG_POWER_RESET_LTC2952) += ltc2952-poweroff.o + obj-$(CONFIG_POWER_RESET_QNAP) += qnap-poweroff.o + obj-$(CONFIG_POWER_RESET_RESTART) += restart-poweroff.o + obj-$(CONFIG_POWER_RESET_ST) += st-poweroff.o ++obj-$(CONFIG_POWER_RESET_TPS65086) += tps65086-restart.o + obj-$(CONFIG_POWER_RESET_VERSATILE) += arm-versatile-reboot.o + obj-$(CONFIG_POWER_RESET_VEXPRESS) += vexpress-poweroff.o + obj-$(CONFIG_POWER_RESET_XGENE) += xgene-reboot.o +diff --git a/drivers/power/reset/tps65086-restart.c b/drivers/power/reset/tps65086-restart.c +new file mode 100644 +index 000000000000..8c47d534d08a +--- /dev/null ++++ b/drivers/power/reset/tps65086-restart.c +@@ -0,0 +1,101 @@ ++// SPDX-License-Identifier: GPL-2.0 ++/* ++ * Copyright (C) 2021 Emil Renner Berthing ++ */ ++ ++#include ++#include ++#include ++#include ++ ++#include ++ ++struct tps65086_restart { ++ struct notifier_block handler; ++ struct tps65086 *tps; ++ struct device *dev; ++}; ++ ++static int tps65086_restart_notify(struct notifier_block *this, ++ unsigned long mode, void *cmd) ++{ ++ struct tps65086_restart *tps65086_restart = ++ container_of(this, struct tps65086_restart, handler); ++ int ret; ++ ++ ret = regmap_write(tps65086_restart->tps->regmap, TPS65086_FORCESHUTDN, 1); ++ if (ret) { ++ dev_err(tps65086_restart->dev, "%s: error writing to tps65086 pmic: %d\n", ++ __func__, ret); ++ return NOTIFY_DONE; ++ } ++ ++ /* give it a little time */ ++ mdelay(200); ++ ++ WARN_ON(1); ++ ++ return NOTIFY_DONE; ++} ++ ++static int tps65086_restart_probe(struct platform_device *pdev) ++{ ++ struct tps65086_restart *tps65086_restart; ++ int ret; ++ ++ tps65086_restart = devm_kzalloc(&pdev->dev, sizeof(*tps65086_restart), GFP_KERNEL); ++ if (!tps65086_restart) ++ return -ENOMEM; ++ ++ platform_set_drvdata(pdev, tps65086_restart); ++ ++ tps65086_restart->handler.notifier_call = tps65086_restart_notify; ++ tps65086_restart->handler.priority = 192; ++ tps65086_restart->tps = dev_get_drvdata(pdev->dev.parent); ++ tps65086_restart->dev = &pdev->dev; ++ ++ ret = register_restart_handler(&tps65086_restart->handler); ++ if (ret) { ++ dev_err(&pdev->dev, "%s: cannot register restart handler: %d\n", ++ __func__, ret); ++ return -ENODEV; ++ } ++ ++ return 0; ++} ++ ++static int tps65086_restart_remove(struct platform_device *pdev) ++{ ++ struct tps65086_restart *tps65086_restart = platform_get_drvdata(pdev); ++ int ret; ++ ++ ret = unregister_restart_handler(&tps65086_restart->handler); ++ if (ret) { ++ dev_err(&pdev->dev, ++ "%s: cannot unregister restart handler: %d\n", ++ __func__, ret); ++ return -ENODEV; ++ } ++ ++ return 0; ++} ++ ++static const struct platform_device_id tps65086_restart_id_table[] = { ++ { "tps65086-restart", }, ++ { /* sentinel */ } ++}; ++MODULE_DEVICE_TABLE(platform, tps65086_restart_id_table); ++ ++static struct platform_driver tps65086_restart_driver = { ++ .driver = { ++ .name = "tps65086-restart", ++ }, ++ .probe = tps65086_restart_probe, ++ .remove = tps65086_restart_remove, ++ .id_table = tps65086_restart_id_table, ++}; ++module_platform_driver(tps65086_restart_driver); ++ ++MODULE_AUTHOR("Emil Renner Berthing "); ++MODULE_DESCRIPTION("TPS65086 restart driver"); ++MODULE_LICENSE("GPL v2"); +-- +2.31.1 + diff --git a/recipes-kernel/linux/linux-starfive/0002-mfd-tps65086-make-interrupt-line-optional.patch b/recipes-kernel/linux/linux-starfive/0002-mfd-tps65086-make-interrupt-line-optional.patch new file mode 100644 index 0000000..19675a1 --- /dev/null +++ b/recipes-kernel/linux/linux-starfive/0002-mfd-tps65086-make-interrupt-line-optional.patch @@ -0,0 +1,36 @@ +From a49f7ec00b6fac15cff2dcb1bd5b483e8efd636e Mon Sep 17 00:00:00 2001 +From: Emil Renner Berthing +Date: Mon, 3 May 2021 12:09:04 +0200 +Subject: [PATCH 2/3] mfd: tps65086: make interrupt line optional + +Signed-off-by: Emil Renner Berthing +--- + drivers/mfd/tps65086.c | 12 +++++++----- + 1 file changed, 7 insertions(+), 5 deletions(-) + +diff --git a/drivers/mfd/tps65086.c b/drivers/mfd/tps65086.c +index e08823736fe9..a6facb30961a 100644 +--- a/drivers/mfd/tps65086.c ++++ b/drivers/mfd/tps65086.c +@@ -101,11 +101,13 @@ static int tps65086_probe(struct i2c_client *client, + (char)((version & TPS65086_DEVICEID_OTP_MASK) >> 4) + 'A', + (version & TPS65086_DEVICEID_REV_MASK) >> 6); + +- ret = regmap_add_irq_chip(tps->regmap, tps->irq, IRQF_ONESHOT, 0, +- &tps65086_irq_chip, &tps->irq_data); +- if (ret) { +- dev_err(tps->dev, "Failed to register IRQ chip\n"); +- return ret; ++ if (tps->irq > 0) { ++ ret = regmap_add_irq_chip(tps->regmap, tps->irq, IRQF_ONESHOT, 0, ++ &tps65086_irq_chip, &tps->irq_data); ++ if (ret) { ++ dev_err(tps->dev, "Failed to register IRQ chip\n"); ++ return ret; ++ } + } + + ret = mfd_add_devices(tps->dev, PLATFORM_DEVID_AUTO, tps65086_cells, +-- +2.31.1 + diff --git a/recipes-kernel/linux/linux-starfive/0001-sync-beaglev-dts-from-u-boot.patch b/recipes-kernel/linux/linux-starfive/0003-riscv-dts-Add-JH7100-and-BeagleV-Starlight-support.patch similarity index 73% rename from recipes-kernel/linux/linux-starfive/0001-sync-beaglev-dts-from-u-boot.patch rename to recipes-kernel/linux/linux-starfive/0003-riscv-dts-Add-JH7100-and-BeagleV-Starlight-support.patch index 374bae4..c974300 100644 --- a/recipes-kernel/linux/linux-starfive/0001-sync-beaglev-dts-from-u-boot.patch +++ b/recipes-kernel/linux/linux-starfive/0003-riscv-dts-Add-JH7100-and-BeagleV-Starlight-support.patch @@ -1,49 +1,294 @@ -From a8be849b25db468101358c4e907db85c05db5e96 Mon Sep 17 00:00:00 2001 -From: Maciej Pijanowski -Date: Fri, 30 Apr 2021 23:53:33 +0200 -Subject: [PATCH] sync beaglev dts from u-boot +From f47d843d8d37b6b84742d9563cc31e58e967e335 Mon Sep 17 00:00:00 2001 +From: TekkamanV +Date: Sat, 23 Jan 2021 02:52:17 +0800 +Subject: [PATCH 3/3] riscv: dts: Add JH7100 and BeagleV Starlight support -The current linux tree does not (yet?) provide the dts files for BeagleV. Only -the U-Boot tree does. In Yocto, we expect to have a dtb as one of the output -file from a kernel recipe. Sync the dts files from U-Boot for know to make the -build pass. - -Signed-off-by: Maciej Pijanowski +Signed-off-by: yanhong.wang +Signed-off-by: Huan.Feng +Signed-off-by: ke.zhu +Signed-off-by: yiming.li +Signed-off-by: jack.zhu +Signed-off-by: Samin Guo +Signed-off-by: Chenjieqin +Signed-off-by: bo.li +Signed-off-by: Emil Renner Berthing --- - arch/riscv/boot/dts/sifive/Makefile | 1 + - arch/riscv/boot/dts/sifive/seeed5inch.dtsi | 119 +++ - .../dts/sifive/starfive_vic7100_beagle_v.dts | 680 ++++++++++++++++++ - .../boot/dts/sifive/starfive_vic7100_clk.dtsi | 109 +++ - arch/riscv/boot/dts/sifive/tda998x_1080p.dtsi | 106 +++ - include/dt-bindings/display/starfive_fb.h | 47 ++ - 6 files changed, 1062 insertions(+) - create mode 100644 arch/riscv/boot/dts/sifive/seeed5inch.dtsi - create mode 100644 arch/riscv/boot/dts/sifive/starfive_vic7100_beagle_v.dts - create mode 100644 arch/riscv/boot/dts/sifive/starfive_vic7100_clk.dtsi - create mode 100644 arch/riscv/boot/dts/sifive/tda998x_1080p.dtsi - create mode 100644 include/dt-bindings/display/starfive_fb.h + arch/riscv/boot/dts/Makefile | 2 +- + arch/riscv/boot/dts/starfive/Makefile | 2 + + .../boot/dts/starfive/jh7100-starlight.dts | 352 +++++++++ + arch/riscv/boot/dts/starfive/jh7100.dtsi | 737 ++++++++++++++++++ + include/dt-bindings/starfive_fb.h | 47 ++ + 5 files changed, 1139 insertions(+), 1 deletion(-) + create mode 100644 arch/riscv/boot/dts/starfive/Makefile + create mode 100644 arch/riscv/boot/dts/starfive/jh7100-starlight.dts + create mode 100644 arch/riscv/boot/dts/starfive/jh7100.dtsi + create mode 100755 include/dt-bindings/starfive_fb.h -diff --git a/arch/riscv/boot/dts/sifive/Makefile b/arch/riscv/boot/dts/sifive/Makefile -index 6d6189e6e4af..63f5384c565f 100644 ---- a/arch/riscv/boot/dts/sifive/Makefile -+++ b/arch/riscv/boot/dts/sifive/Makefile -@@ -1,2 +1,3 @@ +diff --git a/arch/riscv/boot/dts/Makefile b/arch/riscv/boot/dts/Makefile +index ca1f8cbd78c0..b13de6eb614b 100644 +--- a/arch/riscv/boot/dts/Makefile ++++ b/arch/riscv/boot/dts/Makefile +@@ -1,5 +1,5 @@ # SPDX-License-Identifier: GPL-2.0 - dtb-$(CONFIG_SOC_SIFIVE) += hifive-unleashed-a00.dtb -+dtb-$(CONFIG_SOC_SIFIVE) += starfive_vic7100_beagle_v.dtb -diff --git a/arch/riscv/boot/dts/sifive/seeed5inch.dtsi b/arch/riscv/boot/dts/sifive/seeed5inch.dtsi +-subdir-y += sifive ++subdir-y += sifive starfive + subdir-y += kendryte + + obj-$(CONFIG_BUILTIN_DTB) := $(addsuffix /, $(subdir-y)) +diff --git a/arch/riscv/boot/dts/starfive/Makefile b/arch/riscv/boot/dts/starfive/Makefile new file mode 100644 -index 000000000000..59eece30d398 +index 000000000000..685e57c1bf5c --- /dev/null -+++ b/arch/riscv/boot/dts/sifive/seeed5inch.dtsi -@@ -0,0 +1,119 @@ -+#include ++++ b/arch/riscv/boot/dts/starfive/Makefile +@@ -0,0 +1,2 @@ ++# SPDX-License-Identifier: GPL-2.0 ++dtb-$(CONFIG_SOC_STARFIVE_VIC7100) += jh7100-starlight.dtb +diff --git a/arch/riscv/boot/dts/starfive/jh7100-starlight.dts b/arch/riscv/boot/dts/starfive/jh7100-starlight.dts +new file mode 100644 +index 000000000000..ee4ffe15fed9 +--- /dev/null ++++ b/arch/riscv/boot/dts/starfive/jh7100-starlight.dts +@@ -0,0 +1,352 @@ ++/dts-v1/; ++#include "jh7100.dtsi" ++#include ++#include ++ ++/ { ++ #address-cells = <2>; ++ #size-cells = <2>; ++ compatible = "beagle,beaglev-starlight-jh7100"; ++ model = "BeagleV Starlight Beta"; ++ ++ aliases { ++ serial0 = &uart3; ++ serial1 = &uart0; ++ }; ++ ++ chosen { ++ stdout-path = "serial0:115200"; ++ }; ++ ++ cpus { ++ timebase-frequency = <6250000>; ++ }; ++}; ++ ++&uart0 { ++ status = "okay"; ++}; ++ ++&uart3 { ++ status = "okay"; ++}; ++ ++&usb3 { ++ dr_mode = "host"; ++ status = "okay"; ++}; ++ ++&i2c0 { ++ imx219@10 { ++ compatible = "imx219"; ++ reg = <0x10>; ++ reset-gpio = <&gpio 58 0>; ++ }; ++ ++ tps65086@5e { ++ compatible = "ti,tps65086"; ++ reg = <0x5e>; ++ /* ++ interrupt-parent = <&gpio1>; ++ interrupts = <28 IRQ_TYPE_LEVEL_LOW>; ++ interrupt-controller; ++ #interrupt-cells = <2>; ++ */ ++ gpio-controller; ++ #gpio-cells = <2>; ++ }; ++ ++ tda998x@70 { ++ compatible = "nxp,tda998x"; ++ reg = <0x70>; ++ }; ++}; ++ ++&i2c2 { ++ seeed_plane_i2c@45 { ++ compatible = "seeed_panel"; ++ reg = <0x45>; ++ }; ++}; ++ ++&qspi { ++ nor_flash: nor-flash@0 { ++ compatible = "spi-flash"; ++ reg = <0>; ++ spi-max-frequency = <31250000>; ++ page-size = <256>; ++ block-size = <16>; ++ cdns,read-delay = <4>; ++ cdns,tshsl-ns = <1>; ++ cdns,tsd2d-ns = <1>; ++ cdns,tchsh-ns = <1>; ++ cdns,tslch-ns = <1>; ++ spi-tx-bus-width = <1>; ++ spi-rx-bus-width = <1>; ++ }; ++ ++ nand_flash: nand-flash@1 { ++ compatible = "spi-flash-nand"; ++ reg = <1>; ++ spi-max-frequency = <31250000>; ++ page-size = <2048>; ++ block-size = <17>; ++ cdns,read-delay = <4>; ++ cdns,tshsl-ns = <1>; ++ cdns,tsd2d-ns = <1>; ++ cdns,tchsh-ns = <1>; ++ cdns,tslch-ns = <1>; ++ spi-tx-bus-width = <1>; ++ spi-rx-bus-width = <1>; ++ }; ++}; ++ ++&spi2 { ++ spi_dev0: spi@0 { ++ compatible = "rohm,dh2228fv"; ++ spi-max-frequency = <10000000>; ++ reg = <0>; ++ status = "okay"; ++ }; ++}; ++ ++/* ++&sdio1 { ++ bcmdhd_wlan: bcmdhd_wlan@1 { ++ compatible = "android,bcmdhd_wlan"; ++ gpios = <&gpio 26 0>; ++ }; ++}; ++*/ + +&sfivefb { ++ /* ++ pp1 { ++ pp-id = <1>; ++ fifo-out; ++ src-format = ; ++ src-width = <800>; ++ src-height = <480>; ++ dst-format = ; ++ dst-width = <800>; ++ dst-height = <480>; ++ }; ++ */ ++ ++ tda_998x_1080p { ++ compatible = "starfive,display-dev"; ++ panel_name = "tda_998x_1080p"; ++ panel_lcd_id = <22>; /* 1080p */ ++ interface_info = "rgb_interface"; ++ refresh_en = <1>; ++ bits-per-pixel = <16>; ++ physical-width = <62>; ++ physical-height = <114>; ++ panel-width = <1920>; ++ panel-height = <1080>; ++ pixel-clock = <78000000>; ++ /*dyn_fps;*/ /*dynamic frame rate support*/ ++ ++ /*.flags = PREFER_CMD_SEND_MONOLITHIC | CE_CMD_SEND_MONOLITHIC | RESUME_WITH_PREFER | RESUME_WITH_CE*/ ++ /*gamma-command-monolithic;*/ ++ /*ce-command-monolithic;*/ ++ /*resume-with-gamma;*/ ++ /*resume-with-ce;*/ ++ ++ /*mipi info*/ ++ mipi-byte-clock = <78000>; ++ mipi-escape-clock = <13000>; ++ lane-no = <4>; ++ display_mode = "video_mode"; /*video_mode, command_mode*/ ++ ++ /* ++ auto_stop_clklane_en; ++ im_pin_val;*/ ++ ++ color_bits = ; ++ /*is_18bit_loosely;*/ ++ ++ /*video mode info*/ ++ h-pulse-width = <44>; ++ h-back-porch = <148>; ++ h-front-porch = <88>; ++ v-pulse-width = <5>; ++ v-back-porch = <36>; ++ v-front-porch = <4>; ++ status = "okay"; ++ sync_pol = "vsync_high_act"; /*vsync_high_act, hsync_high_act*/ ++ lp_cmd_en; ++ /*lp_hfp_en;*/ ++ /*lp_hbp_en;*/ ++ /*lp_vact_en;*/ ++ lp_vfp_en; ++ lp_vbp_en; ++ lp_vsa_en; ++ traffic-mode = "burst_with_sync_pulses"; /*non_burst_with_sync_pulses, non_burst_with_sync_events*/ ++ ++ /*phy info*/ ++ data_tprepare = /bits/ 8 <0>; ++ data_hs_zero = /bits/ 8 <0>; ++ data_hs_exit = /bits/ 8 <0>; ++ data_hs_trail = /bits/ 8 <0>; ++ ++ /*te info*/ ++ te_source = "external_pin"; /*external_pin, dsi_te_trigger*/ ++ te_trigger_mode = "rising_edge"; /*rising_edge, high_1000us*/ ++ te_enable = <0>; ++ cm_te_effect_sync_enable = <0>; /*used in command mode*/ ++ te_count_per_sec = <64>; /*used in esd*/ ++ ++ /*ext info*/ ++ /* ++ crc_rx_en; ++ ecc_rx_en; ++ eotp_rx_en; ++ */ ++ eotp_tx_en; ++ ++ dev_read_time = <0x7fff>; ++ /*type cmd return_count return_code*/ ++ /*id_read_cmd_info = [];*/ ++ /*pre_id_cmd = [];*/ ++ /*esd_read_cmd_info = [DCS_CMD 0A 01 9C];*/ ++ /*pre_esd_cmd = [];*/ ++ /*panel-on-command = [];*/ ++ /*panel-off-command = [];*/ ++ /*reset-sequence = <1 5>, <0 10>, <1 30>;*/ ++ /* ++ panel-gamma-warm-command = [ ++ ++ ]; ++ panel-gamma-nature-command = [ ++ ++ ]; ++ panel-gamma-cool-command = [ ++ ++ ]; ++ ++ panel-ce-std-command = [ ++ ++ ]; ++ panel-ce-vivid-command = [ ++ ++ ]; ++ */ ++ }; ++ + seeed_5_inch { + compatible = "starfive,display-dev"; + panel_name = "seeed_5_inch"; -+ panel_lcd_id = <22>; /*480p*/ ++ panel_lcd_id = <22>; /* 480p */ + interface_info = "mipi_interface"; + refresh_en = <1>; + bits-per-pixel = <24>; @@ -127,7 +372,7 @@ index 000000000000..59eece30d398 + */ + eotp_tx_en; + -+ dev_read_time = <0x7FFF>; ++ dev_read_time = <0x7fff>; + /*type cmd return_count return_code*/ + /*id_read_cmd_info = [];*/ + /*pre_id_cmd = [];*/ @@ -156,44 +401,36 @@ index 000000000000..59eece30d398 + */ + }; +}; -diff --git a/arch/riscv/boot/dts/sifive/starfive_vic7100_beagle_v.dts b/arch/riscv/boot/dts/sifive/starfive_vic7100_beagle_v.dts +diff --git a/arch/riscv/boot/dts/starfive/jh7100.dtsi b/arch/riscv/boot/dts/starfive/jh7100.dtsi new file mode 100644 -index 000000000000..3b5b086d0ff7 +index 000000000000..111ef700bbcb --- /dev/null -+++ b/arch/riscv/boot/dts/sifive/starfive_vic7100_beagle_v.dts -@@ -0,0 +1,680 @@ ++++ b/arch/riscv/boot/dts/starfive/jh7100.dtsi +@@ -0,0 +1,737 @@ +/dts-v1/; -+#include "starfive_vic7100_clk.dtsi" -+#include ++#include +#include + -+ +/ { + #address-cells = <2>; + #size-cells = <2>; -+ compatible = "sifive,freedom-u74-arty"; -+ model = "sifive,freedom-u74-arty"; ++ compatible = "starfive,jh7100"; ++ ++ aliases { ++ spi0 = "/soc/spi@11860000"; ++ mshc0 = "/soc/sdio0@10000000"; ++ mshc1 = "/soc/sdio1@10010000"; ++ usb0 = "/soc/usb@104c0000"; ++ }; + + chosen { -+ linux,initrd-start = <0x0 0x86100000>; -+ linux,initrd-end = <0x0 0x8c000000>; -+ stdout-path = "/soc/serial@12440000:115200"; -+ #bootargs = "debug console=ttyS0 rootwait"; + }; -+ aliases { -+ spi0="/soc/qspi@11860000"; -+ mshc0="/soc/sdio0@10000000"; -+ mshc1="/soc/sdio1@10010000"; -+ usb0="/soc/usb@104c0000"; -+ }; -+ cpus: cpus { ++ ++ cpus { + #address-cells = <1>; + #size-cells = <0>; -+ timebase-frequency = <6250000>; -+ compatible = "starfive,fu74-g000"; + cpu@0 { -+ clock-frequency = <0>; -+ compatible = "starfive,rocket0", "riscv"; ++ compatible = "sifive,u74-mc", "riscv"; + d-cache-block-size = <64>; + d-cache-sets = <64>; + d-cache-size = <32768>; @@ -206,13 +443,13 @@ index 000000000000..3b5b086d0ff7 + i-tlb-sets = <1>; + i-tlb-size = <32>; + mmu-type = "riscv,sv39"; -+ next-level-cache = <&cachectrl>; ++ next-level-cache = <&ccache>; + reg = <0>; + riscv,isa = "rv64imafdc"; + starfive,itim = <&itim0>; + status = "okay"; + tlb-split; -+ cpu0intctrl: interrupt-controller { ++ cpu0_intc: interrupt-controller { + #interrupt-cells = <1>; + compatible = "riscv,cpu-intc"; + interrupt-controller; @@ -220,8 +457,7 @@ index 000000000000..3b5b086d0ff7 + }; + + cpu@1 { -+ clock-frequency = <0>; -+ compatible = "starfive,rocket0", "riscv"; ++ compatible = "sifive,u74-mc", "riscv"; + d-cache-block-size = <64>; + d-cache-sets = <64>; + d-cache-size = <32768>; @@ -234,633 +470,34 @@ index 000000000000..3b5b086d0ff7 + i-tlb-sets = <1>; + i-tlb-size = <32>; + mmu-type = "riscv,sv39"; -+ next-level-cache = <&cachectrl>; ++ next-level-cache = <&ccache>; + reg = <1>; + riscv,isa = "rv64imafdc"; + starfive,itim = <&itim1>; + status = "okay"; + tlb-split; -+ cpu1intctrl: interrupt-controller { ++ cpu1_intc: interrupt-controller { + #interrupt-cells = <1>; + compatible = "riscv,cpu-intc"; + interrupt-controller; + }; + }; + }; -+ memory@80000000 { -+ device_type = "memory"; -+ reg = <0x0 0x80000000 0x2 0x0>; -+ }; -+ memory@3000000000 { -+ device_type = "memory"; -+ reg = <0x30 0x0 0x0 0x0>; -+ }; + -+ reserved-memory { -+ #address-cells = <2>; -+ #size-cells = <2>; -+ ranges; -+ -+ linux,cma { -+ compatible = "shared-dma-pool"; -+ reusable; -+ size = <0x0 0x28000000>; -+ alignment = <0x0 0x1000>; -+ alloc-ranges = <0x0 0xa0000000 0x0 0x28000000>; -+ linux,cma-default; -+ }; -+ jpu_reserved: framebuffer@c9000000 { -+ reg = <0x0 0xc9000000 0x0 0x4000000>; -+ }; -+ nvdla_reserved:framebuffer@d0000000{ -+ reg = <0x0 0xd0000000 0x0 0x28000000>; -+ }; -+ -+ vin_reserved: framebuffer@f9000000 { -+ compatible = "shared-dma-pool"; -+ no-map; -+ reg = <0x0 0xf9000000 0x0 0x1000000>; -+ }; -+ -+ sffb_reserved: framebuffer@fb000000 { -+ compatible = "shared-dma-pool"; -+ no-map; -+ reg = <0x0 0xfb000000 0x0 0x2000000>; -+ }; -+ }; -+ -+ soc { -+ #address-cells = <2>; -+ #size-cells = <2>; -+ #clock-cells = <1>; -+ compatible = "starfive,freedom-u74-arty", "simple-bus"; -+ ranges; -+ -+ cachectrl: cache-controller@2010000 { -+ cache-block-size = <64>; -+ cache-level = <2>; -+ cache-sets = <2048>; -+ cache-size = <2097152>; -+ cache-unified; -+ compatible = "sifive,fu540-c000-ccache", "starfive,ccache0", "cache"; -+ interrupt-parent = <&plic>; -+ interrupts = <128 131 129 130>; -+ /*next-level-cache = <&L40 &L36>;*/ -+ reg = <0x0 0x2010000 0x0 0x1000 0x0 0x8000000 0x0 0x2000000>; -+ reg-names = "control", "sideband"; -+ }; -+ -+ -+ dtim: dtim@1000000 { -+ compatible = "starfive,dtim0"; -+ reg = <0x0 0x1000000 0x0 0x2000>; -+ reg-names = "mem"; -+ }; -+ -+ itim0: itim@1808000 { -+ compatible = "starfive,itim0"; -+ reg = <0x0 0x1808000 0x0 0x8000>; -+ reg-names = "mem"; -+ }; -+ -+ itim1: itim@1820000 { -+ compatible = "starfive,itim0"; -+ reg = <0x0 0x1820000 0x0 0x8000>; -+ reg-names = "mem"; -+ }; -+ -+ clint: clint@2000000 { -+ #interrupt-cells = <1>; -+ compatible = "riscv,clint0"; -+ interrupts-extended = <&cpu0intctrl 3 &cpu0intctrl 7 &cpu1intctrl 3 &cpu1intctrl 7 >; -+ reg = <0x0 0x2000000 0x0 0x10000>; -+ reg-names = "control"; -+ }; -+ plic: plic@c000000 { -+ #interrupt-cells = <1>; -+ compatible = "riscv,plic0"; -+ interrupt-controller; -+ interrupts-extended = <&cpu0intctrl 11 &cpu0intctrl 9 &cpu1intctrl 11 &cpu1intctrl 9 >; -+ reg = <0x0 0xc000000 0x0 0x4000000>; -+ reg-names = "control"; -+ riscv,max-priority = <7>; -+ riscv,ndev = <127>; -+ }; -+ -+ uart3: serial@12440000 { -+ compatible = "snps,dw-apb-uart", "starfive,uart0"; -+ interrupt-parent = <&plic>; -+ interrupts = <73>; -+ reg = <0x0 0x12440000 0x0 0x10000>; -+ reg-io-width = <4>; -+ reg-shift = <2>; -+ clocks = <&uartclk>, <&apb2clk>; -+ clock-names = "baudclk", "apb_pclk"; -+ current-clock = <100000000>; -+ current-speed = <115200>; -+ status = "okay"; -+ }; -+ uart2: serial@12430000 { -+ compatible = "snps,dw-apb-uart"; -+ interrupt-parent = <&plic>; -+ interrupts = <72>; -+ reg = <0x0 0x12430000 0x0 0x10000>; -+ reg-io-width = <4>; -+ reg-shift = <2>; -+ clocks = <&uartclk>, <&apb2clk>; -+ clock-names = "baudclk", "apb_pclk"; -+ current-clock = <100000000>; -+ current-speed = <115200>; -+ status = "disabled"; -+ }; -+ uart1: hs_serial@11880000 { -+ compatible = "snps,dw-apb-uart"; -+ interrupt-parent = <&plic>; -+ interrupts = <93>; -+ reg = <0x0 0x11880000 0x0 0x10000>; -+ reg-io-width = <4>; -+ reg-shift = <2>; -+ clocks = <&hs_uartclk>, <&apb1clk>; -+ clock-names = "baudclk","apb_pclk"; -+ current-clock = <74250000>; -+ current-speed = <115200>; -+ status = "disabled"; -+ }; -+ uart0: hs_serial@11870000 { -+ compatible = "snps,dw-apb-uart"; -+ interrupt-parent = <&plic>; -+ interrupts = <92>; -+ reg = <0x0 0x11870000 0x0 0x10000>; -+ reg-io-width = <4>; -+ reg-shift = <2>; -+ clocks = <&hs_uartclk>, <&apb1clk>; -+ clock-names = "baudclk", "apb_pclk"; -+ current-clock = <74250000>; -+ current-speed = <115200>; -+ status = "okay"; -+ }; -+ -+ dma2p: sgdma2p@100b0000 { -+ compatible = "snps,axi-dma-1.01a"; -+ reg = <0x0 0x100b0000 0x0 0x10000>; -+ clocks = <&axiclk>,<&ahb0clk>; -+ clock-names = "core-clk", "cfgr-clk"; -+ interrupt-parent = <&plic>; -+ interrupts = <2>; -+ dma-channels = <4>; -+ snps,dma-masters = <1>; -+ snps,data-width = <4>; -+ snps,block-size = <4096 4096 4096 4096>; -+ snps,priority = <0 1 2 3>; -+ snps,axi-max-burst-len = <128>; -+ status = "okay"; -+ }; -+ -+ dma1p: sgdma1p@10500000 { -+ compatible = "snps,axi-dma-1.01a"; -+ reg = <0x0 0x10500000 0x0 0x10000>; -+ clocks = <&axiclk>,<&ahb0clk>; -+ clock-names = "core-clk", "cfgr-clk"; -+ interrupt-parent = <&plic>; -+ interrupts = <1>; -+ dma-channels = <16>; -+ snps,dma-masters = <1>; -+ snps,data-width = <3>; -+ snps,block-size = <4096 4096 4096 4096 4096 4096 4096 4096 4096 4096 4096 4096 4096 4096 4096 4096>; -+ snps,priority = <0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15>; -+ snps,axi-max-burst-len = <64>; -+ status = "okay"; -+ }; -+ -+ USB30: usb@104c0000 { -+ compatible = "cdns,usb3"; -+ reg = <0x0 0x104c0000 0x0 0x10000>, // memory area for HOST registers -+ <0x0 0x104d0000 0x0 0x10000>, // memory area for DEVICE registers -+ <0x0 0x104e0000 0x0 0x10000>; // memory area for OTG/DRD registers -+ reg-names = "otg", "xhci", "dev"; -+ interrupt-parent = <&plic>; -+ interrupts = <43>, <44>, <52>; -+ interrupt-names = "otg", -+ "host", -+ "peripheral"; -+ phy-names = "cdns3,usb3-phy", "cnds3,usb2-phy"; -+ status = "okay"; -+ }; -+ -+ -+ gpio: gpio@11910000 { -+ compatible = "starfive,gpio0"; -+ interrupt-parent = <&plic>; -+ interrupts = <32>; -+ reg = <0x0 0x11910000 0x0 0x10000>; -+ reg-names = "control"; -+ interrupt-controller; -+ #gpio-cells = <2>; -+ }; -+ gpiorst:gpio-restart { -+ compatible = "gpio-restart"; -+ gpios = <&gpio 63 GPIO_ACTIVE_HIGH>; -+ }; -+ gpiopof:gpio-poweroff { -+ compatible = "gpio-poweroff"; -+ gpios = <&gpio 63 GPIO_ACTIVE_HIGH>; -+ }; -+ -+ i2c0: i2c@118b0000 { -+ #address-cells = <1>; -+ #size-cells = <0>; -+ #clock-cells = <0>; -+ compatible = "snps,designware-i2c"; -+ reg = <0x0 0x118b0000 0x0 0x10000>; -+ interrupt-parent = <&plic>; -+ interrupts = <96>; -+ clocks = <49500000>; -+ clock-frequency = <100000>; -+ i2c-sda-hold-time-ns = <300>; -+ i2c-sda-falling-time-ns = <500>; -+ i2c-scl-falling-time-ns = <500>; -+ scl-gpio = <&gpio 62 0>; -+ sda-gpio = <&gpio 61 0>; -+ -+ tda998x@70 { -+ compatible = "nxp,tda998x"; -+ reg = <0x70>; -+ }; -+ -+ imx219@10 { -+ compatible = "imx219"; -+ reg = <0x10>; -+ reset-gpio = <&gpio 58 0>; -+ }; -+ }; -+ -+ i2c1: i2c@118c0000 { -+ #address-cells = <1>; -+ #size-cells = <0>; -+ #clock-cells = <0>; -+ compatible = "snps,designware-i2c"; -+ reg = <0x0 0x118c0000 0x0 0x10000>; -+ interrupt-parent = <&plic>; -+ interrupts = <97>; -+ clocks = <49500000>; -+ clock-frequency = <400000>; -+ i2c-sda-hold-time-ns = <300>; -+ i2c-sda-falling-time-ns = <100>; -+ i2c-scl-falling-time-ns = <100>; -+ scl-gpio = <&gpio 47 0>; -+ sda-gpio = <&gpio 48 0>; -+ }; -+ -+ i2c2: i2c@12450000 { -+ #address-cells = <1>; -+ #size-cells = <0>; -+ #clock-cells = <0>; -+ compatible = "snps,designware-i2c"; -+ reg = <0x0 0x12450000 0x0 0x10000>; -+ interrupt-parent = <&plic>; -+ interrupts = <74>; -+ clocks = <50000000>; -+ clock-frequency = <100000>; -+ i2c-sda-hold-time-ns = <300>; -+ i2c-sda-falling-time-ns = <500>; -+ i2c-scl-falling-time-ns = <500>; -+ scl-gpio = <&gpio 60 0>; -+ sda-gpio = <&gpio 59 0>; -+ -+ seeed_plane_i2c@45 { -+ compatible = "seeed_panel"; -+ reg = <0x45>; -+ }; -+ }; -+ -+ trng: trng@118d0000 { -+ compatible = "starfive,vic-rng"; -+ reg = <0x0 0x118d0000 0x0 0x10000>; -+ interrupt-parent = <&plic>; -+ interrupts = <98>; -+ clocks = <&hfclk>; -+ }; -+ crypto: crypto@100d0000 { -+ compatible = "starfive,vic-sec"; -+ reg = <0x0 0x100d0000 0x0 0x20000>, -+ <0x0 0x11800234 0x0 0xc>; -+ reg-names = "secmem","secclk"; -+ interrupt-parent = <&plic>; -+ interrupts = <31>; -+ clocks = <&hfclk>; -+ }; -+ -+ /*gmac device configuration*/ -+ stmmac_axi_setup: stmmac-axi-config { -+ snps,wr_osr_lmt = <0xf>; -+ snps,rd_osr_lmt = <0xf>; -+ snps,blen = <256 128 64 32 0 0 0>; -+ }; -+ gmac:gmac@10020000{ -+ compatible = "snps,dwmac"; -+ reg = <0x0 0x10020000 0x0 0x10000>; -+ interrupt-parent = <&plic>; -+ interrupts = <6 7>; -+ interrupt-names = "macirq","eth_wake_irq"; -+ max-frame-size = <9000>; -+ phy-mode = "rgmii-txid"; -+ snps,multicast-filter-bins = <256>; -+ snps,perfect-filter-entries = <128>; -+ rx-fifo-depth = <32768>; -+ tx-fifo-depth = <16384>; -+ clocks = <&gmacclk>; -+ clock-names = "stmmaceth"; -+ snps,fixed-burst = <1>; -+ snps,no-pbl-x8 = <1>; -+ /*snps,force_sf_dma_mode;*/ -+ snps,force_thresh_dma_mode; -+ snps,axi-config = <&stmmac_axi_setup>; -+ }; -+ -+ nbdla: nvdla@0x11940000 { -+ compatible = "nvidia,nvdla_os_initial"; -+ interrupt-parent = <&plic>; -+ interrupts = <22>; -+ memory-region = <&nvdla_reserved>; -+ reg = <0x0 0x11940000 0x0 0x40000>; -+ status = "okay"; -+ }; -+ -+ jpu:coadj12@11900000 { -+ compatible = "cm,codaj12-jpu-1"; -+ reg = <0x0 0x11900000 0x0 0x300>; -+ memory-region = <&jpu_reserved>; -+ interrupt-parent = <&plic>; -+ interrupts = <24>; -+ clocks = <&jpuclk>; -+ clock-names = "jpege"; -+ reg-names = "control"; -+ status = "okay"; -+ }; -+ -+ vpu_dec:vpu_dec@118F0000 { -+ compatible = "c&m,cm511-vpu"; -+ reg = <0 0x118F0000 0 0x10000>; -+ //memory-region = <&vpu_reserved>; -+ interrupt-parent = <&plic>; -+ interrupts = <23>; -+ clocks = <&vpuclk>; -+ clock-names = "vcodec"; -+ status = "okay"; -+ }; -+ -+ vpu_enc:vpu_enc@118E0000 { -+ compatible = "cm,cm521-vpu"; -+ reg = <0x0 0x118E0000 0x0 0x4000>; -+ interrupt-parent = <&plic>; -+ interrupts = <26>; -+ clocks = <&vpuclk>; -+ clock-names = "vcodec"; -+ reg-names = "control"; -+ }; -+ -+ ptc: pwm@12490000 { -+ compatible = "starfive,pwm0"; -+ reg = <0x0 0x12490000 0x0 0x10000>; -+ reg-names = "control"; -+ sifive,approx-period = <100000000>; -+ clocks = <&pwmclk>; -+ #pwm-cells=<3>; -+ sifive,npwm = <8>; -+ -+ }; -+ -+ qspi:qspi@11860000 { -+ compatible = "cadence,qspi","cdns,qspi-nor"; -+ #address-cells = <1>; -+ #size-cells = <0>; -+ reg = <0x0 0x11860000 0x0 0x10000 0x0 0x20000000 0x0 0x20000000 >; -+ interrupts = <3>; -+ interrupt-parent = <&plic>; -+ clocks = <&qspi_clk>; -+ cdns,fifo-depth = <256>; -+ cdns,fifo-width = <4>; -+ cdns,trigger-address = <0x00000000>; -+ status = "okay"; -+ spi-max-frequency = <250000000>; -+ nor_flash:nor-flash@0 { -+ compatible = "spi-flash"; -+ reg=<0>; -+ spi-max-frequency = <31250000>; -+ page-size = <256>; -+ block-size = <16>; -+ cdns,read-delay = <4>; -+ cdns,tshsl-ns = <1>; -+ cdns,tsd2d-ns = <1>; -+ cdns,tchsh-ns = <1>; -+ cdns,tslch-ns = <1>; -+ spi-tx-bus-width = <1>; -+ spi-rx-bus-width = <1>; -+ }; -+ nand_flash:nand-flash@1 { -+ compatible = "spi-flash-nand"; -+ reg=<1>; -+ spi-max-frequency = <31250000>; -+ page-size = <2048>; -+ block-size = <17>; -+ cdns,read-delay = <4>; -+ cdns,tshsl-ns = <1>; -+ cdns,tsd2d-ns = <1>; -+ cdns,tchsh-ns = <1>; -+ cdns,tslch-ns = <1>; -+ spi-tx-bus-width = <1>; -+ spi-rx-bus-width = <1>; -+ }; -+ }; -+ -+ spi2:spi2@12410000 { -+ compatible = "snps,dw-apb-ssi"; -+ #address-cells = <1>; -+ #size-cells = <0>; -+ interrupt-parent = <&plic>; -+ interrupts = <70>; -+ reg = <0x0 0x12410000 0x0 0x10000>; -+ clocks = <&spiclk>; -+ /*num-cs = <1>; -+ cs-gpios = <&gpio 0 0>;*/ -+ spi_dev0: spi@0 { -+ compatible = "rohm,dh2228fv"; -+ spi-max-frequency = <10000000>; -+ reg = <0>; -+ status = "okay"; -+ }; -+ }; -+ -+ xrp@0 { -+ compatible = "cdns,xrp"; -+ reg = <0x0 0xf0000000 0x0 0x01ffffff -+ 0x10 0x72000000 0x0 0x00001000 -+ 0x10 0x72001000 0x0 0x00fff000 -+ 0x0 0x124b0000 0x0 0x00010000>; -+ clocks = <&hfclk>; -+ interrupt-parent = <&plic>; -+ firmware-name = "vp6_elf"; -+ dsp-irq = <19 20>; -+ dsp-irq-src = <0x20 0x21>; -+ intc-irq-mode = <1>; -+ intc-irq = <0 1>; -+ interrupts = <27 28>; -+ #address-cells = <1>; -+ #size-cells = <1>; -+ ranges = <0x40000000 0x0 0x40000000 0x01000000 -+ 0xb0000000 0x10 0x70000000 0x3000000>; -+ dsp@0 { -+ }; -+ }; -+ sdio0:sdio0@10000000{ -+ compatible = "snps,dw-mshc"; -+ reg = <0x0 0x10000000 0x0 0x10000>; -+ interrupts = <4>; -+ interrupt-parent = <&plic>; -+ clocks = <&dwmmc_biuclk>; -+ clock-names = "biu"; -+ clock-frequency = <100000000>; -+ max-frequency = <10000000>; -+ fifo-depth = <32>; -+ card-detect-delay = <300>; -+ fifo-watermark-aligned; -+ data-addr = <0>; -+ bus-width = <4>; -+ cap-sd-highspeed; -+ broken-cd; -+ no-sdio; -+ post-power-on-delay-ms = <200>; -+ }; -+ sdio1:sdio1@10010000{ -+ compatible = "snps,dw-mshc"; -+ reg = <0x0 0x10010000 0x0 0x10000>; -+ interrupts = <5>; -+ interrupt-parent = <&plic>; -+ clocks = <&dwmmc_biuclk>; -+ clock-names = "biu"; -+ clock-frequency = <100000000>; -+ max-frequency = <10000000>; -+ fifo-depth = <32>; -+ card-detect-delay = <300>; -+ fifo-watermark-aligned; -+ data-addr = <0>; -+ bus-width = <4>; -+ cap-sd-highspeed; -+ /*broken-cd;*/ -+ cap-sdio-irq; -+ cap-mmc-hw-reset; -+ non-removable; -+ enable-sdio-wakeup; -+ keep-power-in-suspend; -+ /*cap-power-off-card;*/ -+ cap-mmc-highspeed; -+ /*fixed-emmc-driver-type;*/ -+ post-power-on-delay-ms = <200>; -+ /* -+ bcmdhd_wlan: bcmdhd_wlan@1 { -+ compatible = "android,bcmdhd_wlan"; -+ gpios = <&gpio 26 0>; -+ }; -+ */ -+ }; -+ -+ sfivefb:sfivefb@12000000 { -+ compatible = "starfive,vpp-lcdc"; -+ interrupt-parent = <&plic>; -+ interrupts = <101>, <103>; -+ interrupt-names = "lcdc_irq", "vpp1_irq"; -+ reg = <0x0 0x12000000 0x0 0x10000>, -+ <0x0 0x12100000 0x0 0x10000>, -+ <0x0 0x12040000 0x0 0x10000>, -+ <0x0 0x12080000 0x0 0x10000>, -+ <0x0 0x120c0000 0x0 0x10000>, -+ <0x0 0x12240000 0x0 0x10000>, -+ <0x0 0x12250000 0x0 0x10000>, -+ <0x0 0x12260000 0x0 0x10000>; -+ reg-names = "lcdc", "dsitx", "vpp0", "vpp1", "vpp2", "clk", "rst", "sys"; -+ memory-region = <&sffb_reserved>; -+ clocks = <&uartclk>, <&apb2clk>; -+ clock-names = "baudclk", "apb_pclk"; -+ status = "okay"; -+ ddr-format = ;/*LCDC win_format*/ -+ -+ /*pp1 { -+ pp-id = <1>; -+ fifo-out; -+ src-format = ; -+ src-width = <800>; -+ src-height = <480>; -+ dst-format = ; -+ dst-width = <800>; -+ dst-height = <480>; -+ };*/ -+ }; -+ -+ vin_sysctl:vin_sysctl@19800000 { -+ compatible = "starfive,stf-vin"; -+ reg = <0x0 0x19800000 0x0 0x10000>, -+ <0x0 0x19810000 0x0 0x10000>, -+ <0x0 0x19820000 0x0 0x10000>, -+ <0x0 0x19830000 0x0 0x10000>, -+ <0x0 0x19840000 0x0 0x10000>, -+ <0x0 0x19870000 0x0 0x30000>, -+ <0x0 0x198a0000 0x0 0x30000>, -+ <0x0 0x11800000 0x0 0x10000>, -+ <0x0 0x11840000 0x0 0x10000>, -+ <0x0 0x11858000 0x0 0x10000>; -+ reg-names = "mipi0", "vclk", "vrst", "mipi1", "sctrl", "isp0", "isp1", "tclk", "trst", "iopad"; interrupt-parent = <&plic>; -+ interrupts = <119 109>; -+ memory-region = <&vin_reserved>; -+ /*defaule config for imx219 vin&isp*/ -+ format = ; -+ frame-width = <800>; -+ frame-height =<480>; -+ isp0_enable; -+ csi-lane = <2>; -+ csi-dlane-swaps = /bits/ 8 <1>,/bits/ 8 <2>,/bits/ 8 <3>,/bits/ 8 <4>; -+ csi-dlane-pn-swaps = /bits/ 8 <0>,/bits/ 8 <0>,/bits/ 8 <0>,/bits/ 8 <0>; -+ csi-clane-swap = /bits/ 8 <0>; -+ csi-clane-pn-swap = /bits/ 8 <0>; -+ csi-mipiID = <0>; -+ csi-width = <1920>; -+ csi-height = <1080>; -+ csi-dt = <0x2b>; -+ }; -+ sfc_tmp:tmpsensor@124A0000 { -+ compatible = "sfc,tempsensor"; -+ reg = <0x0 0x124A0000 0x0 0x1000>; -+ interrupt-parent = <&plic>; -+ interrupts = <122>; -+ status = "okay"; -+ }; -+ otp:otp@11810000{ -+ compatible = "starfive,fu740-otp"; -+ reg = <0x0 0x11810000 0x0 0x10000>; -+ fuse-count = <0x200>; -+ }; -+ }; -+}; -+#include "tda998x_1080p.dtsi" -+#include "seeed5inch.dtsi" -diff --git a/arch/riscv/boot/dts/sifive/starfive_vic7100_clk.dtsi b/arch/riscv/boot/dts/sifive/starfive_vic7100_clk.dtsi -new file mode 100644 -index 000000000000..f3d571420abb ---- /dev/null -+++ b/arch/riscv/boot/dts/sifive/starfive_vic7100_clk.dtsi -@@ -0,0 +1,109 @@ -+/ { + hfclk: hfclk { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-frequency = <25000000>; + clock-output-names = "hfclk"; + }; ++ + rtcclk: rtcclk { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-frequency = <6250000>; + clock-output-names = "rtcclk"; + }; ++ + i2c0clk: i2c0clk { + #clock-cells = <0>; + compatible = "fixed-clock"; @@ -887,63 +524,75 @@ index 000000000000..f3d571420abb + compatible = "fixed-clock"; + clock-frequency = <250000000>; + }; ++ + ahb2clk: ahb2clk { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-frequency = <125000000>; + }; ++ + apb1clk: apb1clk { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-frequency = <125000000>; + }; ++ + apb2clk: apb2clk { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-frequency = <125000000>; + }; ++ + jpuclk: jpuclk { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-frequency = <333333333>; + }; ++ + vpuclk: vpuclk { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-frequency = <400000000>; + }; ++ + gmacclk: gmacclk { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-frequency = <25000000>; + }; ++ + qspi_clk: qspi-clk@0 { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-frequency = <50000000>; + }; ++ + uartclk: uartclk { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-frequency = <100000000>; + }; ++ + hs_uartclk: hs_uartclk { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-frequency = <74250000>; + }; ++ + dwmmc_biuclk: dwmmc_biuclk { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-frequency = <100000000>; + }; -+/* ++ ++ /* + dwmmc_ciuclk: dwmmc_ciuclk { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-frequency = <100000000>; + }; -+*/ ++ */ ++ + spiclk: spiclk { + #clock-cells = <0>; + compatible = "fixed-clock"; @@ -956,124 +605,550 @@ index 000000000000..f3d571420abb + clock-frequency = <125000000>; + }; + -+}; -diff --git a/arch/riscv/boot/dts/sifive/tda998x_1080p.dtsi b/arch/riscv/boot/dts/sifive/tda998x_1080p.dtsi -new file mode 100644 -index 000000000000..23954092e3a2 ---- /dev/null -+++ b/arch/riscv/boot/dts/sifive/tda998x_1080p.dtsi -@@ -0,0 +1,106 @@ -+#include ++ memory@80000000 { ++ device_type = "memory"; ++ reg = <0x0 0x80000000 0x2 0x0>; ++ }; + -+&sfivefb { -+ tda_998x_1080p { -+ compatible = "starfive,display-dev"; -+ panel_name = "tda_998x_1080p"; -+ panel_lcd_id = <22>; /*1080p*/ -+ interface_info = "rgb_interface"; -+ refresh_en = <1>; -+ bits-per-pixel = <16>; -+ physical-width = <62>; -+ physical-height = <114>; -+ panel-width = <1920>; -+ panel-height = <1080>; -+ pixel-clock = <78000000>; -+ /*dyn_fps;*/ /*dynamic frame rate support*/ ++ memory@3000000000 { ++ device_type = "memory"; ++ reg = <0x30 0x0 0x0 0x0>; ++ }; + -+ /*.flags = PREFER_CMD_SEND_MONOLITHIC | CE_CMD_SEND_MONOLITHIC | RESUME_WITH_PREFER | RESUME_WITH_CE*/ -+ /*gamma-command-monolithic;*/ -+ /*ce-command-monolithic;*/ -+ /*resume-with-gamma;*/ -+ /*resume-with-ce;*/ ++ reserved-memory { ++ #address-cells = <2>; ++ #size-cells = <2>; ++ ranges; + -+ /*mipi info*/ -+ mipi-byte-clock = <78000>; -+ mipi-escape-clock = <13000>; -+ lane-no = <4>; -+ display_mode = "video_mode"; /*video_mode, command_mode*/ ++ linux,cma { ++ compatible = "shared-dma-pool"; ++ reusable; ++ size = <0x0 0x28000000>; ++ alignment = <0x0 0x1000>; ++ alloc-ranges = <0x0 0xa0000000 0x0 0x28000000>; ++ linux,cma-default; ++ }; + -+ /* -+ auto_stop_clklane_en; -+ im_pin_val;*/ ++ jpu_reserved: framebuffer@c9000000 { ++ reg = <0x0 0xc9000000 0x0 0x4000000>; ++ }; + ++ nvdla_reserved:framebuffer@d0000000 { ++ reg = <0x0 0xd0000000 0x0 0x28000000>; ++ }; + -+ color_bits = ; -+ /*is_18bit_loosely;*/ ++ vin_reserved: framebuffer@f9000000 { ++ compatible = "shared-dma-pool"; ++ no-map; ++ reg = <0x0 0xf9000000 0x0 0x1000000>; ++ }; + -+ /*video mode info*/ -+ h-pulse-width = <44>; -+ h-back-porch = <148>; -+ h-front-porch = <88>; -+ v-pulse-width = <5>; -+ v-back-porch = <36>; -+ v-front-porch = <4>; -+ status = "okay"; -+ sync_pol = "vsync_high_act"; /*vsync_high_act, hsync_high_act*/ -+ lp_cmd_en; -+ /*lp_hfp_en;*/ -+ /*lp_hbp_en;*/ -+ /*lp_vact_en;*/ -+ lp_vfp_en; -+ lp_vbp_en; -+ lp_vsa_en; -+ traffic-mode = "burst_with_sync_pulses"; /*non_burst_with_sync_pulses, non_burst_with_sync_events*/ ++ sffb_reserved: framebuffer@fb000000 { ++ compatible = "shared-dma-pool"; ++ no-map; ++ reg = <0x0 0xfb000000 0x0 0x2000000>; ++ }; ++ }; + -+ /*phy info*/ -+ data_tprepare = /bits/ 8 <0>; -+ data_hs_zero = /bits/ 8 <0>; -+ data_hs_exit = /bits/ 8 <0>; -+ data_hs_trail = /bits/ 8 <0>; ++ soc { ++ #address-cells = <2>; ++ #size-cells = <2>; ++ #clock-cells = <1>; ++ compatible = "starfive,jh7100", "simple-bus"; ++ ranges; + -+ /*te info*/ -+ te_source = "external_pin"; /*external_pin, dsi_te_trigger*/ -+ te_trigger_mode = "rising_edge"; /*rising_edge, high_1000us*/ -+ te_enable = <0>; -+ cm_te_effect_sync_enable = <0>; /*used in command mode*/ -+ te_count_per_sec = <64>; /*used in esd*/ ++ ccache: cache-controller@2010000 { ++ cache-block-size = <64>; ++ cache-level = <2>; ++ cache-sets = <2048>; ++ cache-size = <2097152>; ++ cache-unified; ++ compatible = "sifive,fu540-c000-ccache", "starfive,ccache0", "cache"; ++ interrupt-parent = <&plic>; ++ interrupts = <128 131 129 130>; ++ /*next-level-cache = <&L40 &L36>;*/ ++ reg = <0x0 0x2010000 0x0 0x1000 0x0 0x8000000 0x0 0x2000000>; ++ reg-names = "control", "sideband"; ++ }; + -+ /*ext info*/ -+ /* -+ crc_rx_en; -+ ecc_rx_en; -+ eotp_rx_en; -+ */ -+ eotp_tx_en; ++ dtim: dtim@1000000 { ++ compatible = "starfive,dtim0"; ++ reg = <0x0 0x1000000 0x0 0x2000>; ++ reg-names = "mem"; ++ }; + -+ dev_read_time = <0x7FFF>; -+ /*type cmd return_count return_code*/ -+ /*id_read_cmd_info = [];*/ -+ /*pre_id_cmd = [];*/ -+ /*esd_read_cmd_info = [DCS_CMD 0A 01 9C];*/ -+ /*pre_esd_cmd = [];*/ -+ /*panel-on-command = [];*/ -+ /*panel-off-command = [];*/ -+ /*reset-sequence = <1 5>, <0 10>, <1 30>;*/ -+ /* -+ panel-gamma-warm-command = [ ++ itim0: itim@1808000 { ++ compatible = "starfive,itim0"; ++ reg = <0x0 0x1808000 0x0 0x8000>; ++ reg-names = "mem"; ++ }; + -+ ]; -+ panel-gamma-nature-command = [ ++ itim1: itim@1820000 { ++ compatible = "starfive,itim0"; ++ reg = <0x0 0x1820000 0x0 0x8000>; ++ reg-names = "mem"; ++ }; + -+ ]; -+ panel-gamma-cool-command = [ ++ clint: clint@2000000 { ++ #interrupt-cells = <1>; ++ compatible = "riscv,clint0"; ++ interrupts-extended = <&cpu0_intc 3 &cpu0_intc 7 &cpu1_intc 3 &cpu1_intc 7>; ++ reg = <0x0 0x2000000 0x0 0x10000>; ++ reg-names = "control"; ++ }; + -+ ]; ++ plic: plic@c000000 { ++ #interrupt-cells = <1>; ++ compatible = "riscv,plic0"; ++ interrupt-controller; ++ interrupts-extended = <&cpu0_intc 11 &cpu0_intc 9 &cpu1_intc 11 &cpu1_intc 9>; ++ reg = <0x0 0xc000000 0x0 0x4000000>; ++ reg-names = "control"; ++ riscv,max-priority = <7>; ++ riscv,ndev = <127>; ++ }; + -+ panel-ce-std-command = [ ++ uart0: hs_serial@11870000 { ++ compatible = "snps,dw-apb-uart"; ++ interrupt-parent = <&plic>; ++ interrupts = <92>; ++ reg = <0x0 0x11870000 0x0 0x10000>; ++ reg-io-width = <4>; ++ reg-shift = <2>; ++ clocks = <&hs_uartclk>, <&apb1clk>; ++ clock-names = "baudclk", "apb_pclk"; ++ current-clock = <74250000>; ++ current-speed = <115200>; ++ status = "disabled"; ++ }; + -+ ]; -+ panel-ce-vivid-command = [ ++ uart1: hs_serial@11880000 { ++ compatible = "snps,dw-apb-uart"; ++ interrupt-parent = <&plic>; ++ interrupts = <93>; ++ reg = <0x0 0x11880000 0x0 0x10000>; ++ reg-io-width = <4>; ++ reg-shift = <2>; ++ clocks = <&hs_uartclk>, <&apb1clk>; ++ clock-names = "baudclk", "apb_pclk"; ++ current-clock = <74250000>; ++ current-speed = <115200>; ++ status = "disabled"; ++ }; + -+ ]; -+ */ ++ uart2: serial@12430000 { ++ compatible = "snps,dw-apb-uart"; ++ interrupt-parent = <&plic>; ++ interrupts = <72>; ++ reg = <0x0 0x12430000 0x0 0x10000>; ++ reg-io-width = <4>; ++ reg-shift = <2>; ++ clocks = <&uartclk>, <&apb2clk>; ++ clock-names = "baudclk", "apb_pclk"; ++ current-clock = <100000000>; ++ current-speed = <115200>; ++ status = "disabled"; ++ }; ++ ++ uart3: serial@12440000 { ++ compatible = "snps,dw-apb-uart", "starfive,uart0"; ++ interrupt-parent = <&plic>; ++ interrupts = <73>; ++ reg = <0x0 0x12440000 0x0 0x10000>; ++ reg-io-width = <4>; ++ reg-shift = <2>; ++ clocks = <&uartclk>, <&apb2clk>; ++ clock-names = "baudclk", "apb_pclk"; ++ current-clock = <100000000>; ++ current-speed = <115200>; ++ status = "disabled"; ++ }; ++ ++ dma2p: sgdma2p@100b0000 { ++ compatible = "snps,axi-dma-1.01a"; ++ reg = <0x0 0x100b0000 0x0 0x10000>; ++ clocks = <&axiclk>, <&ahb0clk>; ++ clock-names = "core-clk", "cfgr-clk"; ++ interrupt-parent = <&plic>; ++ interrupts = <2>; ++ dma-channels = <4>; ++ snps,dma-masters = <1>; ++ snps,data-width = <4>; ++ snps,block-size = <4096 4096 4096 4096>; ++ snps,priority = <0 1 2 3>; ++ snps,axi-max-burst-len = <128>; ++ status = "okay"; ++ }; ++ ++ dma1p: sgdma1p@10500000 { ++ compatible = "snps,axi-dma-1.01a"; ++ reg = <0x0 0x10500000 0x0 0x10000>; ++ clocks = <&axiclk>, <&ahb0clk>; ++ clock-names = "core-clk", "cfgr-clk"; ++ interrupt-parent = <&plic>; ++ interrupts = <1>; ++ dma-channels = <16>; ++ snps,dma-masters = <1>; ++ snps,data-width = <3>; ++ snps,block-size = <4096 4096 4096 4096 4096 4096 4096 4096 4096 4096 4096 4096 4096 4096 4096 4096>; ++ snps,priority = <0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15>; ++ snps,axi-max-burst-len = <64>; ++ status = "okay"; ++ }; ++ ++ usb3: usb@104c0000 { ++ compatible = "cdns,usb3"; ++ reg = <0x0 0x104c0000 0x0 0x10000>, // memory area for HOST registers ++ <0x0 0x104d0000 0x0 0x10000>, // memory area for DEVICE registers ++ <0x0 0x104e0000 0x0 0x10000>; // memory area for OTG/DRD registers ++ reg-names = "otg", "xhci", "dev"; ++ interrupt-parent = <&plic>; ++ interrupts = <43>, <44>, <52>; ++ interrupt-names = "otg", ++ "host", ++ "peripheral"; ++ phy-names = "cdns3,usb3-phy", "cdns3,usb2-phy"; ++ maximum-speed = "super-speed"; ++ status = "disabled"; ++ }; ++ ++ gpio: gpio@11910000 { ++ compatible = "starfive,gpio0"; ++ interrupt-parent = <&plic>; ++ interrupts = <32>; ++ reg = <0x0 0x11910000 0x0 0x10000>; ++ reg-names = "control"; ++ interrupt-controller; ++ #gpio-cells = <2>; ++ }; ++ ++ gpiopof: gpio-poweroff { ++ compatible = "gpio-poweroff"; ++ gpios = <&gpio 63 GPIO_ACTIVE_HIGH>; ++ }; ++ ++ i2c0: i2c@118b0000 { ++ #address-cells = <1>; ++ #size-cells = <0>; ++ #clock-cells = <0>; ++ compatible = "snps,designware-i2c"; ++ reg = <0x0 0x118b0000 0x0 0x10000>; ++ interrupt-parent = <&plic>; ++ interrupts = <96>; ++ clocks = <&i2c0clk>; ++ clock-frequency = <100000>; ++ i2c-sda-hold-time-ns = <300>; ++ i2c-sda-falling-time-ns = <500>; ++ i2c-scl-falling-time-ns = <500>; ++ scl-gpio = <&gpio 62 0>; ++ sda-gpio = <&gpio 61 0>; ++ }; ++ ++ i2c1: i2c@118c0000 { ++ #address-cells = <1>; ++ #size-cells = <0>; ++ #clock-cells = <0>; ++ compatible = "snps,designware-i2c"; ++ reg = <0x0 0x118c0000 0x0 0x10000>; ++ interrupt-parent = <&plic>; ++ interrupts = <97>; ++ clocks = <&i2c0clk>; ++ clock-frequency = <400000>; ++ i2c-sda-hold-time-ns = <300>; ++ i2c-sda-falling-time-ns = <100>; ++ i2c-scl-falling-time-ns = <100>; ++ scl-gpio = <&gpio 47 0>; ++ sda-gpio = <&gpio 48 0>; ++ }; ++ ++ i2c2: i2c@12450000 { ++ #address-cells = <1>; ++ #size-cells = <0>; ++ #clock-cells = <0>; ++ compatible = "snps,designware-i2c"; ++ reg = <0x0 0x12450000 0x0 0x10000>; ++ interrupt-parent = <&plic>; ++ interrupts = <74>; ++ clocks = <&i2c2clk>; ++ clock-frequency = <100000>; ++ i2c-sda-hold-time-ns = <300>; ++ i2c-sda-falling-time-ns = <500>; ++ i2c-scl-falling-time-ns = <500>; ++ scl-gpio = <&gpio 60 0>; ++ sda-gpio = <&gpio 59 0>; ++ }; ++ ++ trng: trng@118d0000 { ++ compatible = "starfive,vic-rng"; ++ reg = <0x0 0x118d0000 0x0 0x10000>; ++ interrupt-parent = <&plic>; ++ interrupts = <98>; ++ clocks = <&hfclk>; ++ }; ++ ++ crypto: crypto@100d0000 { ++ compatible = "starfive,vic-sec"; ++ reg = <0x0 0x100d0000 0x0 0x20000>, ++ <0x0 0x11800234 0x0 0xc>; ++ reg-names = "secmem", "secclk"; ++ interrupt-parent = <&plic>; ++ interrupts = <31>; ++ clocks = <&hfclk>; ++ }; ++ ++ /* gmac device configuration */ ++ stmmac_axi_setup: stmmac-axi-config { ++ snps,wr_osr_lmt = <0xf>; ++ snps,rd_osr_lmt = <0xf>; ++ snps,blen = <256 128 64 32 0 0 0>; ++ }; ++ ++ gmac: gmac@10020000 { ++ compatible = "snps,dwmac"; ++ reg = <0x0 0x10020000 0x0 0x10000>; ++ interrupt-parent = <&plic>; ++ interrupts = <6 7>; ++ interrupt-names = "macirq", "eth_wake_irq"; ++ max-frame-size = <9000>; ++ phy-mode = "rgmii-txid"; ++ snps,multicast-filter-bins = <256>; ++ snps,perfect-filter-entries = <128>; ++ rx-fifo-depth = <32768>; ++ tx-fifo-depth = <16384>; ++ clocks = <&gmacclk>; ++ clock-names = "stmmaceth"; ++ snps,fixed-burst = <1>; ++ snps,no-pbl-x8 = <1>; ++ /*snps,force_sf_dma_mode;*/ ++ snps,force_thresh_dma_mode; ++ snps,axi-config = <&stmmac_axi_setup>; ++ }; ++ ++ nbdla: nvdla@11940000 { ++ compatible = "nvidia,nvdla_os_initial"; ++ interrupt-parent = <&plic>; ++ interrupts = <22>; ++ memory-region = <&nvdla_reserved>; ++ reg = <0x0 0x11940000 0x0 0x40000>; ++ status = "okay"; ++ }; ++ ++ jpu: coadj12@11900000 { ++ compatible = "cm,codaj12-jpu-1"; ++ reg = <0x0 0x11900000 0x0 0x300>; ++ memory-region = <&jpu_reserved>; ++ interrupt-parent = <&plic>; ++ interrupts = <24>; ++ clocks = <&jpuclk>; ++ clock-names = "jpege"; ++ reg-names = "control"; ++ status = "okay"; ++ }; ++ ++ vpu_dec: vpu_dec@118f0000 { ++ compatible = "c&m,cm511-vpu"; ++ reg = <0 0x118f0000 0 0x10000>; ++ //memory-region = <&vpu_reserved>; ++ interrupt-parent = <&plic>; ++ interrupts = <23>; ++ clocks = <&vpuclk>; ++ clock-names = "vcodec"; ++ status = "okay"; ++ }; ++ ++ vpu_enc: vpu_enc@118e0000 { ++ compatible = "cm,cm521-vpu"; ++ reg = <0x0 0x118e0000 0x0 0x4000>; ++ interrupt-parent = <&plic>; ++ interrupts = <26>; ++ clocks = <&vpuclk>; ++ clock-names = "vcodec"; ++ reg-names = "control"; ++ }; ++ ++ ptc: pwm@12490000 { ++ compatible = "starfive,pwm0"; ++ reg = <0x0 0x12490000 0x0 0x10000>; ++ reg-names = "control"; ++ sifive,approx-period = <100000000>; ++ clocks = <&pwmclk>; ++ #pwm-cells = <3>; ++ sifive,npwm = <8>; ++ ++ }; ++ ++ qspi: spi@11860000 { ++ compatible = "cadence,qspi", "cdns,qspi-nor"; ++ #address-cells = <1>; ++ #size-cells = <0>; ++ reg = <0x0 0x11860000 0x0 0x10000 0x0 0x20000000 0x0 0x20000000>; ++ interrupts = <3>; ++ interrupt-parent = <&plic>; ++ clocks = <&qspi_clk>; ++ cdns,fifo-depth = <256>; ++ cdns,fifo-width = <4>; ++ cdns,trigger-address = <0x00000000>; ++ status = "okay"; ++ spi-max-frequency = <250000000>; ++ }; ++ ++ spi2: spi@12410000 { ++ compatible = "snps,dw-apb-ssi"; ++ #address-cells = <1>; ++ #size-cells = <0>; ++ interrupt-parent = <&plic>; ++ interrupts = <70>; ++ reg = <0x0 0x12410000 0x0 0x10000>; ++ clocks = <&spiclk>; ++ /* ++ num-cs = <1>; ++ cs-gpios = <&gpio 0 0>; ++ */ ++ }; ++ ++ xrp@f0000000 { ++ compatible = "cdns,xrp"; ++ reg = <0x0 0xf0000000 0x0 0x01ffffff ++ 0x10 0x72000000 0x0 0x00001000 ++ 0x10 0x72001000 0x0 0x00fff000 ++ 0x0 0x124b0000 0x0 0x00010000>; ++ clocks = <&hfclk>; ++ interrupt-parent = <&plic>; ++ firmware-name = "vp6_elf"; ++ dsp-irq = <19 20>; ++ dsp-irq-src = <0x20 0x21>; ++ intc-irq-mode = <1>; ++ intc-irq = <0 1>; ++ interrupts = <27 28>; ++ #address-cells = <1>; ++ #size-cells = <1>; ++ ranges = <0x40000000 0x0 0x40000000 0x01000000 ++ 0xb0000000 0x10 0x70000000 0x3000000>; ++ dsp@0 { ++ }; ++ }; ++ ++ sdio0: sdio0@10000000 { ++ compatible = "snps,dw-mshc"; ++ reg = <0x0 0x10000000 0x0 0x10000>; ++ interrupts = <4>; ++ interrupt-parent = <&plic>; ++ clocks = <&dwmmc_biuclk>; ++ clock-names = "biu"; ++ clock-frequency = <100000000>; ++ max-frequency = <10000000>; ++ fifo-depth = <32>; ++ card-detect-delay = <300>; ++ fifo-watermark-aligned; ++ data-addr = <0>; ++ bus-width = <4>; ++ cap-sd-highspeed; ++ broken-cd; ++ no-sdio; ++ post-power-on-delay-ms = <200>; ++ }; ++ ++ sdio1: sdio1@10010000 { ++ compatible = "snps,dw-mshc"; ++ reg = <0x0 0x10010000 0x0 0x10000>; ++ interrupts = <5>; ++ interrupt-parent = <&plic>; ++ clocks = <&dwmmc_biuclk>; ++ clock-names = "biu"; ++ clock-frequency = <100000000>; ++ max-frequency = <10000000>; ++ fifo-depth = <32>; ++ card-detect-delay = <300>; ++ fifo-watermark-aligned; ++ data-addr = <0>; ++ bus-width = <4>; ++ cap-sd-highspeed; ++ /*broken-cd;*/ ++ cap-sdio-irq; ++ cap-mmc-hw-reset; ++ non-removable; ++ enable-sdio-wakeup; ++ keep-power-in-suspend; ++ /*cap-power-off-card;*/ ++ cap-mmc-highspeed; ++ /*fixed-emmc-driver-type;*/ ++ post-power-on-delay-ms = <200>; ++ }; ++ ++ sfivefb: sfivefb@12000000 { ++ compatible = "starfive,vpp-lcdc"; ++ interrupt-parent = <&plic>; ++ interrupts = <101>, <103>; ++ interrupt-names = "lcdc_irq", "vpp1_irq"; ++ reg = <0x0 0x12000000 0x0 0x10000>, ++ <0x0 0x12100000 0x0 0x10000>, ++ <0x0 0x12040000 0x0 0x10000>, ++ <0x0 0x12080000 0x0 0x10000>, ++ <0x0 0x120c0000 0x0 0x10000>, ++ <0x0 0x12240000 0x0 0x10000>, ++ <0x0 0x12250000 0x0 0x10000>, ++ <0x0 0x12260000 0x0 0x10000>; ++ reg-names = "lcdc", "dsitx", "vpp0", "vpp1", "vpp2", "clk", "rst", "sys"; ++ memory-region = <&sffb_reserved>; ++ clocks = <&uartclk>, <&apb2clk>; ++ clock-names = "baudclk", "apb_pclk"; ++ status = "okay"; ++ ddr-format = ;/*LCDC win_format*/ ++ }; ++ ++ vin_sysctl: vin_sysctl@19800000 { ++ compatible = "starfive,stf-vin"; ++ reg = <0x0 0x19800000 0x0 0x10000>, ++ <0x0 0x19810000 0x0 0x10000>, ++ <0x0 0x19820000 0x0 0x10000>, ++ <0x0 0x19830000 0x0 0x10000>, ++ <0x0 0x19840000 0x0 0x10000>, ++ <0x0 0x19870000 0x0 0x30000>, ++ <0x0 0x198a0000 0x0 0x30000>, ++ <0x0 0x11800000 0x0 0x10000>, ++ <0x0 0x11840000 0x0 0x10000>, ++ <0x0 0x11858000 0x0 0x10000>; ++ reg-names = "mipi0", "vclk", "vrst", "mipi1", "sctrl", ++ "isp0", "isp1", "tclk", "trst", "iopad"; ++ interrupt-parent = <&plic>; ++ interrupts = <119 109>; ++ memory-region = <&vin_reserved>; ++ /*defaule config for imx219 vin&isp*/ ++ format = ; ++ frame-width = <800>; ++ frame-height =<480>; ++ isp0_enable; ++ csi-lane = <2>; ++ csi-dlane-swaps = /bits/ 8 <1>,/bits/ 8 <2>,/bits/ 8 <3>,/bits/ 8 <4>; ++ csi-dlane-pn-swaps = /bits/ 8 <0>,/bits/ 8 <0>,/bits/ 8 <0>,/bits/ 8 <0>; ++ csi-clane-swap = /bits/ 8 <0>; ++ csi-clane-pn-swap = /bits/ 8 <0>; ++ csi-mipiID = <0>; ++ csi-width = <1920>; ++ csi-height = <1080>; ++ csi-dt = <0x2b>; ++ }; ++ ++ sfc_tmp: tmpsensor@124a0000 { ++ compatible = "sfc,tempsensor"; ++ reg = <0x0 0x124a0000 0x0 0x1000>; ++ interrupt-parent = <&plic>; ++ interrupts = <122>; ++ status = "okay"; ++ }; ++ ++ otp: otp@11810000 { ++ compatible = "starfive,fu740-otp"; ++ reg = <0x0 0x11810000 0x0 0x10000>; ++ fuse-count = <0x200>; ++ }; + }; +}; -+ -diff --git a/include/dt-bindings/display/starfive_fb.h b/include/dt-bindings/display/starfive_fb.h -new file mode 100644 +diff --git a/include/dt-bindings/starfive_fb.h b/include/dt-bindings/starfive_fb.h +new file mode 100755 index 000000000000..a7e014d61b29 --- /dev/null -+++ b/include/dt-bindings/display/starfive_fb.h ++++ b/include/dt-bindings/starfive_fb.h @@ -0,0 +1,47 @@ +#ifndef __STARFIVE_FB_H +#define __STARFIVE_FB_H @@ -1123,5 +1198,5 @@ index 000000000000..a7e014d61b29 + +#endif -- -2.25.1 +2.31.1 diff --git a/recipes-kernel/linux/linux-starfive/extra.cfg b/recipes-kernel/linux/linux-starfive/extra.cfg index ff6c517..7213d9e 100644 --- a/recipes-kernel/linux/linux-starfive/extra.cfg +++ b/recipes-kernel/linux/linux-starfive/extra.cfg @@ -9,3 +9,5 @@ CONFIG_CC_OPTIMIZE_FOR_SIZE=n CONFIG_MICREL_PHY=y CONFIG_MARVELL_PHY=n +# dtb +CONFIG_SOC_STARFIVE_VIC7100=y diff --git a/recipes-kernel/linux/linux-starfive_5.10.bb b/recipes-kernel/linux/linux-starfive_5.10.bb index 1619526..4fad527 100644 --- a/recipes-kernel/linux/linux-starfive_5.10.bb +++ b/recipes-kernel/linux/linux-starfive_5.10.bb @@ -4,13 +4,13 @@ inherit kernel require recipes-kernel/linux/linux-yocto.inc SRC_URI = "git://github.com/starfive-tech/linux.git;protocol=git;branch=Fedora \ + file://0001-power-reset-Add-TPS65086-restart-driver.patch \ + file://0002-mfd-tps65086-make-interrupt-line-optional.patch \ + file://0003-riscv-dts-Add-JH7100-and-BeagleV-Starlight-support.patch \ file://extra.cfg \ file://wifi.cfg \ " -# The dts files are only in U-Boot repo currently -SRC_URI += "file://0001-sync-beaglev-dts-from-u-boot.patch" - LINUX_VERSION ?= "5.10.6" LINUX_VERSION_EXTENSION_append = "-starfive"