diff --git a/recipes-devtool/riscv-tools/files/bbl b/recipes-devtool/riscv-tools/files/bbl deleted file mode 100755 index 3239675..0000000 Binary files a/recipes-devtool/riscv-tools/files/bbl and /dev/null differ diff --git a/recipes-devtool/riscv-tools/files/binutils-2.21.1-riscv.patch b/recipes-devtool/riscv-tools/files/binutils-2.21.1-riscv.patch deleted file mode 100644 index b6e873b..0000000 --- a/recipes-devtool/riscv-tools/files/binutils-2.21.1-riscv.patch +++ /dev/null @@ -1,14051 +0,0 @@ -diff --git a/binutils-2.21.1/bfd/archures.c b/binutils-2.21.1/bfd/archures.c -index 1867154..ae47b0c 100644 ---- a/binutils-2.21.1/bfd/archures.c -+++ binutils-2.21.1/bfd/archures.c -@@ -515,6 +515,7 @@ extern const bfd_arch_info_type bfd_pj_arch; - extern const bfd_arch_info_type bfd_plugin_arch; - extern const bfd_arch_info_type bfd_powerpc_archs[]; - #define bfd_powerpc_arch bfd_powerpc_archs[0] -+extern const bfd_arch_info_type bfd_riscv_arch; - extern const bfd_arch_info_type bfd_rs6000_arch; - extern const bfd_arch_info_type bfd_rx_arch; - extern const bfd_arch_info_type bfd_s390_arch; -@@ -589,6 +590,7 @@ static const bfd_arch_info_type * const bfd_archures_list[] = - &bfd_or32_arch, - &bfd_pdp11_arch, - &bfd_powerpc_arch, -+ &bfd_riscv_arch, - &bfd_rs6000_arch, - &bfd_rx_arch, - &bfd_s390_arch, -diff --git a/binutils-2.21.1/bfd/bfd-in2.h b/binutils-2.21.1/bfd/bfd-in2.h -index 59b1b8f..25dc423 100644 ---- a/binutils-2.21.1/bfd/bfd-in2.h -+++ binutils-2.21.1/bfd/bfd-in2.h -@@ -1919,6 +1919,9 @@ enum bfd_architecture - #define bfd_mach_ppc_e500mc 5001 - #define bfd_mach_ppc_e500mc64 5005 - #define bfd_mach_ppc_titan 83 -+ bfd_arch_riscv, /* RISC-V */ -+#define bfd_mach_riscv32 132 -+#define bfd_mach_riscv64 164 - bfd_arch_rs6000, /* IBM RS/6000 */ - #define bfd_mach_rs6k 6000 - #define bfd_mach_rs6k_rs1 6001 -@@ -4761,6 +4764,38 @@ relative offset from _GLOBAL_OFFSET_TABLE_ */ - value in a word. The relocation is relative offset from */ - BFD_RELOC_MICROBLAZE_32_GOTOFF, - -+ /* RISC-V relocations */ -+ BFD_RELOC_RISCV_HI20, -+ BFD_RELOC_RISCV_PCREL_HI20, -+ BFD_RELOC_RISCV_PCREL_LO12_I, -+ BFD_RELOC_RISCV_PCREL_LO12_S, -+ BFD_RELOC_RISCV_LO12_I, -+ BFD_RELOC_RISCV_LO12_S, -+ BFD_RELOC_RISCV_GPREL12_I, -+ BFD_RELOC_RISCV_GPREL12_S, -+ BFD_RELOC_RISCV_TPREL_HI20, -+ BFD_RELOC_RISCV_TPREL_LO12_I, -+ BFD_RELOC_RISCV_TPREL_LO12_S, -+ BFD_RELOC_RISCV_TPREL_ADD, -+ BFD_RELOC_RISCV_CALL, -+ BFD_RELOC_RISCV_CALL_PLT, -+ BFD_RELOC_RISCV_ADD32, -+ BFD_RELOC_RISCV_ADD64, -+ BFD_RELOC_RISCV_SUB32, -+ BFD_RELOC_RISCV_SUB64, -+ BFD_RELOC_RISCV_GOT_HI20, -+ BFD_RELOC_RISCV_GOT_LO12, -+ BFD_RELOC_RISCV_TLS_GOT_HI20, -+ BFD_RELOC_RISCV_TLS_GOT_LO12, -+ BFD_RELOC_RISCV_TLS_IE_HI20, -+ BFD_RELOC_RISCV_TLS_IE_LO12, -+ BFD_RELOC_RISCV_TLS_IE_ADD, -+ BFD_RELOC_RISCV_TLS_IE_LO12_I, -+ BFD_RELOC_RISCV_TLS_IE_LO12_S, -+ BFD_RELOC_RISCV_TLS_GD_HI20, -+ BFD_RELOC_RISCV_TLS_GD_LO12, -+ BFD_RELOC_RISCV_TLS_PCREL_LO12, -+ - /* This is used to tell the dynamic linker to copy the value out of - the dynamic object into the runtime process image. */ - BFD_RELOC_MICROBLAZE_COPY, -diff --git a/binutils-2.21.1/bfd/config.bfd b/binutils-2.21.1/bfd/config.bfd -index fbf77ad..5c5535e 100644 ---- a/binutils-2.21.1/bfd/config.bfd -+++ binutils-2.21.1/bfd/config.bfd -@@ -96,6 +96,7 @@ or32*) targ_archs=bfd_or32_arch ;; - pdp11*) targ_archs=bfd_pdp11_arch ;; - pj*) targ_archs="bfd_pj_arch bfd_i386_arch";; - powerpc*) targ_archs="bfd_rs6000_arch bfd_powerpc_arch" ;; -+riscv*) targ_archs=bfd_riscv_arch ;; - rs6000) targ_archs="bfd_rs6000_arch bfd_powerpc_arch" ;; - s390*) targ_archs=bfd_s390_arch ;; - sh*) targ_archs=bfd_sh_arch ;; -@@ -1193,6 +1194,14 @@ case "${targ}" in - targ_selvecs="bfd_powerpcle_pei_vec bfd_powerpc_pei_vec bfd_powerpcle_pe_vec bfd_powerpc_pe_vec" - ;; - -+#ifdef BFD64 -+ riscv*-*-*) -+ targ_defvec=bfd_elf64_littleriscv_vec -+ targ_selvecs="bfd_elf32_littleriscv_vec bfd_elf64_littleriscv_vec" -+ want64=true -+ ;; -+#endif -+ - rx-*-elf) - targ_defvec=bfd_elf32_rx_le_vec - targ_selvecs="bfd_elf32_rx_be_vec bfd_elf32_rx_le_vec" -diff --git a/binutils-2.21.1/bfd/configure b/binutils-2.21.1/bfd/configure -index 4675ad2..e882968 100755 ---- a/binutils-2.21.1/bfd/configure -+++ binutils-2.21.1/bfd/configure -@@ -15239,6 +15239,7 @@ do - bfd_elf32_littlemips_vec) tb="$tb elf32-mips.lo elfxx-mips.lo elf-vxworks.lo elf32.lo $elf ecofflink.lo" ;; - bfd_elf32_littlemips_vxworks_vec) - tb="$tb elf32-mips.lo elfxx-mips.lo elf-vxworks.lo elf32.lo $elf ecofflink.lo" ;; -+ bfd_elf32_littleriscv_vec) tb="$tb elf32-riscv.lo elfxx-riscv.lo elf32.lo $elf ecofflink.lo" ;; - bfd_elf32_m32c_vec) tb="$tb elf32-m32c.lo elf32.lo $elf" ;; - bfd_elf32_m32r_vec) tb="$tb elf32-m32r.lo elf32.lo $elf" ;; - bfd_elf32_m32rle_vec) tb="$tb elf32-m32r.lo elf32.lo $elf" ;; -@@ -15320,6 +15321,7 @@ do - bfd_elf64_ia64_vms_vec) tb="$tb elf64-ia64.lo elf64.lo vms-lib.lo vms-misc.lo $elf"; target_size=64 ;; - bfd_elf64_little_generic_vec) tb="$tb elf64-gen.lo elf64.lo $elf"; target_size=64 ;; - bfd_elf64_littlemips_vec) tb="$tb elf64-mips.lo elf64.lo elfxx-mips.lo elf-vxworks.lo elf32.lo $elf ecofflink.lo"; target_size=64 ;; -+ bfd_elf64_littleriscv_vec) tb="$tb elf64-riscv.lo elf64.lo elfxx-riscv.lo elf32.lo $elf ecofflink.lo"; target_size=64 ;; - bfd_elf64_mmix_vec) tb="$tb elf64-mmix.lo elf64.lo $elf" target_size=64 ;; - bfd_elf64_powerpc_vec) tb="$tb elf64-ppc.lo elf64-gen.lo elf64.lo $elf"; target_size=64 ;; - bfd_elf64_powerpcle_vec) tb="$tb elf64-ppc.lo elf64-gen.lo elf64.lo $elf" target_size=64 ;; -diff --git a/binutils-2.21.1/bfd/configure.in b/binutils-2.21.1/bfd/configure.in -index 9f6d7a9..617b5df 100644 ---- a/binutils-2.21.1/bfd/configure.in -+++ binutils-2.21.1/bfd/configure.in -@@ -730,6 +730,7 @@ do - bfd_elf32_littlemips_vec) tb="$tb elf32-mips.lo elfxx-mips.lo elf-vxworks.lo elf32.lo $elf ecofflink.lo" ;; - bfd_elf32_littlemips_vxworks_vec) - tb="$tb elf32-mips.lo elfxx-mips.lo elf-vxworks.lo elf32.lo $elf ecofflink.lo" ;; -+ bfd_elf32_littleriscv_vec) tb="$tb elf32-riscv.lo elfxx-riscv.lo elf32.lo $elf ecofflink.lo" ;; - bfd_elf32_m32c_vec) tb="$tb elf32-m32c.lo elf32.lo $elf" ;; - bfd_elf32_m32r_vec) tb="$tb elf32-m32r.lo elf32.lo $elf" ;; - bfd_elf32_m32rle_vec) tb="$tb elf32-m32r.lo elf32.lo $elf" ;; -@@ -811,6 +812,7 @@ do - bfd_elf64_ia64_vms_vec) tb="$tb elf64-ia64.lo elf64.lo vms-lib.lo vms-misc.lo $elf"; target_size=64 ;; - bfd_elf64_little_generic_vec) tb="$tb elf64-gen.lo elf64.lo $elf"; target_size=64 ;; - bfd_elf64_littlemips_vec) tb="$tb elf64-mips.lo elf64.lo elfxx-mips.lo elf-vxworks.lo elf32.lo $elf ecofflink.lo"; target_size=64 ;; -+ bfd_elf64_littleriscv_vec) tb="$tb elf64-riscv.lo elf64.lo elfxx-riscv.lo elf32.lo $elf ecofflink.lo"; target_size=64 ;; - bfd_elf64_mmix_vec) tb="$tb elf64-mmix.lo elf64.lo $elf" target_size=64 ;; - bfd_elf64_powerpc_vec) tb="$tb elf64-ppc.lo elf64-gen.lo elf64.lo $elf"; target_size=64 ;; - bfd_elf64_powerpcle_vec) tb="$tb elf64-ppc.lo elf64-gen.lo elf64.lo $elf" target_size=64 ;; -diff --git a/binutils-2.21.1/bfd/cpu-riscv.c b/binutils-2.21.1/bfd/cpu-riscv.c -new file mode 100644 -index 0000000..0dbb3aa ---- /dev/null -+++ binutils-2.21.1/bfd/cpu-riscv.c -@@ -0,0 +1,78 @@ -+/* bfd back-end for mips support -+ Copyright 1990, 1991, 1993, 1994, 1995, 1996, 1997, 1998, 2000, 2001, -+ 2002, 2003, 2004, 2005, 2007, 2008, 2009 Free Software Foundation, Inc. -+ Written by Steve Chamberlain of Cygnus Support. -+ -+ This file is part of BFD, the Binary File Descriptor library. -+ -+ This program is free software; you can redistribute it and/or modify -+ it under the terms of the GNU General Public License as published by -+ the Free Software Foundation; either version 3 of the License, or -+ (at your option) any later version. -+ -+ This program is distributed in the hope that it will be useful, -+ but WITHOUT ANY WARRANTY; without even the implied warranty of -+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -+ GNU General Public License for more details. -+ -+ You should have received a copy of the GNU General Public License -+ along with this program; if not, write to the Free Software -+ Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston, -+ MA 02110-1301, USA. */ -+ -+#include "sysdep.h" -+#include "bfd.h" -+#include "libbfd.h" -+ -+static const bfd_arch_info_type *mips_compatible -+ (const bfd_arch_info_type *, const bfd_arch_info_type *); -+ -+/* The default routine tests bits_per_word, which is wrong on mips as -+ mips word size doesn't correlate with reloc size. */ -+ -+static const bfd_arch_info_type * -+mips_compatible (const bfd_arch_info_type *a, const bfd_arch_info_type *b) -+{ -+ if (a->arch != b->arch) -+ return NULL; -+ -+ /* Machine compatibility is checked in -+ _bfd_mips_elf_merge_private_bfd_data. */ -+ -+ return a; -+} -+ -+#define N(BITS_WORD, BITS_ADDR, NUMBER, PRINT, DEFAULT, NEXT) \ -+ { \ -+ BITS_WORD, /* bits in a word */ \ -+ BITS_ADDR, /* bits in an address */ \ -+ 8, /* 8 bits in a byte */ \ -+ bfd_arch_riscv, \ -+ NUMBER, \ -+ "riscv", \ -+ PRINT, \ -+ 3, \ -+ DEFAULT, \ -+ mips_compatible, \ -+ bfd_default_scan, \ -+ NEXT, \ -+ } -+ -+enum -+{ -+ I_riscv64, -+ I_riscv32 -+}; -+ -+#define NN(index) (&arch_info_struct[(index) + 1]) -+ -+static const bfd_arch_info_type arch_info_struct[] = -+{ -+ N (64, 64, bfd_mach_riscv64, "riscv:rv64", FALSE, NN(I_riscv64)), -+ N (32, 32, bfd_mach_riscv32, "riscv:rv32", FALSE, 0) -+}; -+ -+/* The default architecture is riscv:rv64. */ -+ -+const bfd_arch_info_type bfd_riscv_arch = -+N (64, 64, 0, "riscv", TRUE, &arch_info_struct[0]); -diff --git a/binutils-2.21.1/bfd/doc/bfd.texinfo b/binutils-2.21.1/bfd/doc/bfd.texinfo -index 45ffa73..c3ca5e7 100644 ---- a/binutils-2.21.1/bfd/doc/bfd.texinfo -+++ binutils-2.21.1/bfd/doc/bfd.texinfo -@@ -322,7 +322,7 @@ All of BFD lives in one directory. - @printindex cp - - @tex --% I think something like @colophon should be in texinfo. In the -+% I think something like @@colophon should be in texinfo. In the - % meantime: - \long\def\colophon{\hbox to0pt{}\vfill - \centerline{The body of this manual is set in} -@@ -333,7 +333,7 @@ All of BFD lives in one directory. - \centerline{{\sl\fontname\tensl\/}} - \centerline{are used for emphasis.}\vfill} - \page\colophon --% Blame: doc@cygnus.com, 28mar91. -+% Blame: doc@@cygnus.com, 28mar91. - @end tex - - @bye -diff --git a/binutils-2.21.1/bfd/elf32-riscv.c b/binutils-2.21.1/bfd/elf32-riscv.c -new file mode 100644 -index 0000000..3ef28fa ---- /dev/null -+++ binutils-2.21.1/bfd/elf32-riscv.c -@@ -0,0 +1,225 @@ -+/* MIPS-specific support for 32-bit ELF -+ Copyright 1993, 1994, 1995, 1996, 1997, 1998, 1999, 2000, 2001, 2002, -+ 2003, 2004, 2005, 2006, 2007, 2008, 2009 Free Software Foundation, Inc. -+ -+ Most of the information added by Ian Lance Taylor, Cygnus Support, -+ . -+ N32/64 ABI support added by Mark Mitchell, CodeSourcery, LLC. -+ -+ Traditional MIPS targets support added by Koundinya.K, Dansk Data -+ Elektronik & Operations Research Group. -+ -+ This file is part of BFD, the Binary File Descriptor library. -+ -+ This program is free software; you can redistribute it and/or modify -+ it under the terms of the GNU General Public License as published by -+ the Free Software Foundation; either version 3 of the License, or -+ (at your option) any later version. -+ -+ This program is distributed in the hope that it will be useful, -+ but WITHOUT ANY WARRANTY; without even the implied warranty of -+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -+ GNU General Public License for more details. -+ -+ You should have received a copy of the GNU General Public License -+ along with this program; if not, write to the Free Software -+ Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston, -+ MA 02110-1301, USA. */ -+ -+ -+/* This file handles MIPS ELF targets. SGI Irix 5 uses a slightly -+ different MIPS ELF from other targets. This matters when linking. -+ This file supports both, switching at runtime. */ -+ -+#include "sysdep.h" -+#include "bfd.h" -+#include "libbfd.h" -+#include "bfdlink.h" -+#include "genlink.h" -+#include "elf-bfd.h" -+#include "elfxx-riscv.h" -+#include "elf/riscv.h" -+#include "opcode/riscv.h" -+ -+#include "opcode/riscv.h" -+ -+static bfd_boolean mips_elf_sym_is_global -+ (bfd *, asymbol *); -+static bfd_boolean mips_elf_n32_object_p -+ (bfd *); -+static bfd_boolean elf32_mips_grok_prstatus -+ (bfd *, Elf_Internal_Note *); -+static bfd_boolean elf32_mips_grok_psinfo -+ (bfd *, Elf_Internal_Note *); -+ -+extern const bfd_target bfd_elf32_nbigmips_vec; -+extern const bfd_target bfd_elf32_nlittlemips_vec; -+ -+/* The number of local .got entries we reserve. */ -+#define MIPS_RESERVED_GOTNO (2) -+ -+/* Determine whether a symbol is global for the purposes of splitting -+ the symbol table into global symbols and local symbols. At least -+ on Irix 5, this split must be between section symbols and all other -+ symbols. On most ELF targets the split is between static symbols -+ and externally visible symbols. */ -+ -+static bfd_boolean -+mips_elf_sym_is_global (bfd *abfd ATTRIBUTE_UNUSED, asymbol *sym) -+{ -+ return ((sym->flags & (BSF_GLOBAL | BSF_WEAK | BSF_GNU_UNIQUE)) != 0 -+ || bfd_is_und_section (bfd_get_section (sym)) -+ || bfd_is_com_section (bfd_get_section (sym))); -+} -+ -+/* Set the right machine number for a MIPS ELF file. */ -+ -+static bfd_boolean -+mips_elf_n32_object_p (bfd *abfd) -+{ -+ bfd_default_set_arch_mach (abfd, bfd_arch_riscv, bfd_mach_riscv32); -+ return TRUE; -+} -+ -+/* Support for core dump NOTE sections. */ -+static bfd_boolean -+elf32_mips_grok_prstatus (bfd *abfd, Elf_Internal_Note *note) -+{ -+ int offset; -+ unsigned int size; -+ -+ switch (note->descsz) -+ { -+ default: -+ return FALSE; -+ -+ case 440: /* Linux/MIPS N32 */ -+ /* pr_cursig */ -+ elf_tdata (abfd)->core_signal = bfd_get_16 (abfd, note->descdata + 12); -+ -+ /* pr_pid */ -+ elf_tdata (abfd)->core_lwpid = bfd_get_32 (abfd, note->descdata + 24); -+ -+ /* pr_reg */ -+ offset = 72; -+ size = 360; -+ -+ break; -+ } -+ -+ /* Make a ".reg/999" section. */ -+ return _bfd_elfcore_make_pseudosection (abfd, ".reg", size, -+ note->descpos + offset); -+} -+ -+static bfd_boolean -+elf32_mips_grok_psinfo (bfd *abfd, Elf_Internal_Note *note) -+{ -+ switch (note->descsz) -+ { -+ default: -+ return FALSE; -+ -+ case 128: /* Linux/MIPS elf_prpsinfo */ -+ elf_tdata (abfd)->core_program -+ = _bfd_elfcore_strndup (abfd, note->descdata + 32, 16); -+ elf_tdata (abfd)->core_command -+ = _bfd_elfcore_strndup (abfd, note->descdata + 48, 80); -+ } -+ -+ /* Note that for some reason, a spurious space is tacked -+ onto the end of the args in some (at least one anyway) -+ implementations, so strip it off if it exists. */ -+ -+ { -+ char *command = elf_tdata (abfd)->core_command; -+ int n = strlen (command); -+ -+ if (0 < n && command[n - 1] == ' ') -+ command[n - 1] = '\0'; -+ } -+ -+ return TRUE; -+} -+ -+#define ELF_ARCH bfd_arch_riscv -+#define ELF_TARGET_ID MIPS_ELF_DATA -+#define ELF_MACHINE_CODE EM_RISCV -+ -+#define elf_backend_collect TRUE -+#define elf_backend_type_change_ok TRUE -+#define elf_backend_can_gc_sections TRUE -+#define elf_info_to_howto riscv_elf_info_to_howto_rela -+#define elf_backend_sym_is_global mips_elf_sym_is_global -+#define elf_backend_object_p mips_elf_n32_object_p -+#define elf_backend_symbol_processing _bfd_riscv_elf_symbol_processing -+#define elf_backend_add_symbol_hook _bfd_riscv_elf_add_symbol_hook -+#define elf_backend_create_dynamic_sections \ -+ _bfd_riscv_elf_create_dynamic_sections -+#define elf_backend_check_relocs _bfd_riscv_elf_check_relocs -+#define elf_backend_merge_symbol_attribute \ -+ _bfd_riscv_elf_merge_symbol_attribute -+#define elf_backend_get_target_dtag _bfd_riscv_elf_get_target_dtag -+#define elf_backend_adjust_dynamic_symbol \ -+ _bfd_riscv_elf_adjust_dynamic_symbol -+#define elf_backend_always_size_sections \ -+ _bfd_riscv_elf_always_size_sections -+#define elf_backend_size_dynamic_sections \ -+ _bfd_riscv_elf_size_dynamic_sections -+#define elf_backend_init_index_section _bfd_elf_init_1_index_section -+#define elf_backend_relocate_section _bfd_riscv_elf_relocate_section -+#define elf_backend_finish_dynamic_symbol \ -+ _bfd_riscv_elf_finish_dynamic_symbol -+#define elf_backend_finish_dynamic_sections \ -+ _bfd_riscv_elf_finish_dynamic_sections -+#define elf_backend_additional_program_headers \ -+ _bfd_riscv_elf_additional_program_headers -+#define elf_backend_modify_segment_map _bfd_riscv_elf_modify_segment_map -+#define elf_backend_copy_indirect_symbol \ -+ _bfd_riscv_elf_copy_indirect_symbol -+#define elf_backend_grok_prstatus elf32_mips_grok_prstatus -+#define elf_backend_grok_psinfo elf32_mips_grok_psinfo -+ -+#define elf_backend_got_header_size (4 * MIPS_RESERVED_GOTNO) -+ -+/* MIPS n32 ELF can use a mixture of REL and RELA, but some Relocations -+ work better/work only in RELA, so we default to this. */ -+#define elf_backend_may_use_rel_p 1 -+#define elf_backend_may_use_rela_p 1 -+#define elf_backend_default_use_rela_p 1 -+#define elf_backend_rela_plts_and_copies_p 0 -+#define elf_backend_sign_extend_vma TRUE -+#define elf_backend_plt_readonly 1 -+#define elf_backend_plt_sym_val _bfd_riscv_elf_plt_sym_val -+ -+#define elf_backend_discard_info _bfd_riscv_elf_discard_info -+#define elf_backend_ignore_discarded_relocs \ -+ _bfd_riscv_elf_ignore_discarded_relocs -+#define elf_backend_write_section _bfd_riscv_elf_write_section -+#define bfd_elf32_new_section_hook _bfd_riscv_elf_new_section_hook -+#define bfd_elf32_bfd_get_relocated_section_contents \ -+ bfd_generic_get_relocated_section_contents -+#define bfd_elf32_bfd_link_hash_table_create \ -+ _bfd_riscv_elf_link_hash_table_create -+#define bfd_elf32_bfd_final_link _bfd_riscv_elf_final_link -+#define bfd_elf32_bfd_merge_private_bfd_data \ -+ _bfd_riscv_elf_merge_private_bfd_data -+#define bfd_elf32_bfd_print_private_bfd_data \ -+ _bfd_riscv_elf_print_private_bfd_data -+#define bfd_elf32_bfd_relax_section _bfd_riscv_relax_section -+#define bfd_elf32_bfd_reloc_type_lookup \ -+ riscv_elf_bfd_reloc_type_lookup -+#define bfd_elf32_bfd_reloc_name_lookup \ -+ riscv_elf_bfd_reloc_name_lookup -+ -+/* Support for SGI-ish mips targets using n32 ABI. */ -+ -+#define TARGET_LITTLE_SYM bfd_elf32_littleriscv_vec -+#define TARGET_LITTLE_NAME "elf32-littleriscv" -+#define TARGET_BIG_SYM bfd_elf32_bigriscv_vec -+#define TARGET_BIG_NAME "elf32-bigriscv" -+ -+#define ELF_MAXPAGESIZE 0x1000 -+#define ELF_COMMONPAGESIZE 0x1000 -+ -+#include "elf32-target.h" -diff --git a/binutils-2.21.1/bfd/elf64-riscv.c b/binutils-2.21.1/bfd/elf64-riscv.c -new file mode 100644 -index 0000000..d693841 ---- /dev/null -+++ binutils-2.21.1/bfd/elf64-riscv.c -@@ -0,0 +1,245 @@ -+/* MIPS-specific support for 64-bit ELF -+ Copyright 1996, 1997, 1998, 1999, 2000, 2001, 2002, 2003, 2004, 2005, -+ 2006, 2007, 2008, 2009, 2010 -+ Free Software Foundation, Inc. -+ Ian Lance Taylor, Cygnus Support -+ Linker support added by Mark Mitchell, CodeSourcery, LLC. -+ -+ -+ This file is part of BFD, the Binary File Descriptor library. -+ -+ This program is free software; you can redistribute it and/or modify -+ it under the terms of the GNU General Public License as published by -+ the Free Software Foundation; either version 3 of the License, or -+ (at your option) any later version. -+ -+ This program is distributed in the hope that it will be useful, -+ but WITHOUT ANY WARRANTY; without even the implied warranty of -+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -+ GNU General Public License for more details. -+ -+ You should have received a copy of the GNU General Public License -+ along with this program; if not, write to the Free Software -+ Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston, -+ MA 02110-1301, USA. */ -+ -+ -+/* This file supports the 64-bit MIPS ELF ABI. -+ -+ The MIPS 64-bit ELF ABI uses an unusual reloc format. This file -+ overrides the usual ELF reloc handling, and handles reading and -+ writing the relocations here. */ -+ -+/* TODO: Many things are unsupported, even if there is some code for it -+ . (which was mostly stolen from elf32-mips.c and slightly adapted). -+ . -+ . - Relocation handling for REL relocs is wrong in many cases and -+ . generally untested. -+ . - Relocation handling for RELA relocs related to GOT support are -+ . also likely to be wrong. -+ . - Support for MIPS16 is untested. -+ . - Combined relocs with RSS_* entries are unsupported. -+ . - The whole GOT handling for NewABI is missing, some parts of -+ . the OldABI version is still lying around and should be removed. -+ */ -+ -+#include "sysdep.h" -+#include "bfd.h" -+#include "libbfd.h" -+#include "aout/ar.h" -+#include "bfdlink.h" -+#include "genlink.h" -+#include "elf-bfd.h" -+#include "elfxx-riscv.h" -+#include "elf/riscv.h" -+#include "opcode/riscv.h" -+ -+#include "opcode/riscv.h" -+ -+static bfd_boolean mips_elf64_object_p -+ (bfd *); -+static bfd_boolean elf64_mips_grok_prstatus -+ (bfd *, Elf_Internal_Note *); -+static bfd_boolean elf64_mips_grok_psinfo -+ (bfd *, Elf_Internal_Note *); -+ -+/* The number of local .got entries we reserve. */ -+#define MIPS_RESERVED_GOTNO (2) -+ -+/* Set the right machine number for a MIPS ELF file. */ -+ -+static bfd_boolean -+mips_elf64_object_p (bfd *abfd) -+{ -+ bfd_default_set_arch_mach (abfd, bfd_arch_riscv, bfd_mach_riscv64); -+ return TRUE; -+} -+ -+/* Support for core dump NOTE sections. */ -+static bfd_boolean -+elf64_mips_grok_prstatus (bfd *abfd, Elf_Internal_Note *note) -+{ -+ int offset; -+ unsigned int size; -+ -+ switch (note->descsz) -+ { -+ default: -+ return FALSE; -+ -+ case 480: /* Linux/MIPS - N64 kernel */ -+ /* pr_cursig */ -+ elf_tdata (abfd)->core_signal = bfd_get_16 (abfd, note->descdata + 12); -+ -+ /* pr_pid */ -+ elf_tdata (abfd)->core_lwpid = bfd_get_32 (abfd, note->descdata + 32); -+ -+ /* pr_reg */ -+ offset = 112; -+ size = 360; -+ -+ break; -+ } -+ -+ /* Make a ".reg/999" section. */ -+ return _bfd_elfcore_make_pseudosection (abfd, ".reg", -+ size, note->descpos + offset); -+} -+ -+static bfd_boolean -+elf64_mips_grok_psinfo (bfd *abfd, Elf_Internal_Note *note) -+{ -+ switch (note->descsz) -+ { -+ default: -+ return FALSE; -+ -+ case 136: /* Linux/MIPS - N64 kernel elf_prpsinfo */ -+ elf_tdata (abfd)->core_program -+ = _bfd_elfcore_strndup (abfd, note->descdata + 40, 16); -+ elf_tdata (abfd)->core_command -+ = _bfd_elfcore_strndup (abfd, note->descdata + 56, 80); -+ } -+ -+ /* Note that for some reason, a spurious space is tacked -+ onto the end of the args in some (at least one anyway) -+ implementations, so strip it off if it exists. */ -+ -+ { -+ char *command = elf_tdata (abfd)->core_command; -+ int n = strlen (command); -+ -+ if (0 < n && command[n - 1] == ' ') -+ command[n - 1] = '\0'; -+ } -+ -+ return TRUE; -+} -+ -+#define ELF_ARCH bfd_arch_riscv -+#define ELF_TARGET_ID MIPS_ELF_DATA -+#define ELF_MACHINE_CODE EM_RISCV -+ -+#define elf_backend_collect TRUE -+#define elf_backend_type_change_ok TRUE -+#define elf_backend_can_gc_sections TRUE -+#define elf_info_to_howto riscv_elf_info_to_howto_rela -+#define elf_backend_object_p mips_elf64_object_p -+#define elf_backend_symbol_processing _bfd_riscv_elf_symbol_processing -+#define elf_backend_add_symbol_hook _bfd_riscv_elf_add_symbol_hook -+#define elf_backend_create_dynamic_sections \ -+ _bfd_riscv_elf_create_dynamic_sections -+#define elf_backend_check_relocs _bfd_riscv_elf_check_relocs -+#define elf_backend_merge_symbol_attribute \ -+ _bfd_riscv_elf_merge_symbol_attribute -+#define elf_backend_get_target_dtag _bfd_riscv_elf_get_target_dtag -+#define elf_backend_adjust_dynamic_symbol \ -+ _bfd_riscv_elf_adjust_dynamic_symbol -+#define elf_backend_always_size_sections \ -+ _bfd_riscv_elf_always_size_sections -+#define elf_backend_size_dynamic_sections \ -+ _bfd_riscv_elf_size_dynamic_sections -+#define elf_backend_init_index_section _bfd_elf_init_1_index_section -+#define elf_backend_relocate_section _bfd_riscv_elf_relocate_section -+#define elf_backend_finish_dynamic_symbol \ -+ _bfd_riscv_elf_finish_dynamic_symbol -+#define elf_backend_finish_dynamic_sections \ -+ _bfd_riscv_elf_finish_dynamic_sections -+#define elf_backend_additional_program_headers \ -+ _bfd_riscv_elf_additional_program_headers -+#define elf_backend_modify_segment_map _bfd_riscv_elf_modify_segment_map -+#define elf_backend_copy_indirect_symbol \ -+ _bfd_riscv_elf_copy_indirect_symbol -+#define elf_backend_ignore_discarded_relocs \ -+ _bfd_riscv_elf_ignore_discarded_relocs -+ -+#define elf_backend_grok_prstatus elf64_mips_grok_prstatus -+#define elf_backend_grok_psinfo elf64_mips_grok_psinfo -+ -+#define elf_backend_got_header_size (4 * MIPS_RESERVED_GOTNO) -+ -+/* MIPS ELF64 can use a mixture of REL and RELA, but some Relocations -+ work better/work only in RELA, so we default to this. */ -+#define elf_backend_may_use_rel_p 1 -+#define elf_backend_may_use_rela_p 1 -+#define elf_backend_default_use_rela_p 1 -+#define elf_backend_rela_plts_and_copies_p 0 -+#define elf_backend_plt_readonly 1 -+#define elf_backend_plt_sym_val _bfd_riscv_elf_plt_sym_val -+ -+#define elf_backend_sign_extend_vma TRUE -+ -+#define elf_backend_write_section _bfd_riscv_elf_write_section -+ -+/* We don't set bfd_elf64_bfd_is_local_label_name because the 32-bit -+ MIPS-specific function only applies to IRIX5, which had no 64-bit -+ ABI. */ -+#define bfd_elf64_new_section_hook _bfd_riscv_elf_new_section_hook -+#define bfd_elf64_bfd_get_relocated_section_contents \ -+ bfd_generic_get_relocated_section_contents -+#define bfd_elf64_bfd_link_hash_table_create \ -+ _bfd_riscv_elf_link_hash_table_create -+#define bfd_elf64_bfd_final_link _bfd_riscv_elf_final_link -+#define bfd_elf64_bfd_merge_private_bfd_data \ -+ _bfd_riscv_elf_merge_private_bfd_data -+#define bfd_elf64_bfd_print_private_bfd_data \ -+ _bfd_riscv_elf_print_private_bfd_data -+ -+#define bfd_elf64_bfd_relax_section _bfd_riscv_relax_section -+ -+/* MIPS ELF64 archive functions. */ -+#define bfd_elf64_archive_functions -+extern bfd_boolean bfd_elf64_archive_slurp_armap -+ (bfd *); -+extern bfd_boolean bfd_elf64_archive_write_armap -+ (bfd *, unsigned int, struct orl *, unsigned int, int); -+#define bfd_elf64_archive_slurp_extended_name_table \ -+ _bfd_archive_coff_slurp_extended_name_table -+#define bfd_elf64_archive_construct_extended_name_table \ -+ _bfd_archive_coff_construct_extended_name_table -+#define bfd_elf64_archive_truncate_arname \ -+ _bfd_archive_coff_truncate_arname -+#define bfd_elf64_archive_read_ar_hdr _bfd_archive_coff_read_ar_hdr -+#define bfd_elf64_archive_write_ar_hdr _bfd_archive_coff_write_ar_hdr -+#define bfd_elf64_archive_openr_next_archived_file \ -+ _bfd_archive_coff_openr_next_archived_file -+#define bfd_elf64_archive_get_elt_at_index \ -+ _bfd_archive_coff_get_elt_at_index -+#define bfd_elf64_archive_generic_stat_arch_elt \ -+ _bfd_archive_coff_generic_stat_arch_elt -+#define bfd_elf64_archive_update_armap_timestamp \ -+ _bfd_archive_coff_update_armap_timestamp -+#define bfd_elf64_bfd_reloc_type_lookup \ -+ riscv_elf_bfd_reloc_type_lookup -+#define bfd_elf64_bfd_reloc_name_lookup \ -+ riscv_elf_bfd_reloc_name_lookup -+/* The SGI style (n)64 NewABI. */ -+#define TARGET_LITTLE_SYM bfd_elf64_littleriscv_vec -+#define TARGET_LITTLE_NAME "elf64-littleriscv" -+#define TARGET_BIG_SYM bfd_elf64_bigriscv_vec -+#define TARGET_BIG_NAME "elf64-bigriscv" -+ -+#define ELF_MAXPAGESIZE 0x2000 -+#define ELF_COMMONPAGESIZE 0x2000 -+ -+#include "elf64-target.h" -diff --git a/binutils-2.21.1/bfd/elfxx-riscv.c b/binutils-2.21.1/bfd/elfxx-riscv.c -new file mode 100644 -index 0000000..08272f4 ---- /dev/null -+++ binutils-2.21.1/bfd/elfxx-riscv.c -@@ -0,0 +1,5575 @@ -+/* MIPS-specific support for ELF -+ Copyright 1993, 1994, 1995, 1996, 1997, 1998, 1999, 2000, 2001, 2002, -+ 2003, 2004, 2005, 2006, 2007, 2008, 2009, 2010 Free Software Foundation, Inc. -+ -+ Most of the information added by Ian Lance Taylor, Cygnus Support, -+ . -+ N32/64 ABI support added by Mark Mitchell, CodeSourcery, LLC. -+ -+ Traditional MIPS targets support added by Koundinya.K, Dansk Data -+ Elektronik & Operations Research Group. -+ -+ This file is part of BFD, the Binary File Descriptor library. -+ -+ This program is free software; you can redistribute it and/or modify -+ it under the terms of the GNU General Public License as published by -+ the Free Software Foundation; either version 3 of the License, or -+ (at your option) any later version. -+ -+ This program is distributed in the hope that it will be useful, -+ but WITHOUT ANY WARRANTY; without even the implied warranty of -+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -+ GNU General Public License for more details. -+ -+ You should have received a copy of the GNU General Public License -+ along with this program; if not, write to the Free Software -+ Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston, -+ MA 02110-1301, USA. */ -+ -+ -+/* This file handles functionality common to the different MIPS ABI's. */ -+ -+#include "sysdep.h" -+#include "bfd.h" -+#include "libbfd.h" -+#include "libiberty.h" -+#include "elf-bfd.h" -+#include "elfxx-riscv.h" -+#include "elf/riscv.h" -+#include "opcode/riscv.h" -+ -+#include "hashtab.h" -+#include -+ -+/* This structure is used to hold information about one GOT entry. -+ There are three types of entry: -+ -+ (1) absolute addresses -+ (abfd == NULL) -+ (2) SYMBOL + OFFSET addresses, where SYMBOL is local to an input bfd -+ (abfd != NULL, symndx >= 0) -+ (3) SYMBOL addresses, where SYMBOL is not local to an input bfd -+ (abfd != NULL, symndx == -1) -+ -+ Type (3) entries are treated differently for different types of GOT. -+ In the "master" GOT -- i.e. the one that describes every GOT -+ reference needed in the link -- the mips_got_entry is keyed on both -+ the symbol and the input bfd that references it. If it turns out -+ that we need multiple GOTs, we can then use this information to -+ create separate GOTs for each input bfd. -+ -+ However, we want each of these separate GOTs to have at most one -+ entry for a given symbol, so their type (3) entries are keyed only -+ on the symbol. The input bfd given by the "abfd" field is somewhat -+ arbitrary in this case. -+ -+ This means that when there are multiple GOTs, each GOT has a unique -+ mips_got_entry for every symbol within it. We can therefore use the -+ mips_got_entry fields (tls_type and gotidx) to track the symbol's -+ GOT index. -+ -+ However, if it turns out that we need only a single GOT, we continue -+ to use the master GOT to describe it. There may therefore be several -+ mips_got_entries for the same symbol, each with a different input bfd. -+ We want to make sure that each symbol gets a unique GOT entry, so when -+ there's a single GOT, we use the symbol's hash entry, not the -+ mips_got_entry fields, to track a symbol's GOT index. */ -+struct mips_got_entry -+{ -+ /* The input bfd in which the symbol is defined. */ -+ bfd *abfd; -+ /* The index of the symbol, as stored in the relocation r_info, if -+ we have a local symbol; -1 otherwise. */ -+ long symndx; -+ union -+ { -+ /* If abfd == NULL, an address that must be stored in the got. */ -+ bfd_vma address; -+ /* If abfd != NULL && symndx != -1, the addend of the relocation -+ that should be added to the symbol value. */ -+ bfd_vma addend; -+ /* If abfd != NULL && symndx == -1, the hash table entry -+ corresponding to symbol in the GOT. The symbol's entry -+ is in the local area if h->global_got_area is GGA_NONE, -+ otherwise it is in the global area. */ -+ struct mips_elf_link_hash_entry *h; -+ } d; -+ -+ /* The TLS types included in this GOT entry (specifically, GD and IE). */ -+ unsigned char tls_type; -+ -+ /* The offset from the beginning of the .got section to the entry -+ corresponding to this symbol+addend. If it's a global symbol -+ whose offset is yet to be decided, it's going to be -1. */ -+ long gotidx; -+}; -+ -+/* This structure is used to hold .got information when linking. */ -+ -+struct mips_got_info -+{ -+ /* The global symbol in the GOT with the lowest index in the dynamic -+ symbol table. */ -+ struct elf_link_hash_entry *global_gotsym; -+ /* The number of global .got entries. */ -+ unsigned int global_gotno; -+ /* The number of global .got entries that are in the GGA_RELOC_ONLY area. */ -+ unsigned int reloc_only_gotno; -+ /* The number of .got slots used for TLS. */ -+ unsigned int tls_gotno; -+ /* The first unused TLS .got entry. Used only during -+ mips_elf_initialize_tls_index. */ -+ unsigned int tls_assigned_gotno; -+ /* The number of local .got entries, eventually including page entries. */ -+ unsigned int local_gotno; -+ /* The number of local .got entries we have used. */ -+ unsigned int assigned_gotno; -+ /* A hash table holding members of the got. */ -+ struct htab *got_entries; -+}; -+ -+/* Another structure used to pass arguments for got entries traversal. */ -+ -+struct mips_elf_set_global_got_offset_arg -+{ -+ struct mips_got_info *g; -+ int value; -+ unsigned int needed_relocs; -+ struct bfd_link_info *info; -+}; -+ -+/* A structure used to count TLS relocations or GOT entries, for GOT -+ entry or ELF symbol table traversal. */ -+ -+struct mips_elf_count_tls_arg -+{ -+ struct bfd_link_info *info; -+ unsigned int needed; -+}; -+ -+struct _mips_elf_section_data -+{ -+ struct bfd_elf_section_data elf; -+ union -+ { -+ bfd_byte *tdata; -+ } u; -+}; -+ -+#define mips_elf_section_data(sec) \ -+ ((struct _mips_elf_section_data *) elf_section_data (sec)) -+ -+#define is_mips_elf(bfd) \ -+ (bfd_get_flavour (bfd) == bfd_target_elf_flavour \ -+ && elf_tdata (bfd) != NULL \ -+ && elf_object_id (bfd) == MIPS_ELF_DATA) -+ -+/* The ABI says that every symbol used by dynamic relocations must have -+ a global GOT entry. Among other things, this provides the dynamic -+ linker with a free, directly-indexed cache. The GOT can therefore -+ contain symbols that are not referenced by GOT relocations themselves. -+ -+ GOT relocations are less likely to overflow if we put the associated -+ GOT entries towards the beginning. We therefore divide the global -+ GOT entries into two areas: "normal" and "reloc-only". Entries in -+ the first area can be used for both dynamic relocations and GP-relative -+ accesses, while those in the "reloc-only" area are for dynamic -+ relocations only. -+ -+ These GGA_* ("Global GOT Area") values are organised so that lower -+ values are more general than higher values. Also, non-GGA_NONE -+ values are ordered by the position of the area in the GOT. */ -+#define GGA_NORMAL 0 -+#define GGA_RELOC_ONLY 1 -+#define GGA_NONE 2 -+ -+/* This structure is passed to mips_elf_sort_hash_table_f when sorting -+ the dynamic symbols. */ -+ -+struct mips_elf_hash_sort_data -+{ -+ /* The symbol in the global GOT with the lowest dynamic symbol table -+ index. */ -+ struct elf_link_hash_entry *low; -+ /* The least dynamic symbol table index corresponding to a non-TLS -+ symbol with a GOT entry. */ -+ long min_got_dynindx; -+ /* The greatest dynamic symbol table index corresponding to a symbol -+ with a GOT entry that is not referenced (e.g., a dynamic symbol -+ with dynamic relocations pointing to it from non-primary GOTs). */ -+ long max_unref_got_dynindx; -+ /* The greatest dynamic symbol table index not corresponding to a -+ symbol without a GOT entry. */ -+ long max_non_got_dynindx; -+}; -+ -+/* The MIPS ELF linker needs additional information for each symbol in -+ the global hash table. */ -+ -+struct mips_elf_link_hash_entry -+{ -+ struct elf_link_hash_entry root; -+ -+ /* Number of R_RISCV_32, R_RISCV_REL32, or R_RISCV_64 relocs against -+ this symbol. */ -+ unsigned int possibly_dynamic_relocs; -+ -+#define GOT_NORMAL 0 -+#define GOT_TLS_GD 1 -+#define GOT_TLS_IE 4 -+#define GOT_TLS_OFFSET_DONE 0x40 -+#define GOT_TLS_DONE 0x80 -+ unsigned char tls_type; -+ -+ /* This is only used in single-GOT mode; in multi-GOT mode there -+ is one mips_got_entry per GOT entry, so the offset is stored -+ there. In single-GOT mode there may be many mips_got_entry -+ structures all referring to the same GOT slot. It might be -+ possible to use root.got.offset instead, but that field is -+ overloaded already. */ -+ bfd_vma tls_got_offset; -+ -+ /* The highest GGA_* value that satisfies all references to this symbol. */ -+ unsigned int global_got_area : 2; -+ -+ /* True if one of the relocations described by possibly_dynamic_relocs -+ is against a readonly section. */ -+ unsigned int readonly_reloc : 1; -+ -+ /* True if there is a relocation against this symbol that must be -+ resolved by the static linker (in other words, if the relocation -+ cannot possibly be made dynamic). */ -+ unsigned int has_static_relocs : 1; -+}; -+ -+/* MIPS ELF linker hash table. */ -+ -+struct mips_elf_link_hash_table -+{ -+ struct elf_link_hash_table root; -+ -+ /* Shortcuts to some dynamic sections, or NULL if they are not -+ being used. */ -+ asection *srelbss; -+ asection *sdynbss; -+ asection *srelplt; -+ asection *srelplt2; -+ asection *sgotplt; -+ asection *splt; -+ asection *sgot; -+ -+ /* The master GOT information. */ -+ struct mips_got_info *got_info; -+ -+ /* The number of PLT entries. */ -+ bfd_vma nplt; -+ -+ /* The number of reserved entries at the beginning of the GOT. */ -+ unsigned int reserved_gotno; -+ -+ /* Whether or not relaxation is enabled. */ -+ bfd_boolean relax; -+}; -+ -+/* Get the MIPS ELF linker hash table from a link_info structure. */ -+ -+#define mips_elf_hash_table(p) \ -+ (elf_hash_table_id ((struct elf_link_hash_table *) ((p)->hash)) \ -+ == MIPS_ELF_DATA ? ((struct mips_elf_link_hash_table *) ((p)->hash)) : NULL) -+ -+/* A structure used to communicate with htab_traverse callbacks. */ -+struct mips_htab_traverse_info -+{ -+ /* The usual link-wide information. */ -+ struct bfd_link_info *info; -+ bfd *output_bfd; -+ -+ /* Starts off FALSE and is set to TRUE if the link should be aborted. */ -+ bfd_boolean error; -+}; -+ -+#define TLS_RELOC_P(r_type) \ -+ ((r_type) == R_RISCV_TLS_DTPMOD32 \ -+ || (r_type) == R_RISCV_TLS_DTPMOD64 \ -+ || (r_type) == R_RISCV_TLS_DTPREL32 \ -+ || (r_type) == R_RISCV_TLS_DTPREL64 \ -+ || (r_type) == R_RISCV_TLS_TPREL32 \ -+ || (r_type) == R_RISCV_TLS_TPREL64 \ -+ || (r_type) == R_RISCV_TPREL_HI20 \ -+ || (r_type) == R_RISCV_TPREL_LO12_I \ -+ || (r_type) == R_RISCV_TPREL_LO12_S \ -+ || (r_type) == R_RISCV_TPREL_ADD \ -+ || TLS_GD_RELOC_P(r_type) \ -+ || TLS_GOTTPREL_RELOC_P(r_type)) -+ -+#define TLS_GOTTPREL_RELOC_P(r_type) \ -+ ((r_type) == R_RISCV_TLS_IE_HI20 \ -+ || (r_type) == R_RISCV_TLS_IE_LO12 \ -+ || (r_type) == R_RISCV_TLS_IE_ADD \ -+ || (r_type) == R_RISCV_TLS_IE_LO12_I \ -+ || (r_type) == R_RISCV_TLS_IE_LO12_S \ -+ || (r_type) == R_RISCV_TLS_GOT_HI20 \ -+ || (r_type) == R_RISCV_TLS_GOT_LO12) -+ -+#define TLS_GD_RELOC_P(r_type) \ -+ ((r_type) == R_RISCV_TLS_GD_HI20 \ -+ || (r_type) == R_RISCV_TLS_GD_LO12) -+ -+/* The structure of the runtime procedure descriptor created by the -+ loader for use by the static exception system. */ -+ -+typedef struct runtime_pdr { -+ bfd_vma adr; /* Memory address of start of procedure. */ -+ long regmask; /* Save register mask. */ -+ long regoffset; /* Save register offset. */ -+ long fregmask; /* Save floating point register mask. */ -+ long fregoffset; /* Save floating point register offset. */ -+ long frameoffset; /* Frame size. */ -+ short framereg; /* Frame pointer register. */ -+ short pcreg; /* Offset or reg of return pc. */ -+ long irpss; /* Index into the runtime string table. */ -+ long reserved; -+ struct exception_info *exception_info;/* Pointer to exception array. */ -+} RPDR, *pRPDR; -+#define cbRPDR sizeof (RPDR) -+#define rpdNil ((pRPDR) 0) -+ -+ -+static struct mips_got_entry *mips_elf_create_local_got_entry -+ (bfd *, struct bfd_link_info *, bfd *, bfd_vma, unsigned long, -+ struct mips_elf_link_hash_entry *, int); -+static bfd_boolean mips_elf_sort_hash_table_f -+ (struct mips_elf_link_hash_entry *, void *); -+static bfd_boolean mips_elf_create_dynamic_relocation -+ (bfd *, struct bfd_link_info *, const Elf_Internal_Rela *, -+ struct mips_elf_link_hash_entry *, asection *, bfd_vma, -+ bfd_vma *, asection *); -+static hashval_t mips_elf_got_entry_hash -+ (const void *); -+ -+/* This will be used when we sort the dynamic relocation records. */ -+static bfd *reldyn_sorting_bfd; -+ -+/* Nonzero if ABFD is using the RV64 ABI. */ -+#define ABI_64_P(abfd) \ -+ (get_elf_backend_data (abfd)->s->elfclass == ELFCLASS64) -+ -+/* Nonzero if ABFD is using the RV32 ABI. */ -+#define ABI_32_P(abfd) (!ABI_64_P(abfd)) -+ -+/* Whether the section is readonly. */ -+#define MIPS_ELF_READONLY_SECTION(sec) \ -+ ((sec->flags & (SEC_ALLOC | SEC_LOAD | SEC_READONLY)) \ -+ == (SEC_ALLOC | SEC_LOAD | SEC_READONLY)) -+ -+/* The size of an external REL relocation. */ -+#define MIPS_ELF_REL_SIZE(abfd) \ -+ (get_elf_backend_data (abfd)->s->sizeof_rel) -+ -+/* The size of an external dynamic table entry. */ -+#define MIPS_ELF_DYN_SIZE(abfd) \ -+ (get_elf_backend_data (abfd)->s->sizeof_dyn) -+ -+/* The size of a GOT entry. */ -+#define MIPS_ELF_GOT_SIZE(abfd) \ -+ (get_elf_backend_data (abfd)->s->arch_size / 8) -+ -+/* The size of a symbol-table entry. */ -+#define MIPS_ELF_SYM_SIZE(abfd) \ -+ (get_elf_backend_data (abfd)->s->sizeof_sym) -+ -+/* The default alignment for sections, as a power of two. */ -+#define MIPS_ELF_LOG_FILE_ALIGN(abfd) \ -+ (get_elf_backend_data (abfd)->s->log_file_align) -+ -+/* Get word-sized data. */ -+#define MIPS_ELF_GET_WORD(abfd, ptr) \ -+ (ABI_64_P (abfd) ? bfd_get_64 (abfd, ptr) : bfd_get_32 (abfd, ptr)) -+ -+/* Put out word-sized data. */ -+#define MIPS_ELF_PUT_WORD(abfd, val, ptr) \ -+ (ABI_64_P (abfd) \ -+ ? bfd_put_64 (abfd, val, ptr) \ -+ : bfd_put_32 (abfd, val, ptr)) -+ -+/* The name of the dynamic relocation section. */ -+#define MIPS_ELF_REL_DYN_NAME(INFO) ".rel.dyn" -+ -+/* In case we're on a 32-bit machine, construct a 64-bit "-1" value -+ from smaller values. Start with zero, widen, *then* decrement. */ -+#define MINUS_ONE (((bfd_vma)0) - 1) -+#define MINUS_TWO (((bfd_vma)0) - 2) -+ -+#define MIPS_FUNCTION_STUB_NORMAL_SIZE 16 -+#define MIPS_FUNCTION_STUB_BIG_SIZE 20 -+ -+/* The name of the dynamic interpreter. This is put in the .interp -+ section. */ -+ -+#define ELF_DYNAMIC_INTERPRETER(abfd) \ -+ (ABI_64_P (abfd) ? "/lib/ld.so.1" \ -+ : "/lib32/ld.so.1") -+ -+#ifdef BFD64 -+#define MNAME(bfd,pre,pos) \ -+ (ABI_64_P (bfd) ? CONCAT4 (pre,64,_,pos) : CONCAT4 (pre,32,_,pos)) -+#define ELF_R_SYM(bfd, i) \ -+ (ABI_64_P (bfd) ? ELF64_R_SYM (i) : ELF32_R_SYM (i)) -+#define ELF_R_TYPE(bfd, i) \ -+ (ABI_64_P (bfd) ? ELF64_MIPS_R_TYPE (i) : ELF32_R_TYPE (i)) -+#define ELF_R_INFO(bfd, s, t) \ -+ (ABI_64_P (bfd) ? ELF64_R_INFO (s, t) : ELF32_R_INFO (s, t)) -+#else -+#define MNAME(bfd,pre,pos) CONCAT4 (pre,32,_,pos) -+#define ELF_R_SYM(bfd, i) \ -+ (ELF32_R_SYM (i)) -+#define ELF_R_TYPE(bfd, i) \ -+ (ELF32_R_TYPE (i)) -+#define ELF_R_INFO(bfd, s, t) \ -+ (ELF32_R_INFO (s, t)) -+#endif -+ -+#define MATCH_LREG(abfd) (ABI_64_P(abfd) ? MATCH_LD : MATCH_LW) -+#define MATCH_SREG(abfd) (ABI_64_P(abfd) ? MATCH_SD : MATCH_SW) -+ -+#define OPCODE_MATCHES(OPCODE, OP) \ -+ (((OPCODE) & MASK_##OP) == MATCH_##OP) -+ -+#define MINUS_ONE (((bfd_vma)0) - 1) -+ -+/* The relocation table used for SHT_RELA sections. */ -+ -+static reloc_howto_type howto_table[] = -+{ -+ /* No relocation. */ -+ HOWTO (R_RISCV_NONE, /* type */ -+ 0, /* rightshift */ -+ 0, /* size (0 = byte, 1 = short, 2 = long) */ -+ 0, /* bitsize */ -+ FALSE, /* pc_relative */ -+ 0, /* bitpos */ -+ complain_overflow_dont, /* complain_on_overflow */ -+ _bfd_riscv_elf_generic_reloc, /* special_function */ -+ "R_RISCV_NONE", /* name */ -+ FALSE, /* partial_inplace */ -+ 0, /* src_mask */ -+ 0, /* dst_mask */ -+ FALSE), /* pcrel_offset */ -+ -+ EMPTY_HOWTO (1), -+ -+ /* 32 bit relocation. */ -+ HOWTO (R_RISCV_32, /* type */ -+ 0, /* rightshift */ -+ 2, /* size (0 = byte, 1 = short, 2 = long) */ -+ 32, /* bitsize */ -+ FALSE, /* pc_relative */ -+ 0, /* bitpos */ -+ complain_overflow_dont, /* complain_on_overflow */ -+ _bfd_riscv_elf_generic_reloc, /* special_function */ -+ "R_RISCV_32", /* name */ -+ FALSE, /* partial_inplace */ -+ 0, /* src_mask */ -+ 0xffffffff, /* dst_mask */ -+ FALSE), /* pcrel_offset */ -+ -+ /* 32 bit symbol relative relocation. */ -+ HOWTO (R_RISCV_REL32, /* type */ -+ 0, /* rightshift */ -+ 2, /* size (0 = byte, 1 = short, 2 = long) */ -+ 32, /* bitsize */ -+ FALSE, /* pc_relative */ -+ 0, /* bitpos */ -+ complain_overflow_dont, /* complain_on_overflow */ -+ _bfd_riscv_elf_generic_reloc, /* special_function */ -+ "R_RISCV_REL32", /* name */ -+ FALSE, /* partial_inplace */ -+ 0, /* src_mask */ -+ 0xffffffff, /* dst_mask */ -+ FALSE), /* pcrel_offset */ -+ -+ /* 26 bit jump address. */ -+ HOWTO (R_RISCV_JAL, /* type */ -+ 0, /* rightshift */ -+ 2, /* size (0 = byte, 1 = short, 2 = long) */ -+ 32, /* bitsize */ -+ TRUE, /* pc_relative */ -+ 0, /* bitpos */ -+ complain_overflow_dont, /* complain_on_overflow */ -+ /* This needs complex overflow -+ detection, because the upper 36 -+ bits must match the PC + 4. */ -+ _bfd_riscv_elf_generic_reloc, /* special_function */ -+ "R_RISCV_JAL", /* name */ -+ FALSE, /* partial_inplace */ -+ 0, /* src_mask */ -+ ENCODE_UJTYPE_IMM(-1U), /* dst_mask */ -+ TRUE), /* pcrel_offset */ -+ -+ /* High 16 bits of symbol value. */ -+ HOWTO (R_RISCV_HI20, /* type */ -+ 0, /* rightshift */ -+ 2, /* size (0 = byte, 1 = short, 2 = long) */ -+ 32, /* bitsize */ -+ FALSE, /* pc_relative */ -+ 0, /* bitpos */ -+ complain_overflow_dont, /* complain_on_overflow */ -+ _bfd_riscv_elf_generic_reloc, /* special_function */ -+ "R_RISCV_HI20", /* name */ -+ FALSE, /* partial_inplace */ -+ 0, /* src_mask */ -+ ENCODE_UTYPE_IMM(-1U), /* dst_mask */ -+ FALSE), /* pcrel_offset */ -+ -+ /* Low 12 bits of symbol value. */ -+ HOWTO (R_RISCV_LO12_I, /* type */ -+ 0, /* rightshift */ -+ 2, /* size (0 = byte, 1 = short, 2 = long) */ -+ RISCV_IMM_BITS, /* bitsize */ -+ FALSE, /* pc_relative */ -+ 0, /* bitpos */ -+ complain_overflow_dont, /* complain_on_overflow */ -+ _bfd_riscv_elf_generic_reloc, /* special_function */ -+ "R_RISCV_LO12_I", /* name */ -+ FALSE, /* partial_inplace */ -+ 0, /* src_mask */ -+ ENCODE_ITYPE_IMM(-1U) | (OP_MASK_RS1 << OP_SH_RS1), /* dst_mask */ -+ FALSE), /* pcrel_offset */ -+ -+ /* Low 12 bits of symbol value. */ -+ HOWTO (R_RISCV_LO12_S, /* type */ -+ 0, /* rightshift */ -+ 2, /* size (0 = byte, 1 = short, 2 = long) */ -+ RISCV_IMM_BITS, /* bitsize */ -+ FALSE, /* pc_relative */ -+ 0, /* bitpos */ -+ complain_overflow_dont, /* complain_on_overflow */ -+ _bfd_riscv_elf_generic_reloc, /* special_function */ -+ "R_RISCV_LO12_S", /* name */ -+ FALSE, /* partial_inplace */ -+ 0, /* src_mask */ -+ ENCODE_STYPE_IMM(-1U) | (OP_MASK_RS1 << OP_SH_RS1), /* dst_mask */ -+ FALSE), /* pcrel_offset */ -+ -+ /* Distance between AUIPC and corresponding ADD/load. */ -+ HOWTO (R_RISCV_PCREL_LO12_I, /* type */ -+ 0, /* rightshift */ -+ 2, /* size (0 = byte, 1 = short, 2 = long) */ -+ RISCV_IMM_BITS, /* bitsize */ -+ FALSE, /* pc_relative */ -+ 0, /* bitpos */ -+ complain_overflow_dont, /* complain_on_overflow */ -+ _bfd_riscv_elf_generic_reloc, /* special_function */ -+ "R_RISCV_PCREL_LO12_I",/* name */ -+ FALSE, /* partial_inplace */ -+ 0, /* src_mask */ -+ ENCODE_ITYPE_IMM(-1U), /* dst_mask */ -+ FALSE), /* pcrel_offset */ -+ -+ /* Distance between AUIPC and corresponding store. */ -+ HOWTO (R_RISCV_PCREL_LO12_S, /* type */ -+ 0, /* rightshift */ -+ 2, /* size (0 = byte, 1 = short, 2 = long) */ -+ RISCV_IMM_BITS, /* bitsize */ -+ FALSE, /* pc_relative */ -+ 0, /* bitpos */ -+ complain_overflow_dont, /* complain_on_overflow */ -+ _bfd_riscv_elf_generic_reloc, /* special_function */ -+ "R_RISCV_PCREL_LO12_S",/* name */ -+ FALSE, /* partial_inplace */ -+ 0, /* src_mask */ -+ ENCODE_STYPE_IMM(-1U), /* dst_mask */ -+ FALSE), /* pcrel_offset */ -+ -+ HOWTO (R_RISCV_BRANCH, /* type */ -+ 0, /* rightshift */ -+ 2, /* size (0 = byte, 1 = short, 2 = long) */ -+ RISCV_IMM_BITS, /* bitsize */ -+ TRUE, /* pc_relative */ -+ 0, /* bitpos */ -+ complain_overflow_signed, /* complain_on_overflow */ -+ _bfd_riscv_elf_generic_reloc, /* special_function */ -+ "R_RISCV_BRANCH", /* name */ -+ FALSE, /* partial_inplace */ -+ 0, /* src_mask */ -+ ENCODE_SBTYPE_IMM(-1U), /* dst_mask */ -+ TRUE), /* pcrel_offset */ -+ -+ HOWTO (R_RISCV_CALL, /* type */ -+ 0, /* rightshift */ -+ 2, /* size (0 = byte, 1 = short, 2 = long) */ -+ 32, /* bitsize */ -+ TRUE, /* pc_relative */ -+ 0, /* bitpos */ -+ complain_overflow_dont, /* complain_on_overflow */ -+ _bfd_riscv_elf_generic_reloc, /* special_function */ -+ "R_RISCV_CALL", /* name */ -+ FALSE, /* partial_inplace */ -+ 0, /* src_mask */ -+ 0, /* dst_mask */ -+ TRUE), /* pcrel_offset */ -+ -+ HOWTO (R_RISCV_PCREL_HI20, /* type */ -+ 0, /* rightshift */ -+ 2, /* size (0 = byte, 1 = short, 2 = long) */ -+ 32, /* bitsize */ -+ TRUE, /* pc_relative */ -+ 0, /* bitpos */ -+ complain_overflow_dont, /* complain_on_overflow */ -+ _bfd_riscv_elf_generic_reloc, /* special_function */ -+ "R_RISCV_PCREL_HI20", /* name */ -+ FALSE, /* partial_inplace */ -+ 0, /* src_mask */ -+ ENCODE_UTYPE_IMM(-1U), /* dst_mask */ -+ TRUE), /* pcrel_offset */ -+ -+ HOWTO (R_RISCV_CALL_PLT, /* type */ -+ 0, /* rightshift */ -+ 2, /* size (0 = byte, 1 = short, 2 = long) */ -+ 32, /* bitsize */ -+ TRUE, /* pc_relative */ -+ 0, /* bitpos */ -+ complain_overflow_dont, /* complain_on_overflow */ -+ _bfd_riscv_elf_generic_reloc, /* special_function */ -+ "R_RISCV_CALL_PLT", /* name */ -+ FALSE, /* partial_inplace */ -+ 0, /* src_mask */ -+ 0, /* dst_mask */ -+ TRUE), /* pcrel_offset */ -+ -+ EMPTY_HOWTO (14), -+ EMPTY_HOWTO (15), -+ EMPTY_HOWTO (16), -+ EMPTY_HOWTO (17), -+ -+ /* 64 bit relocation. */ -+ HOWTO (R_RISCV_64, /* type */ -+ 0, /* rightshift */ -+ 4, /* size (0 = byte, 1 = short, 2 = long) */ -+ 64, /* bitsize */ -+ FALSE, /* pc_relative */ -+ 0, /* bitpos */ -+ complain_overflow_dont, /* complain_on_overflow */ -+ _bfd_riscv_elf_generic_reloc, /* special_function */ -+ "R_RISCV_64", /* name */ -+ FALSE, /* partial_inplace */ -+ 0, /* src_mask */ -+ MINUS_ONE, /* dst_mask */ -+ FALSE), /* pcrel_offset */ -+ -+ EMPTY_HOWTO (19), -+ EMPTY_HOWTO (20), -+ EMPTY_HOWTO (21), -+ -+ /* High 16 bits of displacement in global offset table. */ -+ HOWTO (R_RISCV_GOT_HI20, /* type */ -+ 0, /* rightshift */ -+ 2, /* size (0 = byte, 1 = short, 2 = long) */ -+ 32, /* bitsize */ -+ TRUE, /* pc_relative */ -+ 0, /* bitpos */ -+ complain_overflow_dont, /* complain_on_overflow */ -+ _bfd_riscv_elf_generic_reloc, /* special_function */ -+ "R_RISCV_GOT_HI20", /* name */ -+ FALSE, /* partial_inplace */ -+ 0, /* src_mask */ -+ ENCODE_UTYPE_IMM(-1U), /* dst_mask */ -+ FALSE), /* pcrel_offset */ -+ -+ /* Low 16 bits of displacement in global offset table. */ -+ HOWTO (R_RISCV_GOT_LO12, /* type */ -+ 0, /* rightshift */ -+ 2, /* size (0 = byte, 1 = short, 2 = long) */ -+ RISCV_IMM_BITS, /* bitsize */ -+ TRUE, /* pc_relative */ -+ 0, /* bitpos */ -+ complain_overflow_dont, /* complain_on_overflow */ -+ _bfd_riscv_elf_generic_reloc, /* special_function */ -+ "R_RISCV_GOT_LO12", /* name */ -+ FALSE, /* partial_inplace */ -+ 0, /* src_mask */ -+ ENCODE_ITYPE_IMM(-1U), /* dst_mask */ -+ FALSE), /* pcrel_offset */ -+ -+ HOWTO (R_RISCV_COPY, /* type */ -+ 0, /* rightshift */ -+ 0, /* this one is variable size */ -+ 0, /* bitsize */ -+ FALSE, /* pc_relative */ -+ 0, /* bitpos */ -+ complain_overflow_bitfield, /* complain_on_overflow */ -+ bfd_elf_generic_reloc, /* special_function */ -+ "R_RISCV_COPY", /* name */ -+ FALSE, /* partial_inplace */ -+ 0x0, /* src_mask */ -+ 0x0, /* dst_mask */ -+ FALSE), /* pcrel_offset */ -+ -+ HOWTO (R_RISCV_JUMP_SLOT, /* type */ -+ 0, /* rightshift */ -+ 4, /* size (0 = byte, 1 = short, 2 = long) */ -+ 64, /* bitsize */ -+ FALSE, /* pc_relative */ -+ 0, /* bitpos */ -+ complain_overflow_bitfield, /* complain_on_overflow */ -+ bfd_elf_generic_reloc, /* special_function */ -+ "R_RISCV_JUMP_SLOT", /* name */ -+ FALSE, /* partial_inplace */ -+ 0x0, /* src_mask */ -+ 0x0, /* dst_mask */ -+ FALSE), /* pcrel_offset */ -+ -+ EMPTY_HOWTO (26), -+ EMPTY_HOWTO (27), -+ EMPTY_HOWTO (28), -+ -+ /* TLS IE GOT access in non-PIC code. */ -+ HOWTO (R_RISCV_TLS_IE_HI20, /* type */ -+ 0, /* rightshift */ -+ 2, /* size (0 = byte, 1 = short, 2 = long) */ -+ 32, /* bitsize */ -+ FALSE, /* pc_relative */ -+ 0, /* bitpos */ -+ complain_overflow_signed, /* complain_on_overflow */ -+ _bfd_riscv_elf_generic_reloc, /* special_function */ -+ "R_RISCV_TLS_IE_HI20", /* name */ -+ TRUE, /* partial_inplace */ -+ 0, /* src_mask */ -+ ENCODE_UTYPE_IMM(-1U), /* dst_mask */ -+ FALSE), /* pcrel_offset */ -+ -+ /* TLS IE GOT access in non-PIC code. */ -+ HOWTO (R_RISCV_TLS_IE_LO12, /* type */ -+ 0, /* rightshift */ -+ 2, /* size (0 = byte, 1 = short, 2 = long) */ -+ RISCV_IMM_BITS, /* bitsize */ -+ FALSE, /* pc_relative */ -+ 0, /* bitpos */ -+ complain_overflow_signed, /* complain_on_overflow */ -+ _bfd_riscv_elf_generic_reloc, /* special_function */ -+ "R_RISCV_TLS_IE_LO12_I",/* name */ -+ FALSE, /* partial_inplace */ -+ 0, /* src_mask */ -+ ENCODE_ITYPE_IMM(-1U), /* dst_mask */ -+ FALSE), /* pcrel_offset */ -+ -+ /* TLS IE thread pointer usage. */ -+ HOWTO (R_RISCV_TLS_IE_ADD, /* type */ -+ 0, /* rightshift */ -+ 2, /* size (0 = byte, 1 = short, 2 = long) */ -+ 32, /* bitsize */ -+ FALSE, /* pc_relative */ -+ 0, /* bitpos */ -+ complain_overflow_dont,/* complain_on_overflow */ -+ _bfd_riscv_elf_generic_reloc, /* special_function */ -+ "R_RISCV_TLS_IE_ADD", /* name */ -+ TRUE, /* partial_inplace */ -+ 0, /* src_mask */ -+ 0, /* dst_mask */ -+ FALSE), /* pcrel_offset */ -+ -+ /* TLS IE low-part relocation for relaxation. */ -+ HOWTO (R_RISCV_TLS_IE_LO12_I, /* type */ -+ 0, /* rightshift */ -+ 2, /* size (0 = byte, 1 = short, 2 = long) */ -+ RISCV_IMM_BITS, /* bitsize */ -+ FALSE, /* pc_relative */ -+ 0, /* bitpos */ -+ complain_overflow_signed, /* complain_on_overflow */ -+ _bfd_riscv_elf_generic_reloc, /* special_function */ -+ "R_RISCV_TLS_IE_LO12_I",/* name */ -+ TRUE, /* partial_inplace */ -+ 0, /* src_mask */ -+ 0, /* dst_mask */ -+ FALSE), /* pcrel_offset */ -+ -+ /* TLS IE low-part relocation for relaxation. */ -+ HOWTO (R_RISCV_TLS_IE_LO12_S, /* type */ -+ 0, /* rightshift */ -+ 2, /* size (0 = byte, 1 = short, 2 = long) */ -+ RISCV_IMM_BITS, /* bitsize */ -+ FALSE, /* pc_relative */ -+ 0, /* bitpos */ -+ complain_overflow_signed, /* complain_on_overflow */ -+ _bfd_riscv_elf_generic_reloc, /* special_function */ -+ "R_RISCV_TLS_IE_LO12_S",/* name */ -+ TRUE, /* partial_inplace */ -+ 0, /* src_mask */ -+ 0, /* dst_mask */ -+ FALSE), /* pcrel_offset */ -+ -+ /* TLS LE thread pointer offset. */ -+ HOWTO (R_RISCV_TPREL_HI20, /* type */ -+ 0, /* rightshift */ -+ 2, /* size (0 = byte, 1 = short, 2 = long) */ -+ 32, /* bitsize */ -+ FALSE, /* pc_relative */ -+ 0, /* bitpos */ -+ complain_overflow_signed, /* complain_on_overflow */ -+ _bfd_riscv_elf_generic_reloc, /* special_function */ -+ "R_RISCV_TPREL_HI20", /* name */ -+ TRUE, /* partial_inplace */ -+ 0, /* src_mask */ -+ ENCODE_UTYPE_IMM(-1U), /* dst_mask */ -+ FALSE), /* pcrel_offset */ -+ -+ /* TLS LE thread pointer offset. */ -+ HOWTO (R_RISCV_TPREL_LO12_I, /* type */ -+ 0, /* rightshift */ -+ 2, /* size (0 = byte, 1 = short, 2 = long) */ -+ RISCV_IMM_BITS, /* bitsize */ -+ FALSE, /* pc_relative */ -+ 0, /* bitpos */ -+ complain_overflow_signed, /* complain_on_overflow */ -+ _bfd_riscv_elf_generic_reloc, /* special_function */ -+ "R_RISCV_TPREL_LO12_I",/* name */ -+ FALSE, /* partial_inplace */ -+ 0, /* src_mask */ -+ ENCODE_ITYPE_IMM(-1U) | (OP_MASK_RS1 << OP_SH_RS1), /* dst_mask */ -+ FALSE), /* pcrel_offset */ -+ -+ /* TLS LE thread pointer offset. */ -+ HOWTO (R_RISCV_TPREL_LO12_S, /* type */ -+ 0, /* rightshift */ -+ 2, /* size (0 = byte, 1 = short, 2 = long) */ -+ RISCV_IMM_BITS, /* bitsize */ -+ FALSE, /* pc_relative */ -+ 0, /* bitpos */ -+ complain_overflow_signed, /* complain_on_overflow */ -+ _bfd_riscv_elf_generic_reloc, /* special_function */ -+ "R_RISCV_TPREL_LO12_S",/* name */ -+ FALSE, /* partial_inplace */ -+ 0, /* src_mask */ -+ ENCODE_STYPE_IMM(-1U) | (OP_MASK_RS1 << OP_SH_RS1), /* dst_mask */ -+ FALSE), /* pcrel_offset */ -+ -+ /* TLS LE thread pointer usage. */ -+ HOWTO (R_RISCV_TPREL_ADD, /* type */ -+ 0, /* rightshift */ -+ 2, /* size (0 = byte, 1 = short, 2 = long) */ -+ 32, /* bitsize */ -+ FALSE, /* pc_relative */ -+ 0, /* bitpos */ -+ complain_overflow_dont,/* complain_on_overflow */ -+ _bfd_riscv_elf_generic_reloc, /* special_function */ -+ "R_RISCV_TPREL_ADD", /* name */ -+ TRUE, /* partial_inplace */ -+ 0, /* src_mask */ -+ 0, /* dst_mask */ -+ FALSE), /* pcrel_offset */ -+ -+ /* TLS relocations. */ -+ HOWTO (R_RISCV_TLS_DTPMOD32, /* type */ -+ 0, /* rightshift */ -+ 4, /* size (0 = byte, 1 = short, 2 = long) */ -+ 32, /* bitsize */ -+ FALSE, /* pc_relative */ -+ 0, /* bitpos */ -+ complain_overflow_dont, /* complain_on_overflow */ -+ _bfd_riscv_elf_generic_reloc, /* special_function */ -+ "R_RISCV_TLS_DTPMOD32", /* name */ -+ FALSE, /* partial_inplace */ -+ MINUS_ONE, /* src_mask */ -+ MINUS_ONE, /* dst_mask */ -+ FALSE), /* pcrel_offset */ -+ -+ HOWTO (R_RISCV_TLS_DTPREL32, /* type */ -+ 0, /* rightshift */ -+ 4, /* size (0 = byte, 1 = short, 2 = long) */ -+ 32, /* bitsize */ -+ FALSE, /* pc_relative */ -+ 0, /* bitpos */ -+ complain_overflow_dont, /* complain_on_overflow */ -+ _bfd_riscv_elf_generic_reloc, /* special_function */ -+ "R_RISCV_TLS_DTPREL32", /* name */ -+ TRUE, /* partial_inplace */ -+ MINUS_ONE, /* src_mask */ -+ MINUS_ONE, /* dst_mask */ -+ FALSE), /* pcrel_offset */ -+ -+ HOWTO (R_RISCV_TLS_DTPMOD64, /* type */ -+ 0, /* rightshift */ -+ 4, /* size (0 = byte, 1 = short, 2 = long) */ -+ 64, /* bitsize */ -+ FALSE, /* pc_relative */ -+ 0, /* bitpos */ -+ complain_overflow_dont, /* complain_on_overflow */ -+ _bfd_riscv_elf_generic_reloc, /* special_function */ -+ "R_RISCV_TLS_DTPMOD64", /* name */ -+ FALSE, /* partial_inplace */ -+ MINUS_ONE, /* src_mask */ -+ MINUS_ONE, /* dst_mask */ -+ FALSE), /* pcrel_offset */ -+ -+ HOWTO (R_RISCV_TLS_DTPREL64, /* type */ -+ 0, /* rightshift */ -+ 4, /* size (0 = byte, 1 = short, 2 = long) */ -+ 64, /* bitsize */ -+ FALSE, /* pc_relative */ -+ 0, /* bitpos */ -+ complain_overflow_dont, /* complain_on_overflow */ -+ _bfd_riscv_elf_generic_reloc, /* special_function */ -+ "R_RISCV_TLS_DTPREL64", /* name */ -+ TRUE, /* partial_inplace */ -+ MINUS_ONE, /* src_mask */ -+ MINUS_ONE, /* dst_mask */ -+ FALSE), /* pcrel_offset */ -+ -+ EMPTY_HOWTO (42), -+ EMPTY_HOWTO (43), -+ EMPTY_HOWTO (44), -+ EMPTY_HOWTO (45), -+ EMPTY_HOWTO (46), -+ -+ HOWTO (R_RISCV_TLS_TPREL32, /* type */ -+ 0, /* rightshift */ -+ 2, /* size (0 = byte, 1 = short, 2 = long) */ -+ 32, /* bitsize */ -+ FALSE, /* pc_relative */ -+ 0, /* bitpos */ -+ complain_overflow_dont, /* complain_on_overflow */ -+ _bfd_riscv_elf_generic_reloc, /* special_function */ -+ "R_RISCV_TLS_TPREL32", /* name */ -+ FALSE, /* partial_inplace */ -+ MINUS_ONE, /* src_mask */ -+ MINUS_ONE, /* dst_mask */ -+ FALSE), /* pcrel_offset */ -+ -+ HOWTO (R_RISCV_TLS_TPREL64, /* type */ -+ 0, /* rightshift */ -+ 4, /* size (0 = byte, 1 = short, 2 = long) */ -+ 64, /* bitsize */ -+ FALSE, /* pc_relative */ -+ 0, /* bitpos */ -+ complain_overflow_dont, /* complain_on_overflow */ -+ _bfd_riscv_elf_generic_reloc, /* special_function */ -+ "R_RISCV_TLS_TPREL64", /* name */ -+ FALSE, /* partial_inplace */ -+ MINUS_ONE, /* src_mask */ -+ MINUS_ONE, /* dst_mask */ -+ FALSE), /* pcrel_offset */ -+ -+ EMPTY_HOWTO (49), -+ -+ /* Distance between AUIPC and corresponding ADD/load. */ -+ HOWTO (R_RISCV_TLS_PCREL_LO12,/* type */ -+ 0, /* rightshift */ -+ 2, /* size (0 = byte, 1 = short, 2 = long) */ -+ RISCV_IMM_BITS, /* bitsize */ -+ FALSE, /* pc_relative */ -+ 0, /* bitpos */ -+ complain_overflow_dont, /* complain_on_overflow */ -+ _bfd_riscv_elf_generic_reloc, /* special_function */ -+ "R_RISCV_TLS_PCREL_LO12",/* name */ -+ FALSE, /* partial_inplace */ -+ 0, /* src_mask */ -+ ENCODE_ITYPE_IMM(-1U), /* dst_mask */ -+ FALSE), /* pcrel_offset */ -+ -+ /* High 16 bits of displacement in global offset table. */ -+ HOWTO (R_RISCV_TLS_GOT_HI20, /* type */ -+ 0, /* rightshift */ -+ 2, /* size (0 = byte, 1 = short, 2 = long) */ -+ 32, /* bitsize */ -+ TRUE, /* pc_relative */ -+ 0, /* bitpos */ -+ complain_overflow_dont, /* complain_on_overflow */ -+ _bfd_riscv_elf_generic_reloc, /* special_function */ -+ "R_RISCV_TLS_GOT_HI20", /* name */ -+ FALSE, /* partial_inplace */ -+ 0, /* src_mask */ -+ ENCODE_UTYPE_IMM(-1U), /* dst_mask */ -+ FALSE), /* pcrel_offset */ -+ -+ /* Low 16 bits of displacement in global offset table. */ -+ HOWTO (R_RISCV_TLS_GOT_LO12, /* type */ -+ 0, /* rightshift */ -+ 2, /* size (0 = byte, 1 = short, 2 = long) */ -+ RISCV_IMM_BITS, /* bitsize */ -+ TRUE, /* pc_relative */ -+ 0, /* bitpos */ -+ complain_overflow_dont, /* complain_on_overflow */ -+ _bfd_riscv_elf_generic_reloc, /* special_function */ -+ "R_RISCV_TLS_GOT_LO12", /* name */ -+ FALSE, /* partial_inplace */ -+ 0, /* src_mask */ -+ ENCODE_ITYPE_IMM(-1U), /* dst_mask */ -+ FALSE), /* pcrel_offset */ -+ -+ /* High 16 bits of displacement in global offset table. */ -+ HOWTO (R_RISCV_TLS_GD_HI20, /* type */ -+ 0, /* rightshift */ -+ 2, /* size (0 = byte, 1 = short, 2 = long) */ -+ 32, /* bitsize */ -+ FALSE, /* pc_relative */ -+ 0, /* bitpos */ -+ complain_overflow_dont, /* complain_on_overflow */ -+ _bfd_riscv_elf_generic_reloc, /* special_function */ -+ "R_RISCV_TLS_GD_HI20", /* name */ -+ FALSE, /* partial_inplace */ -+ 0, /* src_mask */ -+ ENCODE_UTYPE_IMM(-1U), /* dst_mask */ -+ FALSE), /* pcrel_offset */ -+ -+ /* Low 16 bits of displacement in global offset table. */ -+ HOWTO (R_RISCV_TLS_GD_LO12, /* type */ -+ 0, /* rightshift */ -+ 2, /* size (0 = byte, 1 = short, 2 = long) */ -+ RISCV_IMM_BITS, /* bitsize */ -+ FALSE, /* pc_relative */ -+ 0, /* bitpos */ -+ complain_overflow_dont, /* complain_on_overflow */ -+ _bfd_riscv_elf_generic_reloc, /* special_function */ -+ "R_RISCV_TLS_GD_LO12", /* name */ -+ FALSE, /* partial_inplace */ -+ 0, /* src_mask */ -+ ENCODE_ITYPE_IMM(-1U), /* dst_mask */ -+ FALSE), /* pcrel_offset */ -+ -+ EMPTY_HOWTO (55), -+ EMPTY_HOWTO (56), -+ -+ /* 32 bit relocation with no addend. */ -+ HOWTO (R_RISCV_GLOB_DAT, /* type */ -+ 0, /* rightshift */ -+ 2, /* size (0 = byte, 1 = short, 2 = long) */ -+ 32, /* bitsize */ -+ FALSE, /* pc_relative */ -+ 0, /* bitpos */ -+ complain_overflow_dont, /* complain_on_overflow */ -+ _bfd_riscv_elf_generic_reloc, /* special_function */ -+ "R_RISCV_GLOB_DAT", /* name */ -+ FALSE, /* partial_inplace */ -+ 0x0, /* src_mask */ -+ 0xffffffff, /* dst_mask */ -+ FALSE), /* pcrel_offset */ -+ -+ /* 32 bit in-place addition, for local label subtraction. */ -+ HOWTO (R_RISCV_ADD32, /* type */ -+ 0, /* rightshift */ -+ 2, /* size (0 = byte, 1 = short, 2 = long) */ -+ 32, /* bitsize */ -+ FALSE, /* pc_relative */ -+ 0, /* bitpos */ -+ complain_overflow_dont, /* complain_on_overflow */ -+ _bfd_riscv_elf_generic_reloc, /* special_function */ -+ "R_RISCV_ADD32", /* name */ -+ FALSE, /* partial_inplace */ -+ 0, /* src_mask */ -+ MINUS_ONE, /* dst_mask */ -+ FALSE), /* pcrel_offset */ -+ -+ /* 64 bit in-place addition, for local label subtraction. */ -+ HOWTO (R_RISCV_ADD64, /* type */ -+ 0, /* rightshift */ -+ 4, /* size (0 = byte, 1 = short, 2 = long) */ -+ 64, /* bitsize */ -+ FALSE, /* pc_relative */ -+ 0, /* bitpos */ -+ complain_overflow_dont, /* complain_on_overflow */ -+ _bfd_riscv_elf_generic_reloc, /* special_function */ -+ "R_RISCV_ADD64", /* name */ -+ FALSE, /* partial_inplace */ -+ 0, /* src_mask */ -+ MINUS_ONE, /* dst_mask */ -+ FALSE), /* pcrel_offset */ -+ -+ /* 32 bit in-place addition, for local label subtraction. */ -+ HOWTO (R_RISCV_SUB32, /* type */ -+ 0, /* rightshift */ -+ 2, /* size (0 = byte, 1 = short, 2 = long) */ -+ 32, /* bitsize */ -+ FALSE, /* pc_relative */ -+ 0, /* bitpos */ -+ complain_overflow_dont, /* complain_on_overflow */ -+ _bfd_riscv_elf_generic_reloc, /* special_function */ -+ "R_RISCV_SUB32", /* name */ -+ FALSE, /* partial_inplace */ -+ 0, /* src_mask */ -+ MINUS_ONE, /* dst_mask */ -+ FALSE), /* pcrel_offset */ -+ -+ /* 64 bit in-place addition, for local label subtraction. */ -+ HOWTO (R_RISCV_SUB64, /* type */ -+ 0, /* rightshift */ -+ 4, /* size (0 = byte, 1 = short, 2 = long) */ -+ 64, /* bitsize */ -+ FALSE, /* pc_relative */ -+ 0, /* bitpos */ -+ complain_overflow_dont, /* complain_on_overflow */ -+ _bfd_riscv_elf_generic_reloc, /* special_function */ -+ "R_RISCV_SUB64", /* name */ -+ FALSE, /* partial_inplace */ -+ 0, /* src_mask */ -+ MINUS_ONE, /* dst_mask */ -+ FALSE), /* pcrel_offset */ -+}; -+ -+/* A mapping from BFD reloc types to MIPS ELF reloc types. */ -+ -+struct elf_reloc_map { -+ bfd_reloc_code_real_type bfd_val; -+ enum elf_riscv_reloc_type elf_val; -+}; -+ -+static const struct elf_reloc_map riscv_reloc_map[] = -+{ -+ { BFD_RELOC_NONE, R_RISCV_NONE }, -+ { BFD_RELOC_32, R_RISCV_32 }, -+ { BFD_RELOC_64, R_RISCV_64 }, -+ { BFD_RELOC_RISCV_ADD32, R_RISCV_ADD32 }, -+ { BFD_RELOC_RISCV_ADD64, R_RISCV_ADD64 }, -+ { BFD_RELOC_RISCV_SUB32, R_RISCV_SUB32 }, -+ { BFD_RELOC_RISCV_SUB64, R_RISCV_SUB64 }, -+ { BFD_RELOC_CTOR, R_RISCV_64 }, -+ { BFD_RELOC_12_PCREL, R_RISCV_BRANCH }, -+ { BFD_RELOC_RISCV_HI20, R_RISCV_HI20 }, -+ { BFD_RELOC_RISCV_LO12_I, R_RISCV_LO12_I }, -+ { BFD_RELOC_RISCV_LO12_S, R_RISCV_LO12_S }, -+ { BFD_RELOC_RISCV_PCREL_LO12_I, R_RISCV_PCREL_LO12_I }, -+ { BFD_RELOC_RISCV_PCREL_LO12_S, R_RISCV_PCREL_LO12_S }, -+ { BFD_RELOC_RISCV_CALL, R_RISCV_CALL }, -+ { BFD_RELOC_RISCV_CALL_PLT, R_RISCV_CALL_PLT }, -+ { BFD_RELOC_RISCV_PCREL_HI20, R_RISCV_PCREL_HI20 }, -+ { BFD_RELOC_MIPS_JMP, R_RISCV_JAL }, -+ { BFD_RELOC_RISCV_GOT_HI20, R_RISCV_GOT_HI20 }, -+ { BFD_RELOC_RISCV_GOT_LO12, R_RISCV_GOT_LO12 }, -+ { BFD_RELOC_MIPS_TLS_DTPMOD32, R_RISCV_TLS_DTPMOD32 }, -+ { BFD_RELOC_MIPS_TLS_DTPREL32, R_RISCV_TLS_DTPREL32 }, -+ { BFD_RELOC_MIPS_TLS_DTPMOD64, R_RISCV_TLS_DTPMOD64 }, -+ { BFD_RELOC_MIPS_TLS_DTPREL64, R_RISCV_TLS_DTPREL64 }, -+ { BFD_RELOC_MIPS_TLS_TPREL32, R_RISCV_TLS_TPREL32 }, -+ { BFD_RELOC_MIPS_TLS_TPREL64, R_RISCV_TLS_TPREL64 }, -+ { BFD_RELOC_RISCV_TPREL_HI20, R_RISCV_TPREL_HI20 }, -+ { BFD_RELOC_RISCV_TPREL_ADD, R_RISCV_TPREL_ADD }, -+ { BFD_RELOC_RISCV_TPREL_LO12_S, R_RISCV_TPREL_LO12_S }, -+ { BFD_RELOC_RISCV_TPREL_LO12_I, R_RISCV_TPREL_LO12_I }, -+ { BFD_RELOC_RISCV_TLS_IE_HI20, R_RISCV_TLS_IE_HI20 }, -+ { BFD_RELOC_RISCV_TLS_IE_LO12, R_RISCV_TLS_IE_LO12 }, -+ { BFD_RELOC_RISCV_TLS_IE_ADD, R_RISCV_TLS_IE_ADD }, -+ { BFD_RELOC_RISCV_TLS_IE_LO12_S, R_RISCV_TLS_IE_LO12_S }, -+ { BFD_RELOC_RISCV_TLS_IE_LO12_I, R_RISCV_TLS_IE_LO12_I }, -+ { BFD_RELOC_RISCV_TLS_GOT_HI20, R_RISCV_TLS_GOT_HI20 }, -+ { BFD_RELOC_RISCV_TLS_GOT_LO12, R_RISCV_TLS_GOT_LO12 }, -+ { BFD_RELOC_RISCV_TLS_GD_HI20, R_RISCV_TLS_GD_HI20 }, -+ { BFD_RELOC_RISCV_TLS_GD_LO12, R_RISCV_TLS_GD_LO12 }, -+ { BFD_RELOC_RISCV_TLS_PCREL_LO12, R_RISCV_TLS_PCREL_LO12 }, -+}; -+ -+/* Given a BFD reloc type, return a howto structure. */ -+ -+reloc_howto_type * -+riscv_elf_bfd_reloc_type_lookup (bfd *abfd ATTRIBUTE_UNUSED, -+ bfd_reloc_code_real_type code) -+{ -+ unsigned int i; -+ -+ for (i = 0; i < sizeof (riscv_reloc_map) / sizeof (riscv_reloc_map[0]); i++) -+ if (riscv_reloc_map[i].bfd_val == code) -+ return &howto_table[(int) riscv_reloc_map[i].elf_val]; -+ -+ bfd_set_error (bfd_error_bad_value); -+ return NULL; -+} -+ -+reloc_howto_type * -+riscv_elf_bfd_reloc_name_lookup (bfd *abfd ATTRIBUTE_UNUSED, -+ const char *r_name) -+{ -+ unsigned int i; -+ -+ for (i = 0; i < sizeof (howto_table) / sizeof (howto_table[0]); i++) -+ if (howto_table[i].name && strcasecmp (howto_table[i].name, r_name) == 0) -+ return &howto_table[i]; -+ -+ return NULL; -+} -+ -+/* Given a MIPS Elf_Internal_Rel, fill in an arelent structure. */ -+ -+static reloc_howto_type * -+riscv_elf_rtype_to_howto (unsigned int r_type) -+{ -+ BFD_ASSERT (r_type < (unsigned int) R_RISCV_max); -+ return &howto_table[r_type]; -+} -+ -+void -+riscv_elf_info_to_howto_rela (bfd *abfd, arelent *cache_ptr, -+ Elf_Internal_Rela *dst ATTRIBUTE_UNUSED) -+{ -+ unsigned int r_type; -+ -+ r_type = ELF_R_TYPE (abfd, dst->r_info); -+ cache_ptr->howto = riscv_elf_rtype_to_howto (r_type); -+ cache_ptr->addend = dst->r_addend; -+} -+ -+#define sec_addr(sec) ((sec)->output_section->vma + (sec)->output_offset) -+ -+static bfd_vma -+riscv_elf_got_plt_val (bfd_vma plt_index, struct bfd_link_info *info) -+{ -+ struct mips_elf_link_hash_table *htab = mips_elf_hash_table (info); -+ return sec_addr(htab->sgotplt) -+ + (2+plt_index) * MIPS_ELF_GOT_SIZE (elf_hash_table (info)->dynobj); -+} -+ -+#define PLT_HEADER_INSNS 8 -+#define PLT_ENTRY_INSNS 4 -+#define PLT_HEADER_SIZE (PLT_HEADER_INSNS * 4) -+#define PLT_ENTRY_SIZE (PLT_ENTRY_INSNS * 4) -+ -+#define X_V0 16 -+#define X_V1 17 -+#define X_T0 26 -+#define X_T1 27 -+#define X_T2 28 -+ -+/* The format of the first PLT entry. */ -+ -+static void -+riscv_make_plt0_entry(bfd* abfd, bfd_vma gotplt_addr, bfd_vma addr, -+ uint32_t entry[PLT_HEADER_INSNS]) -+{ -+ int regbytes = ABI_64_P(abfd) ? 8 : 4; -+ -+ /* auipc t2, %hi(.got.plt) -+ sub v0, v0, v1 # shifted .got.plt offset + hdr size + 12 -+ l[w|d] v1, %lo(.got.plt)(t2) # _dl_runtime_resolve -+ addi v0, v0, -(hdr size + 12) # shifted .got.plt offset -+ addi t0, t2, %lo(.got.plt) # &.got.plt -+ srli t1, v0, log2(16/PTRSIZE) # .got.plt offset -+ l[w|d] t0, PTRSIZE(t0) # link map -+ jr v1 */ -+ -+ entry[0] = RISCV_UTYPE(AUIPC, X_T2, RISCV_PCREL_HIGH_PART(gotplt_addr, addr)); -+ entry[1] = RISCV_RTYPE(SUB, X_V0, X_V0, X_V1); -+ entry[2] = RISCV_ITYPE(LREG(abfd), X_V1, X_T2, RISCV_PCREL_LOW_PART(gotplt_addr, addr)); -+ entry[3] = RISCV_ITYPE(ADDI, X_V0, X_V0, -(PLT_HEADER_SIZE + 12)); -+ entry[4] = RISCV_ITYPE(ADDI, X_T0, X_T2, RISCV_PCREL_LOW_PART(gotplt_addr, addr)); -+ entry[5] = RISCV_ITYPE(SRLI, X_T1, X_V0, regbytes == 4 ? 2 : 1); -+ entry[6] = RISCV_ITYPE(LREG(abfd), X_T0, X_T0, regbytes); -+ entry[7] = RISCV_ITYPE(JALR, 0, X_V1, 0); -+} -+ -+/* The format of subsequent PLT entries. */ -+ -+static bfd_vma -+riscv_make_plt_entry(bfd* abfd, bfd_vma got_address, bfd_vma plt0_addr, -+ bfd_vma addr, uint32_t *entry) -+{ -+ /* auipc v0, %hi(.got.plt entry) -+ l[w|d] v1, %lo(.got.plt entry)(v0) -+ jalr v0, v1 -+ nop */ -+ -+ entry[0] = RISCV_UTYPE(AUIPC, X_V0, RISCV_PCREL_HIGH_PART(got_address, addr)); -+ entry[1] = RISCV_ITYPE(LREG(abfd), X_V1, X_V0, RISCV_PCREL_LOW_PART(got_address, addr)); -+ entry[2] = RISCV_ITYPE(JALR, X_V0, X_V1, 0); -+ entry[3] = RISCV_NOP; -+ return plt0_addr; -+} -+ -+/* Look up an entry in a MIPS ELF linker hash table. */ -+ -+#define mips_elf_link_hash_lookup(table, string, create, copy, follow) \ -+ ((struct mips_elf_link_hash_entry *) \ -+ elf_link_hash_lookup (&(table)->root, (string), (create), \ -+ (copy), (follow))) -+ -+/* Traverse a MIPS ELF linker hash table. */ -+ -+#define mips_elf_link_hash_traverse(table, func, info) \ -+ (elf_link_hash_traverse \ -+ (&(table)->root, \ -+ (bfd_boolean (*) (struct elf_link_hash_entry *, void *)) (func), \ -+ (info))) -+ -+/* Find the base offsets for thread-local storage in this object, -+ for GD/LD and IE/LE respectively. */ -+ -+#define TP_OFFSET 0 -+#define DTP_OFFSET 0x800 -+ -+static bfd_vma -+dtprel_base (struct bfd_link_info *info) -+{ -+ /* If tls_sec is NULL, we should have signalled an error already. */ -+ if (elf_hash_table (info)->tls_sec == NULL) -+ return 0; -+ return elf_hash_table (info)->tls_sec->vma + DTP_OFFSET; -+} -+ -+static bfd_vma -+tprel_base (struct bfd_link_info *info) -+{ -+ /* If tls_sec is NULL, we should have signalled an error already. */ -+ if (elf_hash_table (info)->tls_sec == NULL) -+ return 0; -+ return elf_hash_table (info)->tls_sec->vma + TP_OFFSET; -+} -+ -+/* Create an entry in a MIPS ELF linker hash table. */ -+ -+static struct bfd_hash_entry * -+mips_elf_link_hash_newfunc (struct bfd_hash_entry *entry, -+ struct bfd_hash_table *table, const char *string) -+{ -+ struct mips_elf_link_hash_entry *ret = -+ (struct mips_elf_link_hash_entry *) entry; -+ -+ /* Allocate the structure if it has not already been allocated by a -+ subclass. */ -+ if (ret == NULL) -+ ret = bfd_hash_allocate (table, sizeof (struct mips_elf_link_hash_entry)); -+ if (ret == NULL) -+ return (struct bfd_hash_entry *) ret; -+ -+ /* Call the allocation method of the superclass. */ -+ ret = ((struct mips_elf_link_hash_entry *) -+ _bfd_elf_link_hash_newfunc ((struct bfd_hash_entry *) ret, -+ table, string)); -+ if (ret != NULL) -+ { -+ ret->possibly_dynamic_relocs = 0; -+ ret->tls_type = GOT_NORMAL; -+ ret->global_got_area = GGA_NONE; -+ ret->readonly_reloc = FALSE; -+ ret->has_static_relocs = FALSE; -+ } -+ -+ return (struct bfd_hash_entry *) ret; -+} -+ -+bfd_boolean -+_bfd_riscv_elf_new_section_hook (bfd *abfd, asection *sec) -+{ -+ if (!sec->used_by_bfd) -+ { -+ struct _mips_elf_section_data *sdata; -+ bfd_size_type amt = sizeof (*sdata); -+ -+ sdata = bfd_zalloc (abfd, amt); -+ if (sdata == NULL) -+ return FALSE; -+ sec->used_by_bfd = sdata; -+ } -+ -+ return _bfd_elf_new_section_hook (abfd, sec); -+} -+ -+/* A generic howto special_function. This calculates and installs the -+ relocation itself, thus avoiding the oft-discussed problems in -+ bfd_perform_relocation and bfd_install_relocation. */ -+ -+bfd_reloc_status_type -+_bfd_riscv_elf_generic_reloc (bfd *abfd ATTRIBUTE_UNUSED, arelent *reloc_entry, -+ asymbol *symbol, void *data ATTRIBUTE_UNUSED, -+ asection *input_section, bfd *output_bfd, -+ char **error_message ATTRIBUTE_UNUSED) -+{ -+ bfd_signed_vma val; -+ bfd_reloc_status_type status; -+ bfd_boolean relocatable; -+ -+ relocatable = (output_bfd != NULL); -+ -+ if (reloc_entry->address > bfd_get_section_limit (abfd, input_section)) -+ return bfd_reloc_outofrange; -+ -+ /* Build up the field adjustment in VAL. */ -+ val = 0; -+ if (!relocatable || (symbol->flags & BSF_SECTION_SYM) != 0) -+ /* Either we're calculating the final field value or we have a -+ relocation against a section symbol. Add in the section's -+ offset or address. */ -+ val += sec_addr(symbol->section); -+ -+ if (!relocatable) -+ { -+ /* We're calculating the final field value. Add in the symbol's value -+ and, if pc-relative, subtract the address of the field itself. */ -+ val += symbol->value; -+ if (reloc_entry->howto->pc_relative) -+ { -+ val -= sec_addr(input_section); -+ val -= reloc_entry->address; -+ } -+ } -+ -+ /* VAL is now the final adjustment. If we're keeping this relocation -+ in the output file, and if the relocation uses a separate addend, -+ we just need to add VAL to that addend. Otherwise we need to add -+ VAL to the relocation field itself. */ -+ if (relocatable && !reloc_entry->howto->partial_inplace) -+ reloc_entry->addend += val; -+ else -+ { -+ bfd_byte *loc = (bfd_byte *) data + reloc_entry->address; -+ struct reloc_howto_struct howto = *reloc_entry->howto; -+ -+ /* Add in the separate addend, if any. */ -+ val += reloc_entry->addend; -+ -+ /* Add VAL to the reloc field. */ -+ status = _bfd_relocate_contents (&howto, abfd, val, loc); -+ -+ if (status != bfd_reloc_ok) -+ return status; -+ } -+ -+ if (relocatable) -+ reloc_entry->address += input_section->output_offset; -+ -+ return bfd_reloc_ok; -+} -+ -+/* This function is called via qsort() to sort the dynamic relocation -+ entries by increasing r_symndx value. */ -+ -+static int -+sort_dynamic_relocs (const void *arg1, const void *arg2) -+{ -+ Elf_Internal_Rela int_reloc1; -+ Elf_Internal_Rela int_reloc2; -+ int diff; -+ -+ bfd_elf32_swap_reloc_in (reldyn_sorting_bfd, arg1, &int_reloc1); -+ bfd_elf32_swap_reloc_in (reldyn_sorting_bfd, arg2, &int_reloc2); -+ -+ diff = ELF32_R_SYM (int_reloc1.r_info) - ELF32_R_SYM (int_reloc2.r_info); -+ if (diff != 0) -+ return diff; -+ -+ if (int_reloc1.r_offset < int_reloc2.r_offset) -+ return -1; -+ if (int_reloc1.r_offset > int_reloc2.r_offset) -+ return 1; -+ return 0; -+} -+ -+/* Like sort_dynamic_relocs, but used for elf64 relocations. */ -+ -+static int -+sort_dynamic_relocs_64 (const void *arg1 ATTRIBUTE_UNUSED, -+ const void *arg2 ATTRIBUTE_UNUSED) -+{ -+#ifdef BFD64 -+ Elf_Internal_Rela int_reloc1; -+ Elf_Internal_Rela int_reloc2; -+ -+ (*get_elf_backend_data (reldyn_sorting_bfd)->s->swap_reloc_in) -+ (reldyn_sorting_bfd, arg1, &int_reloc1); -+ (*get_elf_backend_data (reldyn_sorting_bfd)->s->swap_reloc_in) -+ (reldyn_sorting_bfd, arg2, &int_reloc2); -+ -+ if (ELF64_R_SYM (int_reloc1.r_info) < ELF64_R_SYM (int_reloc2.r_info)) -+ return -1; -+ if (ELF64_R_SYM (int_reloc1.r_info) > ELF64_R_SYM (int_reloc2.r_info)) -+ return 1; -+ -+ if (int_reloc1.r_offset < int_reloc2.r_offset) -+ return -1; -+ if (int_reloc1.r_offset > int_reloc2.r_offset) -+ return 1; -+ return 0; -+#else -+ abort (); -+#endif -+} -+ -+/* Functions to manage the got entry hash table. */ -+ -+/* Use all 64 bits of a bfd_vma for the computation of a 32-bit -+ hash number. */ -+ -+static INLINE hashval_t -+mips_elf_hash_bfd_vma (bfd_vma addr) -+{ -+#ifdef BFD64 -+ return addr + (addr >> 32); -+#else -+ return addr; -+#endif -+} -+ -+/* got_entries only match if they're identical, except for gotidx, so -+ use all fields to compute the hash, and compare the appropriate -+ union members. */ -+ -+static hashval_t -+mips_elf_got_entry_hash (const void *entry_) -+{ -+ const struct mips_got_entry *entry = (struct mips_got_entry *)entry_; -+ -+ return entry->symndx -+ + (! entry->abfd ? mips_elf_hash_bfd_vma (entry->d.address) -+ : entry->abfd->id -+ + (entry->symndx >= 0 ? mips_elf_hash_bfd_vma (entry->d.addend) -+ : entry->d.h->root.root.root.hash)); -+} -+ -+static int -+mips_elf_got_entry_eq (const void *entry1, const void *entry2) -+{ -+ const struct mips_got_entry *e1 = (struct mips_got_entry *)entry1; -+ const struct mips_got_entry *e2 = (struct mips_got_entry *)entry2; -+ -+ return e1->abfd == e2->abfd && e1->symndx == e2->symndx -+ && (! e1->abfd ? e1->d.address == e2->d.address -+ : e1->symndx >= 0 ? e1->d.addend == e2->d.addend -+ : e1->d.h == e2->d.h); -+} -+ -+/* Return the dynamic relocation section. If it doesn't exist, try to -+ create a new it if CREATE_P, otherwise return NULL. Also return NULL -+ if creation fails. */ -+ -+static asection * -+mips_elf_rel_dyn_section (struct bfd_link_info *info, bfd_boolean create_p) -+{ -+ const char *dname; -+ asection *sreloc; -+ bfd *dynobj; -+ -+ dname = MIPS_ELF_REL_DYN_NAME (info); -+ dynobj = elf_hash_table (info)->dynobj; -+ sreloc = bfd_get_section_by_name (dynobj, dname); -+ if (sreloc == NULL && create_p) -+ { -+ sreloc = bfd_make_section_with_flags (dynobj, dname, -+ (SEC_ALLOC -+ | SEC_LOAD -+ | SEC_HAS_CONTENTS -+ | SEC_IN_MEMORY -+ | SEC_LINKER_CREATED -+ | SEC_READONLY)); -+ if (sreloc == NULL -+ || ! bfd_set_section_alignment (dynobj, sreloc, -+ MIPS_ELF_LOG_FILE_ALIGN (dynobj))) -+ return NULL; -+ } -+ return sreloc; -+} -+ -+/* Count the number of relocations needed for a TLS GOT entry, with -+ access types from TLS_TYPE, and symbol H (or a local symbol if H -+ is NULL). */ -+ -+static int -+mips_tls_got_relocs (struct bfd_link_info *info, unsigned char tls_type, -+ struct elf_link_hash_entry *h) -+{ -+ int indx = 0; -+ int ret = 0; -+ bfd_boolean need_relocs = FALSE; -+ bfd_boolean dyn = elf_hash_table (info)->dynamic_sections_created; -+ -+ if (h && WILL_CALL_FINISH_DYNAMIC_SYMBOL (dyn, info->shared, h) -+ && (!info->shared || !SYMBOL_REFERENCES_LOCAL (info, h))) -+ indx = h->dynindx; -+ -+ if ((info->shared || indx != 0) -+ && (h == NULL -+ || ELF_ST_VISIBILITY (h->other) == STV_DEFAULT -+ || h->root.type != bfd_link_hash_undefweak)) -+ need_relocs = TRUE; -+ -+ if (!need_relocs) -+ return FALSE; -+ -+ if (tls_type & GOT_TLS_GD) -+ { -+ ret++; -+ if (indx != 0) -+ ret++; -+ } -+ -+ if (tls_type & GOT_TLS_IE) -+ ret++; -+ -+ return ret; -+} -+ -+/* Count the number of TLS relocations required for the GOT entry in -+ ARG1, if it describes a local symbol. */ -+ -+static int -+mips_elf_count_local_tls_relocs (void **arg1, void *arg2) -+{ -+ struct mips_got_entry *entry = * (struct mips_got_entry **) arg1; -+ struct mips_elf_count_tls_arg *arg = arg2; -+ -+ if (entry->abfd != NULL && entry->symndx != -1) -+ arg->needed += mips_tls_got_relocs (arg->info, entry->tls_type, NULL); -+ -+ return 1; -+} -+ -+/* Count the number of TLS GOT entries required for the global (or -+ forced-local) symbol in ARG1. */ -+ -+static int -+mips_elf_count_global_tls_entries (void *arg1, void *arg2) -+{ -+ struct mips_elf_link_hash_entry *hm -+ = (struct mips_elf_link_hash_entry *) arg1; -+ struct mips_elf_count_tls_arg *arg = arg2; -+ -+ if (hm->tls_type & GOT_TLS_GD) -+ arg->needed += 2; -+ if (hm->tls_type & GOT_TLS_IE) -+ arg->needed += 1; -+ -+ return 1; -+} -+ -+/* Count the number of TLS relocations required for the global (or -+ forced-local) symbol in ARG1. */ -+ -+static int -+mips_elf_count_global_tls_relocs (void *arg1, void *arg2) -+{ -+ struct mips_elf_link_hash_entry *hm -+ = (struct mips_elf_link_hash_entry *) arg1; -+ struct mips_elf_count_tls_arg *arg = arg2; -+ -+ arg->needed += mips_tls_got_relocs (arg->info, hm->tls_type, &hm->root); -+ -+ return 1; -+} -+ -+/* Output a simple dynamic relocation into SRELOC. */ -+ -+static void -+mips_elf_output_dynamic_relocation (bfd *output_bfd, -+ asection *sreloc, -+ unsigned long reloc_index, -+ unsigned long indx, -+ int r_type, -+ bfd_vma offset) -+{ -+ Elf_Internal_Rela rel; -+ -+ memset (&rel, 0, sizeof (rel)); -+ -+ rel.r_info = ELF_R_INFO (output_bfd, indx, r_type); -+ rel.r_offset = offset; -+ -+ if (ABI_64_P (output_bfd)) -+ bfd_elf64_swap_reloc_out -+ (output_bfd, &rel, -+ (sreloc->contents + reloc_index * sizeof (Elf64_External_Rel))); -+ else -+ bfd_elf32_swap_reloc_out -+ (output_bfd, &rel, -+ (sreloc->contents + reloc_index * sizeof (Elf32_External_Rel))); -+} -+ -+/* Initialize a set of TLS GOT entries for one symbol. */ -+ -+static void -+mips_elf_initialize_tls_slots (bfd *abfd, bfd_vma got_offset, -+ unsigned char *tls_type_p, -+ struct bfd_link_info *info, -+ struct mips_elf_link_hash_entry *h, -+ bfd_vma value) -+{ -+ struct mips_elf_link_hash_table *htab; -+ int indx; -+ asection *sreloc, *sgot; -+ bfd_vma offset, offset2; -+ bfd_boolean need_relocs = FALSE; -+ -+ htab = mips_elf_hash_table (info); -+ if (htab == NULL) -+ return; -+ -+ sgot = htab->sgot; -+ -+ indx = 0; -+ if (h != NULL) -+ { -+ bfd_boolean dyn = elf_hash_table (info)->dynamic_sections_created; -+ -+ if (WILL_CALL_FINISH_DYNAMIC_SYMBOL (dyn, info->shared, &h->root) -+ && (!info->shared || !SYMBOL_REFERENCES_LOCAL (info, &h->root))) -+ indx = h->root.dynindx; -+ } -+ -+ if (*tls_type_p & GOT_TLS_DONE) -+ return; -+ -+ if ((info->shared || indx != 0) -+ && (h == NULL -+ || ELF_ST_VISIBILITY (h->root.other) == STV_DEFAULT -+ || h->root.type != bfd_link_hash_undefweak)) -+ need_relocs = TRUE; -+ -+ /* MINUS_ONE means the symbol is not defined in this object. It may not -+ be defined at all; assume that the value doesn't matter in that -+ case. Otherwise complain if we would use the value. */ -+ BFD_ASSERT (value != MINUS_ONE || (indx != 0 && need_relocs) -+ || h->root.root.type == bfd_link_hash_undefweak); -+ -+ /* Emit necessary relocations. */ -+ sreloc = mips_elf_rel_dyn_section (info, FALSE); -+ -+ /* General Dynamic. */ -+ if (*tls_type_p & GOT_TLS_GD) -+ { -+ offset = got_offset; -+ offset2 = offset + MIPS_ELF_GOT_SIZE (abfd); -+ -+ if (need_relocs) -+ { -+ mips_elf_output_dynamic_relocation -+ (abfd, sreloc, sreloc->reloc_count++, indx, -+ ABI_64_P (abfd) ? R_RISCV_TLS_DTPMOD64 : R_RISCV_TLS_DTPMOD32, -+ sec_addr(sgot) + offset); -+ -+ if (indx) -+ mips_elf_output_dynamic_relocation -+ (abfd, sreloc, sreloc->reloc_count++, indx, -+ ABI_64_P (abfd) ? R_RISCV_TLS_DTPREL64 : R_RISCV_TLS_DTPREL32, -+ sec_addr(sgot) + offset2); -+ else -+ MIPS_ELF_PUT_WORD (abfd, value - dtprel_base (info), -+ sgot->contents + offset2); -+ } -+ else -+ { -+ MIPS_ELF_PUT_WORD (abfd, 1, -+ sgot->contents + offset); -+ MIPS_ELF_PUT_WORD (abfd, value - dtprel_base (info), -+ sgot->contents + offset2); -+ } -+ -+ got_offset += 2 * MIPS_ELF_GOT_SIZE (abfd); -+ } -+ -+ /* Initial Exec model. */ -+ if (*tls_type_p & GOT_TLS_IE) -+ { -+ offset = got_offset; -+ -+ if (need_relocs) -+ { -+ if (indx == 0) -+ MIPS_ELF_PUT_WORD (abfd, value - elf_hash_table (info)->tls_sec->vma, -+ sgot->contents + offset); -+ else -+ MIPS_ELF_PUT_WORD (abfd, 0, -+ sgot->contents + offset); -+ -+ mips_elf_output_dynamic_relocation -+ (abfd, sreloc, sreloc->reloc_count++, indx, -+ ABI_64_P (abfd) ? R_RISCV_TLS_TPREL64 : R_RISCV_TLS_TPREL32, -+ sec_addr(sgot) + offset); -+ } -+ else -+ MIPS_ELF_PUT_WORD (abfd, value - tprel_base (info), -+ sgot->contents + offset); -+ } -+ -+ *tls_type_p |= GOT_TLS_DONE; -+} -+ -+/* Return the GOT index to use for a relocation of type R_TYPE against -+ a symbol accessed using TLS_TYPE models. The GOT entries for this -+ symbol in this GOT start at GOT_INDEX. This function initializes the -+ GOT entries and corresponding relocations. */ -+ -+static bfd_vma -+mips_tls_got_index (bfd *abfd, bfd_vma got_index, unsigned char *tls_type, -+ int r_type, struct bfd_link_info *info, -+ struct mips_elf_link_hash_entry *h, bfd_vma symbol) -+{ -+ BFD_ASSERT (TLS_GOTTPREL_RELOC_P(r_type) || TLS_GD_RELOC_P(r_type)); -+ -+ mips_elf_initialize_tls_slots (abfd, got_index, tls_type, info, h, symbol); -+ -+ if (TLS_GOTTPREL_RELOC_P(r_type)) -+ { -+ BFD_ASSERT (*tls_type & GOT_TLS_IE); -+ if (*tls_type & GOT_TLS_GD) -+ return got_index + 2 * MIPS_ELF_GOT_SIZE (abfd); -+ else -+ return got_index; -+ } -+ -+ BFD_ASSERT (*tls_type & GOT_TLS_GD); -+ return got_index; -+} -+ -+/* Return the GOT offset for address VALUE. If there is not yet a GOT -+ entry for this value, create one. If R_SYMNDX refers to a TLS symbol, -+ create a TLS GOT entry instead. Return -1 if no satisfactory GOT -+ offset can be found. */ -+ -+static bfd_vma -+mips_elf_local_got_index (bfd *abfd, bfd *ibfd, struct bfd_link_info *info, -+ bfd_vma value, unsigned long r_symndx, -+ struct mips_elf_link_hash_entry *h, int r_type) -+{ -+ struct mips_elf_link_hash_table *htab; -+ struct mips_got_entry *entry; -+ -+ htab = mips_elf_hash_table (info); -+ BFD_ASSERT (htab != NULL); -+ -+ entry = mips_elf_create_local_got_entry (abfd, info, ibfd, value, -+ r_symndx, h, r_type); -+ if (!entry) -+ return MINUS_ONE; -+ -+ if (TLS_RELOC_P (r_type)) -+ { -+ if (entry->symndx == -1) -+ /* A type (3) entry in the single-GOT case. We use the symbol's -+ hash table entry to track the index. */ -+ return mips_tls_got_index (abfd, h->tls_got_offset, &h->tls_type, -+ r_type, info, h, value); -+ else -+ return mips_tls_got_index (abfd, entry->gotidx, &entry->tls_type, -+ r_type, info, h, value); -+ } -+ else -+ return entry->gotidx; -+} -+ -+/* Returns the GOT index for the global symbol indicated by H. */ -+ -+static bfd_vma -+mips_elf_global_got_index (bfd *abfd, struct elf_link_hash_entry *h, -+ int r_type, struct bfd_link_info *info) -+{ -+ struct mips_elf_link_hash_table *htab; -+ bfd_vma got_index; -+ struct mips_got_info *g; -+ long global_got_dynindx = 0; -+ -+ htab = mips_elf_hash_table (info); -+ BFD_ASSERT (htab != NULL); -+ -+ g = htab->got_info; -+ -+ if (g->global_gotsym != NULL) -+ global_got_dynindx = g->global_gotsym->dynindx; -+ -+ if (TLS_RELOC_P (r_type)) -+ { -+ struct mips_elf_link_hash_entry *hm -+ = (struct mips_elf_link_hash_entry *) h; -+ bfd_vma value = MINUS_ONE; -+ -+ if ((h->root.type == bfd_link_hash_defined -+ || h->root.type == bfd_link_hash_defweak) -+ && h->root.u.def.section->output_section) -+ value = h->root.u.def.value + sec_addr(h->root.u.def.section); -+ -+ got_index = mips_tls_got_index (abfd, hm->tls_got_offset, &hm->tls_type, -+ r_type, info, hm, value); -+ } -+ else -+ { -+ /* Once we determine the global GOT entry with the lowest dynamic -+ symbol table index, we must put all dynamic symbols with greater -+ indices into the GOT. That makes it easy to calculate the GOT -+ offset. */ -+ BFD_ASSERT (h->dynindx >= global_got_dynindx); -+ got_index = ((h->dynindx - global_got_dynindx + g->local_gotno) -+ * MIPS_ELF_GOT_SIZE (abfd)); -+ } -+ BFD_ASSERT (got_index < htab->sgot->size); -+ -+ return got_index; -+} -+ -+/* Create and return a local GOT entry for VALUE, which was calculated -+ from a symbol belonging to INPUT_SECTON. Return NULL if it could not -+ be created. If R_SYMNDX refers to a TLS symbol, create a TLS entry -+ instead. */ -+ -+static struct mips_got_entry * -+mips_elf_create_local_got_entry (bfd *abfd, struct bfd_link_info *info, -+ bfd *ibfd, bfd_vma value, -+ unsigned long r_symndx, -+ struct mips_elf_link_hash_entry *h, -+ int r_type) -+{ -+ struct mips_got_entry entry, **loc; -+ struct mips_got_info *g; -+ struct mips_elf_link_hash_table *htab; -+ -+ htab = mips_elf_hash_table (info); -+ BFD_ASSERT (htab != NULL); -+ -+ entry.abfd = NULL; -+ entry.symndx = -1; -+ entry.d.address = value; -+ entry.tls_type = 0; -+ -+ g = htab->got_info; -+ -+ /* This function shouldn't be called for symbols that live in the global -+ area of the GOT. */ -+ BFD_ASSERT (h == NULL || h->global_got_area == GGA_NONE); -+ if (TLS_RELOC_P (r_type)) -+ { -+ struct mips_got_entry *p; -+ -+ entry.abfd = ibfd; -+ if (h == NULL) -+ { -+ entry.symndx = r_symndx; -+ entry.d.addend = 0; -+ } -+ else -+ entry.d.h = h; -+ -+ p = (struct mips_got_entry *) -+ htab_find (g->got_entries, &entry); -+ -+ BFD_ASSERT (p); -+ return p; -+ } -+ -+ loc = (struct mips_got_entry **) htab_find_slot (g->got_entries, &entry, -+ INSERT); -+ if (*loc) -+ return *loc; -+ -+ entry.gotidx = MIPS_ELF_GOT_SIZE (abfd) * g->assigned_gotno++; -+ entry.tls_type = 0; -+ -+ *loc = (struct mips_got_entry *)bfd_alloc (abfd, sizeof entry); -+ -+ if (! *loc) -+ return NULL; -+ -+ memcpy (*loc, &entry, sizeof entry); -+ -+ if (g->assigned_gotno > g->local_gotno) -+ { -+ (*loc)->gotidx = -1; -+ /* We didn't allocate enough space in the GOT. */ -+ (*_bfd_error_handler) -+ (_("not enough GOT space for local GOT entries")); -+ bfd_set_error (bfd_error_bad_value); -+ return NULL; -+ } -+ -+ MIPS_ELF_PUT_WORD (abfd, value, -+ (htab->sgot->contents + entry.gotidx)); -+ -+ return *loc; -+} -+ -+/* Return the number of dynamic section symbols required by OUTPUT_BFD. -+ The number might be exact or a worst-case estimate, depending on how -+ much information is available to elf_backend_omit_section_dynsym at -+ the current linking stage. */ -+ -+static bfd_size_type -+count_section_dynsyms (bfd *output_bfd, struct bfd_link_info *info) -+{ -+ bfd_size_type count; -+ -+ count = 0; -+ if (info->shared || elf_hash_table (info)->is_relocatable_executable) -+ { -+ asection *p; -+ const struct elf_backend_data *bed; -+ -+ bed = get_elf_backend_data (output_bfd); -+ for (p = output_bfd->sections; p ; p = p->next) -+ if ((p->flags & SEC_EXCLUDE) == 0 -+ && (p->flags & SEC_ALLOC) != 0 -+ && !(*bed->elf_backend_omit_section_dynsym) (output_bfd, info, p)) -+ ++count; -+ } -+ return count; -+} -+ -+/* Sort the dynamic symbol table so that symbols that need GOT entries -+ appear towards the end. */ -+ -+static bfd_boolean -+mips_elf_sort_hash_table (bfd *abfd, struct bfd_link_info *info) -+{ -+ struct mips_elf_link_hash_table *htab; -+ struct mips_elf_hash_sort_data hsd; -+ struct mips_got_info *g; -+ -+ if (elf_hash_table (info)->dynsymcount == 0) -+ return TRUE; -+ -+ htab = mips_elf_hash_table (info); -+ BFD_ASSERT (htab != NULL); -+ -+ g = htab->got_info; -+ if (g == NULL) -+ return TRUE; -+ -+ hsd.low = NULL; -+ hsd.max_unref_got_dynindx -+ = hsd.min_got_dynindx -+ = (elf_hash_table (info)->dynsymcount - g->reloc_only_gotno); -+ hsd.max_non_got_dynindx = count_section_dynsyms (abfd, info) + 1; -+ mips_elf_link_hash_traverse (((struct mips_elf_link_hash_table *) -+ elf_hash_table (info)), -+ mips_elf_sort_hash_table_f, -+ &hsd); -+ -+ /* There should have been enough room in the symbol table to -+ accommodate both the GOT and non-GOT symbols. */ -+ BFD_ASSERT (hsd.max_non_got_dynindx <= hsd.min_got_dynindx); -+ BFD_ASSERT ((unsigned long) hsd.max_unref_got_dynindx -+ == elf_hash_table (info)->dynsymcount); -+ BFD_ASSERT (elf_hash_table (info)->dynsymcount - hsd.min_got_dynindx -+ == g->global_gotno); -+ -+ /* Now we know which dynamic symbol has the lowest dynamic symbol -+ table index in the GOT. */ -+ g->global_gotsym = hsd.low; -+ -+ return TRUE; -+} -+ -+/* If H needs a GOT entry, assign it the highest available dynamic -+ index. Otherwise, assign it the lowest available dynamic -+ index. */ -+ -+static bfd_boolean -+mips_elf_sort_hash_table_f (struct mips_elf_link_hash_entry *h, void *data) -+{ -+ struct mips_elf_hash_sort_data *hsd = data; -+ -+ if (h->root.root.type == bfd_link_hash_warning) -+ h = (struct mips_elf_link_hash_entry *) h->root.root.u.i.link; -+ -+ /* Symbols without dynamic symbol table entries aren't interesting -+ at all. */ -+ if (h->root.dynindx == -1) -+ return TRUE; -+ -+ switch (h->global_got_area) -+ { -+ case GGA_NONE: -+ h->root.dynindx = hsd->max_non_got_dynindx++; -+ break; -+ -+ case GGA_NORMAL: -+ BFD_ASSERT (h->tls_type == GOT_NORMAL); -+ -+ h->root.dynindx = --hsd->min_got_dynindx; -+ hsd->low = (struct elf_link_hash_entry *) h; -+ break; -+ -+ case GGA_RELOC_ONLY: -+ BFD_ASSERT (h->tls_type == GOT_NORMAL); -+ -+ if (hsd->max_unref_got_dynindx == hsd->min_got_dynindx) -+ hsd->low = (struct elf_link_hash_entry *) h; -+ h->root.dynindx = hsd->max_unref_got_dynindx++; -+ break; -+ } -+ -+ return TRUE; -+} -+ -+/* If H is a symbol that needs a global GOT entry, but has a dynamic -+ symbol table index lower than any we've seen to date, record it for -+ posterity. FOR_CALL is true if the caller is only interested in -+ using the GOT entry for calls. */ -+ -+static bfd_boolean -+mips_elf_record_global_got_symbol (struct elf_link_hash_entry *h, -+ bfd *abfd, struct bfd_link_info *info, -+ unsigned char tls_flag) -+{ -+ struct mips_elf_link_hash_table *htab; -+ struct mips_elf_link_hash_entry *hmips; -+ struct mips_got_entry entry, **loc; -+ struct mips_got_info *g; -+ -+ htab = mips_elf_hash_table (info); -+ BFD_ASSERT (htab != NULL); -+ -+ hmips = (struct mips_elf_link_hash_entry *) h; -+ -+ /* A global symbol in the GOT must also be in the dynamic symbol -+ table. */ -+ if (h->dynindx == -1) -+ { -+ switch (ELF_ST_VISIBILITY (h->other)) -+ { -+ case STV_INTERNAL: -+ case STV_HIDDEN: -+ _bfd_elf_link_hash_hide_symbol (info, h, TRUE); -+ break; -+ } -+ if (!bfd_elf_link_record_dynamic_symbol (info, h)) -+ return FALSE; -+ } -+ -+ /* Make sure we have a GOT to put this entry into. */ -+ g = htab->got_info; -+ BFD_ASSERT (g != NULL); -+ -+ entry.abfd = abfd; -+ entry.symndx = -1; -+ entry.d.h = (struct mips_elf_link_hash_entry *) h; -+ entry.tls_type = 0; -+ -+ loc = (struct mips_got_entry **) htab_find_slot (g->got_entries, &entry, -+ INSERT); -+ -+ /* If we've already marked this entry as needing GOT space, we don't -+ need to do it again. */ -+ if (*loc) -+ { -+ (*loc)->tls_type |= tls_flag; -+ return TRUE; -+ } -+ -+ *loc = (struct mips_got_entry *)bfd_alloc (abfd, sizeof entry); -+ -+ if (! *loc) -+ return FALSE; -+ -+ entry.gotidx = -1; -+ entry.tls_type = tls_flag; -+ -+ memcpy (*loc, &entry, sizeof entry); -+ -+ if (tls_flag == 0) -+ hmips->global_got_area = GGA_NORMAL; -+ -+ return TRUE; -+} -+ -+/* Reserve space in G for a GOT entry containing the value of symbol -+ SYMNDX in input bfd ABDF, plus ADDEND. */ -+ -+static bfd_boolean -+mips_elf_record_local_got_symbol (bfd *abfd, long symndx, bfd_vma addend, -+ struct bfd_link_info *info, -+ unsigned char tls_flag) -+{ -+ struct mips_elf_link_hash_table *htab; -+ struct mips_got_info *g; -+ struct mips_got_entry entry, **loc; -+ -+ htab = mips_elf_hash_table (info); -+ BFD_ASSERT (htab != NULL); -+ -+ g = htab->got_info; -+ BFD_ASSERT (g != NULL); -+ -+ entry.abfd = abfd; -+ entry.symndx = symndx; -+ entry.d.addend = addend; -+ entry.tls_type = tls_flag; -+ loc = (struct mips_got_entry **) -+ htab_find_slot (g->got_entries, &entry, INSERT); -+ -+ if (*loc) -+ { -+ if (tls_flag == GOT_TLS_GD && !((*loc)->tls_type & GOT_TLS_GD)) -+ { -+ g->tls_gotno += 2; -+ (*loc)->tls_type |= tls_flag; -+ } -+ else if (tls_flag == GOT_TLS_IE && !((*loc)->tls_type & GOT_TLS_IE)) -+ { -+ g->tls_gotno += 1; -+ (*loc)->tls_type |= tls_flag; -+ } -+ return TRUE; -+ } -+ -+ if (tls_flag != 0) -+ { -+ entry.gotidx = -1; -+ entry.tls_type = tls_flag; -+ BFD_ASSERT (tls_flag & (GOT_TLS_IE | GOT_TLS_GD)); -+ if (tls_flag == GOT_TLS_IE) -+ g->tls_gotno += 1; -+ else -+ g->tls_gotno += 2; -+ } -+ else -+ { -+ entry.gotidx = g->local_gotno++; -+ entry.tls_type = 0; -+ } -+ -+ *loc = (struct mips_got_entry *)bfd_alloc (abfd, sizeof entry); -+ -+ if (! *loc) -+ return FALSE; -+ -+ memcpy (*loc, &entry, sizeof entry); -+ -+ return TRUE; -+} -+ -+/* Add room for N relocations to the .rel(a).dyn section in ABFD. */ -+ -+static void -+mips_elf_allocate_dynamic_relocations (bfd *abfd, struct bfd_link_info *info, -+ unsigned int n) -+{ -+ asection *s; -+ struct mips_elf_link_hash_table *htab; -+ -+ htab = mips_elf_hash_table (info); -+ BFD_ASSERT (htab != NULL); -+ -+ s = mips_elf_rel_dyn_section (info, FALSE); -+ BFD_ASSERT (s != NULL); -+ -+ if (s->size == 0) -+ { -+ /* Make room for a null element. */ -+ s->size += MIPS_ELF_REL_SIZE (abfd); -+ ++s->reloc_count; -+ } -+ s->size += n * MIPS_ELF_REL_SIZE (abfd); -+} -+ -+/* A htab_traverse callback for GOT entries. Set boolean *DATA to true -+ if the GOT entry is for an indirect or warning symbol. */ -+ -+static int -+mips_elf_check_recreate_got (void **entryp, void *data) -+{ -+ struct mips_got_entry *entry; -+ bfd_boolean *must_recreate; -+ -+ entry = (struct mips_got_entry *) *entryp; -+ must_recreate = (bfd_boolean *) data; -+ if (entry->abfd != NULL && entry->symndx == -1) -+ { -+ struct mips_elf_link_hash_entry *h; -+ -+ h = entry->d.h; -+ if (h->root.root.type == bfd_link_hash_indirect -+ || h->root.root.type == bfd_link_hash_warning) -+ { -+ *must_recreate = TRUE; -+ return 0; -+ } -+ } -+ return 1; -+} -+ -+/* A htab_traverse callback for GOT entries. Add all entries to -+ hash table *DATA, converting entries for indirect and warning -+ symbols into entries for the target symbol. Set *DATA to null -+ on error. */ -+ -+static int -+mips_elf_recreate_got (void **entryp, void *data) -+{ -+ htab_t *new_got; -+ struct mips_got_entry *entry; -+ void **slot; -+ -+ new_got = (htab_t *) data; -+ entry = (struct mips_got_entry *) *entryp; -+ if (entry->abfd != NULL && entry->symndx == -1) -+ { -+ struct mips_elf_link_hash_entry *h; -+ -+ h = entry->d.h; -+ while (h->root.root.type == bfd_link_hash_indirect -+ || h->root.root.type == bfd_link_hash_warning) -+ { -+ BFD_ASSERT (h->global_got_area == GGA_NONE); -+ h = (struct mips_elf_link_hash_entry *) h->root.root.u.i.link; -+ } -+ entry->d.h = h; -+ } -+ slot = htab_find_slot (*new_got, entry, INSERT); -+ if (slot == NULL) -+ { -+ *new_got = NULL; -+ return 0; -+ } -+ if (*slot == NULL) -+ *slot = entry; -+ else -+ free (entry); -+ return 1; -+} -+ -+/* If any entries in G->got_entries are for indirect or warning symbols, -+ replace them with entries for the target symbol. */ -+ -+static bfd_boolean -+mips_elf_resolve_final_got_entries (struct mips_got_info *g) -+{ -+ bfd_boolean must_recreate; -+ htab_t new_got; -+ -+ must_recreate = FALSE; -+ htab_traverse (g->got_entries, mips_elf_check_recreate_got, &must_recreate); -+ if (must_recreate) -+ { -+ new_got = htab_create (htab_size (g->got_entries), -+ mips_elf_got_entry_hash, -+ mips_elf_got_entry_eq, NULL); -+ htab_traverse (g->got_entries, mips_elf_recreate_got, &new_got); -+ if (new_got == NULL) -+ return FALSE; -+ -+ /* Each entry in g->got_entries has either been copied to new_got -+ or freed. Now delete the hash table itself. */ -+ htab_delete (g->got_entries); -+ g->got_entries = new_got; -+ } -+ return TRUE; -+} -+ -+/* A mips_elf_link_hash_traverse callback for which DATA points -+ to the link_info structure. Count the number of type (3) entries -+ in the master GOT. */ -+ -+static int -+mips_elf_count_got_symbols (struct mips_elf_link_hash_entry *h, void *data) -+{ -+ struct bfd_link_info *info; -+ struct mips_elf_link_hash_table *htab; -+ struct mips_got_info *g; -+ -+ info = (struct bfd_link_info *) data; -+ htab = mips_elf_hash_table (info); -+ g = htab->got_info; -+ if (h->global_got_area != GGA_NONE) -+ { -+ /* Make a final decision about whether the symbol belongs in the -+ local or global GOT. Symbols that bind locally can (and in the -+ case of forced-local symbols, must) live in the local GOT. -+ Those that are aren't in the dynamic symbol table must also -+ live in the local GOT. -+ -+ Note that the former condition does not always imply the -+ latter: symbols do not bind locally if they are completely -+ undefined. We'll report undefined symbols later if appropriate. */ -+ if (h->root.dynindx == -1 || SYMBOL_REFERENCES_LOCAL (info, &h->root)) -+ { -+ /* The symbol belongs in the local GOT. We no longer need this -+ entry if it was only used for relocations; those relocations -+ will be against the null or section symbol instead of H. */ -+ if (h->global_got_area != GGA_RELOC_ONLY) -+ g->local_gotno++; -+ h->global_got_area = GGA_NONE; -+ } -+ else -+ { -+ g->global_gotno++; -+ if (h->global_got_area == GGA_RELOC_ONLY) -+ g->reloc_only_gotno++; -+ } -+ } -+ return 1; -+} -+ -+/* Set the TLS GOT index for the GOT entry in ENTRYP. ENTRYP's NEXT field -+ is null iff there is just a single GOT. */ -+ -+static int -+mips_elf_initialize_tls_index (void **entryp, void *p) -+{ -+ struct mips_got_entry *entry = (struct mips_got_entry *)*entryp; -+ struct mips_got_info *g = p; -+ bfd_vma next_index; -+ unsigned char tls_type; -+ -+ /* We're only interested in TLS symbols. */ -+ if (entry->tls_type == 0) -+ return 1; -+ -+ next_index = MIPS_ELF_GOT_SIZE (entry->abfd) * (long) g->tls_assigned_gotno; -+ -+ if (entry->symndx == -1) -+ { -+ /* A type (3) got entry in the single-GOT case. We use the symbol's -+ hash table entry to track its index. */ -+ if (entry->d.h->tls_type & GOT_TLS_OFFSET_DONE) -+ return 1; -+ entry->d.h->tls_type |= GOT_TLS_OFFSET_DONE; -+ entry->d.h->tls_got_offset = next_index; -+ tls_type = entry->d.h->tls_type; -+ } -+ else -+ { -+ entry->gotidx = next_index; -+ tls_type = entry->tls_type; -+ } -+ -+ /* Account for the entries we've just allocated. */ -+ if (tls_type & GOT_TLS_GD) -+ g->tls_assigned_gotno += 2; -+ if (tls_type & GOT_TLS_IE) -+ g->tls_assigned_gotno += 1; -+ -+ return 1; -+} -+ -+/* Return whether an input relocation is against a local symbol. */ -+ -+static bfd_boolean -+mips_elf_local_relocation_p (bfd *input_bfd, -+ const Elf_Internal_Rela *relocation, -+ asection **local_sections) -+{ -+ unsigned long r_symndx; -+ Elf_Internal_Shdr *symtab_hdr; -+ size_t extsymoff; -+ -+ r_symndx = ELF_R_SYM (input_bfd, relocation->r_info); -+ symtab_hdr = &elf_tdata (input_bfd)->symtab_hdr; -+ extsymoff = (elf_bad_symtab (input_bfd)) ? 0 : symtab_hdr->sh_info; -+ -+ if (r_symndx < extsymoff) -+ return TRUE; -+ if (elf_bad_symtab (input_bfd) && local_sections[r_symndx] != NULL) -+ return TRUE; -+ -+ return FALSE; -+} -+ -+/* Create the .got section to hold the global offset table. */ -+ -+static bfd_boolean -+mips_elf_create_got_section (bfd *abfd, struct bfd_link_info *info) -+{ -+ flagword flags; -+ register asection *s; -+ struct elf_link_hash_entry *h; -+ struct bfd_link_hash_entry *bh; -+ struct mips_got_info *g; -+ bfd_size_type amt; -+ struct mips_elf_link_hash_table *htab; -+ -+ htab = mips_elf_hash_table (info); -+ BFD_ASSERT (htab != NULL); -+ -+ /* This function may be called more than once. */ -+ if (htab->sgot) -+ return TRUE; -+ -+ flags = (SEC_ALLOC | SEC_LOAD | SEC_HAS_CONTENTS | SEC_IN_MEMORY -+ | SEC_LINKER_CREATED); -+ -+ /* We have to use an alignment of 2**4 here because this is hardcoded -+ in the function stub generation and in the linker script. */ -+ s = bfd_make_section_with_flags (abfd, ".got", flags); -+ if (s == NULL -+ || ! bfd_set_section_alignment (abfd, s, 4)) -+ return FALSE; -+ htab->sgot = s; -+ -+ /* Define the symbol _GLOBAL_OFFSET_TABLE_. We don't do this in the -+ linker script because we don't want to define the symbol if we -+ are not creating a global offset table. */ -+ bh = NULL; -+ if (! (_bfd_generic_link_add_one_symbol -+ (info, abfd, "_GLOBAL_OFFSET_TABLE_", BSF_GLOBAL, s, -+ 0, NULL, FALSE, get_elf_backend_data (abfd)->collect, &bh))) -+ return FALSE; -+ -+ h = (struct elf_link_hash_entry *) bh; -+ h->non_elf = 0; -+ h->def_regular = 1; -+ h->type = STT_OBJECT; -+ elf_hash_table (info)->hgot = h; -+ -+ if (info->shared -+ && ! bfd_elf_link_record_dynamic_symbol (info, h)) -+ return FALSE; -+ -+ amt = sizeof (struct mips_got_info); -+ g = bfd_alloc (abfd, amt); -+ if (g == NULL) -+ return FALSE; -+ g->global_gotsym = NULL; -+ g->global_gotno = 0; -+ g->reloc_only_gotno = 0; -+ g->tls_gotno = 0; -+ g->local_gotno = 0; -+ g->assigned_gotno = 0; -+ g->got_entries = htab_try_create (1, mips_elf_got_entry_hash, -+ mips_elf_got_entry_eq, NULL); -+ if (g->got_entries == NULL) -+ return FALSE; -+ htab->got_info = g; -+ mips_elf_section_data (s)->elf.this_hdr.sh_flags |= SHF_ALLOC | SHF_WRITE; -+ -+ /* We also need a .got.plt section when generating PLTs. */ -+ s = bfd_make_section_with_flags (abfd, ".got.plt", -+ SEC_ALLOC | SEC_LOAD | SEC_HAS_CONTENTS -+ | SEC_IN_MEMORY | SEC_LINKER_CREATED); -+ if (s == NULL) -+ return FALSE; -+ htab->sgotplt = s; -+ -+ return TRUE; -+} -+ -+/* Return address for Ith PLT stub in section PLT, for relocation REL -+ or (bfd_vma) -1 if it should not be included. */ -+ -+bfd_vma -+_bfd_riscv_elf_plt_sym_val (bfd_vma i, const asection *s, -+ const arelent *rel ATTRIBUTE_UNUSED) -+{ -+ uint32_t plt0_1; -+ if (!bfd_get_section_contents (s->owner, (sec_ptr)s, &plt0_1, 4, 4)) -+ return MINUS_ONE; -+ return s->vma + PLT_HEADER_SIZE + i * PLT_ENTRY_SIZE; -+} -+ -+/* Calculate the value produced by the RELOCATION (which comes from -+ the INPUT_BFD). The ADDEND is the addend to use for this -+ RELOCATION; RELOCATION->R_ADDEND is ignored. -+ -+ The result of the relocation calculation is stored in VALUEP. -+ On exit, set *CROSS_MODE_JUMP_P to true if the relocation field -+ is a MIPS16 jump to non-MIPS16 code, or vice versa. -+ -+ This function returns bfd_reloc_continue if the caller need take no -+ further action regarding this relocation, bfd_reloc_notsupported if -+ something goes dramatically wrong, bfd_reloc_overflow if an -+ overflow occurs, and bfd_reloc_ok to indicate success. */ -+ -+static bfd_reloc_status_type -+mips_elf_calculate_relocation (bfd *abfd, bfd *input_bfd, -+ asection *input_section, -+ struct bfd_link_info *info, -+ const Elf_Internal_Rela *relocation, -+ bfd_vma addend, reloc_howto_type *howto, -+ Elf_Internal_Sym *local_syms, -+ asection **local_sections, bfd_vma *valuep, -+ const char **namep, bfd_byte *contents) -+{ -+ /* The eventual value we will return. */ -+ bfd_vma value; -+ /* The address of the symbol against which the relocation is -+ occurring. */ -+ bfd_vma symbol = 0; -+ /* The place (section offset or address) of the storage unit being -+ relocated. */ -+ bfd_vma p; -+ /* The offset into the global offset table at which the address of -+ the relocation entry symbol, adjusted by the addend, resides -+ during execution. */ -+ bfd_vma g = MINUS_ONE; -+ /* The section in which the symbol referenced by the relocation is -+ located. */ -+ asection *sec = NULL; -+ struct mips_elf_link_hash_entry *h = NULL; -+ /* TRUE if the symbol referred to by this relocation is a local -+ symbol. */ -+ bfd_boolean local_p; -+ Elf_Internal_Shdr *symtab_hdr; -+ size_t extsymoff; -+ unsigned long r_symndx; -+ int r_type; -+ /* TRUE if overflow occurred during the calculation of the -+ relocation value. */ -+ bfd_boolean overflowed_p; -+ /* TRUE if this relocation refers to a MIPS16 function. */ -+ struct mips_elf_link_hash_table *htab; -+ bfd *dynobj; -+ bfd_vma gp = _bfd_get_gp_value (abfd); -+ -+ dynobj = elf_hash_table (info)->dynobj; -+ htab = mips_elf_hash_table (info); -+ BFD_ASSERT (htab != NULL); -+ -+ /* Parse the relocation. */ -+ r_symndx = ELF_R_SYM (input_bfd, relocation->r_info); -+ r_type = ELF_R_TYPE (input_bfd, relocation->r_info); -+ p = sec_addr(input_section) + relocation->r_offset; -+ -+ /* Assume that there will be no overflow. */ -+ overflowed_p = FALSE; -+ -+ /* Figure out whether or not the symbol is local, and get the offset -+ used in the array of hash table entries. */ -+ symtab_hdr = &elf_tdata (input_bfd)->symtab_hdr; -+ local_p = mips_elf_local_relocation_p (input_bfd, relocation, -+ local_sections); -+ if (! elf_bad_symtab (input_bfd)) -+ extsymoff = symtab_hdr->sh_info; -+ else -+ { -+ /* The symbol table does not follow the rule that local symbols -+ must come before globals. */ -+ extsymoff = 0; -+ } -+ -+ /* Figure out the value of the symbol. */ -+ if (local_p) -+ { -+ Elf_Internal_Sym *sym; -+ -+ sym = local_syms + r_symndx; -+ sec = local_sections[r_symndx]; -+ -+ symbol = sec_addr(sec); -+ if (ELF_ST_TYPE (sym->st_info) != STT_SECTION -+ || (sec->flags & SEC_MERGE)) -+ symbol += sym->st_value; -+ if ((sec->flags & SEC_MERGE) -+ && ELF_ST_TYPE (sym->st_info) == STT_SECTION) -+ { -+ addend = _bfd_elf_rel_local_sym (abfd, sym, &sec, addend); -+ addend -= symbol; -+ addend += sec_addr(sec); -+ } -+ -+ /* Record the name of this symbol, for our caller. */ -+ *namep = bfd_elf_string_from_elf_section (input_bfd, -+ symtab_hdr->sh_link, -+ sym->st_name); -+ if (*namep == '\0') -+ *namep = bfd_section_name (input_bfd, sec); -+ } -+ else -+ { -+ /* ??? Could we use RELOC_FOR_GLOBAL_SYMBOL here ? */ -+ -+ /* For global symbols we look up the symbol in the hash-table. */ -+ h = ((struct mips_elf_link_hash_entry *) -+ elf_sym_hashes (input_bfd) [r_symndx - extsymoff]); -+ /* Find the real hash-table entry for this symbol. */ -+ while (h->root.root.type == bfd_link_hash_indirect -+ || h->root.root.type == bfd_link_hash_warning) -+ h = (struct mips_elf_link_hash_entry *) h->root.root.u.i.link; -+ -+ /* Record the name of this symbol, for our caller. */ -+ *namep = h->root.root.root.string; -+ -+ /* If this symbol is defined, calculate its address. */ -+ if ((h->root.root.type == bfd_link_hash_defined -+ || h->root.root.type == bfd_link_hash_defweak) -+ && h->root.root.u.def.section) -+ { -+ sec = h->root.root.u.def.section; -+ if (sec->output_section) -+ symbol = h->root.root.u.def.value + sec_addr(sec); -+ else -+ symbol = h->root.root.u.def.value; -+ } -+ else if (h->root.root.type == bfd_link_hash_undefweak) -+ /* We allow relocations against undefined weak symbols, giving -+ it the value zero, so that you can undefined weak functions -+ and check to see if they exist by looking at their -+ addresses. */ -+ symbol = 0; -+ else if (info->unresolved_syms_in_objects == RM_IGNORE -+ && ELF_ST_VISIBILITY (h->root.other) == STV_DEFAULT) -+ symbol = 0; -+ else if (strcmp (*namep, "_DYNAMIC_LINKING") == 0) -+ { -+ /* If this is a dynamic link, we should have created a -+ _DYNAMIC_LINKING symbol -+ in in _bfd_riscv_elf_create_dynamic_sections. -+ Otherwise, we should define the symbol with a value of 0. -+ FIXME: It should probably get into the symbol table -+ somehow as well. */ -+ BFD_ASSERT (! info->shared); -+ BFD_ASSERT (bfd_get_section_by_name (abfd, ".dynamic") == NULL); -+ symbol = 0; -+ } -+ else if ((*info->callbacks->undefined_symbol) -+ (info, h->root.root.root.string, input_bfd, -+ input_section, relocation->r_offset, -+ (info->unresolved_syms_in_objects == RM_GENERATE_ERROR) -+ || ELF_ST_VISIBILITY (h->root.other))) -+ { -+ return bfd_reloc_undefined; -+ } -+ else -+ { -+ return bfd_reloc_notsupported; -+ } -+ } -+ -+ local_p = h == NULL || SYMBOL_REFERENCES_LOCAL (info, &h->root); -+ -+ /* If we haven't already determined the GOT offset, and we're going -+ to need it, get it now. */ -+ switch (r_type) -+ { -+ case R_RISCV_GOT_HI20: -+ case R_RISCV_GOT_LO12: -+ case R_RISCV_TLS_GD_HI20: -+ case R_RISCV_TLS_GD_LO12: -+ case R_RISCV_TLS_GOT_HI20: -+ case R_RISCV_TLS_GOT_LO12: -+ case R_RISCV_TLS_IE_HI20: -+ case R_RISCV_TLS_IE_LO12: -+ if (!local_p) -+ { -+ BFD_ASSERT (addend == 0); -+ g = mips_elf_global_got_index (dynobj, &h->root, r_type, info); -+ if (h->tls_type == GOT_NORMAL -+ && !elf_hash_table (info)->dynamic_sections_created) -+ /* This is a static link. We must initialize the GOT entry. */ -+ MIPS_ELF_PUT_WORD (dynobj, symbol, htab->sgot->contents + g); -+ } -+ else -+ { -+ g = mips_elf_local_got_index (abfd, input_bfd, info, -+ symbol + addend, r_symndx, h, r_type); -+ if (g == MINUS_ONE) -+ return bfd_reloc_outofrange; -+ } -+ -+ /* Convert GOT indices to actual offsets. */ -+ g = sec_addr(mips_elf_hash_table (info)->sgot) + g; -+ break; -+ } -+ -+ /* Figure out what kind of relocation is being performed. */ -+ switch (r_type) -+ { -+ case R_RISCV_NONE: -+ return bfd_reloc_continue; -+ -+ case R_RISCV_32: -+ case R_RISCV_REL32: -+ case R_RISCV_64: -+ if ((info->shared -+ || (htab->root.dynamic_sections_created -+ && h != NULL -+ && h->root.def_dynamic -+ && !h->root.def_regular -+ && !h->has_static_relocs)) -+ && r_symndx != STN_UNDEF -+ && (h == NULL -+ || h->root.root.type != bfd_link_hash_undefweak -+ || ELF_ST_VISIBILITY (h->root.other) == STV_DEFAULT) -+ && (input_section->flags & SEC_ALLOC) != 0) -+ { -+ /* If we're creating a shared library, then we can't know -+ where the symbol will end up. So, we create a relocation -+ record in the output, and leave the job up to the dynamic -+ linker. We must do the same for executable references to -+ shared library symbols, unless we've decided to use copy -+ relocs or PLTs instead. */ -+ value = addend; -+ if (!mips_elf_create_dynamic_relocation (abfd, -+ info, -+ relocation, -+ h, -+ sec, -+ symbol, -+ &value, -+ input_section)) -+ return bfd_reloc_undefined; -+ } -+ else -+ { -+ if (r_type != R_RISCV_REL32) -+ value = symbol + addend; -+ else -+ value = addend; -+ } -+ value &= howto->dst_mask; -+ break; -+ -+ case R_RISCV_ADD32: -+ case R_RISCV_ADD64: -+ value = addend + symbol; -+ break; -+ -+ case R_RISCV_SUB32: -+ case R_RISCV_SUB64: -+ value = bfd_get (howto->bitsize, input_bfd, -+ contents + relocation->r_offset); -+ value -= addend + symbol; -+ break; -+ -+ case R_RISCV_CALL_PLT: -+ case R_RISCV_CALL: -+ { -+ bfd_vma auipc = bfd_get (32, input_bfd, contents + relocation->r_offset); -+ bfd_vma jalr = bfd_get (32, input_bfd, contents + relocation->r_offset + 4); -+ -+ if (info->shared && h && h->root.plt.offset != MINUS_ONE) -+ symbol = sec_addr(htab->splt) + h->root.plt.offset; -+ value = addend + (symbol ? symbol : p); -+ -+ auipc |= ENCODE_UTYPE_IMM (RISCV_PCREL_HIGH_PART (value, p)); -+ jalr |= ENCODE_ITYPE_IMM (RISCV_PCREL_LOW_PART (value, p)); -+ -+ bfd_put (32, input_bfd, auipc, contents + relocation->r_offset); -+ bfd_put (32, input_bfd, jalr, contents + relocation->r_offset + 4); -+ -+ return bfd_reloc_continue; -+ } -+ case R_RISCV_JAL: -+ if (info->shared && h && h->root.plt.offset != MINUS_ONE) -+ symbol = sec_addr(htab->splt) + h->root.plt.offset; -+ value = addend; -+ if (symbol) -+ value += symbol - p; -+ overflowed_p = !VALID_UJTYPE_IMM (value); -+ if (overflowed_p && !info->shared && VALID_ITYPE_IMM (value + p)) -+ { -+ /* Not all is lost: we can instead use JALR rd, x0, address. */ -+ bfd_vma jal = bfd_get (32, input_bfd, contents+relocation->r_offset); -+ jal = (jal & (OP_MASK_RD << OP_SH_RD)) | MATCH_JALR; -+ jal |= ENCODE_ITYPE_IMM (value + p); -+ bfd_put (32, input_bfd, jal, contents+relocation->r_offset); -+ return bfd_reloc_continue; -+ } -+ value = ENCODE_UJTYPE_IMM (value); -+ break; -+ -+ case R_RISCV_BRANCH: -+ value = addend; -+ if (symbol) -+ value += symbol - p; -+ overflowed_p = !VALID_SBTYPE_IMM (value); -+ value = ENCODE_SBTYPE_IMM (value); -+ break; -+ -+ case R_RISCV_TLS_DTPREL32: -+ case R_RISCV_TLS_DTPREL64: -+ value = ENCODE_ITYPE_IMM (addend + symbol - dtprel_base (info)); -+ break; -+ -+ case R_RISCV_TPREL_HI20: -+ value = RISCV_LUI_HIGH_PART (addend + symbol - tprel_base (info)); -+ value = ENCODE_UTYPE_IMM (value); -+ break; -+ -+ case R_RISCV_TPREL_ADD: -+ case R_RISCV_TLS_IE_ADD: -+ case R_RISCV_TLS_IE_LO12_I: -+ case R_RISCV_TLS_IE_LO12_S: -+ value = 0; -+ break; -+ -+ case R_RISCV_TPREL_LO12_I: -+ case R_RISCV_TPREL_LO12_S: -+ { -+ bfd_vma insn = bfd_get (32, input_bfd, contents + relocation->r_offset); -+ bfd_vma rs1 = (insn >> OP_SH_RS1) & OP_MASK_RS1; -+ -+ value = symbol + addend - tprel_base (info); -+ if (htab->relax && RISCV_CONST_HIGH_PART (value) == 0) -+ rs1 = TP_REG; /* Reference TP directly if possible. */ -+ -+ if (r_type == R_RISCV_TPREL_LO12_I) -+ value = ENCODE_ITYPE_IMM (value); -+ else -+ value = ENCODE_STYPE_IMM (value); -+ value |= rs1 << OP_SH_RS1; -+ break; -+ } -+ -+ case R_RISCV_PCREL_HI20: -+ value = ENCODE_UTYPE_IMM (RISCV_PCREL_HIGH_PART (addend + symbol, p)); -+ break; -+ -+ case R_RISCV_TLS_IE_HI20: -+ value = ENCODE_UTYPE_IMM (RISCV_LUI_HIGH_PART (g)); -+ break; -+ -+ case R_RISCV_TLS_IE_LO12: -+ value = ENCODE_ITYPE_IMM (g); -+ break; -+ -+ case R_RISCV_HI20: -+ value = ENCODE_UTYPE_IMM (RISCV_LUI_HIGH_PART (addend + symbol)); -+ break; -+ -+ case R_RISCV_TLS_PCREL_LO12: -+ case R_RISCV_PCREL_LO12_I: -+ case R_RISCV_PCREL_LO12_S: -+ { -+ bfd_vma insn = bfd_get (32, input_bfd, contents + relocation->r_offset); -+ bfd_vma rd = (insn >> OP_SH_RD) & OP_MASK_RD; -+ bfd_vma rs1 = (insn >> OP_SH_RS1) & OP_MASK_RS1; -+ value = -(p + addend); -+ -+ if (r_type == R_RISCV_PCREL_LO12_S) -+ value = ENCODE_STYPE_IMM (EXTRACT_STYPE_IMM (insn) + value); -+ else if (rs1 == GP_REG && rd != GP_REG) -+ value = insn; /* This has been relaxed. Ignore it. */ -+ else -+ value = ENCODE_ITYPE_IMM (EXTRACT_ITYPE_IMM (insn) + value); -+ break; -+ } -+ -+ case R_RISCV_LO12_I: -+ case R_RISCV_LO12_S: -+ { -+ bfd_vma insn = bfd_get (32, input_bfd, contents + relocation->r_offset); -+ bfd_vma rs1 = (insn >> OP_SH_RS1) & OP_MASK_RS1; -+ -+ value = symbol + addend; -+ if (htab->relax && gp != 0 && value != gp -+ && RISCV_CONST_HIGH_PART (value - gp) == 0) -+ { -+ /* Convert to GP-relative reference. */ -+ value -= gp; -+ rs1 = GP_REG; -+ } -+ -+ if (r_type == R_RISCV_LO12_I) -+ value = ENCODE_ITYPE_IMM (value); -+ else -+ value = ENCODE_STYPE_IMM (value); -+ value |= rs1 << OP_SH_RS1; -+ } -+ break; -+ -+ case R_RISCV_TLS_GOT_HI20: -+ case R_RISCV_TLS_GD_HI20: -+ case R_RISCV_GOT_HI20: -+ value = ENCODE_UTYPE_IMM (RISCV_PCREL_HIGH_PART (g, p)); -+ break; -+ -+ case R_RISCV_TLS_GOT_LO12: -+ case R_RISCV_TLS_GD_LO12: -+ case R_RISCV_GOT_LO12: -+ value = ENCODE_ITYPE_IMM (g); -+ break; -+ -+ default: -+ /* An unrecognized relocation type. */ -+ return bfd_reloc_notsupported; -+ } -+ -+ /* Store the VALUE for our caller. */ -+ *valuep = value; -+ return overflowed_p ? bfd_reloc_overflow : bfd_reloc_ok; -+} -+ -+/* Obtain the field relocated by RELOCATION. */ -+ -+static bfd_vma -+mips_elf_obtain_contents (reloc_howto_type *howto, -+ const Elf_Internal_Rela *relocation, -+ bfd *input_bfd, bfd_byte *contents) -+{ -+ bfd_vma x; -+ bfd_byte *location = contents + relocation->r_offset; -+ -+ /* Obtain the bytes. */ -+ x = bfd_get ((8 * bfd_get_reloc_size (howto)), input_bfd, location); -+ -+ return x; -+} -+ -+/* It has been determined that the result of the RELOCATION is the -+ VALUE. Use HOWTO to place VALUE into the output file at the -+ appropriate position. The SECTION is the section to which the -+ relocation applies. -+ CROSS_MODE_JUMP_P is true if the relocation field -+ is a MIPS16 jump to non-MIPS16 code, or vice versa. -+ -+ Returns FALSE if anything goes wrong. */ -+ -+static bfd_boolean -+mips_elf_perform_relocation (struct bfd_link_info *info ATTRIBUTE_UNUSED, -+ reloc_howto_type *howto, -+ const Elf_Internal_Rela *relocation, -+ bfd_vma value, bfd *input_bfd, -+ asection *input_section ATTRIBUTE_UNUSED, bfd_byte *contents) -+{ -+ bfd_vma x; -+ bfd_byte *location; -+ bfd_vma dst_mask = howto->dst_mask; -+ -+ /* Figure out where the relocation is occurring. */ -+ location = contents + relocation->r_offset; -+ -+ /* Obtain the current value. */ -+ x = mips_elf_obtain_contents (howto, relocation, input_bfd, contents); -+ -+ /* Update the field. */ -+ x = (x &~ dst_mask) | (value & dst_mask); -+ -+ /* Put the value into the output. */ -+ bfd_put (8 * bfd_get_reloc_size (howto), input_bfd, x, location); -+ -+ return TRUE; -+} -+ -+/* Create a rel.dyn relocation for the dynamic linker to resolve. REL -+ is the original relocation, which is now being transformed into a -+ dynamic relocation. The ADDENDP is adjusted if necessary; the -+ caller should store the result in place of the original addend. */ -+ -+static bfd_boolean -+mips_elf_create_dynamic_relocation (bfd *output_bfd, -+ struct bfd_link_info *info, -+ const Elf_Internal_Rela *rel, -+ struct mips_elf_link_hash_entry *h, -+ asection *sec, bfd_vma symbol, -+ bfd_vma *addendp, asection *input_section) -+{ -+ Elf_Internal_Rela outrel; -+ asection *sreloc; -+ int r_type; -+ long indx; -+ bfd_boolean defined_p; -+ struct mips_elf_link_hash_table *htab; -+ -+ htab = mips_elf_hash_table (info); -+ BFD_ASSERT (htab != NULL); -+ -+ r_type = ELF_R_TYPE (output_bfd, rel->r_info); -+ sreloc = mips_elf_rel_dyn_section (info, FALSE); -+ BFD_ASSERT (sreloc != NULL); -+ BFD_ASSERT (sreloc->contents != NULL); -+ BFD_ASSERT (sreloc->reloc_count * MIPS_ELF_REL_SIZE (output_bfd) -+ < sreloc->size); -+ -+ outrel.r_offset = -+ _bfd_elf_section_offset (output_bfd, info, input_section, rel[0].r_offset); -+ -+ if (outrel.r_offset == MINUS_ONE) -+ /* The relocation field has been deleted. */ -+ return TRUE; -+ -+ if (outrel.r_offset == MINUS_TWO) -+ { -+ /* The relocation field has been converted into a relative value of -+ some sort. Functions like _bfd_elf_write_section_eh_frame expect -+ the field to be fully relocated, so add in the symbol's value. */ -+ *addendp += symbol; -+ return TRUE; -+ } -+ -+ /* We must now calculate the dynamic symbol table index to use -+ in the relocation. */ -+ if (h != NULL && ! SYMBOL_REFERENCES_LOCAL (info, &h->root)) -+ { -+ BFD_ASSERT (h->global_got_area != GGA_NONE); -+ indx = h->root.dynindx; -+ /* ??? glibc's ld.so just adds the final GOT entry to the -+ relocation field. It therefore treats relocs against -+ defined symbols in the same way as relocs against -+ undefined symbols. */ -+ defined_p = FALSE; -+ } -+ else -+ { -+ if (sec != NULL && bfd_is_abs_section (sec)) -+ indx = 0; -+ else if (sec == NULL || sec->owner == NULL) -+ { -+ bfd_set_error (bfd_error_bad_value); -+ return FALSE; -+ } -+ else -+ { -+ indx = elf_section_data (sec->output_section)->dynindx; -+ if (indx == 0) -+ { -+ asection *osec = htab->root.text_index_section; -+ indx = elf_section_data (osec)->dynindx; -+ } -+ if (indx == 0) -+ abort (); -+ } -+ -+ /* Instead of generating a relocation using the section -+ symbol, we may as well make it a fully relative -+ relocation. We want to avoid generating relocations to -+ local symbols because we used to generate them -+ incorrectly, without adding the original symbol value, -+ which is mandated by the ABI for section symbols. In -+ order to give dynamic loaders and applications time to -+ phase out the incorrect use, we refrain from emitting -+ section-relative relocations. It's not like they're -+ useful, after all. This should be a bit more efficient -+ as well. */ -+ /* ??? Although this behavior is compatible with glibc's ld.so, -+ the ABI says that relocations against STN_UNDEF should have -+ a symbol value of 0. Irix rld honors this, so relocations -+ against STN_UNDEF have no effect. */ -+ indx = 0; -+ defined_p = TRUE; -+ } -+ -+ /* If the relocation was previously an absolute relocation and -+ this symbol will not be referred to by the relocation, we must -+ adjust it by the value we give it in the dynamic symbol table. -+ Otherwise leave the job up to the dynamic linker. */ -+ if (defined_p && r_type != R_RISCV_REL32) -+ *addendp += symbol; -+ -+ /* The relocation is always an REL32 relocation because we don't -+ know where the shared library will wind up at load-time. */ -+ outrel.r_info = ELF_R_INFO (output_bfd, (unsigned long) indx, -+ R_RISCV_REL32); -+ -+ /* Adjust the output offset of the relocation to reference the -+ correct location in the output file. */ -+ outrel.r_offset += sec_addr(input_section); -+ -+ /* Put the relocation back out. */ -+ if (ABI_64_P (output_bfd)) -+ bfd_elf64_swap_reloc_out -+ (output_bfd, &outrel, -+ (sreloc->contents + sreloc->reloc_count * sizeof (Elf64_External_Rel))); -+ else -+ bfd_elf32_swap_reloc_out -+ (output_bfd, &outrel, -+ (sreloc->contents + sreloc->reloc_count * sizeof (Elf32_External_Rel))); -+ -+ /* We've now added another relocation. */ -+ ++sreloc->reloc_count; -+ -+ /* Make sure the output section is writable. The dynamic linker -+ will be writing to it. */ -+ elf_section_data (input_section->output_section)->this_hdr.sh_flags -+ |= SHF_WRITE; -+ -+ /* If we've written this relocation for a readonly section, -+ we need to set DF_TEXTREL again, so that we do not delete the -+ DT_TEXTREL tag. */ -+ if (MIPS_ELF_READONLY_SECTION (input_section)) -+ info->flags |= DF_TEXTREL; -+ -+ return TRUE; -+} -+ -+/* Return printable name for ABI. */ -+ -+static INLINE char * -+elf_mips_abi_name (bfd *abfd) -+{ -+ return ABI_32_P (abfd) ? "rv32" : "rv64"; -+} -+ -+/* This is used for both the 32-bit and the 64-bit ABI. */ -+ -+void -+_bfd_riscv_elf_symbol_processing (bfd *abfd ATTRIBUTE_UNUSED, asymbol *asym) -+{ -+ elf_symbol_type *elfsym; -+ -+ /* Handle the special MIPS section numbers that a symbol may use. */ -+ elfsym = (elf_symbol_type *) asym; -+ switch (elfsym->internal_elf_sym.st_shndx) -+ { -+ case SHN_COMMON: -+ break; -+ -+ case SHN_MIPS_SUNDEFINED: -+ asym->section = bfd_und_section_ptr; -+ break; -+ } -+ -+ /* If this is an odd-valued function symbol, assume it's a MIPS16 one. */ -+ if (ELF_ST_TYPE (elfsym->internal_elf_sym.st_info) == STT_FUNC -+ && (asym->value & 1) != 0) -+ { -+ asym->value--; -+ elfsym->internal_elf_sym.st_other -+ = ELF_ST_SET_MIPS16 (elfsym->internal_elf_sym.st_other); -+ } -+} -+ -+/* Implement elf_backend_eh_frame_address_size. */ -+ -+unsigned int -+_bfd_riscv_elf_eh_frame_address_size (bfd *abfd, asection *sec ATTRIBUTE_UNUSED) -+{ -+ if (elf_elfheader (abfd)->e_ident[EI_CLASS] == ELFCLASS64) -+ return 8; -+ return 4; -+} -+ -+/* Hook called by the linker routine which adds symbols from an object -+ file. We must handle the special MIPS section numbers here. */ -+ -+bfd_boolean -+_bfd_riscv_elf_add_symbol_hook (bfd *abfd ATTRIBUTE_UNUSED, -+ struct bfd_link_info *info ATTRIBUTE_UNUSED, -+ Elf_Internal_Sym *sym, const char **namep ATTRIBUTE_UNUSED, -+ flagword *flagsp ATTRIBUTE_UNUSED, -+ asection **secp, bfd_vma *valp ATTRIBUTE_UNUSED) -+{ -+ switch (sym->st_shndx) -+ { -+ case SHN_COMMON: -+ break; -+ -+ case SHN_MIPS_TEXT: -+ /* This section is used in a shared object. */ -+ if (elf_tdata (abfd)->elf_text_section == NULL) -+ { -+ asymbol *elf_text_symbol; -+ asection *elf_text_section; -+ bfd_size_type amt = sizeof (asection); -+ -+ elf_text_section = bfd_zalloc (abfd, amt); -+ if (elf_text_section == NULL) -+ return FALSE; -+ -+ amt = sizeof (asymbol); -+ elf_text_symbol = bfd_zalloc (abfd, amt); -+ if (elf_text_symbol == NULL) -+ return FALSE; -+ -+ /* Initialize the section. */ -+ -+ elf_tdata (abfd)->elf_text_section = elf_text_section; -+ elf_tdata (abfd)->elf_text_symbol = elf_text_symbol; -+ -+ elf_text_section->symbol = elf_text_symbol; -+ elf_text_section->symbol_ptr_ptr = &elf_tdata (abfd)->elf_text_symbol; -+ -+ elf_text_section->name = ".text"; -+ elf_text_section->flags = SEC_NO_FLAGS; -+ elf_text_section->output_section = NULL; -+ elf_text_section->owner = abfd; -+ elf_text_symbol->name = ".text"; -+ elf_text_symbol->flags = BSF_SECTION_SYM | BSF_DYNAMIC; -+ elf_text_symbol->section = elf_text_section; -+ } -+ /* This code used to do *secp = bfd_und_section_ptr if -+ info->shared. I don't know why, and that doesn't make sense, -+ so I took it out. */ -+ *secp = elf_tdata (abfd)->elf_text_section; -+ break; -+ -+ case SHN_MIPS_DATA: -+ /* This section is used in a shared object. */ -+ if (elf_tdata (abfd)->elf_data_section == NULL) -+ { -+ asymbol *elf_data_symbol; -+ asection *elf_data_section; -+ bfd_size_type amt = sizeof (asection); -+ -+ elf_data_section = bfd_zalloc (abfd, amt); -+ if (elf_data_section == NULL) -+ return FALSE; -+ -+ amt = sizeof (asymbol); -+ elf_data_symbol = bfd_zalloc (abfd, amt); -+ if (elf_data_symbol == NULL) -+ return FALSE; -+ -+ /* Initialize the section. */ -+ -+ elf_tdata (abfd)->elf_data_section = elf_data_section; -+ elf_tdata (abfd)->elf_data_symbol = elf_data_symbol; -+ -+ elf_data_section->symbol = elf_data_symbol; -+ elf_data_section->symbol_ptr_ptr = &elf_tdata (abfd)->elf_data_symbol; -+ -+ elf_data_section->name = ".data"; -+ elf_data_section->flags = SEC_NO_FLAGS; -+ elf_data_section->output_section = NULL; -+ elf_data_section->owner = abfd; -+ elf_data_symbol->name = ".data"; -+ elf_data_symbol->flags = BSF_SECTION_SYM | BSF_DYNAMIC; -+ elf_data_symbol->section = elf_data_section; -+ } -+ /* This code used to do *secp = bfd_und_section_ptr if -+ info->shared. I don't know why, and that doesn't make sense, -+ so I took it out. */ -+ *secp = elf_tdata (abfd)->elf_data_section; -+ break; -+ -+ case SHN_MIPS_SUNDEFINED: -+ *secp = bfd_und_section_ptr; -+ break; -+ } -+ -+ return TRUE; -+} -+ -+/* Functions for the dynamic linker. */ -+ -+/* Create dynamic sections when linking against a dynamic object. */ -+ -+bfd_boolean -+_bfd_riscv_elf_create_dynamic_sections (bfd *abfd, struct bfd_link_info *info) -+{ -+ struct elf_link_hash_entry *h; -+ struct bfd_link_hash_entry *bh; -+ flagword flags; -+ register asection *s; -+ struct mips_elf_link_hash_table *htab; -+ -+ htab = mips_elf_hash_table (info); -+ BFD_ASSERT (htab != NULL); -+ -+ flags = (SEC_ALLOC | SEC_LOAD | SEC_HAS_CONTENTS | SEC_IN_MEMORY -+ | SEC_LINKER_CREATED | SEC_READONLY); -+ -+ /* The psABI requires a read-only .dynamic section. */ -+ s = bfd_get_section_by_name (abfd, ".dynamic"); -+ if (s != NULL) -+ { -+ if (! bfd_set_section_flags (abfd, s, flags)) -+ return FALSE; -+ } -+ -+ /* We need to create .got section. */ -+ if (!mips_elf_create_got_section (abfd, info)) -+ return FALSE; -+ -+ if (! mips_elf_rel_dyn_section (info, TRUE)) -+ return FALSE; -+ -+ if (!info->shared) -+ { -+ const char *name; -+ -+ name = "_DYNAMIC_LINKING"; -+ bh = NULL; -+ if (!(_bfd_generic_link_add_one_symbol -+ (info, abfd, name, BSF_GLOBAL, bfd_abs_section_ptr, 0, -+ NULL, FALSE, get_elf_backend_data (abfd)->collect, &bh))) -+ return FALSE; -+ -+ h = (struct elf_link_hash_entry *) bh; -+ h->non_elf = 0; -+ h->def_regular = 1; -+ h->type = STT_SECTION; -+ -+ if (! bfd_elf_link_record_dynamic_symbol (info, h)) -+ return FALSE; -+ } -+ -+ /* Create the .plt, .rel(a).plt, .dynbss and .rel(a).bss sections. -+ Also create the _PROCEDURE_LINKAGE_TABLE symbol. */ -+ if (!_bfd_elf_create_dynamic_sections (abfd, info)) -+ return FALSE; -+ -+ /* Cache the sections created above. */ -+ htab->splt = bfd_get_section_by_name (abfd, ".plt"); -+ htab->sdynbss = bfd_get_section_by_name (abfd, ".dynbss"); -+ htab->srelplt = bfd_get_section_by_name (abfd, ".rel.plt"); -+ if (!htab->sdynbss -+ || !htab->srelplt -+ || !htab->splt) -+ abort (); -+ -+ return TRUE; -+} -+ -+/* Look through the relocs for a section during the first phase, and -+ allocate space in the global offset table. */ -+ -+bfd_boolean -+_bfd_riscv_elf_check_relocs (bfd *abfd, struct bfd_link_info *info, -+ asection *sec, const Elf_Internal_Rela *relocs) -+{ -+ const char *name; -+ bfd *dynobj; -+ Elf_Internal_Shdr *symtab_hdr; -+ struct elf_link_hash_entry **sym_hashes; -+ size_t extsymoff; -+ const Elf_Internal_Rela *rel; -+ const Elf_Internal_Rela *rel_end; -+ asection *sreloc; -+ const struct elf_backend_data *bed; -+ -+ if (info->relocatable) -+ return TRUE; -+ -+ dynobj = elf_hash_table (info)->dynobj; -+ symtab_hdr = &elf_tdata (abfd)->symtab_hdr; -+ sym_hashes = elf_sym_hashes (abfd); -+ extsymoff = (elf_bad_symtab (abfd)) ? 0 : symtab_hdr->sh_info; -+ -+ bed = get_elf_backend_data (abfd); -+ rel_end = relocs + sec->reloc_count * bed->s->int_rels_per_ext_rel; -+ -+ name = bfd_get_section_name (abfd, sec); -+ -+ sreloc = NULL; -+ for (rel = relocs; rel < rel_end; ++rel) -+ { -+ unsigned long r_symndx; -+ unsigned int r_type; -+ struct elf_link_hash_entry *h; -+ bfd_boolean can_make_dynamic_p; -+ -+ r_symndx = ELF_R_SYM (abfd, rel->r_info); -+ r_type = ELF_R_TYPE (abfd, rel->r_info); -+ -+ if (r_symndx < extsymoff) -+ h = NULL; -+ else if (r_symndx >= extsymoff + NUM_SHDR_ENTRIES (symtab_hdr)) -+ { -+ (*_bfd_error_handler) -+ (_("%B: Malformed reloc detected for section %s"), -+ abfd, name); -+ bfd_set_error (bfd_error_bad_value); -+ return FALSE; -+ } -+ else -+ { -+ h = sym_hashes[r_symndx - extsymoff]; -+ while (h != NULL -+ && (h->root.type == bfd_link_hash_indirect -+ || h->root.type == bfd_link_hash_warning)) -+ h = (struct elf_link_hash_entry *) h->root.u.i.link; -+ } -+ -+ /* Set CAN_MAKE_DYNAMIC_P to true if we can convert this -+ relocation into a dynamic one. */ -+ can_make_dynamic_p = FALSE; -+ switch (r_type) -+ { -+ case R_RISCV_GOT_HI20: -+ case R_RISCV_GOT_LO12: -+ case R_RISCV_TLS_GOT_HI20: -+ case R_RISCV_TLS_GOT_LO12: -+ case R_RISCV_TLS_GD_HI20: -+ case R_RISCV_TLS_GD_LO12: -+ case R_RISCV_TLS_IE_HI20: -+ case R_RISCV_TLS_IE_LO12: -+ case R_RISCV_TLS_IE_ADD: -+ case R_RISCV_TLS_IE_LO12_I: -+ case R_RISCV_TLS_IE_LO12_S: -+ if (dynobj == NULL) -+ elf_hash_table (info)->dynobj = dynobj = abfd; -+ if (!mips_elf_create_got_section (dynobj, info)) -+ return FALSE; -+ break; -+ -+ case R_RISCV_32: -+ case R_RISCV_REL32: -+ case R_RISCV_64: -+ /* For executables that use PLTs and copy-relocs, we have a -+ choice between converting the relocation into a dynamic -+ one or using copy relocations or PLT entries. It is -+ usually better to do the former, unless the relocation is -+ against a read-only section. */ -+ if ((info->shared -+ || (h != NULL -+ && !(!info->nocopyreloc && MIPS_ELF_READONLY_SECTION (sec)))) -+ && (sec->flags & SEC_ALLOC) != 0) -+ { -+ can_make_dynamic_p = TRUE; -+ if (dynobj == NULL) -+ elf_hash_table (info)->dynobj = dynobj = abfd; -+ break; -+ } -+ /* For sections that are not SEC_ALLOC a copy reloc would be -+ output if possible (implying questionable semantics for -+ read-only data objects) or otherwise the final link would -+ fail as ld.so will not process them and could not therefore -+ handle any outstanding dynamic relocations. -+ -+ For such sections that are also SEC_DEBUGGING, we can avoid -+ these problems by simply ignoring any relocs as these -+ sections have a predefined use and we know it is safe to do -+ so. -+ -+ This is needed in cases such as a global symbol definition -+ in a shared library causing a common symbol from an object -+ file to be converted to an undefined reference. If that -+ happens, then all the relocations against this symbol from -+ SEC_DEBUGGING sections in the object file will resolve to -+ nil. */ -+ if ((sec->flags & SEC_DEBUGGING) != 0) -+ break; -+ /* Fall through. */ -+ -+ default: -+ /* Most static relocations require pointer equality, except -+ for branches. */ -+ if (h) -+ h->pointer_equality_needed = TRUE; -+ /* Fall through. */ -+ -+ case R_RISCV_CALL_PLT: -+ if (info->shared && h) -+ h->needs_plt = TRUE; -+ case R_RISCV_JAL: -+ case R_RISCV_CALL: -+ if (h) -+ ((struct mips_elf_link_hash_entry *) h)->has_static_relocs = TRUE; -+ case R_RISCV_BRANCH: -+ break; -+ } -+ -+ switch (r_type) -+ { -+ case R_RISCV_GOT_LO12: -+ if (!mips_elf_record_local_got_symbol (abfd, r_symndx, -+ rel->r_addend, info, 0)) -+ return FALSE; -+ /* Fall through. */ -+ case R_RISCV_GOT_HI20: -+ if (h && !mips_elf_record_global_got_symbol (h, abfd, info, 0)) -+ return FALSE; -+ break; -+ -+ case R_RISCV_TLS_GOT_HI20: -+ case R_RISCV_TLS_GOT_LO12: -+ case R_RISCV_TLS_IE_HI20: -+ case R_RISCV_TLS_IE_LO12: -+ if (info->shared) -+ info->flags |= DF_STATIC_TLS; -+ /* Fall through */ -+ -+ case R_RISCV_TLS_GD_HI20: -+ case R_RISCV_TLS_GD_LO12: -+ /* This symbol requires a global offset table entry, or two -+ for TLS GD relocations. */ -+ { -+ unsigned char flag = (TLS_GD_RELOC_P(r_type) -+ ? GOT_TLS_GD -+ : GOT_TLS_IE); -+ if (h != NULL) -+ { -+ struct mips_elf_link_hash_entry *hmips = -+ (struct mips_elf_link_hash_entry *) h; -+ hmips->tls_type |= flag; -+ -+ if (h && !mips_elf_record_global_got_symbol (h, abfd, info, flag)) -+ return FALSE; -+ } -+ else -+ { -+ BFD_ASSERT (r_symndx != STN_UNDEF); -+ -+ if (!mips_elf_record_local_got_symbol (abfd, r_symndx, -+ rel->r_addend, -+ info, flag)) -+ return FALSE; -+ } -+ } -+ break; -+ -+ case R_RISCV_32: -+ case R_RISCV_REL32: -+ case R_RISCV_64: -+ /* In VxWorks executables, references to external symbols -+ are handled using copy relocs or PLT stubs, so there's -+ no need to add a .rela.dyn entry for this relocation. */ -+ if (can_make_dynamic_p) -+ { -+ if (sreloc == NULL) -+ { -+ sreloc = mips_elf_rel_dyn_section (info, TRUE); -+ if (sreloc == NULL) -+ return FALSE; -+ } -+ if (info->shared && h == NULL) -+ { -+ /* When creating a shared object, we must copy these -+ reloc types into the output file as R_RISCV_REL32 -+ relocs. Make room for this reloc in .rel(a).dyn. */ -+ mips_elf_allocate_dynamic_relocations (dynobj, info, 1); -+ if (MIPS_ELF_READONLY_SECTION (sec)) -+ /* We tell the dynamic linker that there are -+ relocations against the text segment. */ -+ info->flags |= DF_TEXTREL; -+ } -+ else -+ { -+ struct mips_elf_link_hash_entry *hmips; -+ -+ /* For a shared object, we must copy this relocation -+ unless the symbol turns out to be undefined and -+ weak with non-default visibility, in which case -+ it will be left as zero. -+ -+ We could elide R_RISCV_REL32 for locally binding symbols -+ in shared libraries, but do not yet do so. -+ -+ For an executable, we only need to copy this -+ reloc if the symbol is defined in a dynamic -+ object. */ -+ hmips = (struct mips_elf_link_hash_entry *) h; -+ ++hmips->possibly_dynamic_relocs; -+ if (MIPS_ELF_READONLY_SECTION (sec)) -+ /* We need it to tell the dynamic linker if there -+ are relocations against the text segment. */ -+ hmips->readonly_reloc = TRUE; -+ } -+ } -+ -+ break; -+ -+ case R_RISCV_JAL: -+ break; -+ -+ case R_RISCV_HI20: -+ case R_RISCV_TPREL_HI20: -+ /* Can't use these in a shared library. */ -+ if (info->shared) -+ { -+ reloc_howto_type *howto = riscv_elf_rtype_to_howto (r_type); -+ (*_bfd_error_handler) -+ (_("%B: relocation %s against `%s' can not be used when making a shared object; recompile with -fPIC"), -+ abfd, howto->name, -+ (h) ? h->root.root.string : "a local symbol"); -+ bfd_set_error (bfd_error_bad_value); -+ return FALSE; -+ } -+ break; -+ -+ default: -+ break; -+ } -+ } -+ -+ return TRUE; -+} -+ -+/* Allocate space for global sym dynamic relocs. */ -+ -+static bfd_boolean -+allocate_dynrelocs (struct elf_link_hash_entry *h, void *inf) -+{ -+ struct bfd_link_info *info = inf; -+ bfd *dynobj; -+ struct mips_elf_link_hash_entry *hmips; -+ struct mips_elf_link_hash_table *htab; -+ -+ htab = mips_elf_hash_table (info); -+ BFD_ASSERT (htab != NULL); -+ -+ dynobj = elf_hash_table (info)->dynobj; -+ hmips = (struct mips_elf_link_hash_entry *) h; -+ -+ /* Ignore indirect and warning symbols. All relocations against -+ such symbols will be redirected to the target symbol. */ -+ if (h->root.type == bfd_link_hash_indirect -+ || h->root.type == bfd_link_hash_warning) -+ return TRUE; -+ -+ /* If this symbol is defined in a dynamic object, or we are creating -+ a shared library, we will need to copy any R_RISCV_32 or -+ R_RISCV_REL32 relocs against it into the output file. */ -+ if (! info->relocatable -+ && hmips->possibly_dynamic_relocs != 0 -+ && (h->root.type == bfd_link_hash_defweak -+ || !h->def_regular -+ || info->shared)) -+ { -+ bfd_boolean do_copy = TRUE; -+ -+ if (h->root.type == bfd_link_hash_undefweak) -+ { -+ /* Do not copy relocations for undefined weak symbols with -+ non-default visibility. */ -+ if (ELF_ST_VISIBILITY (h->other) != STV_DEFAULT) -+ do_copy = FALSE; -+ -+ /* Make sure undefined weak symbols are output as a dynamic -+ symbol in PIEs. */ -+ else if (h->dynindx == -1 && !h->forced_local) -+ { -+ if (! bfd_elf_link_record_dynamic_symbol (info, h)) -+ return FALSE; -+ } -+ } -+ -+ if (do_copy) -+ { -+ /* Even though we don't directly need a GOT entry for this symbol, -+ the SVR4 psABI requires it to have a dynamic symbol table -+ index greater that DT_RISCV_GOTSYM if there are dynamic -+ relocations against it. */ -+ if (hmips->global_got_area > GGA_RELOC_ONLY) -+ hmips->global_got_area = GGA_RELOC_ONLY; -+ -+ mips_elf_allocate_dynamic_relocations -+ (dynobj, info, hmips->possibly_dynamic_relocs); -+ if (hmips->readonly_reloc) -+ /* We tell the dynamic linker that there are relocations -+ against the text segment. */ -+ info->flags |= DF_TEXTREL; -+ } -+ } -+ -+ return TRUE; -+} -+ -+/* Adjust a symbol defined by a dynamic object and referenced by a -+ regular object. The current definition is in some section of the -+ dynamic object, but we're not including those sections. We have to -+ change the definition to something the rest of the link can -+ understand. */ -+ -+bfd_boolean -+_bfd_riscv_elf_adjust_dynamic_symbol (struct bfd_link_info *info, -+ struct elf_link_hash_entry *h) -+{ -+ bfd *dynobj; -+ struct mips_elf_link_hash_entry *hmips; -+ struct mips_elf_link_hash_table *htab; -+ -+ htab = mips_elf_hash_table (info); -+ BFD_ASSERT (htab != NULL); -+ -+ dynobj = elf_hash_table (info)->dynobj; -+ hmips = (struct mips_elf_link_hash_entry *) h; -+ -+ /* Make sure we know what is going on here. */ -+ BFD_ASSERT (dynobj != NULL -+ && (h->needs_plt -+ || h->u.weakdef != NULL -+ || (h->def_dynamic -+ && h->ref_regular -+ && !h->def_regular))); -+ -+ hmips = (struct mips_elf_link_hash_entry *) h; -+ -+ /* Establish PLT entries for functions that don't bind locally. */ -+ if (h->type == STT_FUNC && hmips->has_static_relocs -+ && !SYMBOL_CALLS_LOCAL (info, h) -+ && !(ELF_ST_VISIBILITY (h->other) != STV_DEFAULT -+ && h->root.type == bfd_link_hash_undefweak)) -+ { -+ /* We'll turn this into an actual address once we know the PLT size. */ -+ h->plt.offset = htab->nplt++; -+ -+ return TRUE; -+ } -+ -+ /* If this is a weak symbol, and there is a real definition, the -+ processor independent code will have arranged for us to see the -+ real definition first, and we can just use the same value. */ -+ if (h->u.weakdef != NULL) -+ { -+ BFD_ASSERT (h->u.weakdef->root.type == bfd_link_hash_defined -+ || h->u.weakdef->root.type == bfd_link_hash_defweak); -+ h->root.u.def.section = h->u.weakdef->root.u.def.section; -+ h->root.u.def.value = h->u.weakdef->root.u.def.value; -+ return TRUE; -+ } -+ -+ /* Otherwise, there is nothing further to do for symbols defined -+ in regular objects. */ -+ if (h->def_regular) -+ return TRUE; -+ -+ /* There's also nothing more to do if we'll convert all relocations -+ against this symbol into dynamic relocations. */ -+ if (!hmips->has_static_relocs) -+ return TRUE; -+ -+ /* We must allocate the symbol in our .dynbss section, which will -+ become part of the .bss section of the executable. There will be -+ an entry for this symbol in the .dynsym section. The dynamic -+ object will contain position independent code, so all references -+ from the dynamic object to this symbol will go through the global -+ offset table. The dynamic linker will use the .dynsym entry to -+ determine the address it must put in the global offset table, so -+ both the dynamic object and the regular object will refer to the -+ same memory location for the variable. */ -+ -+ if ((h->root.u.def.section->flags & SEC_ALLOC) != 0) -+ { -+ mips_elf_allocate_dynamic_relocations (dynobj, info, 1); -+ h->needs_copy = 1; -+ } -+ -+ /* All relocations against this symbol that could have been made -+ dynamic will now refer to the local copy instead. */ -+ hmips->possibly_dynamic_relocs = 0; -+ -+ return _bfd_elf_adjust_dynamic_copy (h, htab->sdynbss); -+} -+ -+bfd_boolean -+_bfd_riscv_elf_always_size_sections (bfd *output_bfd ATTRIBUTE_UNUSED, -+ struct bfd_link_info *info ATTRIBUTE_UNUSED) -+{ -+ return TRUE; -+} -+ -+static struct bfd_link_hash_entry * -+bfd_riscv_gp_hash (struct bfd_link_info *info) -+{ -+ if (info->shared) -+ return NULL; -+ return bfd_link_hash_lookup (info->hash, "_gp", FALSE, FALSE, TRUE); -+} -+ -+static bfd_vma -+bfd_riscv_init_gp_value (bfd *abfd, struct bfd_link_info *info) -+{ -+ struct bfd_link_hash_entry *h = bfd_riscv_gp_hash (info); -+ -+ if (h != NULL && h->type == bfd_link_hash_defined) -+ elf_gp (abfd) = h->u.def.value + sec_addr(h->u.def.section); -+ -+ return elf_gp (abfd); -+} -+ -+/* After the PLT has been sized, compute PLT entry offsets. */ -+ -+static int -+riscv_elf_compute_plt_offset (void *arg1, void *arg2) -+{ -+ struct elf_link_hash_entry *h = arg1; -+ struct mips_elf_link_hash_table *htab = arg2; -+ -+ if (h->plt.offset != MINUS_ONE) -+ { -+ h->plt.offset = h->plt.offset * PLT_ENTRY_SIZE + PLT_HEADER_SIZE; -+ -+ /* If the output file has no definition of the symbol, set the -+ symbol's value to the address of the stub. */ -+ if (!h->def_regular) -+ { -+ h->root.u.def.section = htab->splt; -+ h->root.u.def.value = h->plt.offset; -+ } -+ } -+ -+ return 1; -+} -+ -+/* If the link uses a GOT, lay it out and work out its size. */ -+ -+static bfd_boolean -+mips_elf_lay_out_got (bfd *output_bfd, struct bfd_link_info *info) -+{ -+ bfd *dynobj; -+ asection *s; -+ struct mips_got_info *g; -+ bfd_size_type loadable_size = 0; -+ bfd *sub; -+ struct mips_elf_count_tls_arg count_tls_arg; -+ struct mips_elf_link_hash_table *htab; -+ struct mips_elf_count_tls_arg arg; -+ -+ htab = mips_elf_hash_table (info); -+ BFD_ASSERT (htab != NULL); -+ -+ s = htab->sgot; -+ if (s == NULL) -+ return TRUE; -+ -+ dynobj = elf_hash_table (info)->dynobj; -+ g = htab->got_info; -+ -+ /* Allocate room for the reserved entries. */ -+ BFD_ASSERT (g->assigned_gotno == 0); -+ htab->reserved_gotno = 2; -+ g->local_gotno += htab->reserved_gotno; -+ g->assigned_gotno = htab->reserved_gotno; -+ -+ /* Replace entries for indirect and warning symbols with entries for -+ the target symbol. */ -+ if (!mips_elf_resolve_final_got_entries (g)) -+ return FALSE; -+ -+ /* Count the number of GOT symbols. */ -+ mips_elf_link_hash_traverse (htab, mips_elf_count_got_symbols, info); -+ -+ /* Calculate the total loadable size of the output. That -+ will give us the maximum number of GOT_PAGE entries -+ required. */ -+ for (sub = info->input_bfds; sub; sub = sub->link_next) -+ { -+ asection *subsection; -+ -+ for (subsection = sub->sections; -+ subsection; -+ subsection = subsection->next) -+ { -+ if ((subsection->flags & SEC_ALLOC) == 0) -+ continue; -+ loadable_size += ((subsection->size + 0xf) -+ &~ (bfd_size_type) 0xf); -+ } -+ } -+ -+ s->size += g->local_gotno * MIPS_ELF_GOT_SIZE (output_bfd); -+ s->size += g->global_gotno * MIPS_ELF_GOT_SIZE (output_bfd); -+ -+ /* We need to calculate tls_gotno for global symbols at this point -+ instead of building it up earlier, to avoid doublecounting -+ entries for one global symbol from multiple input files. */ -+ count_tls_arg.info = info; -+ count_tls_arg.needed = 0; -+ elf_link_hash_traverse (elf_hash_table (info), -+ mips_elf_count_global_tls_entries, -+ &count_tls_arg); -+ g->tls_gotno += count_tls_arg.needed; -+ s->size += g->tls_gotno * MIPS_ELF_GOT_SIZE (output_bfd); -+ -+ /* Set up TLS entries. */ -+ g->tls_assigned_gotno = g->global_gotno + g->local_gotno; -+ htab_traverse (g->got_entries, mips_elf_initialize_tls_index, g); -+ -+ /* Allocate room for the TLS relocations. */ -+ arg.info = info; -+ arg.needed = 0; -+ htab_traverse (g->got_entries, mips_elf_count_local_tls_relocs, &arg); -+ elf_link_hash_traverse (elf_hash_table (info), -+ mips_elf_count_global_tls_relocs, &arg); -+ if (arg.needed) -+ mips_elf_allocate_dynamic_relocations (dynobj, info, arg.needed); -+ -+ return TRUE; -+} -+ -+/* Set the sizes of the dynamic sections. */ -+ -+bfd_boolean -+_bfd_riscv_elf_size_dynamic_sections (bfd *output_bfd, -+ struct bfd_link_info *info) -+{ -+ bfd *dynobj; -+ asection *s, *sreldyn; -+ struct mips_elf_link_hash_table *htab; -+ -+ htab = mips_elf_hash_table (info); -+ BFD_ASSERT (htab != NULL); -+ dynobj = elf_hash_table (info)->dynobj; -+ BFD_ASSERT (dynobj != NULL); -+ -+ if (elf_hash_table (info)->dynamic_sections_created) -+ { -+ /* If we have a PLT, size it and create its symbol. */ -+ if (htab->nplt != 0 && htab->root.hplt == NULL) -+ { -+ struct elf_link_hash_entry *h; -+ -+ BFD_ASSERT (htab->splt->size == 0); -+ htab->splt->size = PLT_HEADER_SIZE + htab->nplt * PLT_ENTRY_SIZE; -+ -+ /* The last and first two entries in .got.plt are reserved. */ -+ BFD_ASSERT (htab->sgotplt->size == 0); -+ htab->sgotplt->size = (3 + htab->nplt) * MIPS_ELF_GOT_SIZE (dynobj); -+ -+ /* Make room for the R_RISCV_JUMP_SLOT relocations. */ -+ BFD_ASSERT (htab->srelplt->size == 0); -+ htab->srelplt->size = htab->nplt * MIPS_ELF_REL_SIZE (dynobj); -+ -+ /* Adjust the PLT offsets. */ -+ elf_link_hash_traverse (elf_hash_table (info), -+ riscv_elf_compute_plt_offset, -+ htab); -+ -+ /* PLT entries are 16 bytes. Don't let them span I$ lines. */ -+ if (!bfd_set_section_alignment (dynobj, htab->splt, 4)) -+ return FALSE; -+ -+ /* The PLT header requires .got.plt be 2-word aligned. */ -+ if (!bfd_set_section_alignment (dynobj, htab->sgotplt, -+ MIPS_ELF_LOG_FILE_ALIGN (dynobj)+1)) -+ return FALSE; -+ -+ /* Make the symbol. */ -+ h = _bfd_elf_define_linkage_sym (dynobj, info, htab->splt, -+ "_PROCEDURE_LINKAGE_TABLE_"); -+ htab->root.hplt = h; -+ if (h == NULL) -+ return FALSE; -+ h->type = STT_FUNC; -+ } -+ -+ /* Set the contents of the .interp section to the interpreter. */ -+ if (info->executable) -+ { -+ s = bfd_get_section_by_name (dynobj, ".interp"); -+ BFD_ASSERT (s != NULL); -+ s->size -+ = strlen (ELF_DYNAMIC_INTERPRETER (output_bfd)) + 1; -+ s->contents -+ = (bfd_byte *) ELF_DYNAMIC_INTERPRETER (output_bfd); -+ } -+ } -+ -+ /* Allocate space for global sym dynamic relocs. */ -+ elf_link_hash_traverse (&htab->root, allocate_dynrelocs, (PTR) info); -+ -+ if (!mips_elf_lay_out_got (output_bfd, info)) -+ return FALSE; -+ -+ /* The check_relocs and adjust_dynamic_symbol entry points have -+ determined the sizes of the various dynamic sections. Allocate -+ memory for them. */ -+ for (s = dynobj->sections; s != NULL; s = s->next) -+ { -+ const char *name; -+ -+ /* It's OK to base decisions on the section name, because none -+ of the dynobj section names depend upon the input files. */ -+ name = bfd_get_section_name (dynobj, s); -+ -+ if ((s->flags & SEC_LINKER_CREATED) == 0) -+ continue; -+ -+ if (CONST_STRNEQ (name, ".rel")) -+ { -+ if (s->size != 0) -+ { -+ /* We use the reloc_count field as a counter if we need -+ to copy relocs into the output file. */ -+ if (strcmp (name, MIPS_ELF_REL_DYN_NAME (info)) != 0) -+ s->reloc_count = 0; -+ -+ /* If combreloc is enabled, elf_link_sort_relocs() will -+ sort relocations, but in a different way than we do, -+ and before we're done creating relocations. Also, it -+ will move them around between input sections' -+ relocation's contents, so our sorting would be -+ broken, so don't let it run. */ -+ info->combreloc = 0; -+ } -+ } -+ else if (s == htab->splt) -+ { -+ } -+ else if (! CONST_STRNEQ (name, ".init") -+ && s != htab->sgot -+ && s != htab->sgotplt -+ && s != htab->sdynbss) -+ { -+ /* It's not one of our sections, so don't allocate space. */ -+ continue; -+ } -+ -+ if (s->size == 0) -+ { -+ s->flags |= SEC_EXCLUDE; -+ continue; -+ } -+ -+ if ((s->flags & SEC_HAS_CONTENTS) == 0) -+ continue; -+ -+ /* Allocate memory for the section contents. */ -+ s->contents = bfd_zalloc (dynobj, s->size); -+ if (s->contents == NULL) -+ { -+ bfd_set_error (bfd_error_no_memory); -+ return FALSE; -+ } -+ } -+ -+ if (elf_hash_table (info)->dynamic_sections_created) -+ { -+ /* Add some entries to the .dynamic section. We fill in the -+ values later, in _bfd_riscv_elf_finish_dynamic_sections, but we -+ must add the entries now so that we get the correct size for -+ the .dynamic section. */ -+ -+ /* The DT_DEBUG entry may be filled in by the dynamic linker and -+ used by the debugger. */ -+ if (info->executable -+ && !_bfd_elf_add_dynamic_entry (info, DT_DEBUG, 0)) -+ return FALSE; -+ -+ if ((info->flags & DF_TEXTREL) != 0) -+ { -+ if (! _bfd_elf_add_dynamic_entry (info, DT_TEXTREL, 0)) -+ return FALSE; -+ -+ /* Clear the DF_TEXTREL flag. It will be set again if we -+ write out an actual text relocation; we may not, because -+ at this point we do not know whether e.g. any .eh_frame -+ absolute relocations have been converted to PC-relative. */ -+ info->flags &= ~DF_TEXTREL; -+ } -+ -+ if (! _bfd_elf_add_dynamic_entry (info, DT_PLTGOT, 0)) -+ return FALSE; -+ -+ sreldyn = mips_elf_rel_dyn_section (info, FALSE); -+ { -+ if (sreldyn && sreldyn->size > 0) -+ { -+ if (! _bfd_elf_add_dynamic_entry (info, DT_REL, 0)) -+ return FALSE; -+ -+ if (! _bfd_elf_add_dynamic_entry (info, DT_RELSZ, 0)) -+ return FALSE; -+ -+ if (! _bfd_elf_add_dynamic_entry (info, DT_RELENT, 0)) -+ return FALSE; -+ } -+ -+ if (! _bfd_elf_add_dynamic_entry (info, DT_RISCV_LOCAL_GOTNO, 0)) -+ return FALSE; -+ -+ if (! _bfd_elf_add_dynamic_entry (info, DT_RISCV_SYMTABNO, 0)) -+ return FALSE; -+ -+ if (! _bfd_elf_add_dynamic_entry (info, DT_RISCV_GOTSYM, 0)) -+ return FALSE; -+ } -+ if (htab->splt->size > 0) -+ { -+ if (! _bfd_elf_add_dynamic_entry (info, DT_PLTREL, 0)) -+ return FALSE; -+ -+ if (! _bfd_elf_add_dynamic_entry (info, DT_JMPREL, 0)) -+ return FALSE; -+ -+ if (! _bfd_elf_add_dynamic_entry (info, DT_PLTRELSZ, 0)) -+ return FALSE; -+ -+ if (! _bfd_elf_add_dynamic_entry (info, DT_RISCV_PLTGOT, 0)) -+ return FALSE; -+ } -+ } -+ -+ return TRUE; -+} -+ -+/* REL is a relocation in INPUT_BFD that is being copied to OUTPUT_BFD. -+ Adjust its R_ADDEND field so that it is correct for the output file. -+ LOCAL_SYMS and LOCAL_SECTIONS are arrays of INPUT_BFD's local symbols -+ and sections respectively; both use symbol indexes. */ -+ -+static void -+mips_elf_adjust_addend (bfd *output_bfd, struct bfd_link_info *info, -+ bfd *input_bfd, Elf_Internal_Sym *local_syms, -+ asection **local_sections, Elf_Internal_Rela *rel) -+{ -+ unsigned int r_symndx; -+ Elf_Internal_Sym *sym; -+ asection *sec; -+ -+ if (mips_elf_local_relocation_p (input_bfd, rel, local_sections)) -+ { -+ r_symndx = ELF_R_SYM (output_bfd, rel->r_info); -+ sym = local_syms + r_symndx; -+ -+ /* Adjust REL's addend to account for section merging. */ -+ if (!info->relocatable) -+ { -+ sec = local_sections[r_symndx]; -+ _bfd_elf_rela_local_sym (output_bfd, sym, &sec, rel); -+ } -+ -+ /* This would normally be done by the rela_normal code in elflink.c. */ -+ if (ELF_ST_TYPE (sym->st_info) == STT_SECTION) -+ rel->r_addend += local_sections[r_symndx]->output_offset; -+ } -+} -+ -+/* Relocate a MIPS ELF section. */ -+ -+bfd_boolean -+_bfd_riscv_elf_relocate_section (bfd *output_bfd, struct bfd_link_info *info, -+ bfd *input_bfd, asection *input_section, -+ bfd_byte *contents, Elf_Internal_Rela *relocs, -+ Elf_Internal_Sym *local_syms, -+ asection **local_sections) -+{ -+ Elf_Internal_Rela *rel; -+ const Elf_Internal_Rela *relend; -+ bfd_vma addend = 0; -+ const struct elf_backend_data *bed; -+ -+ bed = get_elf_backend_data (output_bfd); -+ relend = relocs + input_section->reloc_count * bed->s->int_rels_per_ext_rel; -+ for (rel = relocs; rel < relend; ++rel) -+ { -+ const char *name; -+ bfd_vma value = 0; -+ /* TRUE if the relocation is a RELA relocation, rather than a -+ REL relocation. */ -+ const char *msg; -+ unsigned long r_symndx; -+ asection *sec; -+ Elf_Internal_Shdr *symtab_hdr; -+ struct elf_link_hash_entry *h; -+ unsigned int r_type = ELF_R_TYPE (output_bfd, rel->r_info); -+ reloc_howto_type *howto = riscv_elf_rtype_to_howto (r_type); -+ -+ r_symndx = ELF_R_SYM (input_bfd, rel->r_info); -+ symtab_hdr = &elf_tdata (input_bfd)->symtab_hdr; -+ if (mips_elf_local_relocation_p (input_bfd, rel, local_sections)) -+ { -+ sec = local_sections[r_symndx]; -+ h = NULL; -+ } -+ else -+ { -+ unsigned long extsymoff; -+ -+ extsymoff = 0; -+ if (!elf_bad_symtab (input_bfd)) -+ extsymoff = symtab_hdr->sh_info; -+ h = elf_sym_hashes (input_bfd) [r_symndx - extsymoff]; -+ while (h->root.type == bfd_link_hash_indirect -+ || h->root.type == bfd_link_hash_warning) -+ h = (struct elf_link_hash_entry *) h->root.u.i.link; -+ -+ sec = NULL; -+ if (h->root.type == bfd_link_hash_defined -+ || h->root.type == bfd_link_hash_defweak) -+ sec = h->root.u.def.section; -+ } -+ -+ if (sec != NULL && elf_discarded_section (sec)) -+ RELOC_AGAINST_DISCARDED_SECTION (info, input_bfd, input_section, -+ rel, relend, howto, contents); -+ -+ addend = rel->r_addend; -+ mips_elf_adjust_addend (output_bfd, info, input_bfd, -+ local_syms, local_sections, rel); -+ -+ if (info->relocatable) -+ /* Go on to the next relocation. */ -+ continue; -+ -+ /* Figure out what value we are supposed to relocate. */ -+ switch (mips_elf_calculate_relocation (output_bfd, input_bfd, -+ input_section, info, rel, -+ addend, howto, local_syms, -+ local_sections, &value, &name, -+ contents)) -+ { -+ case bfd_reloc_continue: -+ /* There's nothing to do. */ -+ continue; -+ -+ case bfd_reloc_undefined: -+ /* mips_elf_calculate_relocation already called the -+ undefined_symbol callback. There's no real point in -+ trying to perform the relocation at this point, so we -+ just skip ahead to the next relocation. */ -+ continue; -+ -+ case bfd_reloc_notsupported: -+ msg = _("internal error: unsupported relocation error"); -+ info->callbacks->warning -+ (info, msg, name, input_bfd, input_section, rel->r_offset); -+ return FALSE; -+ -+ case bfd_reloc_overflow: -+ BFD_ASSERT (name != NULL); -+ if (! ((*info->callbacks->reloc_overflow) -+ (info, NULL, name, howto->name, (bfd_vma) 0, -+ input_bfd, input_section, rel->r_offset))) -+ return FALSE; -+ break; -+ -+ case bfd_reloc_ok: -+ break; -+ -+ default: -+ abort (); -+ break; -+ } -+ -+ /* Actually perform the relocation. */ -+ if (! mips_elf_perform_relocation (info, howto, rel, value, -+ input_bfd, input_section, -+ contents)) -+ return FALSE; -+ } -+ -+ return TRUE; -+} -+ -+/* Finish up dynamic symbol handling. We set the contents of various -+ dynamic sections here. */ -+ -+bfd_boolean -+_bfd_riscv_elf_finish_dynamic_symbol (bfd *output_bfd, -+ struct bfd_link_info *info, -+ struct elf_link_hash_entry *h, -+ Elf_Internal_Sym *sym) -+{ -+ bfd *dynobj; -+ asection *sgot; -+ struct mips_got_info *g; -+ const char *name; -+ struct mips_elf_link_hash_table *htab; -+ struct mips_elf_link_hash_entry *hmips; -+ -+ htab = mips_elf_hash_table (info); -+ BFD_ASSERT (htab != NULL); -+ dynobj = elf_hash_table (info)->dynobj; -+ hmips = (struct mips_elf_link_hash_entry *) h; -+ -+ if (h->plt.offset != MINUS_ONE) -+ { -+ /* We've decided to create a PLT entry for this symbol. */ -+ bfd_byte *loc; -+ bfd_vma i, header_address, plt_index, got_address, got_val; -+ uint32_t plt_entry[PLT_ENTRY_INSNS]; -+ -+ BFD_ASSERT (h->dynindx != -1); -+ BFD_ASSERT (htab->splt != NULL); -+ BFD_ASSERT (h->plt.offset <= htab->splt->size); -+ -+ /* Calculate the address of the PLT header. */ -+ header_address = sec_addr(htab->splt); -+ -+ /* Calculate the index of the entry. */ -+ plt_index = (h->plt.offset - PLT_HEADER_SIZE) / PLT_ENTRY_SIZE; -+ -+ /* Calculate the address of the .got.plt entry. */ -+ got_address = riscv_elf_got_plt_val (plt_index, info); -+ -+ /* Find out where the .plt entry should go. */ -+ loc = htab->splt->contents + h->plt.offset; -+ -+ /* Fill in the PLT entry itself. */ -+ got_val = riscv_make_plt_entry (output_bfd, got_address, header_address, -+ header_address + h->plt.offset, -+ plt_entry); -+ for (i = 0; i < PLT_ENTRY_INSNS; i++) -+ bfd_put_32 (output_bfd, plt_entry[i], loc + 4*i); -+ -+ /* Fill in the initial value of the .got.plt entry. */ -+ loc = htab->sgotplt->contents + (got_address - sec_addr(htab->sgotplt)); -+ MIPS_ELF_PUT_WORD (output_bfd, got_val, loc); -+ -+ /* Emit an R_RISCV_JUMP_SLOT relocation against the .got.plt entry. */ -+ mips_elf_output_dynamic_relocation (output_bfd, htab->srelplt, -+ plt_index, h->dynindx, -+ R_RISCV_JUMP_SLOT, got_address); -+ -+ if (!h->def_regular) -+ sym->st_shndx = SHN_UNDEF; -+ } -+ -+ BFD_ASSERT (h->dynindx != -1 -+ || h->forced_local); -+ -+ sgot = htab->sgot; -+ g = htab->got_info; -+ BFD_ASSERT (g != NULL); -+ -+ /* Run through the global symbol table, creating GOT entries for all -+ the symbols that need them. */ -+ if (hmips->global_got_area != GGA_NONE) -+ { -+ bfd_vma offset; -+ bfd_vma value; -+ -+ value = sym->st_value; -+ offset = mips_elf_global_got_index (dynobj, h, R_RISCV_GOT_HI20, info); -+ MIPS_ELF_PUT_WORD (output_bfd, value, sgot->contents + offset); -+ } -+ -+ /* Mark _DYNAMIC and _GLOBAL_OFFSET_TABLE_ as absolute. */ -+ name = h->root.root.string; -+ if (strcmp (name, "_DYNAMIC") == 0 -+ || h == elf_hash_table (info)->hgot) -+ sym->st_shndx = SHN_ABS; -+ else if (strcmp (name, "_DYNAMIC_LINKING") == 0) -+ { -+ sym->st_shndx = SHN_ABS; -+ sym->st_info = ELF_ST_INFO (STB_GLOBAL, STT_SECTION); -+ sym->st_value = 1; -+ } -+ -+ /* Emit a copy reloc, if needed. */ -+ if (h->needs_copy) -+ { -+ asection *s; -+ bfd_vma symval; -+ -+ BFD_ASSERT (h->dynindx != -1); -+ -+ s = mips_elf_rel_dyn_section (info, FALSE); -+ symval = sec_addr(h->root.u.def.section) + h->root.u.def.value; -+ mips_elf_output_dynamic_relocation (output_bfd, s, s->reloc_count++, -+ h->dynindx, R_RISCV_COPY, symval); -+ } -+ -+ return TRUE; -+} -+ -+/* Write out a plt0 entry to the beginning of .plt. */ -+ -+static void -+mips_finish_exec_plt (bfd *output_bfd, struct bfd_link_info *info) -+{ -+ bfd_byte *loc; -+ uint32_t plt_entry[PLT_HEADER_INSNS]; -+ struct mips_elf_link_hash_table *htab; -+ int i; -+ -+ htab = mips_elf_hash_table (info); -+ BFD_ASSERT (htab != NULL); -+ -+ /* Install the PLT header. */ -+ loc = htab->splt->contents; -+ riscv_make_plt0_entry (output_bfd, sec_addr(htab->sgotplt), -+ sec_addr(htab->splt), plt_entry); -+ for (i = 0; i < PLT_HEADER_INSNS; i++) -+ bfd_put_32 (output_bfd, plt_entry[i], loc + 4*i); -+} -+ -+/* Finish up the dynamic sections. */ -+ -+bfd_boolean -+_bfd_riscv_elf_finish_dynamic_sections (bfd *output_bfd, -+ struct bfd_link_info *info) -+{ -+ bfd *dynobj; -+ asection *sdyn; -+ asection *sgot; -+ struct mips_got_info *gg, *g; -+ struct mips_elf_link_hash_table *htab; -+ -+ htab = mips_elf_hash_table (info); -+ BFD_ASSERT (htab != NULL); -+ -+ dynobj = elf_hash_table (info)->dynobj; -+ -+ sdyn = bfd_get_section_by_name (dynobj, ".dynamic"); -+ -+ sgot = htab->sgot; -+ g = gg = htab->got_info; -+ -+ if (elf_hash_table (info)->dynamic_sections_created) -+ { -+ bfd_byte *b; -+ int dyn_to_skip = 0, dyn_skipped = 0; -+ -+ BFD_ASSERT (sdyn != NULL); -+ BFD_ASSERT (gg != NULL); -+ -+ for (b = sdyn->contents; -+ b < sdyn->contents + sdyn->size; -+ b += MIPS_ELF_DYN_SIZE (dynobj)) -+ { -+ Elf_Internal_Dyn dyn; -+ const char *name; -+ size_t elemsize; -+ asection *s; -+ bfd_boolean swap_out_p; -+ -+ /* Read in the current dynamic entry. */ -+ (*get_elf_backend_data (dynobj)->s->swap_dyn_in) (dynobj, b, &dyn); -+ -+ /* Assume that we're going to modify it and write it out. */ -+ swap_out_p = TRUE; -+ -+ switch (dyn.d_tag) -+ { -+ case DT_RELENT: -+ dyn.d_un.d_val = MIPS_ELF_REL_SIZE (dynobj); -+ break; -+ -+ case DT_STRSZ: -+ /* Rewrite DT_STRSZ. */ -+ dyn.d_un.d_val = -+ _bfd_elf_strtab_size (elf_hash_table (info)->dynstr); -+ break; -+ -+ case DT_PLTGOT: -+ dyn.d_un.d_ptr = sec_addr(htab->sgot); -+ break; -+ -+ case DT_RISCV_PLTGOT: -+ dyn.d_un.d_ptr = sec_addr(htab->sgotplt); -+ break; -+ -+ case DT_RISCV_LOCAL_GOTNO: -+ dyn.d_un.d_val = g->local_gotno; -+ break; -+ -+ case DT_RISCV_GOTSYM: -+ if (gg->global_gotsym) -+ { -+ dyn.d_un.d_val = gg->global_gotsym->dynindx; -+ break; -+ } -+ /* In case if we don't have global got symbols we default -+ to setting DT_RISCV_GOTSYM to the same value as -+ DT_RISCV_SYMTABNO, so we just fall through. */ -+ -+ case DT_RISCV_SYMTABNO: -+ name = ".dynsym"; -+ elemsize = MIPS_ELF_SYM_SIZE (output_bfd); -+ s = bfd_get_section_by_name (output_bfd, name); -+ BFD_ASSERT (s != NULL); -+ -+ dyn.d_un.d_val = s->size / elemsize; -+ break; -+ -+ case DT_PLTREL: -+ dyn.d_un.d_val = DT_REL; -+ break; -+ -+ case DT_PLTRELSZ: -+ dyn.d_un.d_val = htab->srelplt->size; -+ break; -+ -+ case DT_JMPREL: -+ dyn.d_un.d_ptr = sec_addr(htab->srelplt); -+ break; -+ -+ case DT_TEXTREL: -+ /* If we didn't need any text relocations after all, delete -+ the dynamic tag. */ -+ if (!(info->flags & DF_TEXTREL)) -+ { -+ dyn_to_skip = MIPS_ELF_DYN_SIZE (dynobj); -+ swap_out_p = FALSE; -+ } -+ break; -+ -+ case DT_FLAGS: -+ /* If we didn't need any text relocations after all, clear -+ DF_TEXTREL from DT_FLAGS. */ -+ if (!(info->flags & DF_TEXTREL)) -+ dyn.d_un.d_val &= ~DF_TEXTREL; -+ else -+ swap_out_p = FALSE; -+ break; -+ -+ default: -+ swap_out_p = FALSE; -+ break; -+ } -+ -+ if (swap_out_p || dyn_skipped) -+ (*get_elf_backend_data (dynobj)->s->swap_dyn_out) -+ (dynobj, &dyn, b - dyn_skipped); -+ -+ if (dyn_to_skip) -+ { -+ dyn_skipped += dyn_to_skip; -+ dyn_to_skip = 0; -+ } -+ } -+ -+ /* Wipe out any trailing entries if we shifted down a dynamic tag. */ -+ if (dyn_skipped > 0) -+ memset (b - dyn_skipped, 0, dyn_skipped); -+ } -+ -+ if (sgot != NULL && sgot->size > 0 -+ && !bfd_is_abs_section (sgot->output_section)) -+ { -+ /* The first two entries of the GOT will be filled at runtime. */ -+ MIPS_ELF_PUT_WORD (output_bfd, (bfd_vma) 0, sgot->contents); -+ MIPS_ELF_PUT_WORD (output_bfd, (bfd_vma) 0, -+ sgot->contents + MIPS_ELF_GOT_SIZE (output_bfd)); -+ -+ elf_section_data (sgot->output_section)->this_hdr.sh_entsize -+ = MIPS_ELF_GOT_SIZE (output_bfd); -+ } -+ -+ /* The generation of dynamic relocations for the non-primary gots -+ adds more dynamic relocations. We cannot count them until -+ here. */ -+ -+ if (elf_hash_table (info)->dynamic_sections_created) -+ { -+ bfd_byte *b; -+ bfd_boolean swap_out_p; -+ -+ BFD_ASSERT (sdyn != NULL); -+ -+ for (b = sdyn->contents; -+ b < sdyn->contents + sdyn->size; -+ b += MIPS_ELF_DYN_SIZE (dynobj)) -+ { -+ Elf_Internal_Dyn dyn; -+ asection *s; -+ -+ /* Read in the current dynamic entry. */ -+ (*get_elf_backend_data (dynobj)->s->swap_dyn_in) (dynobj, b, &dyn); -+ -+ /* Assume that we're going to modify it and write it out. */ -+ swap_out_p = TRUE; -+ -+ switch (dyn.d_tag) -+ { -+ case DT_RELSZ: -+ /* Reduce DT_RELSZ to account for any relocations we -+ decided not to make. This is for the n64 irix rld, -+ which doesn't seem to apply any relocations if there -+ are trailing null entries. */ -+ s = mips_elf_rel_dyn_section (info, FALSE); -+ dyn.d_un.d_val = (s->reloc_count -+ * (ABI_64_P (output_bfd) -+ ? sizeof (Elf64_External_Rel) -+ : sizeof (Elf32_External_Rel))); -+ /* Adjust the section size too. Tools like the prelinker -+ can reasonably expect the values to the same. */ -+ elf_section_data (s->output_section)->this_hdr.sh_size -+ = dyn.d_un.d_val; -+ break; -+ -+ default: -+ swap_out_p = FALSE; -+ break; -+ } -+ -+ if (swap_out_p) -+ (*get_elf_backend_data (dynobj)->s->swap_dyn_out) -+ (dynobj, &dyn, b); -+ } -+ } -+ -+ { -+ asection *s; -+ -+ /* The psABI says that the dynamic relocations must be sorted in -+ increasing order of r_symndx. */ -+ s = mips_elf_rel_dyn_section (info, FALSE); -+ if (s != NULL && s->size > (bfd_vma)2 * MIPS_ELF_REL_SIZE (output_bfd)) -+ { -+ reldyn_sorting_bfd = output_bfd; -+ -+ if (ABI_64_P (output_bfd)) -+ qsort ((Elf64_External_Rel *) s->contents + 1, -+ s->reloc_count - 1, sizeof (Elf64_External_Rel), -+ sort_dynamic_relocs_64); -+ else -+ qsort ((Elf32_External_Rel *) s->contents + 1, -+ s->reloc_count - 1, sizeof (Elf32_External_Rel), -+ sort_dynamic_relocs); -+ } -+ } -+ -+ if (htab->splt && htab->splt->size > 0) -+ mips_finish_exec_plt (output_bfd, info); -+ return TRUE; -+} -+ -+int -+_bfd_riscv_elf_additional_program_headers (bfd *abfd, -+ struct bfd_link_info *info ATTRIBUTE_UNUSED) -+{ -+ /* Allocate a PT_NULL header in dynamic objects. See -+ _bfd_riscv_elf_modify_segment_map for details. */ -+ if (bfd_get_section_by_name (abfd, ".dynamic")) -+ return 1; -+ return 0; -+} -+ -+/* Modify the segment map for an IRIX5 executable. */ -+ -+bfd_boolean -+_bfd_riscv_elf_modify_segment_map (bfd *abfd, -+ struct bfd_link_info *info) -+{ -+ struct elf_segment_map *m, **pm; -+ -+ { -+ /* On IRIX5, the PT_DYNAMIC segment includes the .dynamic, -+ .dynstr, .dynsym, and .hash sections, and everything in -+ between. */ -+ for (pm = &elf_tdata (abfd)->segment_map; *pm != NULL; -+ pm = &(*pm)->next) -+ if ((*pm)->p_type == PT_DYNAMIC) -+ break; -+ m = *pm; -+ if (m != NULL) -+ { -+ /* For a normal mips executable the permissions for the PT_DYNAMIC -+ segment are read, write and execute. We do that here since -+ the code in elf.c sets only the read permission. This matters -+ sometimes for the dynamic linker. */ -+ if (bfd_get_section_by_name (abfd, ".dynamic") != NULL) -+ { -+ m->p_flags = PF_R | PF_W | PF_X; -+ m->p_flags_valid = 1; -+ } -+ } -+ } -+ -+ /* Allocate a spare program header in dynamic objects so that tools -+ like the prelinker can add an extra PT_LOAD entry. -+ -+ If the prelinker needs to make room for a new PT_LOAD entry, its -+ standard procedure is to move the first (read-only) sections into -+ the new (writable) segment. However, the MIPS ABI requires -+ .dynamic to be in a read-only segment, and the section will often -+ start within sizeof (ElfNN_Phdr) bytes of the last program header. -+ -+ Although the prelinker could in principle move .dynamic to a -+ writable segment, it seems better to allocate a spare program -+ header instead, and avoid the need to move any sections. -+ There is a long tradition of allocating spare dynamic tags, -+ so allocating a spare program header seems like a natural -+ extension. -+ -+ If INFO is NULL, we may be copying an already prelinked binary -+ with objcopy or strip, so do not add this header. */ -+ if (info != NULL -+ && bfd_get_section_by_name (abfd, ".dynamic")) -+ { -+ for (pm = &elf_tdata (abfd)->segment_map; *pm != NULL; pm = &(*pm)->next) -+ if ((*pm)->p_type == PT_NULL) -+ break; -+ if (*pm == NULL) -+ { -+ m = bfd_zalloc (abfd, sizeof (*m)); -+ if (m == NULL) -+ return FALSE; -+ -+ m->p_type = PT_NULL; -+ *pm = m; -+ } -+ } -+ -+ return TRUE; -+} -+ -+/* Copy data from a MIPS ELF indirect symbol to its direct symbol, -+ hiding the old indirect symbol. Process additional relocation -+ information. Also called for weakdefs, in which case we just let -+ _bfd_elf_link_hash_copy_indirect copy the flags for us. */ -+ -+void -+_bfd_riscv_elf_copy_indirect_symbol (struct bfd_link_info *info, -+ struct elf_link_hash_entry *dir, -+ struct elf_link_hash_entry *ind) -+{ -+ struct mips_elf_link_hash_entry *dirmips, *indmips; -+ -+ _bfd_elf_link_hash_copy_indirect (info, dir, ind); -+ -+ dirmips = (struct mips_elf_link_hash_entry *) dir; -+ indmips = (struct mips_elf_link_hash_entry *) ind; -+ /* Any absolute non-dynamic relocations against an indirect or weak -+ definition will be against the target symbol. */ -+ if (indmips->has_static_relocs) -+ dirmips->has_static_relocs = TRUE; -+ -+ if (ind->root.type != bfd_link_hash_indirect) -+ return; -+ -+ dirmips->possibly_dynamic_relocs += indmips->possibly_dynamic_relocs; -+ if (indmips->readonly_reloc) -+ dirmips->readonly_reloc = TRUE; -+ if (indmips->global_got_area < dirmips->global_got_area) -+ dirmips->global_got_area = indmips->global_got_area; -+ if (indmips->global_got_area < GGA_NONE) -+ indmips->global_got_area = GGA_NONE; -+ -+ if (dirmips->tls_type == 0) -+ dirmips->tls_type = indmips->tls_type; -+} -+ -+#define PDR_SIZE 32 -+ -+bfd_boolean -+_bfd_riscv_elf_discard_info (bfd *abfd, struct elf_reloc_cookie *cookie, -+ struct bfd_link_info *info) -+{ -+ asection *o; -+ bfd_boolean ret = FALSE; -+ unsigned char *tdata; -+ size_t i, skip; -+ -+ o = bfd_get_section_by_name (abfd, ".pdr"); -+ if (! o) -+ return FALSE; -+ if (o->size == 0) -+ return FALSE; -+ if (o->size % PDR_SIZE != 0) -+ return FALSE; -+ if (o->output_section != NULL -+ && bfd_is_abs_section (o->output_section)) -+ return FALSE; -+ -+ tdata = bfd_zmalloc (o->size / PDR_SIZE); -+ if (! tdata) -+ return FALSE; -+ -+ cookie->rels = _bfd_elf_link_read_relocs (abfd, o, NULL, NULL, -+ info->keep_memory); -+ if (!cookie->rels) -+ { -+ free (tdata); -+ return FALSE; -+ } -+ -+ cookie->rel = cookie->rels; -+ cookie->relend = cookie->rels + o->reloc_count; -+ -+ for (i = 0, skip = 0; i < o->size / PDR_SIZE; i ++) -+ { -+ if (bfd_elf_reloc_symbol_deleted_p (i * PDR_SIZE, cookie)) -+ { -+ tdata[i] = 1; -+ skip ++; -+ } -+ } -+ -+ if (skip != 0) -+ { -+ mips_elf_section_data (o)->u.tdata = tdata; -+ o->size -= skip * PDR_SIZE; -+ ret = TRUE; -+ } -+ else -+ free (tdata); -+ -+ if (! info->keep_memory) -+ free (cookie->rels); -+ -+ return ret; -+} -+ -+bfd_boolean -+_bfd_riscv_elf_ignore_discarded_relocs (asection *sec) -+{ -+ if (strcmp (sec->name, ".pdr") == 0) -+ return TRUE; -+ return FALSE; -+} -+ -+bfd_boolean -+_bfd_riscv_elf_write_section (bfd *output_bfd, -+ struct bfd_link_info *link_info ATTRIBUTE_UNUSED, -+ asection *sec, bfd_byte *contents) -+{ -+ bfd_byte *to, *from, *end; -+ int i; -+ -+ if (strcmp (sec->name, ".pdr") != 0) -+ return FALSE; -+ -+ if (mips_elf_section_data (sec)->u.tdata == NULL) -+ return FALSE; -+ -+ to = contents; -+ end = contents + sec->size; -+ for (from = contents, i = 0; -+ from < end; -+ from += PDR_SIZE, i++) -+ { -+ if ((mips_elf_section_data (sec)->u.tdata)[i] == 1) -+ continue; -+ if (to != from) -+ memcpy (to, from, PDR_SIZE); -+ to += PDR_SIZE; -+ } -+ bfd_set_section_contents (output_bfd, sec->output_section, contents, -+ sec->output_offset, sec->size); -+ return TRUE; -+} -+ -+/* Create a MIPS ELF linker hash table. */ -+ -+struct bfd_link_hash_table * -+_bfd_riscv_elf_link_hash_table_create (bfd *abfd) -+{ -+ struct mips_elf_link_hash_table *ret; -+ bfd_size_type amt = sizeof (struct mips_elf_link_hash_table); -+ -+ ret = bfd_malloc (amt); -+ if (ret == NULL) -+ return NULL; -+ -+ if (!_bfd_elf_link_hash_table_init (&ret->root, abfd, -+ mips_elf_link_hash_newfunc, -+ sizeof (struct mips_elf_link_hash_entry), -+ MIPS_ELF_DATA)) -+ { -+ free (ret); -+ return NULL; -+ } -+ -+ ret->srelbss = NULL; -+ ret->sdynbss = NULL; -+ ret->srelplt = NULL; -+ ret->srelplt2 = NULL; -+ ret->sgotplt = NULL; -+ ret->splt = NULL; -+ ret->sgot = NULL; -+ ret->got_info = NULL; -+ ret->nplt = 0; -+ -+ return &ret->root.root; -+} -+ -+/* We need to use a special link routine to handle the .reginfo and -+ the .mdebug sections. We need to merge all instances of these -+ sections together, not write them all out sequentially. */ -+ -+bfd_boolean -+_bfd_riscv_elf_final_link (bfd *abfd, struct bfd_link_info *info) -+{ -+ struct mips_elf_link_hash_table *htab; -+ -+ bfd_riscv_init_gp_value (abfd, info); -+ /* Sort the dynamic symbols so that those with GOT entries come after -+ those without. */ -+ htab = mips_elf_hash_table (info); -+ BFD_ASSERT (htab != NULL); -+ -+ if (!mips_elf_sort_hash_table (abfd, info)) -+ return FALSE; -+ -+ /* Invoke the regular ELF backend linker to do all the work. */ -+ return bfd_elf_final_link (abfd, info); -+} -+ -+/* Return true if bfd machine EXTENSION is an extension of machine BASE. */ -+ -+static bfd_boolean -+mips_mach_extends_p (unsigned long base, unsigned long extension) -+{ -+ return extension == base; -+} -+ -+/* Merge backend specific data from an object file to the output -+ object file when linking. */ -+ -+bfd_boolean -+_bfd_riscv_elf_merge_private_bfd_data (bfd *ibfd, bfd *obfd) -+{ -+ flagword old_flags; -+ flagword new_flags; -+ bfd_boolean ok; -+ bfd_boolean null_input_bfd = TRUE; -+ asection *sec; -+ -+ /* Check if we have the same endianess */ -+ if (! _bfd_generic_verify_endian_match (ibfd, obfd)) -+ { -+ (*_bfd_error_handler) -+ (_("%B: endianness incompatible with that of the selected emulation"), -+ ibfd); -+ return FALSE; -+ } -+ -+ if (!is_mips_elf (ibfd) || !is_mips_elf (obfd)) -+ return TRUE; -+ -+ if (strcmp (bfd_get_target (ibfd), bfd_get_target (obfd)) != 0) -+ { -+ (*_bfd_error_handler) -+ (_("%B: ABI is incompatible with that of the selected emulation"), -+ ibfd); -+ return FALSE; -+ } -+ -+ if (!_bfd_elf_merge_object_attributes (ibfd, obfd)) -+ return FALSE; -+ -+ new_flags = elf_elfheader (ibfd)->e_flags; -+ old_flags = elf_elfheader (obfd)->e_flags; -+ -+ if (! elf_flags_init (obfd)) -+ { -+ elf_flags_init (obfd) = TRUE; -+ elf_elfheader (obfd)->e_flags = new_flags; -+ elf_elfheader (obfd)->e_ident[EI_CLASS] -+ = elf_elfheader (ibfd)->e_ident[EI_CLASS]; -+ -+ if (bfd_get_arch (obfd) == bfd_get_arch (ibfd) -+ && (bfd_get_arch_info (obfd)->the_default -+ || mips_mach_extends_p (bfd_get_mach (obfd), -+ bfd_get_mach (ibfd)))) -+ { -+ if (! bfd_set_arch_mach (obfd, bfd_get_arch (ibfd), -+ bfd_get_mach (ibfd))) -+ return FALSE; -+ } -+ -+ return TRUE; -+ } -+ -+ /* Check flag compatibility. */ -+ -+ if (new_flags == old_flags) -+ return TRUE; -+ -+ /* Check to see if the input BFD actually contains any sections. -+ If not, its flags may not have been initialised either, but it cannot -+ actually cause any incompatibility. */ -+ for (sec = ibfd->sections; sec != NULL; sec = sec->next) -+ { -+ /* Ignore synthetic sections and empty .text, .data and .bss sections -+ which are automatically generated by gas. Also ignore fake -+ (s)common sections, since merely defining a common symbol does -+ not affect compatibility. */ -+ if ((sec->flags & SEC_IS_COMMON) == 0 -+ && (sec->size != 0 -+ || (strcmp (sec->name, ".text") -+ && strcmp (sec->name, ".data") -+ && strcmp (sec->name, ".bss")))) -+ { -+ null_input_bfd = FALSE; -+ break; -+ } -+ } -+ if (null_input_bfd) -+ return TRUE; -+ -+ ok = TRUE; -+ -+ /* Don't link RV32 and RV64. */ -+ if (elf_elfheader (ibfd)->e_ident[EI_CLASS] -+ != elf_elfheader (obfd)->e_ident[EI_CLASS]) -+ { -+ (*_bfd_error_handler) -+ (_("%B: ABI mismatch: linking %s module with previous %s modules"), -+ ibfd, -+ elf_mips_abi_name (ibfd), -+ elf_mips_abi_name (obfd)); -+ ok = FALSE; -+ } -+ -+ /* Warn about any other mismatches */ -+ if (new_flags != old_flags) -+ { -+ if (!EF_IS_RISCV_EXT_Xcustom(new_flags) && -+ !EF_IS_RISCV_EXT_Xcustom(old_flags)) { -+ (*_bfd_error_handler) -+ (_("%B: uses different e_flags (0x%lx) fields than previous modules (0x%lx)"), -+ ibfd, (unsigned long) new_flags, -+ (unsigned long) old_flags); -+ ok = FALSE; -+ } else if (EF_IS_RISCV_EXT_Xcustom(new_flags)) { -+ EF_SET_RISCV_EXT(elf_elfheader (obfd)->e_flags, EF_GET_RISCV_EXT(old_flags)); -+ } -+ } -+ -+ if (! ok) -+ { -+ bfd_set_error (bfd_error_bad_value); -+ return FALSE; -+ } -+ -+ return TRUE; -+} -+ -+char * -+_bfd_riscv_elf_get_target_dtag (bfd_vma dtag) -+{ -+ switch (dtag) -+ { -+ case DT_RISCV_LOCAL_GOTNO: -+ return "MIPS_LOCAL_GOTNO"; -+ case DT_RISCV_SYMTABNO: -+ return "MIPS_SYMTABNO"; -+ case DT_RISCV_GOTSYM: -+ return "MIPS_GOTSYM"; -+ case DT_RISCV_PLTGOT: -+ return "DT_RISCV_PLTGOT"; -+ default: -+ return ""; -+ } -+} -+ -+bfd_boolean -+_bfd_riscv_elf_print_private_bfd_data (bfd *abfd, void *ptr) -+{ -+ FILE *file = ptr; -+ -+ BFD_ASSERT (abfd != NULL && ptr != NULL); -+ -+ /* Print normal ELF private data. */ -+ _bfd_elf_print_private_bfd_data (abfd, ptr); -+ -+ /* xgettext:c-format */ -+ fprintf (file, _("private flags = %lx:"), elf_elfheader (abfd)->e_flags); -+ -+ if (ABI_32_P (abfd)) -+ fprintf (file, _(" [rv32]")); -+ else if (ABI_64_P (abfd)) -+ fprintf (file, _(" [rv64]")); -+ else -+ fprintf (file, _(" [no abi set]")); -+ -+ fputc ('\n', file); -+ -+ return TRUE; -+} -+ -+const struct bfd_elf_special_section _bfd_riscv_elf_special_sections[] = -+{ -+ { NULL, 0, 0, 0, 0 } -+}; -+ -+/* Merge non visibility st_other attributes. Ensure that the -+ STO_OPTIONAL flag is copied into h->other, even if this is not a -+ definiton of the symbol. */ -+void -+_bfd_riscv_elf_merge_symbol_attribute (struct elf_link_hash_entry *h, -+ const Elf_Internal_Sym *isym, -+ bfd_boolean definition, -+ bfd_boolean dynamic ATTRIBUTE_UNUSED) -+{ -+ if ((isym->st_other & ~ELF_ST_VISIBILITY (-1)) != 0) -+ { -+ unsigned char other; -+ -+ other = (definition ? isym->st_other : h->other); -+ other &= ~ELF_ST_VISIBILITY (-1); -+ h->other = other | ELF_ST_VISIBILITY (h->other); -+ } -+} -+ -+bfd_boolean -+_bfd_riscv_elf_common_definition (Elf_Internal_Sym *sym) -+{ -+ return (sym->st_shndx == SHN_COMMON); -+} -+ -+/* Delete some bytes from a section while relaxing. */ -+ -+static bfd_boolean -+riscv_relax_delete_bytes (bfd *abfd, asection *sec, bfd_vma addr, size_t count) -+{ -+ Elf_Internal_Shdr * symtab_hdr; -+ unsigned int sec_shndx; -+ bfd_byte * contents; -+ Elf_Internal_Rela * irel; -+ Elf_Internal_Rela * irelend; -+ Elf_Internal_Sym * isym; -+ Elf_Internal_Sym * isymend; -+ bfd_vma toaddr; -+ unsigned int symcount; -+ struct elf_link_hash_entry ** sym_hashes; -+ struct elf_link_hash_entry ** end_hashes; -+ -+ /* TODO: handle alignment */ -+ Elf_Internal_Rela *alignment_rel = NULL; -+ -+ sec_shndx = _bfd_elf_section_from_bfd_section (abfd, sec); -+ -+ contents = elf_section_data (sec)->this_hdr.contents; -+ -+ /* The deletion must stop at the next alignment boundary, if -+ ALIGNMENT_REL is non-NULL. */ -+ toaddr = sec->size; -+ if (alignment_rel) -+ toaddr = alignment_rel->r_offset; -+ -+ irel = elf_section_data (sec)->relocs; -+ irelend = irel + sec->reloc_count; -+ -+ /* Actually delete the bytes. */ -+ memmove (contents + addr, contents + addr + count, -+ (size_t) (toaddr - addr - count)); -+ -+ if (alignment_rel) -+ { -+ size_t i; -+ BFD_ASSERT (count % 4 == 0); -+ for (i = 0; i < count; i += 4) -+ bfd_put_32 (abfd, RISCV_NOP, contents + toaddr - count + i); -+ /* TODO: RVC NOP if count % 4 == 2 */ -+ } -+ else -+ sec->size -= count; -+ -+ /* Adjust all the relocs. */ -+ for (irel = elf_section_data (sec)->relocs; irel < irelend; irel++) -+ { -+ if (irel->r_offset <= addr) -+ { -+ if (irel->r_offset + irel->r_addend > addr) -+ irel->r_addend -= ELF_R_SYM (abfd, irel->r_info) ? 0 : count; -+ } -+ else -+ { -+ if (irel->r_offset + irel->r_addend <= addr) -+ irel->r_addend += ELF_R_SYM (abfd, irel->r_info) ? 0 : count; -+ if (irel->r_offset < toaddr) -+ irel->r_offset -= count; -+ } -+ } -+ -+ /* Adjust the local symbols defined in this section. */ -+ symtab_hdr = &elf_tdata (abfd)->symtab_hdr; -+ isym = (Elf_Internal_Sym *) symtab_hdr->contents; -+ isymend = isym + symtab_hdr->sh_info; -+ -+ for (; isym < isymend; isym++) -+ { -+ /* If the symbol is in the range of memory we just moved, we -+ have to adjust its value. */ -+ if (isym->st_shndx == sec_shndx -+ && isym->st_value > addr -+ && isym->st_value <= toaddr) -+ isym->st_value -= count; -+ -+ /* If the symbol *spans* the bytes we just deleted (i.e. its -+ *end* is in the moved bytes but its *start* isn't), then we -+ must adjust its size. */ -+ if (isym->st_shndx == sec_shndx -+ && isym->st_value < addr -+ && isym->st_value + isym->st_size > addr -+ && isym->st_value + isym->st_size <= toaddr) -+ isym->st_size -= count; -+ } -+ -+ /* Now adjust the global symbols defined in this section. */ -+ symcount = symtab_hdr->sh_size / sizeof(Elf64_External_Sym); -+ if (!ABI_64_P (abfd)) -+ symcount = symtab_hdr->sh_size / sizeof(Elf32_External_Sym); -+ symcount -= symtab_hdr->sh_info; -+ -+ sym_hashes = elf_sym_hashes (abfd); -+ end_hashes = sym_hashes + symcount; -+ -+ for (; sym_hashes < end_hashes; sym_hashes++) -+ { -+ struct elf_link_hash_entry *sym_hash = *sym_hashes; -+ -+ if ((sym_hash->root.type == bfd_link_hash_defined -+ || sym_hash->root.type == bfd_link_hash_defweak) -+ && sym_hash->root.u.def.section == sec) -+ { -+ /* As above, adjust the value if needed. */ -+ if (sym_hash->root.u.def.value > addr -+ && sym_hash->root.u.def.value < toaddr) -+ sym_hash->root.u.def.value -= count; -+ -+ /* As above, adjust the size if needed. */ -+ if (sym_hash->root.u.def.value < addr -+ && sym_hash->root.u.def.value + sym_hash->size > addr -+ && sym_hash->root.u.def.value + sym_hash->size < toaddr) -+ sym_hash->size -= count; -+ } -+ } -+ -+ return TRUE; -+} -+ -+static bfd_boolean -+_bfd_riscv_relax_call (bfd *abfd, asection *sec, -+ struct bfd_link_info *link_info, bfd_byte *contents, -+ Elf_Internal_Shdr *symtab_hdr, -+ Elf_Internal_Sym *isymbuf, -+ Elf_Internal_Rela *internal_relocs, -+ Elf_Internal_Rela *irel, bfd_vma symval, -+ bfd_boolean *again) -+{ -+ /* See if this function call can be shortened. */ -+ bfd_signed_vma foff = symval - (sec_addr(sec) + irel->r_offset); -+ bfd_boolean near_zero = !link_info->shared && symval < RISCV_IMM_REACH/2; -+ if (!VALID_UJTYPE_IMM (foff) && !near_zero) -+ return TRUE; -+ -+ /* Shorten the function call. */ -+ elf_section_data (sec)->relocs = internal_relocs; -+ elf_section_data (sec)->this_hdr.contents = contents; -+ symtab_hdr->contents = (unsigned char *) isymbuf; -+ -+ BFD_ASSERT (irel->r_offset + 8 <= sec->size); -+ -+ bfd_vma auipc = bfd_get_32 (abfd, contents + irel->r_offset); -+ BFD_ASSERT ((auipc & MASK_AUIPC) == MATCH_AUIPC); -+ -+ bfd_vma jalr = bfd_get_32 (abfd, contents + irel->r_offset + 4); -+ BFD_ASSERT ((jalr & MASK_JALR) == MATCH_JALR); -+ /* Replace the R_RISCV_CALL reloc with R_RISCV_JAL. */ -+ irel->r_info = ELF_R_INFO (abfd, ELF_R_SYM (abfd, irel->r_info), R_RISCV_JAL); -+ /* Overwrite AUIPC with JAL rd, addr. */ -+ auipc = (jalr & (OP_MASK_RD << OP_SH_RD)) | MATCH_JAL; -+ bfd_put_32 (abfd, auipc, contents + irel->r_offset); -+ -+ /* Delete unnecessary JALR. */ -+ if (! riscv_relax_delete_bytes (abfd, sec, irel->r_offset + 4, 4)) -+ return FALSE; -+ -+ *again = TRUE; -+ return TRUE; -+} -+ -+static bfd_boolean -+_bfd_riscv_relax_lui (bfd *abfd, asection *sec, -+ struct bfd_link_info *link_info, bfd_byte *contents, -+ Elf_Internal_Shdr *symtab_hdr, -+ Elf_Internal_Sym *isymbuf, -+ Elf_Internal_Rela *internal_relocs, -+ Elf_Internal_Rela *irel, bfd_vma symval, -+ bfd_boolean *again) -+{ -+ bfd_vma gp = bfd_riscv_init_gp_value (abfd, link_info); -+ if (!gp || symval == gp) -+ return TRUE; -+ -+ /* See if this symbol is in range of gp. */ -+ if (RISCV_CONST_HIGH_PART (symval - gp) != 0) -+ return TRUE; -+ -+ /* We can delete the unnecessary AUIPC. The corresponding LO12 reloc -+ will be converted to GPREL during relocation. */ -+ elf_section_data (sec)->relocs = internal_relocs; -+ elf_section_data (sec)->this_hdr.contents = contents; -+ symtab_hdr->contents = (unsigned char *) isymbuf; -+ -+ BFD_ASSERT (irel->r_offset + 4 <= sec->size); -+ irel->r_info = ELF_R_INFO (abfd, ELF_R_SYM (abfd, irel->r_info), R_RISCV_NONE); -+ if (! riscv_relax_delete_bytes (abfd, sec, irel->r_offset, 4)) -+ return FALSE; -+ -+ *again = TRUE; -+ return TRUE; -+} -+ -+static bfd_boolean -+_bfd_riscv_relax_tls_le (bfd *abfd, asection *sec, -+ struct bfd_link_info *link_info, bfd_byte *contents, -+ Elf_Internal_Shdr *symtab_hdr, -+ Elf_Internal_Sym *isymbuf, -+ Elf_Internal_Rela *internal_relocs, -+ Elf_Internal_Rela *irel, bfd_vma symval, -+ bfd_boolean *again) -+{ -+ /* See if this symbol is in range of tp. */ -+ if (RISCV_CONST_HIGH_PART (symval - tprel_base (link_info)) != 0) -+ return TRUE; -+ -+ /* We can delete the unnecessary LUI and TP add. The LO12 reloc will be -+ made directly TP-relative. */ -+ elf_section_data (sec)->relocs = internal_relocs; -+ elf_section_data (sec)->this_hdr.contents = contents; -+ symtab_hdr->contents = (unsigned char *) isymbuf; -+ -+ BFD_ASSERT (irel->r_offset + 4 <= sec->size); -+ irel->r_info = ELF_R_INFO (abfd, ELF_R_SYM (abfd, irel->r_info), R_RISCV_NONE); -+ if (! riscv_relax_delete_bytes (abfd, sec, irel->r_offset, 4)) -+ return FALSE; -+ -+ *again = TRUE; -+ return TRUE; -+} -+ -+/* Relax TLS IE to TLS LE. */ -+static bfd_boolean -+_bfd_riscv_relax_tls_ie (bfd *abfd, asection *sec, -+ bfd_byte *contents, -+ Elf_Internal_Shdr *symtab_hdr, -+ Elf_Internal_Sym *isymbuf, -+ Elf_Internal_Rela *internal_relocs, -+ Elf_Internal_Rela *irel, -+ bfd_boolean *again) -+{ -+ bfd_vma insn; -+ -+ elf_section_data (sec)->relocs = internal_relocs; -+ elf_section_data (sec)->this_hdr.contents = contents; -+ symtab_hdr->contents = (unsigned char *) isymbuf; -+ -+ switch (ELF_R_TYPE (abfd, irel->r_info)) -+ { -+ case R_RISCV_TLS_IE_HI20: -+ /* Replace with R_RISCV_TPREL_HI20. */ -+ irel->r_info = ELF_R_INFO (abfd, ELF_R_SYM (abfd, irel->r_info), R_RISCV_TPREL_HI20); -+ /* Overwrite AUIPC with LUI. */ -+ BFD_ASSERT (irel->r_offset + 4 <= sec->size); -+ insn = bfd_get_32 (abfd, contents + irel->r_offset); -+ insn = (insn & ~MASK_LUI) | MATCH_LUI; -+ bfd_put_32 (abfd, insn, contents + irel->r_offset); -+ break; -+ -+ case R_RISCV_TLS_IE_LO12: -+ /* Just delete the reloc. */ -+ irel->r_info = ELF_R_INFO (abfd, ELF_R_SYM (abfd, irel->r_info), R_RISCV_NONE); -+ if (! riscv_relax_delete_bytes (abfd, sec, irel->r_offset, 4)) -+ return FALSE; -+ break; -+ -+ case R_RISCV_TLS_IE_ADD: -+ /* Replace with R_RISCV_TPREL_ADD. */ -+ irel->r_info = ELF_R_INFO (abfd, ELF_R_SYM (abfd, irel->r_info), R_RISCV_TPREL_ADD); -+ break; -+ -+ case R_RISCV_TLS_IE_LO12_I: -+ /* Replace with R_RISCV_TPREL_LO12_I. */ -+ irel->r_info = ELF_R_INFO (abfd, ELF_R_SYM (abfd, irel->r_info), R_RISCV_TPREL_LO12_I); -+ break; -+ -+ case R_RISCV_TLS_IE_LO12_S: -+ /* Replace with R_RISCV_TPREL_LO12_S. */ -+ irel->r_info = ELF_R_INFO (abfd, ELF_R_SYM (abfd, irel->r_info), R_RISCV_TPREL_LO12_S); -+ break; -+ -+ default: -+ abort(); -+ } -+ -+ *again = TRUE; -+ return TRUE; -+} -+ -+/* Relax AUIPC/JALR into JAL. */ -+ -+bfd_boolean -+_bfd_riscv_relax_section (bfd *abfd, asection *sec, -+ struct bfd_link_info *link_info, bfd_boolean *again) -+{ -+ Elf_Internal_Shdr *symtab_hdr; -+ Elf_Internal_Rela *internal_relocs; -+ Elf_Internal_Rela *irel, *irelend; -+ bfd_byte *contents = NULL; -+ Elf_Internal_Sym *isymbuf = NULL; -+ struct mips_elf_link_hash_table *htab; -+ -+ htab = mips_elf_hash_table (link_info); -+ htab->relax = TRUE; -+ -+ *again = FALSE; -+ -+ if (link_info->relocatable -+ || (sec->flags & SEC_RELOC) == 0 -+ || sec->reloc_count == 0) -+ return TRUE; -+ -+ symtab_hdr = &elf_symtab_hdr (abfd); -+ -+ internal_relocs = (_bfd_elf_link_read_relocs -+ (abfd, sec, NULL, (Elf_Internal_Rela *) NULL, -+ link_info->keep_memory)); -+ if (internal_relocs == NULL) -+ goto error_return; -+ -+ irelend = internal_relocs + sec->reloc_count; -+ for (irel = internal_relocs; irel < irelend; irel++) -+ { -+ bfd_vma symval; -+ int type = ELF_R_TYPE (abfd, irel->r_info); -+ bfd_boolean call = type == R_RISCV_CALL || type == R_RISCV_CALL_PLT; -+ bfd_boolean lui = type == R_RISCV_HI20 || type == R_RISCV_PCREL_HI20; -+ bfd_boolean tls_le = type == R_RISCV_TPREL_HI20 || type == R_RISCV_TPREL_ADD; -+ bfd_boolean tls_ie = type == R_RISCV_TLS_IE_HI20 || type == R_RISCV_TLS_IE_LO12 || type == R_RISCV_TLS_IE_ADD || type == R_RISCV_TLS_IE_LO12_I || type == R_RISCV_TLS_IE_LO12_S; -+ -+ if (!(call || lui || tls_le || tls_ie)) -+ continue; -+ -+ /* Get the section contents. */ -+ if (contents == NULL) -+ { -+ if (elf_section_data (sec)->this_hdr.contents != NULL) -+ contents = elf_section_data (sec)->this_hdr.contents; -+ else -+ { -+ if (!bfd_malloc_and_get_section (abfd, sec, &contents)) -+ goto error_return; -+ } -+ } -+ -+ /* Read this BFD's symbols if we haven't done so already. */ -+ if (isymbuf == NULL && symtab_hdr->sh_info != 0) -+ { -+ isymbuf = (Elf_Internal_Sym *) symtab_hdr->contents; -+ if (isymbuf == NULL) -+ isymbuf = bfd_elf_get_elf_syms (abfd, symtab_hdr, -+ symtab_hdr->sh_info, 0, -+ NULL, NULL, NULL); -+ if (isymbuf == NULL) -+ goto error_return; -+ } -+ -+ /* Get the value of the symbol referred to by the reloc. */ -+ if (ELF_R_SYM (abfd, irel->r_info) < symtab_hdr->sh_info) -+ { -+ /* A local symbol. */ -+ Elf_Internal_Sym *isym = isymbuf + ELF_R_SYM (abfd, irel->r_info); -+ -+ if (isym->st_shndx == SHN_UNDEF) -+ symval = sec_addr(sec) + irel->r_offset; -+ else -+ { -+ asection *isec; -+ BFD_ASSERT (isym->st_shndx < elf_numsections (abfd)); -+ isec = elf_elfsections (abfd)[isym->st_shndx]->bfd_section; -+ symval = sec_addr(isec) + isym->st_value; -+ } -+ } -+ else -+ { -+ unsigned long indx; -+ struct elf_link_hash_entry *h; -+ -+ indx = ELF_R_SYM (abfd, irel->r_info) - symtab_hdr->sh_info; -+ h = elf_sym_hashes (abfd)[indx]; -+ -+ while (h->root.type == bfd_link_hash_indirect -+ || h->root.type == bfd_link_hash_warning) -+ h = (struct elf_link_hash_entry *) h->root.u.i.link; -+ -+ if (h->plt.offset != MINUS_ONE) -+ symval = sec_addr(htab->splt) + h->plt.offset; -+ else if (h->root.u.def.section->output_section == NULL -+ || (h->root.type != bfd_link_hash_defined -+ && h->root.type != bfd_link_hash_defweak)) -+ continue; -+ else -+ symval = sec_addr(h->root.u.def.section) + h->root.u.def.value; -+ } -+ -+ symval += irel->r_addend; -+ -+ if (call && !_bfd_riscv_relax_call (abfd, sec, link_info, contents, -+ symtab_hdr, isymbuf, internal_relocs, -+ irel, symval, again)) -+ goto error_return; -+ if (lui && !_bfd_riscv_relax_lui (abfd, sec, link_info, contents, -+ symtab_hdr, isymbuf, internal_relocs, -+ irel, symval, again)) -+ goto error_return; -+ if (tls_le && !_bfd_riscv_relax_tls_le (abfd, sec, link_info, contents, -+ symtab_hdr, isymbuf, internal_relocs, -+ irel, symval, again)) -+ goto error_return; -+ if (tls_ie && !_bfd_riscv_relax_tls_ie (abfd, sec, contents, symtab_hdr, -+ isymbuf, internal_relocs, irel, -+ again)) -+ goto error_return; -+ } -+ -+ if (isymbuf != NULL -+ && symtab_hdr->contents != (unsigned char *) isymbuf) -+ { -+ if (! link_info->keep_memory) -+ free (isymbuf); -+ else -+ { -+ /* Cache the symbols for elf_link_input_bfd. */ -+ symtab_hdr->contents = (unsigned char *) isymbuf; -+ } -+ } -+ -+ if (contents != NULL -+ && elf_section_data (sec)->this_hdr.contents != contents) -+ { -+ if (! link_info->keep_memory) -+ free (contents); -+ else -+ { -+ /* Cache the section contents for elf_link_input_bfd. */ -+ elf_section_data (sec)->this_hdr.contents = contents; -+ } -+ } -+ -+ if (internal_relocs != NULL -+ && elf_section_data (sec)->relocs != internal_relocs) -+ free (internal_relocs); -+ -+ return TRUE; -+ -+ error_return: -+ if (isymbuf != NULL -+ && symtab_hdr->contents != (unsigned char *) isymbuf) -+ free (isymbuf); -+ if (contents != NULL -+ && elf_section_data (sec)->this_hdr.contents != contents) -+ free (contents); -+ if (internal_relocs != NULL -+ && elf_section_data (sec)->relocs != internal_relocs) -+ free (internal_relocs); -+ -+ return FALSE; -+} -diff --git a/binutils-2.21.1/bfd/elfxx-riscv.h b/binutils-2.21.1/bfd/elfxx-riscv.h -new file mode 100644 -index 0000000..11c2ed8 ---- /dev/null -+++ binutils-2.21.1/bfd/elfxx-riscv.h -@@ -0,0 +1,110 @@ -+/* RISC-V ELF specific backend routines. -+ Copyright 2002, 2003, 2004, 2005, 2006, 2007, 2008, 2009 -+ Free Software Foundation, Inc. -+ -+ This file is part of BFD, the Binary File Descriptor library. -+ -+ This program is free software; you can redistribute it and/or modify -+ it under the terms of the GNU General Public License as published by -+ the Free Software Foundation; either version 3 of the License, or -+ (at your option) any later version. -+ -+ This program is distributed in the hope that it will be useful, -+ but WITHOUT ANY WARRANTY; without even the implied warranty of -+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -+ GNU General Public License for more details. -+ -+ You should have received a copy of the GNU General Public License -+ along with this program; if not, write to the Free Software -+ Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston, -+ MA 02110-1301, USA. */ -+ -+#include "elf/common.h" -+#include "elf/internal.h" -+#include "elf/riscv.h" -+ -+extern bfd_boolean _bfd_riscv_elf_new_section_hook -+ (bfd *, asection *); -+extern void _bfd_riscv_elf_symbol_processing -+ (bfd *, asymbol *); -+extern unsigned int _bfd_riscv_elf_eh_frame_address_size -+ (bfd *, asection *); -+extern bfd_boolean _bfd_riscv_elf_fake_sections -+ (bfd *, Elf_Internal_Shdr *, asection *); -+extern bfd_boolean _bfd_riscv_elf_add_symbol_hook -+ (bfd *, struct bfd_link_info *, Elf_Internal_Sym *, -+ const char **, flagword *, asection **, bfd_vma *); -+extern bfd_boolean _bfd_riscv_elf_create_dynamic_sections -+ (bfd *, struct bfd_link_info *); -+extern bfd_boolean _bfd_riscv_elf_check_relocs -+ (bfd *, struct bfd_link_info *, asection *, const Elf_Internal_Rela *); -+extern bfd_boolean _bfd_riscv_elf_adjust_dynamic_symbol -+ (struct bfd_link_info *, struct elf_link_hash_entry *); -+extern bfd_boolean _bfd_riscv_elf_always_size_sections -+ (bfd *, struct bfd_link_info *); -+extern bfd_boolean _bfd_riscv_elf_size_dynamic_sections -+ (bfd *, struct bfd_link_info *); -+extern bfd_boolean _bfd_riscv_elf_relocate_section -+ (bfd *, struct bfd_link_info *, bfd *, asection *, bfd_byte *, -+ Elf_Internal_Rela *, Elf_Internal_Sym *, asection **); -+extern bfd_boolean _bfd_riscv_elf_finish_dynamic_symbol -+ (bfd *, struct bfd_link_info *, struct elf_link_hash_entry *, -+ Elf_Internal_Sym *); -+extern bfd_boolean _bfd_riscv_elf_finish_dynamic_sections -+ (bfd *, struct bfd_link_info *); -+extern int _bfd_riscv_elf_additional_program_headers -+ (bfd *, struct bfd_link_info *); -+extern bfd_boolean _bfd_riscv_elf_modify_segment_map -+ (bfd *, struct bfd_link_info *); -+extern void _bfd_riscv_elf_copy_indirect_symbol -+ (struct bfd_link_info *, struct elf_link_hash_entry *, -+ struct elf_link_hash_entry *); -+extern bfd_boolean _bfd_riscv_elf_ignore_discarded_relocs -+ (asection *); -+extern bfd_boolean _bfd_riscv_elf_find_nearest_line -+ (bfd *, asection *, asymbol **, bfd_vma, const char **, -+ const char **, unsigned int *); -+extern bfd_boolean _bfd_riscv_elf_find_inliner_info -+ (bfd *, const char **, const char **, unsigned int *); -+extern bfd_boolean _bfd_riscv_elf_set_section_contents -+ (bfd *, asection *, const void *, file_ptr, bfd_size_type); -+extern struct bfd_link_hash_table *_bfd_riscv_elf_link_hash_table_create -+ (bfd *); -+extern bfd_boolean _bfd_riscv_elf_final_link -+ (bfd *, struct bfd_link_info *); -+extern bfd_boolean _bfd_riscv_elf_merge_private_bfd_data -+ (bfd *, bfd *); -+extern bfd_boolean _bfd_riscv_elf_print_private_bfd_data -+ (bfd *, void *); -+extern bfd_boolean _bfd_riscv_elf_discard_info -+ (bfd *, struct elf_reloc_cookie *, struct bfd_link_info *); -+extern bfd_boolean _bfd_riscv_elf_write_section -+ (bfd *, struct bfd_link_info *, asection *, bfd_byte *); -+ -+extern bfd_reloc_status_type _bfd_riscv_elf_generic_reloc -+ (bfd *, arelent *, asymbol *, void *, asection *, bfd *, char **); -+extern bfd_boolean _bfd_riscv_relax_section -+ (bfd *, asection *, struct bfd_link_info *, bfd_boolean *); -+extern void _bfd_riscv_elf_merge_symbol_attribute -+ (struct elf_link_hash_entry *, const Elf_Internal_Sym *, bfd_boolean, bfd_boolean); -+extern char *_bfd_riscv_elf_get_target_dtag (bfd_vma); -+extern void _bfd_riscv_elf_use_plts_and_copy_relocs -+ (struct bfd_link_info *); -+extern bfd_vma _bfd_riscv_elf_plt_sym_val -+ (bfd_vma, const asection *, const arelent *rel); -+ -+extern const struct bfd_elf_special_section _bfd_riscv_elf_special_sections []; -+ -+extern bfd_boolean _bfd_riscv_elf_common_definition (Elf_Internal_Sym *); -+extern reloc_howto_type *riscv_elf_bfd_reloc_type_lookup -+ (bfd *, bfd_reloc_code_real_type); -+extern reloc_howto_type *riscv_elf_bfd_reloc_name_lookup (bfd *, const char *); -+extern void riscv_elf_info_to_howto_rel -+ (bfd *, arelent *, Elf_Internal_Rela *); -+extern void riscv_elf_info_to_howto_rela -+ (bfd *, arelent *, Elf_Internal_Rela *); -+ -+#define elf_backend_common_definition _bfd_riscv_elf_common_definition -+#define elf_backend_special_sections _bfd_riscv_elf_special_sections -+#define elf_backend_eh_frame_address_size _bfd_riscv_elf_eh_frame_address_size -+#define elf_backend_merge_symbol_attribute _bfd_riscv_elf_merge_symbol_attribute -diff --git a/binutils-2.21.1/bfd/targets.c b/binutils-2.21.1/bfd/targets.c -index 3e99754..a1f375c 100644 ---- a/binutils-2.21.1/bfd/targets.c -+++ binutils-2.21.1/bfd/targets.c -@@ -624,6 +624,7 @@ extern const bfd_target bfd_elf32_littlearm_symbian_vec; - extern const bfd_target bfd_elf32_littlearm_vxworks_vec; - extern const bfd_target bfd_elf32_littlemips_vec; - extern const bfd_target bfd_elf32_littlemips_vxworks_vec; -+extern const bfd_target bfd_elf32_littleriscv_vec; - extern const bfd_target bfd_elf32_m32c_vec; - extern const bfd_target bfd_elf32_m32r_vec; - extern const bfd_target bfd_elf32_m32rle_vec; -@@ -702,6 +703,7 @@ extern const bfd_target bfd_elf64_ia64_little_vec; - extern const bfd_target bfd_elf64_ia64_vms_vec; - extern const bfd_target bfd_elf64_little_generic_vec; - extern const bfd_target bfd_elf64_littlemips_vec; -+extern const bfd_target bfd_elf64_littleriscv_vec; - extern const bfd_target bfd_elf64_mmix_vec; - extern const bfd_target bfd_elf64_powerpc_vec; - extern const bfd_target bfd_elf64_powerpcle_vec; -diff --git a/binutils-2.21.1/binutils/Makefile.am b/binutils-2.21.1/binutils/Makefile.am -index e59601d..b51d47d 100644 ---- a/binutils-2.21.1/binutils/Makefile.am -+++ binutils-2.21.1/binutils/Makefile.am -@@ -267,7 +267,7 @@ sysinfo$(EXEEXT_FOR_BUILD): sysinfo.@OBJEXT@ syslex.@OBJEXT@ - - syslex.@OBJEXT@: syslex.c sysinfo.h config.h - if [ -r syslex.c ]; then \ -- $(CC_FOR_BUILD) -c -I. $(AM_CFLAGS) $(CFLAGS_FOR_BUILD) $(NO_WERROR) syslex.c ; \ -+ $(CC_FOR_BUILD) -c -I. -I$(srcdir) $(AM_CFLAGS) $(CFLAGS_FOR_BUILD) $(NO_WERROR) syslex.c ; \ - else \ - $(CC_FOR_BUILD) -c -I. -I$(srcdir) $(AM_CFLAGS) $(CFLAGS_FOR_BUILD) $(NO_WERROR) $(srcdir)/syslex.c ;\ - fi -diff --git a/binutils-2.21.1/binutils/Makefile.in b/binutils-2.21.1/binutils/Makefile.in -index ece74e4..4b0e76f 100644 ---- a/binutils-2.21.1/binutils/Makefile.in -+++ binutils-2.21.1/binutils/Makefile.in -@@ -1279,7 +1279,7 @@ sysinfo$(EXEEXT_FOR_BUILD): sysinfo.@OBJEXT@ syslex.@OBJEXT@ - - syslex.@OBJEXT@: syslex.c sysinfo.h config.h - if [ -r syslex.c ]; then \ -- $(CC_FOR_BUILD) -c -I. $(AM_CFLAGS) $(CFLAGS_FOR_BUILD) $(NO_WERROR) syslex.c ; \ -+ $(CC_FOR_BUILD) -c -I. -I$(srcdir) $(AM_CFLAGS) $(CFLAGS_FOR_BUILD) $(NO_WERROR) syslex.c ; \ - else \ - $(CC_FOR_BUILD) -c -I. -I$(srcdir) $(AM_CFLAGS) $(CFLAGS_FOR_BUILD) $(NO_WERROR) $(srcdir)/syslex.c ;\ - fi -diff --git a/binutils-2.21.1/binutils/doc/binutils.texi b/binutils-2.21.1/binutils/doc/binutils.texi -index d8d1899..448d783 100644 ---- a/binutils-2.21.1/binutils/doc/binutils.texi -+++ binutils-2.21.1/binutils/doc/binutils.texi -@@ -147,18 +147,18 @@ in the section entitled ``GNU Free Documentation License''. - * objcopy:: Copy and translate object files - * objdump:: Display information from object files - * ranlib:: Generate index to archive contents --* readelf:: Display the contents of ELF format files - * size:: List section sizes and total size - * strings:: List printable strings from files - * strip:: Discard symbols --* elfedit:: Update the ELF header of ELF files - * c++filt:: Filter to demangle encoded C++ symbols - * cxxfilt: c++filt. MS-DOS name for c++filt - * addr2line:: Convert addresses to file and line - * nlmconv:: Converts object code into an NLM --* windres:: Manipulate Windows resources - * windmc:: Generator for Windows message resources -+* windres:: Manipulate Windows resources - * dlltool:: Create files needed to build and use DLLs -+* readelf:: Display the contents of ELF format files -+* elfedit:: Update the ELF header of ELF files - * Common Options:: Command-line options for all utilities - * Selecting the Target System:: How these utilities determine the target - * Reporting Bugs:: Reporting Bugs -@@ -2767,7 +2767,7 @@ the Info entries for @file{binutils}. - @c man end - @end ignore - --@node c++filt, addr2line, elfedit, Top -+@node c++filt, addr2line, strip, Top - @chapter c++filt - - @kindex c++filt -@@ -4190,28 +4190,28 @@ equivalent. At least one of the @option{--output-mach}, - - @table @env - --@itemx --input-mach=@var{machine} -+@item --input-mach=@var{machine} - Set the matching input ELF machine type to @var{machine}. If - @option{--input-mach} isn't specified, it will match any ELF - machine types. - - The supported ELF machine types are, @var{L1OM} and @var{x86-64}. - --@itemx --output-mach=@var{machine} -+@item --output-mach=@var{machine} - Change the ELF machine type in the ELF header to @var{machine}. The - supported ELF machine types are the same as @option{--input-mach}. - --@itemx --input-type=@var{type} -+@item --input-type=@var{type} - Set the matching input ELF file type to @var{type}. If - @option{--input-type} isn't specified, it will match any ELF file types. - - The supported ELF file types are, @var{rel}, @var{exec} and @var{dyn}. - --@itemx --output-type=@var{type} -+@item --output-type=@var{type} - Change the ELF file type in the ELF header to @var{type}. The - supported ELF types are the same as @option{--input-type}. - --@itemx --input-osabi=@var{osabi} -+@item --input-osabi=@var{osabi} - Set the matching input ELF file OSABI to @var{osbi}. If - @option{--input-osabi} isn't specified, it will match any ELF OSABIs. - -@@ -4220,7 +4220,7 @@ The supported ELF OSABIs are, @var{none}, @var{HPUX}, @var{NetBSD}, - @var{FreeBSD}, @var{TRU64}, @var{Modesto}, @var{OpenBSD}, @var{OpenVMS}, - @var{NSK}, @var{AROS} and @var{FenixOS}. - --@itemx --output-osabi=@var{osabi} -+@item --output-osabi=@var{osabi} - Change the ELF OSABI in the ELF header to @var{type}. The - supported ELF OSABI are the same as @option{--input-osabi}. - -diff --git a/binutils-2.21.1/binutils/readelf.c b/binutils-2.21.1/binutils/readelf.c -index a31dd3c..ccd9436 100644 ---- a/binutils-2.21.1/binutils/readelf.c -+++ binutils-2.21.1/binutils/readelf.c -@@ -123,6 +123,7 @@ - #include "elf/mep.h" - #include "elf/microblaze.h" - #include "elf/mips.h" -+#include "elf/riscv.h" - #include "elf/mmix.h" - #include "elf/mn10200.h" - #include "elf/mn10300.h" -@@ -1080,6 +1081,10 @@ dump_relocations (FILE * file, - rtype = elf_mips_reloc_type (type); - break; - -+ case EM_RISCV: -+ rtype = elf_riscv_reloc_type (type); -+ break; -+ - case EM_ALPHA: - rtype = elf_alpha_reloc_type (type); - break; -@@ -2405,6 +2410,14 @@ get_machine_flags (unsigned e_flags, unsigned e_machine) - strcat (buf, ", fdpic"); - break; - -+ case EM_RISCV: -+ { -+ unsigned int riscv_extension = EF_GET_RISCV_EXT(e_flags); -+ strcat (buf, ", "); -+ strcat (buf, riscv_elf_flag_to_name (riscv_extension)); -+ } -+ break; -+ - case EM_SH: - switch ((e_flags & EF_SH_MACH_MASK)) - { -diff --git a/binutils-2.21.1/config.sub b/binutils-2.21.1/config.sub -index 204218c..e14dc95 100755 ---- a/binutils-2.21.1/config.sub -+++ binutils-2.21.1/config.sub -@@ -323,6 +323,9 @@ case $basic_machine in - ms1) - basic_machine=mt-unknown - ;; -+ riscv) -+ basic_machine=riscv-ucb -+ ;; - - # We use `pc' rather than `unknown' - # because (1) that's what they normally are, and -diff --git a/binutils-2.21.1/gas/Makefile.am b/binutils-2.21.1/gas/Makefile.am -index 7b897f3..88b27e3 100644 ---- a/binutils-2.21.1/gas/Makefile.am -+++ binutils-2.21.1/gas/Makefile.am -@@ -150,6 +150,7 @@ TARGET_CPU_CFILES = \ - config/tc-pdp11.c \ - config/tc-pj.c \ - config/tc-ppc.c \ -+ config/tc-riscv.c \ - config/tc-rx.c \ - config/tc-s390.c \ - config/tc-score.c \ -@@ -213,6 +214,7 @@ TARGET_CPU_HFILES = \ - config/tc-pdp11.h \ - config/tc-pj.h \ - config/tc-ppc.h \ -+ config/tc-riscv.h \ - config/tc-rx.h \ - config/tc-s390.h \ - config/tc-score.h \ -diff --git a/binutils-2.21.1/gas/Makefile.in b/binutils-2.21.1/gas/Makefile.in -index 1aa9bb4..435df2b 100644 ---- a/binutils-2.21.1/gas/Makefile.in -+++ binutils-2.21.1/gas/Makefile.in -@@ -417,6 +417,7 @@ TARGET_CPU_CFILES = \ - config/tc-pdp11.c \ - config/tc-pj.c \ - config/tc-ppc.c \ -+ config/tc-riscv.c \ - config/tc-rx.c \ - config/tc-s390.c \ - config/tc-score.c \ -@@ -480,6 +481,7 @@ TARGET_CPU_HFILES = \ - config/tc-pdp11.h \ - config/tc-pj.h \ - config/tc-ppc.h \ -+ config/tc-riscv.h \ - config/tc-rx.h \ - config/tc-s390.h \ - config/tc-score.h \ -@@ -824,6 +826,7 @@ distclean-compile: - @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/tc-pdp11.Po@am__quote@ - @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/tc-pj.Po@am__quote@ - @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/tc-ppc.Po@am__quote@ -+@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/tc-riscv.Po@am__quote@ - @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/tc-rx.Po@am__quote@ - @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/tc-s390.Po@am__quote@ - @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/tc-score.Po@am__quote@ -@@ -1469,6 +1472,20 @@ tc-ppc.obj: config/tc-ppc.c - @AMDEP_TRUE@@am__fastdepCC_FALSE@ DEPDIR=$(DEPDIR) $(CCDEPMODE) $(depcomp) @AMDEPBACKSLASH@ - @am__fastdepCC_FALSE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(AM_CPPFLAGS) $(CPPFLAGS) $(AM_CFLAGS) $(CFLAGS) -c -o tc-ppc.obj `if test -f 'config/tc-ppc.c'; then $(CYGPATH_W) 'config/tc-ppc.c'; else $(CYGPATH_W) '$(srcdir)/config/tc-ppc.c'; fi` - -+tc-riscv.o: config/tc-riscv.c -+@am__fastdepCC_TRUE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(AM_CPPFLAGS) $(CPPFLAGS) $(AM_CFLAGS) $(CFLAGS) -MT tc-riscv.o -MD -MP -MF $(DEPDIR)/tc-riscv.Tpo -c -o tc-riscv.o `test -f 'config/tc-riscv.c' || echo '$(srcdir)/'`config/tc-riscv.c -+@am__fastdepCC_TRUE@ $(am__mv) $(DEPDIR)/tc-riscv.Tpo $(DEPDIR)/tc-riscv.Po -+@AMDEP_TRUE@@am__fastdepCC_FALSE@ source='config/tc-riscv.c' object='tc-riscv.o' libtool=no @AMDEPBACKSLASH@ -+@AMDEP_TRUE@@am__fastdepCC_FALSE@ DEPDIR=$(DEPDIR) $(CCDEPMODE) $(depcomp) @AMDEPBACKSLASH@ -+@am__fastdepCC_FALSE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(AM_CPPFLAGS) $(CPPFLAGS) $(AM_CFLAGS) $(CFLAGS) -c -o tc-riscv.o `test -f 'config/tc-riscv.c' || echo '$(srcdir)/'`config/tc-riscv.c -+ -+tc-riscv.obj: config/tc-riscv.c -+@am__fastdepCC_TRUE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(AM_CPPFLAGS) $(CPPFLAGS) $(AM_CFLAGS) $(CFLAGS) -MT tc-riscv.obj -MD -MP -MF $(DEPDIR)/tc-riscv.Tpo -c -o tc-riscv.obj `if test -f 'config/tc-riscv.c'; then $(CYGPATH_W) 'config/tc-riscv.c'; else $(CYGPATH_W) '$(srcdir)/config/tc-riscv.c'; fi` -+@am__fastdepCC_TRUE@ $(am__mv) $(DEPDIR)/tc-riscv.Tpo $(DEPDIR)/tc-riscv.Po -+@AMDEP_TRUE@@am__fastdepCC_FALSE@ source='config/tc-riscv.c' object='tc-riscv.obj' libtool=no @AMDEPBACKSLASH@ -+@AMDEP_TRUE@@am__fastdepCC_FALSE@ DEPDIR=$(DEPDIR) $(CCDEPMODE) $(depcomp) @AMDEPBACKSLASH@ -+@am__fastdepCC_FALSE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(AM_CPPFLAGS) $(CPPFLAGS) $(AM_CFLAGS) $(CFLAGS) -c -o tc-riscv.obj `if test -f 'config/tc-riscv.c'; then $(CYGPATH_W) 'config/tc-riscv.c'; else $(CYGPATH_W) '$(srcdir)/config/tc-riscv.c'; fi` -+ - tc-rx.o: config/tc-rx.c - @am__fastdepCC_TRUE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(AM_CPPFLAGS) $(CPPFLAGS) $(AM_CFLAGS) $(CFLAGS) -MT tc-rx.o -MD -MP -MF $(DEPDIR)/tc-rx.Tpo -c -o tc-rx.o `test -f 'config/tc-rx.c' || echo '$(srcdir)/'`config/tc-rx.c - @am__fastdepCC_TRUE@ $(am__mv) $(DEPDIR)/tc-rx.Tpo $(DEPDIR)/tc-rx.Po -diff --git a/binutils-2.21.1/gas/config/tc-riscv.c b/binutils-2.21.1/gas/config/tc-riscv.c -new file mode 100644 -index 0000000..7a3bf45 ---- /dev/null -+++ binutils-2.21.1/gas/config/tc-riscv.c -@@ -0,0 +1,3296 @@ -+/* tc-mips.c -- assemble code for a MIPS chip. -+ Copyright 1993, 1994, 1995, 1996, 1997, 1998, 1999, 2000, 2001, 2002, -+ 2003, 2004, 2005, 2006, 2007, 2008, 2009 Free Software Foundation, Inc. -+ Contributed by the OSF and Ralph Campbell. -+ Written by Keith Knowles and Ralph Campbell, working independently. -+ Modified for ECOFF and R4000 support by Ian Lance Taylor of Cygnus -+ Support. -+ -+ This file is part of GAS. -+ -+ GAS is free software; you can redistribute it and/or modify -+ it under the terms of the GNU General Public License as published by -+ the Free Software Foundation; either version 3, or (at your option) -+ any later version. -+ -+ GAS is distributed in the hope that it will be useful, -+ but WITHOUT ANY WARRANTY; without even the implied warranty of -+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -+ GNU General Public License for more details. -+ -+ You should have received a copy of the GNU General Public License -+ along with GAS; see the file COPYING. If not, write to the Free -+ Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA -+ 02110-1301, USA. */ -+ -+#include "as.h" -+#include "config.h" -+#include "subsegs.h" -+#include "safe-ctype.h" -+ -+#include "itbl-ops.h" -+#include "dwarf2dbg.h" -+#include "dw2gencfi.h" -+ -+#include -+#include -+ -+#ifdef DEBUG -+#define DBG(x) printf x -+#else -+#define DBG(x) -+#endif -+ -+#ifdef OBJ_MAYBE_ELF -+/* Clean up namespace so we can include obj-elf.h too. */ -+static int mips_output_flavor (void); -+static int mips_output_flavor (void) { return OUTPUT_FLAVOR; } -+#undef OBJ_PROCESS_STAB -+#undef OUTPUT_FLAVOR -+#undef S_GET_ALIGN -+#undef S_GET_SIZE -+#undef S_SET_ALIGN -+#undef S_SET_SIZE -+#undef obj_frob_file -+#undef obj_frob_file_after_relocs -+#undef obj_frob_symbol -+#undef obj_pop_insert -+#undef obj_sec_sym_ok_for_reloc -+#undef OBJ_COPY_SYMBOL_ATTRIBUTES -+ -+#include "obj-elf.h" -+/* Fix any of them that we actually care about. */ -+#undef OUTPUT_FLAVOR -+#define OUTPUT_FLAVOR mips_output_flavor() -+#endif -+ -+#if defined (OBJ_ELF) -+#include "elf/riscv.h" -+#endif -+ -+#include "opcode/riscv.h" -+ -+#define ZERO 0 -+#define SP 14 -+ -+/* Information about an instruction, including its format, operands -+ and fixups. */ -+struct mips_cl_insn -+{ -+ /* The opcode's entry in riscv_opcodes or mips16_opcodes. */ -+ const struct riscv_opcode *insn_mo; -+ -+ /* The 16-bit or 32-bit bitstring of the instruction itself. This is -+ a copy of INSN_MO->match with the operands filled in. */ -+ insn_t insn_opcode; -+ -+ /* The frag that contains the instruction. */ -+ struct frag *frag; -+ -+ /* The offset into FRAG of the first instruction byte. */ -+ long where; -+ -+ /* The relocs associated with the instruction, if any. */ -+ fixS *fixp; -+}; -+ -+static bfd_boolean rv64 = TRUE; /* RV64 (true) or RV32 (false) */ -+#define HAVE_32BIT_SYMBOLS 1 /* LUI/ADDI for symbols, even in RV64 */ -+#define HAVE_32BIT_ADDRESSES (!rv64) -+#define LOAD_ADDRESS_INSN (HAVE_32BIT_ADDRESSES ? "lw" : "ld") -+#define ADD32_INSN (rv64 ? "addiw" : "addi") -+ -+struct riscv_subset -+{ -+ const char* name; -+ int version_major; -+ int version_minor; -+ -+ struct riscv_subset* next; -+}; -+ -+static struct riscv_subset* riscv_subsets; -+ -+static int -+riscv_subset_supports(const char* feature) -+{ -+ struct riscv_subset* s; -+ bfd_boolean rv64_insn; -+ -+ if ((rv64_insn = !strncmp(feature, "64", 2)) || !strncmp(feature, "32", 2)) -+ { -+ if (rv64 != rv64_insn) -+ return 0; -+ feature += 2; -+ } -+ -+ for (s = riscv_subsets; s != NULL; s = s->next) -+ if (strcmp(s->name, feature) == 0) -+ /* FIXME: once we support version numbers: -+ return major == s->version_major && minor <= s->version_minor; */ -+ return 1; -+ -+ return 0; -+} -+ -+static void -+riscv_add_subset(const char* subset) -+{ -+ struct riscv_subset* s = xmalloc(sizeof(struct riscv_subset)); -+ s->name = xstrdup(subset); -+ s->version_major = 1; -+ s->version_minor = 0; -+ s->next = riscv_subsets; -+ riscv_subsets = s; -+} -+ -+static void -+riscv_set_arch(const char* arg) -+{ -+ /* Formally, ISA subset names begin with RV, RV32, or RV64, but we allow the -+ prefix to be omitted. We also allow all-lowercase names if version -+ numbers and eXtensions are omitted (i.e. only some combination of imafd -+ is supported in this case). -+ -+ FIXME: Version numbers are not supported yet. */ -+ const char* subsets = "IMAFD"; -+ const char* p; -+ -+ for (p = arg; *p; p++) -+ if (!ISLOWER(*p) || strchr(subsets, TOUPPER(*p)) == NULL) -+ break; -+ -+ if (!*p) -+ { -+ /* Legal all-lowercase name. */ -+ for (p = arg; *p; p++) -+ { -+ char subset[2] = {TOUPPER(*p), 0}; -+ riscv_add_subset(subset); -+ } -+ return; -+ } -+ -+ if (strncmp(arg, "RV32", 4) == 0) -+ { -+ rv64 = FALSE; -+ arg += 4; -+ } -+ else if (strncmp(arg, "RV64", 4) == 0) -+ { -+ rv64 = TRUE; -+ arg += 4; -+ } -+ else if (strncmp(arg, "RV", 2) == 0) -+ arg += 2; -+ -+ if (*arg && *arg != 'I') -+ as_fatal("`I' must be the first ISA subset name specified (got %c)", *arg); -+ -+ for (p = arg; *p; p++) -+ { -+ if (*p == 'X') -+ { -+ const char* q = p+1; -+ while (ISLOWER(*q)) -+ q++; -+ -+ char subset[q-p+1]; -+ memcpy(subset, p, q-p); -+ subset[q-p] = 0; -+ -+ riscv_add_subset(subset); -+ p = q-1; -+ } -+ else if (strchr(subsets, *p) != NULL) -+ { -+ char subset[2] = {*p, 0}; -+ riscv_add_subset(subset); -+ } -+ else -+ as_fatal("unsupported ISA subset %c", *p); -+ } -+} -+ -+/* This is the set of options which may be modified by the .set -+ pseudo-op. We use a struct so that .set push and .set pop are more -+ reliable. */ -+ -+struct mips_set_options -+{ -+ /* Enable RVC instruction compression */ -+ int rvc; -+}; -+ -+static struct mips_set_options mips_opts = -+{ -+ /* rvc */ 0 -+}; -+ -+/* Whether or not we're generating position-independent code. */ -+static bfd_boolean is_pic = FALSE; -+ -+/* handle of the OPCODE hash table */ -+static struct hash_control *op_hash = NULL; -+ -+/* This array holds the chars that always start a comment. If the -+ pre-processor is disabled, these aren't very useful */ -+const char comment_chars[] = "#"; -+ -+/* This array holds the chars that only start a comment at the beginning of -+ a line. If the line seems to have the form '# 123 filename' -+ .line and .file directives will appear in the pre-processed output */ -+/* Note that input_file.c hand checks for '#' at the beginning of the -+ first line of the input file. This is because the compiler outputs -+ #NO_APP at the beginning of its output. */ -+/* Also note that C style comments are always supported. */ -+const char line_comment_chars[] = "#"; -+ -+/* This array holds machine specific line separator characters. */ -+const char line_separator_chars[] = ";"; -+ -+/* Chars that can be used to separate mant from exp in floating point nums */ -+const char EXP_CHARS[] = "eE"; -+ -+/* Chars that mean this number is a floating point constant */ -+/* As in 0f12.456 */ -+/* or 0d1.2345e12 */ -+const char FLT_CHARS[] = "rRsSfFdDxXpP"; -+ -+/* Also be aware that MAXIMUM_NUMBER_OF_CHARS_FOR_FLOAT may have to be -+ changed in read.c . Ideally it shouldn't have to know about it at all, -+ but nothing is ideal around here. -+ */ -+ -+static char *insn_error; -+ -+static int auto_align = 1; -+ -+/* To output NOP instructions correctly, we need to keep information -+ about the previous two instructions. */ -+ -+/* Debugging level. -g sets this to 2. -gN sets this to N. -g0 is -+ equivalent to seeing no -g option at all. */ -+static int mips_debug = 0; -+ -+/* For ECOFF and ELF, relocations against symbols are done in two -+ parts, with a HI relocation and a LO relocation. Each relocation -+ has only 16 bits of space to store an addend. This means that in -+ order for the linker to handle carries correctly, it must be able -+ to locate both the HI and the LO relocation. This means that the -+ relocations must appear in order in the relocation table. -+ -+ In order to implement this, we keep track of each unmatched HI -+ relocation. We then sort them so that they immediately precede the -+ corresponding LO relocation. */ -+ -+struct mips_hi_fixup -+{ -+ /* Next HI fixup. */ -+ struct mips_hi_fixup *next; -+ /* This fixup. */ -+ fixS *fixp; -+ /* The section this fixup is in. */ -+ segT seg; -+}; -+ -+ -+#define RELAX_BRANCH_ENCODE(uncond, rvc, toofar) \ -+ ((relax_substateT) \ -+ (0xc0000000 \ -+ | ((rvc) ? 1 : 0) \ -+ | ((toofar) ? 2 : 0) \ -+ | ((uncond) ? 8 : 0))) -+#define RELAX_BRANCH_P(i) (((i) & 0xf0000000) == 0xc0000000) -+#define RELAX_BRANCH_UNCOND(i) (((i) & 8) != 0) -+#define RELAX_BRANCH_TOOFAR(i) (((i) & 2) != 0) -+#define RELAX_BRANCH_RVC(i) (((i) & 1) != 0) -+ -+/* Is the given value a sign-extended 32-bit value? */ -+#define IS_SEXT_32BIT_NUM(x) \ -+ (((x) &~ (offsetT) 0x7fffffff) == 0 \ -+ || (((x) &~ (offsetT) 0x7fffffff) == ~ (offsetT) 0x7fffffff)) -+ -+#define IS_SEXT_NBIT_NUM(x,n) \ -+ ({ int64_t __tmp = (x); \ -+ __tmp = (__tmp << (64-(n))) >> (64-(n)); \ -+ __tmp == (x); }) -+ -+/* Is the given value a zero-extended 32-bit value? Or a negated one? */ -+#define IS_ZEXT_32BIT_NUM(x) \ -+ (((x) &~ (offsetT) 0xffffffff) == 0 \ -+ || (((x) &~ (offsetT) 0xffffffff) == ~ (offsetT) 0xffffffff)) -+ -+/* Replace bits MASK << SHIFT of STRUCT with the equivalent bits in -+ VALUE << SHIFT. VALUE is evaluated exactly once. */ -+#define INSERT_BITS(STRUCT, VALUE, MASK, SHIFT) \ -+ (STRUCT) = (((STRUCT) & ~((MASK) << (SHIFT))) \ -+ | (((VALUE) & (MASK)) << (SHIFT))) -+ -+/* Extract bits MASK << SHIFT from STRUCT and shift them right -+ SHIFT places. */ -+#define EXTRACT_BITS(STRUCT, MASK, SHIFT) \ -+ (((STRUCT) >> (SHIFT)) & (MASK)) -+ -+/* Change INSN's opcode so that the operand given by FIELD has value VALUE. -+ INSN is a mips_cl_insn structure and VALUE is evaluated exactly once. */ -+#define INSERT_OPERAND(FIELD, INSN, VALUE) \ -+ INSERT_BITS ((INSN).insn_opcode, VALUE, OP_MASK_##FIELD, OP_SH_##FIELD) -+ -+/* Extract the operand given by FIELD from mips_cl_insn INSN. */ -+#define EXTRACT_OPERAND(FIELD, INSN) \ -+ EXTRACT_BITS ((INSN).insn_opcode, OP_MASK_##FIELD, OP_SH_##FIELD) -+ -+/* Determine if an instruction matches an opcode. */ -+#define OPCODE_MATCHES(OPCODE, OP) \ -+ (((OPCODE) & MASK_##OP) == MATCH_##OP) -+ -+#define INSN_MATCHES(INSN, OP) \ -+ (((INSN).insn_opcode & MASK_##OP) == MATCH_##OP) -+ -+/* Prototypes for static functions. */ -+ -+#define internalError() \ -+ as_fatal (_("internal Error, line %d, %s"), __LINE__, __FILE__) -+ -+enum mips_regclass { MIPS_GR_REG, MIPS_FP_REG }; -+ -+static void append_insn -+ (struct mips_cl_insn *ip, expressionS *p, bfd_reloc_code_real_type r); -+static void macro (struct mips_cl_insn * ip); -+static void mips_ip (char *str, struct mips_cl_insn * ip); -+static void my_getExpression (expressionS *, char *); -+static void s_align (int); -+static void s_change_sec (int); -+static void s_change_section (int); -+static void s_cons (int); -+static void s_float_cons (int); -+static void s_riscv_option (int); -+static void s_dtprelword (int); -+static void s_dtpreldword (int); -+static int validate_mips_insn (const struct riscv_opcode *); -+static int relaxed_branch_length (fragS *fragp, asection *sec, int update); -+ -+/* Pseudo-op table. -+ -+ The following pseudo-ops from the Kane and Heinrich MIPS book -+ should be defined here, but are currently unsupported: .alias, -+ .galive, .gjaldef, .gjrlive, .livereg, .noalias. -+ -+ The following pseudo-ops from the Kane and Heinrich MIPS book are -+ specific to the type of debugging information being generated, and -+ should be defined by the object format: .aent, .begin, .bend, -+ .bgnb, .end, .endb, .ent, .fmask, .frame, .loc, .mask, .verstamp, -+ .vreg. -+ -+ The following pseudo-ops from the Kane and Heinrich MIPS book are -+ not MIPS CPU specific, but are also not specific to the object file -+ format. This file is probably the best place to define them, but -+ they are not currently supported: .asm0, .endr, .lab, .struct. */ -+ -+static const pseudo_typeS mips_pseudo_table[] = -+{ -+ /* MIPS specific pseudo-ops. */ -+ {"option", s_riscv_option, 0}, -+ {"rdata", s_change_sec, 'r'}, -+ {"dtprelword", s_dtprelword, 0}, -+ {"dtpreldword", s_dtpreldword, 0}, -+ -+ /* Relatively generic pseudo-ops that happen to be used on MIPS -+ chips. */ -+ {"asciiz", stringer, 8 + 1}, -+ {"bss", s_change_sec, 'b'}, -+ {"err", s_err, 0}, -+ {"half", s_cons, 1}, -+ {"dword", s_cons, 3}, -+ {"origin", s_org, 0}, -+ {"repeat", s_rept, 0}, -+ -+ /* leb128 doesn't work with relaxation; disallow it */ -+ {"uleb128", s_err, 0}, -+ {"sleb128", s_err, 0}, -+ -+ /* These pseudo-ops are defined in read.c, but must be overridden -+ here for one reason or another. */ -+ {"align", s_align, 0}, -+ {"byte", s_cons, 0}, -+ {"data", s_change_sec, 'd'}, -+ {"double", s_float_cons, 'd'}, -+ {"float", s_float_cons, 'f'}, -+ {"globl", s_globl, 0}, -+ {"global", s_globl, 0}, -+ {"hword", s_cons, 1}, -+ {"int", s_cons, 2}, -+ {"long", s_cons, 2}, -+ {"octa", s_cons, 4}, -+ {"quad", s_cons, 3}, -+ {"section", s_change_section, 0}, -+ {"short", s_cons, 1}, -+ {"single", s_float_cons, 'f'}, -+ {"text", s_change_sec, 't'}, -+ {"word", s_cons, 2}, -+ -+ {"bgnb", s_ignore, 0}, -+ {"endb", s_ignore, 0}, -+ {"file", (void (*) (int)) dwarf2_directive_file, 0 }, -+ {"loc", dwarf2_directive_loc, 0 }, -+ {"verstamp", s_ignore, 0}, -+ -+ { NULL, NULL, 0 }, -+}; -+ -+extern void pop_insert (const pseudo_typeS *); -+ -+void -+mips_pop_insert (void) -+{ -+ pop_insert (mips_pseudo_table); -+} -+ -+/* Symbols labelling the current insn. */ -+ -+struct insn_label_list -+{ -+ struct insn_label_list *next; -+ symbolS *label; -+}; -+ -+static struct insn_label_list *free_insn_labels; -+#define label_list tc_segment_info_data.labels -+ -+void -+mips_clear_insn_labels (void) -+{ -+ register struct insn_label_list **pl; -+ segment_info_type *si; -+ -+ if (now_seg) -+ { -+ for (pl = &free_insn_labels; *pl != NULL; pl = &(*pl)->next) -+ ; -+ -+ si = seg_info (now_seg); -+ *pl = si->label_list; -+ si->label_list = NULL; -+ } -+} -+ -+ -+static char *expr_end; -+ -+/* Expressions which appear in instructions. These are set by -+ mips_ip. */ -+ -+static expressionS imm_expr; -+static expressionS offset_expr; -+ -+/* Relocs associated with imm_expr and offset_expr. */ -+ -+static bfd_reloc_code_real_type imm_reloc = BFD_RELOC_UNUSED; -+static bfd_reloc_code_real_type offset_reloc = BFD_RELOC_UNUSED; -+ -+/* The default target format to use. */ -+ -+const char * -+mips_target_format (void) -+{ -+ return rv64 ? "elf64-littleriscv" : "elf32-littleriscv"; -+} -+ -+/* Return the length of instruction INSN. */ -+ -+static inline unsigned int -+insn_length (const struct mips_cl_insn *insn) -+{ -+ return riscv_insn_length (insn->insn_opcode); -+} -+ -+#if 0 -+static int -+imm_bits_needed(int32_t imm) -+{ -+ int imm_bits = 32; -+ while(imm_bits > 1 && (imm << (32-(imm_bits-1)) >> (32-(imm_bits-1))) == imm) -+ imm_bits--; -+ return imm_bits; -+} -+ -+/* return the rvc small register id, if it exists; else, return -1. */ -+#define ARRAY_FIND(array, x) ({ \ -+ size_t _pos = ARRAY_SIZE(array), _i; \ -+ for(_i = 0; _i < ARRAY_SIZE(array); _i++) \ -+ if((x) == (array)[_i]) \ -+ { _pos = _i; break; } \ -+ _pos; }) -+#define IN_ARRAY(array, x) (ARRAY_FIND(array, x) != ARRAY_SIZE(array)) -+ -+#define is_rvc_reg(type, x) IN_ARRAY(rvc_##type##_regmap, x) -+#define rvc_reg(type, x) ARRAY_FIND(rvc_##type##_regmap, x) -+ -+/* If insn can be compressed, compress it and return 1; else return 0. */ -+static int -+riscv_rvc_compress(struct mips_cl_insn* insn) -+{ -+ int rd = EXTRACT_OPERAND(RD, *insn); -+ int rs1 = EXTRACT_OPERAND(RS1, *insn); -+ int rs2 ATTRIBUTE_UNUSED = EXTRACT_OPERAND(RS2, *insn); -+ int32_t imm = EXTRACT_OPERAND(IMMEDIATE, *insn); -+ imm = imm << (32-RISCV_IMM_BITS) >> (32-RISCV_IMM_BITS); -+ int32_t shamt = imm & 0x3f; -+ int32_t bimm = EXTRACT_OPERAND(IMMLO, *insn) | -+ (EXTRACT_OPERAND(IMMHI, *insn) << RISCV_IMMLO_BITS); -+ bimm = bimm << (32-RISCV_IMM_BITS) >> (32-RISCV_IMM_BITS); -+ int32_t jt = EXTRACT_OPERAND(TARGET, *insn); -+ jt = jt << (32-RISCV_JUMP_BITS) >> (32-RISCV_JUMP_BITS); -+ -+ gas_assert(insn_length(insn) == 4); -+ -+ int imm_bits = imm_bits_needed(imm); -+ int bimm_bits = imm_bits_needed(bimm); -+ int jt_bits = imm_bits_needed(jt); -+ -+ if(INSN_MATCHES(*insn, ADDI) && rd != 0 && rd == rs1 && imm_bits <= 6) -+ { -+ insn->insn_opcode = MATCH_C_ADDI; -+ INSERT_OPERAND(CRD, *insn, rd); -+ INSERT_OPERAND(CIMM6, *insn, imm); -+ } -+ else if(INSN_MATCHES(*insn, ADDIW) && rd != 0 && rd == rs1 && imm_bits <= 6) -+ { -+ insn->insn_opcode = MATCH_C_ADDIW; -+ INSERT_OPERAND(CRD, *insn, rd); -+ INSERT_OPERAND(CIMM6, *insn, imm); -+ } -+ else if(INSN_MATCHES(*insn, JALR) && rd == 0 && imm == 0) -+ { -+ // jalr rd=0, imm=0 is encoded as c.addi rd=0, imm={1'b0,rs1} -+ insn->insn_opcode = MATCH_C_ADDI; -+ INSERT_OPERAND(CIMM6, *insn, rs1); -+ } -+ else if(INSN_MATCHES(*insn, JALR) && rd == 1 && imm == 0) -+ { -+ // jalr rd=1, rs1, imm=0 is encoded as c.addi rd=0, imm={1'b1,rs1} -+ insn->insn_opcode = MATCH_C_ADDI; -+ INSERT_OPERAND(CIMM6, *insn, 0x20 | rs1); -+ } -+ else if((INSN_MATCHES(*insn, ADDI) || INSN_MATCHES(*insn, ORI) || -+ INSN_MATCHES(*insn, XORI)) && rs1 == 0 && imm_bits <= 6) -+ { -+ insn->insn_opcode = MATCH_C_LI; -+ INSERT_OPERAND(CRD, *insn, rd); -+ INSERT_OPERAND(CIMM6, *insn, imm); -+ } -+ else if((INSN_MATCHES(*insn, ADDI) || INSN_MATCHES(*insn, ORI) || -+ INSN_MATCHES(*insn, XORI)) && rs1 == 0 && imm_bits <= 6) -+ { -+ insn->insn_opcode = MATCH_C_LI; -+ INSERT_OPERAND(CRD, *insn, rd); -+ INSERT_OPERAND(CIMM6, *insn, imm); -+ } -+ else if((INSN_MATCHES(*insn, ADDI) || INSN_MATCHES(*insn, ORI) || -+ INSN_MATCHES(*insn, XORI)) && imm == 0) -+ { -+ insn->insn_opcode = MATCH_C_MOVE; -+ INSERT_OPERAND(CRD, *insn, rd); -+ INSERT_OPERAND(CRS1, *insn, rs1); -+ } -+ else if((INSN_MATCHES(*insn, ADD) || INSN_MATCHES(*insn, OR) || -+ INSN_MATCHES(*insn, XOR)) && -+ (rs1 == 0 || rs2 == 0)) -+ { -+ insn->insn_opcode = MATCH_C_MOVE; -+ INSERT_OPERAND(CRD, *insn, rd); -+ INSERT_OPERAND(CRS1, *insn, rs1 == 0 ? rs2 : rs1); -+ } -+ else if(INSN_MATCHES(*insn, ADD) && (rd == rs1 || rd == rs2)) -+ { -+ insn->insn_opcode = MATCH_C_ADD; -+ INSERT_OPERAND(CRD, *insn, rd); -+ INSERT_OPERAND(CRS1, *insn, rd == rs1 ? rs2 : rs1); -+ } -+ else if(INSN_MATCHES(*insn, SUB) && rd == rs2) -+ { -+ insn->insn_opcode = MATCH_C_SUB; -+ INSERT_OPERAND(CRD, *insn, rd); -+ INSERT_OPERAND(CRS1, *insn, rs1); -+ } -+ else if(INSN_MATCHES(*insn, ADD) && is_rvc_reg(rd, rd) && is_rvc_reg(rs1, rs1) && is_rvc_reg(rs2b, rs2)) -+ { -+ insn->insn_opcode = MATCH_C_ADD3; -+ INSERT_OPERAND(CRDS, *insn, rvc_reg(rd, rd)); -+ INSERT_OPERAND(CRS1S, *insn, rvc_reg(rs1, rs1)); -+ INSERT_OPERAND(CRS2BS, *insn, rvc_reg(rs2b, rs2)); -+ } -+ else if(INSN_MATCHES(*insn, SUB) && is_rvc_reg(rd, rd) && is_rvc_reg(rs1, rs1) && is_rvc_reg(rs2b, rs2)) -+ { -+ insn->insn_opcode = MATCH_C_SUB3; -+ INSERT_OPERAND(CRDS, *insn, rvc_reg(rd, rd)); -+ INSERT_OPERAND(CRS1S, *insn, rvc_reg(rs1, rs1)); -+ INSERT_OPERAND(CRS2BS, *insn, rvc_reg(rs2b, rs2)); -+ } -+ else if(INSN_MATCHES(*insn, OR) && is_rvc_reg(rd, rd) && is_rvc_reg(rs1, rs1) && is_rvc_reg(rs2b, rs2)) -+ { -+ insn->insn_opcode = MATCH_C_OR3; -+ INSERT_OPERAND(CRDS, *insn, rvc_reg(rd, rd)); -+ INSERT_OPERAND(CRS1S, *insn, rvc_reg(rs1, rs1)); -+ INSERT_OPERAND(CRS2BS, *insn, rvc_reg(rs2b, rs2)); -+ } -+ else if(INSN_MATCHES(*insn, AND) && is_rvc_reg(rd, rd) && is_rvc_reg(rs1, rs1) && is_rvc_reg(rs2b, rs2)) -+ { -+ insn->insn_opcode = MATCH_C_AND3; -+ INSERT_OPERAND(CRDS, *insn, rvc_reg(rd, rd)); -+ INSERT_OPERAND(CRS1S, *insn, rvc_reg(rs1, rs1)); -+ INSERT_OPERAND(CRS2BS, *insn, rvc_reg(rs2b, rs2)); -+ } -+ else if(INSN_MATCHES(*insn, SLLI) && rd == rs1 && is_rvc_reg(rd, rd)) -+ { -+ insn->insn_opcode = shamt >= 32 ? MATCH_C_SLLI32 : MATCH_C_SLLI; -+ INSERT_OPERAND(CRDS, *insn, rvc_reg(rd, rd)); -+ INSERT_OPERAND(CIMM5, *insn, shamt); -+ } -+ else if(INSN_MATCHES(*insn, SRLI) && rd == rs1 && is_rvc_reg(rd, rd)) -+ { -+ insn->insn_opcode = shamt >= 32 ? MATCH_C_SRLI32 : MATCH_C_SRLI; -+ INSERT_OPERAND(CRDS, *insn, rvc_reg(rd, rd)); -+ INSERT_OPERAND(CIMM5, *insn, shamt); -+ } -+ else if(INSN_MATCHES(*insn, SRAI) && rd == rs1 && is_rvc_reg(rd, rd)) -+ { -+ insn->insn_opcode = shamt >= 32 ? MATCH_C_SRAI32 : MATCH_C_SRAI; -+ INSERT_OPERAND(CRDS, *insn, rvc_reg(rd, rd)); -+ INSERT_OPERAND(CIMM5, *insn, shamt); -+ } -+ else if(INSN_MATCHES(*insn, SLLIW) && rd == rs1 && is_rvc_reg(rd, rd)) -+ { -+ insn->insn_opcode = MATCH_C_SLLIW; -+ INSERT_OPERAND(CRDS, *insn, rvc_reg(rd, rd)); -+ INSERT_OPERAND(CIMM5, *insn, shamt); -+ } -+ else if(INSN_MATCHES(*insn, JAL) && rd == 0 && jt_bits <= 10) -+ { -+ insn->insn_opcode = MATCH_C_J; -+ INSERT_OPERAND(CIMM10, *insn, jt); -+ } -+ else if(INSN_MATCHES(*insn, BEQ) && rs1 == rs2 && bimm_bits <= 10) -+ { -+ insn->insn_opcode = MATCH_C_J; -+ INSERT_OPERAND(CIMM10, *insn, bimm); -+ } -+ else if(INSN_MATCHES(*insn, BEQ) && is_rvc_reg(rs1, rs1) && is_rvc_reg(rs2, rs2) && bimm_bits <= 5) -+ { -+ insn->insn_opcode = MATCH_C_BEQ; -+ INSERT_OPERAND(CRS1S, *insn, rvc_reg(rs1, rs1)); -+ INSERT_OPERAND(CRS2S, *insn, rvc_reg(rs2, rs2)); -+ INSERT_OPERAND(CIMM5, *insn, bimm); -+ } -+ else if(INSN_MATCHES(*insn, BNE) && is_rvc_reg(rs1, rs1) && is_rvc_reg(rs2, rs2) && bimm_bits <= 5) -+ { -+ insn->insn_opcode = MATCH_C_BNE; -+ INSERT_OPERAND(CRS1S, *insn, rvc_reg(rs1, rs1)); -+ INSERT_OPERAND(CRS2S, *insn, rvc_reg(rs2, rs2)); -+ INSERT_OPERAND(CIMM5, *insn, bimm); -+ } -+ else if(INSN_MATCHES(*insn, LD) && rs1 == 30 && imm%8 == 0 && imm_bits <= 9) -+ { -+ insn->insn_opcode = MATCH_C_LDSP; -+ INSERT_OPERAND(CRD, *insn, rd); -+ INSERT_OPERAND(CIMM6, *insn, imm/8); -+ } -+ else if(INSN_MATCHES(*insn, LW) && rs1 == 30 && imm%4 == 0 && imm_bits <= 8) -+ { -+ insn->insn_opcode = MATCH_C_LWSP; -+ INSERT_OPERAND(CRD, *insn, rd); -+ INSERT_OPERAND(CIMM6, *insn, imm/4); -+ } -+ else if(INSN_MATCHES(*insn, SD) && rs1 == 30 && bimm%8 == 0 && bimm_bits <= 9) -+ { -+ insn->insn_opcode = MATCH_C_SDSP; -+ INSERT_OPERAND(CRS2, *insn, rs2); -+ INSERT_OPERAND(CIMM6, *insn, bimm/8); -+ } -+ else if(INSN_MATCHES(*insn, SW) && rs1 == 30 && bimm%4 == 0 && bimm_bits <= 8) -+ { -+ insn->insn_opcode = MATCH_C_SWSP; -+ INSERT_OPERAND(CRS2, *insn, rs2); -+ INSERT_OPERAND(CIMM6, *insn, bimm/4); -+ } -+ else if(INSN_MATCHES(*insn, LD) && is_rvc_reg(rs1, rs1) && is_rvc_reg(rd, rd) && imm%8 == 0 && imm_bits <= 8) -+ { -+ insn->insn_opcode = MATCH_C_LD; -+ INSERT_OPERAND(CRS1S, *insn, rvc_reg(rs1, rs1)); -+ INSERT_OPERAND(CRDS, *insn, rvc_reg(rd, rd)); -+ INSERT_OPERAND(CIMM5, *insn, imm/8); -+ } -+ else if(INSN_MATCHES(*insn, LW) && is_rvc_reg(rs1, rs1) && is_rvc_reg(rd, rd) && imm%4 == 0 && imm_bits <= 7) -+ { -+ insn->insn_opcode = MATCH_C_LW; -+ INSERT_OPERAND(CRS1S, *insn, rvc_reg(rs1, rs1)); -+ INSERT_OPERAND(CRDS, *insn, rvc_reg(rd, rd)); -+ INSERT_OPERAND(CIMM5, *insn, imm/4); -+ } -+ else if(INSN_MATCHES(*insn, SD) && is_rvc_reg(rs1, rs1) && is_rvc_reg(rs2, rs2) && bimm%8 == 0 && bimm_bits <= 8) -+ { -+ insn->insn_opcode = MATCH_C_SD; -+ INSERT_OPERAND(CRS1S, *insn, rvc_reg(rs1, rs1)); -+ INSERT_OPERAND(CRS2S, *insn, rvc_reg(rs2, rs2)); -+ INSERT_OPERAND(CIMM5, *insn, bimm/8); -+ } -+ else if(INSN_MATCHES(*insn, SW) && is_rvc_reg(rs1, rs1) && is_rvc_reg(rs2, rs2) && bimm%4 == 0 && bimm_bits <= 7) -+ { -+ insn->insn_opcode = MATCH_C_SW; -+ INSERT_OPERAND(CRS1S, *insn, rvc_reg(rs1, rs1)); -+ INSERT_OPERAND(CRS2S, *insn, rvc_reg(rs2, rs2)); -+ INSERT_OPERAND(CIMM5, *insn, bimm/4); -+ } -+ else if(INSN_MATCHES(*insn, LD) && imm == 0) -+ { -+ insn->insn_opcode = MATCH_C_LD0; -+ INSERT_OPERAND(CRS1, *insn, rs1); -+ INSERT_OPERAND(CRD, *insn, rd); -+ } -+ else if(INSN_MATCHES(*insn, LW) && imm == 0) -+ { -+ insn->insn_opcode = MATCH_C_LW0; -+ INSERT_OPERAND(CRS1, *insn, rs1); -+ INSERT_OPERAND(CRD, *insn, rd); -+ } -+ else if(INSN_MATCHES(*insn, FLD) && is_rvc_reg(rs1, rs1) && is_rvc_reg(rd, rd) && imm%8 == 0 && imm_bits <= 8) -+ { -+ insn->insn_opcode = MATCH_C_FLD; -+ INSERT_OPERAND(CRS1S, *insn, rvc_reg(rs1, rs1)); -+ INSERT_OPERAND(CRDS, *insn, rvc_reg(rd, rd)); -+ INSERT_OPERAND(CIMM5, *insn, imm/8); -+ } -+ else if(INSN_MATCHES(*insn, FLW) && is_rvc_reg(rs1, rs1) && is_rvc_reg(rd, rd) && imm%4 == 0 && imm_bits <= 7) -+ { -+ insn->insn_opcode = MATCH_C_FLW; -+ INSERT_OPERAND(CRS1S, *insn, rvc_reg(rs1, rs1)); -+ INSERT_OPERAND(CRDS, *insn, rvc_reg(rd, rd)); -+ INSERT_OPERAND(CIMM5, *insn, imm/4); -+ } -+ else if(INSN_MATCHES(*insn, FSD) && is_rvc_reg(rs1, rs1) && is_rvc_reg(rs2, rs2) && bimm%8 == 0 && bimm_bits <= 8) -+ { -+ insn->insn_opcode = MATCH_C_FSD; -+ INSERT_OPERAND(CRS1S, *insn, rvc_reg(rs1, rs1)); -+ INSERT_OPERAND(CRS2S, *insn, rvc_reg(rs2, rs2)); -+ INSERT_OPERAND(CIMM5, *insn, bimm/8); -+ } -+ else if(INSN_MATCHES(*insn, FSW) && is_rvc_reg(rs1, rs1) && is_rvc_reg(rs2, rs2) && bimm%4 == 0 && bimm_bits <= 7) -+ { -+ insn->insn_opcode = MATCH_C_FSW; -+ INSERT_OPERAND(CRS1S, *insn, rvc_reg(rs1, rs1)); -+ INSERT_OPERAND(CRS2S, *insn, rvc_reg(rs2, rs2)); -+ INSERT_OPERAND(CIMM5, *insn, bimm/4); -+ } -+ else -+ return 0; -+ -+ gas_assert(insn_length(insn) == 2); -+ -+ return 1; -+} -+#endif -+ -+/* Initialise INSN from opcode entry MO. Leave its position unspecified. */ -+ -+static void -+create_insn (struct mips_cl_insn *insn, const struct riscv_opcode *mo) -+{ -+ insn->insn_mo = mo; -+ insn->insn_opcode = mo->match; -+ insn->frag = NULL; -+ insn->where = 0; -+ insn->fixp = NULL; -+} -+ -+/* Install INSN at the location specified by its "frag" and "where" fields. */ -+ -+static void -+install_insn (const struct mips_cl_insn *insn) -+{ -+ char *f = insn->frag->fr_literal + insn->where; -+ md_number_to_chars (f, insn->insn_opcode, insn_length(insn)); -+} -+ -+/* Move INSN to offset WHERE in FRAG. Adjust the fixups accordingly -+ and install the opcode in the new location. */ -+ -+static void -+move_insn (struct mips_cl_insn *insn, fragS *frag, long where) -+{ -+ insn->frag = frag; -+ insn->where = where; -+ if (insn->fixp != NULL) -+ { -+ insn->fixp->fx_frag = frag; -+ insn->fixp->fx_where = where; -+ } -+ install_insn (insn); -+} -+ -+/* Add INSN to the end of the output. */ -+ -+static void -+add_fixed_insn (struct mips_cl_insn *insn) -+{ -+ char *f = frag_more (insn_length (insn)); -+ move_insn (insn, frag_now, f - frag_now->fr_literal); -+} -+ -+static void -+add_relaxed_insn (struct mips_cl_insn *insn, int max_chars, int var, -+ relax_substateT subtype, symbolS *symbol, offsetT offset) -+{ -+ frag_grow (max_chars); -+ move_insn (insn, frag_now, frag_more (0) - frag_now->fr_literal); -+ frag_var (rs_machine_dependent, max_chars, var, -+ subtype, symbol, offset, NULL); -+} -+ -+struct regname { -+ const char *name; -+ unsigned int num; -+}; -+ -+#define RNUM_MASK 0x000fff -+#define RTYPE_NUM 0x001000 -+#define RTYPE_FPU 0x002000 -+#define RTYPE_VEC 0x004000 -+#define RTYPE_GP 0x008000 -+#define RTYPE_CP0 0x010000 -+#define RTYPE_VGR_REG 0x020000 -+#define RTYPE_VFP_REG 0x040000 -+ -+#define X_REGISTER_NUMBERS \ -+ {"x0", RTYPE_NUM | 0}, \ -+ {"x1", RTYPE_NUM | 1}, \ -+ {"x2", RTYPE_NUM | 2}, \ -+ {"x3", RTYPE_NUM | 3}, \ -+ {"x4", RTYPE_NUM | 4}, \ -+ {"x5", RTYPE_NUM | 5}, \ -+ {"x6", RTYPE_NUM | 6}, \ -+ {"x7", RTYPE_NUM | 7}, \ -+ {"x8", RTYPE_NUM | 8}, \ -+ {"x9", RTYPE_NUM | 9}, \ -+ {"x10", RTYPE_NUM | 10}, \ -+ {"x11", RTYPE_NUM | 11}, \ -+ {"x12", RTYPE_NUM | 12}, \ -+ {"x13", RTYPE_NUM | 13}, \ -+ {"x14", RTYPE_NUM | 14}, \ -+ {"x15", RTYPE_NUM | 15}, \ -+ {"x16", RTYPE_NUM | 16}, \ -+ {"x17", RTYPE_NUM | 17}, \ -+ {"x18", RTYPE_NUM | 18}, \ -+ {"x19", RTYPE_NUM | 19}, \ -+ {"x20", RTYPE_NUM | 20}, \ -+ {"x21", RTYPE_NUM | 21}, \ -+ {"x22", RTYPE_NUM | 22}, \ -+ {"x23", RTYPE_NUM | 23}, \ -+ {"x24", RTYPE_NUM | 24}, \ -+ {"x25", RTYPE_NUM | 25}, \ -+ {"x26", RTYPE_NUM | 26}, \ -+ {"x27", RTYPE_NUM | 27}, \ -+ {"x28", RTYPE_NUM | 28}, \ -+ {"x29", RTYPE_NUM | 29}, \ -+ {"x30", RTYPE_NUM | 30}, \ -+ {"x31", RTYPE_NUM | 31} -+ -+#define F_REGISTER_NUMBERS \ -+ {"f0", RTYPE_FPU | 0}, \ -+ {"f1", RTYPE_FPU | 1}, \ -+ {"f2", RTYPE_FPU | 2}, \ -+ {"f3", RTYPE_FPU | 3}, \ -+ {"f4", RTYPE_FPU | 4}, \ -+ {"f5", RTYPE_FPU | 5}, \ -+ {"f6", RTYPE_FPU | 6}, \ -+ {"f7", RTYPE_FPU | 7}, \ -+ {"f8", RTYPE_FPU | 8}, \ -+ {"f9", RTYPE_FPU | 9}, \ -+ {"f10", RTYPE_FPU | 10}, \ -+ {"f11", RTYPE_FPU | 11}, \ -+ {"f12", RTYPE_FPU | 12}, \ -+ {"f13", RTYPE_FPU | 13}, \ -+ {"f14", RTYPE_FPU | 14}, \ -+ {"f15", RTYPE_FPU | 15}, \ -+ {"f16", RTYPE_FPU | 16}, \ -+ {"f17", RTYPE_FPU | 17}, \ -+ {"f18", RTYPE_FPU | 18}, \ -+ {"f19", RTYPE_FPU | 19}, \ -+ {"f20", RTYPE_FPU | 20}, \ -+ {"f21", RTYPE_FPU | 21}, \ -+ {"f22", RTYPE_FPU | 22}, \ -+ {"f23", RTYPE_FPU | 23}, \ -+ {"f24", RTYPE_FPU | 24}, \ -+ {"f25", RTYPE_FPU | 25}, \ -+ {"f26", RTYPE_FPU | 26}, \ -+ {"f27", RTYPE_FPU | 27}, \ -+ {"f28", RTYPE_FPU | 28}, \ -+ {"f29", RTYPE_FPU | 29}, \ -+ {"f30", RTYPE_FPU | 30}, \ -+ {"f31", RTYPE_FPU | 31} -+ -+/* Remaining symbolic register names */ -+#define X_REGISTER_NAMES \ -+ { "zero", 0 | RTYPE_GP }, \ -+ { "ra", 1 | RTYPE_GP }, \ -+ { "s0", 2 | RTYPE_GP }, \ -+ { "s1", 3 | RTYPE_GP }, \ -+ { "s2", 4 | RTYPE_GP }, \ -+ { "s3", 5 | RTYPE_GP }, \ -+ { "s4", 6 | RTYPE_GP }, \ -+ { "s5", 7 | RTYPE_GP }, \ -+ { "s6", 8 | RTYPE_GP }, \ -+ { "s7", 9 | RTYPE_GP }, \ -+ { "s8", 10 | RTYPE_GP }, \ -+ { "s9", 11 | RTYPE_GP }, \ -+ { "s10", 12 | RTYPE_GP }, \ -+ { "s11", 13 | RTYPE_GP }, \ -+ { "sp", 14 | RTYPE_GP }, \ -+ { "tp", 15 | RTYPE_GP }, \ -+ { "v0", 16 | RTYPE_GP }, \ -+ { "v1", 17 | RTYPE_GP }, \ -+ { "a0", 18 | RTYPE_GP }, \ -+ { "a1", 19 | RTYPE_GP }, \ -+ { "a2", 20 | RTYPE_GP }, \ -+ { "a3", 21 | RTYPE_GP }, \ -+ { "a4", 22 | RTYPE_GP }, \ -+ { "a5", 23 | RTYPE_GP }, \ -+ { "a6", 24 | RTYPE_GP }, \ -+ { "a7", 25 | RTYPE_GP }, \ -+ { "t0", 26 | RTYPE_GP }, \ -+ { "t1", 27 | RTYPE_GP }, \ -+ { "t2", 28 | RTYPE_GP }, \ -+ { "t3", 29 | RTYPE_GP }, \ -+ { "t4", 30 | RTYPE_GP }, \ -+ { "gp", 31 | RTYPE_GP } -+ -+#define F_REGISTER_NAMES \ -+ { "fs0", 0 | RTYPE_FPU }, \ -+ { "fs1", 1 | RTYPE_FPU }, \ -+ { "fs2", 2 | RTYPE_FPU }, \ -+ { "fs3", 3 | RTYPE_FPU }, \ -+ { "fs4", 4 | RTYPE_FPU }, \ -+ { "fs5", 5 | RTYPE_FPU }, \ -+ { "fs6", 6 | RTYPE_FPU }, \ -+ { "fs7", 7 | RTYPE_FPU }, \ -+ { "fs8", 8 | RTYPE_FPU }, \ -+ { "fs9", 9 | RTYPE_FPU }, \ -+ { "fs10", 10 | RTYPE_FPU }, \ -+ { "fs11", 11 | RTYPE_FPU }, \ -+ { "fs12", 12 | RTYPE_FPU }, \ -+ { "fs13", 13 | RTYPE_FPU }, \ -+ { "fs14", 14 | RTYPE_FPU }, \ -+ { "fs15", 15 | RTYPE_FPU }, \ -+ { "fv0", 16 | RTYPE_FPU }, \ -+ { "fv1", 17 | RTYPE_FPU }, \ -+ { "fa0", 18 | RTYPE_FPU }, \ -+ { "fa1", 19 | RTYPE_FPU }, \ -+ { "fa2", 20 | RTYPE_FPU }, \ -+ { "fa3", 21 | RTYPE_FPU }, \ -+ { "fa4", 22 | RTYPE_FPU }, \ -+ { "fa5", 23 | RTYPE_FPU }, \ -+ { "fa6", 24 | RTYPE_FPU }, \ -+ { "fa7", 25 | RTYPE_FPU }, \ -+ { "ft0", 26 | RTYPE_FPU }, \ -+ { "ft1", 27 | RTYPE_FPU }, \ -+ { "ft2", 28 | RTYPE_FPU }, \ -+ { "ft3", 29 | RTYPE_FPU }, \ -+ { "ft4", 30 | RTYPE_FPU }, \ -+ { "ft5", 31 | RTYPE_FPU } -+ -+#define RISCV_VEC_GR_REGISTER_NAMES \ -+ {"vx0", RTYPE_VGR_REG | 0}, \ -+ {"vx1", RTYPE_VGR_REG | 1}, \ -+ {"vx2", RTYPE_VGR_REG | 2}, \ -+ {"vx3", RTYPE_VGR_REG | 3}, \ -+ {"vx4", RTYPE_VGR_REG | 4}, \ -+ {"vx5", RTYPE_VGR_REG | 5}, \ -+ {"vx6", RTYPE_VGR_REG | 6}, \ -+ {"vx7", RTYPE_VGR_REG | 7}, \ -+ {"vx8", RTYPE_VGR_REG | 8}, \ -+ {"vx9", RTYPE_VGR_REG | 9}, \ -+ {"vx10", RTYPE_VGR_REG | 10}, \ -+ {"vx11", RTYPE_VGR_REG | 11}, \ -+ {"vx12", RTYPE_VGR_REG | 12}, \ -+ {"vx13", RTYPE_VGR_REG | 13}, \ -+ {"vx14", RTYPE_VGR_REG | 14}, \ -+ {"vx15", RTYPE_VGR_REG | 15}, \ -+ {"vx16", RTYPE_VGR_REG | 16}, \ -+ {"vx17", RTYPE_VGR_REG | 17}, \ -+ {"vx18", RTYPE_VGR_REG | 18}, \ -+ {"vx19", RTYPE_VGR_REG | 19}, \ -+ {"vx20", RTYPE_VGR_REG | 20}, \ -+ {"vx21", RTYPE_VGR_REG | 21}, \ -+ {"vx22", RTYPE_VGR_REG | 22}, \ -+ {"vx23", RTYPE_VGR_REG | 23}, \ -+ {"vx24", RTYPE_VGR_REG | 24}, \ -+ {"vx25", RTYPE_VGR_REG | 25}, \ -+ {"vx26", RTYPE_VGR_REG | 26}, \ -+ {"vx27", RTYPE_VGR_REG | 27}, \ -+ {"vx28", RTYPE_VGR_REG | 28}, \ -+ {"vx29", RTYPE_VGR_REG | 29}, \ -+ {"vx30", RTYPE_VGR_REG | 30}, \ -+ {"vx31", RTYPE_VGR_REG | 31} -+ -+#define RISCV_VEC_GR_SYMBOLIC_REGISTER_NAMES \ -+ {"vzero", RTYPE_VGR_REG | 0}, \ -+ {"vra", RTYPE_VGR_REG | 1}, \ -+ {"vs0", RTYPE_VGR_REG | 2}, \ -+ {"vs1", RTYPE_VGR_REG | 3}, \ -+ {"vs2", RTYPE_VGR_REG | 4}, \ -+ {"vs3", RTYPE_VGR_REG | 5}, \ -+ {"vs4", RTYPE_VGR_REG | 6}, \ -+ {"vs5", RTYPE_VGR_REG | 7}, \ -+ {"vs6", RTYPE_VGR_REG | 8}, \ -+ {"vs7", RTYPE_VGR_REG | 9}, \ -+ {"vs8", RTYPE_VGR_REG | 10}, \ -+ {"vs9", RTYPE_VGR_REG | 11}, \ -+ {"vs10", RTYPE_VGR_REG | 12}, \ -+ {"vs11", RTYPE_VGR_REG | 13}, \ -+ {"vsp", RTYPE_VGR_REG | 14}, \ -+ {"vtp", RTYPE_VGR_REG | 15}, \ -+ {"vv0", RTYPE_VGR_REG | 16}, \ -+ {"vv1", RTYPE_VGR_REG | 17}, \ -+ {"va0", RTYPE_VGR_REG | 18}, \ -+ {"va1", RTYPE_VGR_REG | 19}, \ -+ {"va2", RTYPE_VGR_REG | 20}, \ -+ {"va3", RTYPE_VGR_REG | 21}, \ -+ {"va4", RTYPE_VGR_REG | 22}, \ -+ {"va5", RTYPE_VGR_REG | 23}, \ -+ {"va6", RTYPE_VGR_REG | 24}, \ -+ {"va7", RTYPE_VGR_REG | 25}, \ -+ {"vt0", RTYPE_VGR_REG | 26}, \ -+ {"vt1", RTYPE_VGR_REG | 27}, \ -+ {"vt2", RTYPE_VGR_REG | 28}, \ -+ {"vt3", RTYPE_VGR_REG | 29}, \ -+ {"vt4", RTYPE_VGR_REG | 30}, \ -+ {"vgp", RTYPE_VGR_REG | 31} -+ -+#define RISCV_VEC_FP_REGISTER_NAMES \ -+ {"vf0", RTYPE_VFP_REG | 0}, \ -+ {"vf1", RTYPE_VFP_REG | 1}, \ -+ {"vf2", RTYPE_VFP_REG | 2}, \ -+ {"vf3", RTYPE_VFP_REG | 3}, \ -+ {"vf4", RTYPE_VFP_REG | 4}, \ -+ {"vf5", RTYPE_VFP_REG | 5}, \ -+ {"vf6", RTYPE_VFP_REG | 6}, \ -+ {"vf7", RTYPE_VFP_REG | 7}, \ -+ {"vf8", RTYPE_VFP_REG | 8}, \ -+ {"vf9", RTYPE_VFP_REG | 9}, \ -+ {"vf10", RTYPE_VFP_REG | 10}, \ -+ {"vf11", RTYPE_VFP_REG | 11}, \ -+ {"vf12", RTYPE_VFP_REG | 12}, \ -+ {"vf13", RTYPE_VFP_REG | 13}, \ -+ {"vf14", RTYPE_VFP_REG | 14}, \ -+ {"vf15", RTYPE_VFP_REG | 15}, \ -+ {"vf16", RTYPE_VFP_REG | 16}, \ -+ {"vf17", RTYPE_VFP_REG | 17}, \ -+ {"vf18", RTYPE_VFP_REG | 18}, \ -+ {"vf19", RTYPE_VFP_REG | 19}, \ -+ {"vf20", RTYPE_VFP_REG | 20}, \ -+ {"vf21", RTYPE_VFP_REG | 21}, \ -+ {"vf22", RTYPE_VFP_REG | 22}, \ -+ {"vf23", RTYPE_VFP_REG | 23}, \ -+ {"vf24", RTYPE_VFP_REG | 24}, \ -+ {"vf25", RTYPE_VFP_REG | 25}, \ -+ {"vf26", RTYPE_VFP_REG | 26}, \ -+ {"vf27", RTYPE_VFP_REG | 27}, \ -+ {"vf28", RTYPE_VFP_REG | 28}, \ -+ {"vf29", RTYPE_VFP_REG | 29}, \ -+ {"vf30", RTYPE_VFP_REG | 30}, \ -+ {"vf31", RTYPE_VFP_REG | 31} -+ -+static const struct regname reg_names[] = { -+ X_REGISTER_NUMBERS, -+ X_REGISTER_NAMES, -+ -+ F_REGISTER_NUMBERS, -+ F_REGISTER_NAMES, -+ -+#define DECLARE_CSR(name, num) {#name, RTYPE_CP0 | num}, -+#include "opcode/riscv-opc.h" -+#undef DECLARE_CSR -+ -+ RISCV_VEC_GR_REGISTER_NAMES, -+ RISCV_VEC_FP_REGISTER_NAMES, -+ RISCV_VEC_GR_SYMBOLIC_REGISTER_NAMES, -+ -+ {0, 0} -+}; -+ -+static struct hash_control *reg_names_hash = NULL; -+ -+static int -+reg_lookup (char **s, unsigned int types, unsigned int *regnop) -+{ -+ struct regname *r; -+ char *e; -+ char save_c; -+ int reg = -1; -+ -+ /* Find end of name. */ -+ e = *s; -+ if (is_name_beginner (*e)) -+ ++e; -+ while (is_part_of_name (*e)) -+ ++e; -+ -+ /* Terminate name. */ -+ save_c = *e; -+ *e = '\0'; -+ -+ /* Look for the register. */ -+ r = (struct regname *) hash_find (reg_names_hash, *s); -+ if (r != NULL && (r->num & types)) -+ reg = r->num & RNUM_MASK; -+ -+ /* Advance to next token if a register was recognised. */ -+ if (reg >= 0) -+ *s = e; -+ -+ *e = save_c; -+ if (regnop) -+ *regnop = reg; -+ return reg >= 0; -+} -+ -+static unsigned int -+reg_lookup_assert (const char *s, unsigned int types) -+{ -+ struct regname *r = (struct regname *) hash_find (reg_names_hash, s); -+ gas_assert (r != NULL && (r->num & types)); -+ return r->num & RNUM_MASK; -+} -+ -+static int -+arg_lookup(char **s, const char* const* array, size_t size, unsigned *regnop) -+{ -+ const char *p = strchr(*s, ','); -+ size_t i, len = p ? (size_t)(p - *s) : strlen(*s); -+ -+ for (i = 0; i < size; i++) -+ if (array[i] != NULL && strncmp(array[i], *s, len) == 0) -+ { -+ *regnop = i; -+ *s += len; -+ return 1; -+ } -+ -+ return 0; -+} -+ -+/* This function is called once, at assembler startup time. It should set up -+ all the tables, etc. that the MD part of the assembler will need. */ -+ -+void -+md_begin (void) -+{ -+ const char *retval = NULL; -+ int i = 0; -+ -+ if (! bfd_set_arch_mach (stdoutput, bfd_arch_riscv, 0)) -+ as_warn (_("Could not set architecture and machine")); -+ -+ op_hash = hash_new (); -+ -+ for (i = 0; i < NUMOPCODES;) -+ { -+ const char *name = riscv_opcodes[i].name; -+ -+ if (riscv_subset_supports(riscv_opcodes[i].subset)) -+ retval = hash_insert (op_hash, name, (void *) &riscv_opcodes[i]); -+ -+ if (retval != NULL) -+ { -+ fprintf (stderr, _("internal error: can't hash `%s': %s\n"), -+ riscv_opcodes[i].name, retval); -+ /* Probably a memory allocation problem? Give up now. */ -+ as_fatal (_("Broken assembler. No assembly attempted.")); -+ } -+ do -+ { -+ if (riscv_opcodes[i].pinfo != INSN_MACRO) -+ { -+ if (!validate_mips_insn (&riscv_opcodes[i])) -+ as_fatal (_("Broken assembler. No assembly attempted.")); -+ } -+ ++i; -+ } -+ while ((i < NUMOPCODES) && !strcmp (riscv_opcodes[i].name, name)); -+ } -+ -+ reg_names_hash = hash_new (); -+ for (i = 0; reg_names[i].name; i++) -+ { -+ retval = hash_insert (reg_names_hash, reg_names[i].name, -+ (void*) ®_names[i]); -+ if (retval != NULL) -+ { -+ fprintf (stderr, _("internal error: can't hash `%s': %s\n"), -+ reg_names[i].name, retval); -+ /* Probably a memory allocation problem? Give up now. */ -+ as_fatal (_("Broken assembler. No assembly attempted.")); -+ } -+ } -+ -+ mips_clear_insn_labels (); -+ -+ /* set the default alignment for the text section (2**2) */ -+ record_alignment (text_section, 2); -+} -+ -+void -+md_assemble (char *str) -+{ -+ struct mips_cl_insn insn; -+ -+ imm_expr.X_op = O_absent; -+ offset_expr.X_op = O_absent; -+ imm_reloc = BFD_RELOC_UNUSED; -+ offset_reloc = BFD_RELOC_UNUSED; -+ -+ mips_ip (str, &insn); -+ DBG ((_("returned from mips_ip(%s) insn_opcode = 0x%x\n"), -+ str, insn.insn_opcode)); -+ -+ -+ if (insn_error) -+ { -+ as_bad ("%s `%s'", insn_error, str); -+ return; -+ } -+ -+ if (insn.insn_mo->pinfo == INSN_MACRO) -+ macro (&insn); -+ else -+ { -+ if (imm_expr.X_op != O_absent) -+ append_insn (&insn, &imm_expr, imm_reloc); -+ else if (offset_expr.X_op != O_absent) -+ append_insn (&insn, &offset_expr, offset_reloc); -+ else -+ append_insn (&insn, NULL, BFD_RELOC_UNUSED); -+ } -+} -+ -+/* Output an instruction. IP is the instruction information. -+ ADDRESS_EXPR is an operand of the instruction to be used with -+ RELOC_TYPE. */ -+ -+static void -+append_insn (struct mips_cl_insn *ip, expressionS *address_expr, -+ bfd_reloc_code_real_type reloc_type) -+{ -+#ifdef OBJ_ELF -+ dwarf2_emit_insn (0); -+#endif -+ -+ gas_assert(reloc_type <= BFD_RELOC_UNUSED); -+ -+#if 0 -+ /* don't compress instructions with relocs */ -+ int compressible = (reloc_type == BFD_RELOC_UNUSED || -+ address_expr == NULL || address_expr->X_op == O_constant) && mips_opts.rvc; -+ -+ /* speculate that branches/jumps can be compressed. if not, we'll relax. */ -+ if (address_expr != NULL && mips_opts.rvc) -+ { -+ int compressible_branch = reloc_type == BFD_RELOC_12_PCREL && -+ (INSN_MATCHES(*ip, BEQ) || INSN_MATCHES(*ip, BNE)); -+ int compressible_jump = reloc_type == BFD_RELOC_MIPS_JMP && -+ INSN_MATCHES(*ip, JAL); -+ if(compressible_branch || compressible_jump) -+ { -+ if(riscv_rvc_compress(ip)) -+ { -+ add_relaxed_insn(ip, 4 /* worst case length */, 0, -+ RELAX_BRANCH_ENCODE(compressible_jump, 0), -+ address_expr->X_add_symbol, -+ address_expr->X_add_number); -+ reloc_type = BFD_RELOC_UNUSED; -+ return; -+ } -+ } -+ } -+#endif -+ -+ if (address_expr != NULL) -+ { -+ if (address_expr->X_op == O_constant) -+ { -+ switch (reloc_type) -+ { -+ case BFD_RELOC_32: -+ ip->insn_opcode |= address_expr->X_add_number; -+ break; -+ -+ case BFD_RELOC_RISCV_HI20: -+ ip->insn_opcode |= ENCODE_UTYPE_IMM ( -+ RISCV_LUI_HIGH_PART (address_expr->X_add_number)); -+ break; -+ -+ case BFD_RELOC_RISCV_LO12_S: -+ ip->insn_opcode |= ENCODE_STYPE_IMM (address_expr->X_add_number); -+ break; -+ -+ case BFD_RELOC_UNUSED: -+ case BFD_RELOC_RISCV_LO12_I: -+ ip->insn_opcode |= ENCODE_ITYPE_IMM (address_expr->X_add_number); -+ break; -+ -+ default: -+ internalError (); -+ } -+ reloc_type = BFD_RELOC_UNUSED; -+ } -+ else if (reloc_type == BFD_RELOC_12_PCREL) -+ { -+ add_relaxed_insn (ip, relaxed_branch_length (NULL, NULL, 0), 4, -+ RELAX_BRANCH_ENCODE (0, 0, 0), -+ address_expr->X_add_symbol, -+ address_expr->X_add_number); -+ return; -+ } -+ else if (reloc_type < BFD_RELOC_UNUSED) -+ { -+ reloc_howto_type *howto; -+ -+ howto = bfd_reloc_type_lookup (stdoutput, reloc_type); -+ if (howto == NULL) -+ as_bad (_("Unsupported MIPS relocation number %d"), reloc_type); -+ -+ ip->fixp = fix_new_exp (ip->frag, ip->where, -+ bfd_get_reloc_size (howto), -+ address_expr, -+ reloc_type == BFD_RELOC_12_PCREL || -+ reloc_type == BFD_RELOC_RISCV_CALL || -+ reloc_type == BFD_RELOC_MIPS_JMP, -+ reloc_type); -+ -+ /* These relocations can have an addend that won't fit in -+ 4 octets for 64bit assembly. */ -+ if (rv64 -+ && ! howto->partial_inplace -+ && (reloc_type == BFD_RELOC_32 -+ || reloc_type == BFD_RELOC_64 -+ || reloc_type == BFD_RELOC_CTOR -+ || reloc_type == BFD_RELOC_RISCV_HI20 -+ || reloc_type == BFD_RELOC_RISCV_LO12_I -+ || reloc_type == BFD_RELOC_RISCV_LO12_S)) -+ ip->fixp->fx_no_overflow = 1; -+ } -+ } -+ -+#if 0 -+ if (compressible) -+ riscv_rvc_compress(ip); -+#endif -+ add_fixed_insn (ip); -+ -+ install_insn (ip); -+ -+ /* We just output an insn, so the next one doesn't have a label. */ -+ mips_clear_insn_labels (); -+} -+ -+/* Build an instruction created by a macro expansion. This is passed -+ a pointer to the count of instructions created so far, an -+ expression, the name of the instruction to build, an operand format -+ string, and corresponding arguments. */ -+ -+static void -+macro_build (expressionS *ep, const char *name, const char *fmt, ...) -+{ -+ const struct riscv_opcode *mo; -+ struct mips_cl_insn insn; -+ bfd_reloc_code_real_type r; -+ va_list args; -+ -+ va_start (args, fmt); -+ -+ r = BFD_RELOC_UNUSED; -+ mo = (struct riscv_opcode *) hash_find (op_hash, name); -+ gas_assert (mo); -+ gas_assert (strcmp (name, mo->name) == 0); -+ -+ create_insn (&insn, mo); -+ for (;;) -+ { -+ switch (*fmt++) -+ { -+ case 'd': -+ INSERT_OPERAND (RD, insn, va_arg (args, int)); -+ continue; -+ -+ case 's': -+ INSERT_OPERAND (RS1, insn, va_arg (args, int)); -+ continue; -+ -+ case 't': -+ INSERT_OPERAND (RS2, insn, va_arg (args, int)); -+ continue; -+ -+ case '>': -+ INSERT_OPERAND (SHAMT, insn, va_arg (args, int)); -+ continue; -+ -+ case 'j': -+ case 'u': -+ case 'q': -+ gas_assert (ep != NULL); -+ r = va_arg (args, int); -+ continue; -+ -+ case '\0': -+ break; -+ case ',': -+ continue; -+ default: -+ internalError (); -+ } -+ break; -+ } -+ va_end (args); -+ gas_assert (r == BFD_RELOC_UNUSED ? ep == NULL : ep != NULL); -+ -+ append_insn (&insn, ep, r); -+} -+ -+/* -+ * Sign-extend 32-bit mode constants that have bit 31 set and all -+ * higher bits unset. -+ */ -+static void -+normalize_constant_expr (expressionS *ex) -+{ -+ if (rv64) -+ return; -+ if (ex->X_op == O_constant -+ && IS_ZEXT_32BIT_NUM (ex->X_add_number)) -+ ex->X_add_number = (((ex->X_add_number & 0xffffffff) ^ 0x80000000) -+ - 0x80000000); -+} -+ -+/* -+ * Sign-extend 32-bit mode address offsets that have bit 31 set and -+ * all higher bits unset. -+ */ -+static void -+normalize_address_expr (expressionS *ex) -+{ -+ if (((ex->X_op == O_constant && HAVE_32BIT_ADDRESSES) -+ || (ex->X_op == O_symbol && HAVE_32BIT_SYMBOLS)) -+ && IS_ZEXT_32BIT_NUM (ex->X_add_number)) -+ ex->X_add_number = (((ex->X_add_number & 0xffffffff) ^ 0x80000000) -+ - 0x80000000); -+} -+ -+/* Load an entry from the GOT. */ -+static void -+pcrel_access (int destreg, int tempreg, expressionS *ep, -+ const char* lo_insn, const char* lo_pattern, -+ bfd_reloc_code_real_type hi_reloc, -+ bfd_reloc_code_real_type lo_reloc) -+{ -+ macro_build (ep, "auipc", "d,u", tempreg, hi_reloc); -+ macro_build (ep, lo_insn, lo_pattern, destreg, tempreg, lo_reloc); -+} -+ -+static void -+pcrel_load (int destreg, int tempreg, expressionS *ep, const char* lo_insn, -+ bfd_reloc_code_real_type hi_reloc, -+ bfd_reloc_code_real_type lo_reloc) -+{ -+ pcrel_access (destreg, tempreg, ep, lo_insn, "d,s,j", hi_reloc, lo_reloc); -+} -+ -+static void -+pcrel_store (int srcreg, int tempreg, expressionS *ep, const char* lo_insn, -+ bfd_reloc_code_real_type hi_reloc, -+ bfd_reloc_code_real_type lo_reloc) -+{ -+ pcrel_access (srcreg, tempreg, ep, lo_insn, "t,s,q", hi_reloc, lo_reloc); -+} -+ -+static void -+pcrel_vf (int tempreg, expressionS *ep, -+ bfd_reloc_code_real_type hi_reloc, -+ bfd_reloc_code_real_type lo_reloc) -+{ -+ macro_build (ep, "auipc", "d,u", tempreg, hi_reloc); -+ macro_build (ep, "vf", "s,q", tempreg, lo_reloc); -+} -+ -+/* PC-relative function call using AUIPC/JALR, relaxed to JAL. */ -+static void -+riscv_call (int destreg, int tempreg, expressionS *ep, -+ bfd_reloc_code_real_type reloc) -+{ -+ macro_build (ep, "auipc", "d,u", tempreg, reloc); -+ macro_build (NULL, "jalr", "d,s", destreg, tempreg); -+} -+ -+/* Warn if an expression is not a constant. */ -+ -+static void -+check_absolute_expr (struct mips_cl_insn *ip, expressionS *ex) -+{ -+ if (ex->X_op == O_big) -+ as_bad (_("unsupported large constant")); -+ else if (ex->X_op != O_constant) -+ as_bad (_("Instruction %s requires absolute expression"), -+ ip->insn_mo->name); -+ normalize_constant_expr (ex); -+} -+ -+/* load_const generates an unoptimized instruction sequence to load -+ * an absolute expression into a register. */ -+static void -+load_const (int reg, expressionS *ep) -+{ -+ gas_assert (ep->X_op == O_constant); -+ gas_assert (reg != ZERO); -+ -+ // this is an awful way to generate arbitrary 64-bit constants. -+ // fortunately, this is just used for hand-coded assembly programs. -+ if (rv64 && !IS_SEXT_32BIT_NUM(ep->X_add_number)) -+ { -+ expressionS upper = *ep, lower = *ep; -+ upper.X_add_number = (int64_t)ep->X_add_number >> (RISCV_IMM_BITS-1); -+ load_const(reg, &upper); -+ -+ macro_build (NULL, "slli", "d,s,>", reg, reg, RISCV_IMM_BITS-1); -+ -+ lower.X_add_number = ep->X_add_number & (RISCV_IMM_REACH/2-1); -+ if (lower.X_add_number != 0) -+ macro_build (&lower, "addi", "d,s,j", reg, reg, BFD_RELOC_RISCV_LO12_I); -+ } -+ else // load a sign-extended 32-bit constant -+ { -+ int hi_reg = ZERO; -+ -+ int32_t hi = ep->X_add_number & (RISCV_IMM_REACH-1); -+ hi = hi << (32-RISCV_IMM_BITS) >> (32-RISCV_IMM_BITS); -+ hi = (int32_t)ep->X_add_number - hi; -+ if(hi) -+ { -+ macro_build (ep, "lui", "d,u", reg, BFD_RELOC_RISCV_HI20); -+ hi_reg = reg; -+ } -+ -+ if((ep->X_add_number & (RISCV_IMM_REACH-1)) || hi_reg == ZERO) -+ macro_build (ep, ADD32_INSN, "d,s,j", reg, hi_reg, BFD_RELOC_RISCV_LO12_I); -+ } -+} -+ -+/* -+ * Build macros -+ * This routine implements the seemingly endless macro or synthesized -+ * instructions and addressing modes in the mips assembly language. Many -+ * of these macros are simple and are similar to each other. These could -+ * probably be handled by some kind of table or grammar approach instead of -+ * this verbose method. Others are not simple macros but are more like -+ * optimizing code generation. -+ * One interesting optimization is when several store macros appear -+ * consecutively that would load AT with the upper half of the same address. -+ * The ensuing load upper instructions are ommited. This implies some kind -+ * of global optimization. We currently only optimize within a single macro. -+ * For many of the load and store macros if the address is specified as a -+ * constant expression in the first 64k of memory (ie ld $2,0x4000c) we -+ * first load register 'at' with zero and use it as the base register. The -+ * mips assembler simply uses register $zero. Just one tiny optimization -+ * we're missing. -+ */ -+static void -+macro (struct mips_cl_insn *ip) -+{ -+ unsigned int rd, rs1, rs2; -+ int mask; -+ -+ rd = (ip->insn_opcode >> OP_SH_RD) & OP_MASK_RD; -+ rs1 = (ip->insn_opcode >> OP_SH_RS1) & OP_MASK_RS1; -+ rs2 = (ip->insn_opcode >> OP_SH_RS2) & OP_MASK_RS2; -+ mask = ip->insn_mo->mask; -+ -+ switch (mask) -+ { -+ case M_LI: -+ load_const (rd, &imm_expr); -+ break; -+ -+ case M_LA: -+ case M_LLA: -+ /* Load the address of a symbol into a register. */ -+ if (!IS_SEXT_32BIT_NUM (offset_expr.X_add_number)) -+ as_bad(_("offset too large")); -+ -+ if (offset_expr.X_op == O_constant) -+ load_const (rd, &offset_expr); -+ else if (is_pic && mask == M_LA) /* Global PIC symbol */ -+ pcrel_load (rd, rd, &offset_expr, LOAD_ADDRESS_INSN, -+ BFD_RELOC_RISCV_GOT_HI20, BFD_RELOC_RISCV_GOT_LO12); -+ else /* Local PIC symbol, or any non-PIC symbol */ -+ pcrel_load (rd, rd, &offset_expr, "addi", -+ BFD_RELOC_RISCV_PCREL_HI20, BFD_RELOC_RISCV_PCREL_LO12_I); -+ break; -+ -+ case M_LA_TLS_GD: -+ pcrel_load (rd, rd, &offset_expr, "addi", -+ BFD_RELOC_RISCV_TLS_GD_HI20, BFD_RELOC_RISCV_TLS_GD_LO12); -+ break; -+ -+ case M_LA_TLS_IE: -+ pcrel_load (rd, rd, &offset_expr, LOAD_ADDRESS_INSN, -+ BFD_RELOC_RISCV_TLS_GOT_HI20, BFD_RELOC_RISCV_TLS_GOT_LO12); -+ break; -+ -+ case M_LB: -+ pcrel_load (rd, rd, &offset_expr, "lb", -+ BFD_RELOC_RISCV_PCREL_HI20, BFD_RELOC_RISCV_PCREL_LO12_I); -+ break; -+ -+ case M_LBU: -+ pcrel_load (rd, rd, &offset_expr, "lbu", -+ BFD_RELOC_RISCV_PCREL_HI20, BFD_RELOC_RISCV_PCREL_LO12_I); -+ break; -+ -+ case M_LH: -+ pcrel_load (rd, rd, &offset_expr, "lh", -+ BFD_RELOC_RISCV_PCREL_HI20, BFD_RELOC_RISCV_PCREL_LO12_I); -+ break; -+ -+ case M_LHU: -+ pcrel_load (rd, rd, &offset_expr, "lhu", -+ BFD_RELOC_RISCV_PCREL_HI20, BFD_RELOC_RISCV_PCREL_LO12_I); -+ break; -+ -+ case M_LW: -+ pcrel_load (rd, rd, &offset_expr, "lw", -+ BFD_RELOC_RISCV_PCREL_HI20, BFD_RELOC_RISCV_PCREL_LO12_I); -+ break; -+ -+ case M_LWU: -+ pcrel_load (rd, rd, &offset_expr, "lwu", -+ BFD_RELOC_RISCV_PCREL_HI20, BFD_RELOC_RISCV_PCREL_LO12_I); -+ break; -+ -+ case M_LD: -+ pcrel_load (rd, rd, &offset_expr, "ld", -+ BFD_RELOC_RISCV_PCREL_HI20, BFD_RELOC_RISCV_PCREL_LO12_I); -+ break; -+ -+ case M_FLW: -+ pcrel_load (rd, rs1, &offset_expr, "flw", -+ BFD_RELOC_RISCV_PCREL_HI20, BFD_RELOC_RISCV_PCREL_LO12_I); -+ break; -+ -+ case M_FLD: -+ pcrel_load (rd, rs1, &offset_expr, "fld", -+ BFD_RELOC_RISCV_PCREL_HI20, BFD_RELOC_RISCV_PCREL_LO12_I); -+ break; -+ -+ case M_SB: -+ pcrel_store (rs2, rs1, &offset_expr, "sb", -+ BFD_RELOC_RISCV_PCREL_HI20, BFD_RELOC_RISCV_PCREL_LO12_S); -+ break; -+ -+ case M_SH: -+ pcrel_store (rs2, rs1, &offset_expr, "sh", -+ BFD_RELOC_RISCV_PCREL_HI20, BFD_RELOC_RISCV_PCREL_LO12_S); -+ break; -+ -+ case M_SW: -+ pcrel_store (rs2, rs1, &offset_expr, "sw", -+ BFD_RELOC_RISCV_PCREL_HI20, BFD_RELOC_RISCV_PCREL_LO12_S); -+ break; -+ -+ case M_SD: -+ pcrel_store (rs2, rs1, &offset_expr, "sd", -+ BFD_RELOC_RISCV_PCREL_HI20, BFD_RELOC_RISCV_PCREL_LO12_S); -+ break; -+ -+ case M_FSW: -+ pcrel_store (rs2, rs1, &offset_expr, "fsw", -+ BFD_RELOC_RISCV_PCREL_HI20, BFD_RELOC_RISCV_PCREL_LO12_S); -+ break; -+ -+ case M_FSD: -+ pcrel_store (rs2, rs1, &offset_expr, "fsd", -+ BFD_RELOC_RISCV_PCREL_HI20, BFD_RELOC_RISCV_PCREL_LO12_S); -+ break; -+ -+ case M_VF: -+ pcrel_vf (rs1, &offset_expr, -+ BFD_RELOC_RISCV_PCREL_HI20, BFD_RELOC_RISCV_PCREL_LO12_S); -+ break; -+ -+ case M_JUMP: -+ rd = 0; -+ goto do_call; -+ case M_CALL: -+ rd = LINK_REG; -+do_call: -+ rs1 = reg_lookup_assert ("t0", RTYPE_GP); -+ riscv_call (rd, rs1, &offset_expr, offset_reloc); -+ break; -+ -+ default: -+ as_bad (_("Macro %s not implemented"), ip->insn_mo->name); -+ break; -+ } -+} -+ -+/* For consistency checking, verify that all bits are specified either -+ by the match/mask part of the instruction definition, or by the -+ operand list. */ -+static int -+validate_mips_insn (const struct riscv_opcode *opc) -+{ -+ const char *p = opc->args; -+ char c; -+ insn_t required_bits, used_bits = opc->mask; -+ -+ if ((used_bits & opc->match) != opc->match) -+ { -+ as_bad (_("internal: bad mips opcode (mask error): %s %s"), -+ opc->name, opc->args); -+ return 0; -+ } -+ required_bits = ((insn_t)1 << (8 * riscv_insn_length (opc->match))) - 1; -+ -+#define USE_BITS(mask,shift) (used_bits |= ((insn_t)(mask) << (shift))) -+ while (*p) -+ switch (c = *p++) -+ { -+ /* Xcustom */ -+ case '^': -+ switch (c = *p++) -+ { -+ case 'd': USE_BITS (OP_MASK_RD, OP_SH_RD); break; -+ case 's': USE_BITS (OP_MASK_RS1, OP_SH_RS1); break; -+ case 't': USE_BITS (OP_MASK_RS2, OP_SH_RS2); break; -+ case 'j': USE_BITS (OP_MASK_CUSTOM_IMM, OP_SH_CUSTOM_IMM); break; -+ } -+ break; -+ /* Xhwacha */ -+ case '#': -+ switch (c = *p++) -+ { -+ case 'g': USE_BITS (OP_MASK_IMMNGPR, OP_SH_IMMNGPR); break; -+ case 'f': USE_BITS (OP_MASK_IMMNFPR, OP_SH_IMMNFPR); break; -+ case 'n': USE_BITS (OP_MASK_IMMSEGNELM, OP_SH_IMMSEGNELM); break; -+ case 'd': USE_BITS (OP_MASK_VRD, OP_SH_VRD); break; -+ case 's': USE_BITS (OP_MASK_VRS, OP_SH_VRS); break; -+ case 't': USE_BITS (OP_MASK_VRT, OP_SH_VRT); break; -+ case 'r': USE_BITS (OP_MASK_VRR, OP_SH_VRR); break; -+ case 'D': USE_BITS (OP_MASK_VFD, OP_SH_VFD); break; -+ case 'S': USE_BITS (OP_MASK_VFS, OP_SH_VFS); break; -+ case 'T': USE_BITS (OP_MASK_VFT, OP_SH_VFT); break; -+ case 'R': USE_BITS (OP_MASK_VFR, OP_SH_VFR); break; -+ -+ default: -+ as_bad (_("internal: bad mips opcode (unknown extension operand type `#%c'): %s %s"), -+ c, opc->name, opc->args); -+ return 0; -+ } -+ break; -+ case ',': break; -+ case '(': break; -+ case ')': break; -+ case '<': USE_BITS (OP_MASK_SHAMTW, OP_SH_SHAMTW); break; -+ case '>': USE_BITS (OP_MASK_SHAMT, OP_SH_SHAMT); break; -+ case 'A': break; -+ case 'D': USE_BITS (OP_MASK_RD, OP_SH_RD); break; -+ case 'Z': USE_BITS (OP_MASK_RS1, OP_SH_RS1); break; -+ case 'E': USE_BITS (OP_MASK_CSR, OP_SH_CSR); break; -+ case 'I': break; -+ case 'R': USE_BITS (OP_MASK_RS3, OP_SH_RS3); break; -+ case 'S': USE_BITS (OP_MASK_RS1, OP_SH_RS1); break; -+ case 'U': USE_BITS (OP_MASK_RS1, OP_SH_RS1); /* fallthru */ -+ case 'T': USE_BITS (OP_MASK_RS2, OP_SH_RS2); break; -+ case 'd': USE_BITS (OP_MASK_RD, OP_SH_RD); break; -+ case 'm': USE_BITS (OP_MASK_RM, OP_SH_RM); break; -+ case 's': USE_BITS (OP_MASK_RS1, OP_SH_RS1); break; -+ case 't': USE_BITS (OP_MASK_RS2, OP_SH_RS2); break; -+ case 'P': USE_BITS (OP_MASK_PRED, OP_SH_PRED); break; -+ case 'Q': USE_BITS (OP_MASK_SUCC, OP_SH_SUCC); break; -+ case 'o': -+ case 'j': used_bits |= ENCODE_ITYPE_IMM(-1U); break; -+ case 'a': used_bits |= ENCODE_UJTYPE_IMM(-1U); break; -+ case 'p': used_bits |= ENCODE_SBTYPE_IMM(-1U); break; -+ case 'q': used_bits |= ENCODE_STYPE_IMM(-1U); break; -+ case 'u': used_bits |= ENCODE_UTYPE_IMM(-1U); break; -+ case '[': break; -+ case ']': break; -+ case '0': break; -+ default: -+ as_bad (_("internal: bad mips opcode (unknown operand type `%c'): %s %s"), -+ c, opc->name, opc->args); -+ return 0; -+ } -+#undef USE_BITS -+ if (used_bits != required_bits) -+ { -+ as_bad (_("internal: bad mips opcode (bits 0x%lx undefined): %s %s"), -+ ~(long)(used_bits & required_bits), opc->name, opc->args); -+ return 0; -+ } -+ return 1; -+} -+ -+struct percent_op_match -+{ -+ const char *str; -+ bfd_reloc_code_real_type reloc; -+}; -+ -+static const struct percent_op_match percent_op_utype[] = -+{ -+ {"%tprel_hi", BFD_RELOC_RISCV_TPREL_HI20}, -+ {"%tls_ie_hi", BFD_RELOC_RISCV_TLS_IE_HI20}, -+ {"%hi", BFD_RELOC_RISCV_HI20}, -+ {0, 0} -+}; -+ -+static const struct percent_op_match percent_op_itype[] = -+{ -+ {"%lo", BFD_RELOC_RISCV_LO12_I}, -+ {"%tprel_lo", BFD_RELOC_RISCV_TPREL_LO12_I}, -+ {"%tls_ie_lo", BFD_RELOC_RISCV_TLS_IE_LO12}, -+ {"%tls_ie_off", BFD_RELOC_RISCV_TLS_IE_LO12_I}, -+ {0, 0} -+}; -+ -+static const struct percent_op_match percent_op_stype[] = -+{ -+ {"%lo", BFD_RELOC_RISCV_LO12_S}, -+ {"%tprel_lo", BFD_RELOC_RISCV_TPREL_LO12_S}, -+ {"%tls_ie_off", BFD_RELOC_RISCV_TLS_IE_LO12_S}, -+ {0, 0} -+}; -+ -+static const struct percent_op_match percent_op_rtype[] = -+{ -+ {"%tprel_add", BFD_RELOC_RISCV_TPREL_ADD}, -+ {"%tls_ie_add", BFD_RELOC_RISCV_TLS_IE_ADD}, -+ {0, 0} -+}; -+ -+/* Return true if *STR points to a relocation operator. When returning true, -+ move *STR over the operator and store its relocation code in *RELOC. -+ Leave both *STR and *RELOC alone when returning false. */ -+ -+static bfd_boolean -+parse_relocation (char **str, bfd_reloc_code_real_type *reloc, -+ const struct percent_op_match *percent_op) -+{ -+ for ( ; percent_op->str; percent_op++) -+ if (strncasecmp (*str, percent_op->str, strlen (percent_op->str)) == 0) -+ { -+ int len = strlen (percent_op->str); -+ -+ if (!ISSPACE ((*str)[len]) && (*str)[len] != '(') -+ continue; -+ -+ *str += strlen (percent_op->str); -+ *reloc = percent_op->reloc; -+ -+ /* Check whether the output BFD supports this relocation. -+ If not, issue an error and fall back on something safe. */ -+ if (!bfd_reloc_type_lookup (stdoutput, percent_op->reloc)) -+ { -+ as_bad ("relocation %s isn't supported by the current ABI", -+ percent_op->str); -+ *reloc = BFD_RELOC_UNUSED; -+ } -+ return TRUE; -+ } -+ return FALSE; -+} -+ -+ -+/* Parse string STR as a 16-bit relocatable operand. Store the -+ expression in *EP and the relocation, if any, in RELOC. -+ Return the number of relocation operators used (0 or 1). -+ -+ On exit, EXPR_END points to the first character after the expression. */ -+ -+static size_t -+my_getSmallExpression (expressionS *ep, bfd_reloc_code_real_type *reloc, -+ char *str, const struct percent_op_match *percent_op) -+{ -+ size_t reloc_index; -+ int crux_depth, str_depth; -+ char *crux; -+ -+ /* Search for the start of the main expression. -+ End the loop with CRUX pointing to the start -+ of the main expression and with CRUX_DEPTH containing the number -+ of open brackets at that point. */ -+ reloc_index = -1; -+ str_depth = 0; -+ do -+ { -+ reloc_index++; -+ crux = str; -+ crux_depth = str_depth; -+ -+ /* Skip over whitespace and brackets, keeping count of the number -+ of brackets. */ -+ while (*str == ' ' || *str == '\t' || *str == '(') -+ if (*str++ == '(') -+ str_depth++; -+ } -+ while (*str == '%' -+ && reloc_index < 1 -+ && parse_relocation (&str, reloc, percent_op)); -+ -+ my_getExpression (ep, crux); -+ str = expr_end; -+ -+ /* Match every open bracket. */ -+ while (crux_depth > 0 && (*str == ')' || *str == ' ' || *str == '\t')) -+ if (*str++ == ')') -+ crux_depth--; -+ -+ if (crux_depth > 0) -+ as_bad ("unclosed '('"); -+ -+ expr_end = str; -+ -+ return reloc_index; -+} -+ -+/* This routine assembles an instruction into its binary format. As a -+ side effect, it sets one of the global variables imm_reloc or -+ offset_reloc to the type of relocation to do if one of the operands -+ is an address expression. */ -+ -+static void -+mips_ip (char *str, struct mips_cl_insn *ip) -+{ -+ char *s; -+ const char *args; -+ char c = 0; -+ struct riscv_opcode *insn; -+ char *argsStart; -+ unsigned int regno; -+ char save_c = 0; -+ int argnum; -+ unsigned int rtype; -+ const struct percent_op_match *p; -+ -+ insn_error = NULL; -+ -+ /* If the instruction contains a '.', we first try to match an instruction -+ including the '.'. Then we try again without the '.'. */ -+ insn = NULL; -+ for (s = str; *s != '\0' && !ISSPACE (*s); ++s) -+ continue; -+ -+ /* If we stopped on whitespace, then replace the whitespace with null for -+ the call to hash_find. Save the character we replaced just in case we -+ have to re-parse the instruction. */ -+ if (ISSPACE (*s)) -+ { -+ save_c = *s; -+ *s++ = '\0'; -+ } -+ -+ insn = (struct riscv_opcode *) hash_find (op_hash, str); -+ -+ /* If we didn't find the instruction in the opcode table, try again, but -+ this time with just the instruction up to, but not including the -+ first '.'. */ -+ if (insn == NULL) -+ { -+ /* Restore the character we overwrite above (if any). */ -+ if (save_c) -+ *(--s) = save_c; -+ -+ /* Scan up to the first '.' or whitespace. */ -+ for (s = str; -+ *s != '\0' && *s != '.' && !ISSPACE (*s); -+ ++s) -+ continue; -+ -+ /* If we did not find a '.', then we can quit now. */ -+ if (*s != '.') -+ { -+ insn_error = "unrecognized opcode"; -+ return; -+ } -+ -+ /* Lookup the instruction in the hash table. */ -+ *s++ = '\0'; -+ if ((insn = (struct riscv_opcode *) hash_find (op_hash, str)) == NULL) -+ { -+ insn_error = "unrecognized opcode"; -+ return; -+ } -+ } -+ -+ argsStart = s; -+ for (;;) -+ { -+ bfd_boolean ok = TRUE; -+ gas_assert (strcmp (insn->name, str) == 0); -+ -+ create_insn (ip, insn); -+ insn_error = NULL; -+ argnum = 1; -+ for (args = insn->args;; ++args) -+ { -+ s += strspn (s, " \t"); -+ switch (*args) -+ { -+ case '\0': /* end of args */ -+ if (*s == '\0') -+ return; -+ break; -+ /* Xcustom */ -+ case '^': -+ { -+ unsigned long max = OP_MASK_RD; -+ my_getExpression (&imm_expr, s); -+ check_absolute_expr (ip, &imm_expr); -+ switch (*++args) -+ { -+ case 'j': -+ max = OP_MASK_CUSTOM_IMM; -+ INSERT_OPERAND (CUSTOM_IMM, *ip, imm_expr.X_add_number); -+ break; -+ case 'd': -+ INSERT_OPERAND (RD, *ip, imm_expr.X_add_number); -+ break; -+ case 's': -+ INSERT_OPERAND (RS1, *ip, imm_expr.X_add_number); -+ break; -+ case 't': -+ INSERT_OPERAND (RS2, *ip, imm_expr.X_add_number); -+ break; -+ } -+ imm_expr.X_op = O_absent; -+ s = expr_end; -+ if ((unsigned long) imm_expr.X_add_number > max) -+ as_warn ("Bad custom immediate (%lu), must be at most %lu", -+ (unsigned long)imm_expr.X_add_number, max); -+ continue; -+ } -+ -+ /* Xhwacha */ -+ case '#': -+ switch ( *++args ) -+ { -+ case 'g': -+ my_getExpression( &imm_expr, s ); -+ /* check_absolute_expr( ip, &imm_expr ); */ -+ if ((unsigned long) imm_expr.X_add_number > 32 ) -+ as_warn( _( "Improper ngpr amount (%lu)" ), -+ (unsigned long) imm_expr.X_add_number ); -+ INSERT_OPERAND( IMMNGPR, *ip, imm_expr.X_add_number ); -+ imm_expr.X_op = O_absent; -+ s = expr_end; -+ continue; -+ case 'f': -+ my_getExpression( &imm_expr, s ); -+ /* check_absolute_expr( ip, &imm_expr ); */ -+ if ((unsigned long) imm_expr.X_add_number > 32 ) -+ as_warn( _( "Improper nfpr amount (%lu)" ), -+ (unsigned long) imm_expr.X_add_number ); -+ INSERT_OPERAND( IMMNFPR, *ip, imm_expr.X_add_number ); -+ imm_expr.X_op = O_absent; -+ s = expr_end; -+ continue; -+ case 'n': -+ my_getExpression( &imm_expr, s ); -+ /* check_absolute_expr( ip, &imm_expr ); */ -+ if ((unsigned long) imm_expr.X_add_number > 8 ) -+ as_warn( _( "Improper nelm amount (%lu)" ), -+ (unsigned long) imm_expr.X_add_number ); -+ INSERT_OPERAND( IMMSEGNELM, *ip, imm_expr.X_add_number - 1 ); -+ imm_expr.X_op = O_absent; -+ s = expr_end; -+ continue; -+ case 'd': -+ ok = reg_lookup( &s, RTYPE_NUM|RTYPE_VGR_REG, ®no ); -+ if ( !ok ) -+ as_bad( _( "Invalid vector register" ) ); -+ INSERT_OPERAND( VRD, *ip, regno ); -+ continue; -+ case 's': -+ ok = reg_lookup( &s, RTYPE_NUM|RTYPE_VGR_REG, ®no ); -+ if ( !ok ) -+ as_bad( _( "Invalid vector register" ) ); -+ INSERT_OPERAND( VRS, *ip, regno ); -+ continue; -+ case 't': -+ ok = reg_lookup( &s, RTYPE_NUM|RTYPE_VGR_REG, ®no ); -+ if ( !ok ) -+ as_bad( _( "Invalid vector register" ) ); -+ INSERT_OPERAND( VRT, *ip, regno ); -+ continue; -+ case 'r': -+ ok = reg_lookup( &s, RTYPE_NUM|RTYPE_VGR_REG, ®no ); -+ if ( !ok ) -+ as_bad( _( "Invalid vector register" ) ); -+ INSERT_OPERAND( VRR, *ip, regno ); -+ continue; -+ case 'D': -+ ok = reg_lookup( &s, RTYPE_NUM|RTYPE_VFP_REG, ®no ); -+ if ( !ok ) -+ as_bad( _( "Invalid vector register" ) ); -+ INSERT_OPERAND( VFD, *ip, regno ); -+ continue; -+ case 'S': -+ ok = reg_lookup( &s, RTYPE_NUM|RTYPE_VFP_REG, ®no ); -+ if ( !ok ) -+ as_bad( _( "Invalid vector register" ) ); -+ INSERT_OPERAND( VFS, *ip, regno ); -+ continue; -+ case 'T': -+ ok = reg_lookup( &s, RTYPE_NUM|RTYPE_VFP_REG, ®no ); -+ if ( !ok ) -+ as_bad( _( "Invalid vector register" ) ); -+ INSERT_OPERAND( VFT, *ip, regno ); -+ continue; -+ case 'R': -+ ok = reg_lookup( &s, RTYPE_NUM|RTYPE_VFP_REG, ®no ); -+ if ( !ok ) -+ as_bad( _( "Invalid vector register" ) ); -+ INSERT_OPERAND( VFR, *ip, regno ); -+ continue; -+ } -+ break; -+ -+ case ',': -+ ++argnum; -+ if (*s++ == *args) -+ continue; -+ s--; -+ break; -+ -+ case '(': -+ case ')': -+ case '[': -+ case ']': -+ if (*s++ == *args) -+ continue; -+ break; -+ -+ case '<': /* must be at least one digit */ -+ /* -+ * According to the manual, if the shift amount is greater -+ * than 31 or less than 0, then the shift amount should be -+ * mod 32. In reality the mips assembler issues an error. -+ * We issue a warning and mask out all but the low 5 bits. -+ */ -+ my_getExpression (&imm_expr, s); -+ check_absolute_expr (ip, &imm_expr); -+ if ((unsigned long) imm_expr.X_add_number > 31) -+ as_warn (_("Improper shift amount (%lu)"), -+ (unsigned long) imm_expr.X_add_number); -+ INSERT_OPERAND (SHAMTW, *ip, imm_expr.X_add_number); -+ imm_expr.X_op = O_absent; -+ s = expr_end; -+ continue; -+ -+ case '>': /* shift amount, 0-63 */ -+ my_getExpression (&imm_expr, s); -+ check_absolute_expr (ip, &imm_expr); -+ if ((unsigned long) imm_expr.X_add_number > (rv64 ? 63 : 31)) -+ as_warn (_("Improper shift amount (%lu)"), -+ (unsigned long) imm_expr.X_add_number); -+ INSERT_OPERAND (SHAMT, *ip, imm_expr.X_add_number); -+ imm_expr.X_op = O_absent; -+ s = expr_end; -+ continue; -+ -+ case 'Z': /* CSRRxI immediate */ -+ my_getExpression (&imm_expr, s); -+ check_absolute_expr (ip, &imm_expr); -+ if ((unsigned long) imm_expr.X_add_number > 31) -+ as_warn (_("Improper CSRxI immediate (%lu)"), -+ (unsigned long) imm_expr.X_add_number); -+ INSERT_OPERAND (RS1, *ip, imm_expr.X_add_number); -+ imm_expr.X_op = O_absent; -+ s = expr_end; -+ continue; -+ -+ case 'E': /* Control register. */ -+ ok = reg_lookup (&s, RTYPE_NUM | RTYPE_CP0, ®no); -+ INSERT_OPERAND (CSR, *ip, regno); -+ if (ok) -+ continue; -+ else -+ break; -+ -+ case 'm': /* rounding mode */ -+ if (arg_lookup (&s, riscv_rm, ARRAY_SIZE(riscv_rm), ®no)) -+ { -+ INSERT_OPERAND (RM, *ip, regno); -+ continue; -+ } -+ break; -+ -+ case 'P': -+ case 'Q': /* fence predecessor/successor */ -+ if (arg_lookup (&s, riscv_pred_succ, ARRAY_SIZE(riscv_pred_succ), ®no)) -+ { -+ if (*args == 'P') -+ INSERT_OPERAND(PRED, *ip, regno); -+ else -+ INSERT_OPERAND(SUCC, *ip, regno); -+ continue; -+ } -+ break; -+ -+ case 'd': /* destination register */ -+ case 's': /* source register */ -+ case 't': /* target register */ -+ ok = reg_lookup (&s, RTYPE_NUM | RTYPE_GP, ®no); -+ if (ok) -+ { -+ c = *args; -+ if (*s == ' ') -+ ++s; -+ -+ /* Now that we have assembled one operand, we use the args string -+ * to figure out where it goes in the instruction. */ -+ switch (c) -+ { -+ case 's': -+ INSERT_OPERAND (RS1, *ip, regno); -+ break; -+ case 'd': -+ INSERT_OPERAND (RD, *ip, regno); -+ break; -+ case 't': -+ INSERT_OPERAND (RS2, *ip, regno); -+ break; -+ } -+ continue; -+ } -+ break; -+ -+ case 'D': /* floating point rd */ -+ case 'S': /* floating point rs1 */ -+ case 'T': /* floating point rs2 */ -+ case 'U': /* floating point rs1 and rs2 */ -+ case 'R': /* floating point rs3 */ -+ rtype = RTYPE_FPU; -+ if (reg_lookup (&s, rtype, ®no)) -+ { -+ c = *args; -+ if (*s == ' ') -+ ++s; -+ switch (c) -+ { -+ case 'D': -+ INSERT_OPERAND (RD, *ip, regno); -+ break; -+ case 'S': -+ INSERT_OPERAND (RS1, *ip, regno); -+ break; -+ case 'U': -+ INSERT_OPERAND (RS1, *ip, regno); -+ /* fallthru */ -+ case 'T': -+ INSERT_OPERAND (RS2, *ip, regno); -+ break; -+ case 'R': -+ INSERT_OPERAND (RS3, *ip, regno); -+ break; -+ } -+ continue; -+ } -+ -+ break; -+ -+ case 'I': -+ my_getExpression (&imm_expr, s); -+ if (imm_expr.X_op != O_big -+ && imm_expr.X_op != O_constant) -+ insn_error = _("absolute expression required"); -+ normalize_constant_expr (&imm_expr); -+ s = expr_end; -+ continue; -+ -+ case 'A': -+ my_getExpression (&offset_expr, s); -+ normalize_address_expr (&offset_expr); -+ imm_reloc = BFD_RELOC_32; -+ s = expr_end; -+ continue; -+ -+ case 'j': /* sign-extended immediate */ -+ imm_reloc = BFD_RELOC_RISCV_LO12_I; -+ p = percent_op_itype; -+ goto alu_op; -+ case 'q': /* store displacement */ -+ p = percent_op_stype; -+ offset_reloc = BFD_RELOC_RISCV_LO12_S; -+ goto load_store; -+ case 'o': /* load displacement */ -+ p = percent_op_itype; -+ offset_reloc = BFD_RELOC_RISCV_LO12_I; -+ goto load_store; -+ case '0': /* AMO "displacement," which must be zero */ -+ p = percent_op_rtype; -+ offset_reloc = BFD_RELOC_UNUSED; -+load_store: -+ /* Check whether there is only a single bracketed expression -+ left. If so, it must be the base register and the -+ constant must be zero. */ -+ offset_expr.X_op = O_constant; -+ offset_expr.X_add_number = 0; -+ if (*s == '(' && strchr (s + 1, '(') == 0) -+ continue; -+alu_op: -+ /* If this value won't fit into a 16 bit offset, then go -+ find a macro that will generate the 32 bit offset -+ code pattern. */ -+ if (!my_getSmallExpression (&offset_expr, &offset_reloc, s, p)) -+ { -+ normalize_constant_expr (&offset_expr); -+ if (offset_expr.X_op != O_constant -+ || (*args == '0' && offset_expr.X_add_number != 0) -+ || offset_expr.X_add_number >= (signed)RISCV_IMM_REACH/2 -+ || offset_expr.X_add_number < -(signed)RISCV_IMM_REACH/2) -+ break; -+ } -+ -+ s = expr_end; -+ continue; -+ -+ case 'p': /* pc relative offset */ -+ offset_reloc = BFD_RELOC_12_PCREL; -+ my_getExpression (&offset_expr, s); -+ s = expr_end; -+ continue; -+ -+ case 'u': /* upper 20 bits */ -+ p = percent_op_utype; -+ if (!my_getSmallExpression (&imm_expr, &imm_reloc, s, p) -+ && imm_expr.X_op == O_constant) -+ { -+ if (imm_expr.X_add_number < 0 -+ || imm_expr.X_add_number >= (signed)RISCV_BIGIMM_REACH) -+ as_bad (_("lui expression not in range 0..1048575")); -+ -+ imm_reloc = BFD_RELOC_RISCV_HI20; -+ imm_expr.X_add_number <<= RISCV_IMM_BITS; -+ } -+ s = expr_end; -+ continue; -+ -+ case 'a': /* 26 bit address */ -+ my_getExpression (&offset_expr, s); -+ s = expr_end; -+ offset_reloc = BFD_RELOC_MIPS_JMP; -+ continue; -+ -+ case 'c': -+ my_getExpression (&offset_expr, s); -+ s = expr_end; -+ offset_reloc = BFD_RELOC_RISCV_CALL; -+ if (*s == '@') -+ offset_reloc = BFD_RELOC_RISCV_CALL_PLT, s++; -+ continue; -+ -+ default: -+ as_bad (_("bad char = '%c'\n"), *args); -+ internalError (); -+ } -+ break; -+ } -+ /* Args don't match. */ -+ if (insn + 1 < &riscv_opcodes[NUMOPCODES] && -+ !strcmp (insn->name, insn[1].name)) -+ { -+ ++insn; -+ s = argsStart; -+ insn_error = _("illegal operands"); -+ continue; -+ } -+ if (save_c) -+ *(--argsStart) = save_c; -+ insn_error = _("illegal operands"); -+ return; -+ } -+} -+ -+static void -+my_getExpression (expressionS *ep, char *str) -+{ -+ char *save_in; -+ -+ save_in = input_line_pointer; -+ input_line_pointer = str; -+ expression (ep); -+ expr_end = input_line_pointer; -+ input_line_pointer = save_in; -+} -+ -+char * -+md_atof (int type, char *litP, int *sizeP) -+{ -+ return ieee_md_atof (type, litP, sizeP, TARGET_BYTES_BIG_ENDIAN); -+} -+ -+void -+md_number_to_chars (char *buf, valueT val, int n) -+{ -+ number_to_chars_littleendian (buf, val, n); -+} -+ -+const char *md_shortopts = "O::g::G:"; -+ -+enum options -+ { -+ OPTION_M32 = OPTION_MD_BASE, -+ OPTION_M64, -+ OPTION_MARCH, -+ OPTION_PIC, -+ OPTION_NO_PIC, -+ OPTION_MRVC, -+ OPTION_MNO_RVC, -+ OPTION_END_OF_ENUM -+ }; -+ -+struct option md_longopts[] = -+{ -+ {"m32", no_argument, NULL, OPTION_M32}, -+ {"m64", no_argument, NULL, OPTION_M64}, -+ {"march", required_argument, NULL, OPTION_MARCH}, -+ {"fPIC", no_argument, NULL, OPTION_PIC}, -+ {"fpic", no_argument, NULL, OPTION_PIC}, -+ {"fno-pic", no_argument, NULL, OPTION_NO_PIC}, -+ {"mrvc", no_argument, NULL, OPTION_MRVC}, -+ {"mno-rvc", no_argument, NULL, OPTION_MNO_RVC}, -+ -+ {NULL, no_argument, NULL, 0} -+}; -+size_t md_longopts_size = sizeof (md_longopts); -+ -+int -+md_parse_option (int c, char *arg) -+{ -+ switch (c) -+ { -+ case 'g': -+ if (arg == NULL) -+ mips_debug = 2; -+ else -+ mips_debug = atoi (arg); -+ break; -+ -+ case OPTION_MRVC: -+ mips_opts.rvc = 1; -+ break; -+ -+ case OPTION_MNO_RVC: -+ mips_opts.rvc = 0; -+ break; -+ -+ case OPTION_M32: -+ rv64 = FALSE; -+ break; -+ -+ case OPTION_M64: -+ rv64 = TRUE; -+ break; -+ -+ case OPTION_MARCH: -+ riscv_set_arch(arg); -+ -+ case OPTION_NO_PIC: -+ is_pic = FALSE; -+ break; -+ -+ case OPTION_PIC: -+ is_pic = TRUE; -+ break; -+ -+ default: -+ return 0; -+ } -+ -+ return 1; -+} -+ -+void -+mips_after_parse_args (void) -+{ -+ if (riscv_subsets == NULL) -+ riscv_set_arch("RVIMAFDXcustom"); -+} -+ -+void -+mips_init_after_args (void) -+{ -+ /* initialize opcodes */ -+ bfd_riscv_num_opcodes = bfd_riscv_num_builtin_opcodes; -+ riscv_opcodes = (struct riscv_opcode *) riscv_builtin_opcodes; -+} -+ -+long -+md_pcrel_from (fixS *fixP) -+{ -+ return fixP->fx_where + fixP->fx_frag->fr_address; -+} -+ -+/* Apply a fixup to the object file. */ -+ -+void -+md_apply_fix (fixS *fixP, valueT *valP, segT seg ATTRIBUTE_UNUSED) -+{ -+ bfd_byte *buf = (bfd_byte *) (fixP->fx_frag->fr_literal + fixP->fx_where); -+ bfd_reloc_code_real_type pcrel_r_type; -+ -+ /* We ignore generic BFD relocations we don't know about. */ -+ if (! bfd_reloc_type_lookup (stdoutput, fixP->fx_r_type)) -+ return; -+ -+ /* Remember value for tc_gen_reloc. */ -+ fixP->fx_addnumber = *valP; -+ -+ switch (fixP->fx_r_type) -+ { -+ case BFD_RELOC_MIPS_TLS_DTPREL32: -+ case BFD_RELOC_MIPS_TLS_DTPREL64: -+ case BFD_RELOC_RISCV_TPREL_HI20: -+ case BFD_RELOC_RISCV_TPREL_LO12_I: -+ case BFD_RELOC_RISCV_TPREL_LO12_S: -+ case BFD_RELOC_RISCV_TPREL_ADD: -+ case BFD_RELOC_RISCV_TLS_IE_HI20: -+ case BFD_RELOC_RISCV_TLS_IE_LO12: -+ case BFD_RELOC_RISCV_TLS_IE_ADD: -+ case BFD_RELOC_RISCV_TLS_IE_LO12_I: -+ case BFD_RELOC_RISCV_TLS_IE_LO12_S: -+ S_SET_THREAD_LOCAL (fixP->fx_addsy); -+ /* fall through */ -+ -+ case BFD_RELOC_RISCV_TLS_GOT_HI20: -+ case BFD_RELOC_RISCV_TLS_GD_HI20: -+ case BFD_RELOC_RISCV_GOT_HI20: -+ case BFD_RELOC_RISCV_PCREL_HI20: -+ case BFD_RELOC_RISCV_HI20: -+ case BFD_RELOC_RISCV_LO12_I: -+ case BFD_RELOC_RISCV_LO12_S: -+ case BFD_RELOC_RISCV_ADD32: -+ case BFD_RELOC_RISCV_ADD64: -+ case BFD_RELOC_RISCV_SUB32: -+ case BFD_RELOC_RISCV_SUB64: -+ gas_assert (fixP->fx_addsy != NULL); -+ /* Nothing needed to do. The value comes from the reloc entry. */ -+ return; -+ -+ case BFD_RELOC_64: -+ case BFD_RELOC_32: -+ if (fixP->fx_addsy && fixP->fx_subsy) -+ { -+ fixP->fx_next = xmemdup (fixP, sizeof (*fixP), sizeof (*fixP)); -+ fixP->fx_next->fx_addsy = fixP->fx_subsy; -+ fixP->fx_next->fx_subsy = NULL; -+ fixP->fx_next->fx_offset = 0; -+ fixP->fx_subsy = NULL; -+ -+ if (fixP->fx_r_type == BFD_RELOC_64) -+ fixP->fx_r_type = BFD_RELOC_RISCV_ADD64, -+ fixP->fx_next->fx_r_type = BFD_RELOC_RISCV_SUB64; -+ else -+ fixP->fx_r_type = BFD_RELOC_RISCV_ADD32, -+ fixP->fx_next->fx_r_type = BFD_RELOC_RISCV_SUB32; -+ } -+ /* fall through */ -+ -+ case BFD_RELOC_RVA: -+ /* If we are deleting this reloc entry, we must fill in the -+ value now. This can happen if we have a .word which is not -+ resolved when it appears but is later defined. */ -+ if (fixP->fx_addsy == NULL) -+ { -+ gas_assert (fixP->fx_size <= sizeof (valueT)); -+ md_number_to_chars ((char *) buf, *valP, fixP->fx_size); -+ fixP->fx_done = 1; -+ } -+ return; -+ -+ case BFD_RELOC_RISCV_TLS_GOT_LO12: -+ case BFD_RELOC_RISCV_TLS_GD_LO12: -+ gas_assert (fixP->fx_addsy != NULL); -+ S_SET_THREAD_LOCAL (fixP->fx_addsy); -+ pcrel_r_type = BFD_RELOC_RISCV_TLS_PCREL_LO12; -+ break; -+ -+ case BFD_RELOC_RISCV_GOT_LO12: -+ gas_assert (fixP->fx_addsy != NULL); -+ pcrel_r_type = BFD_RELOC_RISCV_PCREL_LO12_I; -+ break; -+ -+ case BFD_RELOC_RISCV_PCREL_LO12_S: -+ if (fixP->fx_addsy != NULL) -+ { -+ fixP->fx_r_type = BFD_RELOC_RISCV_LO12_S; -+ pcrel_r_type = BFD_RELOC_RISCV_PCREL_LO12_S; -+ break; -+ } -+ return; -+ -+ case BFD_RELOC_RISCV_PCREL_LO12_I: -+ if (fixP->fx_addsy != NULL) -+ { -+ fixP->fx_r_type = BFD_RELOC_RISCV_LO12_I; -+ pcrel_r_type = BFD_RELOC_RISCV_PCREL_LO12_I; -+ break; -+ } -+ return; -+ -+ case BFD_RELOC_RISCV_TLS_PCREL_LO12: -+ case BFD_RELOC_RISCV_CALL: -+ case BFD_RELOC_RISCV_CALL_PLT: -+ case BFD_RELOC_MIPS_JMP: -+ case BFD_RELOC_12_PCREL: -+ return; -+ -+ default: -+ internalError (); -+ } -+ -+ /* We only get here for the low part of split PC-relative relocs. -+ Record the distance between the high and low parts. For now, -+ we assume the high part (AUIPC) is immediately before us, and -+ so this distance is -4. */ -+ gas_assert (fixP->fx_subsy == NULL); -+ fixP->fx_next = xmemdup (fixP, sizeof (*fixP), sizeof (*fixP)); -+ fixP->fx_next->fx_addsy = NULL; -+ fixP->fx_next->fx_offset = -4; -+ fixP->fx_next->fx_r_type = pcrel_r_type; -+} -+ -+/* Align the current frag to a given power of two. If a particular -+ fill byte should be used, FILL points to an integer that contains -+ that byte, otherwise FILL is null. -+ -+ The MIPS assembler also automatically adjusts any preceding -+ label. */ -+ -+static void -+mips_align (int to, int *fill, symbolS *label) -+{ -+ mips_clear_insn_labels (); -+ if (fill == NULL && subseg_text_p (now_seg)) -+ frag_align_code (to, 0); -+ else -+ frag_align (to, fill ? *fill : 0, 0); -+ record_alignment (now_seg, to); -+ if (label != NULL) -+ { -+ gas_assert (S_GET_SEGMENT (label) == now_seg); -+ symbol_set_frag (label, frag_now); -+ S_SET_VALUE (label, (valueT) frag_now_fix ()); -+ } -+} -+ -+/* Align to a given power of two. .align 0 turns off the automatic -+ alignment used by the data creating pseudo-ops. */ -+ -+static void -+s_align (int x ATTRIBUTE_UNUSED) -+{ -+ int temp, fill_value, *fill_ptr; -+ long max_alignment = 28; -+ -+ /* o Note that the assembler pulls down any immediately preceding label -+ to the aligned address. -+ o It's not documented but auto alignment is reinstated by -+ a .align pseudo instruction. -+ o Note also that after auto alignment is turned off the mips assembler -+ issues an error on attempt to assemble an improperly aligned data item. -+ We don't. */ -+ -+ temp = get_absolute_expression (); -+ if (temp > max_alignment) -+ as_bad (_("Alignment too large: %d. assumed."), temp = max_alignment); -+ else if (temp < 0) -+ { -+ as_warn (_("Alignment negative: 0 assumed.")); -+ temp = 0; -+ } -+ if (*input_line_pointer == ',') -+ { -+ ++input_line_pointer; -+ fill_value = get_absolute_expression (); -+ fill_ptr = &fill_value; -+ } -+ else -+ fill_ptr = 0; -+ if (temp) -+ { -+ segment_info_type *si = seg_info (now_seg); -+ struct insn_label_list *l = si->label_list; -+ /* Auto alignment should be switched on by next section change. */ -+ auto_align = 1; -+ mips_align (temp, fill_ptr, l != NULL ? l->label : NULL); -+ } -+ else -+ { -+ auto_align = 0; -+ } -+ -+ demand_empty_rest_of_line (); -+} -+ -+static void -+s_change_sec (int sec) -+{ -+#ifdef OBJ_ELF -+ /* The ELF backend needs to know that we are changing sections, so -+ that .previous works correctly. We could do something like check -+ for an obj_section_change_hook macro, but that might be confusing -+ as it would not be appropriate to use it in the section changing -+ functions in read.c, since obj-elf.c intercepts those. FIXME: -+ This should be cleaner, somehow. */ -+ if (IS_ELF) -+ obj_elf_section_change_hook (); -+#endif -+ -+ mips_clear_insn_labels (); -+ -+ switch (sec) -+ { -+ case 't': -+ s_text (0); -+ break; -+ case 'd': -+ s_data (0); -+ break; -+ case 'b': -+ subseg_set (bss_section, (subsegT) get_absolute_expression ()); -+ demand_empty_rest_of_line (); -+ break; -+ case 'r': -+ subseg_new (".rodata", (subsegT) get_absolute_expression ()); -+ demand_empty_rest_of_line (); -+ break; -+ } -+ -+ auto_align = 1; -+} -+ -+void -+s_change_section (int ignore ATTRIBUTE_UNUSED) -+{ -+#ifdef OBJ_ELF -+ char *section_name; -+ char c; -+ char next_c = 0; -+ int section_type; -+ int section_flag; -+ int section_entry_size; -+ -+ if (!IS_ELF) -+ return; -+ -+ section_name = input_line_pointer; -+ c = get_symbol_end (); -+ if (c) -+ next_c = *(input_line_pointer + 1); -+ -+ /* Do we have .section Name<,"flags">? */ -+ if (c != ',' || (c == ',' && next_c == '"')) -+ { -+ /* just after name is now '\0'. */ -+ *input_line_pointer = c; -+ input_line_pointer = section_name; -+ obj_elf_section (ignore); -+ return; -+ } -+ input_line_pointer++; -+ -+ /* Do we have .section Name<,type><,flag><,entry_size><,alignment> */ -+ if (c == ',') -+ section_type = get_absolute_expression (); -+ else -+ section_type = 0; -+ if (*input_line_pointer++ == ',') -+ section_flag = get_absolute_expression (); -+ else -+ section_flag = 0; -+ if (*input_line_pointer++ == ',') -+ section_entry_size = get_absolute_expression (); -+ else -+ section_entry_size = 0; -+ -+ section_name = xstrdup (section_name); -+ -+ obj_elf_change_section (section_name, section_type, section_flag, -+ section_entry_size, 0, 0, 0); -+ -+ if (now_seg->name != section_name) -+ free (section_name); -+#endif /* OBJ_ELF */ -+} -+ -+void -+mips_enable_auto_align (void) -+{ -+ auto_align = 1; -+} -+ -+static void -+s_cons (int log_size) -+{ -+ segment_info_type *si = seg_info (now_seg); -+ struct insn_label_list *l = si->label_list; -+ symbolS *label; -+ -+ label = l != NULL ? l->label : NULL; -+ mips_clear_insn_labels (); -+ if (log_size > 0 && auto_align) -+ mips_align (log_size, 0, label); -+ mips_clear_insn_labels (); -+ cons (1 << log_size); -+} -+ -+static void -+s_float_cons (int type) -+{ -+ segment_info_type *si = seg_info (now_seg); -+ struct insn_label_list *l = si->label_list; -+ symbolS *label; -+ -+ label = l != NULL ? l->label : NULL; -+ -+ mips_clear_insn_labels (); -+ -+ if (auto_align) -+ { -+ if (type == 'd') -+ mips_align (3, 0, label); -+ else -+ mips_align (2, 0, label); -+ } -+ -+ mips_clear_insn_labels (); -+ -+ float_cons (type); -+} -+ -+/* This structure is used to hold a stack of .set values. */ -+ -+struct mips_option_stack -+{ -+ struct mips_option_stack *next; -+ struct mips_set_options options; -+}; -+ -+static struct mips_option_stack *mips_opts_stack; -+ -+/* Handle the .set pseudo-op. */ -+ -+static void -+s_riscv_option (int x ATTRIBUTE_UNUSED) -+{ -+ char *name = input_line_pointer, ch; -+ -+ while (!is_end_of_line[(unsigned char) *input_line_pointer]) -+ ++input_line_pointer; -+ ch = *input_line_pointer; -+ *input_line_pointer = '\0'; -+ -+ if (strcmp (name, "rvc") == 0) -+ mips_opts.rvc = 1; -+ else if (strcmp (name, "norvc") == 0) -+ mips_opts.rvc = 0; -+ else if (strcmp (name, "push") == 0) -+ { -+ struct mips_option_stack *s; -+ -+ s = (struct mips_option_stack *) xmalloc (sizeof *s); -+ s->next = mips_opts_stack; -+ s->options = mips_opts; -+ mips_opts_stack = s; -+ } -+ else if (strcmp (name, "pop") == 0) -+ { -+ struct mips_option_stack *s; -+ -+ s = mips_opts_stack; -+ if (s == NULL) -+ as_bad (_(".set pop with no .set push")); -+ else -+ { -+ mips_opts = s->options; -+ mips_opts_stack = s->next; -+ free (s); -+ } -+ } -+ else if (strchr (name, ',')) -+ { -+ /* Generic ".set" directive; use the generic handler. */ -+ *input_line_pointer = ch; -+ input_line_pointer = name; -+ s_set (0); -+ return; -+ } -+ else -+ { -+ as_warn (_("Tried to set unrecognized symbol: %s\n"), name); -+ } -+ *input_line_pointer = ch; -+ demand_empty_rest_of_line (); -+} -+ -+/* Handle the .dtprelword and .dtpreldword pseudo-ops. They generate -+ a 32-bit or 64-bit DTP-relative relocation (BYTES says which) for -+ use in DWARF debug information. */ -+ -+static void -+s_dtprel_internal (size_t bytes) -+{ -+ expressionS ex; -+ char *p; -+ -+ expression (&ex); -+ -+ if (ex.X_op != O_symbol) -+ { -+ as_bad (_("Unsupported use of %s"), (bytes == 8 -+ ? ".dtpreldword" -+ : ".dtprelword")); -+ ignore_rest_of_line (); -+ } -+ -+ p = frag_more (bytes); -+ md_number_to_chars (p, 0, bytes); -+ fix_new_exp (frag_now, p - frag_now->fr_literal, bytes, &ex, FALSE, -+ (bytes == 8 -+ ? BFD_RELOC_MIPS_TLS_DTPREL64 -+ : BFD_RELOC_MIPS_TLS_DTPREL32)); -+ -+ demand_empty_rest_of_line (); -+} -+ -+/* Handle .dtprelword. */ -+ -+static void -+s_dtprelword (int ignore ATTRIBUTE_UNUSED) -+{ -+ s_dtprel_internal (4); -+} -+ -+/* Handle .dtpreldword. */ -+ -+static void -+s_dtpreldword (int ignore ATTRIBUTE_UNUSED) -+{ -+ s_dtprel_internal (8); -+} -+ -+/* Compute the length of a branch sequence, and adjust the -+ RELAX_BRANCH_TOOFAR bit accordingly. If FRAGP is NULL, the -+ worst-case length is computed. */ -+static int -+relaxed_branch_length (fragS *fragp, asection *sec, int update) -+{ -+ bfd_boolean toofar_rvc = TRUE, toofar = TRUE; -+ -+ if (fragp) -+ { -+ bfd_boolean uncond = RELAX_BRANCH_UNCOND (fragp->fr_subtype); -+ bfd_boolean rvc = RELAX_BRANCH_RVC (fragp->fr_subtype); -+ -+ if (S_IS_DEFINED (fragp->fr_symbol) -+ && sec == S_GET_SEGMENT (fragp->fr_symbol)) -+ { -+ offsetT val = S_GET_VALUE (fragp->fr_symbol) + fragp->fr_offset; -+ bfd_vma range; -+ val -= fragp->fr_address + fragp->fr_fix; -+ -+ if (uncond && rvc) -+ range = RVC_JUMP_REACH; -+ else if (rvc) -+ range = RVC_BRANCH_REACH; -+ else if (uncond) -+ range = RISCV_JUMP_REACH; -+ else -+ range = RISCV_BRANCH_REACH; -+ toofar = (bfd_vma)(val + range/2) >= range; -+ } -+ -+ if (update && toofar != RELAX_BRANCH_TOOFAR (fragp->fr_subtype)) -+ fragp->fr_subtype = RELAX_BRANCH_ENCODE (uncond, rvc, toofar); -+ } -+ -+ return toofar ? 8 : toofar_rvc ? 4 : 2; -+} -+ -+int -+md_estimate_size_before_relax (fragS *fragp, asection *segtype) -+{ -+ return (fragp->fr_var = relaxed_branch_length (fragp, segtype, FALSE)); -+} -+ -+/* Translate internal representation of relocation info to BFD target -+ format. */ -+ -+arelent ** -+tc_gen_reloc (asection *section ATTRIBUTE_UNUSED, fixS *fixp) -+{ -+ static arelent *retval[4]; -+ arelent *reloc; -+ bfd_reloc_code_real_type code; -+ -+ memset (retval, 0, sizeof(retval)); -+ reloc = retval[0] = (arelent *) xcalloc (1, sizeof (arelent)); -+ reloc->sym_ptr_ptr = (asymbol **) xmalloc (sizeof (asymbol *)); -+ *reloc->sym_ptr_ptr = symbol_get_bfdsym (fixp->fx_addsy); -+ reloc->address = fixp->fx_frag->fr_address + fixp->fx_where; -+ -+ if (fixp->fx_pcrel) -+ /* At this point, fx_addnumber is "symbol offset - pcrel address". -+ Relocations want only the symbol offset. */ -+ reloc->addend = fixp->fx_addnumber + reloc->address; -+ else -+ reloc->addend = fixp->fx_addnumber; -+ -+ code = fixp->fx_r_type; -+ -+ reloc->howto = bfd_reloc_type_lookup (stdoutput, code); -+ if (reloc->howto == NULL) -+ { -+ as_bad_where (fixp->fx_file, fixp->fx_line, -+ _("Can not represent %s relocation in this object file format"), -+ bfd_get_reloc_code_name (code)); -+ retval[0] = NULL; -+ } -+ -+ return retval; -+} -+ -+int -+mips_relax_frag (asection *sec, fragS *fragp, long stretch ATTRIBUTE_UNUSED) -+{ -+ if (RELAX_BRANCH_P (fragp->fr_subtype)) -+ { -+ offsetT old_var = fragp->fr_var; -+ fragp->fr_var = relaxed_branch_length (fragp, sec, TRUE); -+ return fragp->fr_var - old_var; -+ } -+ -+ return 0; -+} -+ -+/* Convert a machine dependent frag. */ -+ -+static void -+md_convert_frag_branch (bfd *abfd ATTRIBUTE_UNUSED, segT asec ATTRIBUTE_UNUSED, -+ fragS *fragp) -+{ -+ bfd_byte *buf; -+ insn_t insn; -+ expressionS exp; -+ fixS *fixp; -+ -+ buf = (bfd_byte *)fragp->fr_literal + fragp->fr_fix; -+ -+ exp.X_op = O_symbol; -+ exp.X_add_symbol = fragp->fr_symbol; -+ exp.X_add_number = fragp->fr_offset; -+ -+#if 0 -+ if (RELAX_BRANCH_RVC (fragp->fr_subtype)) -+ { -+ if (RELAX_BRANCH_TOOFAR (fragp->fr_subtype)) -+ { -+ bfd_reloc_code_real_type reloc_type = BFD_RELOC_12_PCREL; -+ -+ gas_assert(fragp->fr_var == 4); -+ insn = bfd_getl16 (buf); -+ -+ int rs1 = rvc_rs1_regmap[(insn >> OP_SH_CRS1S) & OP_MASK_CRS1S]; -+ int rs2 = rvc_rs2_regmap[(insn >> OP_SH_CRS2S) & OP_MASK_CRS2S]; -+ -+ if((insn & MASK_C_J) == MATCH_C_J) -+ { -+ insn = MATCH_JAL; -+ reloc_type = BFD_RELOC_MIPS_JMP; -+ } -+ else if((insn & MASK_C_BEQ) == MATCH_C_BEQ) -+ insn = MATCH_BEQ | (rs1 << OP_SH_RS1) | (rs2 << OP_SH_RS2); -+ else if((insn & MASK_C_BNE) == MATCH_C_BNE) -+ insn = MATCH_BNE | (rs1 << OP_SH_RS1) | (rs2 << OP_SH_RS2); -+ else -+ gas_assert(0); -+ -+ fixp = fix_new_exp (fragp, buf - (bfd_byte *)fragp->fr_literal, -+ 4, &exp, FALSE, reloc_type); -+ md_number_to_chars ((char *) buf, insn, 4); -+ buf += 4; -+ } -+ else -+ { -+ fixp = fix_new_exp (fragp, buf - (bfd_byte *)fragp->fr_literal, -+ 2, &exp, FALSE, BFD_RELOC_12_PCREL); -+ buf += 2; -+ } -+ } -+ else -+#endif -+ { -+ if (RELAX_BRANCH_TOOFAR (fragp->fr_subtype)) -+ { -+ gas_assert (fragp->fr_var == 8); -+ /* We could relax JAL to AUIPC/JALR, but we don't do this yet. */ -+ gas_assert (!RELAX_BRANCH_UNCOND (fragp->fr_subtype)); -+ -+ /* Invert the branch condition. Branch over the jump. */ -+ insn = bfd_getl32 (buf); -+ insn ^= MATCH_BEQ ^ MATCH_BNE; -+ insn |= ENCODE_SBTYPE_IMM (8); -+ md_number_to_chars ((char *) buf, insn, 4); -+ buf += 4; -+ -+ /* Jump to the target. */ -+ fixp = fix_new_exp (fragp, buf - (bfd_byte *)fragp->fr_literal, -+ 4, &exp, FALSE, BFD_RELOC_MIPS_JMP); -+ md_number_to_chars ((char *) buf, MATCH_JAL, 4); -+ buf += 4; -+ } -+ else -+ { -+ fixp = fix_new_exp (fragp, buf - (bfd_byte *)fragp->fr_literal, -+ 4, &exp, FALSE, BFD_RELOC_12_PCREL); -+ buf += 4; -+ } -+ } -+ -+ fixp->fx_file = fragp->fr_file; -+ fixp->fx_line = fragp->fr_line; -+ fixp->fx_pcrel = 1; -+ -+ gas_assert (buf == (bfd_byte *)fragp->fr_literal -+ + fragp->fr_fix + fragp->fr_var); -+ -+ fragp->fr_fix += fragp->fr_var; -+} -+ -+/* Relax a machine dependent frag. This returns the amount by which -+ the current size of the frag should change. */ -+ -+void -+md_convert_frag(bfd *abfd, segT asec, fragS *fragp) -+{ -+ if(RELAX_BRANCH_P(fragp->fr_subtype)) -+ md_convert_frag_branch(abfd, asec, fragp); -+ else -+ gas_assert(0); -+} -+ -+/* This function is called whenever a label is defined. It is used -+ when handling branch delays; if a branch has a label, we assume we -+ can not move it. */ -+ -+void -+mips_define_label (symbolS *sym) -+{ -+ segment_info_type *si = seg_info (now_seg); -+ struct insn_label_list *l; -+ -+ if (free_insn_labels == NULL) -+ l = (struct insn_label_list *) xmalloc (sizeof *l); -+ else -+ { -+ l = free_insn_labels; -+ free_insn_labels = l->next; -+ } -+ -+ l->label = sym; -+ l->next = si->label_list; -+ si->label_list = l; -+ -+#ifdef OBJ_ELF -+ dwarf2_emit_label (sym); -+#endif -+} -+ -+void -+mips_handle_align (fragS *fragp) -+{ -+ char *p; -+ -+ if (fragp->fr_type != rs_align_code) -+ return; -+ -+ p = fragp->fr_literal + fragp->fr_fix; -+ md_number_to_chars (p, RISCV_NOP, 4); -+ fragp->fr_var = 4; -+} -+ -+void -+md_show_usage (FILE *stream) -+{ -+ fprintf (stream, _("\ -+RISC-V options:\n\ -+ -m32 assemble RV32 code\n\ -+ -m64 assemble RV64 code (default)\n\ -+ -fpic generate position-independent code\n\ -+ -fno-pic don't generate position-independent code (default)\n\ -+")); -+} -+ -+enum dwarf2_format -+mips_dwarf2_format (asection *sec ATTRIBUTE_UNUSED) -+{ -+ if (HAVE_32BIT_SYMBOLS) -+ return dwarf2_format_32bit; -+ else -+ return dwarf2_format_64bit; -+} -+ -+int -+mips_dwarf2_addr_size (void) -+{ -+ return rv64 ? 8 : 4; -+} -+ -+/* Standard calling conventions leave the CFA at SP on entry. */ -+void -+mips_cfi_frame_initial_instructions (void) -+{ -+ cfi_add_CFA_def_cfa_register (SP); -+} -+ -+int -+tc_mips_regname_to_dw2regnum (char *regname) -+{ -+ unsigned int regnum = -1; -+ unsigned int reg; -+ -+ if (reg_lookup (®name, RTYPE_GP | RTYPE_NUM, ®)) -+ regnum = reg; -+ -+ return regnum; -+} -+ -+void -+riscv_elf_final_processing (void) -+{ -+ struct riscv_subset* s; -+ -+ unsigned int Xlen = 0; -+ for (s = riscv_subsets; s != NULL; s = s->next) -+ if (s->name[0] == 'X') -+ Xlen += strlen(s->name); -+ -+ char extension[Xlen]; -+ extension[0] = 0; -+ for (s = riscv_subsets; s != NULL; s = s->next) -+ if (s->name[0] == 'X') -+ strcat(extension, s->name); -+ -+ EF_SET_RISCV_EXT(elf_elfheader (stdoutput)->e_flags, -+ riscv_elf_name_to_flag (extension)); -+} -diff --git a/binutils-2.21.1/gas/config/tc-riscv.h b/binutils-2.21.1/gas/config/tc-riscv.h -new file mode 100644 -index 0000000..a9a8c37 ---- /dev/null -+++ binutils-2.21.1/gas/config/tc-riscv.h -@@ -0,0 +1,132 @@ -+/* tc-mips.h -- header file for tc-mips.c. -+ Copyright 1993, 1994, 1995, 1996, 1997, 2000, 2001, 2002, 2003, 2004, -+ 2005, 2006, 2007 Free Software Foundation, Inc. -+ Contributed by the OSF and Ralph Campbell. -+ Written by Keith Knowles and Ralph Campbell, working independently. -+ Modified for ECOFF support by Ian Lance Taylor of Cygnus Support. -+ -+ This file is part of GAS. -+ -+ GAS is free software; you can redistribute it and/or modify -+ it under the terms of the GNU General Public License as published by -+ the Free Software Foundation; either version 3, or (at your option) -+ any later version. -+ -+ GAS is distributed in the hope that it will be useful, -+ but WITHOUT ANY WARRANTY; without even the implied warranty of -+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -+ GNU General Public License for more details. -+ -+ You should have received a copy of the GNU General Public License -+ along with GAS; see the file COPYING. If not, write to the Free -+ Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA -+ 02110-1301, USA. */ -+ -+#ifndef TC_RISCV -+#define TC_RISCV -+ -+#include "opcode/riscv.h" -+ -+struct frag; -+struct expressionS; -+ -+#define TARGET_BYTES_BIG_ENDIAN 0 -+ -+#define TARGET_ARCH bfd_arch_riscv -+ -+#define WORKING_DOT_WORD 1 -+#define OLD_FLOAT_READS -+#define REPEAT_CONS_EXPRESSIONS -+#define RELOC_EXPANSION_POSSIBLE -+#define MAX_RELOC_EXPANSION 3 -+#define LOCAL_LABELS_FB 1 -+ -+#define md_relax_frag(segment, fragp, stretch) \ -+ mips_relax_frag(segment, fragp, stretch) -+extern int mips_relax_frag (asection *, struct frag *, long); -+ -+#define md_section_align(seg,size) (size) -+#define md_undefined_symbol(name) (0) -+#define md_operand(x) -+ -+#define NOP_OPCODE RISCV_NOP -+ -+extern void mips_handle_align (struct frag *); -+#define HANDLE_ALIGN(fragp) mips_handle_align (fragp) -+ -+#define MAX_MEM_FOR_RS_ALIGN_CODE (1 + 2) -+ -+struct insn_label_list; -+struct mips_segment_info { -+ struct insn_label_list *labels; -+ unsigned int mips16 : 1; -+}; -+#define TC_SEGMENT_INFO_TYPE struct mips_segment_info -+ -+/* This field is nonzero if the symbol is the target of a MIPS16 jump. */ -+#define TC_SYMFIELD_TYPE int -+ -+/* The ISA of the target may change based on command-line arguments. */ -+#define TARGET_FORMAT mips_target_format() -+extern const char *mips_target_format (void); -+ -+#define md_after_parse_args() mips_after_parse_args() -+extern void mips_after_parse_args (void); -+ -+#define tc_init_after_args() mips_init_after_args() -+extern void mips_init_after_args (void); -+ -+#define md_parse_long_option(arg) mips_parse_long_option (arg) -+extern int mips_parse_long_option (const char *); -+ -+#define tc_frob_label(sym) mips_define_label (sym) -+extern void mips_define_label (symbolS *); -+ -+/* Let the linker resolve all the relocs due to relaxation. */ -+#define tc_fix_adjustable(fixp) 0 -+#define md_allow_local_subtract(l,r,s) 0 -+ -+/* Values passed to md_apply_fix don't include symbol values. */ -+#define MD_APPLY_SYM_VALUE(FIX) 0 -+ -+/* Global syms must not be resolved, to support ELF shared libraries. */ -+#define EXTERN_FORCE_RELOC \ -+ (OUTPUT_FLAVOR == bfd_target_elf_flavour) -+ -+#define TC_FORCE_RELOCATION_SUB_SAME(FIX, SEG) ((SEG)->flags & SEC_CODE) -+#define TC_FORCE_RELOCATION_SUB_LOCAL(FIX, SEG) 1 -+#define TC_VALIDATE_FIX_SUB(FIX, SEG) TC_FORCE_RELOCATION_SUB_SAME(FIX, SEG) -+#define DIFF_EXPR_OK 1 -+ -+extern void mips_pop_insert (void); -+#define md_pop_insert() mips_pop_insert() -+ -+extern void mips_clear_insn_labels (void); -+#define md_flush_pending_output mips_clear_insn_labels -+ -+extern void mips_enable_auto_align (void); -+#define md_elf_section_change_hook() mips_enable_auto_align() -+ -+enum dwarf2_format; -+extern enum dwarf2_format mips_dwarf2_format (asection *); -+#define DWARF2_FORMAT(SEC) mips_dwarf2_format (SEC) -+ -+extern int mips_dwarf2_addr_size (void); -+#define DWARF2_ADDR_SIZE(bfd) mips_dwarf2_addr_size () -+#define DWARF2_FDE_RELOC_SIZE mips_dwarf2_addr_size () -+ -+#define TARGET_USE_CFIPOP 1 -+ -+#define tc_cfi_frame_initial_instructions mips_cfi_frame_initial_instructions -+extern void mips_cfi_frame_initial_instructions (void); -+ -+#define tc_regname_to_dw2regnum tc_mips_regname_to_dw2regnum -+extern int tc_mips_regname_to_dw2regnum (char *regname); -+ -+#define DWARF2_DEFAULT_RETURN_COLUMN LINK_REG -+#define DWARF2_CIE_DATA_ALIGNMENT (-4) -+ -+#define elf_tc_final_processing riscv_elf_final_processing -+extern void riscv_elf_final_processing (void); -+ -+#endif /* TC_RISCV */ -diff --git a/binutils-2.21.1/gas/configure.tgt b/binutils-2.21.1/gas/configure.tgt -index aa12fbb..371c673 100644 ---- a/binutils-2.21.1/gas/configure.tgt -+++ binutils-2.21.1/gas/configure.tgt -@@ -63,6 +63,7 @@ case ${cpu} in - pj*) cpu_type=pj endian=big ;; - powerpc*le*) cpu_type=ppc endian=little ;; - powerpc*) cpu_type=ppc endian=big ;; -+ riscv*) cpu_type=riscv endian=little ;; - rs6000*) cpu_type=ppc ;; - rx) cpu_type=rx ;; - s390x*) cpu_type=s390 arch=s390x ;; -@@ -340,6 +341,8 @@ case ${generic_target} in - ppc-*-kaos*) fmt=elf ;; - ppc-*-lynxos*) fmt=elf em=lynx ;; - -+ riscv*-*-*) fmt=elf endian=little em=linux bfd_gas=yes ;; -+ - s390-*-linux-*) fmt=elf em=linux ;; - s390-*-tpf*) fmt=elf ;; - -diff --git a/binutils-2.21.1/gas/doc/c-arc.texi b/binutils-2.21.1/gas/doc/c-arc.texi -index 3a136a7..cd6f0d9 100644 ---- a/binutils-2.21.1/gas/doc/c-arc.texi -+++ binutils-2.21.1/gas/doc/c-arc.texi -@@ -212,7 +212,7 @@ The extension instructions are not macros. The assembler creates - encodings for use of these instructions according to the specification - by the user. The parameters are: - --@table @bullet -+@table @code - @item @var{name} - Name of the extension instruction - -diff --git a/binutils-2.21.1/gas/doc/c-arm.texi b/binutils-2.21.1/gas/doc/c-arm.texi -index d3cccf4..97c2f92 100644 ---- a/binutils-2.21.1/gas/doc/c-arm.texi -+++ binutils-2.21.1/gas/doc/c-arm.texi -@@ -376,29 +376,29 @@ ARM and THUMB instructions had their own, separate syntaxes. The new, - @code{unified} syntax, which can be selected via the @code{.syntax} - directive, and has the following main features: - --@table @bullet --@item -+@table @code -+@item 1 - Immediate operands do not require a @code{#} prefix. - --@item -+@item 2 - The @code{IT} instruction may appear, and if it does it is validated - against subsequent conditional affixes. In ARM mode it does not - generate machine code, in THUMB mode it does. - --@item -+@item 3 - For ARM instructions the conditional affixes always appear at the end - of the instruction. For THUMB instructions conditional affixes can be - used, but only inside the scope of an @code{IT} instruction. - --@item -+@item 4 - All of the instructions new to the V6T2 architecture (and later) are - available. (Only a few such instructions can be written in the - @code{divided} syntax). - --@item -+@item 5 - The @code{.N} and @code{.W} suffixes are recognized and honored. - --@item -+@item 6 - All instructions set the flags if and only if they have an @code{s} - affix. - @end table -@@ -433,28 +433,6 @@ Either @samp{#} or @samp{$} can be used to indicate immediate operands. - @cindex register names, ARM - *TODO* Explain about ARM register naming, and the predefined names. - --@node ARM-Neon-Alignment --@subsection NEON Alignment Specifiers -- --@cindex alignment for NEON instructions --Some NEON load/store instructions allow an optional address --alignment qualifier. --The ARM documentation specifies that this is indicated by --@samp{@@ @var{align}}. However GAS already interprets --the @samp{@@} character as a "line comment" start, --so @samp{: @var{align}} is used instead. For example: -- --@smallexample -- vld1.8 @{q0@}, [r0, :128] --@end smallexample -- --@node ARM Floating Point --@section Floating Point -- --@cindex floating point, ARM (@sc{ieee}) --@cindex ARM floating point (@sc{ieee}) --The ARM family uses @sc{ieee} floating-point numbers. -- - @node ARM-Relocations - @subsection ARM relocation generation - -@@ -497,6 +475,28 @@ respectively. For example to load the 32-bit address of foo into r0: - MOVT r0, #:upper16:foo - @end smallexample - -+@node ARM-Neon-Alignment -+@subsection NEON Alignment Specifiers -+ -+@cindex alignment for NEON instructions -+Some NEON load/store instructions allow an optional address -+alignment qualifier. -+The ARM documentation specifies that this is indicated by -+@samp{@@ @var{align}}. However GAS already interprets -+the @samp{@@} character as a "line comment" start, -+so @samp{: @var{align}} is used instead. For example: -+ -+@smallexample -+ vld1.8 @{q0@}, [r0, :128] -+@end smallexample -+ -+@node ARM Floating Point -+@section Floating Point -+ -+@cindex floating point, ARM (@sc{ieee}) -+@cindex ARM floating point (@sc{ieee}) -+The ARM family uses @sc{ieee} floating-point numbers. -+ - @node ARM Directives - @section ARM Machine Directives - -diff --git a/binutils-2.21.1/gas/doc/c-cr16.texi b/binutils-2.21.1/gas/doc/c-cr16.texi -index b6cf10f..3332426 100644 ---- a/binutils-2.21.1/gas/doc/c-cr16.texi -+++ binutils-2.21.1/gas/doc/c-cr16.texi -@@ -43,26 +43,33 @@ Operand expression type qualifier is an optional field in the instruction operan - CR16 target operand qualifiers and its size (in bits): - - @table @samp --@item Immediate Operand --- s ---- 4 bits --@item --- m ---- 16 bits, for movb and movw instructions. --@item --- m ---- 20 bits, movd instructions. --@item --- l ---- 32 bits -- --@item Absolute Operand --- s ---- Illegal specifier for this operand. --@item --- m ---- 20 bits, movd instructions. -- --@item Displacement Operand --- s ---- 8 bits --@item --- m ---- 16 bits --@item --- l ---- 24 bits -+@item Immediate Operand: s -+4 bits. -+ -+@item Immediate Operand: m -+16 bits, for movb and movw instructions. -+ -+@item Immediate Operand: m -+20 bits, movd instructions. -+ -+@item Immediate Operand: l -+32 bits. -+ -+@item Absolute Operand: s -+Illegal specifier for this operand. -+ -+@item Absolute Operand: m -+20 bits, movd instructions. -+ -+@item Displacement Operand: s -+8 bits. -+ -+@item Displacement Operand: m -+16 bits. -+ -+@item Displacement Operand: l -+24 bits. -+ - @end table - - For example: -diff --git a/binutils-2.21.1/gas/doc/c-mips.texi b/binutils-2.21.1/gas/doc/c-mips.texi -index 715091e..1250c1e 100644 ---- a/binutils-2.21.1/gas/doc/c-mips.texi -+++ binutils-2.21.1/gas/doc/c-mips.texi -@@ -220,7 +220,7 @@ the @samp{mad} and @samp{madu} instruction, and to not schedule @samp{nop} - instructions around accesses to the @samp{HI} and @samp{LO} registers. - @samp{-no-m4650} turns off this option. - --@itemx -m3900 -+@item -m3900 - @itemx -no-m3900 - @itemx -m4100 - @itemx -no-m4100 -diff --git a/binutils-2.21.1/gas/doc/c-score.texi b/binutils-2.21.1/gas/doc/c-score.texi -index 0820115..a5b570f 100644 ---- a/binutils-2.21.1/gas/doc/c-score.texi -+++ binutils-2.21.1/gas/doc/c-score.texi -@@ -36,7 +36,7 @@ implicitly with the @code{gp} register. The default value is 8. - @item -EB - Assemble code for a big-endian cpu - --@itemx -EL -+@item -EL - Assemble code for a little-endian cpu - - @item -FIXDD -@@ -48,13 +48,13 @@ Assemble code for no warning message for fix data dependency - @item -SCORE5 - Assemble code for target is SCORE5 - --@itemx -SCORE5U -+@item -SCORE5U - Assemble code for target is SCORE5U - --@itemx -SCORE7 -+@item -SCORE7 - Assemble code for target is SCORE7, this is default setting - --@itemx -SCORE3 -+@item -SCORE3 - Assemble code for target is SCORE3 - - @item -march=score7 -diff --git a/binutils-2.21.1/gas/doc/c-tic54x.texi b/binutils-2.21.1/gas/doc/c-tic54x.texi -index 4cfb440..899b49d 100644 ---- a/binutils-2.21.1/gas/doc/c-tic54x.texi -+++ binutils-2.21.1/gas/doc/c-tic54x.texi -@@ -108,7 +108,7 @@ In this example, x is replaced with SYM2; SYM2 is replaced with SYM1, and SYM1 - is replaced with x. At this point, x has already been encountered - and the substitution stops. - --@smallexample @code -+@smallexample - .asg "x",SYM1 - .asg "SYM1",SYM2 - .asg "SYM2",x -@@ -125,14 +125,14 @@ Substitution may be forced in situations where replacement might be - ambiguous by placing colons on either side of the subsym. The following - code: - --@smallexample @code -+@smallexample - .eval "10",x - LAB:X: add #x, a - @end smallexample - - When assembled becomes: - --@smallexample @code -+@smallexample - LAB10 add #10, a - @end smallexample - -@@ -308,7 +308,7 @@ The @code{LDX} pseudo-op is provided for loading the extended addressing bits - of a label or address. For example, if an address @code{_label} resides - in extended program memory, the value of @code{_label} may be loaded as - follows: --@smallexample @code -+@smallexample - ldx #_label,16,a ; loads extended bits of _label - or #_label,a ; loads lower 16 bits of _label - bacc a ; full address is in accumulator A -@@ -325,7 +325,7 @@ follows: - @cindex @code{align} directive, TIC54X - @cindex @code{even} directive, TIC54X - @item .align [@var{size}] --@itemx .even -+@item .even - Align the section program counter on the next boundary, based on - @var{size}. @var{size} may be any power of 2. @code{.even} is - equivalent to @code{.align} with a @var{size} of 2. -@@ -344,7 +344,7 @@ Assign @var{name} the string @var{string}. String replacement is - performed on @var{string} before assignment. - - @cindex @code{eval} directive, TIC54X --@itemx .eval @var{string}, @var{name} -+@item .eval @var{string}, @var{name} - Evaluate the contents of string @var{string} and assign the result as a - string to the subsym @var{name}. String replacement is performed on - @var{string} before assignment. -diff --git a/binutils-2.21.1/include/dis-asm.h b/binutils-2.21.1/include/dis-asm.h -index 63366d9..9f08d4e 100644 ---- a/binutils-2.21.1/include/dis-asm.h -+++ binutils-2.21.1/include/dis-asm.h -@@ -227,6 +227,7 @@ extern int print_insn_big_arm (bfd_vma, disassemble_info *); - extern int print_insn_big_mips (bfd_vma, disassemble_info *); - extern int print_insn_big_or32 (bfd_vma, disassemble_info *); - extern int print_insn_big_powerpc (bfd_vma, disassemble_info *); -+extern int print_insn_big_riscv (bfd_vma, disassemble_info *); - extern int print_insn_big_score (bfd_vma, disassemble_info *); - extern int print_insn_cr16 (bfd_vma, disassemble_info *); - extern int print_insn_crx (bfd_vma, disassemble_info *); -@@ -253,6 +254,7 @@ extern int print_insn_little_arm (bfd_vma, disassemble_info *); - extern int print_insn_little_mips (bfd_vma, disassemble_info *); - extern int print_insn_little_or32 (bfd_vma, disassemble_info *); - extern int print_insn_little_powerpc (bfd_vma, disassemble_info *); -+extern int print_insn_little_riscv (bfd_vma, disassemble_info *); - extern int print_insn_little_score (bfd_vma, disassemble_info *); - extern int print_insn_lm32 (bfd_vma, disassemble_info *); - extern int print_insn_m32c (bfd_vma, disassemble_info *); -diff --git a/binutils-2.21.1/include/elf/common.h b/binutils-2.21.1/include/elf/common.h -index 01c519d..49dafb5 100644 ---- a/binutils-2.21.1/include/elf/common.h -+++ binutils-2.21.1/include/elf/common.h -@@ -295,6 +295,7 @@ - #define EM_TILEPRO 188 /* Tilera TILEPro multicore architecture family */ - #define EM_MICROBLAZE 189 /* Xilinx MicroBlaze 32-bit RISC soft processor core */ - #define EM_CUDA 190 /* NVIDIA CUDA architecture */ -+#define EM_RISCV 243 /* RISC-V */ - - /* If it is necessary to assign new unofficial EM_* values, please pick large - random numbers (0x8523, 0xa7f2, etc.) to minimize the chances of collision -diff --git a/binutils-2.21.1/include/elf/riscv.h b/binutils-2.21.1/include/elf/riscv.h -new file mode 100644 -index 0000000..f455693 ---- /dev/null -+++ binutils-2.21.1/include/elf/riscv.h -@@ -0,0 +1,180 @@ -+/* RISC-V ELF support for BFD. -+ Copyright 1993, 1994, 1995, 1996, 1997, 1998, 1999, 2000, 2001, 2002, -+ 2003, 2004, 2005, 2008, 2009, 2010 -+ Free Software Foundation, Inc. -+ -+ By Andrew Waterman, University of California, -+ . -+ Based on MIPS ELF support for BFD, by Ian Lance Taylor. -+ -+ This file is part of BFD, the Binary File Descriptor library. -+ -+ This program is free software; you can redistribute it and/or modify -+ it under the terms of the GNU General Public License as published by -+ the Free Software Foundation; either version 3 of the License, or -+ (at your option) any later version. -+ -+ This program is distributed in the hope that it will be useful, -+ but WITHOUT ANY WARRANTY; without even the implied warranty of -+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -+ GNU General Public License for more details. -+ -+ You should have received a copy of the GNU General Public License -+ along with this program; if not, write to the Free Software -+ Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston, -+ MA 02110-1301, USA. */ -+ -+/* This file holds definitions specific to the RISCV ELF ABI. Note -+ that most of this is not actually implemented by BFD. */ -+ -+#ifndef _ELF_RISCV_H -+#define _ELF_RISCV_H -+ -+#include "elf/reloc-macros.h" -+ -+/* Relocation types. */ -+START_RELOC_NUMBERS (elf_riscv_reloc_type) -+ RELOC_NUMBER (R_RISCV_NONE, 0) -+ RELOC_NUMBER (R_RISCV_32, 2) -+ RELOC_NUMBER (R_RISCV_REL32, 3) -+ RELOC_NUMBER (R_RISCV_JAL, 4) -+ RELOC_NUMBER (R_RISCV_HI20, 5) -+ RELOC_NUMBER (R_RISCV_LO12_I, 6) -+ RELOC_NUMBER (R_RISCV_LO12_S, 7) -+ RELOC_NUMBER (R_RISCV_PCREL_LO12_I, 8) -+ RELOC_NUMBER (R_RISCV_PCREL_LO12_S, 9) -+ RELOC_NUMBER (R_RISCV_BRANCH, 10) -+ RELOC_NUMBER (R_RISCV_CALL, 11) -+ RELOC_NUMBER (R_RISCV_PCREL_HI20, 12) -+ RELOC_NUMBER (R_RISCV_CALL_PLT, 13) -+ RELOC_NUMBER (R_RISCV_64, 18) -+ RELOC_NUMBER (R_RISCV_GOT_HI20, 22) -+ RELOC_NUMBER (R_RISCV_GOT_LO12, 23) -+ RELOC_NUMBER (R_RISCV_COPY, 24) -+ RELOC_NUMBER (R_RISCV_JUMP_SLOT, 25) -+ /* TLS relocations. */ -+ RELOC_NUMBER (R_RISCV_TLS_IE_HI20, 29) -+ RELOC_NUMBER (R_RISCV_TLS_IE_LO12, 30) -+ RELOC_NUMBER (R_RISCV_TLS_IE_ADD, 31) -+ RELOC_NUMBER (R_RISCV_TLS_IE_LO12_I, 32) -+ RELOC_NUMBER (R_RISCV_TLS_IE_LO12_S, 33) -+ RELOC_NUMBER (R_RISCV_TPREL_HI20, 34) -+ RELOC_NUMBER (R_RISCV_TPREL_LO12_I, 35) -+ RELOC_NUMBER (R_RISCV_TPREL_LO12_S, 36) -+ RELOC_NUMBER (R_RISCV_TPREL_ADD, 37) -+ RELOC_NUMBER (R_RISCV_TLS_DTPMOD32, 38) -+ RELOC_NUMBER (R_RISCV_TLS_DTPREL32, 39) -+ RELOC_NUMBER (R_RISCV_TLS_DTPMOD64, 40) -+ RELOC_NUMBER (R_RISCV_TLS_DTPREL64, 41) -+ RELOC_NUMBER (R_RISCV_TLS_TPREL32, 47) -+ RELOC_NUMBER (R_RISCV_TLS_TPREL64, 48) -+ RELOC_NUMBER (R_RISCV_TLS_PCREL_LO12, 50) -+ RELOC_NUMBER (R_RISCV_TLS_GOT_HI20, 51) -+ RELOC_NUMBER (R_RISCV_TLS_GOT_LO12, 52) -+ RELOC_NUMBER (R_RISCV_TLS_GD_HI20, 53) -+ RELOC_NUMBER (R_RISCV_TLS_GD_LO12, 54) -+ RELOC_NUMBER (R_RISCV_GLOB_DAT, 57) -+ RELOC_NUMBER (R_RISCV_ADD32, 58) -+ RELOC_NUMBER (R_RISCV_ADD64, 59) -+ RELOC_NUMBER (R_RISCV_SUB32, 60) -+ RELOC_NUMBER (R_RISCV_SUB64, 61) -+ FAKE_RELOC (R_RISCV_max, 62) -+END_RELOC_NUMBERS (R_RISCV_maxext) -+ -+/* Processor specific flags for the ELF header e_flags field. */ -+ -+/* Custom flag definitions. */ -+ -+#define EF_RISCV_EXT_MASK 0xffff -+#define EF_RISCV_EXT_SH 16 -+#define E_RISCV_EXT_Xcustom 0x0000 -+#define E_RISCV_EXT_Xhwacha 0x0001 -+#define E_RISCV_EXT_RESERVED 0xffff -+ -+#define EF_GET_RISCV_EXT(x) \ -+ ((x >> EF_RISCV_EXT_SH) & EF_RISCV_EXT_MASK) -+ -+#define EF_SET_RISCV_EXT(x, ext) \ -+ do { x |= ((ext & EF_RISCV_EXT_MASK) << EF_RISCV_EXT_SH); } while (0) -+ -+#define EF_IS_RISCV_EXT_Xcustom(x) \ -+ (EF_GET_RISCV_EXT(x) == E_RISCV_EXT_Xcustom) -+ -+/* A mapping from extension names to elf flags */ -+ -+struct riscv_extension_entry -+{ -+ const char* name; -+ unsigned int flag; -+}; -+ -+static const struct riscv_extension_entry riscv_extension_map[] = -+{ -+ {"Xcustom", E_RISCV_EXT_Xcustom}, -+ {"Xhwacha", E_RISCV_EXT_Xhwacha}, -+}; -+ -+/* Given an extension name, return an elf flag. */ -+ -+static inline const char* riscv_elf_flag_to_name(unsigned int flag) -+{ -+ unsigned int i; -+ -+ for (i=0; i -+#include -+ -+/* RVC fields */ -+ -+#define OP_MASK_COP 0x1f -+#define OP_SH_COP 0 -+#define OP_MASK_CRD 0x1f -+#define OP_SH_CRD 5 -+#define OP_MASK_CRS2 0x1f -+#define OP_SH_CRS2 5 -+#define OP_MASK_CRS1 0x1f -+#define OP_SH_CRS1 10 -+#define OP_MASK_CRDS 0x7 -+#define OP_SH_CRDS 13 -+#define OP_MASK_CRS2S 0x7 -+#define OP_SH_CRS2S 13 -+#define OP_MASK_CRS2BS 0x7 -+#define OP_SH_CRS2BS 5 -+#define OP_MASK_CRS1S 0x7 -+#define OP_SH_CRS1S 10 -+#define OP_MASK_CIMM6 0x3f -+#define OP_SH_CIMM6 10 -+#define OP_MASK_CIMM5 0x1f -+#define OP_SH_CIMM5 5 -+#define OP_MASK_CIMM10 0x3ff -+#define OP_SH_CIMM10 5 -+ -+static const char rvc_rs1_regmap[8] = { 20, 21, 2, 3, 4, 5, 6, 7 }; -+#define rvc_rd_regmap rvc_rs1_regmap -+#define rvc_rs2b_regmap rvc_rs1_regmap -+static const char rvc_rs2_regmap[8] = { 20, 21, 2, 3, 4, 5, 6, 0 }; -+ -+typedef uint64_t insn_t; -+ -+static inline unsigned int riscv_insn_length (insn_t insn) -+{ -+ if ((insn & 0x3) != 3) /* RVC */ -+ return 2; -+ if ((insn & 0x1f) != 0x1f) /* base ISA and extensions in 32-bit space */ -+ return 4; -+ if ((insn & 0x3f) == 0x1f) /* 48-bit extensions */ -+ return 6; -+ if ((insn & 0x7f) == 0x3f) /* 64-bit extensions */ -+ return 8; -+ /* longer instructions not supported at the moment */ -+ return 2; -+} -+ -+static const char * const riscv_rm[8] = { -+ "rne", "rtz", "rdn", "rup", "rmm", 0, 0, "dyn" -+}; -+static const char* const riscv_pred_succ[16] = { -+ 0, "w", "r", "rw", "o", "ow", "or", "orw", -+ "i", "iw", "ir", "irw", "io", "iow", "ior", "iorw", -+}; -+ -+#define RVC_JUMP_BITS 10 -+#define RVC_JUMP_ALIGN_BITS 1 -+#define RVC_JUMP_ALIGN (1 << RVC_JUMP_ALIGN_BITS) -+#define RVC_JUMP_REACH ((1ULL<> (s)) & ((1<<(n))-1)) -+#define RV_IMM_SIGN(x) (-(((x) >> 31) & 1)) -+ -+#define EXTRACT_ITYPE_IMM(x) \ -+ (RV_X(x, 20, 12) | (RV_IMM_SIGN(x) << 12)) -+#define EXTRACT_STYPE_IMM(x) \ -+ (RV_X(x, 7, 5) | (RV_X(x, 25, 7) << 5) | (RV_IMM_SIGN(x) << 12)) -+#define EXTRACT_SBTYPE_IMM(x) \ -+ ((RV_X(x, 8, 4) << 1) | (RV_X(x, 25, 6) << 5) | (RV_X(x, 7, 1) << 11) | (RV_IMM_SIGN(x) << 12)) -+#define EXTRACT_UTYPE_IMM(x) \ -+ (RV_X(x, 12, 20) | (RV_IMM_SIGN(x) << 20)) -+#define EXTRACT_UJTYPE_IMM(x) \ -+ ((RV_X(x, 21, 10) << 1) | (RV_X(x, 20, 1) << 11) | (RV_X(x, 12, 8) << 12) | (RV_IMM_SIGN(x) << 20)) -+ -+#define ENCODE_ITYPE_IMM(x) \ -+ (RV_X(x, 0, 12) << 20) -+#define ENCODE_STYPE_IMM(x) \ -+ ((RV_X(x, 0, 5) << 7) | (RV_X(x, 5, 7) << 25)) -+#define ENCODE_SBTYPE_IMM(x) \ -+ ((RV_X(x, 1, 4) << 8) | (RV_X(x, 5, 6) << 25) | (RV_X(x, 11, 1) << 7) | (RV_X(x, 12, 1) << 31)) -+#define ENCODE_UTYPE_IMM(x) \ -+ (RV_X(x, 0, 20) << 12) -+#define ENCODE_UJTYPE_IMM(x) \ -+ ((RV_X(x, 1, 10) << 21) | (RV_X(x, 11, 1) << 20) | (RV_X(x, 12, 8) << 12) | (RV_X(x, 20, 1) << 31)) -+ -+#define VALID_ITYPE_IMM(x) (EXTRACT_ITYPE_IMM(ENCODE_ITYPE_IMM(x)) == (x)) -+#define VALID_STYPE_IMM(x) (EXTRACT_STYPE_IMM(ENCODE_STYPE_IMM(x)) == (x)) -+#define VALID_SBTYPE_IMM(x) (EXTRACT_SBTYPE_IMM(ENCODE_SBTYPE_IMM(x)) == (x)) -+#define VALID_UTYPE_IMM(x) (EXTRACT_UTYPE_IMM(ENCODE_UTYPE_IMM(x)) == (x)) -+#define VALID_UJTYPE_IMM(x) (EXTRACT_UJTYPE_IMM(ENCODE_UJTYPE_IMM(x)) == (x)) -+ -+#define RISCV_RTYPE(insn, rd, rs1, rs2) \ -+ ((MATCH_ ## insn) | ((rd) << OP_SH_RD) | ((rs1) << OP_SH_RS1) | ((rs2) << OP_SH_RS2)) -+#define RISCV_ITYPE(insn, rd, rs1, imm) \ -+ ((MATCH_ ## insn) | ((rd) << OP_SH_RD) | ((rs1) << OP_SH_RS1) | ENCODE_ITYPE_IMM(imm)) -+#define RISCV_STYPE(insn, rs1, rs2, imm) \ -+ ((MATCH_ ## insn) | ((rs1) << OP_SH_RS1) | ((rs2) << OP_SH_RS2) | ENCODE_STYPE_IMM(imm)) -+#define RISCV_SBTYPE(insn, rs1, rs2, target) \ -+ ((MATCH_ ## insn) | ((rs1) << OP_SH_RS1) | ((rs2) << OP_SH_RS2) | ENCODE_SBTYPE_IMM(target)) -+#define RISCV_UTYPE(insn, rd, bigimm) \ -+ ((MATCH_ ## insn) | ((rd) << OP_SH_RD) | ENCODE_UTYPE_IMM(bigimm)) -+#define RISCV_UJTYPE(insn, rd, target) \ -+ ((MATCH_ ## insn) | ((rd) << OP_SH_RD) | ENCODE_UJTYPE_IMM(target)) -+ -+#define RISCV_NOP RISCV_ITYPE(ADDI, 0, 0, 0) -+ -+#define RISCV_CONST_HIGH_PART(VALUE) \ -+ (((VALUE) + (RISCV_IMM_REACH/2)) & ~(RISCV_IMM_REACH-1)) -+#define RISCV_CONST_LOW_PART(VALUE) ((VALUE) - RISCV_CONST_HIGH_PART (VALUE)) -+#define RISCV_LUI_HIGH_PART(VALUE) (RISCV_CONST_HIGH_PART(VALUE) >> RISCV_IMM_BITS) -+#define RISCV_PCREL_HIGH_PART(VALUE, PC) RISCV_LUI_HIGH_PART((VALUE) - (PC)) -+#define RISCV_PCREL_LOW_PART(VALUE, PC) RISCV_CONST_LOW_PART((VALUE) - (PC)) -+ -+/* RV fields */ -+ -+#define OP_MASK_OP 0x7f -+#define OP_SH_OP 0 -+#define OP_MASK_RS2 0x1f -+#define OP_SH_RS2 20 -+#define OP_MASK_RS1 0x1f -+#define OP_SH_RS1 15 -+#define OP_MASK_RS3 0x1f -+#define OP_SH_RS3 27 -+#define OP_MASK_RD 0x1f -+#define OP_SH_RD 7 -+#define OP_MASK_SHAMT 0x3f -+#define OP_SH_SHAMT 20 -+#define OP_MASK_SHAMTW 0x1f -+#define OP_SH_SHAMTW 20 -+#define OP_MASK_RM 0x7 -+#define OP_SH_RM 12 -+#define OP_MASK_PRED 0xf -+#define OP_SH_PRED 24 -+#define OP_MASK_SUCC 0xf -+#define OP_SH_SUCC 20 -+#define OP_MASK_AQ 0x1 -+#define OP_SH_AQ 26 -+#define OP_MASK_RL 0x1 -+#define OP_SH_RL 25 -+ -+#define OP_MASK_VRD 0x1f -+#define OP_SH_VRD 7 -+#define OP_MASK_VRS 0x1f -+#define OP_SH_VRS 15 -+#define OP_MASK_VRT 0x1f -+#define OP_SH_VRT 20 -+#define OP_MASK_VRR 0x1f -+#define OP_SH_VRR 27 -+ -+#define OP_MASK_VFD 0x1f -+#define OP_SH_VFD 7 -+#define OP_MASK_VFS 0x1f -+#define OP_SH_VFS 15 -+#define OP_MASK_VFT 0x1f -+#define OP_SH_VFT 20 -+#define OP_MASK_VFR 0x1f -+#define OP_SH_VFR 27 -+ -+#define OP_MASK_IMMNGPR 0x3f -+#define OP_SH_IMMNGPR 20 -+#define OP_MASK_IMMNFPR 0x3f -+#define OP_SH_IMMNFPR 26 -+#define OP_MASK_IMMSEGNELM 0x7 -+#define OP_SH_IMMSEGNELM 29 -+#define OP_MASK_CUSTOM_IMM 0x7f -+#define OP_SH_CUSTOM_IMM 25 -+#define OP_MASK_CSR 0xfff -+#define OP_SH_CSR 20 -+ -+#define LINK_REG 1 -+#define TP_REG 15 -+#define GP_REG 31 -+ -+#define RISCV_JUMP_BITS RISCV_BIGIMM_BITS -+#define RISCV_JUMP_ALIGN_BITS 1 -+#define RISCV_JUMP_ALIGN (1 << RISCV_JUMP_ALIGN_BITS) -+#define RISCV_JUMP_REACH ((1ULL< instruction is short for jalr ). */ -+ -+extern const struct riscv_opcode riscv_builtin_opcodes[]; -+extern const int bfd_riscv_num_builtin_opcodes; -+extern struct riscv_opcode *riscv_opcodes; -+extern int bfd_riscv_num_opcodes; -+#define NUMOPCODES bfd_riscv_num_opcodes -+ -+#endif /* _MIPS_H_ */ -diff --git a/binutils-2.21.1/ld/Makefile.am b/binutils-2.21.1/ld/Makefile.am -index 1280b64..5a7c71a 100644 ---- a/binutils-2.21.1/ld/Makefile.am -+++ binutils-2.21.1/ld/Makefile.am -@@ -211,6 +211,7 @@ ALL_EMULATION_SOURCES = \ - eelf32lppc.c \ - eelf32lppcnto.c \ - eelf32lppcsim.c \ -+ eelf32lriscv.c \ - eelf32lsmip.c \ - eelf32ltsmip.c \ - eelf32ltsmipn32.c \ -@@ -454,6 +455,7 @@ ALL_64_EMULATION_SOURCES = \ - eelf64btsmip.c \ - eelf64hppa.c \ - eelf64lppc.c \ -+ eelf64lriscv.c \ - eelf64ltsmip.c \ - eelf64mmix.c \ - eelf64ppc.c \ -@@ -963,6 +965,10 @@ eelf32lppcsim.c: $(srcdir)/emulparams/elf32lppcsim.sh \ - ldemul-list.h \ - $(ELF_DEPS) $(srcdir)/scripttempl/elf.sc ${GEN_DEPENDS} - ${GENSCRIPTS} elf32lppcsim "$(tdir_elf32lppcsim)" -+eelf32lriscv.c: $(srcdir)/emulparams/elf32lriscv.sh \ -+ $(srcdir)/emulparams/elf32lriscv-defs.sh $(ELF_DEPS) \ -+ $(srcdir)/emultempl/mipself.em $(srcdir)/scripttempl/elf.sc ${GEN_DEPENDS} -+ ${GENSCRIPTS} elf32lriscv "$(tdir_elf32lriscv)" - eelf32lsmip.c: $(srcdir)/emulparams/elf32lsmip.sh \ - $(srcdir)/emulparams/elf32lmip.sh $(srcdir)/emulparams/elf32bmip.sh \ - $(ELF_DEPS) $(srcdir)/emultempl/mipself.em $(srcdir)/scripttempl/elf.sc \ -@@ -1848,6 +1854,11 @@ eelf64lppc.c: $(srcdir)/emulparams/elf64lppc.sh \ - ldemul-list.h \ - $(ELF_DEPS) $(srcdir)/scripttempl/elf.sc ${GEN_DEPENDS} - ${GENSCRIPTS} elf64lppc "$(tdir_elf64lppc)" -+eelf64lriscv.c: $(srcdir)/emulparams/elf64lriscv.sh \ -+ $(srcdir)/emulparams/elf64lriscv-defs.sh \ -+ $(srcdir)/emulparams/elf32lriscv-defs.sh $(ELF_DEPS) \ -+ $(srcdir)/emultempl/mipself.em $(srcdir)/scripttempl/elf.sc ${GEN_DEPENDS} -+ ${GENSCRIPTS} elf64lriscv "$(tdir_elf64lriscv)" - eelf64ltsmip.c: $(srcdir)/emulparams/elf64ltsmip.sh \ - $(srcdir)/emulparams/elf64btsmip.sh $(srcdir)/emulparams/elf64bmip-defs.sh \ - $(srcdir)/emulparams/elf32bmipn32-defs.sh $(ELF_DEPS) \ -diff --git a/binutils-2.21.1/ld/Makefile.in b/binutils-2.21.1/ld/Makefile.in -index 00fcd72..2db7ce6 100644 ---- a/binutils-2.21.1/ld/Makefile.in -+++ binutils-2.21.1/ld/Makefile.in -@@ -516,6 +516,7 @@ ALL_EMULATION_SOURCES = \ - eelf32lppc.c \ - eelf32lppcnto.c \ - eelf32lppcsim.c \ -+ eelf32lriscv.c \ - eelf32lsmip.c \ - eelf32ltsmip.c \ - eelf32ltsmipn32.c \ -@@ -758,6 +759,7 @@ ALL_64_EMULATION_SOURCES = \ - eelf64btsmip.c \ - eelf64hppa.c \ - eelf64lppc.c \ -+ eelf64lriscv.c \ - eelf64ltsmip.c \ - eelf64mmix.c \ - eelf64ppc.c \ -@@ -1098,6 +1100,7 @@ distclean-compile: - @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/eelf32lppc.Po@am__quote@ - @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/eelf32lppcnto.Po@am__quote@ - @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/eelf32lppcsim.Po@am__quote@ -+@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/eelf32lriscv.Po@am__quote@ - @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/eelf32lsmip.Po@am__quote@ - @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/eelf32ltsmip.Po@am__quote@ - @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/eelf32ltsmipn32.Po@am__quote@ -@@ -1138,6 +1141,7 @@ distclean-compile: - @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/eelf64btsmip.Po@am__quote@ - @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/eelf64hppa.Po@am__quote@ - @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/eelf64lppc.Po@am__quote@ -+@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/eelf64lriscv.Po@am__quote@ - @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/eelf64ltsmip.Po@am__quote@ - @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/eelf64mmix.Po@am__quote@ - @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/eelf64ppc.Po@am__quote@ -@@ -2398,6 +2402,10 @@ eelf32lppcsim.c: $(srcdir)/emulparams/elf32lppcsim.sh \ - ldemul-list.h \ - $(ELF_DEPS) $(srcdir)/scripttempl/elf.sc ${GEN_DEPENDS} - ${GENSCRIPTS} elf32lppcsim "$(tdir_elf32lppcsim)" -+eelf32lriscv.c: $(srcdir)/emulparams/elf32lriscv.sh \ -+ $(srcdir)/emulparams/elf32lriscv-defs.sh $(ELF_DEPS) \ -+ $(srcdir)/emultempl/mipself.em $(srcdir)/scripttempl/elf.sc ${GEN_DEPENDS} -+ ${GENSCRIPTS} elf32lriscv "$(tdir_elf32lriscv)" - eelf32lsmip.c: $(srcdir)/emulparams/elf32lsmip.sh \ - $(srcdir)/emulparams/elf32lmip.sh $(srcdir)/emulparams/elf32bmip.sh \ - $(ELF_DEPS) $(srcdir)/emultempl/mipself.em $(srcdir)/scripttempl/elf.sc \ -@@ -3283,6 +3291,11 @@ eelf64lppc.c: $(srcdir)/emulparams/elf64lppc.sh \ - ldemul-list.h \ - $(ELF_DEPS) $(srcdir)/scripttempl/elf.sc ${GEN_DEPENDS} - ${GENSCRIPTS} elf64lppc "$(tdir_elf64lppc)" -+eelf64lriscv.c: $(srcdir)/emulparams/elf64lriscv.sh \ -+ $(srcdir)/emulparams/elf64lriscv-defs.sh \ -+ $(srcdir)/emulparams/elf32lriscv-defs.sh $(ELF_DEPS) \ -+ $(srcdir)/emultempl/mipself.em $(srcdir)/scripttempl/elf.sc ${GEN_DEPENDS} -+ ${GENSCRIPTS} elf64lriscv "$(tdir_elf64lriscv)" - eelf64ltsmip.c: $(srcdir)/emulparams/elf64ltsmip.sh \ - $(srcdir)/emulparams/elf64btsmip.sh $(srcdir)/emulparams/elf64bmip-defs.sh \ - $(srcdir)/emulparams/elf32bmipn32-defs.sh $(ELF_DEPS) \ -diff --git a/binutils-2.21.1/ld/configure.tgt b/binutils-2.21.1/ld/configure.tgt -index 90d7461..dc79744 100644 ---- a/binutils-2.21.1/ld/configure.tgt -+++ binutils-2.21.1/ld/configure.tgt -@@ -504,6 +504,9 @@ powerpc-*-aix*) targ_emul=aixppc ;; - powerpc-*-beos*) targ_emul=aixppc ;; - powerpc-*-windiss*) targ_emul=elf32ppcwindiss ;; - powerpc-*-lynxos*) targ_emul=ppclynx ;; -+riscv*-*-*) targ_emul=elf64lriscv -+ targ_extra_emuls="elf32lriscv" -+ targ_extra_libpath=$targ_extra_emuls ;; - rs6000-*-aix[5-9]*) targ_emul=aix5rs6 ;; - rs6000-*-aix*) targ_emul=aixrs6 - ;; -diff --git a/binutils-2.21.1/ld/emulparams/elf32lriscv-defs.sh b/binutils-2.21.1/ld/emulparams/elf32lriscv-defs.sh -new file mode 100644 -index 0000000..fba4f7f ---- /dev/null -+++ binutils-2.21.1/ld/emulparams/elf32lriscv-defs.sh -@@ -0,0 +1,59 @@ -+# This is an ELF platform. -+SCRIPT_NAME=elf -+ -+# Handle both big- and little-ended 32-bit MIPS objects. -+ARCH=riscv -+OUTPUT_FORMAT="elf32-littleriscv" -+ -+TEMPLATE_NAME=elf32 -+EXTRA_EM_FILE=riscvelf -+ -+case "$EMULATION_NAME" in -+elf32*) ELFSIZE=32; LIBPATH_SUFFIX=32 ;; -+elf64*) ELFSIZE=64; LIBPATH_SUFFIX= ;; -+*) echo $0: unhandled emulation $EMULATION_NAME >&2; exit 1 ;; -+esac -+ -+if test `echo "$host" | sed -e s/64//` = `echo "$target" | sed -e s/64//`; then -+ case " $EMULATION_LIBPATH " in -+ *" ${EMULATION_NAME} "*) -+ NATIVE=yes -+ ;; -+ esac -+fi -+ -+GENERATE_SHLIB_SCRIPT=yes -+GENERATE_PIE_SCRIPT=yes -+ -+TEXT_START_ADDR=0x10000000 -+SHLIB_TEXT_START_ADDR=0x1000000 -+MAXPAGESIZE="CONSTANT (MAXPAGESIZE)" -+ENTRY=_start -+ -+# Unlike most targets, the MIPS backend puts all dynamic relocations -+# in a single dynobj section, which it also calls ".rel.dyn". It does -+# this so that it can easily sort all dynamic relocations before the -+# output section has been populated. -+OTHER_GOT_RELOC_SECTIONS=" -+ .rel.dyn ${RELOCATING-0} : { *(.rel.dyn) } -+" -+GOT=".got ${RELOCATING-0} : { *(.got) }" -+unset OTHER_READWRITE_SECTIONS -+unset OTHER_RELRO_SECTIONS -+ -+# Magic symbols. -+TEXT_START_SYMBOLS='_ftext = . ;' -+DATA_START_SYMBOLS='_fdata = . ;' -+OTHER_BSS_SYMBOLS='_fbss = .;' -+ -+INITIAL_READONLY_SECTIONS=".interp ${RELOCATING-0} : { *(.interp) }" -+SDATA_START_SYMBOLS="_gp = . + 0x800; -+ *(.srodata.cst16) *(.srodata.cst8) *(.srodata.cst4) *(.srodata.cst2) *(.srodata*)" -+if test -n "${CREATE_SHLIB}"; then -+ INITIAL_READONLY_SECTIONS= -+ SDATA_START_SYMBOLS= -+ OTHER_READONLY_SECTIONS=".srodata ${RELOCATING-0} : { *(.srodata.cst16) *(.srodata.cst8) *(.srodata.cst4) *(.srodata.cst2) *(.srodata*) }" -+ unset GOT -+fi -+ -+TEXT_DYNAMIC= -diff --git a/binutils-2.21.1/ld/emulparams/elf32lriscv.sh b/binutils-2.21.1/ld/emulparams/elf32lriscv.sh -new file mode 100644 -index 0000000..8ccd147 ---- /dev/null -+++ binutils-2.21.1/ld/emulparams/elf32lriscv.sh -@@ -0,0 +1,12 @@ -+# If you change this file, please also look at files which source this one: -+# elf32ltsmipn32.sh -+ -+. ${srcdir}/emulparams/elf32lriscv-defs.sh -+OUTPUT_FORMAT="elf32-littleriscv" -+COMMONPAGESIZE="CONSTANT (COMMONPAGESIZE)" -+ -+# Magic sections. -+OTHER_SECTIONS=' -+ .gptab.sdata : { *(.gptab.data) *(.gptab.sdata) } -+ .gptab.sbss : { *(.gptab.bss) *(.gptab.sbss) } -+' -diff --git a/binutils-2.21.1/ld/emulparams/elf64lriscv-defs.sh b/binutils-2.21.1/ld/emulparams/elf64lriscv-defs.sh -new file mode 100644 -index 0000000..abaf766 ---- /dev/null -+++ binutils-2.21.1/ld/emulparams/elf64lriscv-defs.sh -@@ -0,0 +1,2 @@ -+. ${srcdir}/emulparams/elf32lriscv-defs.sh -+COMMONPAGESIZE="CONSTANT (COMMONPAGESIZE)" -diff --git a/binutils-2.21.1/ld/emulparams/elf64lriscv.sh b/binutils-2.21.1/ld/emulparams/elf64lriscv.sh -new file mode 100644 -index 0000000..a31964b ---- /dev/null -+++ binutils-2.21.1/ld/emulparams/elf64lriscv.sh -@@ -0,0 +1,11 @@ -+# If you change this file, please also look at files which source this one: -+# elf64ltsmip.sh -+ -+. ${srcdir}/emulparams/elf64lriscv-defs.sh -+OUTPUT_FORMAT="elf64-littleriscv" -+ -+# Magic sections. -+OTHER_SECTIONS=' -+ .gptab.sdata : { *(.gptab.data) *(.gptab.sdata) } -+ .gptab.sbss : { *(.gptab.bss) *(.gptab.sbss) } -+' -diff --git a/binutils-2.21.1/ld/emultempl/riscvelf.em b/binutils-2.21.1/ld/emultempl/riscvelf.em -new file mode 100644 -index 0000000..89eda47 ---- /dev/null -+++ binutils-2.21.1/ld/emultempl/riscvelf.em -@@ -0,0 +1,63 @@ -+# This shell script emits a C file. -*- C -*- -+# Copyright 2004, 2006, 2007, 2008 Free Software Foundation, Inc. -+# -+# This file is part of the GNU Binutils. -+# -+# This program is free software; you can redistribute it and/or modify -+# it under the terms of the GNU General Public License as published by -+# the Free Software Foundation; either version 3 of the License, or -+# (at your option) any later version. -+# -+# This program is distributed in the hope that it will be useful, -+# but WITHOUT ANY WARRANTY; without even the implied warranty of -+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -+# GNU General Public License for more details. -+# -+# You should have received a copy of the GNU General Public License -+# along with this program; if not, write to the Free Software -+# Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston, -+# MA 02110-1301, USA. -+ -+fragment < -+#include -+ -+/* FIXME: These should be shared with gdb somehow. */ -+ -+static const char * const mips_gpr_names_numeric[32] = -+{ -+ "x0", "x1", "x2", "x3", "x4", "x5", "x6", "x7", -+ "x8", "x9", "x10", "x11", "x12", "x13", "x14", "x15", -+ "x16", "x17", "x18", "x19", "x20", "x21", "x22", "x23", -+ "x24", "x25", "x26", "x27", "x28", "x29", "x30", "x31" -+}; -+ -+static const char* mips_gpr_names_abi[32] = { -+ "zero", "ra", "s0", "s1", "s2", "s3", "s4", "s5", -+ "s6", "s7", "s8", "s9", "s10", "s11", "sp", "tp", -+ "v0", "v1", "a0", "a1", "a2", "a3", "a4", "a5", -+ "a6", "a7", "t0", "t1", "t2", "t3", "t4", "gp" -+}; -+ -+ -+static const char * const mips_fpr_names_numeric[32] = -+{ -+ "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7", -+ "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15", -+ "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23", -+ "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31" -+}; -+ -+static const char* mips_fpr_names_abi[32] = { -+ "fs0", "fs1", "fs2", "fs3", "fs4", "fs5", "fs6", "fs7", -+ "fs8", "fs9", "fs10", "fs11", "fs12", "fs13", "fs14", "fs15", -+ "fv0", "fv1", "fa0", "fa1", "fa2", "fa3", "fa4", "fa5", -+ "fa6", "fa7", "ft0", "ft1", "ft2", "ft3", "ft4", "ft5" -+}; -+ -+static const char * const mips_vgr_reg_names_riscv[32] = -+{ -+ "vx0", "vx1", "vx2", "vx3", "vx4", "vx5", "vx6", "vx7", -+ "vx8", "vx9", "vx10", "vx11", "vx12", "vx13", "vx14", "vx15", -+ "vx16", "vx17", "vx18", "vx19", "vx20", "vx21", "vx22", "vx23", -+ "vx24", "vx25", "vx26", "vx27", "vx28", "vx29", "vx30", "vx31" -+}; -+ -+static const char * const mips_vfp_reg_names_riscv[32] = -+{ -+ "vf0", "vf1", "vf2", "vf3", "vf4", "vf5", "vf6", "vf7", -+ "vf8", "vf9", "vf10", "vf11", "vf12", "vf13", "vf14", "vf15", -+ "vf16", "vf17", "vf18", "vf19", "vf20", "vf21", "vf22", "vf23", -+ "vf24", "vf25", "vf26", "vf27", "vf28", "vf29", "vf30", "vf31" -+}; -+ -+struct mips_abi_choice -+{ -+ const char * name; -+ const char * const *gpr_names; -+ const char * const *fpr_names; -+}; -+ -+struct mips_abi_choice mips_abi_choices[] = -+{ -+ { "numeric", mips_gpr_names_numeric, mips_fpr_names_numeric }, -+ { "32", mips_gpr_names_abi, mips_fpr_names_abi }, -+ { "64", mips_gpr_names_abi, mips_fpr_names_abi }, -+}; -+ -+struct mips_arch_choice -+{ -+ const char *name; -+ int bfd_mach_valid; -+ unsigned long bfd_mach; -+}; -+ -+const struct mips_arch_choice mips_arch_choices[] = -+{ -+ { "numeric", 0, 0 }, -+ { "rv32", 1, bfd_mach_riscv32 }, -+ { "rv64", 1, bfd_mach_riscv64 }, -+}; -+ -+struct riscv_private_data -+{ -+ bfd_vma gp; -+ bfd_vma print_addr; -+ bfd_vma hi_addr[OP_MASK_RD + 1]; -+}; -+ -+/* ISA and processor type to disassemble for, and register names to use. -+ set_default_mips_dis_options and parse_mips_dis_options fill in these -+ values. */ -+static const char * const *mips_gpr_names; -+static const char * const *mips_fpr_names; -+ -+/* Other options */ -+static int no_aliases; /* If set disassemble as most general inst. */ -+ -+static const struct mips_abi_choice * -+choose_abi_by_name (const char *name, unsigned int namelen) -+{ -+ const struct mips_abi_choice *c; -+ unsigned int i; -+ -+ for (i = 0, c = NULL; i < ARRAY_SIZE (mips_abi_choices) && c == NULL; i++) -+ if (strncmp (mips_abi_choices[i].name, name, namelen) == 0 -+ && strlen (mips_abi_choices[i].name) == namelen) -+ c = &mips_abi_choices[i]; -+ -+ return c; -+} -+ -+static void -+set_default_mips_dis_options (struct disassemble_info *info ATTRIBUTE_UNUSED) -+{ -+ mips_gpr_names = mips_gpr_names_abi; -+ mips_fpr_names = mips_fpr_names_abi; -+ no_aliases = 0; -+} -+ -+static void -+parse_mips_dis_option (const char *option, unsigned int len) -+{ -+ unsigned int i, optionlen, vallen; -+ const char *val; -+ const struct mips_abi_choice *chosen_abi; -+ -+ /* Try to match options that are simple flags */ -+ if (CONST_STRNEQ (option, "no-aliases")) -+ { -+ no_aliases = 1; -+ return; -+ } -+ -+ /* Look for the = that delimits the end of the option name. */ -+ for (i = 0; i < len; i++) -+ if (option[i] == '=') -+ break; -+ -+ if (i == 0) /* Invalid option: no name before '='. */ -+ return; -+ if (i == len) /* Invalid option: no '='. */ -+ return; -+ if (i == (len - 1)) /* Invalid option: no value after '='. */ -+ return; -+ -+ optionlen = i; -+ val = option + (optionlen + 1); -+ vallen = len - (optionlen + 1); -+ -+ if (strncmp ("gpr-names", option, optionlen) == 0 -+ && strlen ("gpr-names") == optionlen) -+ { -+ chosen_abi = choose_abi_by_name (val, vallen); -+ if (chosen_abi != NULL) -+ mips_gpr_names = chosen_abi->gpr_names; -+ return; -+ } -+ -+ if (strncmp ("fpr-names", option, optionlen) == 0 -+ && strlen ("fpr-names") == optionlen) -+ { -+ chosen_abi = choose_abi_by_name (val, vallen); -+ if (chosen_abi != NULL) -+ mips_fpr_names = chosen_abi->fpr_names; -+ return; -+ } -+ -+ /* Invalid option. */ -+} -+ -+static void -+parse_mips_dis_options (const char *options) -+{ -+ const char *option_end; -+ -+ if (options == NULL) -+ return; -+ -+ while (*options != '\0') -+ { -+ /* Skip empty options. */ -+ if (*options == ',') -+ { -+ options++; -+ continue; -+ } -+ -+ /* We know that *options is neither NUL or a comma. */ -+ option_end = options + 1; -+ while (*option_end != ',' && *option_end != '\0') -+ option_end++; -+ -+ parse_mips_dis_option (options, option_end - options); -+ -+ /* Go on to the next one. If option_end points to a comma, it -+ will be skipped above. */ -+ options = option_end; -+ } -+} -+ -+/* Print one argument from an array. */ -+ -+static void -+arg_print (struct disassemble_info *info, unsigned long val, -+ const char* const* array, size_t size) -+{ -+ const char *s = val >= size || array[val] == NULL ? "unknown" : array[val]; -+ (*info->fprintf_func) (info->stream, "%s", s); -+} -+ -+static void -+maybe_print_address (struct riscv_private_data *pd, int base_reg, int offset) -+{ -+ if (pd->hi_addr[base_reg] != (bfd_vma)-1) -+ { -+ pd->print_addr = pd->hi_addr[base_reg] + offset; -+ pd->hi_addr[base_reg] = -1; -+ } -+ else if (base_reg == GP_REG && pd->gp != (bfd_vma)-1) -+ pd->print_addr = pd->gp + offset; -+ else if (base_reg == TP_REG) -+ pd->print_addr = offset; -+} -+ -+/* Print insn arguments for 32/64-bit code. */ -+ -+static void -+print_insn_args (const char *d, insn_t l, bfd_vma pc, disassemble_info *info) -+{ -+ struct riscv_private_data *pd = info->private_data; -+ int rs1 = (l >> OP_SH_RS1) & OP_MASK_RS1; -+ int rd = (l >> OP_SH_RD) & OP_MASK_RD; -+ -+ if (*d != '\0') -+ (*info->fprintf_func) (info->stream, "\t"); -+ -+ for (; *d != '\0'; d++) -+ { -+ switch (*d) -+ { -+ /* Xcustom */ -+ case '^': -+ switch (*++d) -+ { -+ case 'd': -+ (*info->fprintf_func) (info->stream, "%d", rd); -+ break; -+ case 's': -+ (*info->fprintf_func) (info->stream, "%d", rs1); -+ break; -+ case 't': -+ (*info->fprintf_func) -+ ( info->stream, "%d", ((l >> OP_SH_RS2) & OP_MASK_RS2)); -+ break; -+ case 'j': -+ (*info->fprintf_func) -+ ( info->stream, "%d", ((l >> OP_SH_CUSTOM_IMM) & OP_MASK_CUSTOM_IMM)); -+ break; -+ } -+ break; -+ -+ /* Xhwacha */ -+ case '#': -+ switch ( *++d ) { -+ case 'g': -+ (*info->fprintf_func) -+ ( info->stream, "%d", -+ ((l >> OP_SH_IMMNGPR) & OP_MASK_IMMNGPR)); -+ break; -+ case 'f': -+ (*info->fprintf_func) -+ ( info->stream, "%d", -+ ((l >> OP_SH_IMMNFPR) & OP_MASK_IMMNFPR)); -+ break; -+ case 'p': -+ (*info->fprintf_func) -+ ( info->stream, "%d", -+ ((l >> OP_SH_CUSTOM_IMM) & OP_MASK_CUSTOM_IMM)); -+ break; -+ case 'n': -+ (*info->fprintf_func) -+ ( info->stream, "%d", -+ (((l >> OP_SH_IMMSEGNELM) & OP_MASK_IMMSEGNELM) + 1)); -+ break; -+ case 'd': -+ (*info->fprintf_func) -+ ( info->stream, "%s", -+ mips_vgr_reg_names_riscv[(l >> OP_SH_VRD) & OP_MASK_VRD]); -+ break; -+ case 's': -+ (*info->fprintf_func) -+ ( info->stream, "%s", -+ mips_vgr_reg_names_riscv[(l >> OP_SH_VRS) & OP_MASK_VRS]); -+ break; -+ case 't': -+ (*info->fprintf_func) -+ ( info->stream, "%s", -+ mips_vgr_reg_names_riscv[(l >> OP_SH_VRT) & OP_MASK_VRT]); -+ break; -+ case 'r': -+ (*info->fprintf_func) -+ ( info->stream, "%s", -+ mips_vgr_reg_names_riscv[(l >> OP_SH_VRR) & OP_MASK_VRR]); -+ break; -+ case 'D': -+ (*info->fprintf_func) -+ ( info->stream, "%s", -+ mips_vfp_reg_names_riscv[(l >> OP_SH_VFD) & OP_MASK_VFD]); -+ break; -+ case 'S': -+ (*info->fprintf_func) -+ ( info->stream, "%s", -+ mips_vfp_reg_names_riscv[(l >> OP_SH_VFS) & OP_MASK_VFS]); -+ break; -+ case 'T': -+ (*info->fprintf_func) -+ ( info->stream, "%s", -+ mips_vfp_reg_names_riscv[(l >> OP_SH_VFT) & OP_MASK_VFT]); -+ break; -+ case 'R': -+ (*info->fprintf_func) -+ ( info->stream, "%s", -+ mips_vfp_reg_names_riscv[(l >> OP_SH_VFR) & OP_MASK_VFR]); -+ break; -+ } -+ break; -+ -+ case ',': -+ case '(': -+ case ')': -+ case '[': -+ case ']': -+ (*info->fprintf_func) (info->stream, "%c", *d); -+ break; -+ -+ case '0': -+ break; -+ -+ case 'b': -+ case 's': -+ (*info->fprintf_func) (info->stream, "%s", mips_gpr_names[rs1]); -+ break; -+ -+ case 't': -+ (*info->fprintf_func) (info->stream, "%s", -+ mips_gpr_names[(l >> OP_SH_RS2) & OP_MASK_RS2]); -+ break; -+ -+ case 'u': -+ (*info->fprintf_func) (info->stream, "0x%lx", (uint32_t)EXTRACT_UTYPE_IMM (l) << RISCV_IMM_BITS >> RISCV_IMM_BITS); -+ break; -+ -+ case 'm': -+ arg_print(info, (l >> OP_SH_RM) & OP_MASK_RM, -+ riscv_rm, ARRAY_SIZE(riscv_rm)); -+ break; -+ -+ case 'P': -+ arg_print(info, (l >> OP_SH_PRED) & OP_MASK_PRED, -+ riscv_pred_succ, ARRAY_SIZE(riscv_pred_succ)); -+ break; -+ -+ case 'Q': -+ arg_print(info, (l >> OP_SH_SUCC) & OP_MASK_SUCC, -+ riscv_pred_succ, ARRAY_SIZE(riscv_pred_succ)); -+ break; -+ -+ case 'o': -+ maybe_print_address (pd, rs1, EXTRACT_ITYPE_IMM (l)); -+ case 'j': -+ if ((l & MASK_ADDI) == MATCH_ADDI) -+ maybe_print_address (pd, rs1, EXTRACT_ITYPE_IMM (l)); -+ (*info->fprintf_func) (info->stream, "%d", EXTRACT_ITYPE_IMM (l)); -+ break; -+ -+ case 'q': -+ maybe_print_address (pd, rs1, EXTRACT_STYPE_IMM (l)); -+ (*info->fprintf_func) (info->stream, "%d", EXTRACT_STYPE_IMM (l)); -+ break; -+ -+ case 'a': -+ info->target = EXTRACT_UJTYPE_IMM (l) + pc; -+ (*info->print_address_func) (info->target, info); -+ break; -+ -+ case 'p': -+ info->target = EXTRACT_SBTYPE_IMM (l) + pc; -+ (*info->print_address_func) (info->target, info); -+ break; -+ -+ case 'd': -+ if ((l & MASK_AUIPC) == MATCH_AUIPC) -+ pd->hi_addr[rd] = pc + (EXTRACT_UTYPE_IMM (l) << RISCV_IMM_BITS); -+ else if ((l & MASK_LUI) == MATCH_LUI) -+ pd->hi_addr[rd] = EXTRACT_UTYPE_IMM (l) << RISCV_IMM_BITS; -+ (*info->fprintf_func) (info->stream, "%s", mips_gpr_names[rd]); -+ break; -+ -+ case 'z': -+ (*info->fprintf_func) (info->stream, "%s", mips_gpr_names[0]); -+ break; -+ -+ case '>': -+ (*info->fprintf_func) (info->stream, "0x%lx", -+ (l >> OP_SH_SHAMT) & OP_MASK_SHAMT); -+ break; -+ -+ case '<': -+ (*info->fprintf_func) (info->stream, "0x%lx", -+ (l >> OP_SH_SHAMTW) & OP_MASK_SHAMTW); -+ break; -+ -+ case 'S': -+ case 'U': -+ (*info->fprintf_func) (info->stream, "%s", mips_fpr_names[rs1]); -+ break; -+ -+ case 'T': -+ (*info->fprintf_func) (info->stream, "%s", -+ mips_fpr_names[(l >> OP_SH_RS2) & OP_MASK_RS2]); -+ break; -+ -+ case 'D': -+ (*info->fprintf_func) (info->stream, "%s", mips_fpr_names[rd]); -+ break; -+ -+ case 'R': -+ (*info->fprintf_func) (info->stream, "%s", -+ mips_fpr_names[(l >> OP_SH_RS3) & OP_MASK_RS3]); -+ break; -+ -+ case 'E': -+ { -+ const char* csr_name = "unknown"; -+ switch ((l >> OP_SH_CSR) & OP_MASK_CSR) -+ { -+ #define DECLARE_CSR(name, num) case num: csr_name = #name; break; -+ #include "opcode/riscv-opc.h" -+ #undef DECLARE_CSR -+ } -+ (*info->fprintf_func) (info->stream, "%s", csr_name); -+ break; -+ } -+ -+ case 'Z': -+ (*info->fprintf_func) (info->stream, "%d", rs1); -+ break; -+ -+ default: -+ /* xgettext:c-format */ -+ (*info->fprintf_func) (info->stream, -+ _("# internal error, undefined modifier (%c)"), -+ *d); -+ return; -+ } -+ } -+} -+ -+#if 0 -+static unsigned long -+riscv_rvc_uncompress(unsigned long rvc_insn) -+{ -+ #define IS_INSN(x, op) (((x) & MASK_##op) == MATCH_##op) -+ #define EXTRACT_OPERAND(x, op) (((x) >> OP_SH_##op) & OP_MASK_##op) -+ -+ int crd = EXTRACT_OPERAND(rvc_insn, CRD); -+ int crs1 = EXTRACT_OPERAND(rvc_insn, CRS1); -+ int crs2 = EXTRACT_OPERAND(rvc_insn, CRS2); -+ int crds = EXTRACT_OPERAND(rvc_insn, CRDS); -+ int crs1s = EXTRACT_OPERAND(rvc_insn, CRS1S); -+ int crs2s = EXTRACT_OPERAND(rvc_insn, CRS2S); -+ int crs2bs = EXTRACT_OPERAND(rvc_insn, CRS2BS); -+ -+ int cimm6 = EXTRACT_OPERAND(rvc_insn, CIMM6); -+ int imm6 = ((int32_t)cimm6 << 26 >> 26) & (RISCV_IMM_REACH-1); -+ int imm6x4 = (((int32_t)cimm6 << 26 >> 26)*4) & (RISCV_IMM_REACH-1); -+ int imm6x4lo = imm6x4 & ((1<> RISCV_IMMLO_BITS) & ((1<> 26)*8) & (RISCV_IMM_REACH-1); -+ int imm6x8lo = imm6x8 & ((1<> RISCV_IMMLO_BITS) & ((1<> 27) & (RISCV_IMM_REACH-1); -+ int imm5lo = imm5 & ((1<> RISCV_IMMLO_BITS) & ((1<> 27)*4) & (RISCV_IMM_REACH-1); -+ int imm5x4lo = imm5x4 & ((1<> RISCV_IMMLO_BITS) & ((1<> 27)*8) & (RISCV_IMM_REACH-1); -+ int imm5x8lo = imm5x8 & ((1<> RISCV_IMMLO_BITS) & ((1<> 22) & ((1<section->owner)->e_flags; -+ extension = riscv_elf_flag_to_name(EF_GET_RISCV_EXT(e_flags)); -+ -+ for (i = 0; i <= OP_MASK_OP; i++) -+ for (op = riscv_opcodes; op < &riscv_opcodes[NUMOPCODES]; op++) -+ if (i == ((op->match >> OP_SH_OP) & OP_MASK_OP)) -+ { -+ mips_hash[i] = op; -+ break; -+ } -+ -+ init = 1; -+ } -+ -+ if (info->private_data == NULL) -+ { -+ int i; -+ -+ pd = info->private_data = calloc(1, sizeof (struct riscv_private_data)); -+ pd->gp = -1; -+ pd->print_addr = -1; -+ for (i = 0; i < (int) ARRAY_SIZE(pd->hi_addr); i++) -+ pd->hi_addr[i] = -1; -+ -+ for (i = 0; i < info->symtab_size; i++) -+ if (strcmp (bfd_asymbol_name (info->symtab[i]), "_gp") == 0) -+ pd->gp = bfd_asymbol_value (info->symtab[i]); -+ } -+ else -+ pd = info->private_data; -+ -+ insnlen = riscv_insn_length (word); -+ -+#if 0 -+ if (insnlen == 2) -+ word = riscv_rvc_uncompress(word); -+#endif -+ -+ info->bytes_per_chunk = insnlen % 4 == 0 ? 4 : 2; -+ info->bytes_per_line = 8; -+ info->display_endian = info->endian; -+ info->insn_info_valid = 1; -+ info->branch_delay_insns = 0; -+ info->data_size = 0; -+ info->insn_type = dis_nonbranch; -+ info->target = 0; -+ info->target2 = 0; -+ -+ op = mips_hash[(word >> OP_SH_OP) & OP_MASK_OP]; -+ if (op != NULL) -+ { -+ for (; op < &riscv_opcodes[NUMOPCODES]; op++) -+ { -+ if ((op->match_func) (op, word) -+ && !(no_aliases && (op->pinfo & INSN_ALIAS)) -+ && !(op->subset[0] == 'X' && strcmp(op->subset, extension))) -+ { -+ (*info->fprintf_func) (info->stream, "%s", op->name); -+ print_insn_args (op->args, word, memaddr, info); -+ if (pd->print_addr != (bfd_vma)-1) -+ { -+ info->target = pd->print_addr; -+ (*info->fprintf_func) (info->stream, " # ", word); -+ (*info->print_address_func) (info->target, info); -+ pd->print_addr = -1; -+ } -+ return insnlen; -+ } -+ } -+ } -+ -+ /* Handle undefined instructions. */ -+ info->insn_type = dis_noninsn; -+ (*info->fprintf_func) (info->stream, "0x%llx", (unsigned long long)word); -+ return insnlen; -+} -+ -+/* In an environment where we do not know the symbol type of the -+ instruction we are forced to assume that the low order bit of the -+ instructions' address may mark it as a mips16 instruction. If we -+ are single stepping, or the pc is within the disassembled function, -+ this works. Otherwise, we need a clue. Sometimes. */ -+ -+static int -+_print_insn_mips (bfd_vma memaddr, -+ struct disassemble_info *info, -+ enum bfd_endian endianness) -+{ -+ uint16_t i2; -+ insn_t insn = 0; -+ bfd_vma n; -+ int status; -+ -+ set_default_mips_dis_options (info); -+ parse_mips_dis_options (info->disassembler_options); -+ -+ /* Instructions are stored as a sequence of 2-byte packets in little-endian -+ order. (Within a packet, the byte order is the target endianness). */ -+ for (n = 0; n < sizeof(insn) && n < riscv_insn_length (insn); n += 2) -+ { -+ status = (*info->read_memory_func) (memaddr + n, (bfd_byte*)&i2, 2, info); -+ if (status != 0) -+ { -+ if (n > 0) /* Don't fail just because we fell off the end. */ -+ break; -+ (*info->memory_error_func) (status, memaddr, info); -+ return status; -+ } -+ -+ i2 = endianness == BFD_ENDIAN_BIG ? bfd_getb16 (&i2) : bfd_getl16 (&i2); -+ insn |= (insn_t)i2 << (8*n); -+ } -+ -+ return print_insn_mips (memaddr, insn, info); -+} -+ -+int -+print_insn_big_riscv (bfd_vma memaddr ATTRIBUTE_UNUSED, -+ struct disassemble_info *info ATTRIBUTE_UNUSED) -+{ -+ return _print_insn_mips (memaddr, info, BFD_ENDIAN_BIG); -+} -+ -+int -+print_insn_little_riscv (bfd_vma memaddr, struct disassemble_info *info) -+{ -+ return _print_insn_mips (memaddr, info, BFD_ENDIAN_LITTLE); -+} -+ -+void -+print_mips_disassembler_options (FILE *stream) -+{ -+ unsigned int i; -+ -+ fprintf (stream, _("\n\ -+The following MIPS specific disassembler options are supported for use\n\ -+with the -M switch (multiple options should be separated by commas):\n")); -+ -+ fprintf (stream, _("\n\ -+ gpr-names=ABI Print GPR names according to specified ABI.\n\ -+ Default: based on binary being disassembled.\n")); -+ -+ fprintf (stream, _("\n\ -+ fpr-names=ABI Print FPR names according to specified ABI.\n\ -+ Default: numeric.\n")); -+ -+ fprintf (stream, _("\n\ -+ For the options above, the following values are supported for \"ABI\":\n\ -+ ")); -+ for (i = 0; i < ARRAY_SIZE (mips_abi_choices); i++) -+ fprintf (stream, " %s", mips_abi_choices[i].name); -+ fprintf (stream, _("\n")); -+ -+ fprintf (stream, _("\n")); -+} -diff --git a/binutils-2.21.1/opcodes/riscv-opc.c b/binutils-2.21.1/opcodes/riscv-opc.c -new file mode 100644 -index 0000000..c110732 ---- /dev/null -+++ binutils-2.21.1/opcodes/riscv-opc.c -@@ -0,0 +1,686 @@ -+/* mips-opc.c -- MIPS opcode list. -+ Copyright 1993, 1994, 1995, 1996, 1997, 1998, 1999, 2000, 2001, 2002 -+ 2003, 2004, 2005, 2007, 2008, 2009 Free Software Foundation, Inc. -+ Contributed by Ralph Campbell and OSF -+ Commented and modified by Ian Lance Taylor, Cygnus Support -+ Extended for MIPS32 support by Anders Norlander, and by SiByte, Inc. -+ MIPS-3D, MDMX, and MIPS32 Release 2 support added by Broadcom -+ Corporation (SiByte). -+ -+ This file is part of the GNU opcodes library. -+ -+ This library is free software; you can redistribute it and/or modify -+ it under the terms of the GNU General Public License as published by -+ the Free Software Foundation; either version 3, or (at your option) -+ any later version. -+ -+ It is distributed in the hope that it will be useful, but WITHOUT -+ ANY WARRANTY; without even the implied warranty of MERCHANTABILITY -+ or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public -+ License for more details. -+ -+ You should have received a copy of the GNU General Public License -+ along with this file; see the file COPYING. If not, write to the -+ Free Software Foundation, 51 Franklin Street - Fifth Floor, Boston, -+ MA 02110-1301, USA. */ -+ -+#include -+#include "sysdep.h" -+#include "opcode/riscv.h" -+ -+/* Short hand so the lines aren't too long. */ -+ -+/* The order of overloaded instructions matters. Label arguments and -+ register arguments look the same. Instructions that can have either -+ for arguments must apear in the correct order in this table for the -+ assembler to pick the right one. In other words, entries with -+ immediate operands must apear after the same instruction with -+ registers. -+ -+ Because of the lookup algorithm used, entries with the same opcode -+ name must be contiguous. */ -+ -+#define WR_xd INSN_WRITE_GPR_D -+#define WR_fd INSN_WRITE_FPR_D -+#define RD_xs1 INSN_READ_GPR_S -+#define RD_xs2 INSN_READ_GPR_T -+#define RD_fs1 INSN_READ_FPR_S -+#define RD_fs2 INSN_READ_FPR_T -+#define RD_fs3 INSN_READ_FPR_R -+ -+#define MASK_RS1 (OP_MASK_RS1 << OP_SH_RS1) -+#define MASK_RS2 (OP_MASK_RS2 << OP_SH_RS2) -+#define MASK_RD (OP_MASK_RD << OP_SH_RD) -+#define MASK_IMM ENCODE_ITYPE_IMM(-1U) -+#define MASK_UIMM ENCODE_UTYPE_IMM(-1U) -+#define MASK_RM (OP_MASK_RM << OP_SH_RM) -+#define MASK_PRED (OP_MASK_PRED << OP_SH_PRED) -+#define MASK_SUCC (OP_MASK_SUCC << OP_SH_SUCC) -+#define MASK_AQ (OP_MASK_AQ << OP_SH_AQ) -+#define MASK_RL (OP_MASK_RL << OP_SH_RL) -+#define MASK_AQRL (MASK_AQ | MASK_RL) -+ -+static int match_opcode(const struct riscv_opcode *op, insn_t insn) -+{ -+ return (insn & op->mask) == op->match; -+} -+ -+static int match_never(const struct riscv_opcode *op ATTRIBUTE_UNUSED, -+ insn_t insn ATTRIBUTE_UNUSED) -+{ -+ return 0; -+} -+ -+static int match_rs1_eq_rs2(const struct riscv_opcode *op, insn_t insn) -+{ -+ return match_opcode(op, insn) && -+ ((insn & MASK_RS1) >> OP_SH_RS1) == ((insn & MASK_RS2) >> OP_SH_RS2); -+} -+ -+const struct riscv_opcode riscv_builtin_opcodes[] = -+{ -+/* These instructions appear first so that the disassembler will find -+ them first. The assemblers uses a hash table based on the -+ instruction name anyhow. */ -+/* name, isa, operands, match, mask, pinfo */ -+{"unimp", "I", "", 0, 0xffff, match_opcode, 0 }, -+{"nop", "I", "", MATCH_ADDI, MASK_ADDI | MASK_RD | MASK_RS1 | MASK_IMM, match_opcode, INSN_ALIAS }, -+{"li", "I", "d,j", MATCH_ADDI, MASK_ADDI | MASK_RS1, match_opcode, INSN_ALIAS|WR_xd }, /* addi */ -+{"li", "I", "d,I", 0, (int) M_LI, match_never, INSN_MACRO }, -+{"mv", "I", "d,s", MATCH_ADDI, MASK_ADDI | MASK_IMM, match_opcode, INSN_ALIAS|WR_xd|RD_xs1 }, -+{"move", "I", "d,s", MATCH_ADDI, MASK_ADDI | MASK_IMM, match_opcode, INSN_ALIAS|WR_xd|RD_xs1 }, -+{"b", "I", "p", MATCH_BEQ, MASK_BEQ | MASK_RS1 | MASK_RS2, match_opcode, 0 },/* beq 0,0 */ -+{"andi", "I", "d,s,j", MATCH_ANDI, MASK_ANDI, match_opcode, WR_xd|RD_xs1 }, -+{"and", "I", "d,s,t", MATCH_AND, MASK_AND, match_opcode, WR_xd|RD_xs1|RD_xs2 }, -+{"and", "I", "d,s,j", MATCH_ANDI, MASK_ANDI, match_opcode, INSN_ALIAS|WR_xd|RD_xs1 }, -+{"beqz", "I", "s,p", MATCH_BEQ, MASK_BEQ | MASK_RS2, match_opcode, INSN_ALIAS|RD_xs1 }, -+{"beq", "I", "s,t,p", MATCH_BEQ, MASK_BEQ, match_opcode, RD_xs1|RD_xs2 }, -+{"blez", "I", "t,p", MATCH_BGE, MASK_BGE | MASK_RS1, match_opcode, INSN_ALIAS|RD_xs2 }, -+{"bgez", "I", "s,p", MATCH_BGE, MASK_BGE | MASK_RS2, match_opcode, INSN_ALIAS|RD_xs1 }, -+{"ble", "I", "t,s,p", MATCH_BGE, MASK_BGE, match_opcode, INSN_ALIAS|RD_xs1|RD_xs2 }, -+{"bleu", "I", "t,s,p", MATCH_BGEU, MASK_BGEU, match_opcode, INSN_ALIAS|RD_xs1|RD_xs2 }, -+{"bge", "I", "s,t,p", MATCH_BGE, MASK_BGE, match_opcode, RD_xs1|RD_xs2 }, -+{"bgeu", "I", "s,t,p", MATCH_BGEU, MASK_BGEU, match_opcode, RD_xs1|RD_xs2 }, -+{"bltz", "I", "s,p", MATCH_BLT, MASK_BLT | MASK_RS2, match_opcode, INSN_ALIAS|RD_xs1 }, -+{"bgtz", "I", "t,p", MATCH_BLT, MASK_BLT | MASK_RS1, match_opcode, INSN_ALIAS|RD_xs2 }, -+{"blt", "I", "s,t,p", MATCH_BLT, MASK_BLT, match_opcode, RD_xs1|RD_xs2 }, -+{"bltu", "I", "s,t,p", MATCH_BLTU, MASK_BLTU, match_opcode, RD_xs1|RD_xs2 }, -+{"bgt", "I", "t,s,p", MATCH_BLT, MASK_BLT, match_opcode, INSN_ALIAS|RD_xs1|RD_xs2 }, -+{"bgtu", "I", "t,s,p", MATCH_BLTU, MASK_BLTU, match_opcode, INSN_ALIAS|RD_xs1|RD_xs2 }, -+{"bnez", "I", "s,p", MATCH_BNE, MASK_BNE | MASK_RS2, match_opcode, INSN_ALIAS|RD_xs1 }, -+{"bne", "I", "s,t,p", MATCH_BNE, MASK_BNE, match_opcode, RD_xs1|RD_xs2 }, -+{"addi", "I", "d,s,j", MATCH_ADDI, MASK_ADDI, match_opcode, WR_xd|RD_xs1 }, -+{"add", "I", "d,s,t", MATCH_ADD, MASK_ADD, match_opcode, WR_xd|RD_xs1|RD_xs2 }, -+{"add", "I", "d,s,t,0",MATCH_ADD, MASK_ADD, match_opcode, WR_xd|RD_xs1|RD_xs2 }, -+{"add", "I", "d,s,j", MATCH_ADDI, MASK_ADDI, match_opcode, INSN_ALIAS|WR_xd|RD_xs1 }, -+{"la", "I", "d,A", 0, (int) M_LA, match_never, INSN_MACRO }, -+{"lla", "I", "d,A", 0, (int) M_LLA, match_never, INSN_MACRO }, -+{"la.tls.gd", "I", "d,A", 0, (int) M_LA_TLS_GD, match_never, INSN_MACRO }, -+{"la.tls.ie", "I", "d,A", 0, (int) M_LA_TLS_IE, match_never, INSN_MACRO }, -+{"neg", "I", "d,t", MATCH_SUB, MASK_SUB | MASK_RS1, match_opcode, INSN_ALIAS|WR_xd|RD_xs2 }, /* sub 0 */ -+{"slli", "I", "d,s,>", MATCH_SLLI, MASK_SLLI, match_opcode, WR_xd|RD_xs1 }, -+{"sll", "I", "d,s,t", MATCH_SLL, MASK_SLL, match_opcode, WR_xd|RD_xs1|RD_xs2 }, -+{"sll", "I", "d,s,>", MATCH_SLLI, MASK_SLLI, match_opcode, INSN_ALIAS|WR_xd|RD_xs1 }, -+{"srli", "I", "d,s,>", MATCH_SRLI, MASK_SRLI, match_opcode, WR_xd|RD_xs1 }, -+{"srl", "I", "d,s,t", MATCH_SRL, MASK_SRL, match_opcode, WR_xd|RD_xs1|RD_xs2 }, -+{"srl", "I", "d,s,>", MATCH_SRLI, MASK_SRLI, match_opcode, INSN_ALIAS|WR_xd|RD_xs1 }, -+{"srai", "I", "d,s,>", MATCH_SRAI, MASK_SRAI, match_opcode, WR_xd|RD_xs1 }, -+{"sra", "I", "d,s,t", MATCH_SRA, MASK_SRA, match_opcode, WR_xd|RD_xs1|RD_xs2 }, -+{"sra", "I", "d,s,>", MATCH_SRAI, MASK_SRAI, match_opcode, INSN_ALIAS|WR_xd|RD_xs1 }, -+{"sub", "I", "d,s,t", MATCH_SUB, MASK_SUB, match_opcode, WR_xd|RD_xs1|RD_xs2 }, -+{"ret", "I", "", MATCH_JALR | (LINK_REG << OP_SH_RS1), MASK_JALR | MASK_RD | MASK_RS1 | MASK_IMM, match_opcode, INSN_ALIAS|WR_xd|RD_xs1 }, -+{"j", "I", "a", MATCH_JAL, MASK_JAL | MASK_RD, match_opcode, INSN_ALIAS }, -+{"jal", "I", "a", MATCH_JAL | (LINK_REG << OP_SH_RD), MASK_JAL | MASK_RD, match_opcode, INSN_ALIAS|WR_xd }, -+{"jal", "I", "d,a", MATCH_JAL, MASK_JAL, match_opcode, WR_xd }, -+{"call", "I", "c", 0, (int) M_CALL, match_never, INSN_MACRO }, -+{"jump", "I", "c", 0, (int) M_JUMP, match_never, INSN_MACRO }, -+{"jr", "I", "s", MATCH_JALR, MASK_JALR | MASK_RD | MASK_IMM, match_opcode, INSN_ALIAS|WR_xd|RD_xs1 }, -+{"jr", "I", "s,j", MATCH_JALR, MASK_JALR | MASK_RD, match_opcode, INSN_ALIAS|WR_xd|RD_xs1 }, -+{"jalr", "I", "s", MATCH_JALR | (LINK_REG << OP_SH_RD), MASK_JALR | MASK_RD | MASK_IMM, match_opcode, INSN_ALIAS|WR_xd|RD_xs1 }, -+{"jalr", "I", "s,j", MATCH_JALR | (LINK_REG << OP_SH_RD), MASK_JALR | MASK_RD, match_opcode, INSN_ALIAS|WR_xd|RD_xs1 }, -+{"jalr", "I", "d,s", MATCH_JALR, MASK_JALR | MASK_IMM, match_opcode, INSN_ALIAS|WR_xd|RD_xs1 }, -+{"jalr", "I", "d,s,j", MATCH_JALR, MASK_JALR, match_opcode, WR_xd|RD_xs1 }, -+{"lb", "I", "d,o(s)", MATCH_LB, MASK_LB, match_opcode, WR_xd|RD_xs1 }, -+{"lb", "I", "d,A", 0, (int) M_LB, match_never, INSN_MACRO }, -+{"lbu", "I", "d,o(s)", MATCH_LBU, MASK_LBU, match_opcode, WR_xd|RD_xs1 }, -+{"lbu", "I", "d,A", 0, (int) M_LBU, match_never, INSN_MACRO }, -+{"lh", "I", "d,o(s)", MATCH_LH, MASK_LH, match_opcode, WR_xd|RD_xs1 }, -+{"lh", "I", "d,A", 0, (int) M_LH, match_never, INSN_MACRO }, -+{"lhu", "I", "d,o(s)", MATCH_LHU, MASK_LHU, match_opcode, WR_xd|RD_xs1 }, -+{"lhu", "I", "d,A", 0, (int) M_LHU, match_never, INSN_MACRO }, -+{"lw", "I", "d,o(s)", MATCH_LW, MASK_LW, match_opcode, WR_xd|RD_xs1 }, -+{"lw", "I", "d,A", 0, (int) M_LW, match_never, INSN_MACRO }, -+{"lui", "I", "d,u", MATCH_LUI, MASK_LUI, match_opcode, WR_xd }, -+{"not", "I", "d,s", MATCH_XORI | MASK_IMM, MASK_XORI | MASK_IMM, match_opcode, INSN_ALIAS|WR_xd|RD_xs1 }, -+{"ori", "I", "d,s,j", MATCH_ORI, MASK_ORI, match_opcode, WR_xd|RD_xs1 }, -+{"or", "I", "d,s,t", MATCH_OR, MASK_OR, match_opcode, WR_xd|RD_xs1|RD_xs2 }, -+{"or", "I", "d,s,j", MATCH_ORI, MASK_ORI, match_opcode, INSN_ALIAS|WR_xd|RD_xs1 }, -+{"auipc", "I", "d,u", MATCH_AUIPC, MASK_AUIPC, match_opcode, WR_xd }, -+{"seqz", "I", "d,s", MATCH_SLTIU | ENCODE_ITYPE_IMM(1), MASK_SLTIU | MASK_IMM, match_opcode, INSN_ALIAS|WR_xd|RD_xs1 }, -+{"snez", "I", "d,t", MATCH_SLTU, MASK_SLTU | MASK_RS1, match_opcode, INSN_ALIAS|WR_xd|RD_xs2 }, -+{"sltz", "I", "d,s", MATCH_SLT, MASK_SLT | MASK_RS2, match_opcode, INSN_ALIAS|WR_xd|RD_xs1 }, -+{"sgtz", "I", "d,t", MATCH_SLT, MASK_SLT | MASK_RS1, match_opcode, INSN_ALIAS|WR_xd|RD_xs2 }, -+{"slti", "I", "d,s,j", MATCH_SLTI, MASK_SLTI, match_opcode, INSN_ALIAS|WR_xd|RD_xs1 }, -+{"slt", "I", "d,s,t", MATCH_SLT, MASK_SLT, match_opcode, WR_xd|RD_xs1|RD_xs2 }, -+{"slt", "I", "d,s,j", MATCH_SLTI, MASK_SLTI, match_opcode, WR_xd|RD_xs1 }, -+{"sltiu", "I", "d,s,j", MATCH_SLTIU, MASK_SLTIU, match_opcode, WR_xd|RD_xs1 }, -+{"sltu", "I", "d,s,t", MATCH_SLTU, MASK_SLTU, match_opcode, WR_xd|RD_xs1|RD_xs2 }, -+{"sltu", "I", "d,s,j", MATCH_SLTIU, MASK_SLTIU, match_opcode, INSN_ALIAS|WR_xd|RD_xs1 }, -+{"sgt", "I", "d,t,s", MATCH_SLT, MASK_SLT, match_opcode, INSN_ALIAS|WR_xd|RD_xs1|RD_xs2 }, -+{"sgtu", "I", "d,t,s", MATCH_SLTU, MASK_SLTU, match_opcode, INSN_ALIAS|WR_xd|RD_xs1|RD_xs2 }, -+{"sb", "I", "t,q(s)", MATCH_SB, MASK_SB, match_opcode, RD_xs1|RD_xs2 }, -+{"sb", "I", "t,A,s", 0, (int) M_SB, match_never, INSN_MACRO }, -+{"sh", "I", "t,q(s)", MATCH_SH, MASK_SH, match_opcode, RD_xs1|RD_xs2 }, -+{"sh", "I", "t,A,s", 0, (int) M_SH, match_never, INSN_MACRO }, -+{"sw", "I", "t,q(s)", MATCH_SW, MASK_SW, match_opcode, RD_xs1|RD_xs2 }, -+{"sw", "I", "t,A,s", 0, (int) M_SW, match_never, INSN_MACRO }, -+{"fence", "I", "", MATCH_FENCE | MASK_PRED | MASK_SUCC, MASK_FENCE | MASK_RD | MASK_RS1 | MASK_IMM, match_opcode, INSN_ALIAS }, -+{"fence", "I", "P,Q", MATCH_FENCE, MASK_FENCE | MASK_RD | MASK_RS1 | (MASK_IMM & ~MASK_PRED & ~MASK_SUCC), match_opcode, 0 }, -+{"fence.i", "I", "", MATCH_FENCE_I, MASK_FENCE | MASK_RD | MASK_RS1 | MASK_IMM, match_opcode, 0 }, -+{"rdcycle", "I", "d", MATCH_RDCYCLE, MASK_RDCYCLE, match_opcode, WR_xd }, -+{"rdinstret", "I", "d", MATCH_RDINSTRET, MASK_RDINSTRET, match_opcode, WR_xd }, -+{"rdtime", "I", "d", MATCH_RDTIME, MASK_RDTIME, match_opcode, WR_xd }, -+{"rdcycleh", "32I", "d", MATCH_RDCYCLEH, MASK_RDCYCLEH, match_opcode, WR_xd }, -+{"rdinstreth","32I", "d", MATCH_RDINSTRETH, MASK_RDINSTRETH, match_opcode, WR_xd }, -+{"rdtimeh", "32I", "d", MATCH_RDTIMEH, MASK_RDTIMEH, match_opcode, WR_xd }, -+{"sbreak", "I", "", MATCH_SBREAK, MASK_SBREAK, match_opcode, 0 }, -+{"scall", "I", "", MATCH_SCALL, MASK_SCALL, match_opcode, 0 }, -+{"xori", "I", "d,s,j", MATCH_XORI, MASK_XORI, match_opcode, WR_xd|RD_xs1 }, -+{"xor", "I", "d,s,t", MATCH_XOR, MASK_XOR, match_opcode, WR_xd|RD_xs1|RD_xs2 }, -+{"xor", "I", "d,s,j", MATCH_XORI, MASK_XORI, match_opcode, INSN_ALIAS|WR_xd|RD_xs1 }, -+{"lwu", "64I", "d,o(s)", MATCH_LWU, MASK_LWU, match_opcode, WR_xd|RD_xs1 }, -+{"lwu", "64I", "d,A", 0, (int) M_LWU, match_never, INSN_MACRO }, -+{"ld", "64I", "d,o(s)", MATCH_LD, MASK_LD, match_opcode, WR_xd|RD_xs1 }, -+{"ld", "64I", "d,A", 0, (int) M_LD, match_never, INSN_MACRO }, -+{"sd", "64I", "t,q(s)", MATCH_SD, MASK_SD, match_opcode, RD_xs1|RD_xs2 }, -+{"sd", "64I", "t,A,s", 0, (int) M_SD, match_never, INSN_MACRO }, -+{"sext.w", "64I", "d,s", MATCH_ADDIW, MASK_ADDIW | MASK_IMM, match_opcode, INSN_ALIAS|WR_xd|RD_xs1 }, -+{"addiw", "64I", "d,s,j", MATCH_ADDIW, MASK_ADDIW, match_opcode, WR_xd|RD_xs1 }, -+{"addw", "64I", "d,s,t", MATCH_ADDW, MASK_ADDW, match_opcode, WR_xd|RD_xs1|RD_xs2 }, -+{"addw", "64I", "d,s,j", MATCH_ADDIW, MASK_ADDIW, match_opcode, INSN_ALIAS|WR_xd|RD_xs1 }, -+{"negw", "64I", "d,t", MATCH_SUBW, MASK_SUBW | MASK_RS1, match_opcode, INSN_ALIAS|WR_xd|RD_xs2 }, /* sub 0 */ -+{"slliw", "64I", "d,s,<", MATCH_SLLIW, MASK_SLLIW, match_opcode, WR_xd|RD_xs1 }, -+{"sllw", "64I", "d,s,t", MATCH_SLLW, MASK_SLLW, match_opcode, WR_xd|RD_xs1|RD_xs2 }, -+{"sllw", "64I", "d,s,<", MATCH_SLLIW, MASK_SLLIW, match_opcode, INSN_ALIAS|WR_xd|RD_xs1 }, -+{"srliw", "64I", "d,s,<", MATCH_SRLIW, MASK_SRLIW, match_opcode, WR_xd|RD_xs1 }, -+{"srlw", "64I", "d,s,t", MATCH_SRLW, MASK_SRLW, match_opcode, WR_xd|RD_xs1|RD_xs2 }, -+{"srlw", "64I", "d,s,<", MATCH_SRLIW, MASK_SRLIW, match_opcode, INSN_ALIAS|WR_xd|RD_xs1 }, -+{"sraiw", "64I", "d,s,<", MATCH_SRAIW, MASK_SRAIW, match_opcode, WR_xd|RD_xs1 }, -+{"sraw", "64I", "d,s,t", MATCH_SRAW, MASK_SRAW, match_opcode, WR_xd|RD_xs1|RD_xs2 }, -+{"sraw", "64I", "d,s,<", MATCH_SRAIW, MASK_SRAIW, match_opcode, INSN_ALIAS|WR_xd|RD_xs1 }, -+{"subw", "64I", "d,s,t", MATCH_SUBW, MASK_SUBW, match_opcode, WR_xd|RD_xs1|RD_xs2 }, -+ -+/* Atomic memory operation instruction subset */ -+{"lr.w", "A", "d,0(s)", MATCH_LR_W, MASK_LR_W | MASK_AQRL, match_opcode, WR_xd|RD_xs1 }, -+{"sc.w", "A", "d,t,0(s)", MATCH_SC_W, MASK_SC_W | MASK_AQRL, match_opcode, WR_xd|RD_xs1|RD_xs2 }, -+{"amoadd.w", "A", "d,t,0(s)", MATCH_AMOADD_W, MASK_AMOADD_W | MASK_AQRL, match_opcode, WR_xd|RD_xs1|RD_xs2 }, -+{"amoswap.w", "A", "d,t,0(s)", MATCH_AMOSWAP_W, MASK_AMOSWAP_W | MASK_AQRL, match_opcode, WR_xd|RD_xs1|RD_xs2 }, -+{"amoand.w", "A", "d,t,0(s)", MATCH_AMOAND_W, MASK_AMOAND_W | MASK_AQRL, match_opcode, WR_xd|RD_xs1|RD_xs2 }, -+{"amoor.w", "A", "d,t,0(s)", MATCH_AMOOR_W, MASK_AMOOR_W | MASK_AQRL, match_opcode, WR_xd|RD_xs1|RD_xs2 }, -+{"amoxor.w", "A", "d,t,0(s)", MATCH_AMOXOR_W, MASK_AMOXOR_W | MASK_AQRL, match_opcode, WR_xd|RD_xs1|RD_xs2 }, -+{"amomax.w", "A", "d,t,0(s)", MATCH_AMOMAX_W, MASK_AMOMAX_W | MASK_AQRL, match_opcode, WR_xd|RD_xs1|RD_xs2 }, -+{"amomaxu.w", "A", "d,t,0(s)", MATCH_AMOMAXU_W, MASK_AMOMAXU_W | MASK_AQRL, match_opcode, WR_xd|RD_xs1|RD_xs2 }, -+{"amomin.w", "A", "d,t,0(s)", MATCH_AMOMIN_W, MASK_AMOMIN_W | MASK_AQRL, match_opcode, WR_xd|RD_xs1|RD_xs2 }, -+{"amominu.w", "A", "d,t,0(s)", MATCH_AMOMINU_W, MASK_AMOMINU_W | MASK_AQRL, match_opcode, WR_xd|RD_xs1|RD_xs2 }, -+{"lr.w.aq", "A", "d,0(s)", MATCH_LR_W | MASK_AQ, MASK_LR_W | MASK_AQRL, match_opcode, WR_xd|RD_xs1 }, -+{"sc.w.aq", "A", "d,t,0(s)", MATCH_SC_W | MASK_AQ, MASK_SC_W | MASK_AQRL, match_opcode, WR_xd|RD_xs1|RD_xs2 }, -+{"amoadd.w.aq", "A", "d,t,0(s)", MATCH_AMOADD_W | MASK_AQ, MASK_AMOADD_W | MASK_AQRL, match_opcode, WR_xd|RD_xs1|RD_xs2 }, -+{"amoswap.w.aq", "A", "d,t,0(s)", MATCH_AMOSWAP_W | MASK_AQ, MASK_AMOSWAP_W | MASK_AQRL, match_opcode, WR_xd|RD_xs1|RD_xs2 }, -+{"amoand.w.aq", "A", "d,t,0(s)", MATCH_AMOAND_W | MASK_AQ, MASK_AMOAND_W | MASK_AQRL, match_opcode, WR_xd|RD_xs1|RD_xs2 }, -+{"amoor.w.aq", "A", "d,t,0(s)", MATCH_AMOOR_W | MASK_AQ, MASK_AMOOR_W | MASK_AQRL, match_opcode, WR_xd|RD_xs1|RD_xs2 }, -+{"amoxor.w.aq", "A", "d,t,0(s)", MATCH_AMOXOR_W | MASK_AQ, MASK_AMOXOR_W | MASK_AQRL, match_opcode, WR_xd|RD_xs1|RD_xs2 }, -+{"amomax.w.aq", "A", "d,t,0(s)", MATCH_AMOMAX_W | MASK_AQ, MASK_AMOMAX_W | MASK_AQRL, match_opcode, WR_xd|RD_xs1|RD_xs2 }, -+{"amomaxu.w.aq", "A", "d,t,0(s)", MATCH_AMOMAXU_W | MASK_AQ, MASK_AMOMAXU_W | MASK_AQRL, match_opcode, WR_xd|RD_xs1|RD_xs2 }, -+{"amomin.w.aq", "A", "d,t,0(s)", MATCH_AMOMIN_W | MASK_AQ, MASK_AMOMIN_W | MASK_AQRL, match_opcode, WR_xd|RD_xs1|RD_xs2 }, -+{"amominu.w.aq", "A", "d,t,0(s)", MATCH_AMOMINU_W | MASK_AQ, MASK_AMOMINU_W | MASK_AQRL, match_opcode, WR_xd|RD_xs1|RD_xs2 }, -+{"lr.w.rl", "A", "d,0(s)", MATCH_LR_W | MASK_RL, MASK_LR_W | MASK_AQRL, match_opcode, WR_xd|RD_xs1 }, -+{"sc.w.rl", "A", "d,t,0(s)", MATCH_SC_W | MASK_RL, MASK_SC_W | MASK_AQRL, match_opcode, WR_xd|RD_xs1|RD_xs2 }, -+{"amoadd.w.rl", "A", "d,t,0(s)", MATCH_AMOADD_W | MASK_RL, MASK_AMOADD_W | MASK_AQRL, match_opcode, WR_xd|RD_xs1|RD_xs2 }, -+{"amoswap.w.rl", "A", "d,t,0(s)", MATCH_AMOSWAP_W | MASK_RL, MASK_AMOSWAP_W | MASK_AQRL, match_opcode, WR_xd|RD_xs1|RD_xs2 }, -+{"amoand.w.rl", "A", "d,t,0(s)", MATCH_AMOAND_W | MASK_RL, MASK_AMOAND_W | MASK_AQRL, match_opcode, WR_xd|RD_xs1|RD_xs2 }, -+{"amoor.w.rl", "A", "d,t,0(s)", MATCH_AMOOR_W | MASK_RL, MASK_AMOOR_W | MASK_AQRL, match_opcode, WR_xd|RD_xs1|RD_xs2 }, -+{"amoxor.w.rl", "A", "d,t,0(s)", MATCH_AMOXOR_W | MASK_RL, MASK_AMOXOR_W | MASK_AQRL, match_opcode, WR_xd|RD_xs1|RD_xs2 }, -+{"amomax.w.rl", "A", "d,t,0(s)", MATCH_AMOMAX_W | MASK_RL, MASK_AMOMAX_W | MASK_AQRL, match_opcode, WR_xd|RD_xs1|RD_xs2 }, -+{"amomaxu.w.rl", "A", "d,t,0(s)", MATCH_AMOMAXU_W | MASK_RL, MASK_AMOMAXU_W | MASK_AQRL, match_opcode, WR_xd|RD_xs1|RD_xs2 }, -+{"amomin.w.rl", "A", "d,t,0(s)", MATCH_AMOMIN_W | MASK_RL, MASK_AMOMIN_W | MASK_AQRL, match_opcode, WR_xd|RD_xs1|RD_xs2 }, -+{"amominu.w.rl", "A", "d,t,0(s)", MATCH_AMOMINU_W | MASK_RL, MASK_AMOMINU_W | MASK_AQRL, match_opcode, WR_xd|RD_xs1|RD_xs2 }, -+{"lr.w.sc", "A", "d,0(s)", MATCH_LR_W | MASK_AQRL, MASK_LR_W | MASK_AQRL, match_opcode, WR_xd|RD_xs1 }, -+{"sc.w.sc", "A", "d,t,0(s)", MATCH_SC_W | MASK_AQRL, MASK_SC_W | MASK_AQRL, match_opcode, WR_xd|RD_xs1|RD_xs2 }, -+{"amoadd.w.sc", "A", "d,t,0(s)", MATCH_AMOADD_W | MASK_AQRL, MASK_AMOADD_W | MASK_AQRL, match_opcode, WR_xd|RD_xs1|RD_xs2 }, -+{"amoswap.w.sc", "A", "d,t,0(s)", MATCH_AMOSWAP_W | MASK_AQRL, MASK_AMOSWAP_W | MASK_AQRL, match_opcode, WR_xd|RD_xs1|RD_xs2 }, -+{"amoand.w.sc", "A", "d,t,0(s)", MATCH_AMOAND_W | MASK_AQRL, MASK_AMOAND_W | MASK_AQRL, match_opcode, WR_xd|RD_xs1|RD_xs2 }, -+{"amoor.w.sc", "A", "d,t,0(s)", MATCH_AMOOR_W | MASK_AQRL, MASK_AMOOR_W | MASK_AQRL, match_opcode, WR_xd|RD_xs1|RD_xs2 }, -+{"amoxor.w.sc", "A", "d,t,0(s)", MATCH_AMOXOR_W | MASK_AQRL, MASK_AMOXOR_W | MASK_AQRL, match_opcode, WR_xd|RD_xs1|RD_xs2 }, -+{"amomax.w.sc", "A", "d,t,0(s)", MATCH_AMOMAX_W | MASK_AQRL, MASK_AMOMAX_W | MASK_AQRL, match_opcode, WR_xd|RD_xs1|RD_xs2 }, -+{"amomaxu.w.sc", "A", "d,t,0(s)", MATCH_AMOMAXU_W | MASK_AQRL, MASK_AMOMAXU_W | MASK_AQRL, match_opcode, WR_xd|RD_xs1|RD_xs2 }, -+{"amomin.w.sc", "A", "d,t,0(s)", MATCH_AMOMIN_W | MASK_AQRL, MASK_AMOMIN_W | MASK_AQRL, match_opcode, WR_xd|RD_xs1|RD_xs2 }, -+{"amominu.w.sc", "A", "d,t,0(s)", MATCH_AMOMINU_W | MASK_AQRL, MASK_AMOMINU_W | MASK_AQRL, match_opcode, WR_xd|RD_xs1|RD_xs2 }, -+{"lr.d", "64A", "d,0(s)", MATCH_LR_D, MASK_LR_D | MASK_AQRL, match_opcode, WR_xd|RD_xs1 }, -+{"sc.d", "64A", "d,t,0(s)", MATCH_SC_D, MASK_SC_D | MASK_AQRL, match_opcode, WR_xd|RD_xs1|RD_xs2 }, -+{"amoadd.d", "64A", "d,t,0(s)", MATCH_AMOADD_D, MASK_AMOADD_D | MASK_AQRL, match_opcode, WR_xd|RD_xs1|RD_xs2 }, -+{"amoswap.d", "64A", "d,t,0(s)", MATCH_AMOSWAP_D, MASK_AMOSWAP_D | MASK_AQRL, match_opcode, WR_xd|RD_xs1|RD_xs2 }, -+{"amoand.d", "64A", "d,t,0(s)", MATCH_AMOAND_D, MASK_AMOAND_D | MASK_AQRL, match_opcode, WR_xd|RD_xs1|RD_xs2 }, -+{"amoor.d", "64A", "d,t,0(s)", MATCH_AMOOR_D, MASK_AMOOR_D | MASK_AQRL, match_opcode, WR_xd|RD_xs1|RD_xs2 }, -+{"amoxor.d", "64A", "d,t,0(s)", MATCH_AMOXOR_D, MASK_AMOXOR_D | MASK_AQRL, match_opcode, WR_xd|RD_xs1|RD_xs2 }, -+{"amomax.d", "64A", "d,t,0(s)", MATCH_AMOMAX_D, MASK_AMOMAX_D | MASK_AQRL, match_opcode, WR_xd|RD_xs1|RD_xs2 }, -+{"amomaxu.d", "64A", "d,t,0(s)", MATCH_AMOMAXU_D, MASK_AMOMAXU_D | MASK_AQRL, match_opcode, WR_xd|RD_xs1|RD_xs2 }, -+{"amomin.d", "64A", "d,t,0(s)", MATCH_AMOMIN_D, MASK_AMOMIN_D | MASK_AQRL, match_opcode, WR_xd|RD_xs1|RD_xs2 }, -+{"amominu.d", "64A", "d,t,0(s)", MATCH_AMOMINU_D, MASK_AMOMINU_D | MASK_AQRL, match_opcode, WR_xd|RD_xs1|RD_xs2 }, -+{"lr.d.aq", "64A", "d,0(s)", MATCH_LR_D | MASK_AQ, MASK_LR_D | MASK_AQRL, match_opcode, WR_xd|RD_xs1 }, -+{"sc.d.aq", "64A", "d,t,0(s)", MATCH_SC_D | MASK_AQ, MASK_SC_D | MASK_AQRL, match_opcode, WR_xd|RD_xs1|RD_xs2 }, -+{"amoadd.d.aq", "64A", "d,t,0(s)", MATCH_AMOADD_D | MASK_AQ, MASK_AMOADD_D | MASK_AQRL, match_opcode, WR_xd|RD_xs1|RD_xs2 }, -+{"amoswap.d.aq", "64A", "d,t,0(s)", MATCH_AMOSWAP_D | MASK_AQ, MASK_AMOSWAP_D | MASK_AQRL, match_opcode, WR_xd|RD_xs1|RD_xs2 }, -+{"amoand.d.aq", "64A", "d,t,0(s)", MATCH_AMOAND_D | MASK_AQ, MASK_AMOAND_D | MASK_AQRL, match_opcode, WR_xd|RD_xs1|RD_xs2 }, -+{"amoor.d.aq", "64A", "d,t,0(s)", MATCH_AMOOR_D | MASK_AQ, MASK_AMOOR_D | MASK_AQRL, match_opcode, WR_xd|RD_xs1|RD_xs2 }, -+{"amoxor.d.aq", "64A", "d,t,0(s)", MATCH_AMOXOR_D | MASK_AQ, MASK_AMOXOR_D | MASK_AQRL, match_opcode, WR_xd|RD_xs1|RD_xs2 }, -+{"amomax.d.aq", "64A", "d,t,0(s)", MATCH_AMOMAX_D | MASK_AQ, MASK_AMOMAX_D | MASK_AQRL, match_opcode, WR_xd|RD_xs1|RD_xs2 }, -+{"amomaxu.d.aq", "64A", "d,t,0(s)", MATCH_AMOMAXU_D | MASK_AQ, MASK_AMOMAXU_D | MASK_AQRL, match_opcode, WR_xd|RD_xs1|RD_xs2 }, -+{"amomin.d.aq", "64A", "d,t,0(s)", MATCH_AMOMIN_D | MASK_AQ, MASK_AMOMIN_D | MASK_AQRL, match_opcode, WR_xd|RD_xs1|RD_xs2 }, -+{"amominu.d.aq", "64A", "d,t,0(s)", MATCH_AMOMINU_D | MASK_AQ, MASK_AMOMINU_D | MASK_AQRL, match_opcode, WR_xd|RD_xs1|RD_xs2 }, -+{"lr.d.rl", "64A", "d,0(s)", MATCH_LR_D | MASK_RL, MASK_LR_D | MASK_AQRL, match_opcode, WR_xd|RD_xs1 }, -+{"sc.d.rl", "64A", "d,t,0(s)", MATCH_SC_D | MASK_RL, MASK_SC_D | MASK_AQRL, match_opcode, WR_xd|RD_xs1|RD_xs2 }, -+{"amoadd.d.rl", "64A", "d,t,0(s)", MATCH_AMOADD_D | MASK_RL, MASK_AMOADD_D | MASK_AQRL, match_opcode, WR_xd|RD_xs1|RD_xs2 }, -+{"amoswap.d.rl", "64A", "d,t,0(s)", MATCH_AMOSWAP_D | MASK_RL, MASK_AMOSWAP_D | MASK_AQRL, match_opcode, WR_xd|RD_xs1|RD_xs2 }, -+{"amoand.d.rl", "64A", "d,t,0(s)", MATCH_AMOAND_D | MASK_RL, MASK_AMOAND_D | MASK_AQRL, match_opcode, WR_xd|RD_xs1|RD_xs2 }, -+{"amoor.d.rl", "64A", "d,t,0(s)", MATCH_AMOOR_D | MASK_RL, MASK_AMOOR_D | MASK_AQRL, match_opcode, WR_xd|RD_xs1|RD_xs2 }, -+{"amoxor.d.rl", "64A", "d,t,0(s)", MATCH_AMOXOR_D | MASK_RL, MASK_AMOXOR_D | MASK_AQRL, match_opcode, WR_xd|RD_xs1|RD_xs2 }, -+{"amomax.d.rl", "64A", "d,t,0(s)", MATCH_AMOMAX_D | MASK_RL, MASK_AMOMAX_D | MASK_AQRL, match_opcode, WR_xd|RD_xs1|RD_xs2 }, -+{"amomaxu.d.rl", "64A", "d,t,0(s)", MATCH_AMOMAXU_D | MASK_RL, MASK_AMOMAXU_D | MASK_AQRL, match_opcode, WR_xd|RD_xs1|RD_xs2 }, -+{"amomin.d.rl", "64A", "d,t,0(s)", MATCH_AMOMIN_D | MASK_RL, MASK_AMOMIN_D | MASK_AQRL, match_opcode, WR_xd|RD_xs1|RD_xs2 }, -+{"amominu.d.rl", "64A", "d,t,0(s)", MATCH_AMOMINU_D | MASK_RL, MASK_AMOMINU_D | MASK_AQRL, match_opcode, WR_xd|RD_xs1|RD_xs2 }, -+{"lr.d.sc", "64A", "d,0(s)", MATCH_LR_D | MASK_AQRL, MASK_LR_D | MASK_AQRL, match_opcode, WR_xd|RD_xs1 }, -+{"sc.d.sc", "64A", "d,t,0(s)", MATCH_SC_D | MASK_AQRL, MASK_SC_D | MASK_AQRL, match_opcode, WR_xd|RD_xs1|RD_xs2 }, -+{"amoadd.d.sc", "64A", "d,t,0(s)", MATCH_AMOADD_D | MASK_AQRL, MASK_AMOADD_D | MASK_AQRL, match_opcode, WR_xd|RD_xs1|RD_xs2 }, -+{"amoswap.d.sc", "64A", "d,t,0(s)", MATCH_AMOSWAP_D | MASK_AQRL, MASK_AMOSWAP_D | MASK_AQRL, match_opcode, WR_xd|RD_xs1|RD_xs2 }, -+{"amoand.d.sc", "64A", "d,t,0(s)", MATCH_AMOAND_D | MASK_AQRL, MASK_AMOAND_D | MASK_AQRL, match_opcode, WR_xd|RD_xs1|RD_xs2 }, -+{"amoor.d.sc", "64A", "d,t,0(s)", MATCH_AMOOR_D | MASK_AQRL, MASK_AMOOR_D | MASK_AQRL, match_opcode, WR_xd|RD_xs1|RD_xs2 }, -+{"amoxor.d.sc", "64A", "d,t,0(s)", MATCH_AMOXOR_D | MASK_AQRL, MASK_AMOXOR_D | MASK_AQRL, match_opcode, WR_xd|RD_xs1|RD_xs2 }, -+{"amomax.d.sc", "64A", "d,t,0(s)", MATCH_AMOMAX_D | MASK_AQRL, MASK_AMOMAX_D | MASK_AQRL, match_opcode, WR_xd|RD_xs1|RD_xs2 }, -+{"amomaxu.d.sc", "64A", "d,t,0(s)", MATCH_AMOMAXU_D | MASK_AQRL, MASK_AMOMAXU_D | MASK_AQRL, match_opcode, WR_xd|RD_xs1|RD_xs2 }, -+{"amomin.d.sc", "64A", "d,t,0(s)", MATCH_AMOMIN_D | MASK_AQRL, MASK_AMOMIN_D | MASK_AQRL, match_opcode, WR_xd|RD_xs1|RD_xs2 }, -+{"amominu.d.sc", "64A", "d,t,0(s)", MATCH_AMOMINU_D | MASK_AQRL, MASK_AMOMINU_D | MASK_AQRL, match_opcode, WR_xd|RD_xs1|RD_xs2 }, -+ -+/* Multiply/Divide instruction subset */ -+{"mul", "M", "d,s,t", MATCH_MUL, MASK_MUL, match_opcode, WR_xd|RD_xs1|RD_xs2 }, -+{"mulh", "M", "d,s,t", MATCH_MULH, MASK_MULH, match_opcode, WR_xd|RD_xs1|RD_xs2 }, -+{"mulhu", "M", "d,s,t", MATCH_MULHU, MASK_MULHU, match_opcode, WR_xd|RD_xs1|RD_xs2 }, -+{"mulhsu", "M", "d,s,t", MATCH_MULHSU, MASK_MULHSU, match_opcode, WR_xd|RD_xs1|RD_xs2 }, -+{"div", "M", "d,s,t", MATCH_DIV, MASK_DIV, match_opcode, WR_xd|RD_xs1|RD_xs2 }, -+{"divu", "M", "d,s,t", MATCH_DIVU, MASK_DIVU, match_opcode, WR_xd|RD_xs1|RD_xs2 }, -+{"rem", "M", "d,s,t", MATCH_REM, MASK_REM, match_opcode, WR_xd|RD_xs1|RD_xs2 }, -+{"remu", "M", "d,s,t", MATCH_REMU, MASK_REMU, match_opcode, WR_xd|RD_xs1|RD_xs2 }, -+{"mulw", "64M", "d,s,t", MATCH_MULW, MASK_MULW, match_opcode, WR_xd|RD_xs1|RD_xs2 }, -+{"divw", "64M", "d,s,t", MATCH_DIVW, MASK_DIVW, match_opcode, WR_xd|RD_xs1|RD_xs2 }, -+{"divuw", "64M", "d,s,t", MATCH_DIVUW, MASK_DIVUW, match_opcode, WR_xd|RD_xs1|RD_xs2 }, -+{"remw", "64M", "d,s,t", MATCH_REMW, MASK_REMW, match_opcode, WR_xd|RD_xs1|RD_xs2 }, -+{"remuw", "64M", "d,s,t", MATCH_REMUW, MASK_REMUW, match_opcode, WR_xd|RD_xs1|RD_xs2 }, -+ -+/* Single-precision floating-point instruction subset */ -+{"frsr", "F", "d", MATCH_FRCSR, MASK_FRCSR, match_opcode, WR_xd }, -+{"fssr", "F", "s", MATCH_FSCSR, MASK_FSCSR | MASK_RD, match_opcode, RD_xs1 }, -+{"fssr", "F", "d,s", MATCH_FSCSR, MASK_FSCSR, match_opcode, WR_xd|RD_xs1 }, -+{"frcsr", "F", "d", MATCH_FRCSR, MASK_FRCSR, match_opcode, WR_xd }, -+{"fscsr", "F", "s", MATCH_FSCSR, MASK_FSCSR | MASK_RD, match_opcode, RD_xs1 }, -+{"fscsr", "F", "d,s", MATCH_FSCSR, MASK_FSCSR, match_opcode, WR_xd|RD_xs1 }, -+{"frrm", "F", "d", MATCH_FRRM, MASK_FRRM, match_opcode, WR_xd }, -+{"fsrm", "F", "s", MATCH_FSRM, MASK_FSRM | MASK_RD, match_opcode, RD_xs1 }, -+{"fsrm", "F", "d,s", MATCH_FSRM, MASK_FSRM, match_opcode, WR_xd|RD_xs1 }, -+{"frflags", "F", "d", MATCH_FRFLAGS, MASK_FRFLAGS, match_opcode, WR_xd }, -+{"fsflags", "F", "s", MATCH_FSFLAGS, MASK_FSFLAGS | MASK_RD, match_opcode, RD_xs1 }, -+{"fsflags", "F", "d,s", MATCH_FSFLAGS, MASK_FSFLAGS, match_opcode, WR_xd|RD_xs1 }, -+{"flw", "F", "D,o(s)", MATCH_FLW, MASK_FLW, match_opcode, WR_fd|RD_xs1 }, -+{"flw", "F", "D,A,s", 0, (int) M_FLW, match_never, INSN_MACRO }, -+{"fsw", "F", "T,q(s)", MATCH_FSW, MASK_FSW, match_opcode, RD_xs1|RD_fs2 }, -+{"fsw", "F", "T,A,s", 0, (int) M_FSW, match_never, INSN_MACRO }, -+{"fmv.x.s", "F", "d,S", MATCH_FMV_X_S, MASK_FMV_X_S, match_opcode, WR_xd|RD_fs1 }, -+{"fmv.s.x", "F", "D,s", MATCH_FMV_S_X, MASK_FMV_S_X, match_opcode, WR_fd|RD_xs1 }, -+{"fmv.s", "F", "D,U", MATCH_FSGNJ_S, MASK_FSGNJ_S, match_rs1_eq_rs2, INSN_ALIAS|WR_fd|RD_fs1|RD_fs2 }, -+{"fneg.s", "F", "D,U", MATCH_FSGNJN_S, MASK_FSGNJN_S, match_rs1_eq_rs2, INSN_ALIAS|WR_fd|RD_fs1|RD_fs2 }, -+{"fabs.s", "F", "D,U", MATCH_FSGNJX_S, MASK_FSGNJX_S, match_rs1_eq_rs2, INSN_ALIAS|WR_fd|RD_fs1|RD_fs2 }, -+{"fsgnj.s", "F", "D,S,T", MATCH_FSGNJ_S, MASK_FSGNJ_S, match_opcode, WR_fd|RD_fs1|RD_fs2 }, -+{"fsgnjn.s", "F", "D,S,T", MATCH_FSGNJN_S, MASK_FSGNJN_S, match_opcode, WR_fd|RD_fs1|RD_fs2 }, -+{"fsgnjx.s", "F", "D,S,T", MATCH_FSGNJX_S, MASK_FSGNJX_S, match_opcode, WR_fd|RD_fs1|RD_fs2 }, -+{"fadd.s", "F", "D,S,T", MATCH_FADD_S | MASK_RM, MASK_FADD_S | MASK_RM, match_opcode, WR_fd|RD_fs1|RD_fs2 }, -+{"fadd.s", "F", "D,S,T,m", MATCH_FADD_S, MASK_FADD_S, match_opcode, WR_fd|RD_fs1|RD_fs2 }, -+{"fsub.s", "F", "D,S,T", MATCH_FSUB_S | MASK_RM, MASK_FSUB_S | MASK_RM, match_opcode, WR_fd|RD_fs1|RD_fs2 }, -+{"fsub.s", "F", "D,S,T,m", MATCH_FSUB_S, MASK_FSUB_S, match_opcode, WR_fd|RD_fs1|RD_fs2 }, -+{"fmul.s", "F", "D,S,T", MATCH_FMUL_S | MASK_RM, MASK_FMUL_S | MASK_RM, match_opcode, WR_fd|RD_fs1|RD_fs2 }, -+{"fmul.s", "F", "D,S,T,m", MATCH_FMUL_S, MASK_FMUL_S, match_opcode, WR_fd|RD_fs1|RD_fs2 }, -+{"fdiv.s", "F", "D,S,T", MATCH_FDIV_S | MASK_RM, MASK_FDIV_S | MASK_RM, match_opcode, WR_fd|RD_fs1|RD_fs2 }, -+{"fdiv.s", "F", "D,S,T,m", MATCH_FDIV_S, MASK_FDIV_S, match_opcode, WR_fd|RD_fs1|RD_fs2 }, -+{"fsqrt.s", "F", "D,S", MATCH_FSQRT_S | MASK_RM, MASK_FSQRT_S | MASK_RM, match_opcode, WR_fd|RD_fs1 }, -+{"fsqrt.s", "F", "D,S,m", MATCH_FSQRT_S, MASK_FSQRT_S, match_opcode, WR_fd|RD_fs1 }, -+{"fmin.s", "F", "D,S,T", MATCH_FMIN_S, MASK_FMIN_S, match_opcode, WR_fd|RD_fs1|RD_fs2 }, -+{"fmax.s", "F", "D,S,T", MATCH_FMAX_S, MASK_FMAX_S, match_opcode, WR_fd|RD_fs1|RD_fs2 }, -+{"fmadd.s", "F", "D,S,T,R", MATCH_FMADD_S | MASK_RM, MASK_FMADD_S | MASK_RM, match_opcode, WR_fd|RD_fs1|RD_fs2|RD_fs3 }, -+{"fmadd.s", "F", "D,S,T,R,m", MATCH_FMADD_S, MASK_FMADD_S, match_opcode, WR_fd|RD_fs1|RD_fs2|RD_fs3 }, -+{"fnmadd.s", "F", "D,S,T,R", MATCH_FNMADD_S | MASK_RM, MASK_FNMADD_S | MASK_RM, match_opcode, WR_fd|RD_fs1|RD_fs2|RD_fs3 }, -+{"fnmadd.s", "F", "D,S,T,R,m", MATCH_FNMADD_S, MASK_FNMADD_S, match_opcode, WR_fd|RD_fs1|RD_fs2|RD_fs3 }, -+{"fmsub.s", "F", "D,S,T,R", MATCH_FMSUB_S | MASK_RM, MASK_FMSUB_S | MASK_RM, match_opcode, WR_fd|RD_fs1|RD_fs2|RD_fs3 }, -+{"fmsub.s", "F", "D,S,T,R,m", MATCH_FMSUB_S, MASK_FMSUB_S, match_opcode, WR_fd|RD_fs1|RD_fs2|RD_fs3 }, -+{"fnmsub.s", "F", "D,S,T,R", MATCH_FNMSUB_S | MASK_RM, MASK_FNMSUB_S | MASK_RM, match_opcode, WR_fd|RD_fs1|RD_fs2|RD_fs3 }, -+{"fnmsub.s", "F", "D,S,T,R,m", MATCH_FNMSUB_S, MASK_FNMSUB_S, match_opcode, WR_fd|RD_fs1|RD_fs2|RD_fs3 }, -+{"fcvt.w.s", "F", "d,S", MATCH_FCVT_W_S | MASK_RM, MASK_FCVT_W_S | MASK_RM, match_opcode, WR_xd|RD_fs1 }, -+{"fcvt.w.s", "F", "d,S,m", MATCH_FCVT_W_S, MASK_FCVT_W_S, match_opcode, WR_xd|RD_fs1 }, -+{"fcvt.wu.s", "F", "d,S", MATCH_FCVT_WU_S | MASK_RM, MASK_FCVT_WU_S | MASK_RM, match_opcode, WR_xd|RD_fs1 }, -+{"fcvt.wu.s", "F", "d,S,m", MATCH_FCVT_WU_S, MASK_FCVT_WU_S, match_opcode, WR_xd|RD_fs1 }, -+{"fcvt.s.w", "F", "D,s", MATCH_FCVT_S_W | MASK_RM, MASK_FCVT_S_W | MASK_RM, match_opcode, WR_fd|RD_xs1 }, -+{"fcvt.s.w", "F", "D,s,m", MATCH_FCVT_S_W, MASK_FCVT_S_W, match_opcode, WR_fd|RD_xs1 }, -+{"fcvt.s.wu", "F", "D,s", MATCH_FCVT_S_WU | MASK_RM, MASK_FCVT_S_W | MASK_RM, match_opcode, WR_fd|RD_xs1 }, -+{"fcvt.s.wu", "F", "D,s,m", MATCH_FCVT_S_WU, MASK_FCVT_S_WU, match_opcode, WR_fd|RD_xs1 }, -+{"fclass.s", "F", "d,S", MATCH_FCLASS_S, MASK_FCLASS_S, match_opcode, WR_xd|RD_fs1 }, -+{"feq.s", "F", "d,S,T", MATCH_FEQ_S, MASK_FEQ_S, match_opcode, WR_xd|RD_fs1|RD_fs2 }, -+{"flt.s", "F", "d,S,T", MATCH_FLT_S, MASK_FLT_S, match_opcode, WR_xd|RD_fs1|RD_fs2 }, -+{"fle.s", "F", "d,S,T", MATCH_FLE_S, MASK_FLE_S, match_opcode, WR_xd|RD_fs1|RD_fs2 }, -+{"fgt.s", "F", "d,T,S", MATCH_FLT_S, MASK_FLT_S, match_opcode, WR_xd|RD_fs1|RD_fs2 }, -+{"fge.s", "F", "d,T,S", MATCH_FLE_S, MASK_FLE_S, match_opcode, WR_xd|RD_fs1|RD_fs2 }, -+{"fcvt.l.s", "64F", "d,S", MATCH_FCVT_L_S | MASK_RM, MASK_FCVT_L_S | MASK_RM, match_opcode, WR_xd|RD_fs1 }, -+{"fcvt.l.s", "64F", "d,S,m", MATCH_FCVT_L_S, MASK_FCVT_L_S, match_opcode, WR_xd|RD_fs1 }, -+{"fcvt.lu.s", "64F", "d,S", MATCH_FCVT_LU_S | MASK_RM, MASK_FCVT_LU_S | MASK_RM, match_opcode, WR_xd|RD_fs1 }, -+{"fcvt.lu.s", "64F", "d,S,m", MATCH_FCVT_LU_S, MASK_FCVT_LU_S, match_opcode, WR_xd|RD_fs1 }, -+{"fcvt.s.l", "64F", "D,s", MATCH_FCVT_S_L | MASK_RM, MASK_FCVT_S_L | MASK_RM, match_opcode, WR_fd|RD_xs1 }, -+{"fcvt.s.l", "64F", "D,s,m", MATCH_FCVT_S_L, MASK_FCVT_S_L, match_opcode, WR_fd|RD_xs1 }, -+{"fcvt.s.lu", "64F", "D,s", MATCH_FCVT_S_LU | MASK_RM, MASK_FCVT_S_L | MASK_RM, match_opcode, WR_fd|RD_xs1 }, -+{"fcvt.s.lu", "64F", "D,s,m", MATCH_FCVT_S_LU, MASK_FCVT_S_LU, match_opcode, WR_fd|RD_xs1 }, -+ -+/* Double-precision floating-point instruction subset */ -+{"fld", "D", "D,o(s)", MATCH_FLD, MASK_FLD, match_opcode, WR_fd|RD_xs1 }, -+{"fld", "D", "D,A,s", 0, (int) M_FLD, match_never, INSN_MACRO }, -+{"fsd", "D", "T,q(s)", MATCH_FSD, MASK_FSD, match_opcode, RD_xs1|RD_fs2 }, -+{"fsd", "D", "T,A,s", 0, (int) M_FSD, match_never, INSN_MACRO }, -+{"fmv.d", "D", "D,U", MATCH_FSGNJ_D, MASK_FSGNJ_D, match_rs1_eq_rs2, INSN_ALIAS|WR_fd|RD_fs1|RD_fs2 }, -+{"fneg.d", "D", "D,U", MATCH_FSGNJN_D, MASK_FSGNJN_D, match_rs1_eq_rs2, INSN_ALIAS|WR_fd|RD_fs1|RD_fs2 }, -+{"fabs.d", "D", "D,U", MATCH_FSGNJX_D, MASK_FSGNJX_D, match_rs1_eq_rs2, INSN_ALIAS|WR_fd|RD_fs1|RD_fs2 }, -+{"fsgnj.d", "D", "D,S,T", MATCH_FSGNJ_D, MASK_FSGNJ_D, match_opcode, WR_fd|RD_fs1|RD_fs2 }, -+{"fsgnjn.d", "D", "D,S,T", MATCH_FSGNJN_D, MASK_FSGNJN_D, match_opcode, WR_fd|RD_fs1|RD_fs2 }, -+{"fsgnjx.d", "D", "D,S,T", MATCH_FSGNJX_D, MASK_FSGNJX_D, match_opcode, WR_fd|RD_fs1|RD_fs2 }, -+{"fadd.d", "D", "D,S,T", MATCH_FADD_D | MASK_RM, MASK_FADD_D | MASK_RM, match_opcode, WR_fd|RD_fs1|RD_fs2 }, -+{"fadd.d", "D", "D,S,T,m", MATCH_FADD_D, MASK_FADD_D, match_opcode, WR_fd|RD_fs1|RD_fs2 }, -+{"fsub.d", "D", "D,S,T", MATCH_FSUB_D | MASK_RM, MASK_FSUB_D | MASK_RM, match_opcode, WR_fd|RD_fs1|RD_fs2 }, -+{"fsub.d", "D", "D,S,T,m", MATCH_FSUB_D, MASK_FSUB_D, match_opcode, WR_fd|RD_fs1|RD_fs2 }, -+{"fmul.d", "D", "D,S,T", MATCH_FMUL_D | MASK_RM, MASK_FMUL_D | MASK_RM, match_opcode, WR_fd|RD_fs1|RD_fs2 }, -+{"fmul.d", "D", "D,S,T,m", MATCH_FMUL_D, MASK_FMUL_D, match_opcode, WR_fd|RD_fs1|RD_fs2 }, -+{"fdiv.d", "D", "D,S,T", MATCH_FDIV_D | MASK_RM, MASK_FDIV_D | MASK_RM, match_opcode, WR_fd|RD_fs1|RD_fs2 }, -+{"fdiv.d", "D", "D,S,T,m", MATCH_FDIV_D, MASK_FDIV_D, match_opcode, WR_fd|RD_fs1|RD_fs2 }, -+{"fsqrt.d", "D", "D,S", MATCH_FSQRT_D | MASK_RM, MASK_FSQRT_D | MASK_RM, match_opcode, WR_fd|RD_fs1 }, -+{"fsqrt.d", "D", "D,S,m", MATCH_FSQRT_D, MASK_FSQRT_D, match_opcode, WR_fd|RD_fs1 }, -+{"fmin.d", "D", "D,S,T", MATCH_FMIN_D, MASK_FMIN_D, match_opcode, WR_fd|RD_fs1|RD_fs2 }, -+{"fmax.d", "D", "D,S,T", MATCH_FMAX_D, MASK_FMAX_D, match_opcode, WR_fd|RD_fs1|RD_fs2 }, -+{"fmadd.d", "D", "D,S,T,R", MATCH_FMADD_D | MASK_RM, MASK_FMADD_D | MASK_RM, match_opcode, WR_fd|RD_fs1|RD_fs2|RD_fs3 }, -+{"fmadd.d", "D", "D,S,T,R,m", MATCH_FMADD_D, MASK_FMADD_D, match_opcode, WR_fd|RD_fs1|RD_fs2|RD_fs3 }, -+{"fnmadd.d", "D", "D,S,T,R", MATCH_FNMADD_D | MASK_RM, MASK_FNMADD_D | MASK_RM, match_opcode, WR_fd|RD_fs1|RD_fs2|RD_fs3 }, -+{"fnmadd.d", "D", "D,S,T,R,m", MATCH_FNMADD_D, MASK_FNMADD_D, match_opcode, WR_fd|RD_fs1|RD_fs2|RD_fs3 }, -+{"fmsub.d", "D", "D,S,T,R", MATCH_FMSUB_D | MASK_RM, MASK_FMSUB_D | MASK_RM, match_opcode, WR_fd|RD_fs1|RD_fs2|RD_fs3 }, -+{"fmsub.d", "D", "D,S,T,R,m", MATCH_FMSUB_D, MASK_FMSUB_D, match_opcode, WR_fd|RD_fs1|RD_fs2|RD_fs3 }, -+{"fnmsub.d", "D", "D,S,T,R", MATCH_FNMSUB_D | MASK_RM, MASK_FNMSUB_D | MASK_RM, match_opcode, WR_fd|RD_fs1|RD_fs2|RD_fs3 }, -+{"fnmsub.d", "D", "D,S,T,R,m", MATCH_FNMSUB_D, MASK_FNMSUB_D, match_opcode, WR_fd|RD_fs1|RD_fs2|RD_fs3 }, -+{"fcvt.w.d", "D", "d,S", MATCH_FCVT_W_D | MASK_RM, MASK_FCVT_W_D | MASK_RM, match_opcode, WR_xd|RD_fs1 }, -+{"fcvt.w.d", "D", "d,S,m", MATCH_FCVT_W_D, MASK_FCVT_W_D, match_opcode, WR_xd|RD_fs1 }, -+{"fcvt.wu.d", "D", "d,S", MATCH_FCVT_WU_D | MASK_RM, MASK_FCVT_WU_D | MASK_RM, match_opcode, WR_xd|RD_fs1 }, -+{"fcvt.wu.d", "D", "d,S,m", MATCH_FCVT_WU_D, MASK_FCVT_WU_D, match_opcode, WR_xd|RD_fs1 }, -+{"fcvt.d.w", "D", "D,s", MATCH_FCVT_D_W, MASK_FCVT_D_W | MASK_RM, match_opcode, WR_fd|RD_xs1 }, -+{"fcvt.d.wu", "D", "D,s", MATCH_FCVT_D_WU, MASK_FCVT_D_WU | MASK_RM, match_opcode, WR_fd|RD_xs1 }, -+{"fcvt.d.s", "D", "D,S", MATCH_FCVT_D_S, MASK_FCVT_D_S | MASK_RM, match_opcode, WR_fd|RD_fs1 }, -+{"fcvt.s.d", "D", "D,S", MATCH_FCVT_S_D | MASK_RM, MASK_FCVT_S_D | MASK_RM, match_opcode, WR_fd|RD_fs1 }, -+{"fcvt.s.d", "D", "D,S,m", MATCH_FCVT_S_D, MASK_FCVT_S_D, match_opcode, WR_fd|RD_fs1 }, -+{"fclass.d", "D", "d,S", MATCH_FCLASS_D, MASK_FCLASS_D, match_opcode, WR_xd|RD_fs1 }, -+{"feq.d", "D", "d,S,T", MATCH_FEQ_D, MASK_FEQ_D, match_opcode, WR_xd|RD_fs1|RD_fs2 }, -+{"flt.d", "D", "d,S,T", MATCH_FLT_D, MASK_FLT_D, match_opcode, WR_xd|RD_fs1|RD_fs2 }, -+{"fle.d", "D", "d,S,T", MATCH_FLE_D, MASK_FLE_D, match_opcode, WR_xd|RD_fs1|RD_fs2 }, -+{"fgt.d", "D", "d,T,S", MATCH_FLT_D, MASK_FLT_D, match_opcode, WR_xd|RD_fs1|RD_fs2 }, -+{"fge.d", "D", "d,T,S", MATCH_FLE_D, MASK_FLE_D, match_opcode, WR_xd|RD_fs1|RD_fs2 }, -+{"fmv.x.d", "64D", "d,S", MATCH_FMV_X_D, MASK_FMV_X_D, match_opcode, WR_xd|RD_fs1 }, -+{"fmv.d.x", "64D", "D,s", MATCH_FMV_D_X, MASK_FMV_D_X, match_opcode, WR_fd|RD_xs1 }, -+{"fcvt.l.d", "64D", "d,S", MATCH_FCVT_L_D | MASK_RM, MASK_FCVT_L_D | MASK_RM, match_opcode, WR_xd|RD_fs1 }, -+{"fcvt.l.d", "64D", "d,S,m", MATCH_FCVT_L_D, MASK_FCVT_L_D, match_opcode, WR_xd|RD_fs1 }, -+{"fcvt.lu.d", "64D", "d,S", MATCH_FCVT_LU_D | MASK_RM, MASK_FCVT_LU_D | MASK_RM, match_opcode, WR_xd|RD_fs1 }, -+{"fcvt.lu.d", "64D", "d,S,m", MATCH_FCVT_LU_D, MASK_FCVT_LU_D, match_opcode, WR_xd|RD_fs1 }, -+{"fcvt.d.l", "64D", "D,s", MATCH_FCVT_D_L | MASK_RM, MASK_FCVT_D_L | MASK_RM, match_opcode, WR_fd|RD_xs1 }, -+{"fcvt.d.l", "64D", "D,s,m", MATCH_FCVT_D_L, MASK_FCVT_D_L, match_opcode, WR_fd|RD_xs1 }, -+{"fcvt.d.lu", "64D", "D,s", MATCH_FCVT_D_LU | MASK_RM, MASK_FCVT_D_L | MASK_RM, match_opcode, WR_fd|RD_xs1 }, -+{"fcvt.d.lu", "64D", "D,s,m", MATCH_FCVT_D_LU, MASK_FCVT_D_LU, match_opcode, WR_fd|RD_xs1 }, -+ -+/* Supervisor instructions */ -+{"csrr", "I", "d,E", MATCH_CSRRS, MASK_CSRRS | MASK_RS1, match_opcode, WR_xd }, -+{"csrwi", "I", "E,Z", MATCH_CSRRWI, MASK_CSRRWI | MASK_RD, match_opcode, WR_xd|RD_xs1 }, -+{"csrw", "I", "E,s", MATCH_CSRRW, MASK_CSRRW | MASK_RD, match_opcode, RD_xs1 }, -+{"csrw", "I", "E,Z", MATCH_CSRRWI, MASK_CSRRWI | MASK_RD, match_opcode, WR_xd|RD_xs1 }, -+{"csrsi", "I", "E,Z", MATCH_CSRRSI, MASK_CSRRSI | MASK_RD, match_opcode, WR_xd|RD_xs1 }, -+{"csrs", "I", "E,s", MATCH_CSRRS, MASK_CSRRS | MASK_RD, match_opcode, WR_xd|RD_xs1 }, -+{"csrs", "I", "E,Z", MATCH_CSRRSI, MASK_CSRRSI | MASK_RD, match_opcode, WR_xd|RD_xs1 }, -+{"csrci", "I", "E,Z", MATCH_CSRRCI, MASK_CSRRCI | MASK_RD, match_opcode, WR_xd|RD_xs1 }, -+{"csrc", "I", "E,s", MATCH_CSRRC, MASK_CSRRC | MASK_RD, match_opcode, WR_xd|RD_xs1 }, -+{"csrc", "I", "E,Z", MATCH_CSRRCI, MASK_CSRRCI | MASK_RD, match_opcode, WR_xd|RD_xs1 }, -+{"csrrw", "I", "d,E,s", MATCH_CSRRW, MASK_CSRRW, match_opcode, WR_xd|RD_xs1 }, -+{"csrrw", "I", "d,E,Z", MATCH_CSRRWI, MASK_CSRRWI, match_opcode, WR_xd|RD_xs1 }, -+{"csrrs", "I", "d,E,s", MATCH_CSRRS, MASK_CSRRS, match_opcode, WR_xd|RD_xs1 }, -+{"csrrs", "I", "d,E,Z", MATCH_CSRRSI, MASK_CSRRSI, match_opcode, WR_xd|RD_xs1 }, -+{"csrrc", "I", "d,E,s", MATCH_CSRRC, MASK_CSRRC, match_opcode, WR_xd|RD_xs1 }, -+{"csrrc", "I", "d,E,Z", MATCH_CSRRCI, MASK_CSRRCI, match_opcode, WR_xd|RD_xs1 }, -+{"csrrwi", "I", "d,E,Z", MATCH_CSRRWI, MASK_CSRRWI, match_opcode, WR_xd|RD_xs1 }, -+{"csrrsi", "I", "d,E,Z", MATCH_CSRRSI, MASK_CSRRSI, match_opcode, WR_xd|RD_xs1 }, -+{"csrrci", "I", "d,E,Z", MATCH_CSRRCI, MASK_CSRRCI, match_opcode, WR_xd|RD_xs1 }, -+{"sret", "I", "", MATCH_SRET, MASK_SRET, match_opcode, 0 }, -+ -+/* Half-precision floating-point instruction subset */ -+{"flh", "Xhwacha", "D,o(s)", MATCH_FLH, MASK_FLH, match_opcode, WR_fd|RD_xs1 }, -+{"fsh", "Xhwacha", "T,q(s)", MATCH_FSH, MASK_FSH, match_opcode, RD_xs1|RD_fs2 }, -+{"fsgnj.h", "Xhwacha", "D,S,T", MATCH_FSGNJ_H, MASK_FSGNJ_H, match_opcode, WR_fd|RD_fs1|RD_fs2 }, -+{"fsgnjn.h", "Xhwacha", "D,S,T", MATCH_FSGNJN_H, MASK_FSGNJN_H, match_opcode, WR_fd|RD_fs1|RD_fs2 }, -+{"fsgnjx.h", "Xhwacha", "D,S,T", MATCH_FSGNJX_H, MASK_FSGNJX_H, match_opcode, WR_fd|RD_fs1|RD_fs2 }, -+{"fadd.h", "Xhwacha", "D,S,T", MATCH_FADD_H | MASK_RM, MASK_FADD_H | MASK_RM, match_opcode, WR_fd|RD_fs1|RD_fs2 }, -+{"fadd.h", "Xhwacha", "D,S,T,m", MATCH_FADD_H, MASK_FADD_H, match_opcode, WR_fd|RD_fs1|RD_fs2 }, -+{"fsub.h", "Xhwacha", "D,S,T", MATCH_FSUB_H | MASK_RM, MASK_FSUB_H | MASK_RM, match_opcode, WR_fd|RD_fs1|RD_fs2 }, -+{"fsub.h", "Xhwacha", "D,S,T,m", MATCH_FSUB_H, MASK_FSUB_H, match_opcode, WR_fd|RD_fs1|RD_fs2 }, -+{"fmul.h", "Xhwacha", "D,S,T", MATCH_FMUL_H | MASK_RM, MASK_FMUL_H | MASK_RM, match_opcode, WR_fd|RD_fs1|RD_fs2 }, -+{"fmul.h", "Xhwacha", "D,S,T,m", MATCH_FMUL_H, MASK_FMUL_H, match_opcode, WR_fd|RD_fs1|RD_fs2 }, -+{"fdiv.h", "Xhwacha", "D,S,T", MATCH_FDIV_H | MASK_RM, MASK_FDIV_H | MASK_RM, match_opcode, WR_fd|RD_fs1|RD_fs2 }, -+{"fdiv.h", "Xhwacha", "D,S,T,m", MATCH_FDIV_H, MASK_FDIV_H, match_opcode, WR_fd|RD_fs1|RD_fs2 }, -+{"fsqrt.h", "Xhwacha", "D,S", MATCH_FSQRT_H | MASK_RM, MASK_FSQRT_H | MASK_RM, match_opcode, WR_fd|RD_fs1 }, -+{"fsqrt.h", "Xhwacha", "D,S,m", MATCH_FSQRT_H, MASK_FSQRT_H, match_opcode, WR_fd|RD_fs1 }, -+{"fmin.h", "Xhwacha", "D,S,T", MATCH_FMIN_H, MASK_FMIN_H, match_opcode, WR_fd|RD_fs1|RD_fs2 }, -+{"fmax.h", "Xhwacha", "D,S,T", MATCH_FMAX_H, MASK_FMAX_H, match_opcode, WR_fd|RD_fs1|RD_fs2 }, -+{"fmadd.h", "Xhwacha", "D,S,T,R", MATCH_FMADD_H | MASK_RM, MASK_FMADD_H | MASK_RM, match_opcode, WR_fd|RD_fs1|RD_fs2|RD_fs3 }, -+{"fmadd.h", "Xhwacha", "D,S,T,R,m", MATCH_FMADD_H, MASK_FMADD_H, match_opcode, WR_fd|RD_fs1|RD_fs2|RD_fs3 }, -+{"fnmadd.h", "Xhwacha", "D,S,T,R", MATCH_FNMADD_H | MASK_RM, MASK_FNMADD_H | MASK_RM, match_opcode, WR_fd|RD_fs1|RD_fs2|RD_fs3 }, -+{"fnmadd.h", "Xhwacha", "D,S,T,R,m", MATCH_FNMADD_H, MASK_FNMADD_H, match_opcode, WR_fd|RD_fs1|RD_fs2|RD_fs3 }, -+{"fmsub.h", "Xhwacha", "D,S,T,R", MATCH_FMSUB_H | MASK_RM, MASK_FMSUB_H | MASK_RM, match_opcode, WR_fd|RD_fs1|RD_fs2|RD_fs3 }, -+{"fmsub.h", "Xhwacha", "D,S,T,R,m", MATCH_FMSUB_H, MASK_FMSUB_H, match_opcode, WR_fd|RD_fs1|RD_fs2|RD_fs3 }, -+{"fnmsub.h", "Xhwacha", "D,S,T,R", MATCH_FNMSUB_H | MASK_RM, MASK_FNMSUB_H | MASK_RM, match_opcode, WR_fd|RD_fs1|RD_fs2|RD_fs3 }, -+{"fnmsub.h", "Xhwacha", "D,S,T,R,m", MATCH_FNMSUB_H, MASK_FNMSUB_H, match_opcode, WR_fd|RD_fs1|RD_fs2|RD_fs3 }, -+{"fcvt.s.h", "Xhwacha", "D,S", MATCH_FCVT_S_H, MASK_FCVT_S_H | MASK_RM, match_opcode, WR_fd|RD_fs1 }, -+{"fcvt.h.s", "Xhwacha", "D,S", MATCH_FCVT_H_S | MASK_RM, MASK_FCVT_H_S | MASK_RM, match_opcode, WR_fd|RD_fs1 }, -+{"fcvt.h.s", "Xhwacha", "D,S,m", MATCH_FCVT_H_S, MASK_FCVT_H_S, match_opcode, WR_fd|RD_fs1 }, -+{"fcvt.d.h", "Xhwacha", "D,S", MATCH_FCVT_D_H, MASK_FCVT_D_H | MASK_RM, match_opcode, WR_fd|RD_fs1 }, -+{"fcvt.h.d", "Xhwacha", "D,S", MATCH_FCVT_H_D | MASK_RM, MASK_FCVT_H_D | MASK_RM, match_opcode, WR_fd|RD_fs1 }, -+{"fcvt.h.d", "Xhwacha", "D,S,m", MATCH_FCVT_H_D, MASK_FCVT_H_D, match_opcode, WR_fd|RD_fs1 }, -+{"feq.h", "Xhwacha", "d,S,T", MATCH_FEQ_H, MASK_FEQ_H, match_opcode, WR_xd|RD_fs1|RD_fs2 }, -+{"flt.h", "Xhwacha", "d,S,T", MATCH_FLT_H, MASK_FLT_H, match_opcode, WR_xd|RD_fs1|RD_fs2 }, -+{"fle.h", "Xhwacha", "d,S,T", MATCH_FLE_H, MASK_FLE_H, match_opcode, WR_xd|RD_fs1|RD_fs2 }, -+{"fgt.h", "Xhwacha", "d,T,S", MATCH_FLT_H, MASK_FLT_H, match_opcode, WR_xd|RD_fs1|RD_fs2 }, -+{"fge.h", "Xhwacha", "d,T,S", MATCH_FLE_H, MASK_FLE_H, match_opcode, WR_xd|RD_fs1|RD_fs2 }, -+{"fmv.x.h", "Xhwacha", "d,S", MATCH_FMV_X_H, MASK_FMV_X_H, match_opcode, WR_xd|RD_fs1 }, -+{"fmv.h.x", "Xhwacha", "D,s", MATCH_FMV_H_X, MASK_FMV_H_X, match_opcode, WR_fd|RD_xs1 }, -+{"fcvt.w.h", "Xhwacha", "d,S", MATCH_FCVT_W_H | MASK_RM, MASK_FCVT_W_H | MASK_RM, match_opcode, WR_xd|RD_fs1 }, -+{"fcvt.w.h", "Xhwacha", "d,S,m", MATCH_FCVT_W_H, MASK_FCVT_W_H, match_opcode, WR_xd|RD_fs1 }, -+{"fcvt.wu.h", "Xhwacha", "d,S", MATCH_FCVT_WU_H | MASK_RM, MASK_FCVT_WU_H | MASK_RM, match_opcode, WR_xd|RD_fs1 }, -+{"fcvt.wu.h", "Xhwacha", "d,S,m", MATCH_FCVT_WU_H, MASK_FCVT_WU_H, match_opcode, WR_xd|RD_fs1 }, -+{"fcvt.h.w", "Xhwacha", "D,s", MATCH_FCVT_H_W, MASK_FCVT_H_W | MASK_RM, match_opcode, WR_fd|RD_xs1 }, -+{"fcvt.h.wu", "Xhwacha", "D,s", MATCH_FCVT_H_WU, MASK_FCVT_H_WU | MASK_RM, match_opcode, WR_fd|RD_xs1 }, -+{"fcvt.l.h", "Xhwacha", "d,S", MATCH_FCVT_L_H | MASK_RM, MASK_FCVT_L_H | MASK_RM, match_opcode, WR_xd|RD_fs1 }, -+{"fcvt.l.h", "Xhwacha", "d,S,m", MATCH_FCVT_L_H, MASK_FCVT_L_H, match_opcode, WR_xd|RD_fs1 }, -+{"fcvt.lu.h", "Xhwacha", "d,S", MATCH_FCVT_LU_H | MASK_RM, MASK_FCVT_LU_H | MASK_RM, match_opcode, WR_xd|RD_fs1 }, -+{"fcvt.lu.h", "Xhwacha", "d,S,m", MATCH_FCVT_LU_H, MASK_FCVT_LU_H, match_opcode, WR_xd|RD_fs1 }, -+{"fcvt.h.l", "Xhwacha", "D,s", MATCH_FCVT_H_L | MASK_RM, MASK_FCVT_H_L | MASK_RM, match_opcode, WR_fd|RD_xs1 }, -+{"fcvt.h.l", "Xhwacha", "D,s,m", MATCH_FCVT_H_L, MASK_FCVT_H_L, match_opcode, WR_fd|RD_xs1 }, -+{"fcvt.h.lu", "Xhwacha", "D,s", MATCH_FCVT_H_LU | MASK_RM, MASK_FCVT_H_L | MASK_RM, match_opcode, WR_fd|RD_xs1 }, -+{"fcvt.h.lu", "Xhwacha", "D,s,m", MATCH_FCVT_H_LU, MASK_FCVT_H_LU, match_opcode, WR_fd|RD_xs1 }, -+ -+/* Rocket Custom Coprocessor extension */ -+{"custom0", "Xcustom", "d,s,t,^j", MATCH_CUSTOM0_RD_RS1_RS2, MASK_CUSTOM0_RD_RS1_RS2, match_opcode, 0}, -+{"custom0", "Xcustom", "d,s,^t,^j", MATCH_CUSTOM0_RD_RS1, MASK_CUSTOM0_RD_RS1, match_opcode, 0}, -+{"custom0", "Xcustom", "d,^s,^t,^j", MATCH_CUSTOM0_RD, MASK_CUSTOM0_RD, match_opcode, 0}, -+{"custom0", "Xcustom", "^d,s,t,^j", MATCH_CUSTOM0_RS1_RS2, MASK_CUSTOM0_RS1_RS2, match_opcode, 0}, -+{"custom0", "Xcustom", "^d,s,^t,^j", MATCH_CUSTOM0_RS1, MASK_CUSTOM0_RS1, match_opcode, 0}, -+{"custom0", "Xcustom", "^d,^s,^t,^j", MATCH_CUSTOM0, MASK_CUSTOM0, match_opcode, 0}, -+{"custom1", "Xcustom", "d,s,t,^j", MATCH_CUSTOM1_RD_RS1_RS2, MASK_CUSTOM1_RD_RS1_RS2, match_opcode, 0}, -+{"custom1", "Xcustom", "d,s,^t,^j", MATCH_CUSTOM1_RD_RS1, MASK_CUSTOM1_RD_RS1, match_opcode, 0}, -+{"custom1", "Xcustom", "d,^s,^t,^j", MATCH_CUSTOM1_RD, MASK_CUSTOM1_RD, match_opcode, 0}, -+{"custom1", "Xcustom", "^d,s,t,^j", MATCH_CUSTOM1_RS1_RS2, MASK_CUSTOM1_RS1_RS2, match_opcode, 0}, -+{"custom1", "Xcustom", "^d,s,^t,^j", MATCH_CUSTOM1_RS1, MASK_CUSTOM1_RS1, match_opcode, 0}, -+{"custom1", "Xcustom", "^d,^s,^t,^j", MATCH_CUSTOM1, MASK_CUSTOM1, match_opcode, 0}, -+{"custom2", "Xcustom", "d,s,t,^j", MATCH_CUSTOM2_RD_RS1_RS2, MASK_CUSTOM2_RD_RS1_RS2, match_opcode, 0}, -+{"custom2", "Xcustom", "d,s,^t,^j", MATCH_CUSTOM2_RD_RS1, MASK_CUSTOM2_RD_RS1, match_opcode, 0}, -+{"custom2", "Xcustom", "d,^s,^t,^j", MATCH_CUSTOM2_RD, MASK_CUSTOM2_RD, match_opcode, 0}, -+{"custom2", "Xcustom", "^d,s,t,^j", MATCH_CUSTOM2_RS1_RS2, MASK_CUSTOM2_RS1_RS2, match_opcode, 0}, -+{"custom2", "Xcustom", "^d,s,^t,^j", MATCH_CUSTOM2_RS1, MASK_CUSTOM2_RS1, match_opcode, 0}, -+{"custom2", "Xcustom", "^d,^s,^t,^j", MATCH_CUSTOM2, MASK_CUSTOM2, match_opcode, 0}, -+{"custom3", "Xcustom", "d,s,t,^j", MATCH_CUSTOM3_RD_RS1_RS2, MASK_CUSTOM3_RD_RS1_RS2, match_opcode, 0}, -+{"custom3", "Xcustom", "d,s,^t,^j", MATCH_CUSTOM3_RD_RS1, MASK_CUSTOM3_RD_RS1, match_opcode, 0}, -+{"custom3", "Xcustom", "d,^s,^t,^j", MATCH_CUSTOM3_RD, MASK_CUSTOM3_RD, match_opcode, 0}, -+{"custom3", "Xcustom", "^d,s,t,^j", MATCH_CUSTOM3_RS1_RS2, MASK_CUSTOM3_RS1_RS2, match_opcode, 0}, -+{"custom3", "Xcustom", "^d,s,^t,^j", MATCH_CUSTOM3_RS1, MASK_CUSTOM3_RS1, match_opcode, 0}, -+{"custom3", "Xcustom", "^d,^s,^t,^j", MATCH_CUSTOM3, MASK_CUSTOM3, match_opcode, 0}, -+ -+/* Xhwacha extension */ -+{"stop", "Xhwacha", "", MATCH_STOP, MASK_STOP, match_opcode, 0}, -+{"utidx", "Xhwacha", "d", MATCH_UTIDX, MASK_UTIDX, match_opcode, WR_xd}, -+{"movz", "Xhwacha", "d,s,t", MATCH_MOVZ, MASK_MOVZ, match_opcode, WR_xd|RD_xs1|RD_xs2}, -+{"movn", "Xhwacha", "d,s,t", MATCH_MOVN, MASK_MOVN, match_opcode, WR_xd|RD_xs1|RD_xs2}, -+{"fmovz", "Xhwacha", "D,s,T", MATCH_FMOVZ, MASK_FMOVZ, match_opcode, WR_fd|RD_xs1|RD_fs2}, -+{"fmovn", "Xhwacha", "D,s,T", MATCH_FMOVN, MASK_FMOVN, match_opcode, WR_fd|RD_xs1|RD_fs2}, -+ -+/* unit stride */ -+/* xloads */ -+{"vld", "Xhwacha", "#d,s", MATCH_VLD, MASK_VLD, match_opcode, 0}, -+{"vlw", "Xhwacha", "#d,s", MATCH_VLW, MASK_VLW, match_opcode, 0}, -+{"vlwu", "Xhwacha", "#d,s", MATCH_VLWU, MASK_VLWU, match_opcode, 0}, -+{"vlh", "Xhwacha", "#d,s", MATCH_VLH, MASK_VLH, match_opcode, 0}, -+{"vlhu", "Xhwacha", "#d,s", MATCH_VLHU, MASK_VLHU, match_opcode, 0}, -+{"vlb", "Xhwacha", "#d,s", MATCH_VLB, MASK_VLB, match_opcode, 0}, -+{"vlbu", "Xhwacha", "#d,s", MATCH_VLBU, MASK_VLBU, match_opcode, 0}, -+/* floads */ -+{"vfld", "Xhwacha", "#D,s", MATCH_VFLD, MASK_VFLD, match_opcode, 0}, -+{"vflw", "Xhwacha", "#D,s", MATCH_VFLW, MASK_VFLW, match_opcode, 0}, -+ -+/* stride */ -+/* xloads */ -+{"vlstd", "Xhwacha", "#d,s,t", MATCH_VLSTD, MASK_VLSTD, match_opcode, 0}, -+{"vlstw", "Xhwacha", "#d,s,t", MATCH_VLSTW, MASK_VLSTW, match_opcode, 0}, -+{"vlstwu", "Xhwacha", "#d,s,t", MATCH_VLSTWU, MASK_VLSTWU, match_opcode, 0}, -+{"vlsth", "Xhwacha", "#d,s,t", MATCH_VLSTH, MASK_VLSTH, match_opcode, 0}, -+{"vlsthu", "Xhwacha", "#d,s,t", MATCH_VLSTHU, MASK_VLSTHU, match_opcode, 0}, -+{"vlstb", "Xhwacha", "#d,s,t", MATCH_VLSTB, MASK_VLSTB, match_opcode, 0}, -+{"vlstbu", "Xhwacha", "#d,s,t", MATCH_VLSTBU, MASK_VLSTBU, match_opcode, 0}, -+/* floads */ -+{"vflstd", "Xhwacha", "#D,s,t", MATCH_VFLSTD, MASK_VFLSTD, match_opcode, 0}, -+{"vflstw", "Xhwacha", "#D,s,t", MATCH_VFLSTW, MASK_VFLSTW, match_opcode, 0}, -+ -+/* segment */ -+/* xloads */ -+{"vlsegd", "Xhwacha", "#d,s,#n", MATCH_VLSEGD, MASK_VLSEGD, match_opcode, 0}, -+{"vlsegw", "Xhwacha", "#d,s,#n", MATCH_VLSEGW, MASK_VLSEGW, match_opcode, 0}, -+{"vlsegwu", "Xhwacha", "#d,s,#n", MATCH_VLSEGWU, MASK_VLSEGWU, match_opcode, 0}, -+{"vlsegh", "Xhwacha", "#d,s,#n", MATCH_VLSEGH, MASK_VLSEGH, match_opcode, 0}, -+{"vlseghu", "Xhwacha", "#d,s,#n", MATCH_VLSEGHU, MASK_VLSEGHU, match_opcode, 0}, -+{"vlsegb", "Xhwacha", "#d,s,#n", MATCH_VLSEGB, MASK_VLSEGB, match_opcode, 0}, -+{"vlsegbu", "Xhwacha", "#d,s,#n", MATCH_VLSEGBU, MASK_VLSEGBU, match_opcode, 0}, -+/* floads */ -+{"vflsegd", "Xhwacha", "#D,s,#n", MATCH_VFLSEGD, MASK_VFLSEGD, match_opcode, 0}, -+{"vflsegw", "Xhwacha", "#D,s,#n", MATCH_VFLSEGW, MASK_VFLSEGW, match_opcode, 0}, -+ -+/* stride segment */ -+/* xloads */ -+{"vlsegstd", "Xhwacha", "#d,s,t,#n", MATCH_VLSEGSTD, MASK_VLSEGSTD, match_opcode, 0}, -+{"vlsegstw", "Xhwacha", "#d,s,t,#n", MATCH_VLSEGSTW, MASK_VLSEGSTW, match_opcode, 0}, -+{"vlsegstwu", "Xhwacha", "#d,s,t,#n", MATCH_VLSEGSTWU, MASK_VLSEGSTWU, match_opcode, 0}, -+{"vlsegsth", "Xhwacha", "#d,s,t,#n", MATCH_VLSEGSTH, MASK_VLSEGSTH, match_opcode, 0}, -+{"vlsegsthu", "Xhwacha", "#d,s,t,#n", MATCH_VLSEGSTHU, MASK_VLSEGSTHU, match_opcode, 0}, -+{"vlsegstb", "Xhwacha", "#d,s,t,#n", MATCH_VLSEGSTB, MASK_VLSEGSTB, match_opcode, 0}, -+{"vlsegstbu", "Xhwacha", "#d,s,t,#n", MATCH_VLSEGSTBU, MASK_VLSEGSTBU, match_opcode, 0}, -+/* floads */ -+{"vflsegstd", "Xhwacha", "#D,s,t,#n", MATCH_VFLSEGSTD, MASK_VFLSEGSTD, match_opcode, 0}, -+{"vflsegstw", "Xhwacha", "#D,s,t,#n", MATCH_VFLSEGSTW, MASK_VFLSEGSTW, match_opcode, 0}, -+ -+/* unit stride */ -+/* xstores */ -+{"vsd", "Xhwacha", "#d,s", MATCH_VSD, MASK_VSD, match_opcode, 0}, -+{"vsw", "Xhwacha", "#d,s", MATCH_VSW, MASK_VSW, match_opcode, 0}, -+{"vsh", "Xhwacha", "#d,s", MATCH_VSH, MASK_VSH, match_opcode, 0}, -+{"vsb", "Xhwacha", "#d,s", MATCH_VSB, MASK_VSB, match_opcode, 0}, -+/* fstores */ -+{"vfsd", "Xhwacha", "#D,s", MATCH_VFSD, MASK_VFSD, match_opcode, 0}, -+{"vfsw", "Xhwacha", "#D,s", MATCH_VFSW, MASK_VFSW, match_opcode, 0}, -+ -+/* stride */ -+/* xstores */ -+{"vsstd", "Xhwacha", "#d,s,t", MATCH_VSSTD, MASK_VSSTD, match_opcode, 0}, -+{"vsstw", "Xhwacha", "#d,s,t", MATCH_VSSTW, MASK_VSSTW, match_opcode, 0}, -+{"vssth", "Xhwacha", "#d,s,t", MATCH_VSSTH, MASK_VSSTH, match_opcode, 0}, -+{"vsstb", "Xhwacha", "#d,s,t", MATCH_VSSTB, MASK_VSSTB, match_opcode, 0}, -+/* fstores */ -+{"vfsstd", "Xhwacha", "#D,s,t", MATCH_VFSSTD, MASK_VFSSTD, match_opcode, 0}, -+{"vfsstw", "Xhwacha", "#D,s,t", MATCH_VFSSTW, MASK_VFSSTW, match_opcode, 0}, -+ -+/* segment */ -+/* xstores */ -+{"vssegd", "Xhwacha", "#d,s,#n", MATCH_VSSEGD, MASK_VSSEGD, match_opcode, 0}, -+{"vssegw", "Xhwacha", "#d,s,#n", MATCH_VSSEGW, MASK_VSSEGW, match_opcode, 0}, -+{"vssegh", "Xhwacha", "#d,s,#n", MATCH_VSSEGH, MASK_VSSEGH, match_opcode, 0}, -+{"vssegb", "Xhwacha", "#d,s,#n", MATCH_VSSEGB, MASK_VSSEGB, match_opcode, 0}, -+/* fstores */ -+{"vfssegd", "Xhwacha", "#D,s,#n", MATCH_VFSSEGD, MASK_VFSSEGD, match_opcode, 0}, -+{"vfssegw", "Xhwacha", "#D,s,#n", MATCH_VFSSEGW, MASK_VFSSEGW, match_opcode, 0}, -+ -+/* stride segment */ -+/* xsegstores */ -+{"vssegstd", "Xhwacha", "#d,s,t,#n", MATCH_VSSEGSTD, MASK_VSSEGSTD, match_opcode, 0}, -+{"vssegstw", "Xhwacha", "#d,s,t,#n", MATCH_VSSEGSTW, MASK_VSSEGSTW, match_opcode, 0}, -+{"vssegsth", "Xhwacha", "#d,s,t,#n", MATCH_VSSEGSTH, MASK_VSSEGSTH, match_opcode, 0}, -+{"vssegstb", "Xhwacha", "#d,s,t,#n", MATCH_VSSEGSTB, MASK_VSSEGSTB, match_opcode, 0}, -+/* fsegstores */ -+{"vfssegstd", "Xhwacha", "#D,s,t,#n", MATCH_VFSSEGSTD, MASK_VFSSEGSTD, match_opcode, 0}, -+{"vfssegstw", "Xhwacha", "#D,s,t,#n", MATCH_VFSSEGSTW, MASK_VFSSEGSTW, match_opcode, 0}, -+ -+{"vsetcfg", "Xhwacha", "s", MATCH_VSETCFG, MASK_VSETCFG | MASK_IMM, match_opcode, 0}, -+{"vsetcfg", "Xhwacha", "#g,#f", MATCH_VSETCFG, MASK_VSETCFG | MASK_RS1, match_opcode, 0}, -+{"vsetcfg", "Xhwacha", "s,#g,#f", MATCH_VSETCFG, MASK_VSETCFG, match_opcode, 0}, -+{"vsetucfg", "Xhwacha", "d,u", MATCH_LUI, MASK_LUI, match_opcode, INSN_ALIAS | WR_xd}, -+{"vsetvl", "Xhwacha", "d,s", MATCH_VSETVL, MASK_VSETVL, match_opcode, 0}, -+{"vgetcfg", "Xhwacha", "d", MATCH_VGETCFG, MASK_VGETCFG, match_opcode, 0}, -+{"vgetvl", "Xhwacha", "d", MATCH_VGETVL, MASK_VGETVL, match_opcode, 0}, -+ -+{"vmvv", "Xhwacha", "#d,#s", MATCH_VMVV, MASK_VMVV, match_opcode, 0}, -+{"vmsv", "Xhwacha", "#d,s", MATCH_VMSV, MASK_VMSV, match_opcode, 0}, -+{"vfmvv", "Xhwacha", "#D,#S", MATCH_VFMVV, MASK_VFMVV, match_opcode, 0}, -+{"vfmsv.d", "Xhwacha", "#D,s", MATCH_VFMSV_D, MASK_VFMSV_D, match_opcode, 0}, -+{"vfmsv.s", "Xhwacha", "#D,s", MATCH_VFMSV_S, MASK_VFMSV_S, match_opcode, 0}, -+ -+{"vf", "Xhwacha", "q(s)", MATCH_VF, MASK_VF, match_opcode, 0}, -+{"vf", "Xhwacha", "A,s", 0, (int) M_VF, match_never, INSN_MACRO }, -+ -+{"vxcptcause", "Xhwacha", "d", MATCH_VXCPTCAUSE, MASK_VXCPTCAUSE, match_opcode, 0}, -+{"vxcptaux", "Xhwacha", "d", MATCH_VXCPTAUX, MASK_VXCPTAUX, match_opcode, 0}, -+ -+{"vxcptsave", "Xhwacha", "s", MATCH_VXCPTSAVE, MASK_VXCPTSAVE, match_opcode, 0}, -+{"vxcptrestore", "Xhwacha", "s", MATCH_VXCPTRESTORE, MASK_VXCPTRESTORE, match_opcode, 0}, -+{"vxcptkill", "Xhwacha", "", MATCH_VXCPTKILL, MASK_VXCPTKILL, match_opcode, 0}, -+ -+{"vxcptevac", "Xhwacha", "s", MATCH_VXCPTEVAC, MASK_VXCPTEVAC, match_opcode, 0}, -+{"vxcpthold", "Xhwacha", "", MATCH_VXCPTHOLD, MASK_VXCPTHOLD, match_opcode, 0}, -+{"venqcmd", "Xhwacha", "s,t", MATCH_VENQCMD, MASK_VENQCMD, match_opcode, 0}, -+{"venqimm1", "Xhwacha", "s,t", MATCH_VENQIMM1, MASK_VENQIMM1, match_opcode, 0}, -+{"venqimm2", "Xhwacha", "s,t", MATCH_VENQIMM2, MASK_VENQIMM2, match_opcode, 0}, -+{"venqcnt", "Xhwacha", "s,t", MATCH_VENQCNT, MASK_VENQCNT, match_opcode, 0}, -+}; -+ -+#define RISCV_NUM_OPCODES \ -+ ((sizeof riscv_builtin_opcodes) / (sizeof (riscv_builtin_opcodes[0]))) -+const int bfd_riscv_num_builtin_opcodes = RISCV_NUM_OPCODES; -+ -+/* const removed from the following to allow for dynamic extensions to the -+ * built-in instruction set. */ -+struct riscv_opcode *riscv_opcodes = -+ (struct riscv_opcode *) riscv_builtin_opcodes; -+int bfd_riscv_num_opcodes = RISCV_NUM_OPCODES; -+#undef RISCV_NUM_OPCODES diff --git a/recipes-devtool/riscv-tools/files/gcc-4.6.1-riscv.patch b/recipes-devtool/riscv-tools/files/gcc-4.6.1-riscv.patch deleted file mode 100644 index e0246fe..0000000 --- a/recipes-devtool/riscv-tools/files/gcc-4.6.1-riscv.patch +++ /dev/null @@ -1,11768 +0,0 @@ -diff --git a/gcc-4.6.1/config.sub b/gcc-4.6.1/config.sub -index 204218c..e14dc95 100755 ---- a/gcc-4.6.1/config.sub -+++ gcc-4.6.1/config.sub -@@ -323,6 +323,9 @@ case $basic_machine in - ms1) - basic_machine=mt-unknown - ;; -+ riscv) -+ basic_machine=riscv-ucb -+ ;; - - # We use `pc' rather than `unknown' - # because (1) that's what they normally are, and -diff --git a/gcc-4.6.1/gcc/config.gcc b/gcc-4.6.1/gcc/config.gcc -index ada68dd..321d4f2 100644 ---- a/gcc-4.6.1/gcc/config.gcc -+++ gcc-4.6.1/gcc/config.gcc -@@ -1861,6 +1861,18 @@ mips*-*-netbsd*) # NetBSD/mips, either endian. - tm_file="elfos.h ${tm_file} mips/elf.h netbsd.h netbsd-elf.h mips/netbsd.h" - extra_options="${extra_options} netbsd.opt netbsd-elf.opt" - ;; -+riscv*-*-linux*) # Linux RISC-V -+ tm_file="dbxelf.h elfos.h gnu-user.h linux.h glibc-stdint.h ${tm_file} riscv/linux.h riscv/linux64.h" -+ tmake_file="${tmake_file} riscv/t-linux64" -+ gnu_ld=yes -+ gas=yes -+ ;; -+riscv*-*-elf*) # Linux RISC-V -+ tm_file="dbxelf.h elfos.h newlib-stdint.h ${tm_file} riscv/elf.h" -+ tmake_file="${tmake_file} riscv/t-elf" -+ gnu_ld=yes -+ gas=yes -+ ;; - mips64*-*-linux* | mipsisa64*-*-linux*) - tm_file="dbxelf.h elfos.h gnu-user.h linux.h glibc-stdint.h ${tm_file} mips/linux.h mips/linux64.h" - tmake_file="${tmake_file} mips/t-linux64 mips/t-libgcc-mips16" -@@ -3381,6 +3393,31 @@ case "${target}" in - done - ;; - -+ riscv*-*-*) -+ supported_defaults="abi arch arch_32 arch_64 float tune tune_32 tune_64" -+ -+ case ${with_float} in -+ "" | soft | hard) -+ # OK -+ ;; -+ *) -+ echo "Unknown floating point type used in --with-float=$with_float" 1>&2 -+ exit 1 -+ ;; -+ esac -+ -+ case ${with_abi} in -+ "" | 32 | 64) -+ # OK -+ ;; -+ *) -+ echo "Unknown ABI used in --with-abi=$with_abi" 1>&2 -+ exit 1 -+ ;; -+ esac -+ -+ ;; -+ - mips*-*-*) - supported_defaults="abi arch arch_32 arch_64 float tune tune_32 tune_64 divide llsc mips-plt synci" - -diff --git a/gcc-4.6.1/gcc/config/riscv/constraints.md b/gcc-4.6.1/gcc/config/riscv/constraints.md -new file mode 100644 -index 0000000..b61051f ---- /dev/null -+++ gcc-4.6.1/gcc/config/riscv/constraints.md -@@ -0,0 +1,95 @@ -+;; Constraint definitions for RISC-V target. -+;; Copyright (C) 2011-2014 Free Software Foundation, Inc. -+;; Contributed by Andrew Waterman (waterman@cs.berkeley.edu) at UC Berkeley. -+;; Based on MIPS target for GNU compiler. -+;; -+;; This file is part of GCC. -+;; -+;; GCC is free software; you can redistribute it and/or modify -+;; it under the terms of the GNU General Public License as published by -+;; the Free Software Foundation; either version 3, or (at your option) -+;; any later version. -+;; -+;; GCC is distributed in the hope that it will be useful, -+;; but WITHOUT ANY WARRANTY; without even the implied warranty of -+;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -+;; GNU General Public License for more details. -+;; -+;; You should have received a copy of the GNU General Public License -+;; along with GCC; see the file COPYING3. If not see -+;; . -+ -+;; Register constraints -+ -+(define_register_constraint "f" "TARGET_HARD_FLOAT ? FP_REGS : NO_REGS" -+ "A floating-point register (if available).") -+ -+(define_register_constraint "b" "ALL_REGS" -+ "@internal") -+ -+(define_register_constraint "j" "T_REGS" -+ "@internal") -+ -+;; Integer constraints -+ -+(define_constraint "Z" -+ "@internal" -+ (and (match_code "const_int") -+ (match_test "1"))) -+ -+(define_constraint "I" -+ "An I-type 12-bit signed immediate." -+ (and (match_code "const_int") -+ (match_test "SMALL_OPERAND (ival)"))) -+ -+(define_constraint "J" -+ "Integer zero." -+ (and (match_code "const_int") -+ (match_test "ival == 0"))) -+ -+;; Floating-point constraints -+ -+(define_constraint "G" -+ "Floating-point zero." -+ (and (match_code "const_double") -+ (match_test "op == CONST0_RTX (mode)"))) -+ -+;; General constraints -+ -+(define_constraint "Q" -+ "@internal" -+ (match_operand 0 "const_arith_operand")) -+ -+(define_memory_constraint "YR" -+ "An address that is held in a general-purpose register." -+ (and (match_code "mem") -+ (match_test "GET_CODE(XEXP(op,0)) == REG"))) -+ -+(define_memory_constraint "R" -+ "An address that can be used in a non-macro load or store." -+ (and (match_code "mem") -+ (match_test "riscv_address_insns (XEXP (op, 0), mode, false) == 1"))) -+ -+(define_constraint "S" -+ "@internal -+ A constant call address." -+ (and (match_operand 0 "call_insn_operand") -+ (match_test "CONSTANT_P (op)"))) -+ -+(define_constraint "T" -+ "@internal -+ A constant @code{move_operand}." -+ (and (match_operand 0 "move_operand") -+ (match_test "CONSTANT_P (op)"))) -+ -+(define_memory_constraint "W" -+ "@internal -+ A memory address based on a member of @code{BASE_REG_CLASS}." -+ (and (match_code "mem") -+ (match_operand 0 "memory_operand"))) -+ -+(define_constraint "YG" -+ "@internal -+ A vector zero." -+ (and (match_code "const_vector") -+ (match_test "op == CONST0_RTX (mode)"))) -diff --git a/gcc-4.6.1/gcc/config/riscv/crti.asm b/gcc-4.6.1/gcc/config/riscv/crti.asm -new file mode 100644 -index 0000000..ce9b393 ---- /dev/null -+++ gcc-4.6.1/gcc/config/riscv/crti.asm -@@ -0,0 +1,42 @@ -+/* Copyright (C) 2001, 2002 Free Software Foundation, Inc. -+ -+This file is part of GCC. -+ -+GCC is free software; you can redistribute it and/or modify it under -+the terms of the GNU General Public License as published by the Free -+Software Foundation; either version 3, or (at your option) any later -+version. -+ -+GCC is distributed in the hope that it will be useful, but WITHOUT ANY -+WARRANTY; without even the implied warranty of MERCHANTABILITY or -+FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License -+for more details. -+ -+Under Section 7 of GPL version 3, you are granted additional -+permissions described in the GCC Runtime Library Exception, version -+3.1, as published by the Free Software Foundation. -+ -+You should have received a copy of the GNU General Public License and -+a copy of the GCC Runtime Library Exception along with this program; -+see the files COPYING3 and COPYING.RUNTIME respectively. If not, see -+. */ -+ -+#ifdef __riscv64 -+# define SR sd -+#else -+# define SR sw -+#endif -+ -+ .section .init,"ax",@progbits -+ .globl _init -+ .type _init,@function -+_init: -+ add sp, sp, -8 -+ SR ra, 0(sp) -+ -+ .section .fini,"ax",@progbits -+ .globl _fini -+ .type _fini,@function -+_fini: -+ add sp, sp, -8 -+ SR ra, 0(sp) -diff --git a/gcc-4.6.1/gcc/config/riscv/crtn.asm b/gcc-4.6.1/gcc/config/riscv/crtn.asm -new file mode 100644 -index 0000000..2b82d24 ---- /dev/null -+++ gcc-4.6.1/gcc/config/riscv/crtn.asm -@@ -0,0 +1,38 @@ -+/* Copyright (C) 2001, 2002 Free Software Foundation, Inc. -+ -+This file is part of GCC. -+ -+GCC is free software; you can redistribute it and/or modify it under -+the terms of the GNU General Public License as published by the Free -+Software Foundation; either version 3, or (at your option) any later -+version. -+ -+GCC is distributed in the hope that it will be useful, but WITHOUT ANY -+WARraNTY; without even the implied warranty of MERCHANTABILITY or -+FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License -+for more details. -+ -+Under Section 7 of GPL version 3, you are granted additional -+permissions described in the GCC Runtime Library Exception, version -+3.1, as published by the Free Software Foundation. -+ -+You should have received a copy of the GNU General Public License and -+a copy of the GCC Runtime Library Exception along with this program; -+see the files COPYING3 and COPYING.RUNTIME respectively. If not, see -+. */ -+ -+#ifdef __riscv64 -+# define LR ld -+#else -+# define LR lw -+#endif -+ -+ .section .init,"ax",@progbits -+ LR ra, 0(sp) -+ addi sp, sp, 8 -+ ret -+ -+ .section .fini,"ax",@progbits -+ LR ra, 0(sp) -+ addi sp, sp, 8 -+ ret -diff --git a/gcc-4.6.1/gcc/config/riscv/div.S b/gcc-4.6.1/gcc/config/riscv/div.S -new file mode 100644 -index 0000000..4388836 ---- /dev/null -+++ gcc-4.6.1/gcc/config/riscv/div.S -@@ -0,0 +1,121 @@ -+ .text -+ .align 2 -+ -+#ifndef __riscv64 -+/* Our RV64 64-bit routines are equivalent to our RV32 32-bit routines. */ -+# define __udivdi3 __udivsi3 -+# define __umoddi3 __umodsi3 -+# define __divdi3 __divsi3 -+# define __moddi3 __modsi3 -+#else -+ .globl __udivsi3 -+__udivsi3: -+ /* Compute __udivdi3(a0 << 32, a1 << 32); cast result to uint32_t. */ -+ sll a0, a0, 32 -+ sll a1, a1, 32 -+ move t0, ra -+ jal __udivdi3 -+ sext.w v0, v0 -+ jr t0 -+ -+ .globl __umodsi3 -+__umodsi3: -+ /* Compute __udivdi3((uint32_t)a0, (uint32_t)a1); cast v1 to uint32_t. */ -+ sll a0, a0, 32 -+ sll a1, a1, 32 -+ srl a0, a0, 32 -+ srl a1, a1, 32 -+ move t0, ra -+ jal __udivdi3 -+ sext.w v0, v1 -+ jr t0 -+ -+ .globl __modsi3 -+ __modsi3 = __moddi3 -+ -+ .globl __divsi3 -+__divsi3: -+ /* Check for special case of INT_MIN/-1. Otherwise, fall into __divdi3. */ -+ li t0, -1 -+ beq a1, t0, .L20 -+#endif -+ -+ .globl __divdi3 -+__divdi3: -+ bltz a0, .L10 -+ bltz a1, .L11 -+ /* Since the quotient is positive, fall into __udivdi3. */ -+ -+ .globl __udivdi3 -+__udivdi3: -+ move v1, a0 -+ li v0, -1 -+ beqz a1, .L5 -+ li a0, 1 -+ bgeu a1, v1, .L2 -+.L1: -+ blez a1, .L2 -+ slli a1, a1, 1 -+ slli a0, a0, 1 -+ bgtu v1, a1, .L1 -+.L2: -+ li v0, 0 -+.L3: -+ bltu v1, a1, .L4 -+ sub v1, v1, a1 -+ or v0, v0, a0 -+.L4: -+ srli a0, a0, 1 -+ srli a1, a1, 1 -+ bnez a0, .L3 -+.L5: -+ ret -+ -+ .globl __umoddi3 -+__umoddi3: -+ /* Call __udivdi3(a0, a1), then return the remainder, which is in v1. */ -+ move t0, ra -+ jal __udivdi3 -+ move v0, v1 -+ jr t0 -+ -+ /* Handle negative arguments to __divdi3. */ -+.L10: -+ neg a0, a0 -+ bgez a1, .L12 /* Compute __udivdi3(-a0, a1), then negate the result. */ -+ neg a1, a1 -+ j __divdi3 /* Compute __udivdi3(-a0, -a1). */ -+.L11: /* Compute __udivdi3(a0, -a1), then negate the result. */ -+ neg a1, a1 -+.L12: -+ move t0, ra -+ jal __divdi3 -+ neg v0, v0 -+ jr t0 -+ -+ .globl __moddi3 -+__moddi3: -+ move t0, ra -+ bltz a1, .L31 -+ bltz a0, .L32 -+.L30: -+ jal __udivdi3 /* The dividend is not negative. */ -+ move v0, v1 -+ jr t0 -+.L31: -+ neg a1, a1 -+ bgez a0, .L30 -+.L32: -+ neg a0, a0 -+ jal __udivdi3 /* The dividend is hella negative. */ -+ neg v0, v1 -+ jr t0 -+ -+#ifdef __riscv64 -+ /* continuation of __divsi3 */ -+.L20: -+ sll t0, t0, 31 -+ bne a0, t0, __divdi3 -+ move v0, a0 -+ ret -+#endif -diff --git a/gcc-4.6.1/gcc/config/riscv/elf.h b/gcc-4.6.1/gcc/config/riscv/elf.h -new file mode 100644 -index 0000000..2dc837b ---- /dev/null -+++ gcc-4.6.1/gcc/config/riscv/elf.h -@@ -0,0 +1,31 @@ -+/* Target macros for mips*-elf targets. -+ Copyright (C) 1994, 1997, 1999, 2000, 2002, 2003, 2004, 2007, 2010 -+ Free Software Foundation, Inc. -+ -+This file is part of GCC. -+ -+GCC is free software; you can redistribute it and/or modify -+it under the terms of the GNU General Public License as published by -+the Free Software Foundation; either version 3, or (at your option) -+any later version. -+ -+GCC is distributed in the hope that it will be useful, -+but WITHOUT ANY WARRANTY; without even the implied warranty of -+MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -+GNU General Public License for more details. -+ -+You should have received a copy of the GNU General Public License -+along with GCC; see the file COPYING3. If not see -+. */ -+ -+/* Leave the linker script to choose the appropriate libraries. */ -+#undef LIB_SPEC -+#define LIB_SPEC "" -+ -+#undef STARTFILE_SPEC -+#define STARTFILE_SPEC "crti%O%s crtbegin%O%s" -+ -+#undef ENDFILE_SPEC -+#define ENDFILE_SPEC "crtend%O%s crtn%O%s" -+ -+#define NO_IMPLICIT_EXTERN_C 1 -diff --git a/gcc-4.6.1/gcc/config/riscv/generic.md b/gcc-4.6.1/gcc/config/riscv/generic.md -new file mode 100644 -index 0000000..a6dc8fa7a ---- /dev/null -+++ gcc-4.6.1/gcc/config/riscv/generic.md -@@ -0,0 +1,98 @@ -+;; Generic DFA-based pipeline description for RISC-V targets. -+;; Copyright (C) 2011-2014 Free Software Foundation, Inc. -+;; Contributed by Andrew Waterman (waterman@cs.berkeley.edu) at UC Berkeley. -+;; Based on MIPS target for GNU compiler. -+ -+;; This file is part of GCC. -+ -+;; GCC is free software; you can redistribute it and/or modify it -+;; under the terms of the GNU General Public License as published -+;; by the Free Software Foundation; either version 3, or (at your -+;; option) any later version. -+ -+;; GCC is distributed in the hope that it will be useful, but WITHOUT -+;; ANY WARRANTY; without even the implied warranty of MERCHANTABILITY -+;; or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public -+;; License for more details. -+ -+;; You should have received a copy of the GNU General Public License -+;; along with GCC; see the file COPYING3. If not see -+;; . -+ -+ -+;; This file is derived from the old define_function_unit description. -+;; Each reservation can be overridden on a processor-by-processor basis. -+ -+(define_insn_reservation "generic_alu" 1 -+ (eq_attr "type" "unknown,const,arith,shift,slt,multi,nop,logical,move") -+ "alu") -+ -+(define_insn_reservation "generic_load" 3 -+ (eq_attr "type" "load,fpload,fpidxload") -+ "alu") -+ -+(define_insn_reservation "generic_store" 1 -+ (eq_attr "type" "store,fpstore,fpidxstore") -+ "alu") -+ -+(define_insn_reservation "generic_xfer" 2 -+ (eq_attr "type" "mfc,mtc") -+ "alu") -+ -+(define_insn_reservation "generic_branch" 1 -+ (eq_attr "type" "branch,jump,call") -+ "alu") -+ -+(define_insn_reservation "generic_imul" 17 -+ (eq_attr "type" "imul") -+ "imuldiv*17") -+ -+(define_insn_reservation "generic_idiv" 38 -+ (eq_attr "type" "idiv") -+ "imuldiv*38") -+ -+(define_insn_reservation "generic_fcvt" 1 -+ (eq_attr "type" "fcvt") -+ "alu") -+ -+(define_insn_reservation "generic_fmove" 2 -+ (eq_attr "type" "fmove") -+ "alu") -+ -+(define_insn_reservation "generic_fcmp" 3 -+ (eq_attr "type" "fcmp") -+ "alu") -+ -+(define_insn_reservation "generic_fadd" 4 -+ (eq_attr "type" "fadd") -+ "alu") -+ -+(define_insn_reservation "generic_fmul_single" 7 -+ (and (eq_attr "type" "fmul,fmadd") -+ (eq_attr "mode" "SF")) -+ "alu") -+ -+(define_insn_reservation "generic_fmul_double" 8 -+ (and (eq_attr "type" "fmul,fmadd") -+ (eq_attr "mode" "DF")) -+ "alu") -+ -+(define_insn_reservation "generic_fdiv_single" 23 -+ (and (eq_attr "type" "fdiv") -+ (eq_attr "mode" "SF")) -+ "alu") -+ -+(define_insn_reservation "generic_fdiv_double" 36 -+ (and (eq_attr "type" "fdiv") -+ (eq_attr "mode" "DF")) -+ "alu") -+ -+(define_insn_reservation "generic_fsqrt_single" 54 -+ (and (eq_attr "type" "fsqrt") -+ (eq_attr "mode" "SF")) -+ "alu") -+ -+(define_insn_reservation "generic_fsqrt_double" 112 -+ (and (eq_attr "type" "fsqrt") -+ (eq_attr "mode" "DF")) -+ "alu") -diff --git a/gcc-4.6.1/gcc/config/riscv/linux-unwind.h b/gcc-4.6.1/gcc/config/riscv/linux-unwind.h -new file mode 100644 -index 0000000..2650d61 ---- /dev/null -+++ gcc-4.6.1/gcc/config/riscv/linux-unwind.h -@@ -0,0 +1,50 @@ -+/* DWARF2 EH unwinding support for RISC-V Linux. -+ Copyright (C) 2014 Free Software Foundation, Inc. -+ -+This file is part of GCC. -+ -+GCC is free software; you can redistribute it and/or modify -+it under the terms of the GNU General Public License as published by -+the Free Software Foundation; either version 3, or (at your option) -+any later version. -+ -+GCC is distributed in the hope that it will be useful, -+but WITHOUT ANY WARRANTY; without even the implied warranty of -+MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -+GNU General Public License for more details. -+ -+Under Section 7 of GPL version 3, you are granted additional -+permissions described in the GCC Runtime Library Exception, version -+3.1, as published by the Free Software Foundation. -+ -+You should have received a copy of the GNU General Public License and -+a copy of the GCC Runtime Library Exception along with this program; -+see the files COPYING3 and COPYING.RUNTIME respectively. If not, see -+. */ -+ -+#ifndef inhibit_libc -+/* Examine the code and attempt to identify a signal frame. */ -+ -+#include -+#include -+ -+#define MD_FALLBACK_FRAME_STATE_FOR riscv_fallback_frame_state -+ -+static _Unwind_Reason_Code -+riscv_fallback_frame_state (struct _Unwind_Context *context, -+ _Unwind_FrameState *fs) -+{ -+ unsigned int *pc = (unsigned int *) context->ra; -+ -+ /* Signal frames begin with the following code sequence: -+ li v0, __NR_rt_sigreturn -+ scall */ -+ if (((unsigned long)pc & 0x3) != 0 -+ || pc[0] != RISCV_ITYPE (ADDI, GP_RETURN, 0, __NR_rt_sigreturn) -+ || pc[1] != RISCV_ITYPE (SCALL, 0, 0, 0)) -+ return _URC_END_OF_STACK; -+ -+ /* TODO: Actually implement this. */ -+ abort(); -+} -+#endif -diff --git a/gcc-4.6.1/gcc/config/riscv/linux.h b/gcc-4.6.1/gcc/config/riscv/linux.h -new file mode 100644 -index 0000000..afbe2f7 ---- /dev/null -+++ gcc-4.6.1/gcc/config/riscv/linux.h -@@ -0,0 +1,65 @@ -+/* Definitions for MIPS running Linux-based GNU systems with ELF format. -+ Copyright (C) 1998, 1999, 2000, 2001, 2002, 2003, 2004, 2005, 2006, -+ 2007, 2008, 2010, 2011 Free Software Foundation, Inc. -+ -+This file is part of GCC. -+ -+GCC is free software; you can redistribute it and/or modify -+it under the terms of the GNU General Public License as published by -+the Free Software Foundation; either version 3, or (at your option) -+any later version. -+ -+GCC is distributed in the hope that it will be useful, -+but WITHOUT ANY WARRANTY; without even the implied warranty of -+MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -+GNU General Public License for more details. -+ -+You should have received a copy of the GNU General Public License -+along with GCC; see the file COPYING3. If not see -+. */ -+ -+#undef WCHAR_TYPE -+#define WCHAR_TYPE "int" -+ -+#undef WCHAR_TYPE_SIZE -+#define WCHAR_TYPE_SIZE 32 -+ -+#undef TARGET_VERSION -+#define TARGET_VERSION fprintf (stderr, " (RISC-V Linux/ELF)"); -+ -+#define TARGET_OS_CPP_BUILTINS() \ -+ do { \ -+ LINUX_TARGET_OS_CPP_BUILTINS(); \ -+ /* The GNU C++ standard library requires this. */ \ -+ if (c_dialect_cxx ()) \ -+ builtin_define ("_GNU_SOURCE"); \ -+ } while (0) -+ -+#undef SUBTARGET_CPP_SPEC -+#define SUBTARGET_CPP_SPEC "%{posix:-D_POSIX_SOURCE} %{pthread:-D_REENTRANT}" -+ -+#define GLIBC_DYNAMIC_LINKER "/lib/ld.so.1" -+ -+/* Borrowed from sparc/linux.h */ -+#undef LINK_SPEC -+#define LINK_SPEC \ -+ "%{shared:-shared} \ -+ %{!shared: \ -+ %{!static: \ -+ %{rdynamic:-export-dynamic} \ -+ -dynamic-linker " LINUX_DYNAMIC_LINKER "} \ -+ %{static:-static}}" -+ -+#undef LIB_SPEC -+#define LIB_SPEC "\ -+%{pthread:-lpthread} \ -+%{shared:-lc} \ -+%{!shared: \ -+ %{profile:-lc_p} %{!profile:-lc}}" -+ -+#define MD_UNWIND_SUPPORT "config/riscv/linux-unwind.h" -+ -+/* Similar to standard Linux, but adding -ffast-math support. */ -+#undef ENDFILE_SPEC -+#define ENDFILE_SPEC \ -+ "%{shared|pie:crtendS.o%s;:crtend.o%s} crtn.o%s" -diff --git a/gcc-4.6.1/gcc/config/riscv/linux64.h b/gcc-4.6.1/gcc/config/riscv/linux64.h -new file mode 100644 -index 0000000..b957214 ---- /dev/null -+++ gcc-4.6.1/gcc/config/riscv/linux64.h -@@ -0,0 +1,44 @@ -+/* Definitions for MIPS running Linux-based GNU systems with ELF format -+ using n32/64 abi. -+ Copyright 2002, 2003, 2004, 2005, 2006, 2007, 2008, 2010, 2011 -+ Free Software Foundation, Inc. -+ -+This file is part of GCC. -+ -+GCC is free software; you can redistribute it and/or modify -+it under the terms of the GNU General Public License as published by -+the Free Software Foundation; either version 3, or (at your option) -+any later version. -+ -+GCC is distributed in the hope that it will be useful, -+but WITHOUT ANY WARRANTY; without even the implied warranty of -+MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -+GNU General Public License for more details. -+ -+You should have received a copy of the GNU General Public License -+along with GCC; see the file COPYING3. If not see -+. */ -+ -+/* Force the default ABI flags onto the command line -+ in order to make the other specs easier to write. */ -+#undef LIB_SPEC -+#define LIB_SPEC "\ -+%{pthread:-lpthread} \ -+%{shared:-lc} \ -+%{!shared: \ -+ %{profile:-lc_p} %{!profile:-lc}}" -+ -+#define GLIBC_DYNAMIC_LINKER32 "/lib32/ld.so.1" -+#define GLIBC_DYNAMIC_LINKER64 "/lib/ld.so.1" -+ -+#undef LINK_SPEC -+#define LINK_SPEC "\ -+%{shared} \ -+ %{!shared: \ -+ %{!static: \ -+ %{rdynamic:-export-dynamic} \ -+ %{" OPT_ARCH64 ": -dynamic-linker " LINUX_DYNAMIC_LINKER64 "} \ -+ %{" OPT_ARCH32 ": -dynamic-linker " LINUX_DYNAMIC_LINKER32 "}} \ -+ %{static:-static}} \ -+%{" OPT_ARCH64 ":-melf64lriscv} \ -+%{" OPT_ARCH32 ":-melf32lriscv}" -diff --git a/gcc-4.6.1/gcc/config/riscv/opcode-riscv.h b/gcc-4.6.1/gcc/config/riscv/opcode-riscv.h -new file mode 100644 -index 0000000..012032b ---- /dev/null -+++ gcc-4.6.1/gcc/config/riscv/opcode-riscv.h -@@ -0,0 +1,150 @@ -+/* RISC-V ISA encoding. -+ Copyright (C) 2011-2014 Free Software Foundation, Inc. -+ Contributed by Andrew Waterman (waterman@cs.berkeley.edu) at UC Berkeley. -+ Based on MIPS target for GNU compiler. -+ -+This file is part of GDB, GAS, and the GNU binutils. -+ -+GDB, GAS, and the GNU binutils are free software; you can redistribute -+them and/or modify them under the terms of the GNU General Public -+License as published by the Free Software Foundation; either version -+1, or (at your option) any later version. -+ -+GDB, GAS, and the GNU binutils are distributed in the hope that they -+will be useful, but WITHOUT ANY WARRANTY; without even the implied -+warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See -+the GNU General Public License for more details. -+ -+You should have received a copy of the GNU General Public License -+along with this file; see the file COPYING. If not, write to the Free -+Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA. */ -+ -+#ifndef _RISCV_H_ -+#define _RISCV_H_ -+ -+#define RV_X(x, s, n) (((x) >> (s)) & ((1<<(n))-1)) -+#define RV_IMM_SIGN(x) (-(((x) >> 31) & 1)) -+ -+#define EXTRACT_ITYPE_IMM(x) \ -+ (RV_X(x, 20, 12) | (RV_IMM_SIGN(x) << 12)) -+#define EXTRACT_STYPE_IMM(x) \ -+ (RV_X(x, 7, 5) | (RV_X(x, 25, 7) << 5) | (RV_IMM_SIGN(x) << 12)) -+#define EXTRACT_SBTYPE_IMM(x) \ -+ ((RV_X(x, 8, 4) << 1) | (RV_X(x, 25, 6) << 5) | (RV_X(x, 7, 1) << 11) | (RV_IMM_SIGN(x) << 12)) -+#define EXTRACT_UTYPE_IMM(x) \ -+ (RV_X(x, 12, 20) | (RV_IMM_SIGN(x) << 20)) -+#define EXTRACT_UJTYPE_IMM(x) \ -+ ((RV_X(x, 21, 10) << 1) | (RV_X(x, 20, 1) << 11) | (RV_X(x, 12, 8) << 12) | (RV_IMM_SIGN(x) << 20)) -+ -+#define ENCODE_ITYPE_IMM(x) \ -+ (RV_X(x, 0, 12) << 20) -+#define ENCODE_STYPE_IMM(x) \ -+ ((RV_X(x, 0, 5) << 7) | (RV_X(x, 5, 7) << 25)) -+#define ENCODE_SBTYPE_IMM(x) \ -+ ((RV_X(x, 1, 4) << 8) | (RV_X(x, 5, 6) << 25) | (RV_X(x, 11, 1) << 7) | (RV_X(x, 12, 1) << 31)) -+#define ENCODE_UTYPE_IMM(x) \ -+ (RV_X(x, 0, 20) << 12) -+#define ENCODE_UJTYPE_IMM(x) \ -+ ((RV_X(x, 1, 10) << 21) | (RV_X(x, 11, 1) << 20) | (RV_X(x, 12, 8) << 12) | (RV_X(x, 20, 1) << 31)) -+ -+#define VALID_ITYPE_IMM(x) (EXTRACT_ITYPE_IMM(ENCODE_ITYPE_IMM(x)) == (x)) -+#define VALID_STYPE_IMM(x) (EXTRACT_STYPE_IMM(ENCODE_STYPE_IMM(x)) == (x)) -+#define VALID_SBTYPE_IMM(x) (EXTRACT_SBTYPE_IMM(ENCODE_SBTYPE_IMM(x)) == (x)) -+#define VALID_UTYPE_IMM(x) (EXTRACT_UTYPE_IMM(ENCODE_UTYPE_IMM(x)) == (x)) -+#define VALID_UJTYPE_IMM(x) (EXTRACT_UJTYPE_IMM(ENCODE_UJTYPE_IMM(x)) == (x)) -+ -+#define RISCV_RTYPE(insn, rd, rs1, rs2) \ -+ ((MATCH_ ## insn) | ((rd) << OP_SH_RD) | ((rs1) << OP_SH_RS1) | ((rs2) << OP_SH_RS2)) -+#define RISCV_ITYPE(insn, rd, rs1, imm) \ -+ ((MATCH_ ## insn) | ((rd) << OP_SH_RD) | ((rs1) << OP_SH_RS1) | ENCODE_ITYPE_IMM(imm)) -+#define RISCV_STYPE(insn, rs1, rs2, imm) \ -+ ((MATCH_ ## insn) | ((rs1) << OP_SH_RS1) | ((rs2) << OP_SH_RS2) | ENCODE_STYPE_IMM(imm)) -+#define RISCV_SBTYPE(insn, rs1, rs2, target) \ -+ ((MATCH_ ## insn) | ((rs1) << OP_SH_RS1) | ((rs2) << OP_SH_RS2) | ENCODE_SBTYPE_IMM(target)) -+#define RISCV_UTYPE(insn, rd, bigimm) \ -+ ((MATCH_ ## insn) | ((rd) << OP_SH_RD) | ENCODE_UTYPE_IMM(bigimm)) -+#define RISCV_UJTYPE(insn, rd, target) \ -+ ((MATCH_ ## insn) | ((rd) << OP_SH_RD) | ENCODE_UJTYPE_IMM(target)) -+ -+#define RISCV_NOP RISCV_ITYPE(ADDI, 0, 0, 0) -+ -+#define RISCV_CONST_HIGH_PART(VALUE) \ -+ (((VALUE) + (RISCV_IMM_REACH/2)) & ~(RISCV_IMM_REACH-1)) -+#define RISCV_CONST_LOW_PART(VALUE) ((VALUE) - RISCV_CONST_HIGH_PART (VALUE)) -+#define RISCV_LUI_HIGH_PART(VALUE) (RISCV_CONST_HIGH_PART(VALUE) >> RISCV_IMM_BITS) -+ -+/* RV fields */ -+ -+#define OP_MASK_OP 0x7f -+#define OP_SH_OP 0 -+#define OP_MASK_RS2 0x1f -+#define OP_SH_RS2 20 -+#define OP_MASK_RS1 0x1f -+#define OP_SH_RS1 15 -+#define OP_MASK_RS3 0x1f -+#define OP_SH_RS3 27 -+#define OP_MASK_RD 0x1f -+#define OP_SH_RD 7 -+#define OP_MASK_SHAMT 0x3f -+#define OP_SH_SHAMT 20 -+#define OP_MASK_SHAMTW 0x1f -+#define OP_SH_SHAMTW 20 -+#define OP_MASK_RM 0x7 -+#define OP_SH_RM 12 -+#define OP_MASK_PRED 0xf -+#define OP_SH_PRED 24 -+#define OP_MASK_SUCC 0xf -+#define OP_SH_SUCC 20 -+#define OP_MASK_AQ 0x1 -+#define OP_SH_AQ 26 -+#define OP_MASK_RL 0x1 -+#define OP_SH_RL 25 -+ -+#define OP_MASK_VRD 0x1f -+#define OP_SH_VRD 7 -+#define OP_MASK_VRS 0x1f -+#define OP_SH_VRS 15 -+#define OP_MASK_VRT 0x1f -+#define OP_SH_VRT 20 -+#define OP_MASK_VRR 0x1f -+#define OP_SH_VRR 25 -+ -+#define OP_MASK_VFD 0x1f -+#define OP_SH_VFD 7 -+#define OP_MASK_VFS 0x1f -+#define OP_SH_VFS 15 -+#define OP_MASK_VFT 0x1f -+#define OP_SH_VFT 20 -+#define OP_MASK_VFR 0x1f -+#define OP_SH_VFR 25 -+ -+#define OP_MASK_IMMNGPR 0x3f -+#define OP_SH_IMMNGPR 20 -+#define OP_MASK_IMMNFPR 0x3f -+#define OP_SH_IMMNFPR 26 -+#define OP_MASK_IMMSEGNELM 0x1f -+#define OP_SH_IMMSEGNELM 17 -+#define OP_MASK_IMMSEGSTNELM 0x1f -+#define OP_SH_IMMSEGSTNELM 12 -+#define OP_MASK_CUSTOM_IMM 0x7f -+#define OP_SH_CUSTOM_IMM 25 -+ -+#define LINK_REG 1 -+ -+#define RISCV_JUMP_BITS RISCV_BIGIMM_BITS -+#define RISCV_JUMP_ALIGN_BITS 1 -+#define RISCV_JUMP_ALIGN (1 << RISCV_JUMP_ALIGN_BITS) -+#define RISCV_JUMP_REACH ((1ULL< SI optimizations -+;;........................ -+ -+;; Simplify (int)(a + 1), etc. -+(define_peephole2 -+ [(set (match_operand:DI 0 "register_operand") -+ (match_operator:DI 4 "modular_operator" -+ [(match_operand:DI 1 "register_operand") -+ (match_operand:DI 2 "arith_operand")])) -+ (set (match_operand:SI 3 "register_operand") -+ (truncate:SI (match_dup 0)))] -+ "TARGET_64BIT && (REGNO (operands[0]) == REGNO (operands[3]) || peep2_reg_dead_p (2, operands[0]))" -+ [(set (match_dup 3) -+ (truncate:SI -+ (match_op_dup:DI 4 -+ [(match_operand:DI 1 "register_operand") -+ (match_operand:DI 2 "arith_operand")])))]) -+ -+;; Simplify (int)a + 1, etc. -+(define_peephole2 -+ [(set (match_operand:SI 0 "register_operand") -+ (truncate:SI (match_operand:DI 1 "register_operand"))) -+ (set (match_operand:SI 3 "register_operand") -+ (match_operator:SI 4 "modular_operator" -+ [(match_dup 0) -+ (match_operand:SI 2 "arith_operand")]))] -+ "TARGET_64BIT && (REGNO (operands[0]) == REGNO (operands[3]) || peep2_reg_dead_p (2, operands[0]))" -+ [(set (match_dup 3) -+ (match_op_dup:SI 4 [(match_dup 1) (match_dup 2)]))]) -+ -+;; Simplify -(int)a, etc. -+(define_peephole2 -+ [(set (match_operand:SI 0 "register_operand") -+ (truncate:SI (match_operand:DI 2 "register_operand"))) -+ (set (match_operand:SI 3 "register_operand") -+ (match_operator:SI 4 "modular_operator" -+ [(match_operand:SI 1 "reg_or_0_operand") -+ (match_dup 0)]))] -+ "TARGET_64BIT && (REGNO (operands[0]) == REGNO (operands[3]) || peep2_reg_dead_p (2, operands[0]))" -+ [(set (match_dup 3) -+ (match_op_dup:SI 4 [(match_dup 1) (match_dup 2)]))]) -+ -+;; Simplify PIC loads to static variables. -+(define_peephole2 -+ [(set (match_operand:P 0 "register_operand") -+ (match_operand:P 1 "absolute_symbolic_operand")) -+ (set (match_operand:ANYI 2 "register_operand") -+ (mem:ANYI (match_dup 0)))] -+ "(flag_pic && SYMBOL_REF_LOCAL_P (operands[1])) && (REGNO (operands[0]) == REGNO (operands[2]) || peep2_reg_dead_p (2, operands[0]))" -+ [(set (match_dup 2) (mem:ANYI (match_dup 1)))]) -+(define_peephole2 -+ [(set (match_operand:P 0 "register_operand") -+ (match_operand:P 1 "absolute_symbolic_operand")) -+ (set (match_operand:ANYF 2 "register_operand") -+ (mem:ANYF (match_dup 0)))] -+ "(flag_pic && SYMBOL_REF_LOCAL_P (operands[1])) && peep2_reg_dead_p (2, operands[0])" -+ [(set (match_dup 2) (mem:ANYF (match_dup 1))) -+ (clobber (match_dup 0))]) -+(define_peephole2 -+ [(set (match_operand:DI 0 "register_operand") -+ (match_operand:DI 1 "absolute_symbolic_operand")) -+ (set (mem:ANYIF (match_dup 0)) -+ (match_operand:ANYIF 2 "reg_or_0_operand"))] -+ "TARGET_64BIT && (flag_pic && SYMBOL_REF_LOCAL_P (operands[1])) && peep2_reg_dead_p (2, operands[0])" -+ [(set (mem:ANYIF (match_dup 1)) (match_dup 2)) -+ (clobber (match_dup 0))]) -+(define_peephole2 -+ [(set (match_operand:SI 0 "reg_or_0_operand") -+ (match_operand:SI 1 "absolute_symbolic_operand")) -+ (set (mem:ANYIF (match_dup 0)) -+ (match_operand:ANYIF 2 "register_operand"))] -+ "!TARGET_64BIT && (flag_pic && SYMBOL_REF_LOCAL_P (operands[1])) && peep2_reg_dead_p (2, operands[0])" -+ [(set (mem:ANYIF (match_dup 1)) (match_dup 2)) -+ (clobber (match_dup 0))]) -+(define_insn "*local_pic_load" -+ [(set (match_operand:ANYI 0 "register_operand" "=r") -+ (mem:ANYI (match_operand 1 "absolute_symbolic_operand" "")))] -+ "flag_pic && SYMBOL_REF_LOCAL_P (operands[1])" -+ "\t%0,%1" -+ [(set (attr "length") (const_int 8))]) -+(define_insn "*local_pic_load" -+ [(set (match_operand:ANYF 0 "register_operand" "=f") -+ (mem:ANYF (match_operand 1 "absolute_symbolic_operand" ""))) -+ (clobber (match_scratch:DI 2 "=&r"))] -+ "flag_pic && SYMBOL_REF_LOCAL_P (operands[1])" -+ "\t%0,%1,%2" -+ [(set (attr "length") (const_int 8))]) -+(define_insn "*local_pic_loadu" -+ [(set (match_operand:SUPERQI 0 "register_operand" "=r") -+ (zero_extend:SUPERQI (mem:SUBDI (match_operand 1 "absolute_symbolic_operand" ""))))] -+ "flag_pic && SYMBOL_REF_LOCAL_P (operands[1])" -+ "u\t%0,%1" -+ [(set (attr "length") (const_int 8))]) -+(define_insn "*local_pic_storedi" -+ [(set (mem:ANYI (match_operand 0 "absolute_symbolic_operand" "")) -+ (match_operand:ANYI 1 "reg_or_0_operand" "rJ")) -+ (clobber (match_scratch:DI 2 "=&r"))] -+ "TARGET_64BIT && (flag_pic && SYMBOL_REF_LOCAL_P (operands[0]))" -+ "\t%z1,%0,%2" -+ [(set (attr "length") (const_int 8))]) -+(define_insn "*local_pic_storesi" -+ [(set (mem:ANYI (match_operand 0 "absolute_symbolic_operand" "")) -+ (match_operand:ANYI 1 "reg_or_0_operand" "rJ")) -+ (clobber (match_scratch:SI 2 "=&r"))] -+ "!TARGET_64BIT && (flag_pic && SYMBOL_REF_LOCAL_P (operands[0]))" -+ "\t%z1,%0,%2" -+ [(set (attr "length") (const_int 8))]) -+(define_insn "*local_pic_storedi" -+ [(set (mem:ANYF (match_operand 0 "absolute_symbolic_operand" "")) -+ (match_operand:ANYF 1 "register_operand" "f")) -+ (clobber (match_scratch:DI 2 "=&r"))] -+ "TARGET_64BIT && (flag_pic && SYMBOL_REF_LOCAL_P (operands[0]))" -+ "\t%1,%0,%2" -+ [(set (attr "length") (const_int 8))]) -+(define_insn "*local_pic_storesi" -+ [(set (mem:ANYF (match_operand 0 "absolute_symbolic_operand" "")) -+ (match_operand:ANYF 1 "register_operand" "f")) -+ (clobber (match_scratch:SI 2 "=&r"))] -+ "!TARGET_64BIT && (flag_pic && SYMBOL_REF_LOCAL_P (operands[0]))" -+ "\t%1,%0,%2" -+ [(set (attr "length") (const_int 8))]) -diff --git a/gcc-4.6.1/gcc/config/riscv/predicates.md b/gcc-4.6.1/gcc/config/riscv/predicates.md -new file mode 100644 -index 0000000..f7a92c0 ---- /dev/null -+++ gcc-4.6.1/gcc/config/riscv/predicates.md -@@ -0,0 +1,182 @@ -+;; Predicate description for RISC-V target. -+;; Copyright (C) 2011-2014 Free Software Foundation, Inc. -+;; Contributed by Andrew Waterman (waterman@cs.berkeley.edu) at UC Berkeley. -+;; Based on MIPS target for GNU compiler. -+;; -+;; This file is part of GCC. -+;; -+;; GCC is free software; you can redistribute it and/or modify -+;; it under the terms of the GNU General Public License as published by -+;; the Free Software Foundation; either version 3, or (at your option) -+;; any later version. -+;; -+;; GCC is distributed in the hope that it will be useful, -+;; but WITHOUT ANY WARRANTY; without even the implied warranty of -+;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -+;; GNU General Public License for more details. -+;; -+;; You should have received a copy of the GNU General Public License -+;; along with GCC; see the file COPYING3. If not see -+;; . -+ -+(define_predicate "const_arith_operand" -+ (and (match_code "const_int") -+ (match_test "SMALL_OPERAND (INTVAL (op))"))) -+ -+(define_predicate "arith_operand" -+ (ior (match_operand 0 "const_arith_operand") -+ (match_operand 0 "register_operand"))) -+ -+(define_predicate "sle_operand" -+ (and (match_code "const_int") -+ (match_test "SMALL_OPERAND (INTVAL (op) + 1)"))) -+ -+(define_predicate "sleu_operand" -+ (and (match_operand 0 "sle_operand") -+ (match_test "INTVAL (op) + 1 != 0"))) -+ -+(define_predicate "const_0_operand" -+ (and (match_code "const_int,const_double,const_vector") -+ (match_test "op == CONST0_RTX (GET_MODE (op))"))) -+ -+(define_predicate "reg_or_0_operand" -+ (ior (match_operand 0 "const_0_operand") -+ (match_operand 0 "register_operand"))) -+ -+(define_predicate "const_1_operand" -+ (and (match_code "const_int,const_double,const_vector") -+ (match_test "op == CONST1_RTX (GET_MODE (op))"))) -+ -+(define_predicate "reg_or_1_operand" -+ (ior (match_operand 0 "const_1_operand") -+ (match_operand 0 "register_operand"))) -+ -+;; This is used for indexing into vectors, and hence only accepts const_int. -+(define_predicate "const_0_or_1_operand" -+ (and (match_code "const_int") -+ (ior (match_test "op == CONST0_RTX (GET_MODE (op))") -+ (match_test "op == CONST1_RTX (GET_MODE (op))")))) -+ -+(define_special_predicate "pc_or_label_operand" -+ (match_code "pc,label_ref")) -+ -+;; A legitimate CONST_INT operand that takes more than one instruction -+;; to load. -+(define_predicate "splittable_const_int_operand" -+ (match_code "const_int") -+{ -+ /* Don't handle multi-word moves this way; we don't want to introduce -+ the individual word-mode moves until after reload. */ -+ if (GET_MODE_SIZE (mode) > UNITS_PER_WORD) -+ return false; -+ -+ /* Otherwise check whether the constant can be loaded in a single -+ instruction. */ -+ return !LUI_INT (op) && !SMALL_INT (op); -+}) -+ -+(define_predicate "move_operand" -+ (match_operand 0 "general_operand") -+{ -+ enum mips_symbol_type symbol_type; -+ -+ /* The thinking here is as follows: -+ -+ (1) The move expanders should split complex load sequences into -+ individual instructions. Those individual instructions can -+ then be optimized by all rtl passes. -+ -+ (2) The target of pre-reload load sequences should not be used -+ to store temporary results. If the target register is only -+ assigned one value, reload can rematerialize that value -+ on demand, rather than spill it to the stack. -+ -+ (3) If we allowed pre-reload passes like combine and cse to recreate -+ complex load sequences, we would want to be able to split the -+ sequences before reload as well, so that the pre-reload scheduler -+ can see the individual instructions. This falls foul of (2); -+ the splitter would be forced to reuse the target register for -+ intermediate results. -+ -+ (4) We want to define complex load splitters for combine. These -+ splitters can request a temporary scratch register, which avoids -+ the problem in (2). They allow things like: -+ -+ (set (reg T1) (high SYM)) -+ (set (reg T2) (low (reg T1) SYM)) -+ (set (reg X) (plus (reg T2) (const_int OFFSET))) -+ -+ to be combined into: -+ -+ (set (reg T3) (high SYM+OFFSET)) -+ (set (reg X) (lo_sum (reg T3) SYM+OFFSET)) -+ -+ if T2 is only used this once. */ -+ switch (GET_CODE (op)) -+ { -+ case CONST_INT: -+ return !splittable_const_int_operand (op, mode); -+ -+ case CONST: -+ case SYMBOL_REF: -+ case LABEL_REF: -+ return (mips_symbolic_constant_p (op, &symbol_type) -+ && !riscv_hi_relocs[symbol_type]); -+ -+ case HIGH: -+ op = XEXP (op, 0); -+ return mips_symbolic_constant_p (op, &symbol_type); -+ -+ default: -+ return true; -+ } -+}) -+ -+(define_predicate "consttable_operand" -+ (match_test "CONSTANT_P (op)")) -+ -+(define_predicate "symbolic_operand" -+ (match_code "const,symbol_ref,label_ref") -+{ -+ enum mips_symbol_type type; -+ return mips_symbolic_constant_p (op, &type); -+}) -+ -+(define_predicate "absolute_symbolic_operand" -+ (match_code "const,symbol_ref,label_ref") -+{ -+ enum mips_symbol_type type; -+ return (mips_symbolic_constant_p (op, &type) -+ && type == SYMBOL_ABSOLUTE); -+}) -+ -+(define_predicate "plt_symbolic_operand" -+ (match_code "const,symbol_ref,label_ref") -+{ -+ enum mips_symbol_type type; -+ return (mips_symbolic_constant_p (op, &type) -+ && type == SYMBOL_GOT_DISP && !SYMBOL_REF_WEAK (op) && TARGET_PLT); -+}) -+ -+(define_predicate "call_insn_operand" -+ (ior (match_operand 0 "absolute_symbolic_operand") -+ (match_operand 0 "plt_symbolic_operand") -+ (match_operand 0 "register_operand"))) -+ -+(define_predicate "symbol_ref_operand" -+ (match_code "symbol_ref")) -+ -+(define_predicate "modular_operator" -+ (match_code "plus,minus,mult,ashift")) -+ -+(define_predicate "equality_operator" -+ (match_code "eq,ne")) -+ -+(define_predicate "order_operator" -+ (match_code "eq,ne,lt,ltu,le,leu,ge,geu,gt,gtu")) -+ -+(define_predicate "fp_order_operator" -+ (match_code "eq,lt,le,gt,ge")) -+ -+(define_predicate "fp_unorder_operator" -+ (match_code "ordered,unordered")) -diff --git a/gcc-4.6.1/gcc/config/riscv/riscv-fp.c b/gcc-4.6.1/gcc/config/riscv/riscv-fp.c -new file mode 100644 -index 0000000..ef3ae86 ---- /dev/null -+++ gcc-4.6.1/gcc/config/riscv/riscv-fp.c -@@ -0,0 +1,178 @@ -+/* Functions needed for soft-float on riscv-linux. Based on -+ rs6000/ppc64-fp.c with TF types removed. -+ -+ Copyright (C) 1989, 1992, 1993, 1994, 1995, 1996, 1997, 1998, 1999, -+ 2000, 2001, 2002, 2003, 2004, 2006, 2009 Free Software Foundation, -+ Inc. -+ -+This file is part of GCC. -+ -+GCC is free software; you can redistribute it and/or modify it under -+the terms of the GNU General Public License as published by the Free -+Software Foundation; either version 3, or (at your option) any later -+version. -+ -+GCC is distributed in the hope that it will be useful, but WITHOUT ANY -+WARRANTY; without even the implied warranty of MERCHANTABILITY or -+FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License -+for more details. -+ -+Under Section 7 of GPL version 3, you are granted additional -+permissions described in the GCC Runtime Library Exception, version -+3.1, as published by the Free Software Foundation. -+ -+You should have received a copy of the GNU General Public License and -+a copy of the GCC Runtime Library Exception along with this program; -+see the files COPYING3 and COPYING.RUNTIME respectively. If not, see -+. */ -+ -+#if defined(__riscv64) -+#include "config/fp-bit.h" -+ -+extern DItype __fixdfdi (DFtype); -+extern DItype __fixsfdi (SFtype); -+extern USItype __fixunsdfsi (DFtype); -+extern USItype __fixunssfsi (SFtype); -+extern DFtype __floatdidf (DItype); -+extern DFtype __floatundidf (UDItype); -+extern SFtype __floatdisf (DItype); -+extern SFtype __floatundisf (UDItype); -+ -+static DItype local_fixunssfdi (SFtype); -+static DItype local_fixunsdfdi (DFtype); -+ -+DItype -+__fixdfdi (DFtype a) -+{ -+ if (a < 0) -+ return - local_fixunsdfdi (-a); -+ return local_fixunsdfdi (a); -+} -+ -+DItype -+__fixsfdi (SFtype a) -+{ -+ if (a < 0) -+ return - local_fixunssfdi (-a); -+ return local_fixunssfdi (a); -+} -+ -+USItype -+__fixunsdfsi (DFtype a) -+{ -+ if (a >= - (DFtype) (- ((SItype)(((USItype)1 << ((4 * 8) - 1)) - 1)) - 1)) -+ return (SItype) (a + (- ((SItype)(((USItype)1 << ((4 * 8) - 1)) - 1)) - 1)) -+ - (- ((SItype)(((USItype)1 << ((4 * 8) - 1)) - 1)) - 1); -+ return (SItype) a; -+} -+ -+USItype -+__fixunssfsi (SFtype a) -+{ -+ if (a >= - (SFtype) (- ((SItype)(((USItype)1 << ((4 * 8) - 1)) - 1)) - 1)) -+ return (SItype) (a + (- ((SItype)(((USItype)1 << ((4 * 8) - 1)) - 1)) - 1)) -+ - (- ((SItype)(((USItype)1 << ((4 * 8) - 1)) - 1)) - 1); -+ return (SItype) a; -+} -+ -+DFtype -+__floatdidf (DItype u) -+{ -+ DFtype d; -+ -+ d = (SItype) (u >> (sizeof (SItype) * 8)); -+ d *= 2.0 * (((UDItype) 1) << ((sizeof (SItype) * 8) - 1)); -+ d += (USItype) (u & ((((UDItype) 1) << (sizeof (SItype) * 8)) - 1)); -+ -+ return d; -+} -+ -+DFtype -+__floatundidf (UDItype u) -+{ -+ DFtype d; -+ -+ d = (USItype) (u >> (sizeof (SItype) * 8)); -+ d *= 2.0 * (((UDItype) 1) << ((sizeof (SItype) * 8) - 1)); -+ d += (USItype) (u & ((((UDItype) 1) << (sizeof (SItype) * 8)) - 1)); -+ -+ return d; -+} -+ -+SFtype -+__floatdisf (DItype u) -+{ -+ DFtype f; -+ -+ if (53 < (sizeof (DItype) * 8) -+ && 53 > ((sizeof (DItype) * 8) - 53 + 24)) -+ { -+ if (! (- ((DItype) 1 << 53) < u -+ && u < ((DItype) 1 << 53))) -+ { -+ if ((UDItype) u & (((UDItype) 1 << ((sizeof (DItype) * 8) - 53)) - 1)) -+ { -+ u &= ~ (((UDItype) 1 << ((sizeof (DItype) * 8) - 53)) - 1); -+ u |= ((UDItype) 1 << ((sizeof (DItype) * 8) - 53)); -+ } -+ } -+ } -+ f = (SItype) (u >> (sizeof (SItype) * 8)); -+ f *= 2.0 * (((UDItype) 1) << ((sizeof (SItype) * 8) - 1)); -+ f += (USItype) (u & ((((UDItype) 1) << (sizeof (SItype) * 8)) - 1)); -+ -+ return (SFtype) f; -+} -+ -+SFtype -+__floatundisf (UDItype u) -+{ -+ DFtype f; -+ -+ if (53 < (sizeof (DItype) * 8) -+ && 53 > ((sizeof (DItype) * 8) - 53 + 24)) -+ { -+ if (u >= ((UDItype) 1 << 53)) -+ { -+ if ((UDItype) u & (((UDItype) 1 << ((sizeof (DItype) * 8) - 53)) - 1)) -+ { -+ u &= ~ (((UDItype) 1 << ((sizeof (DItype) * 8) - 53)) - 1); -+ u |= ((UDItype) 1 << ((sizeof (DItype) * 8) - 53)); -+ } -+ } -+ } -+ f = (USItype) (u >> (sizeof (SItype) * 8)); -+ f *= 2.0 * (((UDItype) 1) << ((sizeof (SItype) * 8) - 1)); -+ f += (USItype) (u & ((((UDItype) 1) << (sizeof (SItype) * 8)) - 1)); -+ -+ return (SFtype) f; -+} -+ -+/* This version is needed to prevent recursion; fixunsdfdi in libgcc -+ calls fixdfdi, which in turn calls calls fixunsdfdi. */ -+ -+static DItype -+local_fixunsdfdi (DFtype a) -+{ -+ USItype hi, lo; -+ -+ hi = a / (((UDItype) 1) << (sizeof (SItype) * 8)); -+ lo = (a - ((DFtype) hi) * (((UDItype) 1) << (sizeof (SItype) * 8))); -+ return ((UDItype) hi << (sizeof (SItype) * 8)) | lo; -+} -+ -+/* This version is needed to prevent recursion; fixunssfdi in libgcc -+ calls fixsfdi, which in turn calls calls fixunssfdi. */ -+ -+static DItype -+local_fixunssfdi (SFtype original_a) -+{ -+ DFtype a = original_a; -+ USItype hi, lo; -+ -+ hi = a / (((UDItype) 1) << (sizeof (SItype) * 8)); -+ lo = (a - ((DFtype) hi) * (((UDItype) 1) << (sizeof (SItype) * 8))); -+ return ((UDItype) hi << (sizeof (SItype) * 8)) | lo; -+} -+ -+#endif -diff --git a/gcc-4.6.1/gcc/config/riscv/riscv-ftypes.def b/gcc-4.6.1/gcc/config/riscv/riscv-ftypes.def -new file mode 100644 -index 0000000..96a38f1 ---- /dev/null -+++ gcc-4.6.1/gcc/config/riscv/riscv-ftypes.def -@@ -0,0 +1,39 @@ -+/* Definitions of prototypes for RISC-V built-in functions. -+ Copyright (C) 2011-2014 Free Software Foundation, Inc. -+ Contributed by Andrew Waterman (waterman@cs.berkeley.edu) at UC Berkeley. -+ Based on MIPS target for GNU compiler. -+ -+This file is part of GCC. -+ -+GCC is free software; you can redistribute it and/or modify -+it under the terms of the GNU General Public License as published by -+the Free Software Foundation; either version 3, or (at your option) -+any later version. -+ -+GCC is distributed in the hope that it will be useful, -+but WITHOUT ANY WARRANTY; without even the implied warranty of -+MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -+GNU General Public License for more details. -+ -+You should have received a copy of the GNU General Public License -+along with GCC; see the file COPYING3. If not see -+. */ -+ -+/* Invoke DEF_RISCV_FTYPE (NARGS, LIST) for each prototype used by -+ MIPS built-in functions, where: -+ -+ NARGS is the number of arguments. -+ LIST contains the return-type code followed by the codes for each -+ argument type. -+ -+ Argument- and return-type codes are either modes or one of the following: -+ -+ VOID for void_type_node -+ INT for integer_type_node -+ POINTER for ptr_type_node -+ -+ (we don't use PTR because that's a ANSI-compatibillity macro). -+ -+ Please keep this list lexicographically sorted by the LIST argument. */ -+ -+DEF_RISCV_FTYPE (1, (VOID, VOID)) -diff --git a/gcc-4.6.1/gcc/config/riscv/riscv-modes.def b/gcc-4.6.1/gcc/config/riscv/riscv-modes.def -new file mode 100644 -index 0000000..bb42344 ---- /dev/null -+++ gcc-4.6.1/gcc/config/riscv/riscv-modes.def -@@ -0,0 +1,26 @@ -+/* Extra machine modes for RISC-V target. -+ Copyright (C) 2011-2014 Free Software Foundation, Inc. -+ Contributed by Andrew Waterman (waterman@cs.berkeley.edu) at UC Berkeley. -+ Based on MIPS target for GNU compiler. -+ -+This file is part of GCC. -+ -+GCC is free software; you can redistribute it and/or modify -+it under the terms of the GNU General Public License as published by -+the Free Software Foundation; either version 3, or (at your option) -+any later version. -+ -+GCC is distributed in the hope that it will be useful, -+but WITHOUT ANY WARRANTY; without even the implied warranty of -+MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -+GNU General Public License for more details. -+ -+You should have received a copy of the GNU General Public License -+along with GCC; see the file COPYING3. If not see -+. */ -+ -+FLOAT_MODE (TF, 16, ieee_quad_format); -+ -+/* Vector modes. */ -+VECTOR_MODES (INT, 4); /* V8QI V4HI V2SI */ -+VECTOR_MODES (FLOAT, 4); /* V4HF V2SF */ -diff --git a/gcc-4.6.1/gcc/config/riscv/riscv-opc.h b/gcc-4.6.1/gcc/config/riscv/riscv-opc.h -new file mode 100644 -index 0000000..eb29d3e ---- /dev/null -+++ gcc-4.6.1/gcc/config/riscv/riscv-opc.h -@@ -0,0 +1,1216 @@ -+/* Automatically generated by parse-opcodes */ -+#ifndef RISCV_ENCODING_H -+#define RISCV_ENCODING_H -+#define MATCH_CUSTOM3_RD_RS1_RS2 0x707b -+#define MASK_CUSTOM3_RD_RS1_RS2 0x707f -+#define MATCH_VLSEGSTWU 0xc00305b -+#define MASK_VLSEGSTWU 0x1e00707f -+#define MATCH_C_LW0 0x12 -+#define MASK_C_LW0 0x801f -+#define MATCH_FMV_D_X 0xf2000053 -+#define MASK_FMV_D_X 0xfff0707f -+#define MATCH_VLH 0x200205b -+#define MASK_VLH 0xfff0707f -+#define MATCH_C_LI 0x0 -+#define MASK_C_LI 0x1f -+#define MATCH_FADD_D 0x2000053 -+#define MASK_FADD_D 0xfe00007f -+#define MATCH_C_LD 0x9 -+#define MASK_C_LD 0x1f -+#define MATCH_VLD 0x600205b -+#define MASK_VLD 0xfff0707f -+#define MATCH_FADD_S 0x53 -+#define MASK_FADD_S 0xfe00007f -+#define MATCH_C_LW 0xa -+#define MASK_C_LW 0x1f -+#define MATCH_VLW 0x400205b -+#define MASK_VLW 0xfff0707f -+#define MATCH_VSSEGSTW 0x400307b -+#define MASK_VSSEGSTW 0x1e00707f -+#define MATCH_UTIDX 0x6077 -+#define MASK_UTIDX 0xfffff07f -+#define MATCH_C_FLW 0x14 -+#define MASK_C_FLW 0x1f -+#define MATCH_FSUB_D 0xa000053 -+#define MASK_FSUB_D 0xfe00007f -+#define MATCH_VSSEGSTD 0x600307b -+#define MASK_VSSEGSTD 0x1e00707f -+#define MATCH_VSSEGSTB 0x307b -+#define MASK_VSSEGSTB 0x1e00707f -+#define MATCH_DIV 0x2004033 -+#define MASK_DIV 0xfe00707f -+#define MATCH_FMV_H_X 0xf4000053 -+#define MASK_FMV_H_X 0xfff0707f -+#define MATCH_C_FLD 0x15 -+#define MASK_C_FLD 0x1f -+#define MATCH_FRRM 0x202073 -+#define MASK_FRRM 0xfffff07f -+#define MATCH_VFMSV_S 0x1000202b -+#define MASK_VFMSV_S 0xfff0707f -+#define MATCH_C_LWSP 0x5 -+#define MASK_C_LWSP 0x1f -+#define MATCH_FENCE 0xf -+#define MASK_FENCE 0x707f -+#define MATCH_FNMSUB_S 0x4b -+#define MASK_FNMSUB_S 0x600007f -+#define MATCH_FLE_S 0xa0000053 -+#define MASK_FLE_S 0xfe00707f -+#define MATCH_FNMSUB_H 0x400004b -+#define MASK_FNMSUB_H 0x600007f -+#define MATCH_FLE_H 0xbc000053 -+#define MASK_FLE_H 0xfe00707f -+#define MATCH_FLW 0x2007 -+#define MASK_FLW 0x707f -+#define MATCH_VSETVL 0x600b -+#define MASK_VSETVL 0xfff0707f -+#define MATCH_VFMSV_D 0x1200202b -+#define MASK_VFMSV_D 0xfff0707f -+#define MATCH_FLE_D 0xa2000053 -+#define MASK_FLE_D 0xfe00707f -+#define MATCH_FENCE_I 0x100f -+#define MASK_FENCE_I 0x707f -+#define MATCH_FNMSUB_D 0x200004b -+#define MASK_FNMSUB_D 0x600007f -+#define MATCH_ADDW 0x3b -+#define MASK_ADDW 0xfe00707f -+#define MATCH_XOR 0x4033 -+#define MASK_XOR 0xfe00707f -+#define MATCH_SUB 0x40000033 -+#define MASK_SUB 0xfe00707f -+#define MATCH_VSSTW 0x400307b -+#define MASK_VSSTW 0xfe00707f -+#define MATCH_VSSTH 0x200307b -+#define MASK_VSSTH 0xfe00707f -+#define MATCH_SC_W 0x1800202f -+#define MASK_SC_W 0xf800707f -+#define MATCH_VSSTB 0x307b -+#define MASK_VSSTB 0xfe00707f -+#define MATCH_VSSTD 0x600307b -+#define MASK_VSSTD 0xfe00707f -+#define MATCH_ADDI 0x13 -+#define MASK_ADDI 0x707f -+#define MATCH_RDTIMEH 0xc8102073 -+#define MASK_RDTIMEH 0xfffff07f -+#define MATCH_MULH 0x2001033 -+#define MASK_MULH 0xfe00707f -+#define MATCH_CSRRSI 0x6073 -+#define MASK_CSRRSI 0x707f -+#define MATCH_FCVT_D_WU 0xd2100053 -+#define MASK_FCVT_D_WU 0xfff0007f -+#define MATCH_MULW 0x200003b -+#define MASK_MULW 0xfe00707f -+#define MATCH_CUSTOM1_RD_RS1_RS2 0x702b -+#define MASK_CUSTOM1_RD_RS1_RS2 0x707f -+#define MATCH_VENQIMM1 0xc00302b -+#define MASK_VENQIMM1 0xfe007fff -+#define MATCH_VENQIMM2 0xe00302b -+#define MASK_VENQIMM2 0xfe007fff -+#define MATCH_RDINSTRET 0xc0202073 -+#define MASK_RDINSTRET 0xfffff07f -+#define MATCH_C_SWSP 0x8 -+#define MASK_C_SWSP 0x1f -+#define MATCH_VLSTW 0x400305b -+#define MASK_VLSTW 0xfe00707f -+#define MATCH_VLSTH 0x200305b -+#define MASK_VLSTH 0xfe00707f -+#define MATCH_VLSTB 0x305b -+#define MASK_VLSTB 0xfe00707f -+#define MATCH_VLSTD 0x600305b -+#define MASK_VLSTD 0xfe00707f -+#define MATCH_ANDI 0x7013 -+#define MASK_ANDI 0x707f -+#define MATCH_FMV_X_S 0xe0000053 -+#define MASK_FMV_X_S 0xfff0707f -+#define MATCH_CUSTOM0_RD_RS1_RS2 0x700b -+#define MASK_CUSTOM0_RD_RS1_RS2 0x707f -+#define MATCH_FNMADD_S 0x4f -+#define MASK_FNMADD_S 0x600007f -+#define MATCH_LWU 0x6003 -+#define MASK_LWU 0x707f -+#define MATCH_CUSTOM0_RS1 0x200b -+#define MASK_CUSTOM0_RS1 0x707f -+#define MATCH_VLSEGSTBU 0x800305b -+#define MASK_VLSEGSTBU 0x1e00707f -+#define MATCH_FNMADD_D 0x200004f -+#define MASK_FNMADD_D 0x600007f -+#define MATCH_FCVT_W_S 0xc0000053 -+#define MASK_FCVT_W_S 0xfff0007f -+#define MATCH_C_SRAI 0x1019 -+#define MASK_C_SRAI 0x1c1f -+#define MATCH_MULHSU 0x2002033 -+#define MASK_MULHSU 0xfe00707f -+#define MATCH_FCVT_D_LU 0xd2300053 -+#define MASK_FCVT_D_LU 0xfff0007f -+#define MATCH_FCVT_W_D 0xc2000053 -+#define MASK_FCVT_W_D 0xfff0007f -+#define MATCH_FSUB_H 0xc000053 -+#define MASK_FSUB_H 0xfe00007f -+#define MATCH_DIVUW 0x200503b -+#define MASK_DIVUW 0xfe00707f -+#define MATCH_SLTI 0x2013 -+#define MASK_SLTI 0x707f -+#define MATCH_VLSTBU 0x800305b -+#define MASK_VLSTBU 0xfe00707f -+#define MATCH_SLTU 0x3033 -+#define MASK_SLTU 0xfe00707f -+#define MATCH_FLH 0x1007 -+#define MASK_FLH 0x707f -+#define MATCH_CUSTOM2_RD_RS1_RS2 0x705b -+#define MASK_CUSTOM2_RD_RS1_RS2 0x707f -+#define MATCH_FLD 0x3007 -+#define MASK_FLD 0x707f -+#define MATCH_FSUB_S 0x8000053 -+#define MASK_FSUB_S 0xfe00007f -+#define MATCH_FCVT_H_LU 0x6c000053 -+#define MASK_FCVT_H_LU 0xfff0007f -+#define MATCH_CUSTOM0 0xb -+#define MASK_CUSTOM0 0x707f -+#define MATCH_CUSTOM1 0x2b -+#define MASK_CUSTOM1 0x707f -+#define MATCH_CUSTOM2 0x5b -+#define MASK_CUSTOM2 0x707f -+#define MATCH_CUSTOM3 0x7b -+#define MASK_CUSTOM3 0x707f -+#define MATCH_VXCPTSAVE 0x302b -+#define MASK_VXCPTSAVE 0xfff07fff -+#define MATCH_VMSV 0x200202b -+#define MASK_VMSV 0xfff0707f -+#define MATCH_FCVT_LU_S 0xc0300053 -+#define MASK_FCVT_LU_S 0xfff0007f -+#define MATCH_AUIPC 0x17 -+#define MASK_AUIPC 0x7f -+#define MATCH_FRFLAGS 0x102073 -+#define MASK_FRFLAGS 0xfffff07f -+#define MATCH_FCVT_LU_D 0xc2300053 -+#define MASK_FCVT_LU_D 0xfff0007f -+#define MATCH_CSRRWI 0x5073 -+#define MASK_CSRRWI 0x707f -+#define MATCH_FADD_H 0x4000053 -+#define MASK_FADD_H 0xfe00007f -+#define MATCH_FSQRT_S 0x58000053 -+#define MASK_FSQRT_S 0xfff0007f -+#define MATCH_VXCPTKILL 0x400302b -+#define MASK_VXCPTKILL 0xffffffff -+#define MATCH_STOP 0x5077 -+#define MASK_STOP 0xffffffff -+#define MATCH_FSGNJN_S 0x20001053 -+#define MASK_FSGNJN_S 0xfe00707f -+#define MATCH_FSGNJN_H 0x34000053 -+#define MASK_FSGNJN_H 0xfe00707f -+#define MATCH_FSQRT_D 0x5a000053 -+#define MASK_FSQRT_D 0xfff0007f -+#define MATCH_XORI 0x4013 -+#define MASK_XORI 0x707f -+#define MATCH_DIVU 0x2005033 -+#define MASK_DIVU 0xfe00707f -+#define MATCH_FSGNJN_D 0x22001053 -+#define MASK_FSGNJN_D 0xfe00707f -+#define MATCH_FSQRT_H 0x24000053 -+#define MASK_FSQRT_H 0xfff0007f -+#define MATCH_VSSEGSTH 0x200307b -+#define MASK_VSSEGSTH 0x1e00707f -+#define MATCH_SW 0x2023 -+#define MASK_SW 0x707f -+#define MATCH_VLSTWU 0xc00305b -+#define MASK_VLSTWU 0xfe00707f -+#define MATCH_VFSSEGW 0x1400207b -+#define MASK_VFSSEGW 0x1ff0707f -+#define MATCH_LHU 0x5003 -+#define MASK_LHU 0x707f -+#define MATCH_SH 0x1023 -+#define MASK_SH 0x707f -+#define MATCH_FMSUB_H 0x4000047 -+#define MASK_FMSUB_H 0x600007f -+#define MATCH_VXCPTAUX 0x200402b -+#define MASK_VXCPTAUX 0xfffff07f -+#define MATCH_FMSUB_D 0x2000047 -+#define MASK_FMSUB_D 0x600007f -+#define MATCH_VFSSEGD 0x1600207b -+#define MASK_VFSSEGD 0x1ff0707f -+#define MATCH_VLSEGHU 0xa00205b -+#define MASK_VLSEGHU 0x1ff0707f -+#define MATCH_MOVN 0x2007077 -+#define MASK_MOVN 0xfe00707f -+#define MATCH_CUSTOM1_RS1 0x202b -+#define MASK_CUSTOM1_RS1 0x707f -+#define MATCH_VLSTHU 0xa00305b -+#define MASK_VLSTHU 0xfe00707f -+#define MATCH_MOVZ 0x7077 -+#define MASK_MOVZ 0xfe00707f -+#define MATCH_CSRRW 0x1073 -+#define MASK_CSRRW 0x707f -+#define MATCH_LD 0x3003 -+#define MASK_LD 0x707f -+#define MATCH_LB 0x3 -+#define MASK_LB 0x707f -+#define MATCH_VLWU 0xc00205b -+#define MASK_VLWU 0xfff0707f -+#define MATCH_LH 0x1003 -+#define MASK_LH 0x707f -+#define MATCH_LW 0x2003 -+#define MASK_LW 0x707f -+#define MATCH_CSRRC 0x3073 -+#define MASK_CSRRC 0x707f -+#define MATCH_FCVT_LU_H 0x4c000053 -+#define MASK_FCVT_LU_H 0xfff0007f -+#define MATCH_FCVT_S_D 0x40100053 -+#define MASK_FCVT_S_D 0xfff0007f -+#define MATCH_BGEU 0x7063 -+#define MASK_BGEU 0x707f -+#define MATCH_VFLSTD 0x1600305b -+#define MASK_VFLSTD 0xfe00707f -+#define MATCH_FCVT_S_L 0xd0200053 -+#define MASK_FCVT_S_L 0xfff0007f -+#define MATCH_FCVT_S_H 0x84000053 -+#define MASK_FCVT_S_H 0xfff0007f -+#define MATCH_FSCSR 0x301073 -+#define MASK_FSCSR 0xfff0707f -+#define MATCH_FCVT_S_W 0xd0000053 -+#define MASK_FCVT_S_W 0xfff0007f -+#define MATCH_VFLSTW 0x1400305b -+#define MASK_VFLSTW 0xfe00707f -+#define MATCH_VXCPTEVAC 0x600302b -+#define MASK_VXCPTEVAC 0xfff07fff -+#define MATCH_AMOMINU_D 0xc000302f -+#define MASK_AMOMINU_D 0xf800707f -+#define MATCH_FSFLAGS 0x101073 -+#define MASK_FSFLAGS 0xfff0707f -+#define MATCH_SRLI 0x5013 -+#define MASK_SRLI 0xfc00707f -+#define MATCH_C_SRLI 0x819 -+#define MASK_C_SRLI 0x1c1f -+#define MATCH_AMOMINU_W 0xc000202f -+#define MASK_AMOMINU_W 0xf800707f -+#define MATCH_SRLW 0x503b -+#define MASK_SRLW 0xfe00707f -+#define MATCH_VFLSEGW 0x1400205b -+#define MASK_VFLSEGW 0x1ff0707f -+#define MATCH_C_LD0 0x8012 -+#define MASK_C_LD0 0x801f -+#define MATCH_VLSEGBU 0x800205b -+#define MASK_VLSEGBU 0x1ff0707f -+#define MATCH_JALR 0x67 -+#define MASK_JALR 0x707f -+#define MATCH_BLT 0x4063 -+#define MASK_BLT 0x707f -+#define MATCH_CUSTOM2_RD_RS1 0x605b -+#define MASK_CUSTOM2_RD_RS1 0x707f -+#define MATCH_FCLASS_S 0xe0001053 -+#define MASK_FCLASS_S 0xfff0707f -+#define MATCH_REM 0x2006033 -+#define MASK_REM 0xfe00707f -+#define MATCH_FCLASS_D 0xe2001053 -+#define MASK_FCLASS_D 0xfff0707f -+#define MATCH_FMUL_S 0x10000053 -+#define MASK_FMUL_S 0xfe00007f -+#define MATCH_RDCYCLEH 0xc8002073 -+#define MASK_RDCYCLEH 0xfffff07f -+#define MATCH_VLSEGSTHU 0xa00305b -+#define MASK_VLSEGSTHU 0x1e00707f -+#define MATCH_FMUL_D 0x12000053 -+#define MASK_FMUL_D 0xfe00007f -+#define MATCH_ORI 0x6013 -+#define MASK_ORI 0x707f -+#define MATCH_FMUL_H 0x14000053 -+#define MASK_FMUL_H 0xfe00007f -+#define MATCH_VFLSEGD 0x1600205b -+#define MASK_VFLSEGD 0x1ff0707f -+#define MATCH_FEQ_S 0xa0002053 -+#define MASK_FEQ_S 0xfe00707f -+#define MATCH_FSGNJX_D 0x22002053 -+#define MASK_FSGNJX_D 0xfe00707f -+#define MATCH_SRAIW 0x4000501b -+#define MASK_SRAIW 0xfe00707f -+#define MATCH_FSGNJX_H 0x3c000053 -+#define MASK_FSGNJX_H 0xfe00707f -+#define MATCH_FSGNJX_S 0x20002053 -+#define MASK_FSGNJX_S 0xfe00707f -+#define MATCH_FEQ_D 0xa2002053 -+#define MASK_FEQ_D 0xfe00707f -+#define MATCH_CUSTOM1_RD_RS1 0x602b -+#define MASK_CUSTOM1_RD_RS1 0x707f -+#define MATCH_FEQ_H 0xac000053 -+#define MASK_FEQ_H 0xfe00707f -+#define MATCH_AMOMAXU_D 0xe000302f -+#define MASK_AMOMAXU_D 0xf800707f -+#define MATCH_DIVW 0x200403b -+#define MASK_DIVW 0xfe00707f -+#define MATCH_AMOMAXU_W 0xe000202f -+#define MASK_AMOMAXU_W 0xf800707f -+#define MATCH_SRAI_RV32 0x40005013 -+#define MASK_SRAI_RV32 0xfe00707f -+#define MATCH_C_SRLI32 0xc19 -+#define MASK_C_SRLI32 0x1c1f -+#define MATCH_VFSSTW 0x1400307b -+#define MASK_VFSSTW 0xfe00707f -+#define MATCH_CUSTOM0_RD 0x400b -+#define MASK_CUSTOM0_RD 0x707f -+#define MATCH_C_BEQ 0x10 -+#define MASK_C_BEQ 0x1f -+#define MATCH_VFSSTD 0x1600307b -+#define MASK_VFSSTD 0xfe00707f -+#define MATCH_CUSTOM3_RD_RS1 0x607b -+#define MASK_CUSTOM3_RD_RS1 0x707f -+#define MATCH_LR_D 0x1000302f -+#define MASK_LR_D 0xf9f0707f -+#define MATCH_LR_W 0x1000202f -+#define MASK_LR_W 0xf9f0707f -+#define MATCH_FCVT_H_WU 0x7c000053 -+#define MASK_FCVT_H_WU 0xfff0007f -+#define MATCH_VMVV 0x200002b -+#define MASK_VMVV 0xfff0707f -+#define MATCH_SLLW 0x103b -+#define MASK_SLLW 0xfe00707f -+#define MATCH_SLLI 0x1013 -+#define MASK_SLLI 0xfc00707f -+#define MATCH_BEQ 0x63 -+#define MASK_BEQ 0x707f -+#define MATCH_AND 0x7033 -+#define MASK_AND 0xfe00707f -+#define MATCH_LBU 0x4003 -+#define MASK_LBU 0x707f -+#define MATCH_FSGNJ_S 0x20000053 -+#define MASK_FSGNJ_S 0xfe00707f -+#define MATCH_FMSUB_S 0x47 -+#define MASK_FMSUB_S 0x600007f -+#define MATCH_C_SUB3 0x11c -+#define MASK_C_SUB3 0x31f -+#define MATCH_FSGNJ_H 0x2c000053 -+#define MASK_FSGNJ_H 0xfe00707f -+#define MATCH_VLB 0x205b -+#define MASK_VLB 0xfff0707f -+#define MATCH_C_ADDIW 0x1d -+#define MASK_C_ADDIW 0x1f -+#define MATCH_CUSTOM3_RS1_RS2 0x307b -+#define MASK_CUSTOM3_RS1_RS2 0x707f -+#define MATCH_FSGNJ_D 0x22000053 -+#define MASK_FSGNJ_D 0xfe00707f -+#define MATCH_VLSEGWU 0xc00205b -+#define MASK_VLSEGWU 0x1ff0707f -+#define MATCH_FCVT_S_WU 0xd0100053 -+#define MASK_FCVT_S_WU 0xfff0007f -+#define MATCH_CUSTOM3_RS1 0x207b -+#define MASK_CUSTOM3_RS1 0x707f -+#define MATCH_SC_D 0x1800302f -+#define MASK_SC_D 0xf800707f -+#define MATCH_VFSW 0x1400207b -+#define MASK_VFSW 0xfff0707f -+#define MATCH_AMOSWAP_D 0x800302f -+#define MASK_AMOSWAP_D 0xf800707f -+#define MATCH_SB 0x23 -+#define MASK_SB 0x707f -+#define MATCH_AMOSWAP_W 0x800202f -+#define MASK_AMOSWAP_W 0xf800707f -+#define MATCH_VFSD 0x1600207b -+#define MASK_VFSD 0xfff0707f -+#define MATCH_CUSTOM2_RS1 0x205b -+#define MASK_CUSTOM2_RS1 0x707f -+#define MATCH_SD 0x3023 -+#define MASK_SD 0x707f -+#define MATCH_FMV_S_X 0xf0000053 -+#define MASK_FMV_S_X 0xfff0707f -+#define MATCH_REMUW 0x200703b -+#define MASK_REMUW 0xfe00707f -+#define MATCH_JAL 0x6f -+#define MASK_JAL 0x7f -+#define MATCH_C_FSD 0x18 -+#define MASK_C_FSD 0x1f -+#define MATCH_RDCYCLE 0xc0002073 -+#define MASK_RDCYCLE 0xfffff07f -+#define MATCH_C_BNE 0x11 -+#define MASK_C_BNE 0x1f -+#define MATCH_C_ADD 0x1a -+#define MASK_C_ADD 0x801f -+#define MATCH_VXCPTCAUSE 0x402b -+#define MASK_VXCPTCAUSE 0xfffff07f -+#define MATCH_VGETCFG 0x400b -+#define MASK_VGETCFG 0xfffff07f -+#define MATCH_LUI 0x37 -+#define MASK_LUI 0x7f -+#define MATCH_VSETCFG 0x200b -+#define MASK_VSETCFG 0x7fff -+#define MATCH_C_SDSP 0x6 -+#define MASK_C_SDSP 0x1f -+#define MATCH_C_LDSP 0x4 -+#define MASK_C_LDSP 0x1f -+#define MATCH_FNMADD_H 0x400004f -+#define MASK_FNMADD_H 0x600007f -+#define MATCH_CUSTOM0_RS1_RS2 0x300b -+#define MASK_CUSTOM0_RS1_RS2 0x707f -+#define MATCH_SLLI_RV32 0x1013 -+#define MASK_SLLI_RV32 0xfe00707f -+#define MATCH_MUL 0x2000033 -+#define MASK_MUL 0xfe00707f -+#define MATCH_CSRRCI 0x7073 -+#define MASK_CSRRCI 0x707f -+#define MATCH_C_SRAI32 0x1419 -+#define MASK_C_SRAI32 0x1c1f -+#define MATCH_FLT_H 0xb4000053 -+#define MASK_FLT_H 0xfe00707f -+#define MATCH_SRAI 0x40005013 -+#define MASK_SRAI 0xfc00707f -+#define MATCH_AMOAND_D 0x6000302f -+#define MASK_AMOAND_D 0xf800707f -+#define MATCH_FLT_D 0xa2001053 -+#define MASK_FLT_D 0xfe00707f -+#define MATCH_SRAW 0x4000503b -+#define MASK_SRAW 0xfe00707f -+#define MATCH_CSRRS 0x2073 -+#define MASK_CSRRS 0x707f -+#define MATCH_FLT_S 0xa0001053 -+#define MASK_FLT_S 0xfe00707f -+#define MATCH_ADDIW 0x1b -+#define MASK_ADDIW 0x707f -+#define MATCH_AMOAND_W 0x6000202f -+#define MASK_AMOAND_W 0xf800707f -+#define MATCH_CUSTOM2_RD 0x405b -+#define MASK_CUSTOM2_RD 0x707f -+#define MATCH_FCVT_WU_D 0xc2100053 -+#define MASK_FCVT_WU_D 0xfff0007f -+#define MATCH_AMOXOR_W 0x2000202f -+#define MASK_AMOXOR_W 0xf800707f -+#define MATCH_FCVT_D_L 0xd2200053 -+#define MASK_FCVT_D_L 0xfff0007f -+#define MATCH_FCVT_WU_H 0x5c000053 -+#define MASK_FCVT_WU_H 0xfff0007f -+#define MATCH_C_SLLI 0x19 -+#define MASK_C_SLLI 0x1c1f -+#define MATCH_AMOXOR_D 0x2000302f -+#define MASK_AMOXOR_D 0xf800707f -+#define MATCH_FCVT_WU_S 0xc0100053 -+#define MASK_FCVT_WU_S 0xfff0007f -+#define MATCH_CUSTOM3_RD 0x407b -+#define MASK_CUSTOM3_RD 0x707f -+#define MATCH_FMAX_H 0xcc000053 -+#define MASK_FMAX_H 0xfe00707f -+#define MATCH_VENQCNT 0x1000302b -+#define MASK_VENQCNT 0xfe007fff -+#define MATCH_VLBU 0x800205b -+#define MASK_VLBU 0xfff0707f -+#define MATCH_VLHU 0xa00205b -+#define MASK_VLHU 0xfff0707f -+#define MATCH_C_SW 0xd -+#define MASK_C_SW 0x1f -+#define MATCH_C_SD 0xc -+#define MASK_C_SD 0x1f -+#define MATCH_C_OR3 0x21c -+#define MASK_C_OR3 0x31f -+#define MATCH_C_AND3 0x31c -+#define MASK_C_AND3 0x31f -+#define MATCH_VFSSEGSTW 0x1400307b -+#define MASK_VFSSEGSTW 0x1e00707f -+#define MATCH_SLT 0x2033 -+#define MASK_SLT 0xfe00707f -+#define MATCH_AMOOR_D 0x4000302f -+#define MASK_AMOOR_D 0xf800707f -+#define MATCH_REMU 0x2007033 -+#define MASK_REMU 0xfe00707f -+#define MATCH_REMW 0x200603b -+#define MASK_REMW 0xfe00707f -+#define MATCH_SLL 0x1033 -+#define MASK_SLL 0xfe00707f -+#define MATCH_VFSSEGSTD 0x1600307b -+#define MASK_VFSSEGSTD 0x1e00707f -+#define MATCH_AMOOR_W 0x4000202f -+#define MASK_AMOOR_W 0xf800707f -+#define MATCH_CUSTOM2_RS1_RS2 0x305b -+#define MASK_CUSTOM2_RS1_RS2 0x707f -+#define MATCH_VF 0x10202b -+#define MASK_VF 0x1f0707f -+#define MATCH_VFMVV 0x1000002b -+#define MASK_VFMVV 0xfff0707f -+#define MATCH_VFLSEGSTW 0x1400305b -+#define MASK_VFLSEGSTW 0x1e00707f -+#define MATCH_VXCPTRESTORE 0x200302b -+#define MASK_VXCPTRESTORE 0xfff07fff -+#define MATCH_VXCPTHOLD 0x800302b -+#define MASK_VXCPTHOLD 0xffffffff -+#define MATCH_SLTIU 0x3013 -+#define MASK_SLTIU 0x707f -+#define MATCH_VFLSEGSTD 0x1600305b -+#define MASK_VFLSEGSTD 0x1e00707f -+#define MATCH_VFLD 0x1600205b -+#define MASK_VFLD 0xfff0707f -+#define MATCH_FMADD_S 0x43 -+#define MASK_FMADD_S 0x600007f -+#define MATCH_VFLW 0x1400205b -+#define MASK_VFLW 0xfff0707f -+#define MATCH_FMADD_D 0x2000043 -+#define MASK_FMADD_D 0x600007f -+#define MATCH_FMADD_H 0x4000043 -+#define MASK_FMADD_H 0x600007f -+#define MATCH_SRET 0x80000073 -+#define MASK_SRET 0xffffffff -+#define MATCH_VSSEGW 0x400207b -+#define MASK_VSSEGW 0x1ff0707f -+#define MATCH_CUSTOM0_RD_RS1 0x600b -+#define MASK_CUSTOM0_RD_RS1 0x707f -+#define MATCH_VSSEGH 0x200207b -+#define MASK_VSSEGH 0x1ff0707f -+#define MATCH_FRCSR 0x302073 -+#define MASK_FRCSR 0xfffff07f -+#define MATCH_VSSEGD 0x600207b -+#define MASK_VSSEGD 0x1ff0707f -+#define MATCH_VSSEGB 0x207b -+#define MASK_VSSEGB 0x1ff0707f -+#define MATCH_FMIN_H 0xc4000053 -+#define MASK_FMIN_H 0xfe00707f -+#define MATCH_FMIN_D 0x2a000053 -+#define MASK_FMIN_D 0xfe00707f -+#define MATCH_BLTU 0x6063 -+#define MASK_BLTU 0x707f -+#define MATCH_FMIN_S 0x28000053 -+#define MASK_FMIN_S 0xfe00707f -+#define MATCH_SRLI_RV32 0x5013 -+#define MASK_SRLI_RV32 0xfe00707f -+#define MATCH_SLLIW 0x101b -+#define MASK_SLLIW 0xfe00707f -+#define MATCH_FMAX_S 0x28001053 -+#define MASK_FMAX_S 0xfe00707f -+#define MATCH_FCVT_D_H 0x8c000053 -+#define MASK_FCVT_D_H 0xfff0007f -+#define MATCH_FCVT_D_W 0xd2000053 -+#define MASK_FCVT_D_W 0xfff0007f -+#define MATCH_ADD 0x33 -+#define MASK_ADD 0xfe00707f -+#define MATCH_FCVT_D_S 0x42000053 -+#define MASK_FCVT_D_S 0xfff0007f -+#define MATCH_FMAX_D 0x2a001053 -+#define MASK_FMAX_D 0xfe00707f -+#define MATCH_BNE 0x1063 -+#define MASK_BNE 0x707f -+#define MATCH_CUSTOM1_RD 0x402b -+#define MASK_CUSTOM1_RD 0x707f -+#define MATCH_FSRM 0x201073 -+#define MASK_FSRM 0xfff0707f -+#define MATCH_FDIV_D 0x1a000053 -+#define MASK_FDIV_D 0xfe00007f -+#define MATCH_VSW 0x400207b -+#define MASK_VSW 0xfff0707f -+#define MATCH_FCVT_L_S 0xc0200053 -+#define MASK_FCVT_L_S 0xfff0007f -+#define MATCH_FDIV_H 0x1c000053 -+#define MASK_FDIV_H 0xfe00007f -+#define MATCH_VSB 0x207b -+#define MASK_VSB 0xfff0707f -+#define MATCH_FDIV_S 0x18000053 -+#define MASK_FDIV_S 0xfe00007f -+#define MATCH_FSRMI 0x205073 -+#define MASK_FSRMI 0xfff0707f -+#define MATCH_FCVT_L_H 0x44000053 -+#define MASK_FCVT_L_H 0xfff0007f -+#define MATCH_VSH 0x200207b -+#define MASK_VSH 0xfff0707f -+#define MATCH_FCVT_L_D 0xc2200053 -+#define MASK_FCVT_L_D 0xfff0007f -+#define MATCH_FCVT_H_S 0x90000053 -+#define MASK_FCVT_H_S 0xfff0007f -+#define MATCH_SCALL 0x73 -+#define MASK_SCALL 0xffffffff -+#define MATCH_FSFLAGSI 0x105073 -+#define MASK_FSFLAGSI 0xfff0707f -+#define MATCH_FCVT_H_W 0x74000053 -+#define MASK_FCVT_H_W 0xfff0007f -+#define MATCH_FCVT_H_L 0x64000053 -+#define MASK_FCVT_H_L 0xfff0007f -+#define MATCH_SRLIW 0x501b -+#define MASK_SRLIW 0xfe00707f -+#define MATCH_FCVT_S_LU 0xd0300053 -+#define MASK_FCVT_S_LU 0xfff0007f -+#define MATCH_FCVT_H_D 0x92000053 -+#define MASK_FCVT_H_D 0xfff0007f -+#define MATCH_SBREAK 0x100073 -+#define MASK_SBREAK 0xffffffff -+#define MATCH_RDINSTRETH 0xc8202073 -+#define MASK_RDINSTRETH 0xfffff07f -+#define MATCH_SRA 0x40005033 -+#define MASK_SRA 0xfe00707f -+#define MATCH_BGE 0x5063 -+#define MASK_BGE 0x707f -+#define MATCH_SRL 0x5033 -+#define MASK_SRL 0xfe00707f -+#define MATCH_VENQCMD 0xa00302b -+#define MASK_VENQCMD 0xfe007fff -+#define MATCH_OR 0x6033 -+#define MASK_OR 0xfe00707f -+#define MATCH_SUBW 0x4000003b -+#define MASK_SUBW 0xfe00707f -+#define MATCH_FMV_X_D 0xe2000053 -+#define MASK_FMV_X_D 0xfff0707f -+#define MATCH_RDTIME 0xc0102073 -+#define MASK_RDTIME 0xfffff07f -+#define MATCH_AMOADD_D 0x302f -+#define MASK_AMOADD_D 0xf800707f -+#define MATCH_AMOMAX_W 0xa000202f -+#define MASK_AMOMAX_W 0xf800707f -+#define MATCH_C_MOVE 0x2 -+#define MASK_C_MOVE 0x801f -+#define MATCH_FMOVN 0x6007077 -+#define MASK_FMOVN 0xfe00707f -+#define MATCH_C_FSW 0x16 -+#define MASK_C_FSW 0x1f -+#define MATCH_AMOADD_W 0x202f -+#define MASK_AMOADD_W 0xf800707f -+#define MATCH_AMOMAX_D 0xa000302f -+#define MASK_AMOMAX_D 0xf800707f -+#define MATCH_FMOVZ 0x4007077 -+#define MASK_FMOVZ 0xfe00707f -+#define MATCH_CUSTOM1_RS1_RS2 0x302b -+#define MASK_CUSTOM1_RS1_RS2 0x707f -+#define MATCH_FMV_X_H 0xe4000053 -+#define MASK_FMV_X_H 0xfff0707f -+#define MATCH_VSD 0x600207b -+#define MASK_VSD 0xfff0707f -+#define MATCH_VLSEGSTW 0x400305b -+#define MASK_VLSEGSTW 0x1e00707f -+#define MATCH_C_ADDI 0x1 -+#define MASK_C_ADDI 0x1f -+#define MATCH_C_SLLIW 0x1819 -+#define MASK_C_SLLIW 0x1c1f -+#define MATCH_VLSEGSTB 0x305b -+#define MASK_VLSEGSTB 0x1e00707f -+#define MATCH_VLSEGSTD 0x600305b -+#define MASK_VLSEGSTD 0x1e00707f -+#define MATCH_VLSEGSTH 0x200305b -+#define MASK_VLSEGSTH 0x1e00707f -+#define MATCH_MULHU 0x2003033 -+#define MASK_MULHU 0xfe00707f -+#define MATCH_AMOMIN_W 0x8000202f -+#define MASK_AMOMIN_W 0xf800707f -+#define MATCH_C_SLLI32 0x419 -+#define MASK_C_SLLI32 0x1c1f -+#define MATCH_C_ADD3 0x1c -+#define MASK_C_ADD3 0x31f -+#define MATCH_VGETVL 0x200400b -+#define MASK_VGETVL 0xfffff07f -+#define MATCH_AMOMIN_D 0x8000302f -+#define MASK_AMOMIN_D 0xf800707f -+#define MATCH_FCVT_W_H 0x54000053 -+#define MASK_FCVT_W_H 0xfff0007f -+#define MATCH_VLSEGB 0x205b -+#define MASK_VLSEGB 0x1ff0707f -+#define MATCH_FSD 0x3027 -+#define MASK_FSD 0x707f -+#define MATCH_VLSEGD 0x600205b -+#define MASK_VLSEGD 0x1ff0707f -+#define MATCH_FSH 0x1027 -+#define MASK_FSH 0x707f -+#define MATCH_VLSEGH 0x200205b -+#define MASK_VLSEGH 0x1ff0707f -+#define MATCH_C_SUB 0x801a -+#define MASK_C_SUB 0x801f -+#define MATCH_VLSEGW 0x400205b -+#define MASK_VLSEGW 0x1ff0707f -+#define MATCH_FSW 0x2027 -+#define MASK_FSW 0x707f -+#define MATCH_C_J 0x8002 -+#define MASK_C_J 0x801f -+#define CSR_FFLAGS 0x1 -+#define CSR_FRM 0x2 -+#define CSR_FCSR 0x3 -+#define CSR_STATS 0xc0 -+#define CSR_SUP0 0x500 -+#define CSR_SUP1 0x501 -+#define CSR_EPC 0x502 -+#define CSR_BADVADDR 0x503 -+#define CSR_PTBR 0x504 -+#define CSR_ASID 0x505 -+#define CSR_COUNT 0x506 -+#define CSR_COMPARE 0x507 -+#define CSR_EVEC 0x508 -+#define CSR_CAUSE 0x509 -+#define CSR_STATUS 0x50a -+#define CSR_HARTID 0x50b -+#define CSR_IMPL 0x50c -+#define CSR_FATC 0x50d -+#define CSR_SEND_IPI 0x50e -+#define CSR_CLEAR_IPI 0x50f -+#define CSR_RESET 0x51d -+#define CSR_TOHOST 0x51e -+#define CSR_FROMHOST 0x51f -+#define CSR_CYCLE 0xc00 -+#define CSR_TIME 0xc01 -+#define CSR_INSTRET 0xc02 -+#define CSR_UARCH0 0xcc0 -+#define CSR_UARCH1 0xcc1 -+#define CSR_UARCH2 0xcc2 -+#define CSR_UARCH3 0xcc3 -+#define CSR_UARCH4 0xcc4 -+#define CSR_UARCH5 0xcc5 -+#define CSR_UARCH6 0xcc6 -+#define CSR_UARCH7 0xcc7 -+#define CSR_UARCH8 0xcc8 -+#define CSR_UARCH9 0xcc9 -+#define CSR_UARCH10 0xcca -+#define CSR_UARCH11 0xccb -+#define CSR_UARCH12 0xccc -+#define CSR_UARCH13 0xccd -+#define CSR_UARCH14 0xcce -+#define CSR_UARCH15 0xccf -+#define CSR_COUNTH 0x586 -+#define CSR_CYCLEH 0xc80 -+#define CSR_TIMEH 0xc81 -+#define CSR_INSTRETH 0xc82 -+#define CAUSE_MISALIGNED_FETCH 0x0 -+#define CAUSE_FAULT_FETCH 0x1 -+#define CAUSE_ILLEGAL_INSTRUCTION 0x2 -+#define CAUSE_PRIVILEGED_INSTRUCTION 0x3 -+#define CAUSE_FP_DISABLED 0x4 -+#define CAUSE_SYSCALL 0x6 -+#define CAUSE_BREAKPOINT 0x7 -+#define CAUSE_MISALIGNED_LOAD 0x8 -+#define CAUSE_MISALIGNED_STORE 0x9 -+#define CAUSE_FAULT_LOAD 0xa -+#define CAUSE_FAULT_STORE 0xb -+#define CAUSE_ACCELERATOR_DISABLED 0xc -+#endif -+#ifdef DECLARE_INSN -+DECLARE_INSN(custom3_rd_rs1_rs2, MATCH_CUSTOM3_RD_RS1_RS2, MASK_CUSTOM3_RD_RS1_RS2) -+DECLARE_INSN(vlsegstwu, MATCH_VLSEGSTWU, MASK_VLSEGSTWU) -+DECLARE_INSN(c_lw0, MATCH_C_LW0, MASK_C_LW0) -+DECLARE_INSN(fmv_d_x, MATCH_FMV_D_X, MASK_FMV_D_X) -+DECLARE_INSN(vlh, MATCH_VLH, MASK_VLH) -+DECLARE_INSN(c_li, MATCH_C_LI, MASK_C_LI) -+DECLARE_INSN(fadd_d, MATCH_FADD_D, MASK_FADD_D) -+DECLARE_INSN(c_ld, MATCH_C_LD, MASK_C_LD) -+DECLARE_INSN(vld, MATCH_VLD, MASK_VLD) -+DECLARE_INSN(fadd_s, MATCH_FADD_S, MASK_FADD_S) -+DECLARE_INSN(c_lw, MATCH_C_LW, MASK_C_LW) -+DECLARE_INSN(vlw, MATCH_VLW, MASK_VLW) -+DECLARE_INSN(vssegstw, MATCH_VSSEGSTW, MASK_VSSEGSTW) -+DECLARE_INSN(utidx, MATCH_UTIDX, MASK_UTIDX) -+DECLARE_INSN(c_flw, MATCH_C_FLW, MASK_C_FLW) -+DECLARE_INSN(fsub_d, MATCH_FSUB_D, MASK_FSUB_D) -+DECLARE_INSN(vssegstd, MATCH_VSSEGSTD, MASK_VSSEGSTD) -+DECLARE_INSN(vssegstb, MATCH_VSSEGSTB, MASK_VSSEGSTB) -+DECLARE_INSN(div, MATCH_DIV, MASK_DIV) -+DECLARE_INSN(fmv_h_x, MATCH_FMV_H_X, MASK_FMV_H_X) -+DECLARE_INSN(c_fld, MATCH_C_FLD, MASK_C_FLD) -+DECLARE_INSN(frrm, MATCH_FRRM, MASK_FRRM) -+DECLARE_INSN(vfmsv_s, MATCH_VFMSV_S, MASK_VFMSV_S) -+DECLARE_INSN(c_lwsp, MATCH_C_LWSP, MASK_C_LWSP) -+DECLARE_INSN(fence, MATCH_FENCE, MASK_FENCE) -+DECLARE_INSN(fnmsub_s, MATCH_FNMSUB_S, MASK_FNMSUB_S) -+DECLARE_INSN(fle_s, MATCH_FLE_S, MASK_FLE_S) -+DECLARE_INSN(fnmsub_h, MATCH_FNMSUB_H, MASK_FNMSUB_H) -+DECLARE_INSN(fle_h, MATCH_FLE_H, MASK_FLE_H) -+DECLARE_INSN(flw, MATCH_FLW, MASK_FLW) -+DECLARE_INSN(vsetvl, MATCH_VSETVL, MASK_VSETVL) -+DECLARE_INSN(vfmsv_d, MATCH_VFMSV_D, MASK_VFMSV_D) -+DECLARE_INSN(fle_d, MATCH_FLE_D, MASK_FLE_D) -+DECLARE_INSN(fence_i, MATCH_FENCE_I, MASK_FENCE_I) -+DECLARE_INSN(fnmsub_d, MATCH_FNMSUB_D, MASK_FNMSUB_D) -+DECLARE_INSN(addw, MATCH_ADDW, MASK_ADDW) -+DECLARE_INSN(xor, MATCH_XOR, MASK_XOR) -+DECLARE_INSN(sub, MATCH_SUB, MASK_SUB) -+DECLARE_INSN(vsstw, MATCH_VSSTW, MASK_VSSTW) -+DECLARE_INSN(vssth, MATCH_VSSTH, MASK_VSSTH) -+DECLARE_INSN(sc_w, MATCH_SC_W, MASK_SC_W) -+DECLARE_INSN(vsstb, MATCH_VSSTB, MASK_VSSTB) -+DECLARE_INSN(vsstd, MATCH_VSSTD, MASK_VSSTD) -+DECLARE_INSN(addi, MATCH_ADDI, MASK_ADDI) -+DECLARE_INSN(rdtimeh, MATCH_RDTIMEH, MASK_RDTIMEH) -+DECLARE_INSN(mulh, MATCH_MULH, MASK_MULH) -+DECLARE_INSN(csrrsi, MATCH_CSRRSI, MASK_CSRRSI) -+DECLARE_INSN(fcvt_d_wu, MATCH_FCVT_D_WU, MASK_FCVT_D_WU) -+DECLARE_INSN(mulw, MATCH_MULW, MASK_MULW) -+DECLARE_INSN(custom1_rd_rs1_rs2, MATCH_CUSTOM1_RD_RS1_RS2, MASK_CUSTOM1_RD_RS1_RS2) -+DECLARE_INSN(venqimm1, MATCH_VENQIMM1, MASK_VENQIMM1) -+DECLARE_INSN(venqimm2, MATCH_VENQIMM2, MASK_VENQIMM2) -+DECLARE_INSN(rdinstret, MATCH_RDINSTRET, MASK_RDINSTRET) -+DECLARE_INSN(c_swsp, MATCH_C_SWSP, MASK_C_SWSP) -+DECLARE_INSN(vlstw, MATCH_VLSTW, MASK_VLSTW) -+DECLARE_INSN(vlsth, MATCH_VLSTH, MASK_VLSTH) -+DECLARE_INSN(vlstb, MATCH_VLSTB, MASK_VLSTB) -+DECLARE_INSN(vlstd, MATCH_VLSTD, MASK_VLSTD) -+DECLARE_INSN(andi, MATCH_ANDI, MASK_ANDI) -+DECLARE_INSN(fmv_x_s, MATCH_FMV_X_S, MASK_FMV_X_S) -+DECLARE_INSN(custom0_rd_rs1_rs2, MATCH_CUSTOM0_RD_RS1_RS2, MASK_CUSTOM0_RD_RS1_RS2) -+DECLARE_INSN(fnmadd_s, MATCH_FNMADD_S, MASK_FNMADD_S) -+DECLARE_INSN(lwu, MATCH_LWU, MASK_LWU) -+DECLARE_INSN(custom0_rs1, MATCH_CUSTOM0_RS1, MASK_CUSTOM0_RS1) -+DECLARE_INSN(vlsegstbu, MATCH_VLSEGSTBU, MASK_VLSEGSTBU) -+DECLARE_INSN(fnmadd_d, MATCH_FNMADD_D, MASK_FNMADD_D) -+DECLARE_INSN(fcvt_w_s, MATCH_FCVT_W_S, MASK_FCVT_W_S) -+DECLARE_INSN(c_srai, MATCH_C_SRAI, MASK_C_SRAI) -+DECLARE_INSN(mulhsu, MATCH_MULHSU, MASK_MULHSU) -+DECLARE_INSN(fcvt_d_lu, MATCH_FCVT_D_LU, MASK_FCVT_D_LU) -+DECLARE_INSN(fcvt_w_d, MATCH_FCVT_W_D, MASK_FCVT_W_D) -+DECLARE_INSN(fsub_h, MATCH_FSUB_H, MASK_FSUB_H) -+DECLARE_INSN(divuw, MATCH_DIVUW, MASK_DIVUW) -+DECLARE_INSN(slti, MATCH_SLTI, MASK_SLTI) -+DECLARE_INSN(vlstbu, MATCH_VLSTBU, MASK_VLSTBU) -+DECLARE_INSN(sltu, MATCH_SLTU, MASK_SLTU) -+DECLARE_INSN(flh, MATCH_FLH, MASK_FLH) -+DECLARE_INSN(custom2_rd_rs1_rs2, MATCH_CUSTOM2_RD_RS1_RS2, MASK_CUSTOM2_RD_RS1_RS2) -+DECLARE_INSN(fld, MATCH_FLD, MASK_FLD) -+DECLARE_INSN(fsub_s, MATCH_FSUB_S, MASK_FSUB_S) -+DECLARE_INSN(fcvt_h_lu, MATCH_FCVT_H_LU, MASK_FCVT_H_LU) -+DECLARE_INSN(custom0, MATCH_CUSTOM0, MASK_CUSTOM0) -+DECLARE_INSN(custom1, MATCH_CUSTOM1, MASK_CUSTOM1) -+DECLARE_INSN(custom2, MATCH_CUSTOM2, MASK_CUSTOM2) -+DECLARE_INSN(custom3, MATCH_CUSTOM3, MASK_CUSTOM3) -+DECLARE_INSN(vxcptsave, MATCH_VXCPTSAVE, MASK_VXCPTSAVE) -+DECLARE_INSN(vmsv, MATCH_VMSV, MASK_VMSV) -+DECLARE_INSN(fcvt_lu_s, MATCH_FCVT_LU_S, MASK_FCVT_LU_S) -+DECLARE_INSN(auipc, MATCH_AUIPC, MASK_AUIPC) -+DECLARE_INSN(frflags, MATCH_FRFLAGS, MASK_FRFLAGS) -+DECLARE_INSN(fcvt_lu_d, MATCH_FCVT_LU_D, MASK_FCVT_LU_D) -+DECLARE_INSN(csrrwi, MATCH_CSRRWI, MASK_CSRRWI) -+DECLARE_INSN(fadd_h, MATCH_FADD_H, MASK_FADD_H) -+DECLARE_INSN(fsqrt_s, MATCH_FSQRT_S, MASK_FSQRT_S) -+DECLARE_INSN(vxcptkill, MATCH_VXCPTKILL, MASK_VXCPTKILL) -+DECLARE_INSN(stop, MATCH_STOP, MASK_STOP) -+DECLARE_INSN(fsgnjn_s, MATCH_FSGNJN_S, MASK_FSGNJN_S) -+DECLARE_INSN(fsgnjn_h, MATCH_FSGNJN_H, MASK_FSGNJN_H) -+DECLARE_INSN(fsqrt_d, MATCH_FSQRT_D, MASK_FSQRT_D) -+DECLARE_INSN(xori, MATCH_XORI, MASK_XORI) -+DECLARE_INSN(divu, MATCH_DIVU, MASK_DIVU) -+DECLARE_INSN(fsgnjn_d, MATCH_FSGNJN_D, MASK_FSGNJN_D) -+DECLARE_INSN(fsqrt_h, MATCH_FSQRT_H, MASK_FSQRT_H) -+DECLARE_INSN(vssegsth, MATCH_VSSEGSTH, MASK_VSSEGSTH) -+DECLARE_INSN(sw, MATCH_SW, MASK_SW) -+DECLARE_INSN(vlstwu, MATCH_VLSTWU, MASK_VLSTWU) -+DECLARE_INSN(vfssegw, MATCH_VFSSEGW, MASK_VFSSEGW) -+DECLARE_INSN(lhu, MATCH_LHU, MASK_LHU) -+DECLARE_INSN(sh, MATCH_SH, MASK_SH) -+DECLARE_INSN(fmsub_h, MATCH_FMSUB_H, MASK_FMSUB_H) -+DECLARE_INSN(vxcptaux, MATCH_VXCPTAUX, MASK_VXCPTAUX) -+DECLARE_INSN(fmsub_d, MATCH_FMSUB_D, MASK_FMSUB_D) -+DECLARE_INSN(vfssegd, MATCH_VFSSEGD, MASK_VFSSEGD) -+DECLARE_INSN(vlseghu, MATCH_VLSEGHU, MASK_VLSEGHU) -+DECLARE_INSN(movn, MATCH_MOVN, MASK_MOVN) -+DECLARE_INSN(custom1_rs1, MATCH_CUSTOM1_RS1, MASK_CUSTOM1_RS1) -+DECLARE_INSN(vlsthu, MATCH_VLSTHU, MASK_VLSTHU) -+DECLARE_INSN(movz, MATCH_MOVZ, MASK_MOVZ) -+DECLARE_INSN(csrrw, MATCH_CSRRW, MASK_CSRRW) -+DECLARE_INSN(ld, MATCH_LD, MASK_LD) -+DECLARE_INSN(lb, MATCH_LB, MASK_LB) -+DECLARE_INSN(vlwu, MATCH_VLWU, MASK_VLWU) -+DECLARE_INSN(lh, MATCH_LH, MASK_LH) -+DECLARE_INSN(lw, MATCH_LW, MASK_LW) -+DECLARE_INSN(csrrc, MATCH_CSRRC, MASK_CSRRC) -+DECLARE_INSN(fcvt_lu_h, MATCH_FCVT_LU_H, MASK_FCVT_LU_H) -+DECLARE_INSN(fcvt_s_d, MATCH_FCVT_S_D, MASK_FCVT_S_D) -+DECLARE_INSN(bgeu, MATCH_BGEU, MASK_BGEU) -+DECLARE_INSN(vflstd, MATCH_VFLSTD, MASK_VFLSTD) -+DECLARE_INSN(fcvt_s_l, MATCH_FCVT_S_L, MASK_FCVT_S_L) -+DECLARE_INSN(fcvt_s_h, MATCH_FCVT_S_H, MASK_FCVT_S_H) -+DECLARE_INSN(fscsr, MATCH_FSCSR, MASK_FSCSR) -+DECLARE_INSN(fcvt_s_w, MATCH_FCVT_S_W, MASK_FCVT_S_W) -+DECLARE_INSN(vflstw, MATCH_VFLSTW, MASK_VFLSTW) -+DECLARE_INSN(vxcptevac, MATCH_VXCPTEVAC, MASK_VXCPTEVAC) -+DECLARE_INSN(amominu_d, MATCH_AMOMINU_D, MASK_AMOMINU_D) -+DECLARE_INSN(fsflags, MATCH_FSFLAGS, MASK_FSFLAGS) -+DECLARE_INSN(srli, MATCH_SRLI, MASK_SRLI) -+DECLARE_INSN(c_srli, MATCH_C_SRLI, MASK_C_SRLI) -+DECLARE_INSN(amominu_w, MATCH_AMOMINU_W, MASK_AMOMINU_W) -+DECLARE_INSN(srlw, MATCH_SRLW, MASK_SRLW) -+DECLARE_INSN(vflsegw, MATCH_VFLSEGW, MASK_VFLSEGW) -+DECLARE_INSN(c_ld0, MATCH_C_LD0, MASK_C_LD0) -+DECLARE_INSN(vlsegbu, MATCH_VLSEGBU, MASK_VLSEGBU) -+DECLARE_INSN(jalr, MATCH_JALR, MASK_JALR) -+DECLARE_INSN(blt, MATCH_BLT, MASK_BLT) -+DECLARE_INSN(custom2_rd_rs1, MATCH_CUSTOM2_RD_RS1, MASK_CUSTOM2_RD_RS1) -+DECLARE_INSN(fclass_s, MATCH_FCLASS_S, MASK_FCLASS_S) -+DECLARE_INSN(rem, MATCH_REM, MASK_REM) -+DECLARE_INSN(fclass_d, MATCH_FCLASS_D, MASK_FCLASS_D) -+DECLARE_INSN(fmul_s, MATCH_FMUL_S, MASK_FMUL_S) -+DECLARE_INSN(rdcycleh, MATCH_RDCYCLEH, MASK_RDCYCLEH) -+DECLARE_INSN(vlsegsthu, MATCH_VLSEGSTHU, MASK_VLSEGSTHU) -+DECLARE_INSN(fmul_d, MATCH_FMUL_D, MASK_FMUL_D) -+DECLARE_INSN(ori, MATCH_ORI, MASK_ORI) -+DECLARE_INSN(fmul_h, MATCH_FMUL_H, MASK_FMUL_H) -+DECLARE_INSN(vflsegd, MATCH_VFLSEGD, MASK_VFLSEGD) -+DECLARE_INSN(feq_s, MATCH_FEQ_S, MASK_FEQ_S) -+DECLARE_INSN(fsgnjx_d, MATCH_FSGNJX_D, MASK_FSGNJX_D) -+DECLARE_INSN(sraiw, MATCH_SRAIW, MASK_SRAIW) -+DECLARE_INSN(fsgnjx_h, MATCH_FSGNJX_H, MASK_FSGNJX_H) -+DECLARE_INSN(fsgnjx_s, MATCH_FSGNJX_S, MASK_FSGNJX_S) -+DECLARE_INSN(feq_d, MATCH_FEQ_D, MASK_FEQ_D) -+DECLARE_INSN(custom1_rd_rs1, MATCH_CUSTOM1_RD_RS1, MASK_CUSTOM1_RD_RS1) -+DECLARE_INSN(feq_h, MATCH_FEQ_H, MASK_FEQ_H) -+DECLARE_INSN(amomaxu_d, MATCH_AMOMAXU_D, MASK_AMOMAXU_D) -+DECLARE_INSN(divw, MATCH_DIVW, MASK_DIVW) -+DECLARE_INSN(amomaxu_w, MATCH_AMOMAXU_W, MASK_AMOMAXU_W) -+DECLARE_INSN(srai_rv32, MATCH_SRAI_RV32, MASK_SRAI_RV32) -+DECLARE_INSN(c_srli32, MATCH_C_SRLI32, MASK_C_SRLI32) -+DECLARE_INSN(vfsstw, MATCH_VFSSTW, MASK_VFSSTW) -+DECLARE_INSN(custom0_rd, MATCH_CUSTOM0_RD, MASK_CUSTOM0_RD) -+DECLARE_INSN(c_beq, MATCH_C_BEQ, MASK_C_BEQ) -+DECLARE_INSN(vfsstd, MATCH_VFSSTD, MASK_VFSSTD) -+DECLARE_INSN(custom3_rd_rs1, MATCH_CUSTOM3_RD_RS1, MASK_CUSTOM3_RD_RS1) -+DECLARE_INSN(lr_d, MATCH_LR_D, MASK_LR_D) -+DECLARE_INSN(lr_w, MATCH_LR_W, MASK_LR_W) -+DECLARE_INSN(fcvt_h_wu, MATCH_FCVT_H_WU, MASK_FCVT_H_WU) -+DECLARE_INSN(vmvv, MATCH_VMVV, MASK_VMVV) -+DECLARE_INSN(sllw, MATCH_SLLW, MASK_SLLW) -+DECLARE_INSN(slli, MATCH_SLLI, MASK_SLLI) -+DECLARE_INSN(beq, MATCH_BEQ, MASK_BEQ) -+DECLARE_INSN(and, MATCH_AND, MASK_AND) -+DECLARE_INSN(lbu, MATCH_LBU, MASK_LBU) -+DECLARE_INSN(fsgnj_s, MATCH_FSGNJ_S, MASK_FSGNJ_S) -+DECLARE_INSN(fmsub_s, MATCH_FMSUB_S, MASK_FMSUB_S) -+DECLARE_INSN(c_sub3, MATCH_C_SUB3, MASK_C_SUB3) -+DECLARE_INSN(fsgnj_h, MATCH_FSGNJ_H, MASK_FSGNJ_H) -+DECLARE_INSN(vlb, MATCH_VLB, MASK_VLB) -+DECLARE_INSN(c_addiw, MATCH_C_ADDIW, MASK_C_ADDIW) -+DECLARE_INSN(custom3_rs1_rs2, MATCH_CUSTOM3_RS1_RS2, MASK_CUSTOM3_RS1_RS2) -+DECLARE_INSN(fsgnj_d, MATCH_FSGNJ_D, MASK_FSGNJ_D) -+DECLARE_INSN(vlsegwu, MATCH_VLSEGWU, MASK_VLSEGWU) -+DECLARE_INSN(fcvt_s_wu, MATCH_FCVT_S_WU, MASK_FCVT_S_WU) -+DECLARE_INSN(custom3_rs1, MATCH_CUSTOM3_RS1, MASK_CUSTOM3_RS1) -+DECLARE_INSN(sc_d, MATCH_SC_D, MASK_SC_D) -+DECLARE_INSN(vfsw, MATCH_VFSW, MASK_VFSW) -+DECLARE_INSN(amoswap_d, MATCH_AMOSWAP_D, MASK_AMOSWAP_D) -+DECLARE_INSN(sb, MATCH_SB, MASK_SB) -+DECLARE_INSN(amoswap_w, MATCH_AMOSWAP_W, MASK_AMOSWAP_W) -+DECLARE_INSN(vfsd, MATCH_VFSD, MASK_VFSD) -+DECLARE_INSN(custom2_rs1, MATCH_CUSTOM2_RS1, MASK_CUSTOM2_RS1) -+DECLARE_INSN(sd, MATCH_SD, MASK_SD) -+DECLARE_INSN(fmv_s_x, MATCH_FMV_S_X, MASK_FMV_S_X) -+DECLARE_INSN(remuw, MATCH_REMUW, MASK_REMUW) -+DECLARE_INSN(jal, MATCH_JAL, MASK_JAL) -+DECLARE_INSN(c_fsd, MATCH_C_FSD, MASK_C_FSD) -+DECLARE_INSN(rdcycle, MATCH_RDCYCLE, MASK_RDCYCLE) -+DECLARE_INSN(c_bne, MATCH_C_BNE, MASK_C_BNE) -+DECLARE_INSN(c_add, MATCH_C_ADD, MASK_C_ADD) -+DECLARE_INSN(vxcptcause, MATCH_VXCPTCAUSE, MASK_VXCPTCAUSE) -+DECLARE_INSN(vgetcfg, MATCH_VGETCFG, MASK_VGETCFG) -+DECLARE_INSN(lui, MATCH_LUI, MASK_LUI) -+DECLARE_INSN(vsetcfg, MATCH_VSETCFG, MASK_VSETCFG) -+DECLARE_INSN(c_sdsp, MATCH_C_SDSP, MASK_C_SDSP) -+DECLARE_INSN(c_ldsp, MATCH_C_LDSP, MASK_C_LDSP) -+DECLARE_INSN(fnmadd_h, MATCH_FNMADD_H, MASK_FNMADD_H) -+DECLARE_INSN(custom0_rs1_rs2, MATCH_CUSTOM0_RS1_RS2, MASK_CUSTOM0_RS1_RS2) -+DECLARE_INSN(slli_rv32, MATCH_SLLI_RV32, MASK_SLLI_RV32) -+DECLARE_INSN(mul, MATCH_MUL, MASK_MUL) -+DECLARE_INSN(csrrci, MATCH_CSRRCI, MASK_CSRRCI) -+DECLARE_INSN(c_srai32, MATCH_C_SRAI32, MASK_C_SRAI32) -+DECLARE_INSN(flt_h, MATCH_FLT_H, MASK_FLT_H) -+DECLARE_INSN(srai, MATCH_SRAI, MASK_SRAI) -+DECLARE_INSN(amoand_d, MATCH_AMOAND_D, MASK_AMOAND_D) -+DECLARE_INSN(flt_d, MATCH_FLT_D, MASK_FLT_D) -+DECLARE_INSN(sraw, MATCH_SRAW, MASK_SRAW) -+DECLARE_INSN(csrrs, MATCH_CSRRS, MASK_CSRRS) -+DECLARE_INSN(flt_s, MATCH_FLT_S, MASK_FLT_S) -+DECLARE_INSN(addiw, MATCH_ADDIW, MASK_ADDIW) -+DECLARE_INSN(amoand_w, MATCH_AMOAND_W, MASK_AMOAND_W) -+DECLARE_INSN(custom2_rd, MATCH_CUSTOM2_RD, MASK_CUSTOM2_RD) -+DECLARE_INSN(fcvt_wu_d, MATCH_FCVT_WU_D, MASK_FCVT_WU_D) -+DECLARE_INSN(amoxor_w, MATCH_AMOXOR_W, MASK_AMOXOR_W) -+DECLARE_INSN(fcvt_d_l, MATCH_FCVT_D_L, MASK_FCVT_D_L) -+DECLARE_INSN(fcvt_wu_h, MATCH_FCVT_WU_H, MASK_FCVT_WU_H) -+DECLARE_INSN(c_slli, MATCH_C_SLLI, MASK_C_SLLI) -+DECLARE_INSN(amoxor_d, MATCH_AMOXOR_D, MASK_AMOXOR_D) -+DECLARE_INSN(fcvt_wu_s, MATCH_FCVT_WU_S, MASK_FCVT_WU_S) -+DECLARE_INSN(custom3_rd, MATCH_CUSTOM3_RD, MASK_CUSTOM3_RD) -+DECLARE_INSN(fmax_h, MATCH_FMAX_H, MASK_FMAX_H) -+DECLARE_INSN(venqcnt, MATCH_VENQCNT, MASK_VENQCNT) -+DECLARE_INSN(vlbu, MATCH_VLBU, MASK_VLBU) -+DECLARE_INSN(vlhu, MATCH_VLHU, MASK_VLHU) -+DECLARE_INSN(c_sw, MATCH_C_SW, MASK_C_SW) -+DECLARE_INSN(c_sd, MATCH_C_SD, MASK_C_SD) -+DECLARE_INSN(c_or3, MATCH_C_OR3, MASK_C_OR3) -+DECLARE_INSN(c_and3, MATCH_C_AND3, MASK_C_AND3) -+DECLARE_INSN(vfssegstw, MATCH_VFSSEGSTW, MASK_VFSSEGSTW) -+DECLARE_INSN(slt, MATCH_SLT, MASK_SLT) -+DECLARE_INSN(amoor_d, MATCH_AMOOR_D, MASK_AMOOR_D) -+DECLARE_INSN(remu, MATCH_REMU, MASK_REMU) -+DECLARE_INSN(remw, MATCH_REMW, MASK_REMW) -+DECLARE_INSN(sll, MATCH_SLL, MASK_SLL) -+DECLARE_INSN(vfssegstd, MATCH_VFSSEGSTD, MASK_VFSSEGSTD) -+DECLARE_INSN(amoor_w, MATCH_AMOOR_W, MASK_AMOOR_W) -+DECLARE_INSN(custom2_rs1_rs2, MATCH_CUSTOM2_RS1_RS2, MASK_CUSTOM2_RS1_RS2) -+DECLARE_INSN(vf, MATCH_VF, MASK_VF) -+DECLARE_INSN(vfmvv, MATCH_VFMVV, MASK_VFMVV) -+DECLARE_INSN(vflsegstw, MATCH_VFLSEGSTW, MASK_VFLSEGSTW) -+DECLARE_INSN(vxcptrestore, MATCH_VXCPTRESTORE, MASK_VXCPTRESTORE) -+DECLARE_INSN(vxcpthold, MATCH_VXCPTHOLD, MASK_VXCPTHOLD) -+DECLARE_INSN(sltiu, MATCH_SLTIU, MASK_SLTIU) -+DECLARE_INSN(vflsegstd, MATCH_VFLSEGSTD, MASK_VFLSEGSTD) -+DECLARE_INSN(vfld, MATCH_VFLD, MASK_VFLD) -+DECLARE_INSN(fmadd_s, MATCH_FMADD_S, MASK_FMADD_S) -+DECLARE_INSN(vflw, MATCH_VFLW, MASK_VFLW) -+DECLARE_INSN(fmadd_d, MATCH_FMADD_D, MASK_FMADD_D) -+DECLARE_INSN(fmadd_h, MATCH_FMADD_H, MASK_FMADD_H) -+DECLARE_INSN(sret, MATCH_SRET, MASK_SRET) -+DECLARE_INSN(vssegw, MATCH_VSSEGW, MASK_VSSEGW) -+DECLARE_INSN(custom0_rd_rs1, MATCH_CUSTOM0_RD_RS1, MASK_CUSTOM0_RD_RS1) -+DECLARE_INSN(vssegh, MATCH_VSSEGH, MASK_VSSEGH) -+DECLARE_INSN(frcsr, MATCH_FRCSR, MASK_FRCSR) -+DECLARE_INSN(vssegd, MATCH_VSSEGD, MASK_VSSEGD) -+DECLARE_INSN(vssegb, MATCH_VSSEGB, MASK_VSSEGB) -+DECLARE_INSN(fmin_h, MATCH_FMIN_H, MASK_FMIN_H) -+DECLARE_INSN(fmin_d, MATCH_FMIN_D, MASK_FMIN_D) -+DECLARE_INSN(bltu, MATCH_BLTU, MASK_BLTU) -+DECLARE_INSN(fmin_s, MATCH_FMIN_S, MASK_FMIN_S) -+DECLARE_INSN(srli_rv32, MATCH_SRLI_RV32, MASK_SRLI_RV32) -+DECLARE_INSN(slliw, MATCH_SLLIW, MASK_SLLIW) -+DECLARE_INSN(fmax_s, MATCH_FMAX_S, MASK_FMAX_S) -+DECLARE_INSN(fcvt_d_h, MATCH_FCVT_D_H, MASK_FCVT_D_H) -+DECLARE_INSN(fcvt_d_w, MATCH_FCVT_D_W, MASK_FCVT_D_W) -+DECLARE_INSN(add, MATCH_ADD, MASK_ADD) -+DECLARE_INSN(fcvt_d_s, MATCH_FCVT_D_S, MASK_FCVT_D_S) -+DECLARE_INSN(fmax_d, MATCH_FMAX_D, MASK_FMAX_D) -+DECLARE_INSN(bne, MATCH_BNE, MASK_BNE) -+DECLARE_INSN(custom1_rd, MATCH_CUSTOM1_RD, MASK_CUSTOM1_RD) -+DECLARE_INSN(fsrm, MATCH_FSRM, MASK_FSRM) -+DECLARE_INSN(fdiv_d, MATCH_FDIV_D, MASK_FDIV_D) -+DECLARE_INSN(vsw, MATCH_VSW, MASK_VSW) -+DECLARE_INSN(fcvt_l_s, MATCH_FCVT_L_S, MASK_FCVT_L_S) -+DECLARE_INSN(fdiv_h, MATCH_FDIV_H, MASK_FDIV_H) -+DECLARE_INSN(vsb, MATCH_VSB, MASK_VSB) -+DECLARE_INSN(fdiv_s, MATCH_FDIV_S, MASK_FDIV_S) -+DECLARE_INSN(fsrmi, MATCH_FSRMI, MASK_FSRMI) -+DECLARE_INSN(fcvt_l_h, MATCH_FCVT_L_H, MASK_FCVT_L_H) -+DECLARE_INSN(vsh, MATCH_VSH, MASK_VSH) -+DECLARE_INSN(fcvt_l_d, MATCH_FCVT_L_D, MASK_FCVT_L_D) -+DECLARE_INSN(fcvt_h_s, MATCH_FCVT_H_S, MASK_FCVT_H_S) -+DECLARE_INSN(scall, MATCH_SCALL, MASK_SCALL) -+DECLARE_INSN(fsflagsi, MATCH_FSFLAGSI, MASK_FSFLAGSI) -+DECLARE_INSN(fcvt_h_w, MATCH_FCVT_H_W, MASK_FCVT_H_W) -+DECLARE_INSN(fcvt_h_l, MATCH_FCVT_H_L, MASK_FCVT_H_L) -+DECLARE_INSN(srliw, MATCH_SRLIW, MASK_SRLIW) -+DECLARE_INSN(fcvt_s_lu, MATCH_FCVT_S_LU, MASK_FCVT_S_LU) -+DECLARE_INSN(fcvt_h_d, MATCH_FCVT_H_D, MASK_FCVT_H_D) -+DECLARE_INSN(sbreak, MATCH_SBREAK, MASK_SBREAK) -+DECLARE_INSN(rdinstreth, MATCH_RDINSTRETH, MASK_RDINSTRETH) -+DECLARE_INSN(sra, MATCH_SRA, MASK_SRA) -+DECLARE_INSN(bge, MATCH_BGE, MASK_BGE) -+DECLARE_INSN(srl, MATCH_SRL, MASK_SRL) -+DECLARE_INSN(venqcmd, MATCH_VENQCMD, MASK_VENQCMD) -+DECLARE_INSN(or, MATCH_OR, MASK_OR) -+DECLARE_INSN(subw, MATCH_SUBW, MASK_SUBW) -+DECLARE_INSN(fmv_x_d, MATCH_FMV_X_D, MASK_FMV_X_D) -+DECLARE_INSN(rdtime, MATCH_RDTIME, MASK_RDTIME) -+DECLARE_INSN(amoadd_d, MATCH_AMOADD_D, MASK_AMOADD_D) -+DECLARE_INSN(amomax_w, MATCH_AMOMAX_W, MASK_AMOMAX_W) -+DECLARE_INSN(c_move, MATCH_C_MOVE, MASK_C_MOVE) -+DECLARE_INSN(fmovn, MATCH_FMOVN, MASK_FMOVN) -+DECLARE_INSN(c_fsw, MATCH_C_FSW, MASK_C_FSW) -+DECLARE_INSN(amoadd_w, MATCH_AMOADD_W, MASK_AMOADD_W) -+DECLARE_INSN(amomax_d, MATCH_AMOMAX_D, MASK_AMOMAX_D) -+DECLARE_INSN(fmovz, MATCH_FMOVZ, MASK_FMOVZ) -+DECLARE_INSN(custom1_rs1_rs2, MATCH_CUSTOM1_RS1_RS2, MASK_CUSTOM1_RS1_RS2) -+DECLARE_INSN(fmv_x_h, MATCH_FMV_X_H, MASK_FMV_X_H) -+DECLARE_INSN(vsd, MATCH_VSD, MASK_VSD) -+DECLARE_INSN(vlsegstw, MATCH_VLSEGSTW, MASK_VLSEGSTW) -+DECLARE_INSN(c_addi, MATCH_C_ADDI, MASK_C_ADDI) -+DECLARE_INSN(c_slliw, MATCH_C_SLLIW, MASK_C_SLLIW) -+DECLARE_INSN(vlsegstb, MATCH_VLSEGSTB, MASK_VLSEGSTB) -+DECLARE_INSN(vlsegstd, MATCH_VLSEGSTD, MASK_VLSEGSTD) -+DECLARE_INSN(vlsegsth, MATCH_VLSEGSTH, MASK_VLSEGSTH) -+DECLARE_INSN(mulhu, MATCH_MULHU, MASK_MULHU) -+DECLARE_INSN(amomin_w, MATCH_AMOMIN_W, MASK_AMOMIN_W) -+DECLARE_INSN(c_slli32, MATCH_C_SLLI32, MASK_C_SLLI32) -+DECLARE_INSN(c_add3, MATCH_C_ADD3, MASK_C_ADD3) -+DECLARE_INSN(vgetvl, MATCH_VGETVL, MASK_VGETVL) -+DECLARE_INSN(amomin_d, MATCH_AMOMIN_D, MASK_AMOMIN_D) -+DECLARE_INSN(fcvt_w_h, MATCH_FCVT_W_H, MASK_FCVT_W_H) -+DECLARE_INSN(vlsegb, MATCH_VLSEGB, MASK_VLSEGB) -+DECLARE_INSN(fsd, MATCH_FSD, MASK_FSD) -+DECLARE_INSN(vlsegd, MATCH_VLSEGD, MASK_VLSEGD) -+DECLARE_INSN(fsh, MATCH_FSH, MASK_FSH) -+DECLARE_INSN(vlsegh, MATCH_VLSEGH, MASK_VLSEGH) -+DECLARE_INSN(c_sub, MATCH_C_SUB, MASK_C_SUB) -+DECLARE_INSN(vlsegw, MATCH_VLSEGW, MASK_VLSEGW) -+DECLARE_INSN(fsw, MATCH_FSW, MASK_FSW) -+DECLARE_INSN(c_j, MATCH_C_J, MASK_C_J) -+#endif -+#ifdef DECLARE_CSR -+DECLARE_CSR(fflags, CSR_FFLAGS) -+DECLARE_CSR(frm, CSR_FRM) -+DECLARE_CSR(fcsr, CSR_FCSR) -+DECLARE_CSR(stats, CSR_STATS) -+DECLARE_CSR(sup0, CSR_SUP0) -+DECLARE_CSR(sup1, CSR_SUP1) -+DECLARE_CSR(epc, CSR_EPC) -+DECLARE_CSR(badvaddr, CSR_BADVADDR) -+DECLARE_CSR(ptbr, CSR_PTBR) -+DECLARE_CSR(asid, CSR_ASID) -+DECLARE_CSR(count, CSR_COUNT) -+DECLARE_CSR(compare, CSR_COMPARE) -+DECLARE_CSR(evec, CSR_EVEC) -+DECLARE_CSR(cause, CSR_CAUSE) -+DECLARE_CSR(status, CSR_STATUS) -+DECLARE_CSR(hartid, CSR_HARTID) -+DECLARE_CSR(impl, CSR_IMPL) -+DECLARE_CSR(fatc, CSR_FATC) -+DECLARE_CSR(send_ipi, CSR_SEND_IPI) -+DECLARE_CSR(clear_ipi, CSR_CLEAR_IPI) -+DECLARE_CSR(reset, CSR_RESET) -+DECLARE_CSR(tohost, CSR_TOHOST) -+DECLARE_CSR(fromhost, CSR_FROMHOST) -+DECLARE_CSR(cycle, CSR_CYCLE) -+DECLARE_CSR(time, CSR_TIME) -+DECLARE_CSR(instret, CSR_INSTRET) -+DECLARE_CSR(uarch0, CSR_UARCH0) -+DECLARE_CSR(uarch1, CSR_UARCH1) -+DECLARE_CSR(uarch2, CSR_UARCH2) -+DECLARE_CSR(uarch3, CSR_UARCH3) -+DECLARE_CSR(uarch4, CSR_UARCH4) -+DECLARE_CSR(uarch5, CSR_UARCH5) -+DECLARE_CSR(uarch6, CSR_UARCH6) -+DECLARE_CSR(uarch7, CSR_UARCH7) -+DECLARE_CSR(uarch8, CSR_UARCH8) -+DECLARE_CSR(uarch9, CSR_UARCH9) -+DECLARE_CSR(uarch10, CSR_UARCH10) -+DECLARE_CSR(uarch11, CSR_UARCH11) -+DECLARE_CSR(uarch12, CSR_UARCH12) -+DECLARE_CSR(uarch13, CSR_UARCH13) -+DECLARE_CSR(uarch14, CSR_UARCH14) -+DECLARE_CSR(uarch15, CSR_UARCH15) -+DECLARE_CSR(counth, CSR_COUNTH) -+DECLARE_CSR(cycleh, CSR_CYCLEH) -+DECLARE_CSR(timeh, CSR_TIMEH) -+DECLARE_CSR(instreth, CSR_INSTRETH) -+#endif -+#ifdef DECLARE_CAUSE -+DECLARE_CAUSE("fflags", CAUSE_FFLAGS) -+DECLARE_CAUSE("frm", CAUSE_FRM) -+DECLARE_CAUSE("fcsr", CAUSE_FCSR) -+DECLARE_CAUSE("stats", CAUSE_STATS) -+DECLARE_CAUSE("sup0", CAUSE_SUP0) -+DECLARE_CAUSE("sup1", CAUSE_SUP1) -+DECLARE_CAUSE("epc", CAUSE_EPC) -+DECLARE_CAUSE("badvaddr", CAUSE_BADVADDR) -+DECLARE_CAUSE("ptbr", CAUSE_PTBR) -+DECLARE_CAUSE("asid", CAUSE_ASID) -+DECLARE_CAUSE("count", CAUSE_COUNT) -+DECLARE_CAUSE("compare", CAUSE_COMPARE) -+DECLARE_CAUSE("evec", CAUSE_EVEC) -+DECLARE_CAUSE("cause", CAUSE_CAUSE) -+DECLARE_CAUSE("status", CAUSE_STATUS) -+DECLARE_CAUSE("hartid", CAUSE_HARTID) -+DECLARE_CAUSE("impl", CAUSE_IMPL) -+DECLARE_CAUSE("fatc", CAUSE_FATC) -+DECLARE_CAUSE("send_ipi", CAUSE_SEND_IPI) -+DECLARE_CAUSE("clear_ipi", CAUSE_CLEAR_IPI) -+DECLARE_CAUSE("reset", CAUSE_RESET) -+DECLARE_CAUSE("tohost", CAUSE_TOHOST) -+DECLARE_CAUSE("fromhost", CAUSE_FROMHOST) -+DECLARE_CAUSE("cycle", CAUSE_CYCLE) -+DECLARE_CAUSE("time", CAUSE_TIME) -+DECLARE_CAUSE("instret", CAUSE_INSTRET) -+DECLARE_CAUSE("uarch0", CAUSE_UARCH0) -+DECLARE_CAUSE("uarch1", CAUSE_UARCH1) -+DECLARE_CAUSE("uarch2", CAUSE_UARCH2) -+DECLARE_CAUSE("uarch3", CAUSE_UARCH3) -+DECLARE_CAUSE("uarch4", CAUSE_UARCH4) -+DECLARE_CAUSE("uarch5", CAUSE_UARCH5) -+DECLARE_CAUSE("uarch6", CAUSE_UARCH6) -+DECLARE_CAUSE("uarch7", CAUSE_UARCH7) -+DECLARE_CAUSE("uarch8", CAUSE_UARCH8) -+DECLARE_CAUSE("uarch9", CAUSE_UARCH9) -+DECLARE_CAUSE("uarch10", CAUSE_UARCH10) -+DECLARE_CAUSE("uarch11", CAUSE_UARCH11) -+DECLARE_CAUSE("uarch12", CAUSE_UARCH12) -+DECLARE_CAUSE("uarch13", CAUSE_UARCH13) -+DECLARE_CAUSE("uarch14", CAUSE_UARCH14) -+DECLARE_CAUSE("uarch15", CAUSE_UARCH15) -+DECLARE_CAUSE("counth", CAUSE_COUNTH) -+DECLARE_CAUSE("cycleh", CAUSE_CYCLEH) -+DECLARE_CAUSE("timeh", CAUSE_TIMEH) -+DECLARE_CAUSE("instreth", CAUSE_INSTRETH) -+#endif -diff --git a/gcc-4.6.1/gcc/config/riscv/riscv-protos.h b/gcc-4.6.1/gcc/config/riscv/riscv-protos.h -new file mode 100644 -index 0000000..429da71 ---- /dev/null -+++ gcc-4.6.1/gcc/config/riscv/riscv-protos.h -@@ -0,0 +1,90 @@ -+/* Definition of RISC-V target for GNU compiler. -+ Copyright (C) 2011-2014 Free Software Foundation, Inc. -+ Contributed by Andrew Waterman (waterman@cs.berkeley.edu) at UC Berkeley. -+ Based on MIPS target for GNU compiler. -+ -+This file is part of GCC. -+ -+GCC is free software; you can redistribute it and/or modify -+it under the terms of the GNU General Public License as published by -+the Free Software Foundation; either version 3, or (at your option) -+any later version. -+ -+GCC is distributed in the hope that it will be useful, -+but WITHOUT ANY WARRANTY; without even the implied warranty of -+MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -+GNU General Public License for more details. -+ -+You should have received a copy of the GNU General Public License -+along with GCC; see the file COPYING3. If not see -+. */ -+ -+#ifndef GCC_RISCV_PROTOS_H -+#define GCC_RISCV_PROTOS_H -+ -+enum mips_symbol_type { -+ SYMBOL_ABSOLUTE, -+ SYMBOL_GOT_DISP, -+ SYMBOL_TLS, -+ SYMBOL_TLS_LE, -+ SYMBOL_TLS_IE -+}; -+#define NUM_SYMBOL_TYPES (SYMBOL_TLS_IE + 1) -+ -+extern bool mips_symbolic_constant_p (rtx, enum mips_symbol_type *); -+extern int riscv_regno_mode_ok_for_base_p (int, enum machine_mode, bool); -+extern int riscv_address_insns (rtx, enum machine_mode, bool); -+extern int riscv_const_insns (rtx); -+extern int riscv_split_const_insns (rtx); -+extern int mips_load_store_insns (rtx, rtx); -+extern rtx mips_emit_move (rtx, rtx); -+extern bool mips_split_symbol (rtx, rtx, enum machine_mode, rtx *); -+extern rtx mips_unspec_address (rtx, enum mips_symbol_type); -+extern void mips_move_integer (rtx, rtx, HOST_WIDE_INT); -+extern bool mips_legitimize_move (enum machine_mode, rtx, rtx); -+extern bool mips_legitimize_vector_move (enum machine_mode, rtx, rtx); -+ -+extern rtx mips_subword (rtx, bool); -+extern bool mips_split_64bit_move_p (rtx, rtx); -+extern void mips_split_doubleword_move (rtx, rtx); -+extern const char *mips_output_move (rtx, rtx); -+extern const char *mips_riscv_output_vector_move (enum machine_mode, rtx, rtx); -+#ifdef RTX_CODE -+extern void riscv_expand_scc (rtx *); -+extern void riscv_expand_conditional_branch (rtx *); -+#endif -+extern rtx riscv_expand_call (bool, rtx, rtx, rtx); -+extern void riscv_expand_fcc_reload (rtx, rtx, rtx); -+extern void riscv_set_return_address (rtx, rtx); -+extern bool riscv_expand_block_move (rtx, rtx, rtx); -+extern void riscv_expand_synci_loop (rtx, rtx); -+ -+extern bool riscv_expand_ext_as_unaligned_load (rtx, rtx, HOST_WIDE_INT, -+ HOST_WIDE_INT); -+extern bool riscv_expand_ins_as_unaligned_store (rtx, rtx, HOST_WIDE_INT, -+ HOST_WIDE_INT); -+extern void mips_order_regs_for_local_alloc (void); -+ -+extern rtx riscv_return_addr (int, rtx); -+extern HOST_WIDE_INT riscv_initial_elimination_offset (int, int); -+extern void riscv_expand_prologue (void); -+extern void riscv_expand_epilogue (bool); -+extern bool mips_can_use_return_insn (void); -+extern rtx riscv_function_value (const_tree, const_tree, enum machine_mode); -+ -+extern enum reg_class riscv_secondary_reload_class (enum reg_class, -+ enum machine_mode, -+ rtx, bool); -+extern int riscv_class_max_nregs (enum reg_class, enum machine_mode); -+ -+extern unsigned int riscv_hard_regno_nregs (int, enum machine_mode); -+ -+extern void irix_asm_output_align (FILE *, unsigned); -+extern const char *current_section_name (void); -+extern unsigned int current_section_flags (void); -+ -+extern void riscv_expand_vector_init (rtx, rtx); -+ -+extern bool riscv_size_ok_for_small_data_p (int size); -+ -+#endif /* ! GCC_RISCV_PROTOS_H */ -diff --git a/gcc-4.6.1/gcc/config/riscv/riscv.c b/gcc-4.6.1/gcc/config/riscv/riscv.c -new file mode 100644 -index 0000000..0338fa0 ---- /dev/null -+++ gcc-4.6.1/gcc/config/riscv/riscv.c -@@ -0,0 +1,4750 @@ -+/* Subroutines used for code generation for RISC-V. -+ Copyright (C) 2011-2014 Free Software Foundation, Inc. -+ Contributed by Andrew Waterman (waterman@cs.berkeley.edu) at UC Berkeley. -+ Based on MIPS target for GNU compiler. -+ -+This file is part of GCC. -+ -+GCC is free software; you can redistribute it and/or modify -+it under the terms of the GNU General Public License as published by -+the Free Software Foundation; either version 3, or (at your option) -+any later version. -+ -+GCC is distributed in the hope that it will be useful, -+but WITHOUT ANY WARRANTY; without even the implied warranty of -+MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -+GNU General Public License for more details. -+ -+You should have received a copy of the GNU General Public License -+along with GCC; see the file COPYING3. If not see -+. */ -+ -+#include "config.h" -+#include "system.h" -+#include "coretypes.h" -+#include "tm.h" -+#include "rtl.h" -+#include "regs.h" -+#include "hard-reg-set.h" -+#include "insn-config.h" -+#include "conditions.h" -+#include "insn-attr.h" -+#include "recog.h" -+#include "output.h" -+#include "tree.h" -+#include "function.h" -+#include "expr.h" -+#include "optabs.h" -+#include "libfuncs.h" -+#include "flags.h" -+#include "reload.h" -+#include "tm_p.h" -+#include "ggc.h" -+#include "gstab.h" -+#include "hashtab.h" -+#include "debug.h" -+#include "target.h" -+#include "target-def.h" -+#include "integrate.h" -+#include "langhooks.h" -+#include "cfglayout.h" -+#include "sched-int.h" -+#include "gimple.h" -+#include "bitmap.h" -+#include "diagnostic.h" -+#include "target-globals.h" -+#include "symcat.h" -+#include -+ -+/* True if X is an UNSPEC wrapper around a SYMBOL_REF or LABEL_REF. */ -+#define UNSPEC_ADDRESS_P(X) \ -+ (GET_CODE (X) == UNSPEC \ -+ && XINT (X, 1) >= UNSPEC_ADDRESS_FIRST \ -+ && XINT (X, 1) < UNSPEC_ADDRESS_FIRST + NUM_SYMBOL_TYPES) -+ -+/* Extract the symbol or label from UNSPEC wrapper X. */ -+#define UNSPEC_ADDRESS(X) \ -+ XVECEXP (X, 0, 0) -+ -+/* Extract the symbol type from UNSPEC wrapper X. */ -+#define UNSPEC_ADDRESS_TYPE(X) \ -+ ((enum mips_symbol_type) (XINT (X, 1) - UNSPEC_ADDRESS_FIRST)) -+ -+/* The maximum distance between the top of the stack frame and the -+ value sp has when we save and restore registers. This is set by the -+ range of load/store offsets and must also preserve stack alignment. */ -+#define RISCV_MAX_FIRST_STACK_STEP (RISCV_IMM_REACH/2 - 16) -+ -+/* True if INSN is a mips.md pattern or asm statement. */ -+#define USEFUL_INSN_P(INSN) \ -+ (NONDEBUG_INSN_P (INSN) \ -+ && GET_CODE (PATTERN (INSN)) != USE \ -+ && GET_CODE (PATTERN (INSN)) != CLOBBER \ -+ && GET_CODE (PATTERN (INSN)) != ADDR_VEC \ -+ && GET_CODE (PATTERN (INSN)) != ADDR_DIFF_VEC) -+ -+/* True if bit BIT is set in VALUE. */ -+#define BITSET_P(VALUE, BIT) (((VALUE) & (1 << (BIT))) != 0) -+ -+/* Classifies an address. -+ -+ ADDRESS_REG -+ A natural register + offset address. The register satisfies -+ mips_valid_base_register_p and the offset is a const_arith_operand. -+ -+ ADDRESS_LO_SUM -+ A LO_SUM rtx. The first operand is a valid base register and -+ the second operand is a symbolic address. -+ -+ ADDRESS_CONST_INT -+ A signed 16-bit constant address. -+ -+ ADDRESS_SYMBOLIC: -+ A constant symbolic address. */ -+enum mips_address_type { -+ ADDRESS_REG, -+ ADDRESS_LO_SUM, -+ ADDRESS_CONST_INT, -+ ADDRESS_SYMBOLIC -+}; -+ -+/* Macros to create an enumeration identifier for a function prototype. */ -+#define RISCV_FTYPE_NAME1(A, B) RISCV_##A##_FTYPE_##B -+#define RISCV_FTYPE_NAME2(A, B, C) RISCV_##A##_FTYPE_##B##_##C -+#define RISCV_FTYPE_NAME3(A, B, C, D) RISCV_##A##_FTYPE_##B##_##C##_##D -+#define RISCV_FTYPE_NAME4(A, B, C, D, E) RISCV_##A##_FTYPE_##B##_##C##_##D##_##E -+ -+/* Classifies the prototype of a built-in function. */ -+enum mips_function_type { -+#define DEF_RISCV_FTYPE(NARGS, LIST) RISCV_FTYPE_NAME##NARGS LIST, -+#include "config/riscv/riscv-ftypes.def" -+#undef DEF_RISCV_FTYPE -+ RISCV_MAX_FTYPE_MAX -+}; -+ -+/* Specifies how a built-in function should be converted into rtl. */ -+enum mips_builtin_type { -+ /* The function corresponds directly to an .md pattern. The return -+ value is mapped to operand 0 and the arguments are mapped to -+ operands 1 and above. */ -+ RISCV_BUILTIN_DIRECT, -+ -+ /* The function corresponds directly to an .md pattern. There is no return -+ value and the arguments are mapped to operands 0 and above. */ -+ RISCV_BUILTIN_DIRECT_NO_TARGET -+}; -+ -+/* Information about a function's frame layout. */ -+struct GTY(()) riscv_frame_info { -+ /* The size of the frame in bytes. */ -+ HOST_WIDE_INT total_size; -+ -+ /* Bit X is set if the function saves or restores GPR X. */ -+ unsigned int mask; -+ -+ /* Likewise FPR X. */ -+ unsigned int fmask; -+ -+ /* Offsets of fixed-point and floating-point save areas from frame bottom */ -+ HOST_WIDE_INT gp_sp_offset; -+ HOST_WIDE_INT fp_sp_offset; -+ -+ /* Offset of virtual frame pointer from stack pointer/frame bottom */ -+ HOST_WIDE_INT frame_pointer_offset; -+ -+ /* Offset of hard frame pointer from stack pointer/frame bottom */ -+ HOST_WIDE_INT hard_frame_pointer_offset; -+ -+ /* The offset of arg_pointer_rtx from the bottom of the frame. */ -+ HOST_WIDE_INT arg_pointer_offset; -+}; -+ -+struct GTY(()) machine_function { -+ /* The number of extra stack bytes taken up by register varargs. -+ This area is allocated by the callee at the very top of the frame. */ -+ int varargs_size; -+ -+ /* The current frame information, calculated by riscv_compute_frame_info. */ -+ struct riscv_frame_info frame; -+}; -+ -+/* Information about a single argument. */ -+struct mips_arg_info { -+ /* True if the argument is passed in a floating-point register, or -+ would have been if we hadn't run out of registers. */ -+ bool fpr_p; -+ -+ /* The number of words passed in registers, rounded up. */ -+ unsigned int reg_words; -+ -+ /* For EABI, the offset of the first register from GP_ARG_FIRST or -+ FP_ARG_FIRST. For other ABIs, the offset of the first register from -+ the start of the ABI's argument structure (see the CUMULATIVE_ARGS -+ comment for details). -+ -+ The value is MAX_ARGS_IN_REGISTERS if the argument is passed entirely -+ on the stack. */ -+ unsigned int reg_offset; -+ -+ /* The number of words that must be passed on the stack, rounded up. */ -+ unsigned int stack_words; -+ -+ /* The offset from the start of the stack overflow area of the argument's -+ first stack word. Only meaningful when STACK_WORDS is nonzero. */ -+ unsigned int stack_offset; -+}; -+ -+/* Information about an address described by mips_address_type. -+ -+ ADDRESS_CONST_INT -+ No fields are used. -+ -+ ADDRESS_REG -+ REG is the base register and OFFSET is the constant offset. -+ -+ ADDRESS_LO_SUM -+ REG and OFFSET are the operands to the LO_SUM and SYMBOL_TYPE -+ is the type of symbol it references. -+ -+ ADDRESS_SYMBOLIC -+ SYMBOL_TYPE is the type of symbol that the address references. */ -+struct mips_address_info { -+ enum mips_address_type type; -+ rtx reg; -+ rtx offset; -+ enum mips_symbol_type symbol_type; -+}; -+ -+/* One stage in a constant building sequence. These sequences have -+ the form: -+ -+ A = VALUE[0] -+ A = A CODE[1] VALUE[1] -+ A = A CODE[2] VALUE[2] -+ ... -+ -+ where A is an accumulator, each CODE[i] is a binary rtl operation -+ and each VALUE[i] is a constant integer. CODE[0] is undefined. */ -+struct mips_integer_op { -+ enum rtx_code code; -+ unsigned HOST_WIDE_INT value; -+}; -+ -+/* The largest number of operations needed to load an integer constant. -+ The worst accepted case for 64-bit constants is LUI,ORI,SLL,ORI,SLL,ORI. -+ When the lowest bit is clear, we can try, but reject a sequence with -+ an extra SLL at the end. */ -+#define RISCV_MAX_INTEGER_OPS 32 -+ -+/* Costs of various operations on the different architectures. */ -+ -+struct mips_rtx_cost_data -+{ -+ unsigned short fp_add; -+ unsigned short fp_mult_sf; -+ unsigned short fp_mult_df; -+ unsigned short fp_div_sf; -+ unsigned short fp_div_df; -+ unsigned short int_mult_si; -+ unsigned short int_mult_di; -+ unsigned short int_div_si; -+ unsigned short int_div_di; -+ unsigned short branch_cost; -+ unsigned short memory_latency; -+}; -+ -+/* Global variables for machine-dependent things. */ -+ -+/* The processor that we should tune the code for. */ -+enum processor riscv_tune; -+ -+/* Which cost information to use. */ -+static const struct mips_rtx_cost_data *mips_cost; -+ -+/* Index [M][R] is true if register R is allowed to hold a value of mode M. */ -+bool riscv_hard_regno_mode_ok[(int) MAX_MACHINE_MODE][FIRST_PSEUDO_REGISTER]; -+ -+/* riscv_lo_relocs[X] is the relocation to use when a symbol of type X -+ appears in a LO_SUM. It can be null if such LO_SUMs aren't valid or -+ if they are matched by a special .md file pattern. */ -+const char *riscv_lo_relocs[NUM_SYMBOL_TYPES]; -+ -+/* Likewise for HIGHs. */ -+const char *riscv_hi_relocs[NUM_SYMBOL_TYPES]; -+ -+/* Index R is the smallest register class that contains register R. */ -+const enum reg_class riscv_regno_to_class[FIRST_PSEUDO_REGISTER] = { -+ GR_REGS, GR_REGS, GR_REGS, GR_REGS, -+ GR_REGS, GR_REGS, GR_REGS, GR_REGS, -+ GR_REGS, GR_REGS, GR_REGS, GR_REGS, -+ GR_REGS, GR_REGS, GR_REGS, GR_REGS, -+ GR_REGS, GR_REGS, GR_REGS, GR_REGS, -+ GR_REGS, GR_REGS, GR_REGS, GR_REGS, -+ GR_REGS, GR_REGS, T_REGS, T_REGS, -+ T_REGS, T_REGS, T_REGS, GR_REGS, -+ FP_REGS, FP_REGS, FP_REGS, FP_REGS, -+ FP_REGS, FP_REGS, FP_REGS, FP_REGS, -+ FP_REGS, FP_REGS, FP_REGS, FP_REGS, -+ FP_REGS, FP_REGS, FP_REGS, FP_REGS, -+ FP_REGS, FP_REGS, FP_REGS, FP_REGS, -+ FP_REGS, FP_REGS, FP_REGS, FP_REGS, -+ FP_REGS, FP_REGS, FP_REGS, FP_REGS, -+ FP_REGS, FP_REGS, FP_REGS, FP_REGS, -+ FRAME_REGS, FRAME_REGS, -+}; -+ -+/* The value of TARGET_ATTRIBUTE_TABLE. */ -+static const struct attribute_spec mips_attribute_table[] = { -+ /* { name, min_len, max_len, decl_req, type_req, fn_type_req, handler } */ -+ { "long_call", 0, 0, false, true, true, NULL }, -+ { "far", 0, 0, false, true, true, NULL }, -+ { "near", 0, 0, false, true, true, NULL }, -+ { NULL, 0, 0, false, false, false, NULL } -+}; -+ -+/* A table describing all the processors GCC knows about. Names are -+ matched in the order listed. The first mention of an ISA level is -+ taken as the canonical name for that ISA. -+ -+ To ease comparison, please keep this table in the same order -+ as GAS's riscv_cpu_info_table. Please also make sure that -+ MIPS_ISA_LEVEL_SPEC and MIPS_ARCH_FLOAT_SPEC handle all -march -+ options correctly. */ -+static const struct riscv_cpu_info riscv_cpu_info_table[] = { -+ /* Entries for generic ISAs. */ -+ { "rocket", PROCESSOR_ROCKET, 0 }, -+}; -+ -+/* Default costs. If these are used for a processor we should look -+ up the actual costs. */ -+#define DEFAULT_COSTS COSTS_N_INSNS (8), /* fp_add */ \ -+ COSTS_N_INSNS (8), /* fp_mult_sf */ \ -+ COSTS_N_INSNS (8), /* fp_mult_df */ \ -+ COSTS_N_INSNS (20), /* fp_div_sf */ \ -+ COSTS_N_INSNS (20), /* fp_div_df */ \ -+ COSTS_N_INSNS (4), /* int_mult_si */ \ -+ COSTS_N_INSNS (4), /* int_mult_di */ \ -+ COSTS_N_INSNS (6), /* int_div_si */ \ -+ COSTS_N_INSNS (6), /* int_div_di */ \ -+ 2, /* branch_cost */ \ -+ 7 /* memory_latency */ -+ -+/* Floating-point costs for processors without an FPU. Just assume that -+ all floating-point libcalls are very expensive. */ -+#define SOFT_FP_COSTS COSTS_N_INSNS (256), /* fp_add */ \ -+ COSTS_N_INSNS (256), /* fp_mult_sf */ \ -+ COSTS_N_INSNS (256), /* fp_mult_df */ \ -+ COSTS_N_INSNS (256), /* fp_div_sf */ \ -+ COSTS_N_INSNS (256) /* fp_div_df */ -+ -+/* Costs to use when optimizing for size. */ -+static const struct mips_rtx_cost_data mips_rtx_cost_optimize_size = { -+ COSTS_N_INSNS (1), /* fp_add */ -+ COSTS_N_INSNS (1), /* fp_mult_sf */ -+ COSTS_N_INSNS (1), /* fp_mult_df */ -+ COSTS_N_INSNS (1), /* fp_div_sf */ -+ COSTS_N_INSNS (1), /* fp_div_df */ -+ COSTS_N_INSNS (1), /* int_mult_si */ -+ COSTS_N_INSNS (1), /* int_mult_di */ -+ COSTS_N_INSNS (1), /* int_div_si */ -+ COSTS_N_INSNS (1), /* int_div_di */ -+ 1, /* branch_cost */ -+ 1 /* memory_latency */ -+}; -+ -+/* Costs to use when optimizing for speed, indexed by processor. */ -+static const struct mips_rtx_cost_data -+ mips_rtx_cost_data[NUM_PROCESSOR_VALUES] = { -+ { /* Rocket */ DEFAULT_COSTS}, -+}; -+ -+static int mips_register_move_cost (enum machine_mode, reg_class_t, -+ reg_class_t); -+static unsigned int mips_function_arg_boundary (enum machine_mode, const_tree); -+ -+/* Predicates to test for presence of "near" and "far"/"long_call" -+ attributes on the given TYPE. */ -+ -+static bool -+mips_near_type_p (const_tree type) -+{ -+ return lookup_attribute ("near", TYPE_ATTRIBUTES (type)) != NULL; -+} -+ -+static bool -+mips_far_type_p (const_tree type) -+{ -+ return (lookup_attribute ("long_call", TYPE_ATTRIBUTES (type)) != NULL -+ || lookup_attribute ("far", TYPE_ATTRIBUTES (type)) != NULL); -+} -+ -+/* Implement TARGET_COMP_TYPE_ATTRIBUTES. */ -+ -+static int -+mips_comp_type_attributes (const_tree type1, const_tree type2) -+{ -+ /* Disallow mixed near/far attributes. */ -+ if (mips_far_type_p (type1) && mips_near_type_p (type2)) -+ return 0; -+ if (mips_near_type_p (type1) && mips_far_type_p (type2)) -+ return 0; -+ return 1; -+} -+ -+/* If X is a PLUS of a CONST_INT, return the two terms in *BASE_PTR -+ and *OFFSET_PTR. Return X in *BASE_PTR and 0 in *OFFSET_PTR otherwise. */ -+ -+static void -+mips_split_plus (rtx x, rtx *base_ptr, HOST_WIDE_INT *offset_ptr) -+{ -+ if (GET_CODE (x) == PLUS && GET_CODE (XEXP (x, 1)) == CONST_INT) -+ { -+ *base_ptr = XEXP (x, 0); -+ *offset_ptr = INTVAL (XEXP (x, 1)); -+ } -+ else -+ { -+ *base_ptr = x; -+ *offset_ptr = 0; -+ } -+} -+ -+/* Fill CODES with a sequence of rtl operations to load VALUE. -+ Return the number of operations needed. */ -+ -+static int -+riscv_build_integer_simple (struct mips_integer_op *codes, HOST_WIDE_INT value) -+{ -+ HOST_WIDE_INT low_part = RISCV_CONST_LOW_PART (value); -+ int cost = INT_MAX, alt_cost; -+ struct mips_integer_op alt_codes[RISCV_MAX_INTEGER_OPS]; -+ -+ if (SMALL_OPERAND (value) || LUI_OPERAND (value)) -+ { -+ /* Simply ADDI or LUI */ -+ codes[0].code = UNKNOWN; -+ codes[0].value = value; -+ return 1; -+ } -+ -+ /* End with ADDI */ -+ if (low_part != 0) -+ { -+ cost = 1 + riscv_build_integer_simple (codes, value - low_part); -+ codes[cost-1].code = PLUS; -+ codes[cost-1].value = low_part; -+ } -+ -+ /* End with XORI */ -+ if (low_part < 0) -+ { -+ alt_cost = 1 + riscv_build_integer_simple (alt_codes, value ^ low_part); -+ alt_codes[alt_cost-1].code = XOR; -+ alt_codes[alt_cost-1].value = low_part; -+ if (alt_cost < cost) -+ cost = alt_cost, memcpy (codes, alt_codes, sizeof(alt_codes)); -+ } -+ -+ /* Eliminate trailing zeros and end with SLLI */ -+ if ((value & 1) == 0) -+ { -+ int shift = __builtin_ctzl(value); -+ alt_cost = 1 + riscv_build_integer_simple (alt_codes, value >> shift); -+ alt_codes[alt_cost-1].code = ASHIFT; -+ alt_codes[alt_cost-1].value = shift; -+ if (alt_cost < cost) -+ cost = alt_cost, memcpy (codes, alt_codes, sizeof(alt_codes)); -+ } -+ -+ gcc_assert (cost <= RISCV_MAX_INTEGER_OPS); -+ return cost; -+} -+ -+static int -+riscv_build_integer (struct mips_integer_op *codes, HOST_WIDE_INT value) -+{ -+ int cost = riscv_build_integer_simple (codes, value); -+ -+ /* Eliminate leading zeros and end with SRLI */ -+ if (value > 0 && cost > 2) -+ { -+ struct mips_integer_op alt_codes[RISCV_MAX_INTEGER_OPS]; -+ int alt_cost, shift; -+ HOST_WIDE_INT shifted_value; -+ -+ /* Try filling trailing bits with 1s */ -+ shift = __builtin_clzl(value); -+ shifted_value = (value << shift) | ((((HOST_WIDE_INT) 1) << shift) - 1); -+ alt_cost = 1 + riscv_build_integer_simple (alt_codes, shifted_value); -+ alt_codes[alt_cost-1].code = LSHIFTRT; -+ alt_codes[alt_cost-1].value = shift; -+ if (alt_cost < cost) -+ cost = alt_cost, memcpy (codes, alt_codes, sizeof (alt_codes)); -+ -+ /* Try filling trailing bits with 0s */ -+ shift = __builtin_clzl(value); -+ alt_cost = 1 + riscv_build_integer_simple (alt_codes, value << shift); -+ alt_codes[alt_cost-1].code = LSHIFTRT; -+ alt_codes[alt_cost-1].value = shift; -+ if (alt_cost < cost) -+ cost = alt_cost, memcpy (codes, alt_codes, sizeof (alt_codes)); -+ } -+ -+ return cost; -+} -+ -+static int -+riscv_split_integer_cost (HOST_WIDE_INT val) -+{ -+ int cost; -+ int32_t loval = val, hival = (val - (int32_t)val) >> 32; -+ struct mips_integer_op codes[RISCV_MAX_INTEGER_OPS]; -+ -+ cost = 2 + riscv_build_integer(codes, loval); -+ if (loval != hival) -+ cost += riscv_build_integer(codes, hival); -+ -+ return cost; -+} -+ -+static int -+riscv_integer_cost (HOST_WIDE_INT val) -+{ -+ struct mips_integer_op codes[RISCV_MAX_INTEGER_OPS]; -+ return MIN (riscv_build_integer (codes, val), riscv_split_integer_cost (val)); -+} -+ -+/* Try to split a 64b integer into 32b parts, then reassemble. */ -+ -+static rtx -+riscv_split_integer (HOST_WIDE_INT val, enum machine_mode mode) -+{ -+ int32_t loval = val, hival = (val - (int32_t)val) >> 32; -+ rtx hi = gen_reg_rtx (mode), lo = gen_reg_rtx (mode); -+ -+ mips_move_integer (hi, hi, hival); -+ mips_move_integer (lo, lo, loval); -+ -+ hi = gen_rtx_fmt_ee (ASHIFT, mode, hi, GEN_INT (32)); -+ hi = force_reg (mode, hi); -+ -+ return gen_rtx_fmt_ee (PLUS, mode, hi, lo); -+} -+ -+/* Return true if X is a thread-local symbol. */ -+ -+static bool -+mips_tls_symbol_p (const_rtx x) -+{ -+ return GET_CODE (x) == SYMBOL_REF && SYMBOL_REF_TLS_MODEL (x) != 0; -+} -+ -+static bool -+riscv_symbol_binds_local_p (const_rtx x) -+{ -+ return (SYMBOL_REF_DECL (x) -+ ? targetm.binds_local_p (SYMBOL_REF_DECL (x)) -+ : SYMBOL_REF_LOCAL_P (x)); -+} -+ -+/* Return the method that should be used to access SYMBOL_REF or -+ LABEL_REF X in context CONTEXT. */ -+ -+static enum mips_symbol_type -+mips_classify_symbol (const_rtx x) -+{ -+ if (mips_tls_symbol_p (x)) -+ return SYMBOL_TLS; -+ -+ if (GET_CODE (x) == LABEL_REF) -+ { -+ if (LABEL_REF_NONLOCAL_P (x)) -+ return SYMBOL_GOT_DISP; -+ return SYMBOL_ABSOLUTE; -+ } -+ -+ gcc_assert (GET_CODE (x) == SYMBOL_REF); -+ -+ if (flag_pic && !riscv_symbol_binds_local_p (x)) -+ return SYMBOL_GOT_DISP; -+ -+ return SYMBOL_ABSOLUTE; -+} -+ -+/* Classify the base of symbolic expression X, given that X appears in -+ context CONTEXT. */ -+ -+static enum mips_symbol_type -+mips_classify_symbolic_expression (rtx x) -+{ -+ rtx offset; -+ -+ split_const (x, &x, &offset); -+ if (UNSPEC_ADDRESS_P (x)) -+ return UNSPEC_ADDRESS_TYPE (x); -+ -+ return mips_classify_symbol (x); -+} -+ -+/* Return true if X is a symbolic constant that can be used in context -+ CONTEXT. If it is, store the type of the symbol in *SYMBOL_TYPE. */ -+ -+bool -+mips_symbolic_constant_p (rtx x, enum mips_symbol_type *symbol_type) -+{ -+ rtx offset; -+ -+ split_const (x, &x, &offset); -+ if (UNSPEC_ADDRESS_P (x)) -+ { -+ *symbol_type = UNSPEC_ADDRESS_TYPE (x); -+ x = UNSPEC_ADDRESS (x); -+ } -+ else if (GET_CODE (x) == SYMBOL_REF || GET_CODE (x) == LABEL_REF) -+ *symbol_type = mips_classify_symbol (x); -+ else -+ return false; -+ -+ if (offset == const0_rtx) -+ return true; -+ -+ /* Check whether a nonzero offset is valid for the underlying -+ relocations. */ -+ switch (*symbol_type) -+ { -+ case SYMBOL_ABSOLUTE: -+ return true; -+ -+ case SYMBOL_TLS: -+ case SYMBOL_TLS_LE: -+ case SYMBOL_TLS_IE: -+ case SYMBOL_GOT_DISP: -+ return false; -+ } -+ gcc_unreachable (); -+} -+ -+/* Returns the number of instructions necessary to reference a symbol. */ -+ -+static int riscv_symbol_insns (enum mips_symbol_type type) -+{ -+ switch (type) -+ { -+ case SYMBOL_TLS: return 0; /* Depends on the TLS model. */ -+ case SYMBOL_ABSOLUTE: return 2; /* LUI + the reference itself */ -+ case SYMBOL_TLS_LE: return 3; /* LUI + ADD TP + the reference itself */ -+ case SYMBOL_TLS_IE: return 4; /* LUI + LD + ADD TP + the reference itself */ -+ case SYMBOL_GOT_DISP: return 3; /* AUIPC + LD GOT + the reference itself */ -+ default: gcc_unreachable(); -+ } -+} -+ -+/* A for_each_rtx callback. Stop the search if *X references a -+ thread-local symbol. */ -+ -+static int -+mips_tls_symbol_ref_1 (rtx *x, void *data ATTRIBUTE_UNUSED) -+{ -+ return mips_tls_symbol_p (*x); -+} -+ -+/* Implement TARGET_CANNOT_FORCE_CONST_MEM. */ -+ -+static bool -+mips_cannot_force_const_mem (rtx x) -+{ -+ enum mips_symbol_type type; -+ rtx base, offset; -+ -+ /* There is no assembler syntax for expressing an address-sized -+ high part. */ -+ if (GET_CODE (x) == HIGH) -+ return true; -+ -+ /* As an optimization, reject constants that mips_legitimize_move -+ can expand inline. -+ -+ Suppose we have a multi-instruction sequence that loads constant C -+ into register R. If R does not get allocated a hard register, and -+ R is used in an operand that allows both registers and memory -+ references, reload will consider forcing C into memory and using -+ one of the instruction's memory alternatives. Returning false -+ here will force it to use an input reload instead. */ -+ if (CONST_INT_P (x) && LEGITIMATE_CONSTANT_P (x)) -+ return true; -+ -+ split_const (x, &base, &offset); -+ if (mips_symbolic_constant_p (base, &type)) -+ { -+ /* The same optimization as for CONST_INT. */ -+ if (SMALL_INT (offset) && riscv_symbol_insns (type) > 0) -+ return true; -+ } -+ -+ /* TLS symbols must be computed by mips_legitimize_move. */ -+ if (for_each_rtx (&x, &mips_tls_symbol_ref_1, NULL)) -+ return true; -+ -+ return false; -+} -+ -+/* Return true if register REGNO is a valid base register for mode MODE. -+ STRICT_P is true if REG_OK_STRICT is in effect. */ -+ -+int -+riscv_regno_mode_ok_for_base_p (int regno, enum machine_mode mode ATTRIBUTE_UNUSED, -+ bool strict_p) -+{ -+ if (!HARD_REGISTER_NUM_P (regno)) -+ { -+ if (!strict_p) -+ return true; -+ regno = reg_renumber[regno]; -+ } -+ -+ /* These fake registers will be eliminated to either the stack or -+ hard frame pointer, both of which are usually valid base registers. -+ Reload deals with the cases where the eliminated form isn't valid. */ -+ if (regno == ARG_POINTER_REGNUM || regno == FRAME_POINTER_REGNUM) -+ return true; -+ -+ return GP_REG_P (regno); -+} -+ -+/* Return true if X is a valid base register for mode MODE. -+ STRICT_P is true if REG_OK_STRICT is in effect. */ -+ -+static bool -+mips_valid_base_register_p (rtx x, enum machine_mode mode, bool strict_p) -+{ -+ if (!strict_p && GET_CODE (x) == SUBREG) -+ x = SUBREG_REG (x); -+ -+ return (REG_P (x) -+ && riscv_regno_mode_ok_for_base_p (REGNO (x), mode, strict_p)); -+} -+ -+/* Return true if, for every base register BASE_REG, (plus BASE_REG X) -+ can address a value of mode MODE. */ -+ -+static bool -+mips_valid_offset_p (rtx x, enum machine_mode mode) -+{ -+ /* Check that X is a signed 12-bit number. */ -+ if (!const_arith_operand (x, Pmode)) -+ return false; -+ -+ /* We may need to split multiword moves, so make sure that every word -+ is accessible. */ -+ if (GET_MODE_SIZE (mode) > UNITS_PER_WORD -+ && !SMALL_OPERAND (INTVAL (x) + GET_MODE_SIZE (mode) - UNITS_PER_WORD)) -+ return false; -+ -+ return true; -+} -+ -+/* Return true if a LO_SUM can address a value of mode MODE when the -+ LO_SUM symbol has type SYMBOL_TYPE. */ -+ -+static bool -+mips_valid_lo_sum_p (enum mips_symbol_type symbol_type, enum machine_mode mode) -+{ -+ /* Check that symbols of type SYMBOL_TYPE can be used to access values -+ of mode MODE. */ -+ if (riscv_symbol_insns (symbol_type) == 0) -+ return false; -+ -+ /* Check that there is a known low-part relocation. */ -+ if (riscv_lo_relocs[symbol_type] == NULL) -+ return false; -+ -+ /* We may need to split multiword moves, so make sure that each word -+ can be accessed without inducing a carry. This is mainly needed -+ for o64, which has historically only guaranteed 64-bit alignment -+ for 128-bit types. */ -+ if (GET_MODE_SIZE (mode) > UNITS_PER_WORD -+ && GET_MODE_BITSIZE (mode) > GET_MODE_ALIGNMENT (mode)) -+ return false; -+ -+ return true; -+} -+ -+/* Return true if X is a valid address for machine mode MODE. If it is, -+ fill in INFO appropriately. STRICT_P is true if REG_OK_STRICT is in -+ effect. */ -+ -+static bool -+mips_classify_address (struct mips_address_info *info, rtx x, -+ enum machine_mode mode, bool strict_p) -+{ -+ switch (GET_CODE (x)) -+ { -+ case REG: -+ case SUBREG: -+ info->type = ADDRESS_REG; -+ info->reg = x; -+ info->offset = const0_rtx; -+ return mips_valid_base_register_p (info->reg, mode, strict_p); -+ -+ case PLUS: -+ info->type = ADDRESS_REG; -+ info->reg = XEXP (x, 0); -+ info->offset = XEXP (x, 1); -+ return (mips_valid_base_register_p (info->reg, mode, strict_p) -+ && mips_valid_offset_p (info->offset, mode)); -+ -+ case LO_SUM: -+ info->type = ADDRESS_LO_SUM; -+ info->reg = XEXP (x, 0); -+ info->offset = XEXP (x, 1); -+ /* We have to trust the creator of the LO_SUM to do something vaguely -+ sane. Target-independent code that creates a LO_SUM should also -+ create and verify the matching HIGH. Target-independent code that -+ adds an offset to a LO_SUM must prove that the offset will not -+ induce a carry. Failure to do either of these things would be -+ a bug, and we are not required to check for it here. The MIPS -+ backend itself should only create LO_SUMs for valid symbolic -+ constants, with the high part being either a HIGH or a copy -+ of _gp. */ -+ info->symbol_type -+ = mips_classify_symbolic_expression (info->offset); -+ return (mips_valid_base_register_p (info->reg, mode, strict_p) -+ && mips_valid_lo_sum_p (info->symbol_type, mode)); -+ -+ case CONST_INT: -+ /* Small-integer addresses don't occur very often, but they -+ are legitimate if $0 is a valid base register. */ -+ info->type = ADDRESS_CONST_INT; -+ return SMALL_INT (x); -+ -+ case CONST: -+ case LABEL_REF: -+ case SYMBOL_REF: -+ if (mips_symbolic_constant_p (x, &info->symbol_type) -+ && riscv_symbol_insns (info->symbol_type) > 0 -+ && !riscv_hi_relocs[info->symbol_type] -+ && riscv_lo_relocs[info->symbol_type]) -+ { -+ info->type = ADDRESS_LO_SUM; -+ info->reg = gen_rtx_REG (Pmode, GP_REGNUM); -+ info->offset = x; -+ return true; -+ } -+ -+ default: -+ return false; -+ } -+} -+ -+/* Implement TARGET_LEGITIMATE_ADDRESS_P. */ -+ -+static bool -+mips_legitimate_address_p (enum machine_mode mode, rtx x, bool strict_p) -+{ -+ struct mips_address_info addr; -+ -+ return mips_classify_address (&addr, x, mode, strict_p); -+} -+ -+/* Return the number of instructions needed to load or store a value -+ of mode MODE at address X. Return 0 if X isn't valid for MODE. -+ Assume that multiword moves may need to be split into word moves -+ if MIGHT_SPLIT_P, otherwise assume that a single load or store is -+ enough. */ -+ -+int -+riscv_address_insns (rtx x, enum machine_mode mode, bool might_split_p) -+{ -+ struct mips_address_info addr; -+ int n = 1; -+ -+ if (!mips_classify_address (&addr, x, mode, false)) -+ return 0; -+ -+ /* BLKmode is used for single unaligned loads and stores and should -+ not count as a multiword mode. */ -+ if (mode != BLKmode && might_split_p) -+ n += (GET_MODE_SIZE (mode) + UNITS_PER_WORD - 1) / UNITS_PER_WORD; -+ -+ if (addr.type == ADDRESS_SYMBOLIC) -+ n *= riscv_symbol_insns (addr.symbol_type); -+ -+ return n; -+} -+ -+/* Return the number of instructions needed to load constant X. -+ Return 0 if X isn't a valid constant. */ -+ -+int -+riscv_const_insns (rtx x) -+{ -+ enum mips_symbol_type symbol_type; -+ rtx offset; -+ -+ switch (GET_CODE (x)) -+ { -+ case HIGH: -+ if (!mips_symbolic_constant_p (XEXP (x, 0), &symbol_type) -+ || !riscv_hi_relocs[symbol_type]) -+ return 0; -+ -+ /* This is simply an LUI. */ -+ return 1; -+ -+ case CONST_INT: -+ { -+ int cost = riscv_integer_cost (INTVAL (x)); -+ /* Force complicated constants to memory. */ -+ return cost < 4 ? cost : 0; -+ } -+ -+ case CONST_DOUBLE: -+ case CONST_VECTOR: -+ /* Allow zeros for normal mode, where we can use x0. */ -+ return x == CONST0_RTX (GET_MODE (x)) ? 1 : 0; -+ -+ case CONST: -+ /* See if we can refer to X directly. */ -+ if (mips_symbolic_constant_p (x, &symbol_type)) -+ return riscv_symbol_insns (symbol_type); -+ -+ /* Otherwise try splitting the constant into a base and offset. -+ If the offset is a 16-bit value, we can load the base address -+ into a register and then use (D)ADDIU to add in the offset. -+ If the offset is larger, we can load the base and offset -+ into separate registers and add them together with (D)ADDU. -+ However, the latter is only possible before reload; during -+ and after reload, we must have the option of forcing the -+ constant into the pool instead. */ -+ split_const (x, &x, &offset); -+ if (offset != 0) -+ { -+ int n = riscv_const_insns (x); -+ if (n != 0) -+ { -+ if (SMALL_INT (offset)) -+ return n + 1; -+ else if (!targetm.cannot_force_const_mem (x)) -+ return n + 1 + riscv_integer_cost (INTVAL (offset)); -+ } -+ } -+ return 0; -+ -+ case SYMBOL_REF: -+ case LABEL_REF: -+ return riscv_symbol_insns (mips_classify_symbol (x)); -+ -+ default: -+ return 0; -+ } -+} -+ -+/* X is a doubleword constant that can be handled by splitting it into -+ two words and loading each word separately. Return the number of -+ instructions required to do this. */ -+ -+int -+riscv_split_const_insns (rtx x) -+{ -+ unsigned int low, high; -+ -+ low = riscv_const_insns (mips_subword (x, false)); -+ high = riscv_const_insns (mips_subword (x, true)); -+ gcc_assert (low > 0 && high > 0); -+ return low + high; -+} -+ -+/* Return the number of instructions needed to implement INSN, -+ given that it loads from or stores to MEM. */ -+ -+int -+mips_load_store_insns (rtx mem, rtx insn) -+{ -+ enum machine_mode mode; -+ bool might_split_p; -+ rtx set; -+ -+ gcc_assert (MEM_P (mem)); -+ mode = GET_MODE (mem); -+ -+ /* Try to prove that INSN does not need to be split. */ -+ might_split_p = true; -+ if (GET_MODE_BITSIZE (mode) == 64) -+ { -+ set = single_set (insn); -+ if (set && !mips_split_64bit_move_p (SET_DEST (set), SET_SRC (set))) -+ might_split_p = false; -+ } -+ -+ return riscv_address_insns (XEXP (mem, 0), mode, might_split_p); -+} -+ -+/* Emit a move from SRC to DEST. Assume that the move expanders can -+ handle all moves if !can_create_pseudo_p (). The distinction is -+ important because, unlike emit_move_insn, the move expanders know -+ how to force Pmode objects into the constant pool even when the -+ constant pool address is not itself legitimate. */ -+ -+rtx -+mips_emit_move (rtx dest, rtx src) -+{ -+ return (can_create_pseudo_p () -+ ? emit_move_insn (dest, src) -+ : emit_move_insn_1 (dest, src)); -+} -+ -+/* Emit an instruction of the form (set TARGET (CODE OP0 OP1)). */ -+ -+static void -+mips_emit_binary (enum rtx_code code, rtx target, rtx op0, rtx op1) -+{ -+ emit_insn (gen_rtx_SET (VOIDmode, target, -+ gen_rtx_fmt_ee (code, GET_MODE (target), op0, op1))); -+} -+ -+/* Compute (CODE OP0 OP1) and store the result in a new register -+ of mode MODE. Return that new register. */ -+ -+static rtx -+mips_force_binary (enum machine_mode mode, enum rtx_code code, rtx op0, rtx op1) -+{ -+ rtx reg; -+ -+ reg = gen_reg_rtx (mode); -+ mips_emit_binary (code, reg, op0, op1); -+ return reg; -+} -+ -+/* Copy VALUE to a register and return that register. If new pseudos -+ are allowed, copy it into a new register, otherwise use DEST. */ -+ -+static rtx -+mips_force_temporary (rtx dest, rtx value) -+{ -+ if (can_create_pseudo_p ()) -+ return force_reg (Pmode, value); -+ else -+ { -+ mips_emit_move (dest, value); -+ return dest; -+ } -+} -+ -+/* Wrap symbol or label BASE in an UNSPEC address of type SYMBOL_TYPE, -+ then add CONST_INT OFFSET to the result. */ -+ -+static rtx -+mips_unspec_address_offset (rtx base, rtx offset, -+ enum mips_symbol_type symbol_type) -+{ -+ base = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, base), -+ UNSPEC_ADDRESS_FIRST + symbol_type); -+ if (offset != const0_rtx) -+ base = gen_rtx_PLUS (Pmode, base, offset); -+ return gen_rtx_CONST (Pmode, base); -+} -+ -+/* Return an UNSPEC address with underlying address ADDRESS and symbol -+ type SYMBOL_TYPE. */ -+ -+rtx -+mips_unspec_address (rtx address, enum mips_symbol_type symbol_type) -+{ -+ rtx base, offset; -+ -+ split_const (address, &base, &offset); -+ return mips_unspec_address_offset (base, offset, symbol_type); -+} -+ -+/* If OP is an UNSPEC address, return the address to which it refers, -+ otherwise return OP itself. */ -+ -+static rtx -+mips_strip_unspec_address (rtx op) -+{ -+ rtx base, offset; -+ -+ split_const (op, &base, &offset); -+ if (UNSPEC_ADDRESS_P (base)) -+ op = plus_constant (UNSPEC_ADDRESS (base), INTVAL (offset)); -+ return op; -+} -+ -+/* If mips_unspec_address (ADDR, SYMBOL_TYPE) is a 32-bit value, add the -+ high part to BASE and return the result. Just return BASE otherwise. -+ TEMP is as for mips_force_temporary. -+ -+ The returned expression can be used as the first operand to a LO_SUM. */ -+ -+static rtx -+mips_unspec_offset_high (rtx temp, rtx addr, enum mips_symbol_type symbol_type) -+{ -+ addr = gen_rtx_HIGH (Pmode, mips_unspec_address (addr, symbol_type)); -+ return mips_force_temporary (temp, addr); -+} -+ -+/* Load an entry from the GOT. */ -+static rtx riscv_got_load_tls_gd(rtx dest, rtx sym) -+{ -+ return (Pmode == DImode ? gen_got_load_tls_gddi(dest, sym) : gen_got_load_tls_gdsi(dest, sym)); -+} -+ -+static rtx riscv_got_load_tls_ie(rtx dest, rtx sym) -+{ -+ return (Pmode == DImode ? gen_got_load_tls_iedi(dest, sym) : gen_got_load_tls_iesi(dest, sym)); -+} -+ -+static rtx riscv_got_load_tls_ie_hi(rtx dest, rtx sym) -+{ -+ return (Pmode == DImode ? gen_got_load_tls_ie_hidi(dest, sym) : gen_got_load_tls_ie_hisi(dest, sym)); -+} -+ -+static rtx riscv_got_load_tls_ie_lo(rtx dest, rtx base, rtx sym) -+{ -+ return (Pmode == DImode ? gen_got_load_tls_ie_lodi(dest, base, sym) : gen_got_load_tls_ie_losi(dest, base, sym)); -+} -+ -+static rtx riscv_tls_add_tp_ie(rtx dest, rtx base, rtx sym) -+{ -+ rtx tp = gen_rtx_REG (Pmode, THREAD_POINTER_REGNUM); -+ return (Pmode == DImode ? gen_tls_add_tp_iedi(dest, base, tp, sym) : gen_tls_add_tp_iesi(dest, base, tp, sym)); -+} -+ -+static rtx riscv_tls_add_tp_le(rtx dest, rtx base, rtx sym) -+{ -+ rtx tp = gen_rtx_REG (Pmode, THREAD_POINTER_REGNUM); -+ return (Pmode == DImode ? gen_tls_add_tp_ledi(dest, base, tp, sym) : gen_tls_add_tp_lesi(dest, base, tp, sym)); -+} -+ -+/* If MODE is MAX_MACHINE_MODE, ADDR appears as a move operand, otherwise -+ it appears in a MEM of that mode. Return true if ADDR is a legitimate -+ constant in that context and can be split into high and low parts. -+ If so, and if LOW_OUT is nonnull, emit the high part and store the -+ low part in *LOW_OUT. Leave *LOW_OUT unchanged otherwise. -+ -+ TEMP is as for mips_force_temporary and is used to load the high -+ part into a register. -+ -+ When MODE is MAX_MACHINE_MODE, the low part is guaranteed to be -+ a legitimize SET_SRC for an .md pattern, otherwise the low part -+ is guaranteed to be a legitimate address for mode MODE. */ -+ -+bool -+mips_split_symbol (rtx temp, rtx addr, enum machine_mode mode, rtx *low_out) -+{ -+ enum mips_symbol_type symbol_type; -+ rtx high; -+ -+ if ((GET_CODE (addr) == HIGH && mode == MAX_MACHINE_MODE) -+ || !mips_symbolic_constant_p (addr, &symbol_type) -+ || riscv_symbol_insns (symbol_type) == 0 -+ || !riscv_hi_relocs[symbol_type]) -+ return false; -+ -+ if (low_out) -+ { -+ switch (symbol_type) -+ { -+ case SYMBOL_ABSOLUTE: -+ high = gen_rtx_HIGH (Pmode, copy_rtx (addr)); -+ high = mips_force_temporary (temp, high); -+ *low_out = gen_rtx_LO_SUM (Pmode, high, addr); -+ break; -+ -+ default: -+ gcc_unreachable (); -+ } -+ } -+ -+ return true; -+} -+ -+/* Return a legitimate address for REG + OFFSET. TEMP is as for -+ mips_force_temporary; it is only needed when OFFSET is not a -+ SMALL_OPERAND. */ -+ -+static rtx -+mips_add_offset (rtx temp, rtx reg, HOST_WIDE_INT offset) -+{ -+ if (!SMALL_OPERAND (offset)) -+ { -+ rtx high; -+ -+ /* Leave OFFSET as a 16-bit offset and put the excess in HIGH. -+ The addition inside the macro CONST_HIGH_PART may cause an -+ overflow, so we need to force a sign-extension check. */ -+ high = gen_int_mode (RISCV_CONST_HIGH_PART (offset), Pmode); -+ offset = RISCV_CONST_LOW_PART (offset); -+ high = mips_force_temporary (temp, high); -+ reg = mips_force_temporary (temp, gen_rtx_PLUS (Pmode, high, reg)); -+ } -+ return plus_constant (reg, offset); -+} -+ -+/* The __tls_get_attr symbol. */ -+static GTY(()) rtx mips_tls_symbol; -+ -+/* Return an instruction sequence that calls __tls_get_addr. SYM is -+ the TLS symbol we are referencing and TYPE is the symbol type to use -+ (either global dynamic or local dynamic). V0 is an RTX for the -+ return value location. */ -+ -+static rtx -+mips_call_tls_get_addr (rtx sym, rtx v0) -+{ -+ rtx insn, a0; -+ -+ a0 = gen_rtx_REG (Pmode, GP_ARG_FIRST); -+ -+ if (!mips_tls_symbol) -+ mips_tls_symbol = init_one_libfunc ("__tls_get_addr"); -+ -+ start_sequence (); -+ -+ emit_insn (riscv_got_load_tls_gd(a0, sym)); -+ insn = riscv_expand_call (false, v0, mips_tls_symbol, const0_rtx); -+ RTL_CONST_CALL_P (insn) = 1; -+ use_reg (&CALL_INSN_FUNCTION_USAGE (insn), a0); -+ insn = get_insns (); -+ -+ end_sequence (); -+ -+ return insn; -+} -+ -+/* Generate the code to access LOC, a thread-local SYMBOL_REF, and return -+ its address. The return value will be both a valid address and a valid -+ SET_SRC (either a REG or a LO_SUM). */ -+ -+static rtx -+mips_legitimize_tls_address (rtx loc) -+{ -+ rtx dest, insn, v0, tp, tmp1; -+ -+ switch (SYMBOL_REF_TLS_MODEL (loc)) -+ { -+ case TLS_MODEL_LOCAL_DYNAMIC: -+ /* Rely on section anchors for the optimization that LDM TLS -+ provides. The anchor's address is loaded with GD TLS. */ -+ case TLS_MODEL_GLOBAL_DYNAMIC: -+ v0 = gen_rtx_REG (Pmode, GP_RETURN); -+ insn = mips_call_tls_get_addr (loc, v0); -+ dest = gen_reg_rtx (Pmode); -+ emit_libcall_block (insn, dest, v0, loc); -+ break; -+ -+ case TLS_MODEL_INITIAL_EXEC: -+ if (flag_pic) -+ { -+ /* la.tls.ie; tp-relative add */ -+ tp = gen_rtx_REG (Pmode, THREAD_POINTER_REGNUM); -+ tmp1 = gen_reg_rtx (Pmode); -+ emit_insn (riscv_got_load_tls_ie (tmp1, loc)); -+ dest = gen_reg_rtx (Pmode); -+ emit_insn (gen_add3_insn (dest, tmp1, tp)); -+ } -+ else -+ { -+ /* lui %tls_ie_hi; ld %tls_le_lo; tp-relative add */ -+ tmp1 = gen_reg_rtx (Pmode); -+ emit_insn (riscv_got_load_tls_ie_hi (tmp1, loc)); -+ dest = gen_reg_rtx (Pmode); -+ emit_insn (riscv_got_load_tls_ie_lo (dest, tmp1, loc)); -+ tmp1 = gen_reg_rtx (Pmode); -+ emit_insn (riscv_tls_add_tp_ie (tmp1, dest, loc)); -+ dest = gen_rtx_LO_SUM (Pmode, tmp1, -+ mips_unspec_address (loc, SYMBOL_TLS_IE)); -+ } -+ break; -+ -+ case TLS_MODEL_LOCAL_EXEC: -+ tmp1 = mips_unspec_offset_high (NULL, loc, SYMBOL_TLS_LE); -+ dest = gen_reg_rtx (Pmode); -+ emit_insn (riscv_tls_add_tp_le (dest, tmp1, loc)); -+ dest = gen_rtx_LO_SUM (Pmode, dest, -+ mips_unspec_address (loc, SYMBOL_TLS_LE)); -+ break; -+ -+ default: -+ gcc_unreachable (); -+ } -+ return dest; -+} -+ -+/* If X is not a valid address for mode MODE, force it into a register. */ -+ -+static rtx -+mips_force_address (rtx x, enum machine_mode mode) -+{ -+ if (!mips_legitimate_address_p (mode, x, false)) -+ x = force_reg (Pmode, x); -+ return x; -+} -+ -+/* This function is used to implement LEGITIMIZE_ADDRESS. If X can -+ be legitimized in a way that the generic machinery might not expect, -+ return a new address, otherwise return NULL. MODE is the mode of -+ the memory being accessed. */ -+ -+static rtx -+mips_legitimize_address (rtx x, rtx oldx ATTRIBUTE_UNUSED, -+ enum machine_mode mode) -+{ -+ rtx addr; -+ -+ if (mips_tls_symbol_p (x)) -+ return mips_legitimize_tls_address (x); -+ -+ /* See if the address can split into a high part and a LO_SUM. */ -+ if (mips_split_symbol (NULL, x, mode, &addr)) -+ return mips_force_address (addr, mode); -+ -+ /* Handle BASE + OFFSET using mips_add_offset. */ -+ if (GET_CODE (x) == PLUS && CONST_INT_P (XEXP (x, 1)) -+ && INTVAL (XEXP (x, 1)) != 0) -+ { -+ rtx base = XEXP (x, 0); -+ HOST_WIDE_INT offset = INTVAL (XEXP (x, 1)); -+ -+ if (!mips_valid_base_register_p (base, mode, false)) -+ base = copy_to_mode_reg (Pmode, base); -+ addr = mips_add_offset (NULL, base, offset); -+ return mips_force_address (addr, mode); -+ } -+ -+ return x; -+} -+ -+/* Load VALUE into DEST. TEMP is as for mips_force_temporary. */ -+ -+void -+mips_move_integer (rtx temp, rtx dest, HOST_WIDE_INT value) -+{ -+ struct mips_integer_op codes[RISCV_MAX_INTEGER_OPS]; -+ enum machine_mode mode; -+ int i, num_ops; -+ rtx x; -+ -+ mode = GET_MODE (dest); -+ num_ops = riscv_build_integer (codes, value); -+ -+ if (can_create_pseudo_p () && num_ops > 2 /* not a simple constant */ -+ && num_ops >= riscv_split_integer_cost (value)) -+ x = riscv_split_integer (value, mode); -+ else -+ { -+ /* Apply each binary operation to X. */ -+ x = GEN_INT (codes[0].value); -+ -+ for (i = 1; i < num_ops; i++) -+ { -+ if (!can_create_pseudo_p ()) -+ { -+ emit_insn (gen_rtx_SET (VOIDmode, temp, x)); -+ x = temp; -+ } -+ else -+ x = force_reg (mode == HImode ? SImode : mode, x); -+ -+ x = gen_rtx_fmt_ee (codes[i].code, mode, x, GEN_INT (codes[i].value)); -+ } -+ } -+ -+ emit_insn (gen_rtx_SET (VOIDmode, dest, x)); -+} -+ -+/* Subroutine of mips_legitimize_move. Move constant SRC into register -+ DEST given that SRC satisfies immediate_operand but doesn't satisfy -+ move_operand. */ -+ -+static void -+mips_legitimize_const_move (enum machine_mode mode, rtx dest, rtx src) -+{ -+ rtx base, offset; -+ -+ /* Split moves of big integers into smaller pieces. */ -+ if (splittable_const_int_operand (src, mode)) -+ { -+ mips_move_integer (dest, dest, INTVAL (src)); -+ return; -+ } -+ -+ /* Split moves of symbolic constants into high/low pairs. */ -+ if (mips_split_symbol (dest, src, MAX_MACHINE_MODE, &src)) -+ { -+ emit_insn (gen_rtx_SET (VOIDmode, dest, src)); -+ return; -+ } -+ -+ /* Generate the appropriate access sequences for TLS symbols. */ -+ if (mips_tls_symbol_p (src)) -+ { -+ mips_emit_move (dest, mips_legitimize_tls_address (src)); -+ return; -+ } -+ -+ /* If we have (const (plus symbol offset)), and that expression cannot -+ be forced into memory, load the symbol first and add in the offset. Also -+ prefer to do this even if the constant _can_ be forced into memory, as it -+ usually produces better code. */ -+ split_const (src, &base, &offset); -+ if (offset != const0_rtx -+ && (targetm.cannot_force_const_mem (src) || can_create_pseudo_p ())) -+ { -+ base = mips_force_temporary (dest, base); -+ mips_emit_move (dest, mips_add_offset (NULL, base, INTVAL (offset))); -+ return; -+ } -+ -+ src = force_const_mem (mode, src); -+ -+ /* When using explicit relocs, constant pool references are sometimes -+ not legitimate addresses. */ -+ mips_split_symbol (dest, XEXP (src, 0), mode, &XEXP (src, 0)); -+ mips_emit_move (dest, src); -+} -+ -+/* If (set DEST SRC) is not a valid move instruction, emit an equivalent -+ sequence that is valid. */ -+ -+bool -+mips_legitimize_move (enum machine_mode mode, rtx dest, rtx src) -+{ -+ if (!register_operand (dest, mode) && !reg_or_0_operand (src, mode)) -+ { -+ mips_emit_move (dest, force_reg (mode, src)); -+ return true; -+ } -+ -+ /* We need to deal with constants that would be legitimate -+ immediate_operands but aren't legitimate move_operands. */ -+ if (CONSTANT_P (src) && !move_operand (src, mode)) -+ { -+ mips_legitimize_const_move (mode, dest, src); -+ set_unique_reg_note (get_last_insn (), REG_EQUAL, copy_rtx (src)); -+ return true; -+ } -+ return false; -+} -+ -+/* The cost of loading values from the constant pool. It should be -+ larger than the cost of any constant we want to synthesize inline. */ -+#define CONSTANT_POOL_COST COSTS_N_INSNS (8) -+ -+/* Return true if there is an instruction that implements CODE and accepts -+ X as an immediate operand. */ -+ -+static int -+mips_immediate_operand_p (int code, HOST_WIDE_INT x) -+{ -+ switch (code) -+ { -+ case ASHIFT: -+ case ASHIFTRT: -+ case LSHIFTRT: -+ /* All shift counts are truncated to a valid constant. */ -+ return true; -+ -+ case AND: -+ case IOR: -+ case XOR: -+ case PLUS: -+ case LT: -+ case LTU: -+ /* These instructions take 12-bit signed immediates. */ -+ return SMALL_OPERAND (x); -+ -+ case LE: -+ /* We add 1 to the immediate and use SLT. */ -+ return SMALL_OPERAND (x + 1); -+ -+ case LEU: -+ /* Likewise SLTU, but reject the always-true case. */ -+ return SMALL_OPERAND (x + 1) && x + 1 != 0; -+ -+ case GE: -+ case GEU: -+ /* We can emulate an immediate of 1 by using GT/GTU against x0. */ -+ return x == 1; -+ -+ default: -+ /* By default assume that x0 can be used for 0. */ -+ return x == 0; -+ } -+} -+ -+/* Return the cost of binary operation X, given that the instruction -+ sequence for a word-sized or smaller operation has cost SINGLE_COST -+ and that the sequence of a double-word operation has cost DOUBLE_COST. -+ If SPEED is true, optimize for speed otherwise optimize for size. */ -+ -+static int -+mips_binary_cost (rtx x, int single_cost, int double_cost, bool speed) -+{ -+ if (GET_MODE_SIZE (GET_MODE (x)) == UNITS_PER_WORD * 2) -+ single_cost = double_cost; -+ -+ return (COSTS_N_INSNS (single_cost) -+ + rtx_cost (XEXP (x, 0), SET, speed) -+ + rtx_cost (XEXP (x, 1), GET_CODE (x), speed)); -+} -+ -+/* Return the cost of floating-point multiplications of mode MODE. */ -+ -+static int -+mips_fp_mult_cost (enum machine_mode mode) -+{ -+ return mode == DFmode ? mips_cost->fp_mult_df : mips_cost->fp_mult_sf; -+} -+ -+/* Return the cost of floating-point divisions of mode MODE. */ -+ -+static int -+mips_fp_div_cost (enum machine_mode mode) -+{ -+ return mode == DFmode ? mips_cost->fp_div_df : mips_cost->fp_div_sf; -+} -+ -+/* Return the cost of sign-extending OP to mode MODE, not including the -+ cost of OP itself. */ -+ -+static int -+mips_sign_extend_cost (enum machine_mode mode, rtx op) -+{ -+ if (MEM_P (op)) -+ /* Extended loads are as cheap as unextended ones. */ -+ return 0; -+ -+ if (TARGET_64BIT && mode == DImode && GET_MODE (op) == SImode) -+ /* A sign extension from SImode to DImode in 64-bit mode is free. */ -+ return 0; -+ -+ /* We need to use a shift left and a shift right. */ -+ return COSTS_N_INSNS (2); -+} -+ -+/* Return the cost of zero-extending OP to mode MODE, not including the -+ cost of OP itself. */ -+ -+static int -+mips_zero_extend_cost (enum machine_mode mode, rtx op) -+{ -+ if (MEM_P (op)) -+ /* Extended loads are as cheap as unextended ones. */ -+ return 0; -+ -+ if ((TARGET_64BIT && mode == DImode && GET_MODE (op) == SImode) || -+ ((mode == DImode || mode == SImode) && GET_MODE (op) == HImode)) -+ /* We need a shift left by 32 bits and a shift right by 32 bits. */ -+ return COSTS_N_INSNS (2); -+ -+ /* We can use ANDI. */ -+ return COSTS_N_INSNS (1); -+} -+ -+/* Implement TARGET_RTX_COSTS. */ -+ -+static bool -+mips_rtx_costs (rtx x, int code, int outer_code, int *total, bool speed) -+{ -+ enum machine_mode mode = GET_MODE (x); -+ bool float_mode_p = FLOAT_MODE_P (mode); -+ int cost; -+ rtx addr; -+ -+ /* The cost of a COMPARE is hard to define for MIPS. COMPAREs don't -+ appear in the instruction stream, and the cost of a comparison is -+ really the cost of the branch or scc condition. At the time of -+ writing, GCC only uses an explicit outer COMPARE code when optabs -+ is testing whether a constant is expensive enough to force into a -+ register. We want optabs to pass such constants through the MIPS -+ expanders instead, so make all constants very cheap here. */ -+ if (outer_code == COMPARE) -+ { -+ gcc_assert (CONSTANT_P (x)); -+ *total = 0; -+ return true; -+ } -+ -+ switch (code) -+ { -+ case CONST_INT: -+ /* When not optimizing for size, we care more about the cost -+ of hot code, and hot code is often in a loop. If a constant -+ operand needs to be forced into a register, we will often be -+ able to hoist the constant load out of the loop, so the load -+ should not contribute to the cost. */ -+ if (!optimize_size || mips_immediate_operand_p (outer_code, INTVAL (x))) -+ { -+ *total = 0; -+ return true; -+ } -+ /* Fall through. */ -+ -+ case CONST: -+ case SYMBOL_REF: -+ case LABEL_REF: -+ case CONST_DOUBLE: -+ cost = riscv_const_insns (x); -+ if (cost > 0) -+ { -+ /* If the constant is likely to be stored in a GPR, SETs of -+ single-insn constants are as cheap as register sets; we -+ never want to CSE them. */ -+ if (cost == 1 && outer_code == SET && code == CONST_INT) -+ cost = 0; -+ *total = COSTS_N_INSNS (cost); -+ return true; -+ } -+ /* The value will need to be fetched from the constant pool. */ -+ *total = CONSTANT_POOL_COST; -+ return true; -+ -+ case MEM: -+ /* If the address is legitimate, return the number of -+ instructions it needs. */ -+ addr = XEXP (x, 0); -+ cost = riscv_address_insns (addr, mode, true); -+ if (cost > 0) -+ { -+ *total = COSTS_N_INSNS (cost + mips_cost->memory_latency); -+ return true; -+ } -+ /* Otherwise use the default handling. */ -+ return false; -+ -+ case FFS: -+ *total = COSTS_N_INSNS (6); -+ return false; -+ -+ case NOT: -+ *total = COSTS_N_INSNS (GET_MODE_SIZE (mode) > UNITS_PER_WORD ? 2 : 1); -+ return false; -+ -+ case AND: -+ case IOR: -+ case XOR: -+ /* Double-word operations use two single-word operations. */ -+ *total = mips_binary_cost (x, 1, 2, speed); -+ return true; -+ -+ case ASHIFT: -+ case ASHIFTRT: -+ case LSHIFTRT: -+ case ROTATE: -+ case ROTATERT: -+ if (CONSTANT_P (XEXP (x, 1))) -+ *total = mips_binary_cost (x, 1, 4, speed); -+ else -+ *total = mips_binary_cost (x, 1, 12, speed); -+ return true; -+ -+ case ABS: -+ if (float_mode_p) -+ *total = mips_cost->fp_add; -+ else -+ *total = COSTS_N_INSNS (4); -+ return false; -+ -+ case LO_SUM: -+ *total = (COSTS_N_INSNS (1) -+ + rtx_cost (XEXP (x, 0), SET, speed)); -+ return true; -+ -+ case LT: -+ case LTU: -+ case LE: -+ case LEU: -+ case GT: -+ case GTU: -+ case GE: -+ case GEU: -+ case EQ: -+ case NE: -+ case UNORDERED: -+ case LTGT: -+ /* Branch comparisons have VOIDmode, so use the first operand's -+ mode instead. */ -+ mode = GET_MODE (XEXP (x, 0)); -+ if (FLOAT_MODE_P (mode)) -+ { -+ *total = mips_cost->fp_add; -+ return false; -+ } -+ *total = mips_binary_cost (x, 1, 4, speed); -+ return true; -+ -+ case MINUS: -+ if (float_mode_p -+ && !HONOR_NANS (mode) -+ && !HONOR_SIGNED_ZEROS (mode)) -+ { -+ /* See if we can use NMADD or NMSUB. See mips.md for the -+ associated patterns. */ -+ rtx op0 = XEXP (x, 0); -+ rtx op1 = XEXP (x, 1); -+ if (GET_CODE (op0) == MULT && GET_CODE (XEXP (op0, 0)) == NEG) -+ { -+ *total = (mips_fp_mult_cost (mode) -+ + rtx_cost (XEXP (XEXP (op0, 0), 0), SET, speed) -+ + rtx_cost (XEXP (op0, 1), SET, speed) -+ + rtx_cost (op1, SET, speed)); -+ return true; -+ } -+ if (GET_CODE (op1) == MULT) -+ { -+ *total = (mips_fp_mult_cost (mode) -+ + rtx_cost (op0, SET, speed) -+ + rtx_cost (XEXP (op1, 0), SET, speed) -+ + rtx_cost (XEXP (op1, 1), SET, speed)); -+ return true; -+ } -+ } -+ /* Fall through. */ -+ -+ case PLUS: -+ if (float_mode_p) -+ { -+ /* If this is part of a MADD or MSUB, treat the PLUS as -+ being free. */ -+ if (GET_CODE (XEXP (x, 0)) == MULT) -+ *total = 0; -+ else -+ *total = mips_cost->fp_add; -+ return false; -+ } -+ -+ /* Double-word operations require three ADDs and an SLTU. */ -+ *total = mips_binary_cost (x, 1, 4, speed); -+ return true; -+ -+ case NEG: -+ if (float_mode_p -+ && !HONOR_NANS (mode) -+ && HONOR_SIGNED_ZEROS (mode)) -+ { -+ /* See if we can use NMADD or NMSUB. See mips.md for the -+ associated patterns. */ -+ rtx op = XEXP (x, 0); -+ if ((GET_CODE (op) == PLUS || GET_CODE (op) == MINUS) -+ && GET_CODE (XEXP (op, 0)) == MULT) -+ { -+ *total = (mips_fp_mult_cost (mode) -+ + rtx_cost (XEXP (XEXP (op, 0), 0), SET, speed) -+ + rtx_cost (XEXP (XEXP (op, 0), 1), SET, speed) -+ + rtx_cost (XEXP (op, 1), SET, speed)); -+ return true; -+ } -+ } -+ -+ if (float_mode_p) -+ *total = mips_cost->fp_add; -+ else -+ *total = COSTS_N_INSNS (GET_MODE_SIZE (mode) > UNITS_PER_WORD ? 4 : 1); -+ return false; -+ -+ case MULT: -+ if (float_mode_p) -+ *total = mips_fp_mult_cost (mode); -+ else if (mode == DImode && !TARGET_64BIT) -+ /* We use a MUL and a MULH[[S]U]. */ -+ *total = mips_cost->int_mult_si * 2; -+ else if (!speed) -+ *total = 1; -+ else if (mode == DImode) -+ *total = mips_cost->int_mult_di; -+ else -+ *total = mips_cost->int_mult_si; -+ return false; -+ -+ case DIV: -+ /* Check for a reciprocal. */ -+ if (float_mode_p -+ && flag_unsafe_math_optimizations -+ && XEXP (x, 0) == CONST1_RTX (mode)) -+ { -+ if (outer_code == SQRT || GET_CODE (XEXP (x, 1)) == SQRT) -+ /* An rsqrta or rsqrtb pattern. Count the -+ division as being free. */ -+ *total = rtx_cost (XEXP (x, 1), SET, speed); -+ else -+ *total = (mips_fp_div_cost (mode) -+ + rtx_cost (XEXP (x, 1), SET, speed)); -+ return true; -+ } -+ /* Fall through. */ -+ -+ case SQRT: -+ case MOD: -+ if (float_mode_p) -+ { -+ *total = mips_fp_div_cost (mode); -+ return false; -+ } -+ /* Fall through. */ -+ -+ case UDIV: -+ case UMOD: -+ if (!speed) -+ *total = 1; -+ else if (mode == DImode) -+ *total = mips_cost->int_div_di; -+ else -+ *total = mips_cost->int_div_si; -+ return false; -+ -+ case SIGN_EXTEND: -+ *total = mips_sign_extend_cost (mode, XEXP (x, 0)); -+ return false; -+ -+ case ZERO_EXTEND: -+ *total = mips_zero_extend_cost (mode, XEXP (x, 0)); -+ return false; -+ -+ case FLOAT: -+ case UNSIGNED_FLOAT: -+ case FIX: -+ case FLOAT_EXTEND: -+ case FLOAT_TRUNCATE: -+ *total = mips_cost->fp_add; -+ return false; -+ -+ default: -+ return false; -+ } -+} -+ -+/* Implement TARGET_ADDRESS_COST. */ -+ -+static int -+riscv_address_cost (rtx addr, bool speed ATTRIBUTE_UNUSED) -+{ -+ return riscv_address_insns (addr, SImode, false); -+} -+ -+/* Return one word of double-word value OP. HIGH_P is true to select the -+ high part or false to select the low part. */ -+ -+rtx -+mips_subword (rtx op, bool high_p) -+{ -+ unsigned int byte; -+ enum machine_mode mode; -+ -+ mode = GET_MODE (op); -+ if (mode == VOIDmode) -+ mode = TARGET_64BIT ? TImode : DImode; -+ -+ byte = high_p ? UNITS_PER_WORD : 0; -+ -+ if (FP_REG_RTX_P (op)) -+ return gen_rtx_REG (word_mode, REGNO (op) + high_p); -+ -+ if (MEM_P (op)) -+ return adjust_address (op, word_mode, byte); -+ -+ return simplify_gen_subreg (word_mode, op, mode, byte); -+} -+ -+/* Return true if a 64-bit move from SRC to DEST should be split into two. */ -+ -+bool -+mips_split_64bit_move_p (rtx dest, rtx src) -+{ -+ /* All 64b moves are legal in 64b mode. All 64b FPR <-> FPR and -+ FPR <-> MEM moves are legal in 32b mode, too. Although -+ FPR <-> GPR moves are not available in general in 32b mode, -+ we can at least load 0 into an FPR with fcvt.d.w fpr, x0. */ -+ return !(TARGET_64BIT -+ || (FP_REG_RTX_P (src) && FP_REG_RTX_P (dest)) -+ || (FP_REG_RTX_P (dest) && MEM_P (src)) -+ || (FP_REG_RTX_P (src) && MEM_P (dest)) -+ || (FP_REG_RTX_P(dest) && src == CONST0_RTX(GET_MODE(src)))); -+} -+ -+/* Split a doubleword move from SRC to DEST. On 32-bit targets, -+ this function handles 64-bit moves for which mips_split_64bit_move_p -+ holds. For 64-bit targets, this function handles 128-bit moves. */ -+ -+void -+mips_split_doubleword_move (rtx dest, rtx src) -+{ -+ rtx low_dest; -+ -+ /* The operation can be split into two normal moves. Decide in -+ which order to do them. */ -+ low_dest = mips_subword (dest, false); -+ if (REG_P (low_dest) && reg_overlap_mentioned_p (low_dest, src)) -+ { -+ mips_emit_move (mips_subword (dest, true), mips_subword (src, true)); -+ mips_emit_move (low_dest, mips_subword (src, false)); -+ } -+ else -+ { -+ mips_emit_move (low_dest, mips_subword (src, false)); -+ mips_emit_move (mips_subword (dest, true), mips_subword (src, true)); -+ } -+} -+ -+/* Return the appropriate instructions to move SRC into DEST. Assume -+ that SRC is operand 1 and DEST is operand 0. */ -+ -+const char * -+mips_output_move (rtx dest, rtx src) -+{ -+ enum rtx_code dest_code, src_code; -+ enum machine_mode mode; -+ bool dbl_p; -+ -+ dest_code = GET_CODE (dest); -+ src_code = GET_CODE (src); -+ mode = GET_MODE (dest); -+ dbl_p = (GET_MODE_SIZE (mode) == 8); -+ -+ if (dbl_p && mips_split_64bit_move_p (dest, src)) -+ return "#"; -+ -+ if ((src_code == REG && GP_REG_P (REGNO (src))) -+ || (src == CONST0_RTX (mode))) -+ { -+ if (dest_code == REG) -+ { -+ if (GP_REG_P (REGNO (dest))) -+ return "move\t%0,%z1"; -+ -+ if (FP_REG_P (REGNO (dest))) -+ { -+ if (!dbl_p) -+ return "fmv.s.x\t%0,%z1"; -+ if (TARGET_64BIT) -+ return "fmv.d.x\t%0,%z1"; -+ /* in RV32, we can emulate fmv.d.x %0, x0 using fcvt.d.w */ -+ gcc_assert (src == CONST0_RTX (mode)); -+ return "fcvt.d.w\t%0,x0"; -+ } -+ } -+ if (dest_code == MEM) -+ switch (GET_MODE_SIZE (mode)) -+ { -+ case 1: return "sb\t%z1,%0"; -+ case 2: return "sh\t%z1,%0"; -+ case 4: return "sw\t%z1,%0"; -+ case 8: return "sd\t%z1,%0"; -+ } -+ } -+ if (dest_code == REG && GP_REG_P (REGNO (dest))) -+ { -+ if (src_code == REG) -+ { -+ if (FP_REG_P (REGNO (src))) -+ return dbl_p ? "fmv.x.d\t%0,%1" : "fmv.x.s\t%0,%1"; -+ } -+ -+ if (src_code == MEM) -+ switch (GET_MODE_SIZE (mode)) -+ { -+ case 1: return "lbu\t%0,%1"; -+ case 2: return "lhu\t%0,%1"; -+ case 4: return "lw\t%0,%1"; -+ case 8: return "ld\t%0,%1"; -+ } -+ -+ if (src_code == CONST_INT) -+ return "li\t%0,%1"; -+ -+ if (src_code == HIGH) -+ return "lui\t%0,%h1"; -+ -+ if (symbolic_operand (src, VOIDmode)) -+ { -+ if (SYMBOL_REF_LOCAL_P (src) -+ || (src_code == LABEL_REF && !LABEL_REF_NONLOCAL_P (src))) -+ return "lla\t%0,%1"; -+ return "la\t%0,%1"; -+ } -+ } -+ if (src_code == REG && FP_REG_P (REGNO (src))) -+ { -+ if (dest_code == REG && FP_REG_P (REGNO (dest))) -+ return dbl_p ? "fmv.d\t%0,%1" : "fmv.s\t%0,%1"; -+ -+ if (dest_code == MEM) -+ return dbl_p ? "fsd\t%1,%0" : "fsw\t%1,%0"; -+ } -+ if (dest_code == REG && FP_REG_P (REGNO (dest))) -+ { -+ if (src_code == MEM) -+ return dbl_p ? "fld\t%0,%1" : "flw\t%0,%1"; -+ } -+ gcc_unreachable (); -+} -+ -+/* Return true if CMP1 is a suitable second operand for integer ordering -+ test CODE. See also the *sCC patterns in mips.md. */ -+ -+static bool -+mips_int_order_operand_ok_p (enum rtx_code code, rtx cmp1) -+{ -+ switch (code) -+ { -+ case GT: -+ case GTU: -+ return reg_or_0_operand (cmp1, VOIDmode); -+ -+ case GE: -+ case GEU: -+ return cmp1 == const1_rtx; -+ -+ case LT: -+ case LTU: -+ return arith_operand (cmp1, VOIDmode); -+ -+ case LE: -+ return sle_operand (cmp1, VOIDmode); -+ -+ case LEU: -+ return sleu_operand (cmp1, VOIDmode); -+ -+ default: -+ gcc_unreachable (); -+ } -+} -+ -+/* Return true if *CMP1 (of mode MODE) is a valid second operand for -+ integer ordering test *CODE, or if an equivalent combination can -+ be formed by adjusting *CODE and *CMP1. When returning true, update -+ *CODE and *CMP1 with the chosen code and operand, otherwise leave -+ them alone. */ -+ -+static bool -+mips_canonicalize_int_order_test (enum rtx_code *code, rtx *cmp1, -+ enum machine_mode mode) -+{ -+ HOST_WIDE_INT plus_one; -+ -+ if (mips_int_order_operand_ok_p (*code, *cmp1)) -+ return true; -+ -+ if (CONST_INT_P (*cmp1)) -+ switch (*code) -+ { -+ case LE: -+ plus_one = trunc_int_for_mode (UINTVAL (*cmp1) + 1, mode); -+ if (INTVAL (*cmp1) < plus_one) -+ { -+ *code = LT; -+ *cmp1 = force_reg (mode, GEN_INT (plus_one)); -+ return true; -+ } -+ break; -+ -+ case LEU: -+ plus_one = trunc_int_for_mode (UINTVAL (*cmp1) + 1, mode); -+ if (plus_one != 0) -+ { -+ *code = LTU; -+ *cmp1 = force_reg (mode, GEN_INT (plus_one)); -+ return true; -+ } -+ break; -+ -+ default: -+ break; -+ } -+ return false; -+} -+ -+/* Compare CMP0 and CMP1 using ordering test CODE and store the result -+ in TARGET. CMP0 and TARGET are register_operands. If INVERT_PTR -+ is nonnull, it's OK to set TARGET to the inverse of the result and -+ flip *INVERT_PTR instead. */ -+ -+static void -+mips_emit_int_order_test (enum rtx_code code, bool *invert_ptr, -+ rtx target, rtx cmp0, rtx cmp1) -+{ -+ enum machine_mode mode; -+ -+ /* First see if there is a MIPS instruction that can do this operation. -+ If not, try doing the same for the inverse operation. If that also -+ fails, force CMP1 into a register and try again. */ -+ mode = GET_MODE (cmp0); -+ if (mips_canonicalize_int_order_test (&code, &cmp1, mode)) -+ mips_emit_binary (code, target, cmp0, cmp1); -+ else -+ { -+ enum rtx_code inv_code = reverse_condition (code); -+ if (!mips_canonicalize_int_order_test (&inv_code, &cmp1, mode)) -+ { -+ cmp1 = force_reg (mode, cmp1); -+ mips_emit_int_order_test (code, invert_ptr, target, cmp0, cmp1); -+ } -+ else if (invert_ptr == 0) -+ { -+ rtx inv_target; -+ -+ inv_target = mips_force_binary (GET_MODE (target), -+ inv_code, cmp0, cmp1); -+ mips_emit_binary (XOR, target, inv_target, const1_rtx); -+ } -+ else -+ { -+ *invert_ptr = !*invert_ptr; -+ mips_emit_binary (inv_code, target, cmp0, cmp1); -+ } -+ } -+} -+ -+/* Return a register that is zero iff CMP0 and CMP1 are equal. -+ The register will have the same mode as CMP0. */ -+ -+static rtx -+mips_zero_if_equal (rtx cmp0, rtx cmp1) -+{ -+ if (cmp1 == const0_rtx) -+ return cmp0; -+ -+ return expand_binop (GET_MODE (cmp0), sub_optab, -+ cmp0, cmp1, 0, 0, OPTAB_DIRECT); -+} -+ -+/* Return false if we can easily emit code for the FP comparison specified -+ by *CODE. If not, set *CODE to its inverse and return true. */ -+ -+static bool -+riscv_reversed_fp_cond (enum rtx_code *code) -+{ -+ switch (*code) -+ { -+ case EQ: -+ case LT: -+ case LE: -+ case GT: -+ case GE: -+ case LTGT: -+ case ORDERED: -+ /* We know how to emit code for these cases... */ -+ return false; -+ -+ default: -+ /* ...but we must invert these and rely on the others. */ -+ *code = reverse_condition_maybe_unordered (*code); -+ return true; -+ } -+} -+ -+/* Convert a comparison into something that can be used in a branch or -+ conditional move. On entry, *OP0 and *OP1 are the values being -+ compared and *CODE is the code used to compare them. -+ -+ Update *CODE, *OP0 and *OP1 so that they describe the final comparison. */ -+ -+static void -+mips_emit_compare (enum rtx_code *code, rtx *op0, rtx *op1) -+{ -+ rtx cmp_op0 = *op0; -+ rtx cmp_op1 = *op1; -+ -+ if (GET_MODE_CLASS (GET_MODE (*op0)) == MODE_INT) -+ { -+ if (*op1 == const0_rtx) -+ ; -+ else if ((*code == EQ || *code == NE) && CONST_INT_P (cmp_op1) -+ && SMALL_OPERAND (-INTVAL (cmp_op1))) -+ { -+ *op0 = gen_reg_rtx (GET_MODE (cmp_op0)); -+ mips_emit_binary (PLUS, *op0, cmp_op0, GEN_INT (-INTVAL (cmp_op1))); -+ *op1 = const0_rtx; -+ } -+ else if (*op1 != const0_rtx) -+ *op1 = force_reg (GET_MODE (cmp_op0), cmp_op1); -+ } -+ else -+ { -+ /* For FP comparisons, set an integer register with the result of the -+ comparison, then branch on it. */ -+ rtx tmp0, tmp1, final_op; -+ enum rtx_code fp_code = *code; -+ *code = riscv_reversed_fp_cond (&fp_code) ? EQ : NE; -+ -+ switch (fp_code) -+ { -+ case ORDERED: -+ /* a == a && b == b */ -+ tmp0 = gen_reg_rtx (SImode); -+ mips_emit_binary (EQ, tmp0, cmp_op0, cmp_op0); -+ tmp1 = gen_reg_rtx (SImode); -+ mips_emit_binary (EQ, tmp1, cmp_op1, cmp_op1); -+ final_op = gen_reg_rtx (SImode); -+ mips_emit_binary (AND, final_op, tmp0, tmp1); -+ break; -+ -+ case LTGT: -+ /* a < b || a > b */ -+ tmp0 = gen_reg_rtx (SImode); -+ mips_emit_binary (LT, tmp0, cmp_op0, cmp_op1); -+ tmp1 = gen_reg_rtx (SImode); -+ mips_emit_binary (GT, tmp1, cmp_op0, cmp_op1); -+ final_op = gen_reg_rtx (SImode); -+ mips_emit_binary (IOR, final_op, tmp0, tmp1); -+ break; -+ -+ case EQ: -+ case LE: -+ case LT: -+ case GE: -+ case GT: -+ /* We have instructions for these cases. */ -+ final_op = gen_reg_rtx (SImode); -+ mips_emit_binary (fp_code, final_op, cmp_op0, cmp_op1); -+ break; -+ -+ default: -+ gcc_unreachable (); -+ } -+ -+ /* Compare the binary result against 0. */ -+ *op0 = final_op; -+ *op1 = const0_rtx; -+ } -+} -+ -+/* Try performing the comparison in OPERANDS[1], whose arms are OPERANDS[2] -+ and OPERAND[3]. Store the result in OPERANDS[0]. -+ -+ On 64-bit targets, the mode of the comparison and target will always be -+ SImode, thus possibly narrower than that of the comparison's operands. */ -+ -+void -+riscv_expand_scc (rtx operands[]) -+{ -+ rtx target = operands[0]; -+ enum rtx_code code = GET_CODE (operands[1]); -+ rtx op0 = operands[2]; -+ rtx op1 = operands[3]; -+ -+ gcc_assert (GET_MODE_CLASS (GET_MODE (op0)) == MODE_INT); -+ -+ if (code == EQ || code == NE) -+ { -+ rtx zie = mips_zero_if_equal (op0, op1); -+ mips_emit_binary (code, target, zie, const0_rtx); -+ } -+ else -+ mips_emit_int_order_test (code, 0, target, op0, op1); -+} -+ -+/* Compare OPERANDS[1] with OPERANDS[2] using comparison code -+ CODE and jump to OPERANDS[3] if the condition holds. */ -+ -+void -+riscv_expand_conditional_branch (rtx *operands) -+{ -+ enum rtx_code code = GET_CODE (operands[0]); -+ rtx op0 = operands[1]; -+ rtx op1 = operands[2]; -+ rtx condition; -+ -+ mips_emit_compare (&code, &op0, &op1); -+ condition = gen_rtx_fmt_ee (code, VOIDmode, op0, op1); -+ emit_jump_insn (gen_condjump (condition, operands[3])); -+} -+ -+/* Fill INFO with information about a single argument. CUM is the -+ cumulative state for earlier arguments. MODE is the mode of this -+ argument and TYPE is its type (if known). NAMED is true if this -+ is a named (fixed) argument rather than a variable one. */ -+ -+static void -+mips_get_arg_info (struct mips_arg_info *info, const CUMULATIVE_ARGS *cum, -+ enum machine_mode mode, const_tree type, bool named) -+{ -+ bool doubleword_aligned_p; -+ unsigned int num_bytes, num_words, max_regs; -+ -+ /* Work out the size of the argument. */ -+ num_bytes = type ? int_size_in_bytes (type) : GET_MODE_SIZE (mode); -+ num_words = (num_bytes + UNITS_PER_WORD - 1) / UNITS_PER_WORD; -+ -+ /* Scalar, complex and vector floating-point types are passed in -+ floating-point registers, as long as this is a named rather -+ than a variable argument. */ -+ info->fpr_p = (named -+ && (type == 0 || FLOAT_TYPE_P (type)) -+ && (GET_MODE_CLASS (mode) == MODE_FLOAT -+ || GET_MODE_CLASS (mode) == MODE_COMPLEX_FLOAT -+ || GET_MODE_CLASS (mode) == MODE_VECTOR_FLOAT) -+ && GET_MODE_UNIT_SIZE (mode) <= UNITS_PER_FPVALUE); -+ -+ /* Complex floats should only go into FPRs if there are two FPRs free, -+ otherwise they should be passed in the same way as a struct -+ containing two floats. */ -+ if (info->fpr_p -+ && GET_MODE_CLASS (mode) == MODE_COMPLEX_FLOAT -+ && GET_MODE_UNIT_SIZE (mode) < UNITS_PER_FPVALUE) -+ { -+ if (cum->num_gprs >= MAX_ARGS_IN_REGISTERS - 1) -+ info->fpr_p = false; -+ else -+ num_words = 2; -+ } -+ -+ /* See whether the argument has doubleword alignment. */ -+ doubleword_aligned_p = (mips_function_arg_boundary (mode, type) -+ > BITS_PER_WORD); -+ -+ /* Set REG_OFFSET to the register count we're interested in. -+ The EABI allocates the floating-point registers separately, -+ but the other ABIs allocate them like integer registers. */ -+ info->reg_offset = cum->num_gprs; -+ -+ /* Advance to an even register if the argument is doubleword-aligned. */ -+ if (doubleword_aligned_p) -+ info->reg_offset += info->reg_offset & 1; -+ -+ /* Work out the offset of a stack argument. */ -+ info->stack_offset = cum->stack_words; -+ if (doubleword_aligned_p) -+ info->stack_offset += info->stack_offset & 1; -+ -+ max_regs = MAX_ARGS_IN_REGISTERS - info->reg_offset; -+ -+ /* Partition the argument between registers and stack. */ -+ info->reg_words = MIN (num_words, max_regs); -+ info->stack_words = num_words - info->reg_words; -+} -+ -+/* INFO describes a register argument that has the normal format for the -+ argument's mode. Return the register it uses, assuming that FPRs are -+ available if HARD_FLOAT_P. */ -+ -+static unsigned int -+mips_arg_regno (const struct mips_arg_info *info, bool hard_float_p) -+{ -+ if (!info->fpr_p || !hard_float_p) -+ return GP_ARG_FIRST + info->reg_offset; -+ else -+ return FP_ARG_FIRST + info->reg_offset; -+} -+ -+/* Implement TARGET_FUNCTION_ARG. */ -+ -+static rtx -+mips_function_arg (CUMULATIVE_ARGS *cum, enum machine_mode mode, -+ const_tree type, bool named) -+{ -+ struct mips_arg_info info; -+ -+ if (mode == VOIDmode) -+ return NULL; -+ -+ mips_get_arg_info (&info, cum, mode, type, named); -+ -+ /* Return straight away if the whole argument is passed on the stack. */ -+ if (info.reg_offset == MAX_ARGS_IN_REGISTERS) -+ return NULL; -+ -+ /* The n32 and n64 ABIs say that if any 64-bit chunk of the structure -+ contains a double in its entirety, then that 64-bit chunk is passed -+ in a floating-point register. */ -+ if (TARGET_HARD_FLOAT -+ && named -+ && type != 0 -+ && TREE_CODE (type) == RECORD_TYPE -+ && TYPE_SIZE_UNIT (type) -+ && host_integerp (TYPE_SIZE_UNIT (type), 1)) -+ { -+ tree field; -+ -+ /* First check to see if there is any such field. */ -+ for (field = TYPE_FIELDS (type); field; field = DECL_CHAIN (field)) -+ if (TREE_CODE (field) == FIELD_DECL -+ && SCALAR_FLOAT_TYPE_P (TREE_TYPE (field)) -+ && TYPE_PRECISION (TREE_TYPE (field)) == BITS_PER_WORD -+ && host_integerp (bit_position (field), 0) -+ && int_bit_position (field) % BITS_PER_WORD == 0) -+ break; -+ -+ if (field != 0) -+ { -+ /* Now handle the special case by returning a PARALLEL -+ indicating where each 64-bit chunk goes. INFO.REG_WORDS -+ chunks are passed in registers. */ -+ unsigned int i; -+ HOST_WIDE_INT bitpos; -+ rtx ret; -+ -+ /* assign_parms checks the mode of ENTRY_PARM, so we must -+ use the actual mode here. */ -+ ret = gen_rtx_PARALLEL (mode, rtvec_alloc (info.reg_words)); -+ -+ bitpos = 0; -+ field = TYPE_FIELDS (type); -+ for (i = 0; i < info.reg_words; i++) -+ { -+ rtx reg; -+ -+ for (; field; field = DECL_CHAIN (field)) -+ if (TREE_CODE (field) == FIELD_DECL -+ && int_bit_position (field) >= bitpos) -+ break; -+ -+ if (field -+ && int_bit_position (field) == bitpos -+ && SCALAR_FLOAT_TYPE_P (TREE_TYPE (field)) -+ && TYPE_PRECISION (TREE_TYPE (field)) == BITS_PER_WORD) -+ reg = gen_rtx_REG (DFmode, FP_ARG_FIRST + info.reg_offset + i); -+ else -+ reg = gen_rtx_REG (DImode, GP_ARG_FIRST + info.reg_offset + i); -+ -+ XVECEXP (ret, 0, i) -+ = gen_rtx_EXPR_LIST (VOIDmode, reg, -+ GEN_INT (bitpos / BITS_PER_UNIT)); -+ -+ bitpos += BITS_PER_WORD; -+ } -+ return ret; -+ } -+ } -+ -+ /* Handle the n32/n64 conventions for passing complex floating-point -+ arguments in FPR pairs. The real part goes in the lower register -+ and the imaginary part goes in the upper register. */ -+ if (info.fpr_p -+ && GET_MODE_CLASS (mode) == MODE_COMPLEX_FLOAT) -+ { -+ rtx real, imag; -+ enum machine_mode inner; -+ unsigned int regno; -+ -+ inner = GET_MODE_INNER (mode); -+ regno = FP_ARG_FIRST + info.reg_offset; -+ if (info.reg_words * UNITS_PER_WORD == GET_MODE_SIZE (inner)) -+ { -+ /* Real part in registers, imaginary part on stack. */ -+ gcc_assert (info.stack_words == info.reg_words); -+ return gen_rtx_REG (inner, regno); -+ } -+ else -+ { -+ gcc_assert (info.stack_words == 0); -+ real = gen_rtx_EXPR_LIST (VOIDmode, -+ gen_rtx_REG (inner, regno), -+ const0_rtx); -+ imag = gen_rtx_EXPR_LIST (VOIDmode, -+ gen_rtx_REG (inner, -+ regno + info.reg_words / 2), -+ GEN_INT (GET_MODE_SIZE (inner))); -+ return gen_rtx_PARALLEL (mode, gen_rtvec (2, real, imag)); -+ } -+ } -+ -+ return gen_rtx_REG (mode, mips_arg_regno (&info, TARGET_HARD_FLOAT)); -+} -+ -+/* Implement TARGET_FUNCTION_ARG_ADVANCE. */ -+ -+static void -+mips_function_arg_advance (CUMULATIVE_ARGS *cum, enum machine_mode mode, -+ const_tree type, bool named) -+{ -+ struct mips_arg_info info; -+ -+ mips_get_arg_info (&info, cum, mode, type, named); -+ -+ /* Advance the register count. This has the effect of setting -+ num_gprs to MAX_ARGS_IN_REGISTERS if a doubleword-aligned -+ argument required us to skip the final GPR and pass the whole -+ argument on the stack. */ -+ cum->num_gprs = info.reg_offset + info.reg_words; -+ -+ /* Advance the stack word count. */ -+ if (info.stack_words > 0) -+ cum->stack_words = info.stack_offset + info.stack_words; -+} -+ -+/* Implement TARGET_ARG_PARTIAL_BYTES. */ -+ -+static int -+mips_arg_partial_bytes (CUMULATIVE_ARGS *cum, -+ enum machine_mode mode, tree type, bool named) -+{ -+ struct mips_arg_info info; -+ -+ mips_get_arg_info (&info, cum, mode, type, named); -+ return info.stack_words > 0 ? info.reg_words * UNITS_PER_WORD : 0; -+} -+ -+/* Implement TARGET_FUNCTION_ARG_BOUNDARY. Every parameter gets at -+ least PARM_BOUNDARY bits of alignment, but will be given anything up -+ to STACK_BOUNDARY bits if the type requires it. */ -+ -+static unsigned int -+mips_function_arg_boundary (enum machine_mode mode, const_tree type) -+{ -+ unsigned int alignment; -+ -+ alignment = type ? TYPE_ALIGN (type) : GET_MODE_ALIGNMENT (mode); -+ if (alignment < PARM_BOUNDARY) -+ alignment = PARM_BOUNDARY; -+ if (alignment > STACK_BOUNDARY) -+ alignment = STACK_BOUNDARY; -+ return alignment; -+} -+ -+/* See whether VALTYPE is a record whose fields should be returned in -+ floating-point registers. If so, return the number of fields and -+ list them in FIELDS (which should have two elements). Return 0 -+ otherwise. -+ -+ For n32 & n64, a structure with one or two fields is returned in -+ floating-point registers as long as every field has a floating-point -+ type. */ -+ -+static int -+mips_fpr_return_fields (const_tree valtype, tree *fields) -+{ -+ tree field; -+ int i; -+ -+ if (TREE_CODE (valtype) != RECORD_TYPE) -+ return 0; -+ -+ i = 0; -+ for (field = TYPE_FIELDS (valtype); field != 0; field = DECL_CHAIN (field)) -+ { -+ if (TREE_CODE (field) != FIELD_DECL) -+ continue; -+ -+ if (!SCALAR_FLOAT_TYPE_P (TREE_TYPE (field))) -+ return 0; -+ -+ if (i == 2) -+ return 0; -+ -+ fields[i++] = field; -+ } -+ return i; -+} -+ -+/* Return true if the function return value MODE will get returned in a -+ floating-point register. */ -+ -+static bool -+mips_return_mode_in_fpr_p (enum machine_mode mode) -+{ -+ return ((GET_MODE_CLASS (mode) == MODE_FLOAT -+ || GET_MODE_CLASS (mode) == MODE_VECTOR_FLOAT -+ || GET_MODE_CLASS (mode) == MODE_COMPLEX_FLOAT) -+ && GET_MODE_UNIT_SIZE (mode) <= UNITS_PER_HWFPVALUE); -+} -+ -+/* Return the representation of an FPR return register when the -+ value being returned in FP_RETURN has mode VALUE_MODE and the -+ return type itself has mode TYPE_MODE. On NewABI targets, -+ the two modes may be different for structures like: -+ -+ struct __attribute__((packed)) foo { float f; } -+ -+ where we return the SFmode value of "f" in FP_RETURN, but where -+ the structure itself has mode BLKmode. */ -+ -+static rtx -+mips_return_fpr_single (enum machine_mode type_mode, -+ enum machine_mode value_mode) -+{ -+ rtx x; -+ -+ x = gen_rtx_REG (value_mode, FP_RETURN); -+ if (type_mode != value_mode) -+ { -+ x = gen_rtx_EXPR_LIST (VOIDmode, x, const0_rtx); -+ x = gen_rtx_PARALLEL (type_mode, gen_rtvec (1, x)); -+ } -+ return x; -+} -+ -+/* Return a composite value in a pair of floating-point registers. -+ MODE1 and OFFSET1 are the mode and byte offset for the first value, -+ likewise MODE2 and OFFSET2 for the second. MODE is the mode of the -+ complete value. -+ -+ For n32 & n64, $f0 always holds the first value and $f2 the second. -+ Otherwise the values are packed together as closely as possible. */ -+ -+static rtx -+mips_return_fpr_pair (enum machine_mode mode, -+ enum machine_mode mode1, HOST_WIDE_INT offset1, -+ enum machine_mode mode2, HOST_WIDE_INT offset2) -+{ -+ return gen_rtx_PARALLEL -+ (mode, -+ gen_rtvec (2, -+ gen_rtx_EXPR_LIST (VOIDmode, -+ gen_rtx_REG (mode1, FP_RETURN), -+ GEN_INT (offset1)), -+ gen_rtx_EXPR_LIST (VOIDmode, -+ gen_rtx_REG (mode2, FP_RETURN + 1), -+ GEN_INT (offset2)))); -+ -+} -+ -+/* Implement FUNCTION_VALUE and LIBCALL_VALUE. For normal calls, -+ VALTYPE is the return type and MODE is VOIDmode. For libcalls, -+ VALTYPE is null and MODE is the mode of the return value. */ -+ -+rtx -+riscv_function_value (const_tree valtype, const_tree func, enum machine_mode mode) -+{ -+ if (valtype) -+ { -+ tree fields[2]; -+ int unsigned_p; -+ -+ mode = TYPE_MODE (valtype); -+ unsigned_p = TYPE_UNSIGNED (valtype); -+ -+ /* Since TARGET_PROMOTE_FUNCTION_MODE unconditionally promotes, -+ return values, promote the mode here too. */ -+ mode = promote_function_mode (valtype, mode, &unsigned_p, func, 1); -+ -+ /* Handle structures whose fields are returned in $f0/$f2. */ -+ switch (mips_fpr_return_fields (valtype, fields)) -+ { -+ case 1: -+ return mips_return_fpr_single (mode, -+ TYPE_MODE (TREE_TYPE (fields[0]))); -+ -+ case 2: -+ return mips_return_fpr_pair (mode, -+ TYPE_MODE (TREE_TYPE (fields[0])), -+ int_byte_position (fields[0]), -+ TYPE_MODE (TREE_TYPE (fields[1])), -+ int_byte_position (fields[1])); -+ } -+ -+ /* Only use FPRs for scalar, complex or vector types. */ -+ if (!FLOAT_TYPE_P (valtype)) -+ return gen_rtx_REG (mode, GP_RETURN); -+ } -+ -+ /* Handle long doubles for n32 & n64. */ -+ if (mode == TFmode) -+ return mips_return_fpr_pair (mode, -+ DImode, 0, -+ DImode, GET_MODE_SIZE (mode) / 2); -+ -+ if (mips_return_mode_in_fpr_p (mode)) -+ { -+ if (GET_MODE_CLASS (mode) == MODE_COMPLEX_FLOAT) -+ return mips_return_fpr_pair (mode, -+ GET_MODE_INNER (mode), 0, -+ GET_MODE_INNER (mode), -+ GET_MODE_SIZE (mode) / 2); -+ else -+ return gen_rtx_REG (mode, FP_RETURN); -+ } -+ -+ return gen_rtx_REG (mode, GP_RETURN); -+} -+ -+/* Implement TARGET_RETURN_IN_MEMORY. Scalars and small structures -+ that fit in two registers are returned in v0/v1. */ -+ -+static bool -+mips_return_in_memory (const_tree type, const_tree fndecl ATTRIBUTE_UNUSED) -+{ -+ return !IN_RANGE (int_size_in_bytes (type), 0, 2 * UNITS_PER_WORD); -+} -+ -+/* Implement TARGET_PASS_BY_REFERENCE. */ -+ -+static bool -+riscv_pass_by_reference (CUMULATIVE_ARGS *cum ATTRIBUTE_UNUSED, -+ enum machine_mode mode, const_tree type, -+ bool named ATTRIBUTE_UNUSED) -+{ -+ if (type && mips_return_in_memory (type, NULL_TREE)) -+ return true; -+ return targetm.calls.must_pass_in_stack (mode, type); -+} -+ -+/* Implement TARGET_SETUP_INCOMING_VARARGS. */ -+ -+static void -+mips_setup_incoming_varargs (CUMULATIVE_ARGS *cum, enum machine_mode mode, -+ tree type, int *pretend_size ATTRIBUTE_UNUSED, -+ int no_rtl) -+{ -+ CUMULATIVE_ARGS local_cum; -+ int gp_saved; -+ -+ /* The caller has advanced CUM up to, but not beyond, the last named -+ argument. Advance a local copy of CUM past the last "real" named -+ argument, to find out how many registers are left over. */ -+ local_cum = *cum; -+ mips_function_arg_advance (&local_cum, mode, type, true); -+ -+ /* Found out how many registers we need to save. */ -+ gp_saved = MAX_ARGS_IN_REGISTERS - local_cum.num_gprs; -+ -+ if (!no_rtl && gp_saved > 0) -+ { -+ rtx ptr, mem; -+ -+ ptr = plus_constant (virtual_incoming_args_rtx, -+ REG_PARM_STACK_SPACE (cfun->decl) -+ - gp_saved * UNITS_PER_WORD); -+ mem = gen_frame_mem (BLKmode, ptr); -+ set_mem_alias_set (mem, get_varargs_alias_set ()); -+ -+ move_block_from_reg (local_cum.num_gprs + GP_ARG_FIRST, -+ mem, gp_saved); -+ } -+ if (REG_PARM_STACK_SPACE (cfun->decl) == 0) -+ cfun->machine->varargs_size = gp_saved * UNITS_PER_WORD; -+} -+ -+/* Implement TARGET_EXPAND_BUILTIN_VA_START. */ -+ -+static void -+mips_va_start (tree valist, rtx nextarg) -+{ -+ nextarg = plus_constant (nextarg, -cfun->machine->varargs_size); -+ std_expand_builtin_va_start (valist, nextarg); -+} -+ -+/* Expand a call of type TYPE. RESULT is where the result will go (null -+ for "call"s and "sibcall"s), ADDR is the address of the function, -+ ARGS_SIZE is the size of the arguments and AUX is the value passed -+ to us by mips_function_arg. Return the call itself. */ -+ -+rtx -+riscv_expand_call (bool sibcall_p, rtx result, rtx addr, rtx args_size) -+{ -+ rtx pattern; -+ -+ if (!call_insn_operand (addr, VOIDmode)) -+ { -+ rtx reg = RISCV_EPILOGUE_TEMP (Pmode); -+ mips_emit_move (reg, addr); -+ addr = reg; -+ } -+ -+ if (result == 0) -+ { -+ rtx (*fn) (rtx, rtx); -+ -+ if (sibcall_p) -+ fn = gen_sibcall_internal; -+ else -+ fn = gen_call_internal; -+ -+ pattern = fn (addr, args_size); -+ } -+ else if (GET_CODE (result) == PARALLEL && XVECLEN (result, 0) == 2) -+ { -+ /* Handle return values created by mips_return_fpr_pair. */ -+ rtx (*fn) (rtx, rtx, rtx, rtx); -+ rtx reg1, reg2; -+ -+ if (sibcall_p) -+ fn = gen_sibcall_value_multiple_internal; -+ else -+ fn = gen_call_value_multiple_internal; -+ -+ reg1 = XEXP (XVECEXP (result, 0, 0), 0); -+ reg2 = XEXP (XVECEXP (result, 0, 1), 0); -+ pattern = fn (reg1, addr, args_size, reg2); -+ } -+ else -+ { -+ rtx (*fn) (rtx, rtx, rtx); -+ -+ if (sibcall_p) -+ fn = gen_sibcall_value_internal; -+ else -+ fn = gen_call_value_internal; -+ -+ /* Handle return values created by mips_return_fpr_single. */ -+ if (GET_CODE (result) == PARALLEL && XVECLEN (result, 0) == 1) -+ result = XEXP (XVECEXP (result, 0, 0), 0); -+ pattern = fn (result, addr, args_size); -+ } -+ -+ return emit_call_insn (pattern); -+} -+ -+/* Emit straight-line code to move LENGTH bytes from SRC to DEST. -+ Assume that the areas do not overlap. */ -+ -+static void -+riscv_block_move_straight (rtx dest, rtx src, HOST_WIDE_INT length) -+{ -+ HOST_WIDE_INT offset, delta; -+ unsigned HOST_WIDE_INT bits; -+ int i; -+ enum machine_mode mode; -+ rtx *regs; -+ -+ bits = MAX( BITS_PER_UNIT, -+ MIN( BITS_PER_WORD, MIN( MEM_ALIGN(src),MEM_ALIGN(dest) ) ) ); -+ -+ mode = mode_for_size (bits, MODE_INT, 0); -+ delta = bits / BITS_PER_UNIT; -+ -+ /* Allocate a buffer for the temporary registers. */ -+ regs = XALLOCAVEC (rtx, length / delta); -+ -+ /* Load as many BITS-sized chunks as possible. Use a normal load if -+ the source has enough alignment, otherwise use left/right pairs. */ -+ for (offset = 0, i = 0; offset + delta <= length; offset += delta, i++) -+ { -+ regs[i] = gen_reg_rtx (mode); -+ mips_emit_move (regs[i], adjust_address (src, mode, offset)); -+ } -+ -+ /* Copy the chunks to the destination. */ -+ for (offset = 0, i = 0; offset + delta <= length; offset += delta, i++) -+ mips_emit_move (adjust_address (dest, mode, offset), regs[i]); -+ -+ /* Mop up any left-over bytes. */ -+ if (offset < length) -+ { -+ src = adjust_address (src, BLKmode, offset); -+ dest = adjust_address (dest, BLKmode, offset); -+ move_by_pieces (dest, src, length - offset, -+ MIN (MEM_ALIGN (src), MEM_ALIGN (dest)), 0); -+ } -+} -+ -+/* Helper function for doing a loop-based block operation on memory -+ reference MEM. Each iteration of the loop will operate on LENGTH -+ bytes of MEM. -+ -+ Create a new base register for use within the loop and point it to -+ the start of MEM. Create a new memory reference that uses this -+ register. Store them in *LOOP_REG and *LOOP_MEM respectively. */ -+ -+static void -+mips_adjust_block_mem (rtx mem, HOST_WIDE_INT length, -+ rtx *loop_reg, rtx *loop_mem) -+{ -+ *loop_reg = copy_addr_to_reg (XEXP (mem, 0)); -+ -+ /* Although the new mem does not refer to a known location, -+ it does keep up to LENGTH bytes of alignment. */ -+ *loop_mem = change_address (mem, BLKmode, *loop_reg); -+ set_mem_align (*loop_mem, MIN (MEM_ALIGN (mem), length * BITS_PER_UNIT)); -+} -+ -+/* Move LENGTH bytes from SRC to DEST using a loop that moves BYTES_PER_ITER -+ bytes at a time. LENGTH must be at least BYTES_PER_ITER. Assume that -+ the memory regions do not overlap. */ -+ -+static void -+riscv_block_move_loop (rtx dest, rtx src, HOST_WIDE_INT length, -+ HOST_WIDE_INT bytes_per_iter) -+{ -+ rtx label, src_reg, dest_reg, final_src, test; -+ HOST_WIDE_INT leftover; -+ -+ leftover = length % bytes_per_iter; -+ length -= leftover; -+ -+ /* Create registers and memory references for use within the loop. */ -+ mips_adjust_block_mem (src, bytes_per_iter, &src_reg, &src); -+ mips_adjust_block_mem (dest, bytes_per_iter, &dest_reg, &dest); -+ -+ /* Calculate the value that SRC_REG should have after the last iteration -+ of the loop. */ -+ final_src = expand_simple_binop (Pmode, PLUS, src_reg, GEN_INT (length), -+ 0, 0, OPTAB_WIDEN); -+ -+ /* Emit the start of the loop. */ -+ label = gen_label_rtx (); -+ emit_label (label); -+ -+ /* Emit the loop body. */ -+ riscv_block_move_straight (dest, src, bytes_per_iter); -+ -+ /* Move on to the next block. */ -+ mips_emit_move (src_reg, plus_constant (src_reg, bytes_per_iter)); -+ mips_emit_move (dest_reg, plus_constant (dest_reg, bytes_per_iter)); -+ -+ /* Emit the loop condition. */ -+ test = gen_rtx_NE (VOIDmode, src_reg, final_src); -+ if (Pmode == DImode) -+ emit_jump_insn (gen_cbranchdi4 (test, src_reg, final_src, label)); -+ else -+ emit_jump_insn (gen_cbranchsi4 (test, src_reg, final_src, label)); -+ -+ /* Mop up any left-over bytes. */ -+ if (leftover) -+ riscv_block_move_straight (dest, src, leftover); -+} -+ -+/* Expand a movmemsi instruction, which copies LENGTH bytes from -+ memory reference SRC to memory reference DEST. */ -+ -+bool -+riscv_expand_block_move (rtx dest, rtx src, rtx length) -+{ -+ if (CONST_INT_P (length)) -+ { -+ HOST_WIDE_INT factor, align; -+ -+ align = MIN (MIN (MEM_ALIGN (src), MEM_ALIGN (dest)), BITS_PER_WORD); -+ factor = BITS_PER_WORD / align; -+ -+ if (INTVAL (length) <= RISCV_MAX_MOVE_BYTES_STRAIGHT / factor) -+ { -+ riscv_block_move_straight (dest, src, INTVAL (length)); -+ return true; -+ } -+ else if (optimize && align >= BITS_PER_WORD) -+ { -+ riscv_block_move_loop (dest, src, INTVAL (length), -+ RISCV_MAX_MOVE_BYTES_PER_LOOP_ITER / factor); -+ return true; -+ } -+ } -+ return false; -+} -+ -+/* (Re-)Initialize riscv_lo_relocs and riscv_hi_relocs. */ -+ -+static void -+mips_init_relocs (void) -+{ -+ memset (riscv_hi_relocs, '\0', sizeof (riscv_hi_relocs)); -+ memset (riscv_lo_relocs, '\0', sizeof (riscv_lo_relocs)); -+ -+ if (!flag_pic) -+ { -+ riscv_hi_relocs[SYMBOL_ABSOLUTE] = "%hi("; -+ riscv_lo_relocs[SYMBOL_ABSOLUTE] = "%lo("; -+ -+ riscv_hi_relocs[SYMBOL_TLS_LE] = "%tprel_hi("; -+ riscv_lo_relocs[SYMBOL_TLS_LE] = "%tprel_lo("; -+ -+ riscv_lo_relocs[SYMBOL_TLS_IE] = "%tls_ie_off("; -+ } -+} -+ -+/* Print symbolic operand OP, which is part of a HIGH or LO_SUM -+ in context CONTEXT. RELOCS is the array of relocations to use. */ -+ -+static void -+mips_print_operand_reloc (FILE *file, rtx op, const char **relocs) -+{ -+ enum mips_symbol_type symbol_type; -+ const char *p; -+ -+ symbol_type = mips_classify_symbolic_expression (op); -+ gcc_assert (relocs[symbol_type]); -+ -+ fputs (relocs[symbol_type], file); -+ output_addr_const (file, mips_strip_unspec_address (op)); -+ for (p = relocs[symbol_type]; *p != 0; p++) -+ if (*p == '(') -+ fputc (')', file); -+} -+ -+/* Implement TARGET_PRINT_OPERAND. The MIPS-specific operand codes are: -+ -+ 'h' Print the high-part relocation associated with OP, after stripping -+ any outermost HIGH. -+ 'R' Print the low-part relocation associated with OP. -+ 'C' Print the integer branch condition for comparison OP. -+ 'z' Print $0 if OP is zero, otherwise print OP normally. */ -+ -+static void -+mips_print_operand (FILE *file, rtx op, int letter) -+{ -+ enum rtx_code code; -+ -+ gcc_assert (op); -+ code = GET_CODE (op); -+ -+ switch (letter) -+ { -+ case 'h': -+ if (code == HIGH) -+ op = XEXP (op, 0); -+ mips_print_operand_reloc (file, op, riscv_hi_relocs); -+ break; -+ -+ case 'R': -+ mips_print_operand_reloc (file, op, riscv_lo_relocs); -+ break; -+ -+ case 'C': -+ /* The RTL names match the instruction names. */ -+ fputs (GET_RTX_NAME (code), file); -+ break; -+ -+ default: -+ switch (code) -+ { -+ case REG: -+ if (letter && letter != 'z') -+ output_operand_lossage ("invalid use of '%%%c'", letter); -+ fprintf (file, "%s", reg_names[REGNO (op)]); -+ break; -+ -+ case MEM: -+ if (letter == 'y') -+ fprintf (file, "%s", reg_names[REGNO(XEXP(op, 0))]); -+ else if (letter && letter != 'z') -+ output_operand_lossage ("invalid use of '%%%c'", letter); -+ else -+ output_address (XEXP (op, 0)); -+ break; -+ -+ default: -+ if (letter == 'z' && op == CONST0_RTX (GET_MODE (op))) -+ fputs (reg_names[GP_REG_FIRST], file); -+ else if (letter && letter != 'z') -+ output_operand_lossage ("invalid use of '%%%c'", letter); -+ else -+ output_addr_const (file, mips_strip_unspec_address (op)); -+ break; -+ } -+ } -+} -+ -+/* Implement TARGET_PRINT_OPERAND_ADDRESS. */ -+ -+static void -+mips_print_operand_address (FILE *file, rtx x) -+{ -+ struct mips_address_info addr; -+ -+ if (mips_classify_address (&addr, x, word_mode, true)) -+ switch (addr.type) -+ { -+ case ADDRESS_REG: -+ mips_print_operand (file, addr.offset, 0); -+ fprintf (file, "(%s)", reg_names[REGNO (addr.reg)]); -+ return; -+ -+ case ADDRESS_LO_SUM: -+ mips_print_operand_reloc (file, addr.offset, riscv_lo_relocs); -+ fprintf (file, "(%s)", reg_names[REGNO (addr.reg)]); -+ return; -+ -+ case ADDRESS_CONST_INT: -+ output_addr_const (file, x); -+ fprintf (file, "(%s)", reg_names[GP_REG_FIRST]); -+ return; -+ -+ case ADDRESS_SYMBOLIC: -+ output_addr_const (file, mips_strip_unspec_address (x)); -+ return; -+ } -+ gcc_unreachable (); -+} -+ -+bool -+riscv_size_ok_for_small_data_p (int size) -+{ -+ return g_switch_value && IN_RANGE (size, 1, g_switch_value); -+} -+ -+/* Return true if EXP should be placed in the small data section. */ -+ -+static bool -+riscv_in_small_data_p (const_tree x) -+{ -+ if (TREE_CODE (x) == STRING_CST || TREE_CODE (x) == FUNCTION_DECL) -+ return false; -+ -+ if (TREE_CODE (x) == VAR_DECL && DECL_SECTION_NAME (x)) -+ { -+ const char *sec = TREE_STRING_POINTER (DECL_SECTION_NAME (x)); -+ return strcmp (sec, ".sdata") == 0 || strcmp (sec, ".sbss") == 0; -+ } -+ -+ return riscv_size_ok_for_small_data_p (int_size_in_bytes (TREE_TYPE (x))); -+} -+ -+/* Return a section for X, handling small data. */ -+ -+static section * -+riscv_elf_select_rtx_section (enum machine_mode mode, rtx x, -+ unsigned HOST_WIDE_INT align) -+{ -+ section *s = default_elf_select_rtx_section (mode, x, align); -+ -+ if (riscv_size_ok_for_small_data_p (GET_MODE_SIZE (mode))) -+ { -+ if (strncmp (s->named.name, ".rodata.cst", strlen (".rodata.cst")) == 0) -+ { -+ /* Rename .rodata.cst* to .srodata.cst*. */ -+ char name[32]; -+ sprintf (name, ".s%s", s->named.name + 1); -+ return get_section (name, s->named.common.flags, NULL); -+ } -+ -+ if (s == data_section) -+ return sdata_section; -+ } -+ -+ return s; -+} -+ -+/* Implement TARGET_ASM_OUTPUT_DWARF_DTPREL. */ -+ -+static void ATTRIBUTE_UNUSED -+mips_output_dwarf_dtprel (FILE *file, int size, rtx x) -+{ -+ switch (size) -+ { -+ case 4: -+ fputs ("\t.dtprelword\t", file); -+ break; -+ -+ case 8: -+ fputs ("\t.dtpreldword\t", file); -+ break; -+ -+ default: -+ gcc_unreachable (); -+ } -+ output_addr_const (file, x); -+ fputs ("+0x8000", file); -+} -+ -+/* Make the last instruction frame-related and note that it performs -+ the operation described by FRAME_PATTERN. */ -+ -+static void -+mips_set_frame_expr (rtx frame_pattern) -+{ -+ rtx insn; -+ -+ insn = get_last_insn (); -+ RTX_FRAME_RELATED_P (insn) = 1; -+ REG_NOTES (insn) = alloc_EXPR_LIST (REG_FRAME_RELATED_EXPR, -+ frame_pattern, -+ REG_NOTES (insn)); -+} -+ -+/* Return a frame-related rtx that stores REG at MEM. -+ REG must be a single register. */ -+ -+static rtx -+mips_frame_set (rtx mem, rtx reg) -+{ -+ rtx set; -+ -+ set = gen_rtx_SET (VOIDmode, mem, reg); -+ RTX_FRAME_RELATED_P (set) = 1; -+ -+ return set; -+} -+ -+/* Return true if the current function must save register REGNO. */ -+ -+static bool -+riscv_save_reg_p (unsigned int regno) -+{ -+ bool call_saved = !global_regs[regno] && !call_really_used_regs[regno]; -+ bool might_clobber = crtl->saves_all_registers -+ || df_regs_ever_live_p (regno) -+ || (regno == HARD_FRAME_POINTER_REGNUM -+ && frame_pointer_needed); -+ -+ return (call_saved && might_clobber) -+ || (regno == RETURN_ADDR_REGNUM && crtl->calls_eh_return); -+} -+ -+/* Populate the current function's riscv_frame_info structure. -+ -+ RISC-V stack frames grown downward. High addresses are at the top. -+ -+ +-------------------------------+ -+ | | -+ | incoming stack arguments | -+ | | -+ +-------------------------------+ -+ | | -+ | caller-allocated save area | -+ A | for register arguments | -+ | | -+ +-------------------------------+ <-- incoming stack pointer -+ | | -+ | callee-allocated save area | -+ B | for arguments that are | -+ | split between registers and | -+ | the stack | -+ | | -+ +-------------------------------+ <-- arg_pointer_rtx -+ | | -+ C | callee-allocated save area | -+ | for register varargs | -+ | | -+ +-------------------------------+ <-- hard_frame_pointer_rtx; -+ | | stack_pointer_rtx + gp_sp_offset -+ | GPR save area | + UNITS_PER_WORD -+ | | -+ +-------------------------------+ <-- stack_pointer_rtx + fp_sp_offset -+ | | + UNITS_PER_HWVALUE -+ | FPR save area | -+ | | -+ +-------------------------------+ <-- frame_pointer_rtx (virtual) -+ | | -+ | local variables | -+ | | -+ P +-------------------------------+ -+ | | -+ | outgoing stack arguments | -+ | | -+ +-------------------------------+ -+ | | -+ | caller-allocated save area | -+ | for register arguments | -+ | | -+ +-------------------------------+ <-- stack_pointer_rtx -+ -+ At least two of A, B and C will be empty. -+ -+ Dynamic stack allocations such as alloca insert data at point P. -+ They decrease stack_pointer_rtx but leave frame_pointer_rtx and -+ hard_frame_pointer_rtx unchanged. */ -+ -+static void -+riscv_compute_frame_info (void) -+{ -+ struct riscv_frame_info *frame; -+ HOST_WIDE_INT offset; -+ unsigned int regno, i; -+ -+ frame = &cfun->machine->frame; -+ memset (frame, 0, sizeof (*frame)); -+ -+ /* Find out which GPRs we need to save. */ -+ for (regno = GP_REG_FIRST; regno <= GP_REG_LAST; regno++) -+ if (riscv_save_reg_p (regno)) -+ frame->mask |= 1 << (regno - GP_REG_FIRST); -+ -+ /* If this function calls eh_return, we must also save and restore the -+ EH data registers. */ -+ if (crtl->calls_eh_return) -+ for (i = 0; EH_RETURN_DATA_REGNO (i) != INVALID_REGNUM; i++) -+ frame->mask |= 1 << (EH_RETURN_DATA_REGNO (i) - GP_REG_FIRST); -+ -+ /* Find out which FPRs we need to save. This loop must iterate over -+ the same space as its companion in riscv_for_each_saved_gpr_and_fpr. */ -+ if (TARGET_HARD_FLOAT) -+ for (regno = FP_REG_FIRST; regno <= FP_REG_LAST; regno++) -+ if (riscv_save_reg_p (regno)) -+ frame->fmask |= 1 << (regno - FP_REG_FIRST); -+ -+ /* At the bottom of the frame are any outgoing stack arguments. */ -+ offset = crtl->outgoing_args_size; -+ /* Next are local stack variables. */ -+ offset += RISCV_STACK_ALIGN (get_frame_size ()); -+ /* The virtual frame pointer points above the local variables. */ -+ frame->frame_pointer_offset = offset; -+ /* Next are the callee-saved FPRs. */ -+ if (frame->fmask) -+ { -+ unsigned num_saved = __builtin_popcount(frame->fmask); -+ offset += RISCV_STACK_ALIGN (num_saved * UNITS_PER_FPREG); -+ frame->fp_sp_offset = offset - UNITS_PER_HWFPVALUE; -+ } -+ /* Next are the callee-saved GPRs. */ -+ if (frame->mask) -+ { -+ unsigned num_saved = __builtin_popcount(frame->mask); -+ offset += RISCV_STACK_ALIGN (num_saved * UNITS_PER_WORD); -+ frame->gp_sp_offset = offset - UNITS_PER_WORD; -+ } -+ /* The hard frame pointer points above the callee-saved GPRs. */ -+ frame->hard_frame_pointer_offset = offset; -+ /* Above the hard frame pointer is the callee-allocated varags save area. */ -+ offset += RISCV_STACK_ALIGN (cfun->machine->varargs_size); -+ frame->arg_pointer_offset = offset; -+ /* Next is the callee-allocated area for pretend stack arguments. */ -+ offset += crtl->args.pretend_args_size; -+ frame->total_size = offset; -+ /* Next points the incoming stack pointer and any incoming arguments. */ -+} -+ -+/* Make sure that we're not trying to eliminate to the wrong hard frame -+ pointer. */ -+ -+static bool -+mips_can_eliminate (const int from ATTRIBUTE_UNUSED, const int to) -+{ -+ return (to == HARD_FRAME_POINTER_REGNUM || to == STACK_POINTER_REGNUM); -+} -+ -+/* Implement INITIAL_ELIMINATION_OFFSET. FROM is either the frame pointer -+ or argument pointer. TO is either the stack pointer or hard frame -+ pointer. */ -+ -+HOST_WIDE_INT -+riscv_initial_elimination_offset (int from, int to) -+{ -+ HOST_WIDE_INT src, dest; -+ -+ riscv_compute_frame_info (); -+ -+ if (to == HARD_FRAME_POINTER_REGNUM) -+ dest = cfun->machine->frame.hard_frame_pointer_offset; -+ else if (to == STACK_POINTER_REGNUM) -+ dest = 0; /* this is the base of all offsets */ -+ else -+ gcc_unreachable (); -+ -+ if (from == FRAME_POINTER_REGNUM) -+ src = cfun->machine->frame.frame_pointer_offset; -+ else if (from == ARG_POINTER_REGNUM) -+ src = cfun->machine->frame.arg_pointer_offset; -+ else -+ gcc_unreachable (); -+ -+ return src - dest; -+} -+ -+/* Implement RETURN_ADDR_RTX. We do not support moving back to a -+ previous frame. */ -+ -+rtx -+riscv_return_addr (int count, rtx frame ATTRIBUTE_UNUSED) -+{ -+ if (count != 0) -+ return const0_rtx; -+ -+ return get_hard_reg_initial_val (Pmode, RETURN_ADDR_REGNUM); -+} -+ -+/* Emit code to change the current function's return address to -+ ADDRESS. SCRATCH is available as a scratch register, if needed. -+ ADDRESS and SCRATCH are both word-mode GPRs. */ -+ -+void -+riscv_set_return_address (rtx address, rtx scratch) -+{ -+ rtx slot_address; -+ -+ gcc_assert (BITSET_P (cfun->machine->frame.mask, RETURN_ADDR_REGNUM)); -+ slot_address = mips_add_offset (scratch, stack_pointer_rtx, -+ cfun->machine->frame.gp_sp_offset); -+ mips_emit_move (gen_frame_mem (GET_MODE (address), slot_address), address); -+} -+ -+/* A function to save or store a register. The first argument is the -+ register and the second is the stack slot. */ -+typedef void (*mips_save_restore_fn) (rtx, rtx); -+ -+/* Use FN to save or restore register REGNO. MODE is the register's -+ mode and OFFSET is the offset of its save slot from the current -+ stack pointer. */ -+ -+static void -+mips_save_restore_reg (enum machine_mode mode, int regno, -+ HOST_WIDE_INT offset, mips_save_restore_fn fn) -+{ -+ rtx mem; -+ -+ mem = gen_frame_mem (mode, plus_constant (stack_pointer_rtx, offset)); -+ fn (gen_rtx_REG (mode, regno), mem); -+} -+ -+/* Call FN for each register that is saved by the current function. -+ SP_OFFSET is the offset of the current stack pointer from the start -+ of the frame. */ -+ -+static void -+riscv_for_each_saved_gpr_and_fpr (HOST_WIDE_INT sp_offset, -+ mips_save_restore_fn fn) -+{ -+ HOST_WIDE_INT offset; -+ int regno; -+ -+ /* Save the link register and s-registers. */ -+ offset = cfun->machine->frame.gp_sp_offset - sp_offset; -+ for (regno = GP_REG_FIRST; regno <= GP_REG_LAST-1; regno++) -+ if (BITSET_P (cfun->machine->frame.mask, regno - GP_REG_FIRST)) -+ { -+ mips_save_restore_reg (word_mode, regno, offset, fn); -+ offset -= UNITS_PER_WORD; -+ } -+ -+ /* This loop must iterate over the same space as its companion in -+ riscv_compute_frame_info. */ -+ offset = cfun->machine->frame.fp_sp_offset - sp_offset; -+ for (regno = FP_REG_FIRST; regno <= FP_REG_LAST; regno++) -+ if (BITSET_P (cfun->machine->frame.fmask, regno - FP_REG_FIRST)) -+ { -+ mips_save_restore_reg (DFmode, regno, offset, fn); -+ offset -= GET_MODE_SIZE (DFmode); -+ } -+} -+ -+/* Emit a move from SRC to DEST, given that one of them is a register -+ save slot and that the other is a register. TEMP is a temporary -+ GPR of the same mode that is available if need be. */ -+ -+static void -+riscv_emit_save_slot_move (rtx dest, rtx src, rtx temp) -+{ -+ unsigned int regno; -+ rtx mem; -+ enum reg_class rclass; -+ -+ if (REG_P (src)) -+ { -+ regno = REGNO (src); -+ mem = dest; -+ } -+ else -+ { -+ regno = REGNO (dest); -+ mem = src; -+ } -+ -+ rclass = riscv_secondary_reload_class (REGNO_REG_CLASS (regno), -+ GET_MODE (mem), mem, mem == src); -+ -+ if (rclass == NO_REGS) -+ mips_emit_move (dest, src); -+ else -+ { -+ gcc_assert (!reg_overlap_mentioned_p (dest, temp)); -+ mips_emit_move (temp, src); -+ mips_emit_move (dest, temp); -+ } -+ if (MEM_P (dest)) -+ mips_set_frame_expr (mips_frame_set (dest, src)); -+} -+ -+/* Save register REG to MEM. Make the instruction frame-related. */ -+ -+static void -+riscv_save_reg (rtx reg, rtx mem) -+{ -+ riscv_emit_save_slot_move (mem, reg, RISCV_PROLOGUE_TEMP (GET_MODE (reg))); -+} -+ -+ -+/* Expand the "prologue" pattern. */ -+ -+void -+riscv_expand_prologue (void) -+{ -+ const struct riscv_frame_info *frame; -+ HOST_WIDE_INT size; -+ rtx insn; -+ -+ frame = &cfun->machine->frame; -+ size = frame->total_size; -+ -+ if (flag_stack_usage) -+ current_function_static_stack_size = size; -+ -+ /* Save the registers. Allocate up to RISCV_MAX_FIRST_STACK_STEP -+ bytes beforehand; this is enough to cover the register save area -+ without going out of range. */ -+ if ((frame->mask | frame->fmask) != 0) -+ { -+ HOST_WIDE_INT step1; -+ -+ step1 = MIN (size, RISCV_MAX_FIRST_STACK_STEP); -+ insn = gen_add3_insn (stack_pointer_rtx, -+ stack_pointer_rtx, -+ GEN_INT (-step1)); -+ RTX_FRAME_RELATED_P (emit_insn (insn)) = 1; -+ size -= step1; -+ riscv_for_each_saved_gpr_and_fpr (size, riscv_save_reg); -+ } -+ -+ /* Set up the frame pointer, if we're using one. */ -+ if (frame_pointer_needed) -+ { -+ insn = gen_add3_insn (hard_frame_pointer_rtx, stack_pointer_rtx, -+ GEN_INT (frame->hard_frame_pointer_offset - size)); -+ RTX_FRAME_RELATED_P (emit_insn (insn)) = 1; -+ } -+ -+ /* Allocate the rest of the frame. */ -+ if (size > 0) -+ { -+ if (SMALL_OPERAND (-size)) -+ RTX_FRAME_RELATED_P (emit_insn (gen_add3_insn (stack_pointer_rtx, -+ stack_pointer_rtx, -+ GEN_INT (-size)))) = 1; -+ else -+ { -+ mips_emit_move (RISCV_PROLOGUE_TEMP (Pmode), GEN_INT (size)); -+ emit_insn (gen_sub3_insn (stack_pointer_rtx, -+ stack_pointer_rtx, -+ RISCV_PROLOGUE_TEMP (Pmode))); -+ -+ /* Describe the combined effect of the previous instructions. */ -+ mips_set_frame_expr -+ (gen_rtx_SET (VOIDmode, stack_pointer_rtx, -+ plus_constant (stack_pointer_rtx, -size))); -+ } -+ } -+} -+ -+/* Emit instructions to restore register REG from slot MEM. */ -+ -+static void -+riscv_restore_reg (rtx reg, rtx mem) -+{ -+ riscv_emit_save_slot_move (reg, mem, RISCV_EPILOGUE_TEMP (GET_MODE (reg))); -+} -+ -+/* Expand an "epilogue" or "sibcall_epilogue" pattern; SIBCALL_P -+ says which. */ -+ -+void -+riscv_expand_epilogue (bool sibcall_p) -+{ -+ const struct riscv_frame_info *frame; -+ HOST_WIDE_INT step1, step2; -+ -+ if (!sibcall_p && mips_can_use_return_insn ()) -+ { -+ emit_jump_insn (gen_return ()); -+ return; -+ } -+ -+ /* Split the frame into two. STEP1 is the amount of stack we should -+ deallocate before restoring the registers. STEP2 is the amount we -+ should deallocate afterwards. -+ -+ Start off by assuming that no registers need to be restored. */ -+ frame = &cfun->machine->frame; -+ step1 = frame->total_size; -+ step2 = 0; -+ -+ /* Move past any dynamic stack allocations. */ -+ if (cfun->calls_alloca) -+ { -+ rtx adjust = GEN_INT (-frame->hard_frame_pointer_offset); -+ if (!SMALL_INT (adjust)) -+ { -+ mips_emit_move (RISCV_EPILOGUE_TEMP (Pmode), adjust); -+ adjust = RISCV_EPILOGUE_TEMP (Pmode); -+ } -+ -+ emit_insn (gen_add3_insn (stack_pointer_rtx, hard_frame_pointer_rtx, adjust)); -+ } -+ -+ /* If we need to restore registers, deallocate as much stack as -+ possible in the second step without going out of range. */ -+ if ((frame->mask | frame->fmask) != 0) -+ { -+ step2 = MIN (step1, RISCV_MAX_FIRST_STACK_STEP); -+ step1 -= step2; -+ } -+ -+ /* Set TARGET to BASE + STEP1. */ -+ if (step1 > 0) -+ { -+ /* Get an rtx for STEP1 that we can add to BASE. */ -+ rtx adjust = GEN_INT (step1); -+ if (!SMALL_OPERAND (step1)) -+ { -+ mips_emit_move (RISCV_EPILOGUE_TEMP (Pmode), adjust); -+ adjust = RISCV_EPILOGUE_TEMP (Pmode); -+ } -+ -+ emit_insn (gen_add3_insn (stack_pointer_rtx, stack_pointer_rtx, adjust)); -+ } -+ -+ /* Restore the registers. */ -+ riscv_for_each_saved_gpr_and_fpr (frame->total_size - step2, -+ riscv_restore_reg); -+ -+ /* Deallocate the final bit of the frame. */ -+ if (step2 > 0) -+ emit_insn (gen_add3_insn (stack_pointer_rtx, stack_pointer_rtx, -+ GEN_INT (step2))); -+ -+ /* Add in the __builtin_eh_return stack adjustment. */ -+ if (crtl->calls_eh_return) -+ emit_insn (gen_add3_insn (stack_pointer_rtx, stack_pointer_rtx, -+ EH_RETURN_STACKADJ_RTX)); -+ -+ if (!sibcall_p) -+ emit_jump_insn (gen_return_internal (gen_rtx_REG (Pmode, RETURN_ADDR_REGNUM))); -+} -+ -+/* Return nonzero if this function is known to have a null epilogue. -+ This allows the optimizer to omit jumps to jumps if no stack -+ was created. */ -+ -+bool -+mips_can_use_return_insn (void) -+{ -+ return reload_completed && cfun->machine->frame.total_size == 0; -+} -+ -+/* Return true if register REGNO can store a value of mode MODE. -+ The result of this function is cached in riscv_hard_regno_mode_ok. */ -+ -+static bool -+riscv_hard_regno_mode_ok_p (unsigned int regno, enum machine_mode mode) -+{ -+ unsigned int size; -+ enum mode_class mclass; -+ -+ /* This is hella bogus but ira_build segfaults on RV32 without it. */ -+ if (VECTOR_MODE_P (mode)) -+ return true; -+ -+ if (mode == CCmode) -+ return GP_REG_P (regno); -+ -+ size = GET_MODE_SIZE (mode); -+ mclass = GET_MODE_CLASS (mode); -+ -+ if (GP_REG_P (regno)) -+ /* Double-word values must be even-register-aligned. */ -+ return ((regno - GP_REG_FIRST) & 1) == 0 || size <= UNITS_PER_WORD; -+ -+ if (FP_REG_P (regno)) -+ { -+ /* Allow TFmode for CCmode reloads. */ -+ if (mode == TFmode) -+ return true; -+ -+ if (mclass == MODE_FLOAT -+ || mclass == MODE_COMPLEX_FLOAT -+ || mclass == MODE_VECTOR_FLOAT) -+ return size <= UNITS_PER_FPVALUE; -+ } -+ -+ return false; -+} -+ -+/* Implement HARD_REGNO_NREGS. */ -+ -+unsigned int -+riscv_hard_regno_nregs (int regno, enum machine_mode mode) -+{ -+ if (FP_REG_P (regno)) -+ return (GET_MODE_SIZE (mode) + UNITS_PER_FPREG - 1) / UNITS_PER_FPREG; -+ -+ /* All other registers are word-sized. */ -+ return (GET_MODE_SIZE (mode) + UNITS_PER_WORD - 1) / UNITS_PER_WORD; -+} -+ -+/* Implement CLASS_MAX_NREGS, taking the maximum of the cases -+ in riscv_hard_regno_nregs. */ -+ -+int -+riscv_class_max_nregs (enum reg_class rclass, enum machine_mode mode) -+{ -+ int size; -+ HARD_REG_SET left; -+ -+ size = 0x8000; -+ COPY_HARD_REG_SET (left, reg_class_contents[(int) rclass]); -+ if (hard_reg_set_intersect_p (left, reg_class_contents[(int) FP_REGS])) -+ { -+ size = MIN (size, UNITS_PER_FPREG); -+ AND_COMPL_HARD_REG_SET (left, reg_class_contents[(int) FP_REGS]); -+ } -+ if (!hard_reg_set_empty_p (left)) -+ size = MIN (size, UNITS_PER_WORD); -+ return (GET_MODE_SIZE (mode) + size - 1) / size; -+} -+ -+/* Implement TARGET_PREFERRED_RELOAD_CLASS. */ -+ -+static reg_class_t -+mips_preferred_reload_class (rtx x, reg_class_t rclass) -+{ -+ return reg_class_subset_p (FP_REGS, rclass) ? FP_REGS : -+ reg_class_subset_p (GR_REGS, rclass) ? GR_REGS : -+ rclass; -+} -+ -+/* RCLASS is a class involved in a REGISTER_MOVE_COST calculation. -+ Return a "canonical" class to represent it in later calculations. */ -+ -+static reg_class_t -+mips_canonicalize_move_class (reg_class_t rclass) -+{ -+ if (reg_class_subset_p (rclass, GENERAL_REGS)) -+ rclass = GENERAL_REGS; -+ -+ return rclass; -+} -+ -+/* Return the cost of moving a value of mode MODE from a register of -+ class FROM to a GPR. Return 0 for classes that are unions of other -+ classes handled by this function. */ -+ -+static int -+mips_move_to_gpr_cost (reg_class_t from) -+{ -+ switch (from) -+ { -+ case GENERAL_REGS: -+ return 1; -+ -+ case FP_REGS: -+ /* FP->int moves can cause recoupling on decoupled implementations */ -+ return 4; -+ -+ default: -+ return 0; -+ } -+} -+ -+/* Return the cost of moving a value of mode MODE from a GPR to a -+ register of class TO. Return 0 for classes that are unions of -+ other classes handled by this function. */ -+ -+static int -+mips_move_from_gpr_cost (reg_class_t to) -+{ -+ switch (to) -+ { -+ case GENERAL_REGS: -+ case FP_REGS: -+ return 1; -+ -+ default: -+ return 0; -+ } -+} -+ -+/* Implement TARGET_REGISTER_MOVE_COST. Return 0 for classes that are the -+ maximum of the move costs for subclasses; regclass will work out -+ the maximum for us. */ -+ -+static int -+mips_register_move_cost (enum machine_mode mode, -+ reg_class_t from, reg_class_t to) -+{ -+ int cost1, cost2; -+ -+ from = mips_canonicalize_move_class (from); -+ to = mips_canonicalize_move_class (to); -+ -+ /* Handle moves that can be done without using general-purpose registers. */ -+ if (from == FP_REGS && to == FP_REGS) -+ /* fmv.fmt. */ -+ return 1; -+ -+ /* Handle cases in which only one class deviates from the ideal. */ -+ if (from == GENERAL_REGS) -+ return mips_move_from_gpr_cost (to); -+ if (to == GENERAL_REGS) -+ return mips_move_to_gpr_cost (from); -+ -+ /* Handles cases that require a GPR temporary. */ -+ cost1 = mips_move_to_gpr_cost (from); -+ if (cost1 != 0) -+ { -+ cost2 = mips_move_from_gpr_cost (to); -+ if (cost2 != 0) -+ return cost1 + cost2; -+ } -+ -+ return 0; -+} -+ -+/* Implement TARGET_MEMORY_MOVE_COST. */ -+ -+static int -+mips_memory_move_cost (enum machine_mode mode, reg_class_t rclass, bool in) -+{ -+ return (mips_cost->memory_latency -+ + memory_move_secondary_cost (mode, rclass, in)); -+} -+ -+/* Implement TARGET_IRA_COVER_CLASSES. */ -+ -+static const reg_class_t * -+mips_ira_cover_classes (void) -+{ -+ static const reg_class_t no_acc_classes[] = { -+ GR_REGS, FP_REGS, -+ LIM_REG_CLASSES -+ }; -+ -+ return no_acc_classes; -+} -+ -+/* Return the register class required for a secondary register when -+ copying between one of the registers in RCLASS and value X, which -+ has mode MODE. X is the source of the move if IN_P, otherwise it -+ is the destination. Return NO_REGS if no secondary register is -+ needed. */ -+ -+enum reg_class -+riscv_secondary_reload_class (enum reg_class rclass, -+ enum machine_mode mode, rtx x, -+ bool in_p ATTRIBUTE_UNUSED) -+{ -+ int regno; -+ -+ regno = true_regnum (x); -+ -+ if (reg_class_subset_p (rclass, FP_REGS)) -+ { -+ if (MEM_P (x) && (GET_MODE_SIZE (mode) == 4 || GET_MODE_SIZE (mode) == 8)) -+ /* We can use flw/fld/fsw/fsd. */ -+ return NO_REGS; -+ -+ if (GP_REG_P (regno) || x == CONST0_RTX (mode)) -+ /* We can use fmv or go through memory when mode > Pmode. */ -+ return NO_REGS; -+ -+ if (CONSTANT_P (x) && !targetm.cannot_force_const_mem (x)) -+ /* We can force the constant to memory and use flw/fld. */ -+ return NO_REGS; -+ -+ if (FP_REG_P (regno)) -+ /* We can use fmv.fmt. */ -+ return NO_REGS; -+ -+ /* Otherwise, we need to reload through an integer register. */ -+ return GR_REGS; -+ } -+ if (FP_REG_P (regno)) -+ return reg_class_subset_p (rclass, GR_REGS) ? NO_REGS : GR_REGS; -+ -+ return NO_REGS; -+} -+ -+/* Implement TARGET_MODE_REP_EXTENDED. */ -+ -+static int -+mips_mode_rep_extended (enum machine_mode mode, enum machine_mode mode_rep) -+{ -+ /* On 64-bit targets, SImode register values are sign-extended to DImode. */ -+ if (TARGET_64BIT && mode == SImode && mode_rep == DImode) -+ return SIGN_EXTEND; -+ -+ return UNKNOWN; -+} -+ -+/* Implement TARGET_SCALAR_MODE_SUPPORTED_P. */ -+ -+static bool -+mips_scalar_mode_supported_p (enum machine_mode mode) -+{ -+ if (ALL_FIXED_POINT_MODE_P (mode) -+ && GET_MODE_PRECISION (mode) <= 2 * BITS_PER_WORD) -+ return true; -+ -+ return default_scalar_mode_supported_p (mode); -+} -+ -+/* Implement TARGET_SCHED_ADJUST_COST. We assume that anti and output -+ dependencies have no cost. */ -+ -+static int -+mips_adjust_cost (rtx insn ATTRIBUTE_UNUSED, rtx link, -+ rtx dep ATTRIBUTE_UNUSED, int cost) -+{ -+ if (REG_NOTE_KIND (link) != 0) -+ return 0; -+ return cost; -+} -+ -+/* Return the number of instructions that can be issued per cycle. */ -+ -+static int -+mips_issue_rate (void) -+{ -+ switch (riscv_tune) -+ { -+ case PROCESSOR_ROCKET: -+ return 1; -+ -+ default: -+ return 1; -+ } -+} -+ -+/* This structure describes a single built-in function. */ -+struct mips_builtin_description { -+ /* The code of the main .md file instruction. See mips_builtin_type -+ for more information. */ -+ enum insn_code icode; -+ -+ /* The name of the built-in function. */ -+ const char *name; -+ -+ /* Specifies how the function should be expanded. */ -+ enum mips_builtin_type builtin_type; -+ -+ /* The function's prototype. */ -+ enum mips_function_type function_type; -+ -+ /* Whether the function is available. */ -+ unsigned int (*avail) (void); -+}; -+ -+static unsigned int -+mips_builtin_avail_riscv (void) -+{ -+ return 1; -+} -+ -+/* Construct a mips_builtin_description from the given arguments. -+ -+ INSN is the name of the associated instruction pattern, without the -+ leading CODE_FOR_mips_. -+ -+ CODE is the floating-point condition code associated with the -+ function. It can be 'f' if the field is not applicable. -+ -+ NAME is the name of the function itself, without the leading -+ "__builtin_mips_". -+ -+ BUILTIN_TYPE and FUNCTION_TYPE are mips_builtin_description fields. -+ -+ AVAIL is the name of the availability predicate, without the leading -+ mips_builtin_avail_. */ -+#define RISCV_BUILTIN(INSN, NAME, BUILTIN_TYPE, FUNCTION_TYPE, AVAIL) \ -+ { CODE_FOR_ ## INSN, "__builtin_riscv_" NAME, \ -+ BUILTIN_TYPE, FUNCTION_TYPE, mips_builtin_avail_ ## AVAIL } -+ -+/* Define __builtin_mips_, which is a RISCV_BUILTIN_DIRECT function -+ mapped to instruction CODE_FOR_, FUNCTION_TYPE and AVAIL -+ are as for RISCV_BUILTIN. */ -+#define DIRECT_BUILTIN(INSN, FUNCTION_TYPE, AVAIL) \ -+ RISCV_BUILTIN (INSN, #INSN, RISCV_BUILTIN_DIRECT, FUNCTION_TYPE, AVAIL) -+ -+/* Define __builtin_riscv_, which is a RISCV_BUILTIN_DIRECT_NO_TARGET -+ function mapped to instruction CODE_FOR_, FUNCTION_TYPE -+ and AVAIL are as for RISCV_BUILTIN. */ -+#define DIRECT_NO_TARGET_BUILTIN(INSN, FUNCTION_TYPE, AVAIL) \ -+ RISCV_BUILTIN (INSN, #INSN, RISCV_BUILTIN_DIRECT_NO_TARGET, \ -+ FUNCTION_TYPE, AVAIL) -+ -+static const struct mips_builtin_description mips_builtins[] = { -+ DIRECT_NO_TARGET_BUILTIN (nop, RISCV_VOID_FTYPE_VOID, riscv), -+}; -+ -+/* Index I is the function declaration for mips_builtins[I], or null if the -+ function isn't defined on this target. */ -+static GTY(()) tree mips_builtin_decls[ARRAY_SIZE (mips_builtins)]; -+ -+/* MODE is a vector mode whose elements have type TYPE. Return the type -+ of the vector itself. */ -+ -+static tree -+mips_builtin_vector_type (tree type, enum machine_mode mode) -+{ -+ static tree types[2 * (int) MAX_MACHINE_MODE]; -+ int mode_index; -+ -+ mode_index = (int) mode; -+ -+ if (TREE_CODE (type) == INTEGER_TYPE && TYPE_UNSIGNED (type)) -+ mode_index += MAX_MACHINE_MODE; -+ -+ if (types[mode_index] == NULL_TREE) -+ types[mode_index] = build_vector_type_for_mode (type, mode); -+ return types[mode_index]; -+} -+ -+/* Source-level argument types. */ -+#define RISCV_ATYPE_VOID void_type_node -+#define RISCV_ATYPE_INT integer_type_node -+#define RISCV_ATYPE_POINTER ptr_type_node -+#define RISCV_ATYPE_CPOINTER const_ptr_type_node -+ -+/* Standard mode-based argument types. */ -+#define RISCV_ATYPE_UQI unsigned_intQI_type_node -+#define RISCV_ATYPE_SI intSI_type_node -+#define RISCV_ATYPE_USI unsigned_intSI_type_node -+#define RISCV_ATYPE_DI intDI_type_node -+#define RISCV_ATYPE_UDI unsigned_intDI_type_node -+#define RISCV_ATYPE_SF float_type_node -+#define RISCV_ATYPE_DF double_type_node -+ -+/* RISCV_FTYPE_ATYPESN takes N RISCV_FTYPES-like type codes and lists -+ their associated RISCV_ATYPEs. */ -+#define RISCV_FTYPE_ATYPES1(A, B) \ -+ RISCV_ATYPE_##A, RISCV_ATYPE_##B -+ -+#define RISCV_FTYPE_ATYPES2(A, B, C) \ -+ RISCV_ATYPE_##A, RISCV_ATYPE_##B, RISCV_ATYPE_##C -+ -+#define RISCV_FTYPE_ATYPES3(A, B, C, D) \ -+ RISCV_ATYPE_##A, RISCV_ATYPE_##B, RISCV_ATYPE_##C, RISCV_ATYPE_##D -+ -+#define RISCV_FTYPE_ATYPES4(A, B, C, D, E) \ -+ RISCV_ATYPE_##A, RISCV_ATYPE_##B, RISCV_ATYPE_##C, RISCV_ATYPE_##D, \ -+ RISCV_ATYPE_##E -+ -+/* Return the function type associated with function prototype TYPE. */ -+ -+static tree -+mips_build_function_type (enum mips_function_type type) -+{ -+ static tree types[(int) RISCV_MAX_FTYPE_MAX]; -+ -+ if (types[(int) type] == NULL_TREE) -+ switch (type) -+ { -+#define DEF_RISCV_FTYPE(NUM, ARGS) \ -+ case RISCV_FTYPE_NAME##NUM ARGS: \ -+ types[(int) type] \ -+ = build_function_type_list (RISCV_FTYPE_ATYPES##NUM ARGS, \ -+ NULL_TREE); \ -+ break; -+#include "config/riscv/riscv-ftypes.def" -+#undef DEF_RISCV_FTYPE -+ default: -+ gcc_unreachable (); -+ } -+ -+ return types[(int) type]; -+} -+ -+/* Implement TARGET_INIT_BUILTINS. */ -+ -+static void -+mips_init_builtins (void) -+{ -+ const struct mips_builtin_description *d; -+ unsigned int i; -+ -+ /* Iterate through all of the bdesc arrays, initializing all of the -+ builtin functions. */ -+ for (i = 0; i < ARRAY_SIZE (mips_builtins); i++) -+ { -+ d = &mips_builtins[i]; -+ if (d->avail ()) -+ mips_builtin_decls[i] -+ = add_builtin_function (d->name, -+ mips_build_function_type (d->function_type), -+ i, BUILT_IN_MD, NULL, NULL); -+ } -+} -+ -+/* Implement TARGET_BUILTIN_DECL. */ -+ -+static tree -+mips_builtin_decl (unsigned int code, bool initialize_p ATTRIBUTE_UNUSED) -+{ -+ if (code >= ARRAY_SIZE (mips_builtins)) -+ return error_mark_node; -+ return mips_builtin_decls[code]; -+} -+ -+/* Take argument ARGNO from EXP's argument list and convert it into a -+ form suitable for input operand OPNO of instruction ICODE. Return the -+ value. */ -+ -+static rtx -+mips_prepare_builtin_arg (enum insn_code icode, -+ unsigned int opno, tree exp, unsigned int argno) -+{ -+ tree arg; -+ rtx value; -+ enum machine_mode mode; -+ -+ arg = CALL_EXPR_ARG (exp, argno); -+ value = expand_normal (arg); -+ mode = insn_data[icode].operand[opno].mode; -+ if (!insn_data[icode].operand[opno].predicate (value, mode)) -+ { -+ /* We need to get the mode from ARG for two reasons: -+ -+ - to cope with address operands, where MODE is the mode of the -+ memory, rather than of VALUE itself. -+ -+ - to cope with special predicates like pmode_register_operand, -+ where MODE is VOIDmode. */ -+ value = copy_to_mode_reg (TYPE_MODE (TREE_TYPE (arg)), value); -+ -+ /* Check the predicate again. */ -+ if (!insn_data[icode].operand[opno].predicate (value, mode)) -+ { -+ error ("invalid argument to built-in function"); -+ return const0_rtx; -+ } -+ } -+ -+ return value; -+} -+ -+/* Return an rtx suitable for output operand OP of instruction ICODE. -+ If TARGET is non-null, try to use it where possible. */ -+ -+static rtx -+mips_prepare_builtin_target (enum insn_code icode, unsigned int op, rtx target) -+{ -+ enum machine_mode mode; -+ -+ mode = insn_data[icode].operand[op].mode; -+ if (target == 0 || !insn_data[icode].operand[op].predicate (target, mode)) -+ target = gen_reg_rtx (mode); -+ -+ return target; -+} -+ -+/* Expand a RISCV_BUILTIN_DIRECT or RISCV_BUILTIN_DIRECT_NO_TARGET function; -+ HAS_TARGET_P says which. EXP is the CALL_EXPR that calls the function -+ and ICODE is the code of the associated .md pattern. TARGET, if nonnull, -+ suggests a good place to put the result. */ -+ -+static rtx -+riscv_expand_builtin_direct (enum insn_code icode, rtx target, tree exp, -+ bool has_target_p) -+{ -+ rtx ops[MAX_RECOG_OPERANDS]; -+ int opno, argno; -+ -+ /* Map any target to operand 0. */ -+ opno = 0; -+ if (has_target_p) -+ { -+ target = mips_prepare_builtin_target (icode, opno, target); -+ ops[opno] = target; -+ opno++; -+ } -+ -+ /* Map the arguments to the other operands. The n_operands value -+ for an expander includes match_dups and match_scratches as well as -+ match_operands, so n_operands is only an upper bound on the number -+ of arguments to the expander function. */ -+ gcc_assert (opno + call_expr_nargs (exp) <= insn_data[icode].n_operands); -+ for (argno = 0; argno < call_expr_nargs (exp); argno++, opno++) -+ ops[opno] = mips_prepare_builtin_arg (icode, opno, exp, argno); -+ -+ switch (opno) -+ { -+ case 2: -+ emit_insn (GEN_FCN (icode) (ops[0], ops[1])); -+ break; -+ -+ case 3: -+ emit_insn (GEN_FCN (icode) (ops[0], ops[1], ops[2])); -+ break; -+ -+ case 4: -+ emit_insn (GEN_FCN (icode) (ops[0], ops[1], ops[2], ops[3])); -+ break; -+ -+ default: -+ gcc_unreachable (); -+ } -+ return target; -+} -+ -+/* Implement TARGET_EXPAND_BUILTIN. */ -+ -+static rtx -+riscv_expand_builtin (tree exp, rtx target, rtx subtarget ATTRIBUTE_UNUSED, -+ enum machine_mode mode ATTRIBUTE_UNUSED, -+ int ignore ATTRIBUTE_UNUSED) -+{ -+ tree fndecl; -+ unsigned int fcode, avail; -+ const struct mips_builtin_description *d; -+ -+ fndecl = TREE_OPERAND (CALL_EXPR_FN (exp), 0); -+ fcode = DECL_FUNCTION_CODE (fndecl); -+ gcc_assert (fcode < ARRAY_SIZE (mips_builtins)); -+ d = &mips_builtins[fcode]; -+ avail = d->avail (); -+ gcc_assert (avail != 0); -+ switch (d->builtin_type) -+ { -+ case RISCV_BUILTIN_DIRECT: -+ return riscv_expand_builtin_direct (d->icode, target, exp, true); -+ -+ case RISCV_BUILTIN_DIRECT_NO_TARGET: -+ return riscv_expand_builtin_direct (d->icode, target, exp, false); -+ } -+ gcc_unreachable (); -+} -+ -+/* This structure records that the current function has a LO_SUM -+ involving SYMBOL_REF or LABEL_REF BASE and that MAX_OFFSET is -+ the largest offset applied to BASE by all such LO_SUMs. */ -+struct mips_lo_sum_offset { -+ rtx base; -+ HOST_WIDE_INT offset; -+}; -+ -+/* Return a hash value for SYMBOL_REF or LABEL_REF BASE. */ -+ -+static hashval_t -+mips_hash_base (rtx base) -+{ -+ int do_not_record_p; -+ -+ return hash_rtx (base, GET_MODE (base), &do_not_record_p, NULL, false); -+} -+ -+/* Hash-table callbacks for mips_lo_sum_offsets. */ -+ -+static hashval_t -+mips_lo_sum_offset_hash (const void *entry) -+{ -+ return mips_hash_base (((const struct mips_lo_sum_offset *) entry)->base); -+} -+ -+static int -+mips_lo_sum_offset_eq (const void *entry, const void *value) -+{ -+ return rtx_equal_p (((const struct mips_lo_sum_offset *) entry)->base, -+ (const_rtx) value); -+} -+ -+/* Look up symbolic constant X in HTAB, which is a hash table of -+ mips_lo_sum_offsets. If OPTION is NO_INSERT, return true if X can be -+ paired with a recorded LO_SUM, otherwise record X in the table. */ -+ -+static bool -+mips_lo_sum_offset_lookup (htab_t htab, rtx x, enum insert_option option) -+{ -+ rtx base, offset; -+ void **slot; -+ struct mips_lo_sum_offset *entry; -+ -+ /* Split X into a base and offset. */ -+ split_const (x, &base, &offset); -+ if (UNSPEC_ADDRESS_P (base)) -+ base = UNSPEC_ADDRESS (base); -+ -+ /* Look up the base in the hash table. */ -+ slot = htab_find_slot_with_hash (htab, base, mips_hash_base (base), option); -+ if (slot == NULL) -+ return false; -+ -+ entry = (struct mips_lo_sum_offset *) *slot; -+ if (option == INSERT) -+ { -+ if (entry == NULL) -+ { -+ entry = XNEW (struct mips_lo_sum_offset); -+ entry->base = base; -+ entry->offset = INTVAL (offset); -+ *slot = entry; -+ } -+ else -+ { -+ if (INTVAL (offset) > entry->offset) -+ entry->offset = INTVAL (offset); -+ } -+ } -+ return INTVAL (offset) <= entry->offset; -+} -+ -+/* A for_each_rtx callback for which DATA is a mips_lo_sum_offset hash table. -+ Record every LO_SUM in *LOC. */ -+ -+static int -+mips_record_lo_sum (rtx *loc, void *data) -+{ -+ if (GET_CODE (*loc) == LO_SUM) -+ mips_lo_sum_offset_lookup ((htab_t) data, XEXP (*loc, 1), INSERT); -+ return 0; -+} -+ -+/* Return true if INSN is a SET of an orphaned high-part relocation. -+ HTAB is a hash table of mips_lo_sum_offsets that describes all the -+ LO_SUMs in the current function. */ -+ -+static bool -+mips_orphaned_high_part_p (htab_t htab, rtx insn) -+{ -+ rtx x, set; -+ -+ set = single_set (insn); -+ if (set) -+ { -+ /* Check for %his. */ -+ x = SET_SRC (set); -+ if (GET_CODE (x) == HIGH -+ && absolute_symbolic_operand (XEXP (x, 0), VOIDmode)) -+ return !mips_lo_sum_offset_lookup (htab, XEXP (x, 0), NO_INSERT); -+ } -+ return false; -+} -+ -+/* Delete any high-part relocations whose partnering low parts are dead. */ -+ -+static void -+mips_reorg_process_insns (void) -+{ -+ rtx insn, next_insn; -+ htab_t htab; -+ -+ /* Force all instructions to be split into their final form. */ -+ split_all_insns_noflow (); -+ -+ /* Recalculate instruction lengths without taking nops into account. */ -+ shorten_branches (get_insns ()); -+ -+ htab = htab_create (37, mips_lo_sum_offset_hash, -+ mips_lo_sum_offset_eq, free); -+ -+ /* Make a first pass over the instructions, recording all the LO_SUMs. */ -+ for (insn = get_insns (); insn != 0; insn = NEXT_INSN (insn)) -+ if (USEFUL_INSN_P (insn)) -+ for_each_rtx (&PATTERN (insn), mips_record_lo_sum, htab); -+ -+ /* Make a second pass over the instructions. Delete orphaned -+ high-part relocations or turn them into NOPs. Avoid hazards -+ by inserting NOPs. */ -+ for (insn = get_insns (); insn != 0; insn = next_insn) -+ { -+ next_insn = NEXT_INSN (insn); -+ if (USEFUL_INSN_P (insn)) -+ { -+ /* INSN is a single instruction. Delete it if it's an -+ orphaned high-part relocation. */ -+ if (mips_orphaned_high_part_p (htab, insn)) -+ delete_insn (insn); -+ } -+ } -+ -+ htab_delete (htab); -+} -+ -+/* Implement TARGET_MACHINE_DEPENDENT_REORG. */ -+ -+static void -+mips_reorg (void) -+{ -+ mips_reorg_process_insns (); -+} -+ -+/* Implement TARGET_ASM_OUTPUT_MI_THUNK. Generate rtl rather than asm text -+ in order to avoid duplicating too much logic from elsewhere. */ -+ -+static void -+mips_output_mi_thunk (FILE *file, tree thunk_fndecl ATTRIBUTE_UNUSED, -+ HOST_WIDE_INT delta, HOST_WIDE_INT vcall_offset, -+ tree function) -+{ -+ rtx this_rtx, temp1, temp2, insn, fnaddr; -+ bool use_sibcall_p; -+ -+ /* Pretend to be a post-reload pass while generating rtl. */ -+ reload_completed = 1; -+ -+ /* Mark the end of the (empty) prologue. */ -+ emit_note (NOTE_INSN_PROLOGUE_END); -+ -+ /* Determine if we can use a sibcall to call FUNCTION directly. */ -+ fnaddr = XEXP (DECL_RTL (function), 0); -+ use_sibcall_p = absolute_symbolic_operand (fnaddr, Pmode); -+ -+ /* We need two temporary registers in some cases. */ -+ temp1 = gen_rtx_REG (Pmode, GP_RETURN); -+ temp2 = gen_rtx_REG (Pmode, GP_RETURN + 1); -+ -+ /* Find out which register contains the "this" pointer. */ -+ if (aggregate_value_p (TREE_TYPE (TREE_TYPE (function)), function)) -+ this_rtx = gen_rtx_REG (Pmode, GP_ARG_FIRST + 1); -+ else -+ this_rtx = gen_rtx_REG (Pmode, GP_ARG_FIRST); -+ -+ /* Add DELTA to THIS_RTX. */ -+ if (delta != 0) -+ { -+ rtx offset = GEN_INT (delta); -+ if (!SMALL_OPERAND (delta)) -+ { -+ mips_emit_move (temp1, offset); -+ offset = temp1; -+ } -+ emit_insn (gen_add3_insn (this_rtx, this_rtx, offset)); -+ } -+ -+ /* If needed, add *(*THIS_RTX + VCALL_OFFSET) to THIS_RTX. */ -+ if (vcall_offset != 0) -+ { -+ rtx addr; -+ -+ /* Set TEMP1 to *THIS_RTX. */ -+ mips_emit_move (temp1, gen_rtx_MEM (Pmode, this_rtx)); -+ -+ /* Set ADDR to a legitimate address for *THIS_RTX + VCALL_OFFSET. */ -+ addr = mips_add_offset (temp2, temp1, vcall_offset); -+ -+ /* Load the offset and add it to THIS_RTX. */ -+ mips_emit_move (temp1, gen_rtx_MEM (Pmode, addr)); -+ emit_insn (gen_add3_insn (this_rtx, this_rtx, temp1)); -+ } -+ -+ /* Jump to the target function. Use a sibcall if direct jumps are -+ allowed, otherwise load the address into a register first. */ -+ if (use_sibcall_p) -+ { -+ insn = emit_call_insn (gen_sibcall_internal (fnaddr, const0_rtx)); -+ SIBLING_CALL_P (insn) = 1; -+ } -+ else -+ { -+ mips_emit_move(temp1, fnaddr); -+ emit_jump_insn (gen_indirect_jump (temp1)); -+ } -+ -+ /* Run just enough of rest_of_compilation. This sequence was -+ "borrowed" from alpha.c. */ -+ insn = get_insns (); -+ insn_locators_alloc (); -+ split_all_insns_noflow (); -+ shorten_branches (insn); -+ final_start_function (insn, file, 1); -+ final (insn, file, 1); -+ final_end_function (); -+ -+ /* Clean up the vars set above. Note that final_end_function resets -+ the global pointer for us. */ -+ reload_completed = 0; -+} -+ -+/* Allocate a chunk of memory for per-function machine-dependent data. */ -+ -+static struct machine_function * -+mips_init_machine_status (void) -+{ -+ return ggc_alloc_cleared_machine_function (); -+} -+ -+/* Return the riscv_cpu_info entry for the processor or ISA given -+ by CPU_STRING. Return null if the string isn't recognized. -+ -+ A similar function exists in GAS. */ -+ -+static const struct riscv_cpu_info * -+mips_parse_cpu (const char *cpu_string) -+{ -+ unsigned int i; -+ -+ for (i = 0; i < ARRAY_SIZE (riscv_cpu_info_table); i++) -+ if (strcmp (riscv_cpu_info_table[i].name, cpu_string) == 0) -+ return riscv_cpu_info_table + i; -+ -+ return NULL; -+} -+ -+/* Implement TARGET_HANDLE_OPTION. */ -+ -+static bool -+mips_handle_option (size_t code, const char *arg, int value ATTRIBUTE_UNUSED) -+{ -+ switch (code) -+ { -+ case OPT_mtune_: -+ return mips_parse_cpu (arg) != 0; -+ -+ default: -+ return true; -+ } -+} -+ -+/* Implement TARGET_OPTION_OVERRIDE. */ -+ -+static void -+mips_option_override (void) -+{ -+ int regno, mode; -+ const struct riscv_cpu_info *info; -+ -+#ifdef SUBTARGET_OVERRIDE_OPTIONS -+ SUBTARGET_OVERRIDE_OPTIONS; -+#endif -+ -+ info = mips_parse_cpu (RISCV_CPU_STRING_DEFAULT); -+ gcc_assert (info); -+ riscv_tune = info->cpu; -+ -+ if (riscv_tune_string != 0) -+ { -+ const struct riscv_cpu_info *tune = mips_parse_cpu (riscv_tune_string); -+ if (tune) -+ riscv_tune = tune->cpu; -+ } -+ -+ flag_pcc_struct_return = 0; -+ -+ /* Decide which rtx_costs structure to use. */ -+ if (optimize_size) -+ mips_cost = &mips_rtx_cost_optimize_size; -+ else -+ mips_cost = &mips_rtx_cost_data[riscv_tune]; -+ -+ /* If the user hasn't specified a branch cost, use the processor's -+ default. */ -+ if (riscv_branch_cost == 0) -+ riscv_branch_cost = mips_cost->branch_cost; -+ -+ if (!TARGET_USE_GP) -+ g_switch_value = 0; -+ -+ /* Prefer a call to memcpy over inline code when optimizing for size, -+ though see MOVE_RATIO in mips.h. */ -+ if (optimize_size && (target_flags_explicit & MASK_MEMCPY) == 0) -+ target_flags |= MASK_MEMCPY; -+ -+ /* Use atomic instructions, if user did not specify a preference */ -+ if ((target_flags_explicit & MASK_ATOMIC) == 0) -+ target_flags |= MASK_ATOMIC; -+ -+ /* Use multiplier/division instructions, if user did not specify a preference */ -+ if ((target_flags_explicit & MASK_RVM) == 0) -+ target_flags |= MASK_RVM; -+ -+ /* Set up riscv_hard_regno_mode_ok. */ -+ for (mode = 0; mode < MAX_MACHINE_MODE; mode++) -+ for (regno = 0; regno < FIRST_PSEUDO_REGISTER; regno++) -+ riscv_hard_regno_mode_ok[mode][regno] -+ = riscv_hard_regno_mode_ok_p (regno, (enum machine_mode) mode); -+ -+ /* Function to allocate machine-dependent function status. */ -+ init_machine_status = &mips_init_machine_status; -+ -+ mips_init_relocs (); -+} -+ -+/* Implement TARGET_OPTION_OPTIMIZATION_TABLE. */ -+static const struct default_options mips_option_optimization_table[] = -+ { -+ { OPT_LEVELS_1_PLUS, OPT_fsection_anchors, NULL, 1 }, -+ { OPT_LEVELS_1_PLUS, OPT_fomit_frame_pointer, NULL, 1 }, -+ { OPT_LEVELS_NONE, 0, NULL, 0 } -+ }; -+ -+/* Implement TARGET_CONDITIONAL_REGISTER_USAGE. */ -+ -+static void -+mips_conditional_register_usage (void) -+{ -+ int regno; -+ -+ if (!TARGET_HARD_FLOAT) -+ { -+ for (regno = FP_REG_FIRST; regno <= FP_REG_LAST; regno++) -+ fixed_regs[regno] = call_used_regs[regno] = 1; -+ } -+} -+ -+/* Implement TARGET_TRAMPOLINE_INIT. */ -+ -+static void -+mips_trampoline_init (rtx m_tramp, tree fndecl, rtx chain_value) -+{ -+ rtx addr, end_addr, mem; -+ rtx trampoline[4]; -+ unsigned int i; -+ HOST_WIDE_INT static_chain_offset, target_function_offset; -+ -+ /* Work out the offsets of the pointers from the start of the -+ trampoline code. */ -+ gcc_assert (ARRAY_SIZE (trampoline) * 4 == TRAMPOLINE_CODE_SIZE); -+ static_chain_offset = TRAMPOLINE_CODE_SIZE; -+ target_function_offset = static_chain_offset + GET_MODE_SIZE (ptr_mode); -+ -+ /* Get pointers to the beginning and end of the code block. */ -+ addr = force_reg (Pmode, XEXP (m_tramp, 0)); -+ end_addr = mips_force_binary (Pmode, PLUS, addr, GEN_INT (TRAMPOLINE_CODE_SIZE)); -+ -+#define OP(X) gen_int_mode (X, SImode) -+#define MATCH_LREG ((Pmode) == DImode ? MATCH_LD : MATCH_LW) -+ -+ /* auipc v0, 0 -+ l[wd] v1, target_function_offset(v0) -+ l[wd] $static_chain, static_chain_offset(v0) -+ jr v1 -+ */ -+ -+ trampoline[0] = OP (RISCV_UTYPE (AUIPC, STATIC_CHAIN_REGNUM, 0)); -+ trampoline[1] = OP (RISCV_ITYPE (LREG, RISCV_PROLOGUE_TEMP_REGNUM, -+ STATIC_CHAIN_REGNUM, target_function_offset)); -+ trampoline[2] = OP (RISCV_ITYPE (LREG, STATIC_CHAIN_REGNUM, -+ STATIC_CHAIN_REGNUM, static_chain_offset)); -+ trampoline[3] = OP (RISCV_ITYPE (JALR, 0, RISCV_PROLOGUE_TEMP_REGNUM, 0)); -+ -+#undef MATCH_LREG -+#undef OP -+ -+ /* Copy the trampoline code. Leave any padding uninitialized. */ -+ for (i = 0; i < ARRAY_SIZE (trampoline); i++) -+ { -+ mem = adjust_address (m_tramp, SImode, i * GET_MODE_SIZE (SImode)); -+ mips_emit_move (mem, trampoline[i]); -+ } -+ -+ /* Set up the static chain pointer field. */ -+ mem = adjust_address (m_tramp, ptr_mode, static_chain_offset); -+ mips_emit_move (mem, chain_value); -+ -+ /* Set up the target function field. */ -+ mem = adjust_address (m_tramp, ptr_mode, target_function_offset); -+ mips_emit_move (mem, XEXP (DECL_RTL (fndecl), 0)); -+ -+ /* Flush the code part of the trampoline. */ -+ emit_insn (gen_add3_insn (end_addr, addr, GEN_INT (TRAMPOLINE_SIZE))); -+ emit_insn (gen_clear_cache (addr, end_addr)); -+} -+ -+/* Initialize the GCC target structure. */ -+#undef TARGET_ASM_ALIGNED_HI_OP -+#define TARGET_ASM_ALIGNED_HI_OP "\t.half\t" -+#undef TARGET_ASM_ALIGNED_SI_OP -+#define TARGET_ASM_ALIGNED_SI_OP "\t.word\t" -+#undef TARGET_ASM_ALIGNED_DI_OP -+#define TARGET_ASM_ALIGNED_DI_OP "\t.dword\t" -+ -+#undef TARGET_OPTION_OVERRIDE -+#define TARGET_OPTION_OVERRIDE mips_option_override -+#undef TARGET_OPTION_OPTIMIZATION_TABLE -+#define TARGET_OPTION_OPTIMIZATION_TABLE mips_option_optimization_table -+ -+#undef TARGET_LEGITIMIZE_ADDRESS -+#define TARGET_LEGITIMIZE_ADDRESS mips_legitimize_address -+ -+#undef TARGET_SCHED_ADJUST_COST -+#define TARGET_SCHED_ADJUST_COST mips_adjust_cost -+#undef TARGET_SCHED_ISSUE_RATE -+#define TARGET_SCHED_ISSUE_RATE mips_issue_rate -+ -+#undef TARGET_DEFAULT_TARGET_FLAGS -+#define TARGET_DEFAULT_TARGET_FLAGS \ -+ (TARGET_DEFAULT \ -+ | TARGET_CPU_DEFAULT \ -+ | (TARGET_64BIT_DEFAULT ? 0 : MASK_32BIT)) -+#undef TARGET_HANDLE_OPTION -+#define TARGET_HANDLE_OPTION mips_handle_option -+ -+#undef TARGET_FUNCTION_OK_FOR_SIBCALL -+#define TARGET_FUNCTION_OK_FOR_SIBCALL hook_bool_tree_tree_true -+ -+#undef TARGET_REGISTER_MOVE_COST -+#define TARGET_REGISTER_MOVE_COST mips_register_move_cost -+#undef TARGET_MEMORY_MOVE_COST -+#define TARGET_MEMORY_MOVE_COST mips_memory_move_cost -+#undef TARGET_RTX_COSTS -+#define TARGET_RTX_COSTS mips_rtx_costs -+#undef TARGET_ADDRESS_COST -+#define TARGET_ADDRESS_COST riscv_address_cost -+ -+#undef TARGET_MACHINE_DEPENDENT_REORG -+#define TARGET_MACHINE_DEPENDENT_REORG mips_reorg -+ -+#undef TARGET_PREFERRED_RELOAD_CLASS -+#define TARGET_PREFERRED_RELOAD_CLASS mips_preferred_reload_class -+ -+#undef TARGET_ASM_FILE_START_FILE_DIRECTIVE -+#define TARGET_ASM_FILE_START_FILE_DIRECTIVE true -+ -+#undef TARGET_EXPAND_BUILTIN_VA_START -+#define TARGET_EXPAND_BUILTIN_VA_START mips_va_start -+ -+#undef TARGET_PROMOTE_FUNCTION_MODE -+#define TARGET_PROMOTE_FUNCTION_MODE default_promote_function_mode_always_promote -+ -+#undef TARGET_RETURN_IN_MEMORY -+#define TARGET_RETURN_IN_MEMORY mips_return_in_memory -+ -+#undef TARGET_ASM_OUTPUT_MI_THUNK -+#define TARGET_ASM_OUTPUT_MI_THUNK mips_output_mi_thunk -+#undef TARGET_ASM_CAN_OUTPUT_MI_THUNK -+#define TARGET_ASM_CAN_OUTPUT_MI_THUNK hook_bool_const_tree_hwi_hwi_const_tree_true -+ -+#undef TARGET_PRINT_OPERAND -+#define TARGET_PRINT_OPERAND mips_print_operand -+#undef TARGET_PRINT_OPERAND_ADDRESS -+#define TARGET_PRINT_OPERAND_ADDRESS mips_print_operand_address -+ -+#undef TARGET_SETUP_INCOMING_VARARGS -+#define TARGET_SETUP_INCOMING_VARARGS mips_setup_incoming_varargs -+#undef TARGET_STRICT_ARGUMENT_NAMING -+#define TARGET_STRICT_ARGUMENT_NAMING hook_bool_CUMULATIVE_ARGS_true -+#undef TARGET_MUST_PASS_IN_STACK -+#define TARGET_MUST_PASS_IN_STACK must_pass_in_stack_var_size -+#undef TARGET_PASS_BY_REFERENCE -+#define TARGET_PASS_BY_REFERENCE riscv_pass_by_reference -+#undef TARGET_ARG_PARTIAL_BYTES -+#define TARGET_ARG_PARTIAL_BYTES mips_arg_partial_bytes -+#undef TARGET_FUNCTION_ARG -+#define TARGET_FUNCTION_ARG mips_function_arg -+#undef TARGET_FUNCTION_ARG_ADVANCE -+#define TARGET_FUNCTION_ARG_ADVANCE mips_function_arg_advance -+#undef TARGET_FUNCTION_ARG_BOUNDARY -+#define TARGET_FUNCTION_ARG_BOUNDARY mips_function_arg_boundary -+ -+#undef TARGET_MODE_REP_EXTENDED -+#define TARGET_MODE_REP_EXTENDED mips_mode_rep_extended -+ -+#undef TARGET_SCALAR_MODE_SUPPORTED_P -+#define TARGET_SCALAR_MODE_SUPPORTED_P mips_scalar_mode_supported_p -+ -+#undef TARGET_INIT_BUILTINS -+#define TARGET_INIT_BUILTINS mips_init_builtins -+#undef TARGET_BUILTIN_DECL -+#define TARGET_BUILTIN_DECL mips_builtin_decl -+#undef TARGET_EXPAND_BUILTIN -+#define TARGET_EXPAND_BUILTIN riscv_expand_builtin -+ -+#undef TARGET_HAVE_TLS -+#define TARGET_HAVE_TLS HAVE_AS_TLS -+ -+#undef TARGET_CANNOT_FORCE_CONST_MEM -+#define TARGET_CANNOT_FORCE_CONST_MEM mips_cannot_force_const_mem -+ -+#undef TARGET_ATTRIBUTE_TABLE -+#define TARGET_ATTRIBUTE_TABLE mips_attribute_table -+/* All our function attributes are related to how out-of-line copies should -+ be compiled or called. They don't in themselves prevent inlining. */ -+#undef TARGET_FUNCTION_ATTRIBUTE_INLINABLE_P -+#define TARGET_FUNCTION_ATTRIBUTE_INLINABLE_P hook_bool_const_tree_true -+ -+#undef TARGET_USE_BLOCKS_FOR_CONSTANT_P -+#define TARGET_USE_BLOCKS_FOR_CONSTANT_P hook_bool_mode_const_rtx_true -+ -+#undef TARGET_COMP_TYPE_ATTRIBUTES -+#define TARGET_COMP_TYPE_ATTRIBUTES mips_comp_type_attributes -+ -+#ifdef HAVE_AS_DTPRELWORD -+#undef TARGET_ASM_OUTPUT_DWARF_DTPREL -+#define TARGET_ASM_OUTPUT_DWARF_DTPREL mips_output_dwarf_dtprel -+#endif -+ -+#undef TARGET_IRA_COVER_CLASSES -+#define TARGET_IRA_COVER_CLASSES mips_ira_cover_classes -+ -+#undef TARGET_LEGITIMATE_ADDRESS_P -+#define TARGET_LEGITIMATE_ADDRESS_P mips_legitimate_address_p -+ -+#undef TARGET_CAN_ELIMINATE -+#define TARGET_CAN_ELIMINATE mips_can_eliminate -+ -+#undef TARGET_CONDITIONAL_REGISTER_USAGE -+#define TARGET_CONDITIONAL_REGISTER_USAGE mips_conditional_register_usage -+ -+#undef TARGET_TRAMPOLINE_INIT -+#define TARGET_TRAMPOLINE_INIT mips_trampoline_init -+ -+#undef TARGET_IN_SMALL_DATA_P -+#define TARGET_IN_SMALL_DATA_P riscv_in_small_data_p -+ -+#undef TARGET_ASM_SELECT_RTX_SECTION -+#define TARGET_ASM_SELECT_RTX_SECTION riscv_elf_select_rtx_section -+ -+#undef TARGET_MIN_ANCHOR_OFFSET -+#define TARGET_MIN_ANCHOR_OFFSET (-RISCV_IMM_REACH/2) -+ -+#undef TARGET_MAX_ANCHOR_OFFSET -+#define TARGET_MAX_ANCHOR_OFFSET (RISCV_IMM_REACH/2-1) -+ -+struct gcc_target targetm = TARGET_INITIALIZER; -+ -+#include "gt-riscv.h" -diff --git a/gcc-4.6.1/gcc/config/riscv/riscv.h b/gcc-4.6.1/gcc/config/riscv/riscv.h -new file mode 100644 -index 0000000..ce3afe3 ---- /dev/null -+++ gcc-4.6.1/gcc/config/riscv/riscv.h -@@ -0,0 +1,1189 @@ -+/* Definition of RISC-V target for GNU compiler. -+ Copyright (C) 2011-2014 Free Software Foundation, Inc. -+ Contributed by Andrew Waterman (waterman@cs.berkeley.edu) at UC Berkeley. -+ Based on MIPS target for GNU compiler. -+ -+This file is part of GCC. -+ -+GCC is free software; you can redistribute it and/or modify -+it under the terms of the GNU General Public License as published by -+the Free Software Foundation; either version 3, or (at your option) -+any later version. -+ -+GCC is distributed in the hope that it will be useful, -+but WITHOUT ANY WARRANTY; without even the implied warranty of -+MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -+GNU General Public License for more details. -+ -+You should have received a copy of the GNU General Public License -+along with GCC; see the file COPYING3. If not see -+. */ -+ -+/* Information about one recognized processor. Defined here for the -+ benefit of TARGET_CPU_CPP_BUILTINS. */ -+struct riscv_cpu_info { -+ /* The 'canonical' name of the processor as far as GCC is concerned. -+ It's typically a manufacturer's prefix followed by a numerical -+ designation. It should be lowercase. */ -+ const char *name; -+ -+ /* The internal processor number that most closely matches this -+ entry. Several processors can have the same value, if there's no -+ difference between them from GCC's point of view. */ -+ enum processor cpu; -+ -+ /* A mask of PTF_* values. */ -+ unsigned int tune_flags; -+}; -+ -+/* True if a global pointer can be used to access small data. */ -+#define TARGET_USE_GP (!flag_pic) -+ -+/* TARGET_HARD_FLOAT and TARGET_SOFT_FLOAT reflect whether the FPU is -+ directly accessible, while the command-line options select -+ TARGET_HARD_FLOAT_ABI and TARGET_SOFT_FLOAT_ABI to reflect the ABI -+ in use. */ -+#define TARGET_HARD_FLOAT TARGET_HARD_FLOAT_ABI -+#define TARGET_SOFT_FLOAT TARGET_SOFT_FLOAT_ABI -+ -+/* Target CPU builtins. */ -+#define TARGET_CPU_CPP_BUILTINS() \ -+ do \ -+ { \ -+ builtin_assert ("machine=riscv"); \ -+ \ -+ builtin_assert ("cpu=riscv"); \ -+ builtin_define ("__riscv__"); \ -+ builtin_define ("__riscv"); \ -+ builtin_define ("_riscv"); \ -+ \ -+ if (TARGET_64BIT) \ -+ { \ -+ builtin_define ("__riscv64"); \ -+ builtin_define ("_RISCV_SIM=_ABI64"); \ -+ } \ -+ else \ -+ builtin_define ("_RISCV_SIM=_ABI32"); \ -+ \ -+ builtin_define ("_ABI32=1"); \ -+ builtin_define ("_ABI64=3"); \ -+ \ -+ \ -+ builtin_define_with_int_value ("_RISCV_SZINT", INT_TYPE_SIZE); \ -+ builtin_define_with_int_value ("_RISCV_SZLONG", LONG_TYPE_SIZE); \ -+ builtin_define_with_int_value ("_RISCV_SZPTR", POINTER_SIZE); \ -+ builtin_define_with_int_value ("_RISCV_FPSET", 32); \ -+ \ -+ if (TARGET_ATOMIC) { \ -+ builtin_define ("__riscv_atomic"); \ -+ } \ -+ \ -+ /* These defines reflect the ABI in use, not whether the \ -+ FPU is directly accessible. */ \ -+ if (TARGET_HARD_FLOAT_ABI) { \ -+ builtin_define ("__riscv_hard_float"); \ -+ if (TARGET_FDIV) { \ -+ builtin_define ("__riscv_fdiv"); \ -+ builtin_define ("__riscv_fsqrt"); \ -+ } \ -+ } else \ -+ builtin_define ("__riscv_soft_float"); \ -+ \ -+ /* The base RISC-V ISA is always little-endian. */ \ -+ builtin_define_std ("RISCVEL"); \ -+ builtin_define ("_RISCVEL"); \ -+ \ -+ /* Macros dependent on the C dialect. */ \ -+ if (preprocessing_asm_p ()) \ -+ { \ -+ builtin_define_std ("LANGUAGE_ASSEMBLY"); \ -+ builtin_define ("_LANGUAGE_ASSEMBLY"); \ -+ } \ -+ else if (c_dialect_cxx ()) \ -+ { \ -+ builtin_define ("_LANGUAGE_C_PLUS_PLUS"); \ -+ builtin_define ("__LANGUAGE_C_PLUS_PLUS"); \ -+ builtin_define ("__LANGUAGE_C_PLUS_PLUS__"); \ -+ } \ -+ else \ -+ { \ -+ builtin_define_std ("LANGUAGE_C"); \ -+ builtin_define ("_LANGUAGE_C"); \ -+ } \ -+ if (c_dialect_objc ()) \ -+ { \ -+ builtin_define ("_LANGUAGE_OBJECTIVE_C"); \ -+ builtin_define ("__LANGUAGE_OBJECTIVE_C"); \ -+ /* Bizarre, but needed at least for Irix. */ \ -+ builtin_define_std ("LANGUAGE_C"); \ -+ builtin_define ("_LANGUAGE_C"); \ -+ } \ -+ } \ -+ while (0) -+ -+/* Default target_flags if no switches are specified */ -+ -+#ifndef TARGET_DEFAULT -+#define TARGET_DEFAULT 0 -+#endif -+ -+#ifndef TARGET_CPU_DEFAULT -+#define TARGET_CPU_DEFAULT 0 -+#endif -+ -+#ifndef RISCV_CPU_STRING_DEFAULT -+#define RISCV_CPU_STRING_DEFAULT "rocket" -+#endif -+ -+#ifndef TARGET_64BIT_DEFAULT -+#define TARGET_64BIT_DEFAULT 1 -+#endif -+ -+#if TARGET_64BIT_DEFAULT -+# define MULTILIB_ARCH_DEFAULT "m64" -+# define OPT_ARCH64 "!m32" -+# define OPT_ARCH32 "m32" -+#else -+# define MULTILIB_ARCH_DEFAULT "m32" -+# define OPT_ARCH64 "m64" -+# define OPT_ARCH32 "!m64" -+#endif -+ -+#ifndef MULTILIB_DEFAULTS -+#define MULTILIB_DEFAULTS \ -+ { MULTILIB_ARCH_DEFAULT } -+#endif -+ -+ -+/* Support for a compile-time default CPU, et cetera. The rules are: -+ --with-arch is ignored if -march is specified. -+ --with-tune is ignored if -mtune is specified. -+ --with-float is ignored if -mhard-float or -msoft-float are specified. */ -+#define OPTION_DEFAULT_SPECS \ -+ {"arch_32", "%{" OPT_ARCH32 ":%{m32}}" }, \ -+ {"arch_64", "%{" OPT_ARCH64 ":%{m64}}" }, \ -+ {"tune", "%{!mtune=*:-mtune=%(VALUE)}" }, \ -+ {"float", "%{!msoft-float:%{!mhard-float:-m%(VALUE)-float}}" }, \ -+ -+#define DRIVER_SELF_SPECS "" -+ -+#ifdef IN_LIBGCC2 -+#undef TARGET_64BIT -+/* Make this compile time constant for libgcc2 */ -+#ifdef __riscv64 -+#define TARGET_64BIT 1 -+#else -+#define TARGET_64BIT 0 -+#endif -+#endif /* IN_LIBGCC2 */ -+ -+/* Tell collect what flags to pass to nm. */ -+#ifndef NM_FLAGS -+#define NM_FLAGS "-Bn" -+#endif -+ -+#undef ASM_SPEC -+#define ASM_SPEC "\ -+%(subtarget_asm_debugging_spec) \ -+%{m32} %{m64} %{!m32:%{!m64: %(asm_abi_default_spec)}} \ -+%{fPIC|fpic|fPIE|fpie:-fpic} \ -+%{march=*} \ -+%(subtarget_asm_spec)" -+ -+/* Extra switches sometimes passed to the linker. */ -+ -+#ifndef LINK_SPEC -+#define LINK_SPEC "\ -+%{!T:-dT riscv.ld} \ -+%{m64:-melf64lriscv} \ -+%{m32:-melf32lriscv} \ -+%{shared}" -+#endif /* LINK_SPEC defined */ -+ -+/* This macro defines names of additional specifications to put in the specs -+ that can be used in various specifications like CC1_SPEC. Its definition -+ is an initializer with a subgrouping for each command option. -+ -+ Each subgrouping contains a string constant, that defines the -+ specification name, and a string constant that used by the GCC driver -+ program. -+ -+ Do not define this macro if it does not need to do anything. */ -+ -+#define EXTRA_SPECS \ -+ { "asm_abi_default_spec", "-" MULTILIB_ARCH_DEFAULT }, \ -+ SUBTARGET_EXTRA_SPECS -+ -+#ifndef SUBTARGET_EXTRA_SPECS -+#define SUBTARGET_EXTRA_SPECS -+#endif -+ -+#ifndef PREFERRED_DEBUGGING_TYPE -+#define PREFERRED_DEBUGGING_TYPE DWARF2_DEBUG -+#endif -+ -+#define DWARF2_ADDR_SIZE UNITS_PER_WORD -+ -+/* By default, turn on GDB extensions. */ -+#define DEFAULT_GDB_EXTENSIONS 1 -+ -+#define LOCAL_LABEL_PREFIX "." -+#define USER_LABEL_PREFIX "" -+ -+/* The mapping from gcc register number to DWARF 2 CFA column number. */ -+#define DWARF_FRAME_REGNUM(REGNO) \ -+ (GP_REG_P (REGNO) || FP_REG_P (REGNO) ? REGNO : INVALID_REGNUM) -+ -+/* The DWARF 2 CFA column which tracks the return address. */ -+#define DWARF_FRAME_RETURN_COLUMN RETURN_ADDR_REGNUM -+ -+/* Don't emit .cfi_sections, as it does not work */ -+#undef HAVE_GAS_CFI_SECTIONS_DIRECTIVE -+#define HAVE_GAS_CFI_SECTIONS_DIRECTIVE 0 -+ -+/* Before the prologue, RA lives in r31. */ -+#define INCOMING_RETURN_ADDR_RTX gen_rtx_REG (VOIDmode, RETURN_ADDR_REGNUM) -+ -+/* Describe how we implement __builtin_eh_return. */ -+#define EH_RETURN_DATA_REGNO(N) \ -+ ((N) < 4 ? (N) + GP_ARG_FIRST : INVALID_REGNUM) -+ -+#define EH_RETURN_STACKADJ_RTX gen_rtx_REG (Pmode, GP_ARG_FIRST + 4) -+ -+/* Offsets recorded in opcodes are a multiple of this alignment factor. -+ The default for this in 64-bit mode is 8, which causes problems with -+ SFmode register saves. */ -+#define DWARF_CIE_DATA_ALIGNMENT -4 -+ -+/* Target machine storage layout */ -+ -+#define BITS_BIG_ENDIAN 0 -+#define BYTES_BIG_ENDIAN 0 -+#define WORDS_BIG_ENDIAN 0 -+ -+#define MAX_BITS_PER_WORD 64 -+ -+/* Width of a word, in units (bytes). */ -+#define UNITS_PER_WORD (TARGET_64BIT ? 8 : 4) -+#ifndef IN_LIBGCC2 -+#define MIN_UNITS_PER_WORD 4 -+#endif -+ -+/* We currently require both or neither of the `F' and `D' extensions. */ -+#define UNITS_PER_FPREG 8 -+ -+/* If FP regs aren't wide enough for a given FP argument, it is passed in -+ integer registers. */ -+#define MIN_FPRS_PER_FMT 1 -+ -+/* The largest size of value that can be held in floating-point -+ registers and moved with a single instruction. */ -+#define UNITS_PER_HWFPVALUE \ -+ (TARGET_SOFT_FLOAT_ABI ? 0 : UNITS_PER_FPREG) -+ -+/* The largest size of value that can be held in floating-point -+ registers. */ -+#define UNITS_PER_FPVALUE \ -+ (TARGET_SOFT_FLOAT_ABI ? 0 \ -+ : LONG_DOUBLE_TYPE_SIZE / BITS_PER_UNIT) -+ -+/* The number of bytes in a double. */ -+#define UNITS_PER_DOUBLE (TYPE_PRECISION (double_type_node) / BITS_PER_UNIT) -+ -+/* Set the sizes of the core types. */ -+#define SHORT_TYPE_SIZE 16 -+#define INT_TYPE_SIZE 32 -+#define LONG_TYPE_SIZE (TARGET_64BIT ? 64 : 32) -+#define LONG_LONG_TYPE_SIZE 64 -+ -+#define FLOAT_TYPE_SIZE 32 -+#define DOUBLE_TYPE_SIZE 64 -+/* XXX The ABI says long doubles are IEEE-754-2008 float128s. */ -+#define LONG_DOUBLE_TYPE_SIZE 64 -+ -+#ifdef IN_LIBGCC2 -+# define LIBGCC2_LONG_DOUBLE_TYPE_SIZE LONG_DOUBLE_TYPE_SIZE -+#endif -+ -+/* Allocation boundary (in *bits*) for storing arguments in argument list. */ -+#define PARM_BOUNDARY BITS_PER_WORD -+ -+/* Allocation boundary (in *bits*) for the code of a function. */ -+#define FUNCTION_BOUNDARY 32 -+ -+/* There is no point aligning anything to a rounder boundary than this. */ -+#define BIGGEST_ALIGNMENT 128 -+ -+/* All accesses must be aligned. */ -+#define STRICT_ALIGNMENT 1 -+ -+/* Define this if you wish to imitate the way many other C compilers -+ handle alignment of bitfields and the structures that contain -+ them. -+ -+ The behavior is that the type written for a bit-field (`int', -+ `short', or other integer type) imposes an alignment for the -+ entire structure, as if the structure really did contain an -+ ordinary field of that type. In addition, the bit-field is placed -+ within the structure so that it would fit within such a field, -+ not crossing a boundary for it. -+ -+ Thus, on most machines, a bit-field whose type is written as `int' -+ would not cross a four-byte boundary, and would force four-byte -+ alignment for the whole structure. (The alignment used may not -+ be four bytes; it is controlled by the other alignment -+ parameters.) -+ -+ If the macro is defined, its definition should be a C expression; -+ a nonzero value for the expression enables this behavior. */ -+ -+#define PCC_BITFIELD_TYPE_MATTERS 1 -+ -+/* If defined, a C expression to compute the alignment given to a -+ constant that is being placed in memory. CONSTANT is the constant -+ and ALIGN is the alignment that the object would ordinarily have. -+ The value of this macro is used instead of that alignment to align -+ the object. -+ -+ If this macro is not defined, then ALIGN is used. -+ -+ The typical use of this macro is to increase alignment for string -+ constants to be word aligned so that `strcpy' calls that copy -+ constants can be done inline. */ -+ -+#define CONSTANT_ALIGNMENT(EXP, ALIGN) \ -+ ((TREE_CODE (EXP) == STRING_CST || TREE_CODE (EXP) == CONSTRUCTOR) \ -+ && (ALIGN) < BITS_PER_WORD ? BITS_PER_WORD : (ALIGN)) -+ -+/* If defined, a C expression to compute the alignment for a static -+ variable. TYPE is the data type, and ALIGN is the alignment that -+ the object would ordinarily have. The value of this macro is used -+ instead of that alignment to align the object. -+ -+ If this macro is not defined, then ALIGN is used. -+ -+ One use of this macro is to increase alignment of medium-size -+ data to make it all fit in fewer cache lines. Another is to -+ cause character arrays to be word-aligned so that `strcpy' calls -+ that copy constants to character arrays can be done inline. */ -+ -+#undef DATA_ALIGNMENT -+#define DATA_ALIGNMENT(TYPE, ALIGN) \ -+ ((((ALIGN) < BITS_PER_WORD) \ -+ && (TREE_CODE (TYPE) == ARRAY_TYPE \ -+ || TREE_CODE (TYPE) == UNION_TYPE \ -+ || TREE_CODE (TYPE) == RECORD_TYPE)) ? BITS_PER_WORD : (ALIGN)) -+ -+/* We need this for the same reason as DATA_ALIGNMENT, namely to cause -+ character arrays to be word-aligned so that `strcpy' calls that copy -+ constants to character arrays can be done inline, and 'strcmp' can be -+ optimised to use word loads. */ -+#define LOCAL_ALIGNMENT(TYPE, ALIGN) \ -+ DATA_ALIGNMENT (TYPE, ALIGN) -+ -+/* Define if operations between registers always perform the operation -+ on the full register even if a narrower mode is specified. */ -+#define WORD_REGISTER_OPERATIONS -+ -+/* When in 64-bit mode, move insns will sign extend SImode and CCmode -+ moves. All other references are zero extended. */ -+#define LOAD_EXTEND_OP(MODE) \ -+ (TARGET_64BIT && ((MODE) == SImode || (MODE) == CCmode) \ -+ ? SIGN_EXTEND : ZERO_EXTEND) -+ -+/* Define this macro if it is advisable to hold scalars in registers -+ in a wider mode than that declared by the program. In such cases, -+ the value is constrained to be within the bounds of the declared -+ type, but kept valid in the wider mode. The signedness of the -+ extension may differ from that of the type. */ -+ -+#define PROMOTE_MODE(MODE, UNSIGNEDP, TYPE) \ -+ if (GET_MODE_CLASS (MODE) == MODE_INT \ -+ && GET_MODE_SIZE (MODE) < 4) \ -+ { \ -+ (MODE) = Pmode; \ -+ } -+ -+/* Pmode is always the same as ptr_mode, but not always the same as word_mode. -+ Extensions of pointers to word_mode must be signed. */ -+#define POINTERS_EXTEND_UNSIGNED false -+ -+/* RV32 double-precision FP <-> integer moves go through memory */ -+#define SECONDARY_MEMORY_NEEDED(CLASS1,CLASS2,MODE) \ -+ (!TARGET_64BIT && GET_MODE_SIZE (MODE) == 8 && \ -+ (((CLASS1) == FP_REGS && (CLASS2) != FP_REGS) \ -+ || ((CLASS2) == FP_REGS && (CLASS1) != FP_REGS))) -+ -+/* Define if loading short immediate values into registers sign extends. */ -+#define SHORT_IMMEDIATES_SIGN_EXTEND -+ -+/* Standard register usage. */ -+ -+/* Number of hardware registers. We have: -+ -+ - 32 integer registers -+ - 32 floating point registers -+ - 32 vector integer registers -+ - 32 vector floating point registers -+ - 2 fake registers: -+ - ARG_POINTER_REGNUM -+ - FRAME_POINTER_REGNUM */ -+ -+#define FIRST_PSEUDO_REGISTER 66 -+ -+/* x0, sp, tp, and gp are fixed. */ -+ -+#define FIXED_REGISTERS \ -+{ /* General registers. */ \ -+ 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, \ -+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, \ -+ /* Floating-point registers. */ \ -+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ -+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ -+ /* Others. */ \ -+ 1, 1 \ -+} -+ -+ -+/* Function calls clobber x16-30 (v0-1, a0-7, t0-4) and f16-31 -+ (fv0-1, fa0-7, ft0-5). The call RTLs themselves clobber x1 (ra). */ -+ -+#define CALL_USED_REGISTERS \ -+{ /* General registers. */ \ -+ 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, \ -+ 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \ -+ /* Floating-point registers. */ \ -+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ -+ 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \ -+ /* Others. */ \ -+ 1, 1 \ -+} -+ -+#define CALL_REALLY_USED_REGISTERS \ -+{ /* General registers. */ \ -+ 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, \ -+ 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \ -+ /* Floating-point registers. */ \ -+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ -+ 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \ -+ /* Others. */ \ -+ 1, 1 \ -+} -+ -+/* Internal macros to classify an ISA register's type. */ -+ -+#define GP_REG_FIRST 0 -+#define GP_REG_LAST 31 -+#define GP_REG_NUM (GP_REG_LAST - GP_REG_FIRST + 1) -+ -+#define FP_REG_FIRST 32 -+#define FP_REG_LAST 63 -+#define FP_REG_NUM (FP_REG_LAST - FP_REG_FIRST + 1) -+ -+#define CALLEE_SAVED_GP_REG_FIRST (GP_REG_FIRST + 2) -+#define CALLEE_SAVED_GP_REG_LAST (CALLEE_SAVED_GP_REG_FIRST + 12 - 1) -+ -+#define CALLEE_SAVED_FP_REG_FIRST (FP_REG_FIRST + 0) -+#define CALLEE_SAVED_FP_REG_LAST (CALLEE_SAVED_FP_REG_FIRST + 16 - 1) -+ -+/* The DWARF 2 CFA column which tracks the return address from a -+ signal handler context. This means that to maintain backwards -+ compatibility, no hard register can be assigned this column if it -+ would need to be handled by the DWARF unwinder. */ -+#define DWARF_ALT_FRAME_RETURN_COLUMN 66 -+ -+#define GP_REG_P(REGNO) \ -+ ((unsigned int) ((int) (REGNO) - GP_REG_FIRST) < GP_REG_NUM) -+#define FP_REG_P(REGNO) \ -+ ((unsigned int) ((int) (REGNO) - FP_REG_FIRST) < FP_REG_NUM) -+ -+#define FP_REG_RTX_P(X) (REG_P (X) && FP_REG_P (REGNO (X))) -+ -+/* Return coprocessor number from register number. */ -+ -+#define COPNUM_AS_CHAR_FROM_REGNUM(REGNO) \ -+ (COP0_REG_P (REGNO) ? '0' : COP2_REG_P (REGNO) ? '2' \ -+ : COP3_REG_P (REGNO) ? '3' : '?') -+ -+ -+#define HARD_REGNO_NREGS(REGNO, MODE) riscv_hard_regno_nregs (REGNO, MODE) -+ -+#define HARD_REGNO_MODE_OK(REGNO, MODE) \ -+ riscv_hard_regno_mode_ok[ (int)(MODE) ][ (REGNO) ] -+ -+#define MODES_TIEABLE_P(MODE1, MODE2) \ -+ ((MODE1) == (MODE2) || (GET_MODE_CLASS (MODE1) == MODE_INT \ -+ && GET_MODE_CLASS (MODE2) == MODE_INT)) -+ -+/* Use s0 as the frame pointer if it is so requested. */ -+#define HARD_FRAME_POINTER_REGNUM 2 -+#define STACK_POINTER_REGNUM 14 -+#define THREAD_POINTER_REGNUM 15 -+#define GP_REGNUM 31 -+ -+/* These two registers don't really exist: they get eliminated to either -+ the stack or hard frame pointer. */ -+#define ARG_POINTER_REGNUM 64 -+#define FRAME_POINTER_REGNUM 65 -+ -+#define HARD_FRAME_POINTER_IS_FRAME_POINTER 0 -+#define HARD_FRAME_POINTER_IS_ARG_POINTER 0 -+ -+/* Register in which static-chain is passed to a function. */ -+#define STATIC_CHAIN_REGNUM GP_RETURN -+ -+/* Registers used as temporaries in prologue/epilogue code. -+ -+ The prologue registers mustn't conflict with any -+ incoming arguments, the static chain pointer, or the frame pointer. -+ The epilogue temporary mustn't conflict with the return registers, -+ the frame pointer, the EH stack adjustment, or the EH data registers. */ -+ -+#define RISCV_PROLOGUE_TEMP_REGNUM GP_TEMP_FIRST -+#define RISCV_EPILOGUE_TEMP_REGNUM GP_TEMP_FIRST -+ -+#define RISCV_PROLOGUE_TEMP(MODE) gen_rtx_REG (MODE, RISCV_PROLOGUE_TEMP_REGNUM) -+#define RISCV_EPILOGUE_TEMP(MODE) gen_rtx_REG (MODE, RISCV_EPILOGUE_TEMP_REGNUM) -+ -+#define FUNCTION_PROFILER(STREAM, LABELNO) \ -+{ \ -+ sorry ("profiler support for RISC-V"); \ -+} -+ -+/* Define this macro if it is as good or better to call a constant -+ function address than to call an address kept in a register. */ -+#define NO_FUNCTION_CSE 1 -+ -+/* Define the classes of registers for register constraints in the -+ machine description. Also define ranges of constants. -+ -+ One of the classes must always be named ALL_REGS and include all hard regs. -+ If there is more than one class, another class must be named NO_REGS -+ and contain no registers. -+ -+ The name GENERAL_REGS must be the name of a class (or an alias for -+ another name such as ALL_REGS). This is the class of registers -+ that is allowed by "g" or "r" in a register constraint. -+ Also, registers outside this class are allocated only when -+ instructions express preferences for them. -+ -+ The classes must be numbered in nondecreasing order; that is, -+ a larger-numbered class must never be contained completely -+ in a smaller-numbered class. -+ -+ For any two classes, it is very desirable that there be another -+ class that represents their union. */ -+ -+enum reg_class -+{ -+ NO_REGS, /* no registers in set */ -+ T_REGS, /* registers used by indirect sibcalls */ -+ GR_REGS, /* integer registers */ -+ FP_REGS, /* floating point registers */ -+ FRAME_REGS, /* $arg and $frame */ -+ ALL_REGS, /* all registers */ -+ LIM_REG_CLASSES /* max value + 1 */ -+}; -+ -+#define N_REG_CLASSES (int) LIM_REG_CLASSES -+ -+#define GENERAL_REGS GR_REGS -+ -+/* An initializer containing the names of the register classes as C -+ string constants. These names are used in writing some of the -+ debugging dumps. */ -+ -+#define REG_CLASS_NAMES \ -+{ \ -+ "NO_REGS", \ -+ "T_REGS", \ -+ "GR_REGS", \ -+ "FP_REGS", \ -+ "FRAME_REGS", \ -+ "ALL_REGS" \ -+} -+ -+/* An initializer containing the contents of the register classes, -+ as integers which are bit masks. The Nth integer specifies the -+ contents of class N. The way the integer MASK is interpreted is -+ that register R is in the class if `MASK & (1 << R)' is 1. -+ -+ When the machine has more than 32 registers, an integer does not -+ suffice. Then the integers are replaced by sub-initializers, -+ braced groupings containing several integers. Each -+ sub-initializer must be suitable as an initializer for the type -+ `HARD_REG_SET' which is defined in `hard-reg-set.h'. */ -+ -+#define REG_CLASS_CONTENTS \ -+{ \ -+ { 0x00000000, 0x00000000, 0x00000000 }, /* NO_REGS */ \ -+ { 0x7c000000, 0x00000000, 0x00000000 }, /* T_REGS */ \ -+ { 0xffffffff, 0x00000000, 0x00000000 }, /* GR_REGS */ \ -+ { 0x00000000, 0xffffffff, 0x00000000 }, /* FP_REGS */ \ -+ { 0x00000000, 0x00000000, 0x00000003 }, /* FRAME_REGS */ \ -+ { 0xffffffff, 0xffffffff, 0x00000003 } /* ALL_REGS */ \ -+} -+ -+/* A C expression whose value is a register class containing hard -+ register REGNO. In general there is more that one such class; -+ choose a class which is "minimal", meaning that no smaller class -+ also contains the register. */ -+ -+#define REGNO_REG_CLASS(REGNO) riscv_regno_to_class[ (REGNO) ] -+ -+/* A macro whose definition is the name of the class to which a -+ valid base register must belong. A base register is one used in -+ an address which is the register value plus a displacement. */ -+ -+#define BASE_REG_CLASS GR_REGS -+ -+/* A macro whose definition is the name of the class to which a -+ valid index register must belong. An index register is one used -+ in an address where its value is either multiplied by a scale -+ factor or added to another register (as well as added to a -+ displacement). */ -+ -+#define INDEX_REG_CLASS NO_REGS -+ -+/* We generally want to put call-clobbered registers ahead of -+ call-saved ones. (IRA expects this.) */ -+ -+#define REG_ALLOC_ORDER \ -+{ \ -+ /* Call-clobbered GPRs. */ \ -+ 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 1, \ -+ /* Call-saved GPRs. */ \ -+ 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, \ -+ /* GPRs that can never be exposed to the register allocator. */ \ -+ 0, 14, 15, \ -+ /* Call-clobbered FPRs. */ \ -+ 48, 49, 50, 51, 52, 53, 54, 55, 56, 57, 58, 59, 60, 61, 62, 63, \ -+ /* Call-saved FPRs. */ \ -+ 32, 33, 34, 35, 36, 37, 38, 39, 40, 41, 42, 43, 44, 45, 46, 47, \ -+ /* None of the remaining classes have defined call-saved \ -+ registers. */ \ -+ 64, 65 \ -+} -+ -+/* True if VALUE is a signed 16-bit number. */ -+ -+#include "opcode-riscv.h" -+#define SMALL_OPERAND(VALUE) \ -+ ((unsigned HOST_WIDE_INT) (VALUE) + RISCV_IMM_REACH/2 < RISCV_IMM_REACH) -+ -+/* True if VALUE can be loaded into a register using LUI. */ -+ -+#define LUI_OPERAND(VALUE) \ -+ (((VALUE) | ((1UL<<31) - RISCV_IMM_REACH)) == ((1UL<<31) - RISCV_IMM_REACH) \ -+ || ((VALUE) | ((1UL<<31) - RISCV_IMM_REACH)) + RISCV_IMM_REACH == 0) -+ -+/* Return a value X with the low 16 bits clear, and such that -+ VALUE - X is a signed 16-bit value. */ -+ -+#define SMALL_INT(X) SMALL_OPERAND (INTVAL (X)) -+#define LUI_INT(X) LUI_OPERAND (INTVAL (X)) -+ -+/* The HI and LO registers can only be reloaded via the general -+ registers. Condition code registers can only be loaded to the -+ general registers, and from the floating point registers. */ -+ -+#define SECONDARY_INPUT_RELOAD_CLASS(CLASS, MODE, X) \ -+ riscv_secondary_reload_class (CLASS, MODE, X, true) -+#define SECONDARY_OUTPUT_RELOAD_CLASS(CLASS, MODE, X) \ -+ riscv_secondary_reload_class (CLASS, MODE, X, false) -+ -+/* Return the maximum number of consecutive registers -+ needed to represent mode MODE in a register of class CLASS. */ -+ -+#define CLASS_MAX_NREGS(CLASS, MODE) riscv_class_max_nregs (CLASS, MODE) -+ -+/* It is undefined to interpret an FP register in a different format than -+ that which it was created to be. */ -+ -+#define CANNOT_CHANGE_MODE_CLASS(FROM, TO, CLASS) \ -+ reg_classes_intersect_p (FP_REGS, CLASS) -+ -+/* Stack layout; function entry, exit and calling. */ -+ -+#define STACK_GROWS_DOWNWARD -+ -+#define FRAME_GROWS_DOWNWARD 1 -+ -+#define STARTING_FRAME_OFFSET 0 -+ -+#define RETURN_ADDR_RTX riscv_return_addr -+ -+#define ELIMINABLE_REGS \ -+{{ ARG_POINTER_REGNUM, STACK_POINTER_REGNUM}, \ -+ { ARG_POINTER_REGNUM, HARD_FRAME_POINTER_REGNUM}, \ -+ { FRAME_POINTER_REGNUM, STACK_POINTER_REGNUM}, \ -+ { FRAME_POINTER_REGNUM, HARD_FRAME_POINTER_REGNUM}} \ -+ -+#define INITIAL_ELIMINATION_OFFSET(FROM, TO, OFFSET) \ -+ (OFFSET) = riscv_initial_elimination_offset (FROM, TO) -+ -+/* Allocate stack space for arguments at the beginning of each function. */ -+#define ACCUMULATE_OUTGOING_ARGS 1 -+ -+/* The argument pointer always points to the first argument. */ -+#define FIRST_PARM_OFFSET(FNDECL) 0 -+ -+#define REG_PARM_STACK_SPACE(FNDECL) 0 -+ -+/* Define this if it is the responsibility of the caller to -+ allocate the area reserved for arguments passed in registers. -+ If `ACCUMULATE_OUTGOING_ARGS' is also defined, the only effect -+ of this macro is to determine whether the space is included in -+ `crtl->outgoing_args_size'. */ -+#define OUTGOING_REG_PARM_STACK_SPACE(FNTYPE) 1 -+ -+#define STACK_BOUNDARY 128 -+ -+/* Symbolic macros for the registers used to return integer and floating -+ point values. */ -+ -+#define GP_RETURN (GP_REG_FIRST + 16) -+#define FP_RETURN ((TARGET_SOFT_FLOAT) ? GP_RETURN : (FP_REG_FIRST + 16)) -+ -+#define MAX_ARGS_IN_REGISTERS 8 -+ -+/* Symbolic macros for the first/last argument registers. */ -+ -+#define GP_ARG_FIRST (GP_REG_FIRST + 18) -+#define GP_ARG_LAST (GP_ARG_FIRST + MAX_ARGS_IN_REGISTERS - 1) -+#define GP_TEMP_FIRST (GP_ARG_LAST + 1) -+#define FP_ARG_FIRST (FP_REG_FIRST + 18) -+#define FP_ARG_LAST (FP_ARG_FIRST + MAX_ARGS_IN_REGISTERS - 1) -+ -+#define LIBCALL_VALUE(MODE) \ -+ riscv_function_value (NULL_TREE, NULL_TREE, MODE) -+ -+#define FUNCTION_VALUE(VALTYPE, FUNC) \ -+ riscv_function_value (VALTYPE, FUNC, VOIDmode) -+ -+/* Return scalar values in v0 or fv0. */ -+ -+#define FUNCTION_VALUE_REGNO_P(N) ((N) == GP_RETURN || (N) == FP_RETURN) -+ -+/* 1 if N is a possible register number for function argument passing. -+ We have no FP argument registers when soft-float. When FP registers -+ are 32 bits, we can't directly reference the odd numbered ones. */ -+ -+/* Accept arguments in a0-a7 and/or fa0-fa7. */ -+#define FUNCTION_ARG_REGNO_P(N) \ -+ (IN_RANGE((N), GP_ARG_FIRST, GP_ARG_LAST) \ -+ || IN_RANGE((N), FP_ARG_FIRST, FP_ARG_LAST)) -+ -+/* The ABI views the arguments as a structure, of which the first 8 -+ words go in registers and the rest go on the stack. If I < 8, N, the Ith -+ word might go in the Ith integer argument register or the Ith -+ floating-point argument register. */ -+ -+typedef struct { -+ /* Number of integer registers used so far, up to MAX_ARGS_IN_REGISTERS. */ -+ unsigned int num_gprs; -+ -+ /* Number of words passed on the stack. */ -+ unsigned int stack_words; -+} CUMULATIVE_ARGS; -+ -+/* Initialize a variable CUM of type CUMULATIVE_ARGS -+ for a call to a function whose data type is FNTYPE. -+ For a library call, FNTYPE is 0. */ -+ -+#define INIT_CUMULATIVE_ARGS(CUM, FNTYPE, LIBNAME, INDIRECT, N_NAMED_ARGS) \ -+ memset (&(CUM), 0, sizeof (CUM)) -+ -+#define EPILOGUE_USES(REGNO) ((REGNO) == RETURN_ADDR_REGNUM) -+ -+/* ABI requires 16-byte alignment, even on ven on RV32. */ -+#define RISCV_STACK_ALIGN(LOC) (((LOC) + 15) & -16) -+ -+#define NO_PROFILE_COUNTERS 1 -+ -+/* Define this macro if the code for function profiling should come -+ before the function prologue. Normally, the profiling code comes -+ after. */ -+ -+/* #define PROFILE_BEFORE_PROLOGUE */ -+ -+/* EXIT_IGNORE_STACK should be nonzero if, when returning from a function, -+ the stack pointer does not matter. The value is tested only in -+ functions that have frame pointers. -+ No definition is equivalent to always zero. */ -+ -+#define EXIT_IGNORE_STACK 1 -+ -+ -+/* Trampolines are a block of code followed by two pointers. */ -+ -+#define TRAMPOLINE_CODE_SIZE 16 -+#define TRAMPOLINE_SIZE (TRAMPOLINE_CODE_SIZE + POINTER_SIZE * 2) -+#define TRAMPOLINE_ALIGNMENT POINTER_SIZE -+ -+/* Addressing modes, and classification of registers for them. */ -+ -+#define REGNO_OK_FOR_INDEX_P(REGNO) 0 -+#define REGNO_MODE_OK_FOR_BASE_P(REGNO, MODE) \ -+ riscv_regno_mode_ok_for_base_p (REGNO, MODE, 1) -+ -+/* The macros REG_OK_FOR..._P assume that the arg is a REG rtx -+ and check its validity for a certain class. -+ We have two alternate definitions for each of them. -+ The usual definition accepts all pseudo regs; the other rejects them all. -+ The symbol REG_OK_STRICT causes the latter definition to be used. -+ -+ Most source files want to accept pseudo regs in the hope that -+ they will get allocated to the class that the insn wants them to be in. -+ Some source files that are used after register allocation -+ need to be strict. */ -+ -+#ifndef REG_OK_STRICT -+#define REG_MODE_OK_FOR_BASE_P(X, MODE) \ -+ riscv_regno_mode_ok_for_base_p (REGNO (X), MODE, 0) -+#else -+#define REG_MODE_OK_FOR_BASE_P(X, MODE) \ -+ riscv_regno_mode_ok_for_base_p (REGNO (X), MODE, 1) -+#endif -+ -+#define REG_OK_FOR_INDEX_P(X) 0 -+ -+ -+/* Maximum number of registers that can appear in a valid memory address. */ -+ -+#define MAX_REGS_PER_ADDRESS 1 -+ -+#define CONSTANT_ADDRESS_P(X) \ -+ (CONSTANT_P (X) && memory_address_p (SImode, X)) -+ -+#define LEGITIMATE_CONSTANT_P(X) (riscv_const_insns (X) > 0) -+ -+/* This handles the magic '..CURRENT_FUNCTION' symbol, which means -+ 'the start of the function that this code is output in'. */ -+ -+#define ASM_OUTPUT_LABELREF(FILE,NAME) \ -+ if (strcmp (NAME, "..CURRENT_FUNCTION") == 0) \ -+ asm_fprintf ((FILE), "%U%s", \ -+ XSTR (XEXP (DECL_RTL (current_function_decl), 0), 0)); \ -+ else \ -+ asm_fprintf ((FILE), "%U%s", (NAME)) -+ -+/* This flag marks functions that cannot be lazily bound. */ -+#define SYMBOL_FLAG_BIND_NOW (SYMBOL_FLAG_MACH_DEP << 1) -+#define SYMBOL_REF_BIND_NOW_P(RTX) \ -+ ((SYMBOL_REF_FLAGS (RTX) & SYMBOL_FLAG_BIND_NOW) != 0) -+ -+#define JUMP_TABLES_IN_TEXT_SECTION 0 -+#define CASE_VECTOR_MODE SImode -+ -+/* Define this as 1 if `char' should by default be signed; else as 0. */ -+#define DEFAULT_SIGNED_CHAR 0 -+ -+/* Consider using fld/fsd to move 8 bytes at a time for RV32IFD. */ -+#define MOVE_MAX UNITS_PER_WORD -+#define MAX_MOVE_MAX 8 -+ -+#define SLOW_BYTE_ACCESS 0 -+ -+#define SHIFT_COUNT_TRUNCATED 1 -+ -+/* Value is 1 if truncating an integer of INPREC bits to OUTPREC bits -+ is done just by pretending it is already truncated. */ -+#define TRULY_NOOP_TRUNCATION(OUTPREC, INPREC) \ -+ (TARGET_64BIT ? ((INPREC) <= 32 || (OUTPREC) < 32) : 1) -+ -+/* Specify the machine mode that pointers have. -+ After generation of rtl, the compiler makes no further distinction -+ between pointers and any other objects of this machine mode. */ -+ -+#ifndef Pmode -+#define Pmode (TARGET_64BIT ? DImode : SImode) -+#endif -+ -+/* Give call MEMs SImode since it is the "most permissive" mode -+ for both 32-bit and 64-bit targets. */ -+ -+#define FUNCTION_MODE SImode -+ -+/* A C expression for the cost of a branch instruction. A value of -+ 1 is the default; other values are interpreted relative to that. */ -+ -+#define BRANCH_COST(speed_p, predictable_p) riscv_branch_cost -+#define LOGICAL_OP_NON_SHORT_CIRCUIT 0 -+ -+/* Control the assembler format that we output. */ -+ -+/* Output to assembler file text saying following lines -+ may contain character constants, extra white space, comments, etc. */ -+ -+#ifndef ASM_APP_ON -+#define ASM_APP_ON " #APP\n" -+#endif -+ -+/* Output to assembler file text saying following lines -+ no longer contain unusual constructs. */ -+ -+#ifndef ASM_APP_OFF -+#define ASM_APP_OFF " #NO_APP\n" -+#endif -+ -+#define REGISTER_NAMES \ -+{ "zero","ra", "s0", "s1", "s2", "s3", "s4", "s5", \ -+ "s6", "s7", "s8", "s9", "s10", "s11", "sp", "tp", \ -+ "v0", "v1", "a0", "a1", "a2", "a3", "a4", "a5", \ -+ "a6", "a7", "t0", "t1", "t2", "t3", "t4", "gp", \ -+ "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7", \ -+ "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15", \ -+ "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23", \ -+ "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31", \ -+ "arg", "frame", } -+ -+#define ADDITIONAL_REGISTER_NAMES \ -+{ \ -+ { "x0", 0 + GP_REG_FIRST }, \ -+ { "x1", 1 + GP_REG_FIRST }, \ -+ { "x2", 2 + GP_REG_FIRST }, \ -+ { "x3", 3 + GP_REG_FIRST }, \ -+ { "x4", 4 + GP_REG_FIRST }, \ -+ { "x5", 5 + GP_REG_FIRST }, \ -+ { "x6", 6 + GP_REG_FIRST }, \ -+ { "x7", 7 + GP_REG_FIRST }, \ -+ { "x8", 8 + GP_REG_FIRST }, \ -+ { "x9", 9 + GP_REG_FIRST }, \ -+ { "x10", 10 + GP_REG_FIRST }, \ -+ { "x11", 11 + GP_REG_FIRST }, \ -+ { "x12", 12 + GP_REG_FIRST }, \ -+ { "x13", 13 + GP_REG_FIRST }, \ -+ { "x14", 14 + GP_REG_FIRST }, \ -+ { "x15", 15 + GP_REG_FIRST }, \ -+ { "x16", 16 + GP_REG_FIRST }, \ -+ { "x17", 17 + GP_REG_FIRST }, \ -+ { "x18", 18 + GP_REG_FIRST }, \ -+ { "x19", 19 + GP_REG_FIRST }, \ -+ { "x20", 20 + GP_REG_FIRST }, \ -+ { "x21", 21 + GP_REG_FIRST }, \ -+ { "x22", 22 + GP_REG_FIRST }, \ -+ { "x23", 23 + GP_REG_FIRST }, \ -+ { "x24", 24 + GP_REG_FIRST }, \ -+ { "x25", 25 + GP_REG_FIRST }, \ -+ { "x26", 26 + GP_REG_FIRST }, \ -+ { "x27", 27 + GP_REG_FIRST }, \ -+ { "x28", 28 + GP_REG_FIRST }, \ -+ { "x29", 29 + GP_REG_FIRST }, \ -+ { "x30", 30 + GP_REG_FIRST }, \ -+ { "x31", 31 + GP_REG_FIRST }, \ -+ { "fs0", 0 + FP_REG_FIRST }, \ -+ { "fs1", 1 + FP_REG_FIRST }, \ -+ { "fs2", 2 + FP_REG_FIRST }, \ -+ { "fs3", 3 + FP_REG_FIRST }, \ -+ { "fs4", 4 + FP_REG_FIRST }, \ -+ { "fs5", 5 + FP_REG_FIRST }, \ -+ { "fs6", 6 + FP_REG_FIRST }, \ -+ { "fs7", 7 + FP_REG_FIRST }, \ -+ { "fs8", 8 + FP_REG_FIRST }, \ -+ { "fs9", 9 + FP_REG_FIRST }, \ -+ { "fs10", 10 + FP_REG_FIRST }, \ -+ { "fs11", 11 + FP_REG_FIRST }, \ -+ { "fs12", 12 + FP_REG_FIRST }, \ -+ { "fs13", 13 + FP_REG_FIRST }, \ -+ { "fs14", 14 + FP_REG_FIRST }, \ -+ { "fs15", 15 + FP_REG_FIRST }, \ -+ { "fv0", 16 + FP_REG_FIRST }, \ -+ { "fv1", 17 + FP_REG_FIRST }, \ -+ { "fa0", 18 + FP_REG_FIRST }, \ -+ { "fa1", 19 + FP_REG_FIRST }, \ -+ { "fa2", 20 + FP_REG_FIRST }, \ -+ { "fa3", 21 + FP_REG_FIRST }, \ -+ { "fa4", 22 + FP_REG_FIRST }, \ -+ { "fa5", 23 + FP_REG_FIRST }, \ -+ { "fa6", 24 + FP_REG_FIRST }, \ -+ { "fa7", 25 + FP_REG_FIRST }, \ -+ { "ft0", 26 + FP_REG_FIRST }, \ -+ { "ft1", 27 + FP_REG_FIRST }, \ -+ { "ft2", 28 + FP_REG_FIRST }, \ -+ { "ft3", 29 + FP_REG_FIRST }, \ -+ { "ft4", 30 + FP_REG_FIRST }, \ -+ { "ft5", 31 + FP_REG_FIRST }, \ -+} -+ -+/* Globalizing directive for a label. */ -+#define GLOBAL_ASM_OP "\t.globl\t" -+ -+/* This is how to store into the string LABEL -+ the symbol_ref name of an internal numbered label where -+ PREFIX is the class of label and NUM is the number within the class. -+ This is suitable for output with `assemble_name'. */ -+ -+#undef ASM_GENERATE_INTERNAL_LABEL -+#define ASM_GENERATE_INTERNAL_LABEL(LABEL,PREFIX,NUM) \ -+ sprintf ((LABEL), "*%s%s%ld", (LOCAL_LABEL_PREFIX), (PREFIX), (long)(NUM)) -+ -+/* Put small global uninitialized data in .sbss, otherwise in .bss. */ -+ -+#undef ASM_OUTPUT_ALIGNED_COMMON -+#define ASM_OUTPUT_ALIGNED_COMMON(FILE, NAME, SIZE, ALIGN) \ -+do { \ -+ targetm.asm_out.globalize_label (FILE, NAME); \ -+ ASM_OUTPUT_ALIGNED_LOCAL (FILE, NAME, SIZE, ALIGN); \ -+} while (0) -+ -+/* Likewise, for local data. */ -+ -+#undef ASM_OUTPUT_ALIGNED_LOCAL -+#define ASM_OUTPUT_ALIGNED_LOCAL(FILE, NAME, SIZE, ALIGN) \ -+do { \ -+ if (riscv_size_ok_for_small_data_p (SIZE)) \ -+ switch_to_section (sbss_section); \ -+ else \ -+ switch_to_section (bss_section); \ -+ ASM_OUTPUT_ALIGN (FILE, exact_log2 ((ALIGN) / BITS_PER_UNIT)); \ -+ ASM_OUTPUT_TYPE_DIRECTIVE (FILE, NAME, "object"); \ -+ ASM_OUTPUT_SIZE_DIRECTIVE (FILE, NAME, SIZE); \ -+ ASM_OUTPUT_LABEL (FILE, NAME); \ -+ ASM_OUTPUT_SKIP (FILE, (SIZE) ? (SIZE) : 1); \ -+} while (0) -+ -+/* This is how to output an element of a case-vector that is absolute. */ -+ -+#define ASM_OUTPUT_ADDR_VEC_ELT(STREAM, VALUE) \ -+ fprintf (STREAM, "\t.word\t%sL%d\n", LOCAL_LABEL_PREFIX, VALUE) -+ -+/* This is how to output an element of a PIC case-vector. */ -+ -+#define ASM_OUTPUT_ADDR_DIFF_ELT(STREAM, BODY, VALUE, REL) \ -+ fprintf (STREAM, "\t.word\t%sL%d-%sL%d\n", \ -+ LOCAL_LABEL_PREFIX, VALUE, LOCAL_LABEL_PREFIX, REL) -+ -+/* This is how to output an assembler line -+ that says to advance the location counter -+ to a multiple of 2**LOG bytes. */ -+ -+#define ASM_OUTPUT_ALIGN(STREAM,LOG) \ -+ fprintf (STREAM, "\t.align\t%d\n", (LOG)) -+ -+/* Define the strings to put out for each section in the object file. */ -+#define TEXT_SECTION_ASM_OP "\t.text" /* instructions */ -+#define DATA_SECTION_ASM_OP "\t.data" /* large data */ -+#define READONLY_DATA_SECTION_ASM_OP "\t.section\t.rodata" -+#define BSS_SECTION_ASM_OP "\t.bss" -+#define SBSS_SECTION_ASM_OP "\t.section\t.sbss,\"aw\",@nobits" -+#define SDATA_SECTION_ASM_OP "\t.section\t.sdata,\"aw\",@progbits" -+ -+#define ASM_OUTPUT_REG_PUSH(STREAM,REGNO) \ -+do \ -+ { \ -+ fprintf (STREAM, "\taddi\t%s,%s,-8\n\t%s\t%s,0(%s)\n", \ -+ reg_names[STACK_POINTER_REGNUM], \ -+ reg_names[STACK_POINTER_REGNUM], \ -+ TARGET_64BIT ? "sd" : "sw", \ -+ reg_names[REGNO], \ -+ reg_names[STACK_POINTER_REGNUM]); \ -+ } \ -+while (0) -+ -+#define ASM_OUTPUT_REG_POP(STREAM,REGNO) \ -+do \ -+ { \ -+ fprintf (STREAM, "\t%s\t%s,0(%s)\n\taddi\t%s,%s,8\n", \ -+ TARGET_64BIT ? "ld" : "lw", \ -+ reg_names[REGNO], \ -+ reg_names[STACK_POINTER_REGNUM], \ -+ reg_names[STACK_POINTER_REGNUM], \ -+ reg_names[STACK_POINTER_REGNUM]); \ -+ } \ -+while (0) -+ -+#define ASM_COMMENT_START "#" -+ -+#undef SIZE_TYPE -+#define SIZE_TYPE (POINTER_SIZE == 64 ? "long unsigned int" : "unsigned int") -+ -+#undef PTRDIFF_TYPE -+#define PTRDIFF_TYPE (POINTER_SIZE == 64 ? "long int" : "int") -+ -+/* The maximum number of bytes that can be copied by one iteration of -+ a movmemsi loop; see riscv_block_move_loop. */ -+#define RISCV_MAX_MOVE_BYTES_PER_LOOP_ITER (UNITS_PER_WORD * 4) -+ -+/* The maximum number of bytes that can be copied by a straight-line -+ implementation of movmemsi; see riscv_block_move_straight. We want -+ to make sure that any loop-based implementation will iterate at -+ least twice. */ -+#define RISCV_MAX_MOVE_BYTES_STRAIGHT (RISCV_MAX_MOVE_BYTES_PER_LOOP_ITER * 2) -+ -+/* The base cost of a memcpy call, for MOVE_RATIO and friends. */ -+ -+#define RISCV_CALL_RATIO 6 -+ -+/* Any loop-based implementation of movmemsi will have at least -+ RISCV_MAX_MOVE_BYTES_STRAIGHT / UNITS_PER_WORD memory-to-memory -+ moves, so allow individual copies of fewer elements. -+ -+ When movmemsi is not available, use a value approximating -+ the length of a memcpy call sequence, so that move_by_pieces -+ will generate inline code if it is shorter than a function call. -+ Since move_by_pieces_ninsns counts memory-to-memory moves, but -+ we'll have to generate a load/store pair for each, halve the -+ value of RISCV_CALL_RATIO to take that into account. */ -+ -+#define MOVE_RATIO(speed) \ -+ (HAVE_movmemsi \ -+ ? RISCV_MAX_MOVE_BYTES_STRAIGHT / MOVE_MAX \ -+ : RISCV_CALL_RATIO / 2) -+ -+/* movmemsi is meant to generate code that is at least as good as -+ move_by_pieces. However, movmemsi effectively uses a by-pieces -+ implementation both for moves smaller than a word and for word-aligned -+ moves of no more than RISCV_MAX_MOVE_BYTES_STRAIGHT bytes. We should -+ allow the tree-level optimisers to do such moves by pieces, as it -+ often exposes other optimization opportunities. We might as well -+ continue to use movmemsi at the rtl level though, as it produces -+ better code when scheduling is disabled (such as at -O). */ -+ -+#define MOVE_BY_PIECES_P(SIZE, ALIGN) \ -+ (HAVE_movmemsi \ -+ ? (!currently_expanding_to_rtl \ -+ && ((ALIGN) < BITS_PER_WORD \ -+ ? (SIZE) < UNITS_PER_WORD \ -+ : (SIZE) <= RISCV_MAX_MOVE_BYTES_STRAIGHT)) \ -+ : (move_by_pieces_ninsns (SIZE, ALIGN, MOVE_MAX_PIECES + 1) \ -+ < (unsigned int) MOVE_RATIO (false))) -+ -+/* For CLEAR_RATIO, when optimizing for size, give a better estimate -+ of the length of a memset call, but use the default otherwise. */ -+ -+#define CLEAR_RATIO(speed)\ -+ ((speed) ? 15 : RISCV_CALL_RATIO) -+ -+/* This is similar to CLEAR_RATIO, but for a non-zero constant, so when -+ optimizing for size adjust the ratio to account for the overhead of -+ loading the constant and replicating it across the word. */ -+ -+#define SET_RATIO(speed) \ -+ ((speed) ? 15 : RISCV_CALL_RATIO - 2) -+ -+/* STORE_BY_PIECES_P can be used when copying a constant string, but -+ in that case each word takes 3 insns (lui, ori, sw), or more in -+ 64-bit mode, instead of 2 (lw, sw). For now we always fail this -+ and let the move_by_pieces code copy the string from read-only -+ memory. In the future, this could be tuned further for multi-issue -+ CPUs that can issue stores down one pipe and arithmetic instructions -+ down another; in that case, the lui/ori/sw combination would be a -+ win for long enough strings. */ -+ -+#define STORE_BY_PIECES_P(SIZE, ALIGN) 0 -+ -+#ifndef HAVE_AS_TLS -+#define HAVE_AS_TLS 0 -+#endif -+ -+#ifndef USED_FOR_TARGET -+ -+extern const enum reg_class riscv_regno_to_class[]; -+extern bool riscv_hard_regno_mode_ok[][FIRST_PSEUDO_REGISTER]; -+extern const char* riscv_hi_relocs[]; -+extern enum processor riscv_tune; /* which cpu to schedule for */ -+#endif -+ -+#define ASM_PREFERRED_EH_DATA_FORMAT(CODE,GLOBAL) \ -+ (((GLOBAL) ? DW_EH_PE_indirect : 0) | DW_EH_PE_absptr) -diff --git a/gcc-4.6.1/gcc/config/riscv/riscv.md b/gcc-4.6.1/gcc/config/riscv/riscv.md -new file mode 100644 -index 0000000..5f1dd42 ---- /dev/null -+++ gcc-4.6.1/gcc/config/riscv/riscv.md -@@ -0,0 +1,2421 @@ -+;; Machine description for RISC-V for GNU compiler. -+;; Copyright (C) 2011-2014 Free Software Foundation, Inc. -+;; Contributed by Andrew Waterman (waterman@cs.berkeley.edu) at UC Berkeley. -+;; Based on MIPS target for GNU compiler. -+ -+;; This file is part of GCC. -+ -+;; GCC is free software; you can redistribute it and/or modify -+;; it under the terms of the GNU General Public License as published by -+;; the Free Software Foundation; either version 3, or (at your option) -+;; any later version. -+ -+;; GCC is distributed in the hope that it will be useful, -+;; but WITHOUT ANY WARRANTY; without even the implied warranty of -+;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -+;; GNU General Public License for more details. -+ -+;; You should have received a copy of the GNU General Public License -+;; along with GCC; see the file COPYING3. If not see -+;; . -+ -+(define_enum "processor" [ -+ rocket -+]) -+ -+(define_c_enum "unspec" [ -+ ;; Floating-point moves. -+ UNSPEC_LOAD_LOW -+ UNSPEC_LOAD_HIGH -+ UNSPEC_STORE_WORD -+ -+ ;; GP manipulation. -+ UNSPEC_EH_RETURN -+ -+ ;; Symbolic accesses. -+ UNSPEC_LOAD_GOT -+ UNSPEC_TLS_LE_ADD -+ UNSPEC_TLS_IE_ADD -+ UNSPEC_TLS_GD -+ UNSPEC_TLS_IE -+ UNSPEC_TLS_IE_HI -+ UNSPEC_TLS_IE_LO -+ -+ ;; Blockage and synchronisation. -+ UNSPEC_BLOCKAGE -+ UNSPEC_FENCE -+ UNSPEC_FENCE_I -+]) -+ -+(define_constants -+ [(RETURN_ADDR_REGNUM 1) -+]) -+ -+(include "predicates.md") -+(include "constraints.md") -+ -+;; .................... -+;; -+;; Attributes -+;; -+;; .................... -+ -+(define_attr "got" "unset,xgot_high,load" -+ (const_string "unset")) -+ -+;; For jal instructions, this attribute is DIRECT when the target address -+;; is symbolic and INDIRECT when it is a register. -+(define_attr "jal" "unset,direct,indirect" -+ (const_string "unset")) -+ -+;; Classification of moves, extensions and truncations. Most values -+;; are as for "type" (see below) but there are also the following -+;; move-specific values: -+;; -+;; andi a single ANDI instruction -+;; shift_shift a shift left followed by a shift right -+;; -+;; This attribute is used to determine the instruction's length and -+;; scheduling type. For doubleword moves, the attribute always describes -+;; the split instructions; in some cases, it is more appropriate for the -+;; scheduling type to be "multi" instead. -+(define_attr "move_type" -+ "unknown,load,fpload,store,fpstore,mtc,mfc,move,fmove, -+ const,logical,arith,andi,shift_shift" -+ (const_string "unknown")) -+ -+(define_attr "alu_type" "unknown,add,sub,and,or,xor" -+ (const_string "unknown")) -+ -+;; Main data type used by the insn -+(define_attr "mode" "unknown,none,QI,HI,SI,DI,TI,SF,DF,TF,FPSW" -+ (const_string "unknown")) -+ -+;; True if the main data type is twice the size of a word. -+(define_attr "dword_mode" "no,yes" -+ (cond [(and (eq_attr "mode" "DI,DF") -+ (eq (symbol_ref "TARGET_64BIT") (const_int 0))) -+ (const_string "yes") -+ -+ (and (eq_attr "mode" "TI,TF") -+ (ne (symbol_ref "TARGET_64BIT") (const_int 0))) -+ (const_string "yes")] -+ (const_string "no"))) -+ -+;; Classification of each insn. -+;; branch conditional branch -+;; jump unconditional jump -+;; call unconditional call -+;; load load instruction(s) -+;; fpload floating point load -+;; fpidxload floating point indexed load -+;; store store instruction(s) -+;; fpstore floating point store -+;; fpidxstore floating point indexed store -+;; mtc transfer to coprocessor -+;; mfc transfer from coprocessor -+;; const load constant -+;; arith integer arithmetic instructions -+;; logical integer logical instructions -+;; shift integer shift instructions -+;; slt set less than instructions -+;; imul integer multiply -+;; idiv integer divide -+;; move integer register move (addi rd, rs1, 0) -+;; fmove floating point register move -+;; fadd floating point add/subtract -+;; fmul floating point multiply -+;; fmadd floating point multiply-add -+;; fdiv floating point divide -+;; fcmp floating point compare -+;; fcvt floating point convert -+;; fsqrt floating point square root -+;; multi multiword sequence (or user asm statements) -+;; nop no operation -+;; ghost an instruction that produces no real code -+(define_attr "type" -+ "unknown,branch,jump,call,load,fpload,fpidxload,store,fpstore,fpidxstore, -+ mtc,mfc,const,arith,logical,shift,slt,imul,idiv,move,fmove,fadd,fmul, -+ fmadd,fdiv,fcmp,fcvt,fsqrt,multi,nop,ghost" -+ (cond [(eq_attr "jal" "!unset") (const_string "call") -+ (eq_attr "got" "load") (const_string "load") -+ -+ (eq_attr "alu_type" "add,sub") (const_string "arith") -+ -+ (eq_attr "alu_type" "and,or,xor") (const_string "logical") -+ -+ ;; If a doubleword move uses these expensive instructions, -+ ;; it is usually better to schedule them in the same way -+ ;; as the singleword form, rather than as "multi". -+ (eq_attr "move_type" "load") (const_string "load") -+ (eq_attr "move_type" "fpload") (const_string "fpload") -+ (eq_attr "move_type" "store") (const_string "store") -+ (eq_attr "move_type" "fpstore") (const_string "fpstore") -+ (eq_attr "move_type" "mtc") (const_string "mtc") -+ (eq_attr "move_type" "mfc") (const_string "mfc") -+ -+ ;; These types of move are always single insns. -+ (eq_attr "move_type" "fmove") (const_string "fmove") -+ (eq_attr "move_type" "arith") (const_string "arith") -+ (eq_attr "move_type" "logical") (const_string "logical") -+ (eq_attr "move_type" "andi") (const_string "logical") -+ -+ ;; These types of move are always split. -+ (eq_attr "move_type" "shift_shift") -+ (const_string "multi") -+ -+ ;; These types of move are split for doubleword modes only. -+ (and (eq_attr "move_type" "move,const") -+ (eq_attr "dword_mode" "yes")) -+ (const_string "multi") -+ (eq_attr "move_type" "move") (const_string "move") -+ (eq_attr "move_type" "const") (const_string "const")] -+ (const_string "unknown"))) -+ -+;; Mode for conversion types (fcvt) -+;; I2S integer to float single (SI/DI to SF) -+;; I2D integer to float double (SI/DI to DF) -+;; S2I float to integer (SF to SI/DI) -+;; D2I float to integer (DF to SI/DI) -+;; D2S double to float single -+;; S2D float single to double -+ -+(define_attr "cnv_mode" "unknown,I2S,I2D,S2I,D2I,D2S,S2D" -+ (const_string "unknown")) -+ -+;; Length of instruction in bytes. -+(define_attr "length" "" -+ (cond [ -+ ;; Direct branch instructions have a range of [-0x1000,0xffc], -+ ;; relative to the address of the delay slot. If a branch is -+ ;; outside this range, convert a branch like: -+ ;; -+ ;; bne r1,r2,target -+ ;; -+ ;; to: -+ ;; -+ ;; beq r1,r2,1f -+ ;; j target -+ ;; 1: -+ ;; -+ (eq_attr "type" "branch") -+ (if_then_else (and (le (minus (match_dup 0) (pc)) (const_int 4088)) -+ (le (minus (pc) (match_dup 0)) (const_int 4092))) -+ (const_int 4) -+ (const_int 8)) -+ -+ ;; Conservatively assume calls take two instructions, as in: -+ ;; auipc t0, %pcrel_hi(target) -+ ;; jalr ra, t0, %lo(target) -+ ;; The linker will relax these into JAL when appropriate. -+ (eq_attr "type" "call") -+ (const_int 8) -+ -+ ;; "Ghost" instructions occupy no space. -+ (eq_attr "type" "ghost") -+ (const_int 0) -+ -+ (eq_attr "got" "load") (const_int 8) -+ -+ ;; SHIFT_SHIFTs are decomposed into two separate instructions. -+ (eq_attr "move_type" "shift_shift") -+ (const_int 8) -+ -+ ;; Check for doubleword moves that are decomposed into two -+ ;; instructions. -+ (and (eq_attr "move_type" "mtc,mfc,move") -+ (eq_attr "dword_mode" "yes")) -+ (const_int 8) -+ -+ ;; Doubleword CONST{,N} moves are split into two word -+ ;; CONST{,N} moves. -+ (and (eq_attr "move_type" "const") -+ (eq_attr "dword_mode" "yes")) -+ (symbol_ref "riscv_split_const_insns (operands[1]) * 4") -+ -+ ;; Otherwise, constants, loads and stores are handled by external -+ ;; routines. -+ (eq_attr "move_type" "load,fpload") -+ (symbol_ref "mips_load_store_insns (operands[1], insn) * 4") -+ (eq_attr "move_type" "store,fpstore") -+ (symbol_ref "mips_load_store_insns (operands[0], insn) * 4") -+ ] (const_int 4))) -+ -+;; Attribute describing the processor. -+(define_enum_attr "cpu" "processor" -+ (const (symbol_ref "riscv_tune"))) -+ -+;; Describe a user's asm statement. -+(define_asm_attributes -+ [(set_attr "type" "multi")]) -+ -+;; This mode iterator allows 32-bit and 64-bit GPR patterns to be generated -+;; from the same template. -+(define_mode_iterator GPR [SI (DI "TARGET_64BIT")]) -+(define_mode_iterator SUPERQI [HI SI (DI "TARGET_64BIT")]) -+ -+;; A copy of GPR that can be used when a pattern has two independent -+;; modes. -+(define_mode_iterator GPR2 [SI (DI "TARGET_64BIT")]) -+ -+;; This mode iterator allows :P to be used for patterns that operate on -+;; pointer-sized quantities. Exactly one of the two alternatives will match. -+(define_mode_iterator P [(SI "Pmode == SImode") (DI "Pmode == DImode")]) -+ -+;; 32-bit integer moves for which we provide move patterns. -+(define_mode_iterator IMOVE32 [SI]) -+ -+;; 64-bit modes for which we provide move patterns. -+(define_mode_iterator MOVE64 [DI DF]) -+ -+;; 128-bit modes for which we provide move patterns on 64-bit targets. -+(define_mode_iterator MOVE128 [TI TF]) -+ -+;; This mode iterator allows the QI and HI extension patterns to be -+;; defined from the same template. -+(define_mode_iterator SHORT [QI HI]) -+ -+;; Likewise the 64-bit truncate-and-shift patterns. -+(define_mode_iterator SUBDI [QI HI SI]) -+(define_mode_iterator HISI [HI SI]) -+(define_mode_iterator ANYI [QI HI SI (DI "TARGET_64BIT")]) -+ -+;; This mode iterator allows :ANYF to be used wherever a scalar or vector -+;; floating-point mode is allowed. -+(define_mode_iterator ANYF [(SF "TARGET_HARD_FLOAT") -+ (DF "TARGET_HARD_FLOAT")]) -+(define_mode_iterator ANYIF [QI HI SI (DI "TARGET_64BIT") -+ (SF "TARGET_HARD_FLOAT") -+ (DF "TARGET_HARD_FLOAT")]) -+ -+;; Like ANYF, but only applies to scalar modes. -+(define_mode_iterator SCALARF [(SF "TARGET_HARD_FLOAT") -+ (DF "TARGET_HARD_FLOAT")]) -+ -+;; A floating-point mode for which moves involving FPRs may need to be split. -+(define_mode_iterator SPLITF -+ [(DF "!TARGET_64BIT") -+ (DI "!TARGET_64BIT") -+ (TF "TARGET_64BIT")]) -+ -+;; This attribute gives the length suffix for a sign- or zero-extension -+;; instruction. -+(define_mode_attr size [(QI "b") (HI "h")]) -+ -+;; Mode attributes for loads. -+(define_mode_attr load [(QI "lb") (HI "lh") (SI "lw") (DI "ld") (SF "flw") (DF "fld")]) -+ -+;; Instruction names for stores. -+(define_mode_attr store [(QI "sb") (HI "sh") (SI "sw") (DI "sd") (SF "fsw") (DF "fsd")]) -+ -+;; This attribute gives the best constraint to use for registers of -+;; a given mode. -+(define_mode_attr reg [(SI "d") (DI "d") (CC "d")]) -+ -+;; This attribute gives the format suffix for floating-point operations. -+(define_mode_attr fmt [(SF "s") (DF "d")]) -+ -+;; This attribute gives the format suffix for atomic memory operations. -+(define_mode_attr amo [(SI "w") (DI "d")]) -+ -+;; This attribute gives the upper-case mode name for one unit of a -+;; floating-point mode. -+(define_mode_attr UNITMODE [(SF "SF") (DF "DF")]) -+ -+;; This attribute gives the integer mode that has half the size of -+;; the controlling mode. -+(define_mode_attr HALFMODE [(DF "SI") (DI "SI") (TF "DI")]) -+ -+;; This code iterator allows signed and unsigned widening multiplications -+;; to use the same template. -+(define_code_iterator any_extend [sign_extend zero_extend]) -+ -+;; This code iterator allows the two right shift instructions to be -+;; generated from the same template. -+(define_code_iterator any_shiftrt [ashiftrt lshiftrt]) -+ -+;; This code iterator allows the three shift instructions to be generated -+;; from the same template. -+(define_code_iterator any_shift [ashift ashiftrt lshiftrt]) -+ -+;; This code iterator allows unsigned and signed division to be generated -+;; from the same template. -+(define_code_iterator any_div [div udiv]) -+ -+;; This code iterator allows unsigned and signed modulus to be generated -+;; from the same template. -+(define_code_iterator any_mod [mod umod]) -+ -+;; Equality operators. -+(define_code_iterator equality_op [eq ne]) -+ -+;; These code iterators allow the signed and unsigned scc operations to use -+;; the same template. -+(define_code_iterator any_gt [gt gtu]) -+(define_code_iterator any_ge [ge geu]) -+(define_code_iterator any_lt [lt ltu]) -+(define_code_iterator any_le [le leu]) -+ -+;; expands to an empty string when doing a signed operation and -+;; "u" when doing an unsigned operation. -+(define_code_attr u [(sign_extend "") (zero_extend "u") -+ (div "") (udiv "u") -+ (mod "") (umod "u") -+ (gt "") (gtu "u") -+ (ge "") (geu "u") -+ (lt "") (ltu "u") -+ (le "") (leu "u")]) -+ -+;; is like , but the signed form expands to "s" rather than "". -+(define_code_attr su [(sign_extend "s") (zero_extend "u")]) -+ -+;; expands to the name of the optab for a particular code. -+(define_code_attr optab [(ashift "ashl") -+ (ashiftrt "ashr") -+ (lshiftrt "lshr") -+ (ior "ior") -+ (xor "xor") -+ (and "and") -+ (plus "add") -+ (minus "sub")]) -+ -+;; expands to the name of the insn that implements a particular code. -+(define_code_attr insn [(ashift "sll") -+ (ashiftrt "sra") -+ (lshiftrt "srl") -+ (ior "or") -+ (xor "xor") -+ (and "and") -+ (plus "add") -+ (minus "sub")]) -+ -+;; The value of the bit when the branch is taken for branch_bit patterns. -+;; Comparison is always against zero so this depends on the operator. -+(define_code_attr bbv [(eq "0") (ne "1")]) -+ -+;; This is the inverse value of bbv. -+(define_code_attr bbinv [(eq "1") (ne "0")]) -+ -+;; Pipeline descriptions. -+;; -+;; generic.md provides a fallback for processors without a specific -+;; pipeline description. It is derived from the old define_function_unit -+;; version and uses the "alu" and "imuldiv" units declared below. -+;; -+;; Some of the processor-specific files are also derived from old -+;; define_function_unit descriptions and simply override the parts of -+;; generic.md that don't apply. The other processor-specific files -+;; are self-contained. -+(define_automaton "alu,imuldiv") -+ -+(define_cpu_unit "alu" "alu") -+(define_cpu_unit "imuldiv" "imuldiv") -+ -+;; Ghost instructions produce no real code and introduce no hazards. -+;; They exist purely to express an effect on dataflow. -+(define_insn_reservation "ghost" 0 -+ (eq_attr "type" "ghost") -+ "nothing") -+ -+(include "generic.md") -+ -+;; -+;; .................... -+;; -+;; ADDITION -+;; -+;; .................... -+;; -+ -+(define_insn "add3" -+ [(set (match_operand:ANYF 0 "register_operand" "=f") -+ (plus:ANYF (match_operand:ANYF 1 "register_operand" "f") -+ (match_operand:ANYF 2 "register_operand" "f")))] -+ "" -+ "fadd.\t%0,%1,%2" -+ [(set_attr "type" "fadd") -+ (set_attr "mode" "")]) -+ -+(define_expand "add3" -+ [(set (match_operand:GPR 0 "register_operand") -+ (plus:GPR (match_operand:GPR 1 "register_operand") -+ (match_operand:GPR 2 "arith_operand")))] -+ "") -+ -+(define_insn "*addsi3" -+ [(set (match_operand:SI 0 "register_operand" "=r,r") -+ (plus:SI (match_operand:GPR 1 "register_operand" "r,r") -+ (match_operand:GPR2 2 "arith_operand" "r,Q")))] -+ "" -+ { return TARGET_64BIT ? "addw\t%0,%1,%2" : "add\t%0,%1,%2"; } -+ [(set_attr "type" "arith") -+ (set_attr "mode" "SI")]) -+ -+(define_insn "*adddi3" -+ [(set (match_operand:DI 0 "register_operand" "=r,r") -+ (plus:DI (match_operand:DI 1 "register_operand" "r,r") -+ (match_operand:DI 2 "arith_operand" "r,Q")))] -+ "TARGET_64BIT" -+ "add\t%0,%1,%2" -+ [(set_attr "type" "arith") -+ (set_attr "mode" "DI")]) -+ -+(define_insn "*addsi3_extended" -+ [(set (match_operand:DI 0 "register_operand" "=r,r") -+ (sign_extend:DI -+ (plus:SI (match_operand:SI 1 "register_operand" "r,r") -+ (match_operand:SI 2 "arith_operand" "r,Q"))))] -+ "TARGET_64BIT" -+ "addw\t%0,%1,%2" -+ [(set_attr "type" "arith") -+ (set_attr "mode" "SI")]) -+ -+(define_insn "*adddisi3" -+ [(set (match_operand:SI 0 "register_operand" "=r,r") -+ (plus:SI (truncate:SI (match_operand:DI 1 "register_operand" "r,r")) -+ (truncate:SI (match_operand:DI 2 "arith_operand" "r,Q"))))] -+ "TARGET_64BIT" -+ "addw\t%0,%1,%2" -+ [(set_attr "type" "arith") -+ (set_attr "mode" "SI")]) -+ -+(define_insn "*adddisisi3" -+ [(set (match_operand:SI 0 "register_operand" "=r,r") -+ (plus:SI (truncate:SI (match_operand:DI 1 "register_operand" "r,r")) -+ (match_operand:SI 2 "arith_operand" "r,Q")))] -+ "TARGET_64BIT" -+ "addw\t%0,%1,%2" -+ [(set_attr "type" "arith") -+ (set_attr "mode" "SI")]) -+ -+(define_insn "*adddi3_truncsi" -+ [(set (match_operand:SI 0 "register_operand" "=r,r") -+ (truncate:SI -+ (plus:DI (match_operand:DI 1 "register_operand" "r,r") -+ (match_operand:DI 2 "arith_operand" "r,Q"))))] -+ "TARGET_64BIT" -+ "addw\t%0,%1,%2" -+ [(set_attr "type" "arith") -+ (set_attr "mode" "SI")]) -+ -+;; HImode constant generation; see mips_move_integer for details. -+;; si+si->hi without truncation is legal because of TRULY_NOOP_TRUNCATION. -+ -+(define_insn "addhi3" -+ [(set (match_operand:HI 0 "register_operand" "=r,r") -+ (plus:HI (match_operand:HISI 1 "register_operand" "r,r") -+ (match_operand:HISI 2 "arith_operand" "r,Q")))] -+ "" -+ { return TARGET_64BIT ? "addw\t%0,%1,%2" : "add\t%0,%1,%2"; } -+ [(set_attr "type" "arith") -+ (set_attr "mode" "HI")]) -+ -+;; -+;; .................... -+;; -+;; SUBTRACTION -+;; -+;; .................... -+;; -+ -+(define_insn "sub3" -+ [(set (match_operand:ANYF 0 "register_operand" "=f") -+ (minus:ANYF (match_operand:ANYF 1 "register_operand" "f") -+ (match_operand:ANYF 2 "register_operand" "f")))] -+ "" -+ "fsub.\t%0,%1,%2" -+ [(set_attr "type" "fadd") -+ (set_attr "mode" "")]) -+ -+(define_expand "sub3" -+ [(set (match_operand:GPR 0 "register_operand") -+ (minus:GPR (match_operand:GPR 1 "reg_or_0_operand") -+ (match_operand:GPR 2 "register_operand")))] -+ "") -+ -+(define_insn "*subdi3" -+ [(set (match_operand:DI 0 "register_operand" "=r") -+ (minus:DI (match_operand:DI 1 "reg_or_0_operand" "rJ") -+ (match_operand:DI 2 "register_operand" "r")))] -+ "TARGET_64BIT" -+ "sub\t%0,%z1,%2" -+ [(set_attr "type" "arith") -+ (set_attr "mode" "DI")]) -+ -+(define_insn "*subsi3" -+ [(set (match_operand:SI 0 "register_operand" "=r") -+ (minus:SI (match_operand:GPR 1 "reg_or_0_operand" "rJ") -+ (match_operand:GPR2 2 "register_operand" "r")))] -+ "" -+ { return TARGET_64BIT ? "subw\t%0,%z1,%2" : "sub\t%0,%z1,%2"; } -+ [(set_attr "type" "arith") -+ (set_attr "mode" "SI")]) -+ -+(define_insn "*subsi3_extended" -+ [(set (match_operand:DI 0 "register_operand" "=r") -+ (sign_extend:DI -+ (minus:SI (match_operand:SI 1 "reg_or_0_operand" "rJ") -+ (match_operand:SI 2 "register_operand" "r"))))] -+ "TARGET_64BIT" -+ "subw\t%0,%z1,%2" -+ [(set_attr "type" "arith") -+ (set_attr "mode" "DI")]) -+ -+(define_insn "*subdisi3" -+ [(set (match_operand:SI 0 "register_operand" "=r") -+ (minus:SI (truncate:SI (match_operand:DI 1 "reg_or_0_operand" "rJ")) -+ (truncate:SI (match_operand:DI 2 "register_operand" "r"))))] -+ "TARGET_64BIT" -+ "subw\t%0,%z1,%2" -+ [(set_attr "type" "arith") -+ (set_attr "mode" "SI")]) -+ -+(define_insn "*subdisisi3" -+ [(set (match_operand:SI 0 "register_operand" "=r") -+ (minus:SI (truncate:SI (match_operand:DI 1 "reg_or_0_operand" "rJ")) -+ (match_operand:SI 2 "register_operand" "r")))] -+ "TARGET_64BIT" -+ "subw\t%0,%z1,%2" -+ [(set_attr "type" "arith") -+ (set_attr "mode" "SI")]) -+ -+(define_insn "*subsidisi3" -+ [(set (match_operand:SI 0 "register_operand" "=r") -+ (minus:SI (match_operand:SI 1 "reg_or_0_operand" "rJ") -+ (truncate:SI (match_operand:DI 2 "register_operand" "r"))))] -+ "TARGET_64BIT" -+ "subw\t%0,%z1,%2" -+ [(set_attr "type" "arith") -+ (set_attr "mode" "SI")]) -+ -+(define_insn "*subdi3_truncsi" -+ [(set (match_operand:SI 0 "register_operand" "=r,r") -+ (truncate:SI -+ (minus:DI (match_operand:DI 1 "reg_or_0_operand" "rJ,r") -+ (match_operand:DI 2 "arith_operand" "r,Q"))))] -+ "TARGET_64BIT" -+ "subw\t%0,%z1,%2" -+ [(set_attr "type" "arith") -+ (set_attr "mode" "SI")]) -+ -+;; -+;; .................... -+;; -+;; MULTIPLICATION -+;; -+;; .................... -+;; -+ -+(define_insn "mul3" -+ [(set (match_operand:SCALARF 0 "register_operand" "=f") -+ (mult:SCALARF (match_operand:SCALARF 1 "register_operand" "f") -+ (match_operand:SCALARF 2 "register_operand" "f")))] -+ "" -+ "fmul.\t%0,%1,%2" -+ [(set_attr "type" "fmul") -+ (set_attr "mode" "")]) -+ -+(define_expand "mul3" -+ [(set (match_operand:GPR 0 "register_operand") -+ (mult:GPR (match_operand:GPR 1 "reg_or_0_operand") -+ (match_operand:GPR 2 "register_operand")))] -+ "TARGET_RVM") -+ -+(define_insn "*mulsi3" -+ [(set (match_operand:SI 0 "register_operand" "=r") -+ (mult:SI (match_operand:GPR 1 "register_operand" "r") -+ (match_operand:GPR2 2 "register_operand" "r")))] -+ "TARGET_RVM" -+ { return TARGET_64BIT ? "mulw\t%0,%1,%2" : "mul\t%0,%1,%2"; } -+ [(set_attr "type" "imul") -+ (set_attr "mode" "SI")]) -+ -+(define_insn "*muldisi3" -+ [(set (match_operand:SI 0 "register_operand" "=r") -+ (mult:SI (truncate:SI (match_operand:DI 1 "register_operand" "r")) -+ (truncate:SI (match_operand:DI 2 "register_operand" "r"))))] -+ "TARGET_64BIT && TARGET_RVM" -+ "mulw\t%0,%1,%2" -+ [(set_attr "type" "imul") -+ (set_attr "mode" "SI")]) -+ -+(define_insn "*muldi3_truncsi" -+ [(set (match_operand:SI 0 "register_operand" "=r") -+ (truncate:SI -+ (mult:DI (match_operand:DI 1 "register_operand" "r") -+ (match_operand:DI 2 "register_operand" "r"))))] -+ "TARGET_64BIT && TARGET_RVM" -+ "mulw\t%0,%1,%2" -+ [(set_attr "type" "imul") -+ (set_attr "mode" "SI")]) -+ -+(define_insn "*muldi3" -+ [(set (match_operand:DI 0 "register_operand" "=r") -+ (mult:DI (match_operand:DI 1 "register_operand" "r") -+ (match_operand:DI 2 "register_operand" "r")))] -+ "TARGET_64BIT && TARGET_RVM" -+ "mul\t%0,%1,%2" -+ [(set_attr "type" "imul") -+ (set_attr "mode" "DI")]) -+ -+;; -+;; ........................ -+;; -+;; MULTIPLICATION HIGH-PART -+;; -+;; ........................ -+;; -+ -+ -+;; Using a clobber here is ghetto, but I'm not smart enough to do better. ' -+(define_insn_and_split "mulditi3" -+ [(set (match_operand:TI 0 "register_operand" "=r") -+ (mult:TI (any_extend:TI -+ (match_operand:DI 1 "register_operand" "r")) -+ (any_extend:TI -+ (match_operand:DI 2 "register_operand" "r")))) -+ (clobber (match_scratch:DI 3 "=r"))] -+ "TARGET_64BIT && TARGET_RVM" -+ "#" -+ "reload_completed" -+ [ -+ (set (match_dup 3) (mult:DI (match_dup 1) (match_dup 2))) -+ (set (match_dup 4) (truncate:DI -+ (lshiftrt:TI -+ (mult:TI (any_extend:TI (match_dup 1)) -+ (any_extend:TI (match_dup 2))) -+ (const_int 64)))) -+ (set (match_dup 5) (match_dup 3)) -+ ] -+{ -+ operands[4] = mips_subword (operands[0], true); -+ operands[5] = mips_subword (operands[0], false); -+} -+ ) -+ -+(define_insn "muldi3_highpart" -+ [(set (match_operand:DI 0 "register_operand" "=r") -+ (truncate:DI -+ (lshiftrt:TI -+ (mult:TI (any_extend:TI -+ (match_operand:DI 1 "register_operand" "r")) -+ (any_extend:TI -+ (match_operand:DI 2 "register_operand" "r"))) -+ (const_int 64))))] -+ "TARGET_64BIT && TARGET_RVM" -+ "mulh\t%0,%1,%2" -+ [(set_attr "type" "imul") -+ (set_attr "mode" "DI")]) -+ -+ -+(define_insn_and_split "usmulditi3" -+ [(set (match_operand:TI 0 "register_operand" "=r") -+ (mult:TI (zero_extend:TI -+ (match_operand:DI 1 "register_operand" "r")) -+ (sign_extend:TI -+ (match_operand:DI 2 "register_operand" "r")))) -+ (clobber (match_scratch:DI 3 "=r"))] -+ "TARGET_64BIT && TARGET_RVM" -+ "#" -+ "reload_completed" -+ [ -+ (set (match_dup 3) (mult:DI (match_dup 1) (match_dup 2))) -+ (set (match_dup 4) (truncate:DI -+ (lshiftrt:TI -+ (mult:TI (zero_extend:TI (match_dup 1)) -+ (sign_extend:TI (match_dup 2))) -+ (const_int 64)))) -+ (set (match_dup 5) (match_dup 3)) -+ ] -+{ -+ operands[4] = mips_subword (operands[0], true); -+ operands[5] = mips_subword (operands[0], false); -+} -+ ) -+ -+(define_insn "usmuldi3_highpart" -+ [(set (match_operand:DI 0 "register_operand" "=r") -+ (truncate:DI -+ (lshiftrt:TI -+ (mult:TI (zero_extend:TI -+ (match_operand:DI 1 "register_operand" "r")) -+ (sign_extend:TI -+ (match_operand:DI 2 "register_operand" "r"))) -+ (const_int 64))))] -+ "TARGET_64BIT && TARGET_RVM" -+ "mulhsu\t%0,%2,%1" -+ [(set_attr "type" "imul") -+ (set_attr "mode" "DI")]) -+ -+(define_insn_and_split "mulsidi3" -+ [(set (match_operand:DI 0 "register_operand" "=r") -+ (mult:DI (any_extend:DI -+ (match_operand:SI 1 "register_operand" "r")) -+ (any_extend:DI -+ (match_operand:SI 2 "register_operand" "r")))) -+ (clobber (match_scratch:SI 3 "=r"))] -+ "!TARGET_64BIT && TARGET_RVM" -+ "#" -+ "reload_completed" -+ [ -+ (set (match_dup 3) (mult:SI (match_dup 1) (match_dup 2))) -+ (set (match_dup 4) (truncate:SI -+ (lshiftrt:DI -+ (mult:DI (any_extend:DI (match_dup 1)) -+ (any_extend:DI (match_dup 2))) -+ (const_int 32)))) -+ (set (match_dup 5) (match_dup 3)) -+ ] -+{ -+ operands[4] = mips_subword (operands[0], true); -+ operands[5] = mips_subword (operands[0], false); -+} -+ ) -+ -+(define_insn "mulsi3_highpart" -+ [(set (match_operand:SI 0 "register_operand" "=r") -+ (truncate:SI -+ (lshiftrt:DI -+ (mult:DI (any_extend:DI -+ (match_operand:SI 1 "register_operand" "r")) -+ (any_extend:DI -+ (match_operand:SI 2 "register_operand" "r"))) -+ (const_int 32))))] -+ "!TARGET_64BIT && TARGET_RVM" -+ "mulh\t%0,%1,%2" -+ [(set_attr "type" "imul") -+ (set_attr "mode" "SI")]) -+ -+ -+(define_insn_and_split "usmulsidi3" -+ [(set (match_operand:DI 0 "register_operand" "=r") -+ (mult:DI (zero_extend:DI -+ (match_operand:SI 1 "register_operand" "r")) -+ (sign_extend:DI -+ (match_operand:SI 2 "register_operand" "r")))) -+ (clobber (match_scratch:SI 3 "=r"))] -+ "!TARGET_64BIT && TARGET_RVM" -+ "#" -+ "reload_completed" -+ [ -+ (set (match_dup 3) (mult:SI (match_dup 1) (match_dup 2))) -+ (set (match_dup 4) (truncate:SI -+ (lshiftrt:DI -+ (mult:DI (zero_extend:DI (match_dup 1)) -+ (sign_extend:DI (match_dup 2))) -+ (const_int 32)))) -+ (set (match_dup 5) (match_dup 3)) -+ ] -+{ -+ operands[4] = mips_subword (operands[0], true); -+ operands[5] = mips_subword (operands[0], false); -+} -+ ) -+ -+(define_insn "usmulsi3_highpart" -+ [(set (match_operand:SI 0 "register_operand" "=r") -+ (truncate:SI -+ (lshiftrt:DI -+ (mult:DI (zero_extend:DI -+ (match_operand:SI 1 "register_operand" "r")) -+ (sign_extend:DI -+ (match_operand:SI 2 "register_operand" "r"))) -+ (const_int 32))))] -+ "!TARGET_64BIT && TARGET_RVM" -+ "mulhsu\t%0,%2,%1" -+ [(set_attr "type" "imul") -+ (set_attr "mode" "SI")]) -+ -+;; -+;; .................... -+;; -+;; DIVISION and REMAINDER -+;; -+;; .................... -+;; -+ -+(define_insn "divsi3" -+ [(set (match_operand:SI 0 "register_operand" "=r") -+ (any_div:SI (match_operand:SI 1 "register_operand" "r") -+ (match_operand:SI 2 "register_operand" "r")))] -+ "TARGET_RVM" -+ { return TARGET_64BIT ? "divw\t%0,%1,%2" : "div\t%0,%1,%2"; } -+ [(set_attr "type" "idiv") -+ (set_attr "mode" "SI")]) -+ -+(define_insn "divdi3" -+ [(set (match_operand:DI 0 "register_operand" "=r") -+ (any_div:DI (match_operand:DI 1 "register_operand" "r") -+ (match_operand:DI 2 "register_operand" "r")))] -+ "TARGET_64BIT && TARGET_RVM" -+ "div\t%0,%1,%2" -+ [(set_attr "type" "idiv") -+ (set_attr "mode" "DI")]) -+ -+(define_insn "modsi3" -+ [(set (match_operand:SI 0 "register_operand" "=r") -+ (any_mod:SI (match_operand:SI 1 "register_operand" "r") -+ (match_operand:SI 2 "register_operand" "r")))] -+ "TARGET_RVM" -+ { return TARGET_64BIT ? "remw\t%0,%1,%2" : "rem\t%0,%1,%2"; } -+ [(set_attr "type" "idiv") -+ (set_attr "mode" "SI")]) -+ -+(define_insn "moddi3" -+ [(set (match_operand:DI 0 "register_operand" "=r") -+ (any_mod:DI (match_operand:DI 1 "register_operand" "r") -+ (match_operand:DI 2 "register_operand" "r")))] -+ "TARGET_64BIT && TARGET_RVM" -+ "rem\t%0,%1,%2" -+ [(set_attr "type" "idiv") -+ (set_attr "mode" "DI")]) -+ -+(define_insn "div3" -+ [(set (match_operand:ANYF 0 "register_operand" "=f") -+ (div:ANYF (match_operand:ANYF 1 "register_operand" "f") -+ (match_operand:ANYF 2 "register_operand" "f")))] -+ "TARGET_HARD_FLOAT && TARGET_FDIV" -+ "fdiv.\t%0,%1,%2" -+ [(set_attr "type" "fdiv") -+ (set_attr "mode" "")]) -+ -+;; -+;; .................... -+;; -+;; SQUARE ROOT -+;; -+;; .................... -+ -+(define_insn "sqrt2" -+ [(set (match_operand:ANYF 0 "register_operand" "=f") -+ (sqrt:ANYF (match_operand:ANYF 1 "register_operand" "f")))] -+ "TARGET_HARD_FLOAT && TARGET_FDIV" -+{ -+ return "fsqrt.\t%0,%1"; -+} -+ [(set_attr "type" "fsqrt") -+ (set_attr "mode" "")]) -+ -+;; Floating point multiply accumulate instructions. -+ -+(define_insn "fma4" -+ [(set (match_operand:ANYF 0 "register_operand" "=f") -+ (fma:ANYF -+ (match_operand:ANYF 1 "register_operand" "f") -+ (match_operand:ANYF 2 "register_operand" "f") -+ (match_operand:ANYF 3 "register_operand" "f")))] -+ "TARGET_HARD_FLOAT" -+ "fmadd.\t%0,%1,%2,%3" -+ [(set_attr "type" "fmadd") -+ (set_attr "mode" "")]) -+ -+(define_insn "fms4" -+ [(set (match_operand:ANYF 0 "register_operand" "=f") -+ (fma:ANYF -+ (match_operand:ANYF 1 "register_operand" "f") -+ (match_operand:ANYF 2 "register_operand" "f") -+ (neg:ANYF (match_operand:ANYF 3 "register_operand" "f"))))] -+ "TARGET_HARD_FLOAT" -+ "fmsub.\t%0,%1,%2,%3" -+ [(set_attr "type" "fmadd") -+ (set_attr "mode" "")]) -+ -+(define_insn "nfma4" -+ [(set (match_operand:ANYF 0 "register_operand" "=f") -+ (neg:ANYF -+ (fma:ANYF -+ (match_operand:ANYF 1 "register_operand" "f") -+ (match_operand:ANYF 2 "register_operand" "f") -+ (match_operand:ANYF 3 "register_operand" "f"))))] -+ "TARGET_HARD_FLOAT" -+ "fnmadd.\t%0,%1,%2,%3" -+ [(set_attr "type" "fmadd") -+ (set_attr "mode" "")]) -+ -+(define_insn "nfms4" -+ [(set (match_operand:ANYF 0 "register_operand" "=f") -+ (neg:ANYF -+ (fma:ANYF -+ (match_operand:ANYF 1 "register_operand" "f") -+ (match_operand:ANYF 2 "register_operand" "f") -+ (neg:ANYF (match_operand:ANYF 3 "register_operand" "f")))))] -+ "TARGET_HARD_FLOAT" -+ "fnmsub.\t%0,%1,%2,%3" -+ [(set_attr "type" "fmadd") -+ (set_attr "mode" "")]) -+ -+;; modulo signed zeros, -(a*b+c) == -c-a*b -+(define_insn "*nfma4_fastmath" -+ [(set (match_operand:ANYF 0 "register_operand" "=f") -+ (minus:ANYF -+ (match_operand:ANYF 3 "register_operand" "f") -+ (mult:ANYF -+ (neg:ANYF (match_operand:ANYF 1 "register_operand" "f")) -+ (match_operand:ANYF 2 "register_operand" "f"))))] -+ "TARGET_HARD_FLOAT && !HONOR_SIGNED_ZEROS (mode)" -+ "fnmadd.\t%0,%1,%2,%3" -+ [(set_attr "type" "fmadd") -+ (set_attr "mode" "")]) -+ -+;; modulo signed zeros, -(a*b-c) == c-a*b -+(define_insn "*nfms4_fastmath" -+ [(set (match_operand:ANYF 0 "register_operand" "=f") -+ (minus:ANYF -+ (match_operand:ANYF 3 "register_operand" "f") -+ (mult:ANYF -+ (match_operand:ANYF 1 "register_operand" "f") -+ (match_operand:ANYF 2 "register_operand" "f"))))] -+ "TARGET_HARD_FLOAT && !HONOR_SIGNED_ZEROS (mode)" -+ "fnmsub.\t%0,%1,%2,%3" -+ [(set_attr "type" "fmadd") -+ (set_attr "mode" "")]) -+ -+;; -+;; .................... -+;; -+;; ABSOLUTE VALUE -+;; -+;; .................... -+ -+(define_insn "abs2" -+ [(set (match_operand:ANYF 0 "register_operand" "=f") -+ (abs:ANYF (match_operand:ANYF 1 "register_operand" "f")))] -+ "TARGET_HARD_FLOAT" -+ "fabs.\t%0,%1" -+ [(set_attr "type" "fmove") -+ (set_attr "mode" "")]) -+ -+ -+;; -+;; .................... -+;; -+;; MIN/MAX -+;; -+;; .................... -+ -+(define_insn "smin3" -+ [(set (match_operand:ANYF 0 "register_operand" "=f") -+ (smin:ANYF (match_operand:ANYF 1 "register_operand" "f") -+ (match_operand:ANYF 2 "register_operand" "f")))] -+ "TARGET_HARD_FLOAT" -+ "fmin.\t%0,%1,%2" -+ [(set_attr "type" "fmove") -+ (set_attr "mode" "")]) -+ -+(define_insn "smax3" -+ [(set (match_operand:ANYF 0 "register_operand" "=f") -+ (smax:ANYF (match_operand:ANYF 1 "register_operand" "f") -+ (match_operand:ANYF 2 "register_operand" "f")))] -+ "TARGET_HARD_FLOAT" -+ "fmax.\t%0,%1,%2" -+ [(set_attr "type" "fmove") -+ (set_attr "mode" "")]) -+ -+ -+;; -+;; .................... -+;; -+;; NEGATION and ONE'S COMPLEMENT ' -+;; -+;; .................... -+ -+(define_insn "neg2" -+ [(set (match_operand:ANYF 0 "register_operand" "=f") -+ (neg:ANYF (match_operand:ANYF 1 "register_operand" "f")))] -+ "TARGET_HARD_FLOAT" -+ "fneg.\t%0,%1" -+ [(set_attr "type" "fmove") -+ (set_attr "mode" "")]) -+ -+(define_insn "one_cmpl2" -+ [(set (match_operand:GPR 0 "register_operand" "=r") -+ (not:GPR (match_operand:GPR 1 "register_operand" "r")))] -+ "" -+ "not\t%0,%1" -+ [(set_attr "type" "logical") -+ (set_attr "mode" "")]) -+ -+;; -+;; .................... -+;; -+;; LOGICAL -+;; -+;; .................... -+;; -+ -+(define_insn "and3" -+ [(set (match_operand:GPR 0 "register_operand" "=r,r") -+ (and:GPR (match_operand:GPR 1 "register_operand" "%r,r") -+ (match_operand:GPR 2 "arith_operand" "r,Q")))] -+ "" -+ "and\t%0,%1,%2" -+ [(set_attr "type" "logical") -+ (set_attr "mode" "")]) -+ -+(define_insn "ior3" -+ [(set (match_operand:GPR 0 "register_operand" "=r,r") -+ (ior:GPR (match_operand:GPR 1 "register_operand" "%r,r") -+ (match_operand:GPR 2 "arith_operand" "r,Q")))] -+ "" -+ "or\t%0,%1,%2" -+ [(set_attr "type" "logical") -+ (set_attr "mode" "")]) -+ -+;; this is used for generating HImode constants. -+(define_insn "iorhi3" -+ [(set (match_operand:HI 0 "register_operand" "=r,r") -+ (ior:HI (match_operand:HI 1 "register_operand" "%r,r") -+ (match_operand:HI 2 "arith_operand" "r,Q")))] -+ "" -+ "or\t%0,%1,%2" -+ [(set_attr "type" "logical") -+ (set_attr "mode" "HI")]) -+ -+(define_insn "xor3" -+ [(set (match_operand:GPR 0 "register_operand" "=r,r") -+ (xor:GPR (match_operand:GPR 1 "register_operand" "%r,r") -+ (match_operand:GPR 2 "arith_operand" "r,Q")))] -+ "" -+ "xor\t%0,%1,%2" -+ [(set_attr "type" "logical") -+ (set_attr "mode" "")]) -+ -+;; -+;; .................... -+;; -+;; TRUNCATION -+;; -+;; .................... -+ -+(define_insn "truncdfsf2" -+ [(set (match_operand:SF 0 "register_operand" "=f") -+ (float_truncate:SF (match_operand:DF 1 "register_operand" "f")))] -+ "TARGET_HARD_FLOAT" -+ "fcvt.s.d\t%0,%1" -+ [(set_attr "type" "fcvt") -+ (set_attr "cnv_mode" "D2S") -+ (set_attr "mode" "SF")]) -+ -+;; Integer truncation patterns. Truncating to HImode/QImode is a no-op. -+;; Truncating from DImode to SImode is not, because we always keep SImode -+;; values sign-extended in a register so we can safely use DImode branches -+;; and comparisons on SImode values. -+ -+(define_insn "truncdisi2" -+ [(set (match_operand:SI 0 "nonimmediate_operand" "=r,m") -+ (truncate:SI (match_operand:DI 1 "register_operand" "r,r")))] -+ "TARGET_64BIT" -+ "@ -+ sext.w\t%0,%1 -+ sw\t%1,%0" -+ [(set_attr "move_type" "arith,store") -+ (set_attr "mode" "SI")]) -+ -+;; Combiner patterns to optimize shift/truncate combinations. -+ -+(define_insn "*ashr_trunc" -+ [(set (match_operand:SUBDI 0 "register_operand" "=r") -+ (truncate:SUBDI -+ (ashiftrt:DI (match_operand:DI 1 "register_operand" "r") -+ (match_operand:DI 2 "const_arith_operand" ""))))] -+ "TARGET_64BIT && IN_RANGE (INTVAL (operands[2]), 32, 63)" -+ "sra\t%0,%1,%2" -+ [(set_attr "type" "shift") -+ (set_attr "mode" "")]) -+ -+(define_insn "*lshr32_trunc" -+ [(set (match_operand:SUBDI 0 "register_operand" "=r") -+ (truncate:SUBDI -+ (lshiftrt:DI (match_operand:DI 1 "register_operand" "r") -+ (const_int 32))))] -+ "TARGET_64BIT" -+ "sra\t%0,%1,32" -+ [(set_attr "type" "shift") -+ (set_attr "mode" "")]) -+ -+;; -+;; .................... -+;; -+;; ZERO EXTENSION -+;; -+;; .................... -+ -+;; Extension insns. -+ -+(define_insn_and_split "zero_extendsidi2" -+ [(set (match_operand:DI 0 "register_operand" "=r,r") -+ (zero_extend:DI (match_operand:SI 1 "nonimmediate_operand" "r,W")))] -+ "TARGET_64BIT" -+ "@ -+ # -+ lwu\t%0,%1" -+ "&& reload_completed && REG_P (operands[1])" -+ [(set (match_dup 0) -+ (ashift:DI (match_dup 1) (const_int 32))) -+ (set (match_dup 0) -+ (lshiftrt:DI (match_dup 0) (const_int 32)))] -+ { operands[1] = gen_lowpart (DImode, operands[1]); } -+ [(set_attr "move_type" "shift_shift,load") -+ (set_attr "mode" "DI")]) -+ -+;; Combine is not allowed to convert this insn into a zero_extendsidi2 -+;; because of TRULY_NOOP_TRUNCATION. -+ -+(define_insn_and_split "*clear_upper32" -+ [(set (match_operand:DI 0 "register_operand" "=r,r") -+ (and:DI (match_operand:DI 1 "nonimmediate_operand" "r,W") -+ (const_int 4294967295)))] -+ "TARGET_64BIT" -+{ -+ if (which_alternative == 0) -+ return "#"; -+ -+ operands[1] = gen_lowpart (SImode, operands[1]); -+ return "lwu\t%0,%1"; -+} -+ "&& reload_completed && REG_P (operands[1])" -+ [(set (match_dup 0) -+ (ashift:DI (match_dup 1) (const_int 32))) -+ (set (match_dup 0) -+ (lshiftrt:DI (match_dup 0) (const_int 32)))] -+ "" -+ [(set_attr "move_type" "shift_shift,load") -+ (set_attr "mode" "DI")]) -+ -+(define_insn_and_split "zero_extendhi2" -+ [(set (match_operand:GPR 0 "register_operand" "=r,r") -+ (zero_extend:GPR (match_operand:HI 1 "nonimmediate_operand" "r,m")))] -+ "" -+ "@ -+ # -+ lhu\t%0,%1" -+ "&& reload_completed && REG_P (operands[1])" -+ [(set (match_dup 0) -+ (ashift:GPR (match_dup 1) (match_dup 2))) -+ (set (match_dup 0) -+ (lshiftrt:GPR (match_dup 0) (match_dup 2)))] -+ { -+ operands[1] = gen_lowpart (mode, operands[1]); -+ operands[2] = GEN_INT(GET_MODE_BITSIZE(mode) - 16); -+ } -+ [(set_attr "move_type" "shift_shift,load") -+ (set_attr "mode" "")]) -+ -+(define_insn "zero_extendqi2" -+ [(set (match_operand:SUPERQI 0 "register_operand" "=r,r") -+ (zero_extend:SUPERQI -+ (match_operand:QI 1 "nonimmediate_operand" "r,m")))] -+ "" -+ "@ -+ and\t%0,%1,0xff -+ lbu\t%0,%1" -+ [(set_attr "move_type" "andi,load") -+ (set_attr "mode" "")]) -+ -+;; -+;; .................... -+;; -+;; SIGN EXTENSION -+;; -+;; .................... -+ -+;; Extension insns. -+;; Those for integer source operand are ordered widest source type first. -+ -+;; When TARGET_64BIT, all SImode integer registers should already be in -+;; sign-extended form (see TRULY_NOOP_TRUNCATION and truncdisi2). We can -+;; therefore get rid of register->register instructions if we constrain -+;; the source to be in the same register as the destination. -+;; -+;; The register alternative has type "arith" so that the pre-reload -+;; scheduler will treat it as a move. This reflects what happens if -+;; the register alternative needs a reload. -+(define_insn_and_split "extendsidi2" -+ [(set (match_operand:DI 0 "register_operand" "=r,r") -+ (sign_extend:DI (match_operand:SI 1 "nonimmediate_operand" "0,m")))] -+ "TARGET_64BIT" -+ "@ -+ # -+ lw\t%0,%1" -+ "&& reload_completed && register_operand (operands[1], VOIDmode)" -+ [(const_int 0)] -+{ -+ emit_note (NOTE_INSN_DELETED); -+ DONE; -+} -+ [(set_attr "move_type" "move,load") -+ (set_attr "mode" "DI")]) -+ -+(define_insn_and_split "extend2" -+ [(set (match_operand:SUPERQI 0 "register_operand" "=r,r") -+ (sign_extend:SUPERQI -+ (match_operand:SHORT 1 "nonimmediate_operand" "r,m")))] -+ "" -+ "@ -+ # -+ l\t%0,%1" -+ "&& reload_completed && REG_P (operands[1])" -+ [(set (match_dup 0) (ashift:SI (match_dup 1) (match_dup 2))) -+ (set (match_dup 0) (ashiftrt:SI (match_dup 0) (match_dup 2)))] -+{ -+ operands[0] = gen_lowpart (SImode, operands[0]); -+ operands[1] = gen_lowpart (SImode, operands[1]); -+ operands[2] = GEN_INT (GET_MODE_BITSIZE (SImode) -+ - GET_MODE_BITSIZE (mode)); -+} -+ [(set_attr "move_type" "shift_shift,load") -+ (set_attr "mode" "SI")]) -+ -+(define_insn "extendsfdf2" -+ [(set (match_operand:DF 0 "register_operand" "=f") -+ (float_extend:DF (match_operand:SF 1 "register_operand" "f")))] -+ "TARGET_HARD_FLOAT" -+ "fcvt.d.s\t%0,%1" -+ [(set_attr "type" "fcvt") -+ (set_attr "cnv_mode" "S2D") -+ (set_attr "mode" "DF")]) -+ -+;; -+;; .................... -+;; -+;; CONVERSIONS -+;; -+;; .................... -+ -+(define_insn "fix_truncdfsi2" -+ [(set (match_operand:SI 0 "register_operand" "=r") -+ (fix:SI (match_operand:DF 1 "register_operand" "f")))] -+ "TARGET_HARD_FLOAT" -+ "fcvt.w.d %0,%1,rtz" -+ [(set_attr "type" "fcvt") -+ (set_attr "mode" "DF") -+ (set_attr "cnv_mode" "D2I")]) -+ -+ -+(define_insn "fix_truncsfsi2" -+ [(set (match_operand:SI 0 "register_operand" "=r") -+ (fix:SI (match_operand:SF 1 "register_operand" "f")))] -+ "TARGET_HARD_FLOAT" -+ "fcvt.w.s %0,%1,rtz" -+ [(set_attr "type" "fcvt") -+ (set_attr "mode" "SF") -+ (set_attr "cnv_mode" "S2I")]) -+ -+ -+(define_insn "fix_truncdfdi2" -+ [(set (match_operand:DI 0 "register_operand" "=r") -+ (fix:DI (match_operand:DF 1 "register_operand" "f")))] -+ "TARGET_HARD_FLOAT && TARGET_64BIT" -+ "fcvt.l.d %0,%1,rtz" -+ [(set_attr "type" "fcvt") -+ (set_attr "mode" "DF") -+ (set_attr "cnv_mode" "D2I")]) -+ -+ -+(define_insn "fix_truncsfdi2" -+ [(set (match_operand:DI 0 "register_operand" "=r") -+ (fix:DI (match_operand:SF 1 "register_operand" "f")))] -+ "TARGET_HARD_FLOAT && TARGET_64BIT" -+ "fcvt.l.s %0,%1,rtz" -+ [(set_attr "type" "fcvt") -+ (set_attr "mode" "SF") -+ (set_attr "cnv_mode" "S2I")]) -+ -+ -+(define_insn "floatsidf2" -+ [(set (match_operand:DF 0 "register_operand" "=f") -+ (float:DF (match_operand:SI 1 "reg_or_0_operand" "rJ")))] -+ "TARGET_HARD_FLOAT" -+ "fcvt.d.w\t%0,%z1" -+ [(set_attr "type" "fcvt") -+ (set_attr "mode" "DF") -+ (set_attr "cnv_mode" "I2D")]) -+ -+ -+(define_insn "floatdidf2" -+ [(set (match_operand:DF 0 "register_operand" "=f") -+ (float:DF (match_operand:DI 1 "reg_or_0_operand" "rJ")))] -+ "TARGET_HARD_FLOAT && TARGET_64BIT" -+ "fcvt.d.l\t%0,%z1" -+ [(set_attr "type" "fcvt") -+ (set_attr "mode" "DF") -+ (set_attr "cnv_mode" "I2D")]) -+ -+ -+(define_insn "floatsisf2" -+ [(set (match_operand:SF 0 "register_operand" "=f") -+ (float:SF (match_operand:SI 1 "reg_or_0_operand" "rJ")))] -+ "TARGET_HARD_FLOAT" -+ "fcvt.s.w\t%0,%z1" -+ [(set_attr "type" "fcvt") -+ (set_attr "mode" "SF") -+ (set_attr "cnv_mode" "I2S")]) -+ -+ -+(define_insn "floatdisf2" -+ [(set (match_operand:SF 0 "register_operand" "=f") -+ (float:SF (match_operand:DI 1 "reg_or_0_operand" "rJ")))] -+ "TARGET_HARD_FLOAT && TARGET_64BIT" -+ "fcvt.s.l\t%0,%z1" -+ [(set_attr "type" "fcvt") -+ (set_attr "mode" "SF") -+ (set_attr "cnv_mode" "I2S")]) -+ -+ -+(define_insn "floatunssidf2" -+ [(set (match_operand:DF 0 "register_operand" "=f") -+ (unsigned_float:DF (match_operand:SI 1 "reg_or_0_operand" "rJ")))] -+ "TARGET_HARD_FLOAT" -+ "fcvt.d.wu\t%0,%z1" -+ [(set_attr "type" "fcvt") -+ (set_attr "mode" "DF") -+ (set_attr "cnv_mode" "I2D")]) -+ -+ -+(define_insn "floatunsdidf2" -+ [(set (match_operand:DF 0 "register_operand" "=f") -+ (unsigned_float:DF (match_operand:DI 1 "reg_or_0_operand" "rJ")))] -+ "TARGET_HARD_FLOAT && TARGET_64BIT" -+ "fcvt.d.lu\t%0,%z1" -+ [(set_attr "type" "fcvt") -+ (set_attr "mode" "DF") -+ (set_attr "cnv_mode" "I2D")]) -+ -+ -+(define_insn "floatunssisf2" -+ [(set (match_operand:SF 0 "register_operand" "=f") -+ (unsigned_float:SF (match_operand:SI 1 "reg_or_0_operand" "rJ")))] -+ "TARGET_HARD_FLOAT" -+ "fcvt.s.wu\t%0,%z1" -+ [(set_attr "type" "fcvt") -+ (set_attr "mode" "SF") -+ (set_attr "cnv_mode" "I2S")]) -+ -+ -+(define_insn "floatunsdisf2" -+ [(set (match_operand:SF 0 "register_operand" "=f") -+ (unsigned_float:SF (match_operand:DI 1 "reg_or_0_operand" "rJ")))] -+ "TARGET_HARD_FLOAT && TARGET_64BIT" -+ "fcvt.s.lu\t%0,%z1" -+ [(set_attr "type" "fcvt") -+ (set_attr "mode" "SF") -+ (set_attr "cnv_mode" "I2S")]) -+ -+ -+(define_insn "fixuns_truncdfsi2" -+ [(set (match_operand:SI 0 "register_operand" "=r") -+ (unsigned_fix:SI (match_operand:DF 1 "register_operand" "f")))] -+ "TARGET_HARD_FLOAT" -+ "fcvt.wu.d %0,%1,rtz" -+ [(set_attr "type" "fcvt") -+ (set_attr "mode" "DF") -+ (set_attr "cnv_mode" "D2I")]) -+ -+ -+(define_insn "fixuns_truncsfsi2" -+ [(set (match_operand:SI 0 "register_operand" "=r") -+ (unsigned_fix:SI (match_operand:SF 1 "register_operand" "f")))] -+ "TARGET_HARD_FLOAT" -+ "fcvt.wu.s %0,%1,rtz" -+ [(set_attr "type" "fcvt") -+ (set_attr "mode" "SF") -+ (set_attr "cnv_mode" "S2I")]) -+ -+ -+(define_insn "fixuns_truncdfdi2" -+ [(set (match_operand:DI 0 "register_operand" "=r") -+ (unsigned_fix:DI (match_operand:DF 1 "register_operand" "f")))] -+ "TARGET_HARD_FLOAT && TARGET_64BIT" -+ "fcvt.lu.d %0,%1,rtz" -+ [(set_attr "type" "fcvt") -+ (set_attr "mode" "DF") -+ (set_attr "cnv_mode" "D2I")]) -+ -+ -+(define_insn "fixuns_truncsfdi2" -+ [(set (match_operand:DI 0 "register_operand" "=r") -+ (unsigned_fix:DI (match_operand:SF 1 "register_operand" "f")))] -+ "TARGET_HARD_FLOAT && TARGET_64BIT" -+ "fcvt.lu.s %0,%1,rtz" -+ [(set_attr "type" "fcvt") -+ (set_attr "mode" "SF") -+ (set_attr "cnv_mode" "S2I")]) -+ -+;; -+;; .................... -+;; -+;; DATA MOVEMENT -+;; -+;; .................... -+ -+;; Lower-level instructions for loading an address from the GOT. -+;; We could use MEMs, but an unspec gives more optimization -+;; opportunities. -+ -+(define_insn "got_load" -+ [(set (match_operand:P 0 "register_operand" "=r") -+ (unspec:P [(match_operand:P 1 "symbolic_operand" "")] -+ UNSPEC_LOAD_GOT))] -+ "flag_pic" -+ "la\t%0,%1" -+ [(set_attr "got" "load") -+ (set_attr "mode" "")]) -+ -+(define_insn "tls_add_tp_le" -+ [(set (match_operand:P 0 "register_operand" "=r") -+ (unspec:P [(match_operand:P 1 "register_operand" "r") -+ (match_operand:P 2 "register_operand" "r") -+ (match_operand:P 3 "symbolic_operand" "")] -+ UNSPEC_TLS_LE_ADD))] -+ "!flag_pic" -+ "add\t%0,%1,%2,%%tprel_add(%3)" -+ [(set_attr "type" "arith") -+ (set_attr "mode" "")]) -+ -+(define_insn "tls_add_tp_ie" -+ [(set (match_operand:P 0 "register_operand" "=r") -+ (unspec:P [(match_operand:P 1 "register_operand" "r") -+ (match_operand:P 2 "register_operand" "r") -+ (match_operand:P 3 "symbolic_operand" "")] -+ UNSPEC_TLS_IE_ADD))] -+ "!flag_pic" -+ "add\t%0,%1,%2,%%tls_ie_add(%3)" -+ [(set_attr "type" "arith") -+ (set_attr "mode" "")]) -+ -+(define_insn "got_load_tls_gd" -+ [(set (match_operand:P 0 "register_operand" "=r") -+ (unspec:P [(match_operand:P 1 "symbolic_operand" "")] -+ UNSPEC_TLS_GD))] -+ "flag_pic" -+ "la.tls.gd\t%0,%1" -+ [(set_attr "got" "load") -+ (set_attr "mode" "")]) -+ -+(define_insn "got_load_tls_ie" -+ [(set (match_operand:P 0 "register_operand" "=r") -+ (unspec:P [(match_operand:P 1 "symbolic_operand" "")] -+ UNSPEC_TLS_IE))] -+ "flag_pic" -+ "la.tls.ie\t%0,%1" -+ [(set_attr "got" "load") -+ (set_attr "mode" "")]) -+ -+(define_insn "got_load_tls_ie_hi" -+ [(set (match_operand:P 0 "register_operand" "=r") -+ (unspec:P [(match_operand:P 1 "symbolic_operand" "")] -+ UNSPEC_TLS_IE_HI))] -+ "!flag_pic" -+ "lui\t%0,%%tls_ie_hi(%1)" -+ [(set_attr "type" "arith") -+ (set_attr "mode" "")]) -+ -+(define_insn "got_load_tls_ie_lo" -+ [(set (match_operand:P 0 "register_operand" "=r") -+ (unspec:P [(match_operand:P 1 "register_operand" "r") -+ (match_operand:P 2 "symbolic_operand" "")] -+ UNSPEC_TLS_IE_LO))] -+ "!flag_pic" -+ "\t%0,%%tls_ie_lo(%2)(%1)" -+ [(set_attr "type" "load") -+ (set_attr "mode" "")]) -+ -+;; Instructions for adding the low 16 bits of an address to a register. -+;; Operand 2 is the address: mips_print_operand works out which relocation -+;; should be applied. -+ -+(define_insn "*low" -+ [(set (match_operand:P 0 "register_operand" "=r") -+ (lo_sum:P (match_operand:P 1 "register_operand" "r") -+ (match_operand:P 2 "immediate_operand" "")))] -+ "" -+ "add\t%0,%1,%R2" -+ [(set_attr "alu_type" "add") -+ (set_attr "mode" "")]) -+ -+;; Allow combine to split complex const_int load sequences, using operand 2 -+;; to store the intermediate results. See move_operand for details. -+(define_split -+ [(set (match_operand:GPR 0 "register_operand") -+ (match_operand:GPR 1 "splittable_const_int_operand")) -+ (clobber (match_operand:GPR 2 "register_operand"))] -+ "" -+ [(const_int 0)] -+{ -+ mips_move_integer (operands[2], operands[0], INTVAL (operands[1])); -+ DONE; -+}) -+ -+;; Likewise, for symbolic operands. -+(define_split -+ [(set (match_operand:P 0 "register_operand") -+ (match_operand:P 1)) -+ (clobber (match_operand:P 2 "register_operand"))] -+ "mips_split_symbol (operands[2], operands[1], MAX_MACHINE_MODE, NULL)" -+ [(set (match_dup 0) (match_dup 3))] -+{ -+ mips_split_symbol (operands[2], operands[1], -+ MAX_MACHINE_MODE, &operands[3]); -+}) -+ -+;; 64-bit integer moves -+ -+;; Unlike most other insns, the move insns can't be split with ' -+;; different predicates, because register spilling and other parts of -+;; the compiler, have memoized the insn number already. -+ -+(define_expand "movdi" -+ [(set (match_operand:DI 0 "") -+ (match_operand:DI 1 ""))] -+ "" -+{ -+ if (mips_legitimize_move (DImode, operands[0], operands[1])) -+ DONE; -+}) -+ -+(define_insn "*movdi_32bit" -+ [(set (match_operand:DI 0 "nonimmediate_operand" "=r,r,r,m,*f,*f,*r,*m") -+ (match_operand:DI 1 "move_operand" "r,i,m,r,*J*r,*m,*f,*f"))] -+ "!TARGET_64BIT -+ && (register_operand (operands[0], DImode) -+ || reg_or_0_operand (operands[1], DImode))" -+ { return mips_output_move (operands[0], operands[1]); } -+ [(set_attr "move_type" "move,const,load,store,mtc,fpload,mfc,fpstore") -+ (set_attr "mode" "DI")]) -+ -+(define_insn "*movdi_64bit" -+ [(set (match_operand:DI 0 "nonimmediate_operand" "=r,r,r,m,*f,*f,*r,*m") -+ (match_operand:DI 1 "move_operand" "r,T,m,rJ,*r*J,*m,*f,*f"))] -+ "TARGET_64BIT -+ && (register_operand (operands[0], DImode) -+ || reg_or_0_operand (operands[1], DImode))" -+ { return mips_output_move (operands[0], operands[1]); } -+ [(set_attr "move_type" "move,const,load,store,mtc,fpload,mfc,fpstore") -+ (set_attr "mode" "DI")]) -+ -+;; 32-bit Integer moves -+ -+;; Unlike most other insns, the move insns can't be split with -+;; different predicates, because register spilling and other parts of -+;; the compiler, have memoized the insn number already. -+ -+(define_expand "mov" -+ [(set (match_operand:IMOVE32 0 "") -+ (match_operand:IMOVE32 1 ""))] -+ "" -+{ -+ if (mips_legitimize_move (mode, operands[0], operands[1])) -+ DONE; -+}) -+ -+;; The difference between these two is whether or not ints are allowed -+;; in FP registers (off by default, use -mdebugh to enable). -+ -+(define_insn "*mov_internal" -+ [(set (match_operand:IMOVE32 0 "nonimmediate_operand" "=r,r,r,m,*f,*f,*r,*m") -+ (match_operand:IMOVE32 1 "move_operand" "r,T,m,rJ,*r*J,*m,*f,*f"))] -+ "(register_operand (operands[0], mode) -+ || reg_or_0_operand (operands[1], mode))" -+ { return mips_output_move (operands[0], operands[1]); } -+ [(set_attr "move_type" "move,const,load,store,mtc,fpload,mfc,fpstore") -+ (set_attr "mode" "SI")]) -+ -+;; 16-bit Integer moves -+ -+;; Unlike most other insns, the move insns can't be split with -+;; different predicates, because register spilling and other parts of -+;; the compiler, have memoized the insn number already. -+;; Unsigned loads are used because LOAD_EXTEND_OP returns ZERO_EXTEND. -+ -+(define_expand "movhi" -+ [(set (match_operand:HI 0 "") -+ (match_operand:HI 1 ""))] -+ "" -+{ -+ if (mips_legitimize_move (HImode, operands[0], operands[1])) -+ DONE; -+}) -+ -+(define_insn "*movhi_internal" -+ [(set (match_operand:HI 0 "nonimmediate_operand" "=r,r,r,m") -+ (match_operand:HI 1 "move_operand" "r,T,m,rJ"))] -+ "(register_operand (operands[0], HImode) -+ || reg_or_0_operand (operands[1], HImode))" -+ { return mips_output_move (operands[0], operands[1]); } -+ [(set_attr "move_type" "move,const,load,store") -+ (set_attr "mode" "HI")]) -+ -+;; 8-bit Integer moves -+ -+(define_expand "movqi" -+ [(set (match_operand:QI 0 "") -+ (match_operand:QI 1 ""))] -+ "" -+{ -+ if (mips_legitimize_move (QImode, operands[0], operands[1])) -+ DONE; -+}) -+ -+(define_insn "*movqi_internal" -+ [(set (match_operand:QI 0 "nonimmediate_operand" "=r,r,r,m") -+ (match_operand:QI 1 "move_operand" "r,I,m,rJ"))] -+ "(register_operand (operands[0], QImode) -+ || reg_or_0_operand (operands[1], QImode))" -+ { return mips_output_move (operands[0], operands[1]); } -+ [(set_attr "move_type" "move,const,load,store") -+ (set_attr "mode" "QI")]) -+ -+;; 32-bit floating point moves -+ -+(define_expand "movsf" -+ [(set (match_operand:SF 0 "") -+ (match_operand:SF 1 ""))] -+ "" -+{ -+ if (mips_legitimize_move (SFmode, operands[0], operands[1])) -+ DONE; -+}) -+ -+(define_insn "*movsf_hardfloat" -+ [(set (match_operand:SF 0 "nonimmediate_operand" "=f,f,f,m,m,*f,*r,*r,*r,*m") -+ (match_operand:SF 1 "move_operand" "f,G,m,f,G,*r,*f,*G*r,*m,*r"))] -+ "TARGET_HARD_FLOAT -+ && (register_operand (operands[0], SFmode) -+ || reg_or_0_operand (operands[1], SFmode))" -+ { return mips_output_move (operands[0], operands[1]); } -+ [(set_attr "move_type" "fmove,mtc,fpload,fpstore,store,mtc,mfc,move,load,store") -+ (set_attr "mode" "SF")]) -+ -+(define_insn "*movsf_softfloat" -+ [(set (match_operand:SF 0 "nonimmediate_operand" "=r,r,m") -+ (match_operand:SF 1 "move_operand" "Gr,m,r"))] -+ "TARGET_SOFT_FLOAT -+ && (register_operand (operands[0], SFmode) -+ || reg_or_0_operand (operands[1], SFmode))" -+ { return mips_output_move (operands[0], operands[1]); } -+ [(set_attr "move_type" "move,load,store") -+ (set_attr "mode" "SF")]) -+ -+;; 64-bit floating point moves -+ -+(define_expand "movdf" -+ [(set (match_operand:DF 0 "") -+ (match_operand:DF 1 ""))] -+ "" -+{ -+ if (mips_legitimize_move (DFmode, operands[0], operands[1])) -+ DONE; -+}) -+ -+;; In RV32, we lack mtf.d/mff.d. Go through memory instead. -+;; (except for moving a constant 0 to an FPR. for that we use fcvt.d.w.) -+(define_insn "*movdf_hardfloat_rv32" -+ [(set (match_operand:DF 0 "nonimmediate_operand" "=f,f,f,m,m,*r,*r,*m") -+ (match_operand:DF 1 "move_operand" "f,G,m,f,G,*r*G,*m,*r"))] -+ "!TARGET_64BIT && TARGET_HARD_FLOAT -+ && (register_operand (operands[0], DFmode) -+ || reg_or_0_operand (operands[1], DFmode))" -+ { return mips_output_move (operands[0], operands[1]); } -+ [(set_attr "move_type" "fmove,mtc,fpload,fpstore,store,move,load,store") -+ (set_attr "mode" "DF")]) -+ -+(define_insn "*movdf_hardfloat_rv64" -+ [(set (match_operand:DF 0 "nonimmediate_operand" "=f,f,f,m,m,*f,*r,*r,*r,*m") -+ (match_operand:DF 1 "move_operand" "f,G,m,f,G,*r,*f,*r*G,*m,*r"))] -+ "TARGET_64BIT && TARGET_HARD_FLOAT -+ && (register_operand (operands[0], DFmode) -+ || reg_or_0_operand (operands[1], DFmode))" -+ { return mips_output_move (operands[0], operands[1]); } -+ [(set_attr "move_type" "fmove,mtc,fpload,fpstore,store,mtc,mfc,move,load,store") -+ (set_attr "mode" "DF")]) -+ -+(define_insn "*movdf_softfloat" -+ [(set (match_operand:DF 0 "nonimmediate_operand" "=r,r,m") -+ (match_operand:DF 1 "move_operand" "rG,m,rG"))] -+ "TARGET_SOFT_FLOAT -+ && (register_operand (operands[0], DFmode) -+ || reg_or_0_operand (operands[1], DFmode))" -+ { return mips_output_move (operands[0], operands[1]); } -+ [(set_attr "move_type" "move,load,store") -+ (set_attr "mode" "DF")]) -+ -+;; 128-bit integer moves -+ -+(define_expand "movti" -+ [(set (match_operand:TI 0) -+ (match_operand:TI 1))] -+ "TARGET_64BIT" -+{ -+ if (mips_legitimize_move (TImode, operands[0], operands[1])) -+ DONE; -+}) -+ -+(define_insn "*movti" -+ [(set (match_operand:TI 0 "nonimmediate_operand" "=r,r,r,m") -+ (match_operand:TI 1 "move_operand" "r,i,m,rJ"))] -+ "TARGET_64BIT -+ && (register_operand (operands[0], TImode) -+ || reg_or_0_operand (operands[1], TImode))" -+ "#" -+ [(set_attr "move_type" "move,const,load,store") -+ (set_attr "mode" "TI")]) -+ -+(define_split -+ [(set (match_operand:MOVE64 0 "nonimmediate_operand") -+ (match_operand:MOVE64 1 "move_operand"))] -+ "reload_completed && !TARGET_64BIT -+ && mips_split_64bit_move_p (operands[0], operands[1])" -+ [(const_int 0)] -+{ -+ mips_split_doubleword_move (operands[0], operands[1]); -+ DONE; -+}) -+ -+(define_split -+ [(set (match_operand:MOVE128 0 "nonimmediate_operand") -+ (match_operand:MOVE128 1 "move_operand"))] -+ "TARGET_64BIT && reload_completed" -+ [(const_int 0)] -+{ -+ mips_split_doubleword_move (operands[0], operands[1]); -+ DONE; -+}) -+ -+;; 64-bit paired-single floating point moves -+ -+;; Load the low word of operand 0 with operand 1. -+(define_insn "load_low" -+ [(set (match_operand:SPLITF 0 "register_operand" "=f,f") -+ (unspec:SPLITF [(match_operand: 1 "general_operand" "rJ,m")] -+ UNSPEC_LOAD_LOW))] -+ "TARGET_HARD_FLOAT" -+{ -+ operands[0] = mips_subword (operands[0], 0); -+ return mips_output_move (operands[0], operands[1]); -+} -+ [(set_attr "move_type" "mtc,fpload") -+ (set_attr "mode" "")]) -+ -+;; Load the high word of operand 0 from operand 1, preserving the value -+;; in the low word. -+(define_insn "load_high" -+ [(set (match_operand:SPLITF 0 "register_operand" "=f,f") -+ (unspec:SPLITF [(match_operand: 1 "general_operand" "rJ,m") -+ (match_operand:SPLITF 2 "register_operand" "0,0")] -+ UNSPEC_LOAD_HIGH))] -+ "TARGET_HARD_FLOAT" -+{ -+ operands[0] = mips_subword (operands[0], 1); -+ return mips_output_move (operands[0], operands[1]); -+} -+ [(set_attr "move_type" "mtc,fpload") -+ (set_attr "mode" "")]) -+ -+;; Store one word of operand 1 in operand 0. Operand 2 is 1 to store the -+;; high word and 0 to store the low word. -+(define_insn "store_word" -+ [(set (match_operand: 0 "nonimmediate_operand" "=r,m") -+ (unspec: [(match_operand:SPLITF 1 "register_operand" "f,f") -+ (match_operand 2 "const_int_operand")] -+ UNSPEC_STORE_WORD))] -+ "TARGET_HARD_FLOAT" -+{ -+ operands[1] = mips_subword (operands[1], INTVAL (operands[2])); -+ return mips_output_move (operands[0], operands[1]); -+} -+ [(set_attr "move_type" "mfc,fpstore") -+ (set_attr "mode" "")]) -+ -+;; Expand in-line code to clear the instruction cache between operand[0] and -+;; operand[1]. -+(define_expand "clear_cache" -+ [(match_operand 0 "pmode_register_operand") -+ (match_operand 1 "pmode_register_operand")] -+ "" -+ " -+{ -+ emit_insn(gen_fence_i()); -+ DONE; -+}") -+ -+(define_insn "fence" -+ [(unspec_volatile [(const_int 0)] UNSPEC_FENCE)] -+ "" -+ "%|fence%-") -+ -+(define_insn "fence_i" -+ [(unspec_volatile [(const_int 0)] UNSPEC_FENCE_I)] -+ "" -+ "fence.i") -+ -+;; Block moves, see mips.c for more details. -+;; Argument 0 is the destination -+;; Argument 1 is the source -+;; Argument 2 is the length -+;; Argument 3 is the alignment -+ -+(define_expand "movmemsi" -+ [(parallel [(set (match_operand:BLK 0 "general_operand") -+ (match_operand:BLK 1 "general_operand")) -+ (use (match_operand:SI 2 "")) -+ (use (match_operand:SI 3 "const_int_operand"))])] -+ "!TARGET_MEMCPY" -+{ -+ if (riscv_expand_block_move (operands[0], operands[1], operands[2])) -+ DONE; -+ else -+ FAIL; -+}) -+ -+;; -+;; .................... -+;; -+;; SHIFTS -+;; -+;; .................... -+ -+(define_insn "si3" -+ [(set (match_operand:SI 0 "register_operand" "=r") -+ (any_shift:SI (match_operand:SI 1 "register_operand" "r") -+ (match_operand:SI 2 "arith_operand" "rI")))] -+ "" -+{ -+ if (GET_CODE (operands[2]) == CONST_INT) -+ operands[2] = GEN_INT (INTVAL (operands[2]) -+ & (GET_MODE_BITSIZE (SImode) - 1)); -+ -+ return TARGET_64BIT ? "w\t%0,%1,%2" : "\t%0,%1,%2"; -+} -+ [(set_attr "type" "shift") -+ (set_attr "mode" "SI")]) -+ -+(define_insn "*disi3" -+ [(set (match_operand:SI 0 "register_operand" "=r") -+ (any_shift:SI (truncate:SI (match_operand:DI 1 "register_operand" "r")) -+ (truncate:SI (match_operand:DI 2 "arith_operand" "rI"))))] -+ "TARGET_64BIT" -+ "w\t%0,%1,%2" -+ [(set_attr "type" "shift") -+ (set_attr "mode" "SI")]) -+ -+(define_insn "*ashldi3_truncsi" -+ [(set (match_operand:SI 0 "register_operand" "=r") -+ (truncate:SI -+ (ashift:DI (match_operand:DI 1 "register_operand" "r") -+ (match_operand:DI 2 "arith_operand" "rI"))))] -+ "TARGET_64BIT && (GET_CODE (operands[2]) == CONST_INT ? INTVAL (operands[2]) < 32 : 1)" -+ "sllw\t%0,%1,%2" -+ [(set_attr "type" "shift") -+ (set_attr "mode" "SI")]) -+ -+(define_insn "*ashldisi3" -+ [(set (match_operand:SI 0 "register_operand" "=r") -+ (ashift:SI (match_operand:GPR 1 "register_operand" "r") -+ (match_operand:GPR2 2 "arith_operand" "rI")))] -+ "TARGET_64BIT && (GET_CODE (operands[2]) == CONST_INT ? INTVAL (operands[2]) < 32 : 1)" -+ "sllw\t%0,%1,%2" -+ [(set_attr "type" "shift") -+ (set_attr "mode" "SI")]) -+ -+(define_insn "di3" -+ [(set (match_operand:DI 0 "register_operand" "=r") -+ (any_shift:DI (match_operand:DI 1 "register_operand" "r") -+ (match_operand:DI 2 "arith_operand" "rI")))] -+ "TARGET_64BIT" -+{ -+ if (GET_CODE (operands[2]) == CONST_INT) -+ operands[2] = GEN_INT (INTVAL (operands[2]) -+ & (GET_MODE_BITSIZE (DImode) - 1)); -+ -+ return "\t%0,%1,%2"; -+} -+ [(set_attr "type" "shift") -+ (set_attr "mode" "DI")]) -+ -+(define_insn "si3_extend" -+ [(set (match_operand:DI 0 "register_operand" "=r") -+ (sign_extend:DI -+ (any_shift:SI (match_operand:SI 1 "register_operand" "r") -+ (match_operand:SI 2 "arith_operand" "rI"))))] -+ "TARGET_64BIT" -+{ -+ if (GET_CODE (operands[2]) == CONST_INT) -+ operands[2] = GEN_INT (INTVAL (operands[2]) & 0x1f); -+ -+ return "w\t%0,%1,%2"; -+} -+ [(set_attr "type" "shift") -+ (set_attr "mode" "SI")]) -+ -+;; -+;; .................... -+;; -+;; CONDITIONAL BRANCHES -+;; -+;; .................... -+ -+;; Conditional branches -+ -+(define_insn "*branch_order" -+ [(set (pc) -+ (if_then_else -+ (match_operator 1 "order_operator" -+ [(match_operand:GPR 2 "register_operand" "r") -+ (match_operand:GPR 3 "reg_or_0_operand" "rJ")]) -+ (label_ref (match_operand 0 "" "")) -+ (pc)))] -+ "" -+ "b%C1\t%2,%z3,%0" -+ [(set_attr "type" "branch") -+ (set_attr "mode" "none")]) -+ -+;; Used to implement built-in functions. -+(define_expand "condjump" -+ [(set (pc) -+ (if_then_else (match_operand 0) -+ (label_ref (match_operand 1)) -+ (pc)))]) -+ -+(define_expand "cbranch4" -+ [(set (pc) -+ (if_then_else (match_operator 0 "comparison_operator" -+ [(match_operand:GPR 1 "register_operand") -+ (match_operand:GPR 2 "nonmemory_operand")]) -+ (label_ref (match_operand 3 "")) -+ (pc)))] -+ "" -+{ -+ riscv_expand_conditional_branch (operands); -+ DONE; -+}) -+ -+(define_expand "cbranch4" -+ [(set (pc) -+ (if_then_else (match_operator 0 "comparison_operator" -+ [(match_operand:SCALARF 1 "register_operand") -+ (match_operand:SCALARF 2 "register_operand")]) -+ (label_ref (match_operand 3 "")) -+ (pc)))] -+ "" -+{ -+ riscv_expand_conditional_branch (operands); -+ DONE; -+}) -+ -+;; -+;; .................... -+;; -+;; SETTING A REGISTER FROM A COMPARISON -+;; -+;; .................... -+ -+;; Destination is always set in SI mode. -+ -+(define_expand "cstore4" -+ [(set (match_operand:SI 0 "register_operand") -+ (match_operator:SI 1 "order_operator" -+ [(match_operand:GPR 2 "register_operand") -+ (match_operand:GPR 3 "nonmemory_operand")]))] -+ "" -+{ -+ riscv_expand_scc (operands); -+ DONE; -+}) -+ -+(define_insn "cstore4" -+ [(set (match_operand:SI 0 "register_operand" "=r") -+ (match_operator:SI 1 "fp_order_operator" -+ [(match_operand:SCALARF 2 "register_operand" "f") -+ (match_operand:SCALARF 3 "register_operand" "f")]))] -+ "TARGET_HARD_FLOAT" -+ "f%C1.\t%0,%2,%3" -+ [(set_attr "type" "fcmp") -+ (set_attr "mode" "")]) -+ -+(define_insn "*seq_zero_" -+ [(set (match_operand:GPR2 0 "register_operand" "=r") -+ (eq:GPR2 (match_operand:GPR 1 "register_operand" "r") -+ (const_int 0)))] -+ "" -+ "seqz\t%0,%1" -+ [(set_attr "type" "slt") -+ (set_attr "mode" "")]) -+ -+(define_insn "*sne_zero_" -+ [(set (match_operand:GPR2 0 "register_operand" "=r") -+ (ne:GPR2 (match_operand:GPR 1 "register_operand" "r") -+ (const_int 0)))] -+ "" -+ "snez\t%0,%1" -+ [(set_attr "type" "slt") -+ (set_attr "mode" "")]) -+ -+(define_insn "*sgt_" -+ [(set (match_operand:GPR2 0 "register_operand" "=r") -+ (any_gt:GPR2 (match_operand:GPR 1 "register_operand" "r") -+ (match_operand:GPR 2 "reg_or_0_operand" "rJ")))] -+ "" -+ "slt\t%0,%z2,%1" -+ [(set_attr "type" "slt") -+ (set_attr "mode" "")]) -+ -+(define_insn "*sge_" -+ [(set (match_operand:GPR2 0 "register_operand" "=r") -+ (any_ge:GPR2 (match_operand:GPR 1 "register_operand" "r") -+ (const_int 1)))] -+ "" -+ "slt\t%0,zero,%1" -+ [(set_attr "type" "slt") -+ (set_attr "mode" "")]) -+ -+(define_insn "*slt_" -+ [(set (match_operand:GPR2 0 "register_operand" "=r") -+ (any_lt:GPR2 (match_operand:GPR 1 "register_operand" "r") -+ (match_operand:GPR 2 "arith_operand" "rI")))] -+ "" -+ "slt\t%0,%1,%2" -+ [(set_attr "type" "slt") -+ (set_attr "mode" "")]) -+ -+(define_insn "*sle_" -+ [(set (match_operand:GPR2 0 "register_operand" "=r") -+ (any_le:GPR2 (match_operand:GPR 1 "register_operand" "r") -+ (match_operand:GPR 2 "sle_operand" "")))] -+ "" -+{ -+ operands[2] = GEN_INT (INTVAL (operands[2]) + 1); -+ return "slt\t%0,%1,%2"; -+} -+ [(set_attr "type" "slt") -+ (set_attr "mode" "")]) -+ -+;; -+;; .................... -+;; -+;; UNCONDITIONAL BRANCHES -+;; -+;; .................... -+ -+;; Unconditional branches. -+ -+(define_insn "jump" -+ [(set (pc) -+ (label_ref (match_operand 0 "" "")))] -+ "" -+ "j\t%l0" -+ [(set_attr "type" "jump") -+ (set_attr "mode" "none")]) -+ -+(define_expand "indirect_jump" -+ [(set (pc) (match_operand 0 "register_operand"))] -+ "" -+{ -+ operands[0] = force_reg (Pmode, operands[0]); -+ if (Pmode == SImode) -+ emit_jump_insn (gen_indirect_jumpsi (operands[0])); -+ else -+ emit_jump_insn (gen_indirect_jumpdi (operands[0])); -+ DONE; -+}) -+ -+(define_insn "indirect_jump" -+ [(set (pc) (match_operand:P 0 "register_operand" "r"))] -+ "" -+ "jr\t%0" -+ [(set_attr "type" "jump") -+ (set_attr "mode" "none")]) -+ -+(define_expand "tablejump" -+ [(set (pc) (match_operand 0 "register_operand" "")) -+ (use (label_ref (match_operand 1 "" "")))] -+ "" -+{ -+ if (flag_pic) -+ operands[0] = expand_simple_binop (Pmode, PLUS, operands[0], -+ gen_rtx_LABEL_REF (Pmode, operands[1]), -+ NULL_RTX, 0, OPTAB_DIRECT); -+ -+ if (flag_pic && Pmode == DImode) -+ emit_jump_insn (gen_tablejumpdi (operands[0], operands[1])); -+ else -+ emit_jump_insn (gen_tablejumpsi (operands[0], operands[1])); -+ DONE; -+}) -+ -+(define_insn "tablejump" -+ [(set (pc) (match_operand:GPR 0 "register_operand" "r")) -+ (use (label_ref (match_operand 1 "" "")))] -+ "" -+ "jr\t%0" -+ [(set_attr "type" "jump") -+ (set_attr "mode" "none")]) -+ -+;; -+;; .................... -+;; -+;; Function prologue/epilogue -+;; -+;; .................... -+;; -+ -+(define_expand "prologue" -+ [(const_int 1)] -+ "" -+{ -+ riscv_expand_prologue (); -+ DONE; -+}) -+ -+;; Block any insns from being moved before this point, since the -+;; profiling call to mcount can use various registers that aren't -+;; saved or used to pass arguments. -+ -+(define_insn "blockage" -+ [(unspec_volatile [(const_int 0)] UNSPEC_BLOCKAGE)] -+ "" -+ "" -+ [(set_attr "type" "ghost") -+ (set_attr "mode" "none")]) -+ -+(define_expand "epilogue" -+ [(const_int 2)] -+ "" -+{ -+ riscv_expand_epilogue (false); -+ DONE; -+}) -+ -+(define_expand "sibcall_epilogue" -+ [(const_int 2)] -+ "" -+{ -+ riscv_expand_epilogue (true); -+ DONE; -+}) -+ -+;; Trivial return. Make it look like a normal return insn as that -+;; allows jump optimizations to work better. -+ -+(define_insn "return" -+ [(return)] -+ "mips_can_use_return_insn ()" -+ "ret" -+ [(set_attr "type" "jump") -+ (set_attr "mode" "none")]) -+ -+;; Normal return. -+ -+(define_insn "return_internal" -+ [(return) -+ (use (match_operand 0 "pmode_register_operand" ""))] -+ "" -+ "jr\t%0" -+ [(set_attr "type" "jump") -+ (set_attr "mode" "none")]) -+ -+;; This is used in compiling the unwind routines. -+(define_expand "eh_return" -+ [(use (match_operand 0 "general_operand"))] -+ "" -+{ -+ if (GET_MODE (operands[0]) != word_mode) -+ operands[0] = convert_to_mode (word_mode, operands[0], 0); -+ if (TARGET_64BIT) -+ emit_insn (gen_eh_set_lr_di (operands[0])); -+ else -+ emit_insn (gen_eh_set_lr_si (operands[0])); -+ DONE; -+}) -+ -+;; Clobber the return address on the stack. We can't expand this -+;; until we know where it will be put in the stack frame. -+ -+(define_insn "eh_set_lr_si" -+ [(unspec [(match_operand:SI 0 "register_operand" "r")] UNSPEC_EH_RETURN) -+ (clobber (match_scratch:SI 1 "=&r"))] -+ "! TARGET_64BIT" -+ "#") -+ -+(define_insn "eh_set_lr_di" -+ [(unspec [(match_operand:DI 0 "register_operand" "r")] UNSPEC_EH_RETURN) -+ (clobber (match_scratch:DI 1 "=&r"))] -+ "TARGET_64BIT" -+ "#") -+ -+(define_split -+ [(unspec [(match_operand 0 "register_operand")] UNSPEC_EH_RETURN) -+ (clobber (match_scratch 1))] -+ "reload_completed" -+ [(const_int 0)] -+{ -+ riscv_set_return_address (operands[0], operands[1]); -+ DONE; -+}) -+ -+;; -+;; .................... -+;; -+;; FUNCTION CALLS -+;; -+;; .................... -+ -+;; Sibling calls. All these patterns use jump instructions. -+ -+;; call_insn_operand will only accept constant -+;; addresses if a direct jump is acceptable. Since the 'S' constraint -+;; is defined in terms of call_insn_operand, the same is true of the -+;; constraints. -+ -+;; When we use an indirect jump, we need a register that will be -+;; preserved by the epilogue (constraint j). -+ -+(define_expand "sibcall" -+ [(parallel [(call (match_operand 0 "") -+ (match_operand 1 "")) -+ (use (match_operand 2 "")) ;; next_arg_reg -+ (use (match_operand 3 ""))])] ;; struct_value_size_rtx -+ "" -+{ -+ riscv_expand_call (true, NULL_RTX, XEXP (operands[0], 0), operands[1]); -+ DONE; -+}) -+ -+(define_insn "sibcall_internal" -+ [(call (mem:SI (match_operand 0 "call_insn_operand" "j,S")) -+ (match_operand 1 "" ""))] -+ "SIBLING_CALL_P (insn)" -+ { return REG_P (operands[0]) ? "jr\t%0" -+ : absolute_symbolic_operand (operands[0], VOIDmode) ? "jump\t%0" -+ : "jump\t%0@"; } -+ [(set_attr "type" "call")]) -+ -+(define_expand "sibcall_value" -+ [(parallel [(set (match_operand 0 "") -+ (call (match_operand 1 "") -+ (match_operand 2 ""))) -+ (use (match_operand 3 ""))])] ;; next_arg_reg -+ "" -+{ -+ riscv_expand_call (true, operands[0], XEXP (operands[1], 0), operands[2]); -+ DONE; -+}) -+ -+(define_insn "sibcall_value_internal" -+ [(set (match_operand 0 "register_operand" "") -+ (call (mem:SI (match_operand 1 "call_insn_operand" "j,S")) -+ (match_operand 2 "" "")))] -+ "SIBLING_CALL_P (insn)" -+ { return REG_P (operands[1]) ? "jr\t%1" -+ : absolute_symbolic_operand (operands[1], VOIDmode) ? "jump\t%1" -+ : "jump\t%1@"; } -+ [(set_attr "type" "call")]) -+ -+(define_insn "sibcall_value_multiple_internal" -+ [(set (match_operand 0 "register_operand" "") -+ (call (mem:SI (match_operand 1 "call_insn_operand" "j,S")) -+ (match_operand 2 "" ""))) -+ (set (match_operand 3 "register_operand" "") -+ (call (mem:SI (match_dup 1)) -+ (match_dup 2))) -+ (clobber (match_scratch:SI 4 "=j,j"))] -+ "SIBLING_CALL_P (insn)" -+ { return REG_P (operands[1]) ? "jr\t%1" -+ : absolute_symbolic_operand (operands[1], VOIDmode) ? "jump\t%1" -+ : "jump\t%1@"; } -+ [(set_attr "type" "call")]) -+ -+(define_expand "call" -+ [(parallel [(call (match_operand 0 "") -+ (match_operand 1 "")) -+ (use (match_operand 2 "")) ;; next_arg_reg -+ (use (match_operand 3 ""))])] ;; struct_value_size_rtx -+ "" -+{ -+ riscv_expand_call (false, NULL_RTX, XEXP (operands[0], 0), operands[1]); -+ DONE; -+}) -+ -+(define_insn "call_internal" -+ [(call (mem:SI (match_operand 0 "call_insn_operand" "r,S")) -+ (match_operand 1 "" "")) -+ (clobber (reg:SI RETURN_ADDR_REGNUM))] -+ "" -+ { return REG_P (operands[0]) ? "jalr\t%0" -+ : absolute_symbolic_operand (operands[0], VOIDmode) ? "call\t%0" -+ : "call\t%0@"; } -+ [(set_attr "jal" "indirect,direct")]) -+ -+(define_expand "call_value" -+ [(parallel [(set (match_operand 0 "") -+ (call (match_operand 1 "") -+ (match_operand 2 ""))) -+ (use (match_operand 3 ""))])] ;; next_arg_reg -+ "" -+{ -+ riscv_expand_call (false, operands[0], XEXP (operands[1], 0), operands[2]); -+ DONE; -+}) -+ -+;; See comment for call_internal. -+(define_insn "call_value_internal" -+ [(set (match_operand 0 "register_operand" "") -+ (call (mem:SI (match_operand 1 "call_insn_operand" "r,S")) -+ (match_operand 2 "" ""))) -+ (clobber (reg:SI RETURN_ADDR_REGNUM))] -+ "" -+ { return REG_P (operands[1]) ? "jalr\t%1" -+ : absolute_symbolic_operand (operands[1], VOIDmode) ? "call\t%1" -+ : "call\t%1@"; } -+ [(set_attr "jal" "indirect,direct")]) -+ -+;; See comment for call_internal. -+(define_insn "call_value_multiple_internal" -+ [(set (match_operand 0 "register_operand" "") -+ (call (mem:SI (match_operand 1 "call_insn_operand" "r,S")) -+ (match_operand 2 "" ""))) -+ (set (match_operand 3 "register_operand" "") -+ (call (mem:SI (match_dup 1)) -+ (match_dup 2))) -+ (clobber (reg:SI RETURN_ADDR_REGNUM))] -+ "" -+ { return REG_P (operands[1]) ? "jalr\t%1" -+ : absolute_symbolic_operand (operands[1], VOIDmode) ? "call\t%1" -+ : "call\t%1@"; } -+ [(set_attr "jal" "indirect,direct")]) -+ -+;; Call subroutine returning any type. -+ -+(define_expand "untyped_call" -+ [(parallel [(call (match_operand 0 "") -+ (const_int 0)) -+ (match_operand 1 "") -+ (match_operand 2 "")])] -+ "" -+{ -+ int i; -+ -+ emit_call_insn (GEN_CALL (operands[0], const0_rtx, NULL, const0_rtx)); -+ -+ for (i = 0; i < XVECLEN (operands[2], 0); i++) -+ { -+ rtx set = XVECEXP (operands[2], 0, i); -+ mips_emit_move (SET_DEST (set), SET_SRC (set)); -+ } -+ -+ emit_insn (gen_blockage ()); -+ DONE; -+}) -+ -+(define_insn "nop" -+ [(const_int 0)] -+ "" -+ "nop" -+ [(set_attr "type" "nop") -+ (set_attr "mode" "none")]) -+ -+(include "sync.md") -+(include "peephole.md") -+ -+(define_c_enum "unspec" [ -+ UNSPEC_ADDRESS_FIRST -+]) -diff --git a/gcc-4.6.1/gcc/config/riscv/riscv.opt b/gcc-4.6.1/gcc/config/riscv/riscv.opt -new file mode 100644 -index 0000000..683bb06 ---- /dev/null -+++ gcc-4.6.1/gcc/config/riscv/riscv.opt -@@ -0,0 +1,67 @@ -+; Options for the MIPS port of the compiler -+; -+; Copyright (C) 2005, 2007, 2008, 2010, 2011 Free Software Foundation, Inc. -+; -+; This file is part of GCC. -+; -+; GCC is free software; you can redistribute it and/or modify it under -+; the terms of the GNU General Public License as published by the Free -+; Software Foundation; either version 3, or (at your option) any later -+; version. -+; -+; GCC is distributed in the hope that it will be useful, but WITHOUT -+; ANY WARRANTY; without even the implied warranty of MERCHANTABILITY -+; or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public -+; License for more details. -+; -+; You should have received a copy of the GNU General Public License -+; along with GCC; see the file COPYING3. If not see -+; . -+ -+m32 -+Target RejectNegative Mask(32BIT) -+Generate RV32 code -+ -+m64 -+Target RejectNegative InverseMask(32BIT, 64BIT) -+Generate RV64 code -+ -+mbranch-cost= -+Target RejectNegative Joined UInteger Var(riscv_branch_cost) -+-mbranch-cost=COST Set the cost of branches to roughly COST instructions -+ -+mhard-float -+Target Report RejectNegative InverseMask(SOFT_FLOAT_ABI, HARD_FLOAT_ABI) -+Allow the use of hardware floating-point ABI and instructions -+ -+mmemcpy -+Target Report Mask(MEMCPY) -+Don't optimize block moves -+ -+mplt -+Target Report Var(TARGET_PLT) Init(1) -+When generating -fpic code, allow the use of PLTs. Ignored for fno-pic. -+ -+msoft-float -+Target Report RejectNegative Mask(SOFT_FLOAT_ABI) -+Prevent the use of all hardware floating-point instructions -+ -+mfdiv -+Target Report RejectNegative Mask(FDIV) -+Use hardware floating-point divide and square root instructions -+ -+mtune= -+Target RejectNegative Joined Var(riscv_tune_string) -+-mtune=PROCESSOR Optimize the output for PROCESSOR -+ -+msmall-data-limit= -+Target Joined Separate UInteger Var(g_switch_value) Init(8) -+-msmall-data-limit= Put global and static data smaller than bytes into a special section (on some targets) -+ -+matomic -+Target Report Mask(ATOMIC) -+Use hardware atomic memory instructions. Enabled by default, use -mno-atomic to disable -+ -+mrvm -+Target Mask(RVM) -+Use M standard extensions for integer multiplication and division. Enabled by default, use -mno-rvm to disable -diff --git a/gcc-4.6.1/gcc/config/riscv/ros.h b/gcc-4.6.1/gcc/config/riscv/ros.h -new file mode 100644 -index 0000000..593fbc5 ---- /dev/null -+++ gcc-4.6.1/gcc/config/riscv/ros.h -@@ -0,0 +1,9 @@ -+#include "linux.h" -+ -+#undef LINUX_DYNAMIC_LINKER -+#define LINUX_DYNAMIC_LINKER GLIBC_DYNAMIC_LINKER -+ -+#undef TARGET_VERSION -+#define TARGET_VERSION fprintf (stderr, " (RISC-V ROS/ELF)"); -+ -+#undef MD_UNWIND_SUPPORT -diff --git a/gcc-4.6.1/gcc/config/riscv/ros64.h b/gcc-4.6.1/gcc/config/riscv/ros64.h -new file mode 100644 -index 0000000..bf19839 ---- /dev/null -+++ gcc-4.6.1/gcc/config/riscv/ros64.h -@@ -0,0 +1,7 @@ -+#include "linux64.h" -+ -+#undef LINUX_DYNAMIC_LINKER32 -+#define LINUX_DYNAMIC_LINKER32 GLIBC_DYNAMIC_LINKER32 -+ -+#undef LINUX_DYNAMIC_LINKER64 -+#define LINUX_DYNAMIC_LINKER64 GLIBC_DYNAMIC_LINKER64 -diff --git a/gcc-4.6.1/gcc/config/riscv/sync.md b/gcc-4.6.1/gcc/config/riscv/sync.md -new file mode 100644 -index 0000000..1f19e4d ---- /dev/null -+++ gcc-4.6.1/gcc/config/riscv/sync.md -@@ -0,0 +1,92 @@ -+;; Machine description for RISC-V atomic operations. -+;; Copyright (C) 2011-2014 Free Software Foundation, Inc. -+;; Contributed by Andrew Waterman (waterman@cs.berkeley.edu) at UC Berkeley. -+;; Based on MIPS target for GNU compiler. -+ -+;; This file is part of GCC. -+ -+;; GCC is free software; you can redistribute it and/or modify -+;; it under the terms of the GNU General Public License as published by -+;; the Free Software Foundation; either version 3, or (at your option) -+;; any later version. -+ -+;; GCC is distributed in the hope that it will be useful, -+;; but WITHOUT ANY WARRANTY; without even the implied warranty of -+;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -+;; GNU General Public License for more details. -+ -+;; You should have received a copy of the GNU General Public License -+;; along with GCC; see the file COPYING3. If not see -+;; . -+ -+(define_c_enum "unspec" [ -+ UNSPEC_COMPARE_AND_SWAP -+ UNSPEC_COMPARE_AND_SWAP_12 -+ UNSPEC_SYNC_OLD_OP -+ UNSPEC_SYNC_NEW_OP -+ UNSPEC_SYNC_NEW_OP_12 -+ UNSPEC_SYNC_OLD_OP_12 -+ UNSPEC_SYNC_EXCHANGE -+ UNSPEC_SYNC_EXCHANGE_12 -+ UNSPEC_MEMORY_BARRIER -+]) -+ -+(define_code_iterator any_atomic [plus ior xor and]) -+ -+;; Atomic memory operations. -+ -+(define_expand "memory_barrier" -+ [(set (match_dup 0) -+ (unspec:BLK [(match_dup 0)] UNSPEC_MEMORY_BARRIER))] -+ "" -+{ -+ operands[0] = gen_rtx_MEM (BLKmode, gen_rtx_SCRATCH (Pmode)); -+ MEM_VOLATILE_P (operands[0]) = 1; -+}) -+ -+(define_insn "*memory_barrier" -+ [(set (match_operand:BLK 0 "" "") -+ (unspec:BLK [(match_dup 0)] UNSPEC_MEMORY_BARRIER))] -+ "" -+ "fence") -+ -+(define_insn "sync_" -+ [(set (match_operand:GPR 0 "memory_operand" "+YR") -+ (unspec_volatile:GPR -+ [(any_atomic:GPR (match_dup 0) -+ (match_operand:GPR 1 "reg_or_0_operand" "rJ"))] -+ UNSPEC_SYNC_OLD_OP))] -+ "TARGET_ATOMIC" -+ "amo. zero,%z1,%0") -+ -+(define_insn "sync_old_" -+ [(set (match_operand:GPR 0 "register_operand" "=&r") -+ (match_operand:GPR 1 "memory_operand" "+YR")) -+ (set (match_dup 1) -+ (unspec_volatile:GPR -+ [(any_atomic:GPR (match_dup 1) -+ (match_operand:GPR 2 "reg_or_0_operand" "rJ"))] -+ UNSPEC_SYNC_OLD_OP))] -+ "TARGET_ATOMIC" -+ "amo. %0,%z2,%1") -+ -+(define_insn "sync_lock_test_and_set" -+ [(set (match_operand:GPR 0 "register_operand" "=&r") -+ (match_operand:GPR 1 "memory_operand" "+YR")) -+ (set (match_dup 1) -+ (unspec_volatile:GPR [(match_operand:GPR 2 "reg_or_0_operand" "rJ")] -+ UNSPEC_SYNC_EXCHANGE))] -+ "TARGET_ATOMIC" -+ "amoswap. %0,%z2,%1") -+ -+(define_insn "sync_compare_and_swap" -+ [(set (match_operand:GPR 0 "register_operand" "=&r") -+ (match_operand:GPR 1 "memory_operand" "+YR")) -+ (set (match_dup 1) -+ (unspec_volatile:GPR [(match_operand:GPR 2 "reg_or_0_operand" "rJ") -+ (match_operand:GPR 3 "reg_or_0_operand" "rJ")] -+ UNSPEC_COMPARE_AND_SWAP)) -+ (clobber (match_scratch:GPR 4 "=&r"))] -+ "TARGET_ATOMIC" -+ "1: lr. %0,%1; bne %0,%z2,1f; sc. %4,%z3,%1; bnez %4,1b; 1:" -+ [(set (attr "length") (const_int 16))]) -diff --git a/gcc-4.6.1/gcc/config/riscv/t-elf b/gcc-4.6.1/gcc/config/riscv/t-elf -new file mode 100644 -index 0000000..2330377 ---- /dev/null -+++ gcc-4.6.1/gcc/config/riscv/t-elf -@@ -0,0 +1,50 @@ -+# Copyright (C) 1999, 2000, 2001, 2002, 2003, 2004, 2006, -+# 2007 Free Software Foundation, Inc. -+# -+# This file is part of GCC. -+# -+# GCC is free software; you can redistribute it and/or modify -+# it under the terms of the GNU General Public License as published by -+# the Free Software Foundation; either version 3, or (at your option) -+# any later version. -+# -+# GCC is distributed in the hope that it will be useful, -+# but WITHOUT ANY WARRANTY; without even the implied warranty of -+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -+# GNU General Public License for more details. -+# -+# You should have received a copy of the GNU General Public License -+# along with GCC; see the file COPYING3. If not see -+# . -+ -+# Assemble startup files. -+$(T)crti.o: $(srcdir)/config/riscv/crti.asm $(GCC_PASSES) -+ $(GCC_FOR_TARGET) $(GCC_CFLAGS) $(MULTILIB_CFLAGS) $(INCLUDES) \ -+ -c -o $(T)crti.o -x assembler-with-cpp $(srcdir)/config/riscv/crti.asm -+ -+$(T)crtn.o: $(srcdir)/config/riscv/crtn.asm $(GCC_PASSES) -+ $(GCC_FOR_TARGET) $(GCC_CFLAGS) $(MULTILIB_CFLAGS) $(INCLUDES) \ -+ -c -o $(T)crtn.o -x assembler-with-cpp $(srcdir)/config/riscv/crtn.asm -+ -+# Build the libraries for both hard and soft floating point -+ -+MULTILIB_OPTIONS = msoft-float m64/m32 mfdiv mno-atomic -+MULTILIB_DIRNAMES = soft-float 64 32 fdiv no-atomic -+MULTILIB_EXCEPTIONS = *msoft-float*/*mfdiv* -+EXTRA_MULTILIB_PARTS = crtbegin.o crtend.o crti.o crtn.o -+ -+LIBGCC = stmp-multilib -+INSTALL_LIBGCC = install-multilib -+ -+FPBIT = fp-bit.c -+DPBIT = dp-bit.c -+ -+dp-bit.c: $(srcdir)/config/fp-bit.c -+ cat $(srcdir)/config/fp-bit.c > dp-bit.c -+ -+fp-bit.c: $(srcdir)/config/fp-bit.c -+ echo '#define FLOAT' > fp-bit.c -+ cat $(srcdir)/config/fp-bit.c >> fp-bit.c -+ -+LIB2FUNCS_EXTRA += $(srcdir)/config/riscv/riscv-fp.c -+LIB2FUNCS_EXTRA := $(sort $(LIB2FUNCS_EXTRA)) -diff --git a/gcc-4.6.1/gcc/config/riscv/t-linux64 b/gcc-4.6.1/gcc/config/riscv/t-linux64 -new file mode 100644 -index 0000000..fee61a4 ---- /dev/null -+++ gcc-4.6.1/gcc/config/riscv/t-linux64 -@@ -0,0 +1,48 @@ -+# Copyright (C) 2003, 2004, 2005, 2006 Free Software Foundation, Inc. -+# -+# This file is part of GCC. -+# -+# GCC is free software; you can redistribute it and/or modify -+# it under the terms of the GNU General Public License as published by -+# the Free Software Foundation; either version 3, or (at your option) -+# any later version. -+# -+# GCC is distributed in the hope that it will be useful, -+# but WITHOUT ANY WARRANTY; without even the implied warranty of -+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -+# GNU General Public License for more details. -+# -+# You should have received a copy of the GNU General Public License -+# along with GCC; see the file COPYING3. If not see -+# . -+ -+MULTILIB_OPTIONS = m64/m32 msoft-float mfdiv mno-atomic -+MULTILIB_DIRNAMES = 64 32 soft-float fdiv no-atomic -+MULTILIB_EXCEPTIONS = *msoft-float*/*mfdiv* -+MULTILIB_OSDIRNAMES = ../lib ../lib32 -+ -+EXTRA_MULTILIB_PARTS=crtbegin.o crtend.o crtbeginS.o crtendS.o crtbeginT.o -+ -+TPBIT = tp-bit.c -+ -+tp-bit.c: $(srcdir)/config/fp-bit.c -+ echo '#ifdef _RISCVEL' > tp-bit.c -+ echo '# define FLOAT_BIT_ORDER_MISMATCH' >> tp-bit.c -+ echo '#endif' >> tp-bit.c -+ echo '#if __LDBL_MANT_DIG__ == 113' >> tp-bit.c -+ echo '# define TFLOAT' >> tp-bit.c -+ cat $(srcdir)/config/fp-bit.c >> tp-bit.c -+ echo '#endif' >> tp-bit.c -+ -+FPBIT = fp-bit.c -+DPBIT = dp-bit.c -+ -+dp-bit.c: $(srcdir)/config/fp-bit.c -+ cat $(srcdir)/config/fp-bit.c > dp-bit.c -+ -+fp-bit.c: $(srcdir)/config/fp-bit.c -+ echo '#define FLOAT' > fp-bit.c -+ cat $(srcdir)/config/fp-bit.c >> fp-bit.c -+ -+LIB2FUNCS_EXTRA += $(srcdir)/config/riscv/riscv-fp.c -+LIB2FUNCS_EXTRA := $(sort $(LIB2FUNCS_EXTRA)) -diff --git a/gcc-4.6.1/gcc/cp/cfns.gperf b/gcc-4.6.1/gcc/cp/cfns.gperf -index ef1ed08..c17458a 100644 ---- a/gcc-4.6.1/gcc/cp/cfns.gperf -+++ gcc-4.6.1/gcc/cp/cfns.gperf -@@ -20,8 +20,8 @@ along with GCC; see the file COPYING3. If not see - __inline - #endif - static unsigned int hash (const char *, unsigned int); --#ifdef __GNUC__ --__inline -+#if defined __GNUC_STDC_INLINE__ || defined __GNUC_GNU_INLINE__ -+__attribute__ ((__gnu_inline__)) - #endif - const char * libc_name_p (const char *, unsigned int); - %} -diff --git a/gcc-4.6.1/gcc/cp/cfns.h b/gcc-4.6.1/gcc/cp/cfns.h -index 62cdfab..13ed014 100644 ---- a/gcc-4.6.1/gcc/cp/cfns.h -+++ gcc-4.6.1/gcc/cp/cfns.h -@@ -51,8 +51,8 @@ along with GCC; see the file COPYING3. If not see - __inline - #endif - static unsigned int hash (const char *, unsigned int); --#ifdef __GNUC__ --__inline -+#if defined __GNUC_STDC_INLINE__ || defined __GNUC_GNU_INLINE__ -+__attribute__ ((__gnu_inline__)) - #endif - const char * libc_name_p (const char *, unsigned int); - /* maximum key range = 391, duplicates = 0 */ -@@ -122,12 +122,9 @@ hash (register const char *str, register unsigned int len) - return hval + asso_values[(unsigned char)str[len - 1]]; - } - --#ifdef __GNUC__ --__inline --#ifdef __GNUC_STDC_INLINE__ -+#if defined __GNUC_STDC_INLINE__ || defined __GNUC_GNU_INLINE__ - __attribute__ ((__gnu_inline__)) - #endif --#endif - const char * - libc_name_p (register const char *str, register unsigned int len) - { -diff --git a/gcc-4.6.1/gcc/doc/cppopts.texi b/gcc-4.6.1/gcc/doc/cppopts.texi -index 5212478..52d5997 100644 ---- a/gcc-4.6.1/gcc/doc/cppopts.texi -+++ gcc-4.6.1/gcc/doc/cppopts.texi -@@ -769,7 +769,7 @@ Replacement: [ ] @{ @} # \ ^ | ~ - Enable special code to work around file systems which only permit very - short file names, such as MS-DOS@. - --@itemx --help -+@item --help - @itemx --target-help - @opindex help - @opindex target-help -diff --git a/gcc-4.6.1/gcc/doc/generic.texi b/gcc-4.6.1/gcc/doc/generic.texi -index 5874c55..79af22f 100644 ---- a/gcc-4.6.1/gcc/doc/generic.texi -+++ gcc-4.6.1/gcc/doc/generic.texi -@@ -1415,13 +1415,13 @@ generate these expressions anyhow, if it can tell that strictness does - not matter. The type of the operands and that of the result are - always of @code{BOOLEAN_TYPE} or @code{INTEGER_TYPE}. - --@itemx POINTER_PLUS_EXPR -+@item POINTER_PLUS_EXPR - This node represents pointer arithmetic. The first operand is always - a pointer/reference type. The second operand is always an unsigned - integer type compatible with sizetype. This is the only binary - arithmetic operand that can operate on pointer types. - --@itemx PLUS_EXPR -+@item PLUS_EXPR - @itemx MINUS_EXPR - @itemx MULT_EXPR - These nodes represent various binary arithmetic operations. -diff --git a/gcc-4.6.1/gcc/doc/invoke.texi b/gcc-4.6.1/gcc/doc/invoke.texi -index 4bcf83a..b6ef068 100644 ---- a/gcc-4.6.1/gcc/doc/invoke.texi -+++ gcc-4.6.1/gcc/doc/invoke.texi -@@ -165,7 +165,7 @@ in the following sections. - -pipe -pass-exit-codes @gol - -x @var{language} -v -### --help@r{[}=@var{class}@r{[},@dots{}@r{]]} --target-help @gol - --version -wrapper @@@var{file} -fplugin=@var{file} -fplugin-arg-@var{name}=@var{arg} @gol ---fdump-ada-spec@r{[}-slim@r{]}} -fdump-go-spec=@var{file} -+-fdump-ada-spec@r{[}-slim@r{]} -fdump-go-spec=@var{file}} - - @item C Language Options - @xref{C Dialect Options,,Options Controlling C Dialect}. -@@ -5083,11 +5083,11 @@ Dump after duplicating the computed gotos. - @option{-fdump-rtl-ce3} enable dumping after the three - if conversion passes. - --@itemx -fdump-rtl-cprop_hardreg -+@item -fdump-rtl-cprop_hardreg - @opindex fdump-rtl-cprop_hardreg - Dump after hard register copy propagation. - --@itemx -fdump-rtl-csa -+@item -fdump-rtl-csa - @opindex fdump-rtl-csa - Dump after combining stack adjustments. - -@@ -5098,11 +5098,11 @@ Dump after combining stack adjustments. - @option{-fdump-rtl-cse1} and @option{-fdump-rtl-cse2} enable dumping after - the two common sub-expression elimination passes. - --@itemx -fdump-rtl-dce -+@item -fdump-rtl-dce - @opindex fdump-rtl-dce - Dump after the standalone dead code elimination passes. - --@itemx -fdump-rtl-dbr -+@item -fdump-rtl-dbr - @opindex fdump-rtl-dbr - Dump after delayed branch scheduling. - -@@ -5147,7 +5147,7 @@ Dump after the initialization of the registers. - @opindex fdump-rtl-initvals - Dump after the computation of the initial value sets. - --@itemx -fdump-rtl-into_cfglayout -+@item -fdump-rtl-into_cfglayout - @opindex fdump-rtl-into_cfglayout - Dump after converting to cfglayout mode. - -@@ -5177,7 +5177,7 @@ Dump after removing redundant mode switches. - @opindex fdump-rtl-rnreg - Dump after register renumbering. - --@itemx -fdump-rtl-outof_cfglayout -+@item -fdump-rtl-outof_cfglayout - @opindex fdump-rtl-outof_cfglayout - Dump after converting from cfglayout mode. - -@@ -5189,7 +5189,7 @@ Dump after the peephole pass. - @opindex fdump-rtl-postreload - Dump after post-reload optimizations. - --@itemx -fdump-rtl-pro_and_epilogue -+@item -fdump-rtl-pro_and_epilogue - @opindex fdump-rtl-pro_and_epilogue - Dump after generating the function pro and epilogues. - -diff --git a/gcc-4.6.1/gcc/doc/sourcebuild.texi b/gcc-4.6.1/gcc/doc/sourcebuild.texi -index f4a2807..3d3e348 100644 ---- a/gcc-4.6.1/gcc/doc/sourcebuild.texi -+++ gcc-4.6.1/gcc/doc/sourcebuild.texi -@@ -676,7 +676,7 @@ standard rule in @file{gcc/Makefile.in} to the variable - @code{lang_checks}. - - @table @code --@itemx all.cross -+@item all.cross - @itemx start.encap - @itemx rest.encap - FIXME: exactly what goes in each of these targets? -diff --git a/gcc-4.6.1/gcc/dse.c b/gcc-4.6.1/gcc/dse.c -index a15b735..05c0d01 100644 ---- a/gcc-4.6.1/gcc/dse.c -+++ gcc-4.6.1/gcc/dse.c -@@ -1326,7 +1326,46 @@ record_store (rtx body, bb_info_t bb_info) - else - { - width = GET_MODE_SIZE (GET_MODE (mem)); -+ /* cbatten - Previously there was the following assertion here: -+ - gcc_assert ((unsigned) width <= HOST_BITS_PER_WIDE_INT); -+ -+ I don't think we need this assertion, and it prevents us from -+ using very large vector types which we would like to do on -+ maven. In the above if condition you can see that we already -+ need to be able to handle widths which are greater than the -+ number of bits in a wide int. And I looked through the -+ remaining codeand it seems like it is used in these two -+ functions: -+ -+ set_usage_bits -+ all_positions_needed_p -+ -+ neither use is guarded by a check to see if the mode is BLKmode -+ and it looks like both use the general gcc bitmap code which -+ supports arbitrarilty sized bitmaps. -+ -+ The width value is also used as "offset + width" in a couple -+ places but all of these places look like it takes an int (as -+ opposed to a bitmap) so we should be okay. -+ -+ And then at the bottom of this function there is this: -+ -+ if ( width > HOST_BITS_PER_WIDE_INT ) { -+ store_info->is_large = true; -+ store_info->positions_needed.large.count = 0; -+ store_info->positions_needed.large.bitmap = BITMAP_ALLOC(NULL); -+ } -+ else { -+ store_info->is_large = false; -+ store_info->positions_needed.small_bitmask -+ = lowpart_bitmask(width); -+ } -+ -+ Which as you can see explicitly handles the case where the -+ width is too large. The store_info struct has specific hooks to -+ enable this - so other code should work fine as long as it -+ checks the is_large flag. */ - } - - if (spill_alias_set) -diff --git a/gcc-4.6.1/gcc/expr.c b/gcc-4.6.1/gcc/expr.c -index 9a81754..773b270 100644 ---- a/gcc-4.6.1/gcc/expr.c -+++ gcc-4.6.1/gcc/expr.c -@@ -351,7 +351,12 @@ convert_move (rtx to, rtx from, int unsignedp) - - if (VECTOR_MODE_P (to_mode) || VECTOR_MODE_P (from_mode)) - { -+ /* cbatten - On maven the size of both vectors need not be the -+ same, I am not quite sure yet if it is safe to comment out -+ this assertion. -+ - gcc_assert (GET_MODE_BITSIZE (from_mode) == GET_MODE_BITSIZE (to_mode)); -+ */ - - if (VECTOR_MODE_P (to_mode)) - from = simplify_gen_subreg (to_mode, from, GET_MODE (from), 0); -diff --git a/gcc-4.6.1/gcc/gengtype.c b/gcc-4.6.1/gcc/gengtype.c -index abf17f8..6c0ca4a 100644 ---- a/gcc-4.6.1/gcc/gengtype.c -+++ gcc-4.6.1/gcc/gengtype.c -@@ -3594,14 +3594,13 @@ write_field_root (outf_p f, pair_p v, type_p type, const char *name, - int has_length, struct fileloc *line, const char *if_marked, - bool emit_pch, type_p field_type, const char *field_name) - { -+ struct pair newv; - /* If the field reference is relative to V, rather than to some - subcomponent of V, we can mark any subarrays with a single stride. - We're effectively treating the field as a global variable in its - own right. */ - if (v && type == v->type) - { -- struct pair newv; -- - newv = *v; - newv.type = field_type; - newv.name = ACONCAT ((v->name, ".", field_name, NULL)); -diff --git a/gcc-4.6.1/gcc/genmodes.c b/gcc-4.6.1/gcc/genmodes.c -index dae7e38..df3db0e 100644 ---- a/gcc-4.6.1/gcc/genmodes.c -+++ gcc-4.6.1/gcc/genmodes.c -@@ -1002,7 +1002,7 @@ emit_mode_size (void) - int c; - struct mode_data *m; - -- print_maybe_const_decl ("%sunsigned char", "mode_size", -+ print_maybe_const_decl ("%sunsigned short", "mode_size", - "NUM_MACHINE_MODES", bytesize); - - for_all_modes (c, m) -@@ -1120,7 +1120,7 @@ emit_mode_base_align (void) - int c; - struct mode_data *m; - -- print_maybe_const_decl ("%sunsigned char", -+ print_maybe_const_decl ("%sunsigned short", - "mode_base_align", "NUM_MACHINE_MODES", - alignment); - -diff --git a/gcc-4.6.1/gcc/ira-int.h b/gcc-4.6.1/gcc/ira-int.h -index 049a07f..a58f0ca 100644 ---- a/gcc-4.6.1/gcc/ira-int.h -+++ gcc-4.6.1/gcc/ira-int.h -@@ -1123,8 +1123,13 @@ static inline bool - ira_allocno_object_iter_cond (ira_allocno_object_iterator *i, ira_allocno_t a, - ira_object_t *o) - { -- *o = ALLOCNO_OBJECT (a, i->n); -- return i->n++ < ALLOCNO_NUM_OBJECTS (a); -+ int n = i->n++; -+ if (n < ALLOCNO_NUM_OBJECTS (a)) -+ { -+ *o = ALLOCNO_OBJECT (a, n); -+ return true; -+ } -+ return false; - } - - /* Loop over all objects associated with allocno A. In each -diff --git a/gcc-4.6.1/gcc/machmode.h b/gcc-4.6.1/gcc/machmode.h -index bdcd02d..c70a0de 100644 ---- a/gcc-4.6.1/gcc/machmode.h -+++ gcc-4.6.1/gcc/machmode.h -@@ -176,7 +176,7 @@ extern const unsigned char mode_class[NUM_MACHINE_MODES]; - - /* Get the size in bytes and bits of an object of mode MODE. */ - --extern CONST_MODE_SIZE unsigned char mode_size[NUM_MACHINE_MODES]; -+extern CONST_MODE_SIZE unsigned short mode_size[NUM_MACHINE_MODES]; - #define GET_MODE_SIZE(MODE) ((unsigned short) mode_size[MODE]) - #define GET_MODE_BITSIZE(MODE) ((unsigned short) (GET_MODE_SIZE (MODE) * BITS_PER_UNIT)) - -@@ -253,7 +253,7 @@ extern enum machine_mode get_best_mode (int, int, unsigned int, - - /* Determine alignment, 1<=result<=BIGGEST_ALIGNMENT. */ - --extern CONST_MODE_BASE_ALIGN unsigned char mode_base_align[NUM_MACHINE_MODES]; -+extern CONST_MODE_BASE_ALIGN unsigned short mode_base_align[NUM_MACHINE_MODES]; - - extern unsigned get_mode_alignment (enum machine_mode); - -diff --git a/gcc-4.6.1/libgcc/config.host b/gcc-4.6.1/libgcc/config.host -index d3f64d6..27545ff 100644 ---- a/gcc-4.6.1/libgcc/config.host -+++ gcc-4.6.1/libgcc/config.host -@@ -506,6 +506,8 @@ powerpcle-*-eabisim*) - ;; - powerpcle-*-eabi*) - ;; -+riscv*-*-*) -+ ;; - rs6000-ibm-aix4.[3456789]* | powerpc-ibm-aix4.[3456789]*) - ;; - rs6000-ibm-aix5.1.* | powerpc-ibm-aix5.1.*) diff --git a/recipes-devtool/riscv-tools/files/glibc-2.14.1-riscv.patch b/recipes-devtool/riscv-tools/files/glibc-2.14.1-riscv.patch deleted file mode 100644 index e890997..0000000 --- a/recipes-devtool/riscv-tools/files/glibc-2.14.1-riscv.patch +++ /dev/null @@ -1,13141 +0,0 @@ -diff --git a/glibc-2.14.1/configure b/glibc-2.14.1/configure -index 6cf85e5..c2571b5 100755 ---- a/glibc-2.14.1/configure -+++ glibc-2.14.1/configure -@@ -5002,7 +5002,7 @@ $as_echo_n "checking version of $MAKE... " >&6; } - ac_prog_version=`$MAKE --version 2>&1 | sed -n 's/^.*GNU Make[^0-9]*\([0-9][0-9.]*\).*$/\1/p'` - case $ac_prog_version in - '') ac_prog_version="v. ?.??, bad"; ac_verc_fail=yes;; -- 3.79* | 3.[89]*) -+ 3.79* | 3.[89]* | [4-9].* | [1-9][0-9]*) - ac_prog_version="$ac_prog_version, ok"; ac_verc_fail=no;; - *) ac_prog_version="$ac_prog_version, bad"; ac_verc_fail=yes;; - -diff --git a/glibc-2.14.1/configure.in b/glibc-2.14.1/configure.in -index fbc64b9..caf7c09 100644 ---- a/glibc-2.14.1/configure.in -+++ glibc-2.14.1/configure.in -@@ -1030,7 +1030,7 @@ AC_CHECK_PROG_VER(CC, ${ac_tool_prefix}gcc ${ac_tool_prefix}cc, -v, - critic_missing="$critic_missing gcc") - AC_CHECK_PROG_VER(MAKE, gnumake gmake make, --version, - [GNU Make[^0-9]*\([0-9][0-9.]*\)], -- [3.79* | 3.[89]*], critic_missing="$critic_missing make") -+ [3.79* | 3.[89]* | [4-9].* | [1-9][0-9]*], critic_missing="$critic_missing make") - - AC_CHECK_PROG_VER(MSGFMT, gnumsgfmt gmsgfmt msgfmt, --version, - [GNU gettext.* \([0-9]*\.[0-9.]*\)], -diff --git a/glibc-2.14.1/scripts/config.sub b/glibc-2.14.1/scripts/config.sub -index 459eb41..46a0794 100755 ---- a/glibc-2.14.1/scripts/config.sub -+++ glibc-2.14.1/scripts/config.sub -@@ -290,6 +290,7 @@ case $basic_machine in - | pdp10 | pdp11 | pj | pjl \ - | powerpc | powerpc64 | powerpc64le | powerpcle | ppcbe \ - | pyramid \ -+ | riscv \ - | rx \ - | score \ - | sh | sh[1234] | sh[24]a | sh[24]aeb | sh[23]e | sh[34]eb | sheb | shbe | shle | sh[1234]le | sh3ele \ -diff --git a/glibc-2.14.1/shlib-versions b/glibc-2.14.1/shlib-versions -index d3e8407..68754a1 100644 ---- a/glibc-2.14.1/shlib-versions -+++ glibc-2.14.1/shlib-versions -@@ -31,6 +31,7 @@ cris-.*-linux.* DEFAULT GLIBC_2.2 - x86_64-.*-linux.* DEFAULT GLIBC_2.2.5 - powerpc64-.*-linux.* DEFAULT GLIBC_2.3 - .*-.*-gnu-gnu.* DEFAULT GLIBC_2.2.6 -+riscv-.*-linux.* DEFAULT GLIBC_2.14 - - # Configuration WORDSIZE[32|64] Alternate configuration - # ------------- ---------- ----------------------- -diff --git a/glibc-2.14.1/sysdeps/riscv/Implies b/glibc-2.14.1/sysdeps/riscv/Implies -new file mode 100644 -index 0000000..3c3d8e7 ---- /dev/null -+++ glibc-2.14.1/sysdeps/riscv/Implies -@@ -0,0 +1,5 @@ -+ieee754/flt-32 -+ieee754/dbl-64 -+ -+# This needs to change to support rv32 -+riscv/rv64 -diff --git a/glibc-2.14.1/sysdeps/riscv/Makefile b/glibc-2.14.1/sysdeps/riscv/Makefile -new file mode 100644 -index 0000000..cd9598a ---- /dev/null -+++ glibc-2.14.1/sysdeps/riscv/Makefile -@@ -0,0 +1,49 @@ -+ifneq ($(all-rtld-routines),) -+CFLAGS-rtld.c += -mno-plt -+CFLAGS-dl-load.c += -mno-plt -+CFLAGS-dl-cache.c += -mno-plt -+CFLAGS-dl-lookup.c += -mno-plt -+CFLAGS-dl-object.c += -mno-plt -+CFLAGS-dl-reloc.c += -mno-plt -+CFLAGS-dl-deps.c += -mno-plt -+CFLAGS-dl-runtime.c += -mno-plt -+CFLAGS-dl-error.c += -mno-plt -+CFLAGS-dl-init.c += -mno-plt -+CFLAGS-dl-fini.c += -mno-plt -+CFLAGS-dl-debug.c += -mno-plt -+CFLAGS-dl-misc.c += -mno-plt -+CFLAGS-dl-version.c += -mno-plt -+CFLAGS-dl-profile.c += -mno-plt -+CFLAGS-dl-conflict.c += -mno-plt -+CFLAGS-dl-tls.c += -mno-plt -+CFLAGS-dl-origin.c += -mno-plt -+CFLAGS-dl-scope.c += -mno-plt -+CFLAGS-dl-execstack.c += -mno-plt -+CFLAGS-dl-caller.c += -mno-plt -+CFLAGS-dl-open.c += -mno-plt -+CFLAGS-dl-close.c += -mno-plt -+CFLAGS-dl-sysdep.c += -mno-plt -+CFLAGS-dl-environ.c += -mno-plt -+CFLAGS-dl-minimal.c += -mno-plt -+CFLAGS-dl-static.c += -mno-plt -+CFLAGS-dl-brk.c += -mno-plt -+CFLAGS-dl-sbrk.c += -mno-plt -+CFLAGS-dl-getcwd.c += -mno-plt -+CFLAGS-dl-openat64.c += -mno-plt -+CFLAGS-dl-opendir.c += -mno-plt -+CFLAGS-dl-fxstatat64.c += -mno-plt -+endif -+ -+CFLAGS-closedir.c += -mno-plt -+CFLAGS-exit.c += -mno-plt -+CFLAGS-cxa_atexit.c += -mno-plt -+ -+ifeq ($(subdir),misc) -+sysdep_headers += sys/asm.h sgidefs.h -+endif -+ -+ifeq ($(subdir),rt) -+librt-sysdep_routines += rt-sysdep -+endif -+ -+ASFLAGS-.os += $(pic-ccflag) -diff --git a/glibc-2.14.1/sysdeps/riscv/Versions b/glibc-2.14.1/sysdeps/riscv/Versions -new file mode 100644 -index 0000000..5a0c2d2 ---- /dev/null -+++ glibc-2.14.1/sysdeps/riscv/Versions -@@ -0,0 +1,5 @@ -+libc { -+ GLIBC_2.14 { -+ __memcpy_g; -+ } -+} -diff --git a/glibc-2.14.1/sysdeps/riscv/__longjmp.S b/glibc-2.14.1/sysdeps/riscv/__longjmp.S -new file mode 100644 -index 0000000..88f720e ---- /dev/null -+++ glibc-2.14.1/sysdeps/riscv/__longjmp.S -@@ -0,0 +1,67 @@ -+/* Copyright (C) 1996, 1997, 2000, 2002, 2003, 2004 -+ Free Software Foundation, Inc. -+ This file is part of the GNU C Library. -+ -+ The GNU C Library is free software; you can redistribute it and/or -+ modify it under the terms of the GNU Lesser General Public -+ License as published by the Free Software Foundation; either -+ version 2.1 of the License, or (at your option) any later version. -+ -+ The GNU C Library is distributed in the hope that it will be useful, -+ but WITHOUT ANY WARRANTY; without even the implied warranty of -+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU -+ Lesser General Public License for more details. -+ -+ You should have received a copy of the GNU Lesser General Public -+ License along with the GNU C Library; if not, write to the Free -+ Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA -+ 02111-1307 USA. */ -+ -+#include -+#include -+ -+ENTRY (__longjmp) -+ REG_L ra, 0*SZREG(a0) -+ REG_L s0, 1*SZREG(a0) -+ REG_L s1, 2*SZREG(a0) -+ REG_L s2, 3*SZREG(a0) -+ REG_L s3, 4*SZREG(a0) -+ REG_L s4, 5*SZREG(a0) -+ REG_L s5, 6*SZREG(a0) -+ REG_L s6, 7*SZREG(a0) -+ REG_L s7, 8*SZREG(a0) -+ REG_L s8, 9*SZREG(a0) -+ REG_L s9, 10*SZREG(a0) -+ REG_L s10,11*SZREG(a0) -+ REG_L s11,12*SZREG(a0) -+ REG_L sp, 13*SZREG(a0) -+ REG_L tp, 14*SZREG(a0) -+ -+#ifdef __riscv_hard_float -+ REG_L a3, 15*SZREG(a0) -+ -+ fld fs0, 16*SZREG+ 0*8(a0) -+ fld fs1, 16*SZREG+ 1*8(a0) -+ fld fs2, 16*SZREG+ 2*8(a0) -+ fld fs3, 16*SZREG+ 3*8(a0) -+ fld fs4, 16*SZREG+ 4*8(a0) -+ fld fs5, 16*SZREG+ 5*8(a0) -+ fld fs6, 16*SZREG+ 6*8(a0) -+ fld fs7, 16*SZREG+ 7*8(a0) -+ fld fs8, 16*SZREG+ 8*8(a0) -+ fld fs9, 16*SZREG+ 9*8(a0) -+ fld fs10,16*SZREG+10*8(a0) -+ fld fs11,16*SZREG+11*8(a0) -+ fld fs12,16*SZREG+12*8(a0) -+ fld fs13,16*SZREG+13*8(a0) -+ fld fs14,16*SZREG+14*8(a0) -+ fld fs15,16*SZREG+15*8(a0) -+ -+ fssr a3 -+#endif -+ -+ sltu a3, a1, 1 # a3 = (a1 == 0) -+ add v0, a3, a1 # v0 = (a1 == 0 ? 1 : a1) -+ ret -+ -+END(__longjmp) -diff --git a/glibc-2.14.1/sysdeps/riscv/bits/atomic.h b/glibc-2.14.1/sysdeps/riscv/bits/atomic.h -new file mode 100644 -index 0000000..aaa62d7 ---- /dev/null -+++ glibc-2.14.1/sysdeps/riscv/bits/atomic.h -@@ -0,0 +1,151 @@ -+/* Low-level functions for atomic operations. Mips version. -+ Copyright (C) 2005 Free Software Foundation, Inc. -+ This file is part of the GNU C Library. -+ -+ The GNU C Library is free software; you can redistribute it and/or -+ modify it under the terms of the GNU Lesser General Public -+ License as published by the Free Software Foundation; either -+ version 2.1 of the License, or (at your option) any later version. -+ -+ The GNU C Library is distributed in the hope that it will be useful, -+ but WITHOUT ANY WARRANTY; without even the implied warranty of -+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU -+ Lesser General Public License for more details. -+ -+ You should have received a copy of the GNU Lesser General Public -+ License along with the GNU C Library; if not, write to the Free -+ Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA -+ 02111-1307 USA. */ -+ -+#ifndef _MIPS_BITS_ATOMIC_H -+#define _MIPS_BITS_ATOMIC_H 1 -+ -+#include -+#include -+ -+typedef int32_t atomic32_t; -+typedef uint32_t uatomic32_t; -+typedef int_fast32_t atomic_fast32_t; -+typedef uint_fast32_t uatomic_fast32_t; -+ -+typedef int64_t atomic64_t; -+typedef uint64_t uatomic64_t; -+typedef int_fast64_t atomic_fast64_t; -+typedef uint_fast64_t uatomic_fast64_t; -+ -+typedef intptr_t atomicptr_t; -+typedef uintptr_t uatomicptr_t; -+typedef intmax_t atomic_max_t; -+typedef uintmax_t uatomic_max_t; -+ -+#ifdef __riscv_atomic -+ -+#define asm_amo(which, ordering, mem, value) ({ \ -+ typeof(*mem) __tmp; \ -+ if (sizeof(__tmp) == 4) \ -+ asm volatile (which ".w" ordering "\t%0, %z1, (%2)" : "=r"(__tmp) : "rJ"(value), "r"(mem)); \ -+ else if (sizeof(__tmp) == 8) \ -+ asm volatile (which ".d" ordering "\t%0, %z1, (%2)" : "=r"(__tmp) : "rJ"(value), "r"(mem)); \ -+ else \ -+ abort(); \ -+ __tmp; }) -+ -+#define asm_load_reserved(ordering, mem) ({ \ -+ typeof(*mem) __tmp; \ -+ if (sizeof(__tmp) == 4) \ -+ asm volatile ("lr.w" ordering "\t%0, (%1)" : "=r"(__tmp) : "r"(mem)); \ -+ else if (sizeof(__tmp) == 8) \ -+ asm volatile ("lr.d" ordering "\t%0, (%1)" : "=r"(__tmp) : "r"(mem)); \ -+ else \ -+ abort(); \ -+ __tmp; }) -+ -+#define asm_store_conditional(ordering, mem, value) \ -+ asm_amo("sc", ordering, mem, value) -+ -+/* Atomic compare and exchange. */ -+ -+#define atomic_cas(ordering, mem, newval, oldval) ({ \ -+ typeof(*mem) __tmp; \ -+ int __tmp2; \ -+ if (sizeof(__tmp) == 4) \ -+ asm volatile ("1: lr.w" ordering "\t%0, (%2)\n" \ -+ "bne\t%0, %z4, 1f\n" \ -+ "sc.w" ordering "\t%1, %z3, (%2)\n" \ -+ "bnez\t%1, 1b\n" \ -+ "1:" \ -+ : "=&r"(__tmp), "=&r"(__tmp2) : "r"(mem), "rJ"(newval), "rJ"(oldval)); \ -+ else if (sizeof(__tmp) == 8) \ -+ asm volatile ("1: lr.d" ordering "\t%0, (%2)\n" \ -+ "bne\t%0, %z4, 1f\n" \ -+ "sc.d" ordering "\t%1, %z3, (%2)\n" \ -+ "bnez\t%1, 1b\n" \ -+ "1:" \ -+ : "=&r"(__tmp), "=&r"(__tmp2) : "r"(mem), "rJ"(newval), "rJ"(oldval)); \ -+ else \ -+ abort(); \ -+ __tmp; }) -+ -+#define atomic_cas_bool(ordering, mem, newval, oldval) ({ \ -+ __label__ failure, success; \ -+ typeof(*mem) __tmp; \ -+ int __res; \ -+ if (sizeof(__tmp) == 4) \ -+ asm goto ("1: lr.w" ordering "\tt3, (%0)\n" \ -+ "bne\tt3, %z2, %l[failure]\n" \ -+ "sc.w" ordering "\tt3, %z1, (%0)\n" \ -+ "bnez\tt3, 1b" \ -+ : : "r"(mem), "rJ"(newval), "rJ"(oldval) : "t3" : failure); \ -+ else if (sizeof(__tmp) == 8) \ -+ asm goto ("1: lr.d" ordering "\tt3, (%0)\n" \ -+ "bne\tt3, %z2, %l[failure]\n" \ -+ "sc.d" ordering "\tt3, %z1, (%0)\n" \ -+ "bnez\tt3, 1b" \ -+ : : "r"(mem), "rJ"(newval), "rJ"(oldval) : "t3" : failure); \ -+ else \ -+ abort(); \ -+ __res = 0; \ -+ goto success; \ -+failure: \ -+ __res = 1; \ -+success: \ -+ __res; }) -+ -+#define atomic_compare_and_exchange_val_acq(mem, newval, oldval) \ -+ atomic_cas(".aq", mem, newval, oldval) -+ -+#define atomic_compare_and_exchange_val_rel(mem, newval, oldval) \ -+ atomic_cas(".rl", mem, newval, oldval) -+ -+#define atomic_compare_and_exchange_bool_acq(mem, newval, oldval) \ -+ atomic_cas_bool(".aq", mem, newval, oldval) -+ -+#define atomic_compare_and_exchange_bool_rel(mem, newval, oldval) \ -+ atomic_cas_bool(".rl", mem, newval, oldval) -+ -+/* Atomic exchange (without compare). */ -+ -+#define atomic_exchange_acq(mem, value) asm_amo("amoswap", ".aq", mem, value) -+#define atomic_exchange_rel(mem, value) asm_amo("amoswap", ".rl", mem, value) -+ -+ -+/* Atomically add value and return the previous (unincremented) value. */ -+ -+#define atomic_exchange_and_add(mem, value) asm_amo("amoadd", "", mem, value) -+ -+#define atomic_max(mem, value) asm_amo("amomaxu", "", mem, value) -+#define atomic_min(mem, value) asm_amo("amominu", "", mem, value) -+ -+#define atomic_bit_test_set(mem, bit) \ -+ ({ typeof(*mem) __mask = (typeof(*mem))1 << (bit); \ -+ asm_amo("amoor", "", mem, __mask) & __mask; }) -+ -+#define atomic_full_barrier() __sync_synchronize() -+ -+#define catomic_exchange_and_add(mem, value) \ -+ atomic_exchange_and_add(mem, value) -+#define catomic_max(mem, value) atomic_max(mem, value) -+ -+#endif /* __riscv_atomic */ -+ -+#endif /* bits/atomic.h */ -diff --git a/glibc-2.14.1/sysdeps/riscv/bits/dlfcn.h b/glibc-2.14.1/sysdeps/riscv/bits/dlfcn.h -new file mode 100644 -index 0000000..a5b5bf5 ---- /dev/null -+++ glibc-2.14.1/sysdeps/riscv/bits/dlfcn.h -@@ -0,0 +1,66 @@ -+/* System dependent definitions for run-time dynamic loading. -+ Copyright (C) 1996, 1997, 1999, 2000, 2001, 2004 -+ Free Software Foundation, Inc. -+ This file is part of the GNU C Library. -+ -+ The GNU C Library is free software; you can redistribute it and/or -+ modify it under the terms of the GNU Lesser General Public -+ License as published by the Free Software Foundation; either -+ version 2.1 of the License, or (at your option) any later version. -+ -+ The GNU C Library is distributed in the hope that it will be useful, -+ but WITHOUT ANY WARRANTY; without even the implied warranty of -+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU -+ Lesser General Public License for more details. -+ -+ You should have received a copy of the GNU Lesser General Public -+ License along with the GNU C Library; if not, write to the Free -+ Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA -+ 02111-1307 USA. */ -+ -+#ifndef _DLFCN_H -+# error "Never use directly; include instead." -+#endif -+ -+/* The MODE argument to `dlopen' contains one of the following: */ -+#define RTLD_LAZY 0x0001 /* Lazy function call binding. */ -+#define RTLD_NOW 0x0002 /* Immediate function call binding. */ -+#define RTLD_BINDING_MASK 0x3 /* Mask of binding time value. */ -+#define RTLD_NOLOAD 0x00008 /* Do not load the object. */ -+#define RTLD_DEEPBIND 0x00010 /* Use deep binding. */ -+ -+/* If the following bit is set in the MODE argument to `dlopen', -+ the symbols of the loaded object and its dependencies are made -+ visible as if the object were linked directly into the program. */ -+#define RTLD_GLOBAL 0x0004 -+ -+/* Unix98 demands the following flag which is the inverse to RTLD_GLOBAL. -+ The implementation does this by default and so we can define the -+ value to zero. */ -+#define RTLD_LOCAL 0 -+ -+/* Do not delete object when closed. */ -+#define RTLD_NODELETE 0x01000 -+ -+#ifdef __USE_GNU -+/* To support profiling of shared objects it is a good idea to call -+ the function found using `dlsym' using the following macro since -+ these calls do not use the PLT. But this would mean the dynamic -+ loader has no chance to find out when the function is called. The -+ macro applies the necessary magic so that profiling is possible. -+ Rewrite -+ foo = (*fctp) (arg1, arg2); -+ into -+ foo = DL_CALL_FCT (fctp, (arg1, arg2)); -+*/ -+# define DL_CALL_FCT(fctp, args) \ -+ (_dl_mcount_wrapper_check ((void *) (fctp)), (*(fctp)) args) -+ -+__BEGIN_DECLS -+ -+/* This function calls the profiling functions. */ -+extern void _dl_mcount_wrapper_check (void *__selfpc) __THROW; -+ -+__END_DECLS -+ -+#endif -diff --git a/glibc-2.14.1/sysdeps/riscv/bits/endian.h b/glibc-2.14.1/sysdeps/riscv/bits/endian.h -new file mode 100644 -index 0000000..4aaf559 ---- /dev/null -+++ glibc-2.14.1/sysdeps/riscv/bits/endian.h -@@ -0,0 +1,5 @@ -+#ifndef _ENDIAN_H -+# error "Never use directly; include instead." -+#endif -+ -+#define __BYTE_ORDER __LITTLE_ENDIAN -diff --git a/glibc-2.14.1/sysdeps/riscv/bits/fenv.h b/glibc-2.14.1/sysdeps/riscv/bits/fenv.h -new file mode 100644 -index 0000000..0ccf5cb ---- /dev/null -+++ glibc-2.14.1/sysdeps/riscv/bits/fenv.h -@@ -0,0 +1,57 @@ -+/* Copyright (C) 1998, 1999, 2000 Free Software Foundation, Inc. -+ This file is part of the GNU C Library. -+ -+ The GNU C Library is free software; you can redistribute it and/or -+ modify it under the terms of the GNU Lesser General Public -+ License as published by the Free Software Foundation; either -+ version 2.1 of the License, or (at your option) any later version. -+ -+ The GNU C Library is distributed in the hope that it will be useful, -+ but WITHOUT ANY WARRANTY; without even the implied warranty of -+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU -+ Lesser General Public License for more details. -+ -+ You should have received a copy of the GNU Lesser General Public -+ License along with the GNU C Library; if not, write to the Free -+ Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA -+ 02111-1307 USA. */ -+ -+#ifndef _FENV_H -+# error "Never use directly; include instead." -+#endif -+ -+enum -+ { -+ FE_INEXACT = 0x01, -+#define FE_INEXACT FE_INEXACT -+ FE_UNDERFLOW = 0x02, -+#define FE_UNDERFLOW FE_UNDERFLOW -+ FE_OVERFLOW = 0x04, -+#define FE_OVERFLOW FE_OVERFLOW -+ FE_DIVBYZERO = 0x08, -+#define FE_DIVBYZERO FE_DIVBYZERO -+ FE_INVALID = 0x10, -+#define FE_INVALID FE_INVALID -+ }; -+ -+#define FE_ALL_EXCEPT \ -+ (FE_INEXACT | FE_DIVBYZERO | FE_UNDERFLOW | FE_OVERFLOW | FE_INVALID) -+ -+enum -+ { -+ FE_TONEAREST = 0x0, -+#define FE_TONEAREST FE_TONEAREST -+ FE_TOWARDZERO = 0x1, -+#define FE_TOWARDZERO FE_TOWARDZERO -+ FE_DOWNWARD = 0x2, -+#define FE_DOWNWARD FE_DOWNWARD -+ FE_UPWARD = 0x3 -+#define FE_UPWARD FE_UPWARD -+ }; -+ -+ -+typedef unsigned int fexcept_t; -+typedef unsigned int fenv_t; -+ -+/* If the default argument is used we use this value. */ -+#define FE_DFL_ENV ((__const fenv_t *) -1) -diff --git a/glibc-2.14.1/sysdeps/riscv/bits/ipctypes.h b/glibc-2.14.1/sysdeps/riscv/bits/ipctypes.h -new file mode 100644 -index 0000000..0956e7d ---- /dev/null -+++ glibc-2.14.1/sysdeps/riscv/bits/ipctypes.h -@@ -0,0 +1,32 @@ -+/* bits/ipctypes.h -- Define some types used by SysV IPC/MSG/SHM. MIPS version -+ Copyright (C) 2002 Free Software Foundation, Inc. -+ This file is part of the GNU C Library. -+ -+ The GNU C Library is free software; you can redistribute it and/or -+ modify it under the terms of the GNU Lesser General Public -+ License as published by the Free Software Foundation; either -+ version 2.1 of the License, or (at your option) any later version. -+ -+ The GNU C Library is distributed in the hope that it will be useful, -+ but WITHOUT ANY WARRANTY; without even the implied warranty of -+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU -+ Lesser General Public License for more details. -+ -+ You should have received a copy of the GNU Lesser General Public -+ License along with the GNU C Library; if not, write to the Free -+ Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA -+ 02111-1307 USA. */ -+ -+/* -+ * Never include directly. -+ */ -+ -+#ifndef _BITS_IPCTYPES_H -+#define _BITS_IPCTYPES_H 1 -+ -+#include -+ -+typedef __SLONG32_TYPE __ipc_pid_t; -+ -+ -+#endif /* bits/ipctypes.h */ -diff --git a/glibc-2.14.1/sysdeps/riscv/bits/link.h b/glibc-2.14.1/sysdeps/riscv/bits/link.h -new file mode 100644 -index 0000000..f216ebd ---- /dev/null -+++ glibc-2.14.1/sysdeps/riscv/bits/link.h -@@ -0,0 +1,76 @@ -+/* Copyright (C) 2005, 2009 Free Software Foundation, Inc. -+ This file is part of the GNU C Library. -+ -+ The GNU C Library is free software; you can redistribute it and/or -+ modify it under the terms of the GNU Lesser General Public -+ License as published by the Free Software Foundation; either -+ version 2.1 of the License, or (at your option) any later version. -+ -+ The GNU C Library is distributed in the hope that it will be useful, -+ but WITHOUT ANY WARRANTY; without even the implied warranty of -+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU -+ Lesser General Public License for more details. -+ -+ You should have received a copy of the GNU Lesser General Public -+ License along with the GNU C Library; if not, write to the Free -+ Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA -+ 02111-1307 USA. */ -+ -+#ifndef _LINK_H -+# error "Never include directly; use instead." -+#endif -+ -+typedef struct La_mips_64_regs -+{ -+ unsigned long lr_reg[8]; /* $a0 through $a7 */ -+ double lr_fpreg[8]; /* $f4 throgh $f11 */ -+ unsigned long lr_ra; -+ unsigned long lr_sp; -+} La_mips_64_regs; -+ -+/* Return values for calls from PLT on MIPS. */ -+typedef struct La_mips_64_retval -+{ -+ unsigned long lrv_v0; -+ unsigned long lrv_v1; -+ double lrv_fv0; -+ double lrv_fv1; -+} La_mips_64_retval; -+ -+__BEGIN_DECLS -+ -+#if _RISCV_SIM == _ABI32 -+ -+extern Elf32_Addr la_mips_n32_gnu_pltenter (Elf32_Sym *__sym, unsigned int __ndx, -+ uintptr_t *__refcook, -+ uintptr_t *__defcook, -+ La_mips_64_regs *__regs, -+ unsigned int *__flags, -+ const char *__symname, -+ long int *__framesizep); -+extern unsigned int la_mips_n32_gnu_pltexit (Elf32_Sym *__sym, unsigned int __ndx, -+ uintptr_t *__refcook, -+ uintptr_t *__defcook, -+ const La_mips_64_regs *__inregs, -+ La_mips_64_retval *__outregs, -+ const char *__symname); -+ -+#else -+ -+extern Elf64_Addr la_mips_n64_gnu_pltenter (Elf64_Sym *__sym, unsigned int __ndx, -+ uintptr_t *__refcook, -+ uintptr_t *__defcook, -+ La_mips_64_regs *__regs, -+ unsigned int *__flags, -+ const char *__symname, -+ long int *__framesizep); -+extern unsigned int la_mips_n64_gnu_pltexit (Elf64_Sym *__sym, unsigned int __ndx, -+ uintptr_t *__refcook, -+ uintptr_t *__defcook, -+ const La_mips_64_regs *__inregs, -+ La_mips_64_retval *__outregs, -+ const char *__symname); -+ -+#endif -+ -+__END_DECLS -diff --git a/glibc-2.14.1/sysdeps/riscv/bits/linkmap.h b/glibc-2.14.1/sysdeps/riscv/bits/linkmap.h -new file mode 100644 -index 0000000..a6df782 ---- /dev/null -+++ glibc-2.14.1/sysdeps/riscv/bits/linkmap.h -@@ -0,0 +1,4 @@ -+struct link_map_machine -+ { -+ ElfW(Addr) plt; /* Address of .plt */ -+ }; -diff --git a/glibc-2.14.1/sysdeps/riscv/bits/mathdef.h b/glibc-2.14.1/sysdeps/riscv/bits/mathdef.h -new file mode 100644 -index 0000000..1fef80f ---- /dev/null -+++ glibc-2.14.1/sysdeps/riscv/bits/mathdef.h -@@ -0,0 +1,45 @@ -+/* Copyright (C) 1997, 1998, 1999, 2000, 2002, 2003, 2004, 2007 -+ Free Software Foundation, Inc. -+ This file is part of the GNU C Library. -+ -+ The GNU C Library is free software; you can redistribute it and/or -+ modify it under the terms of the GNU Lesser General Public -+ License as published by the Free Software Foundation; either -+ version 2.1 of the License, or (at your option) any later version. -+ -+ The GNU C Library is distributed in the hope that it will be useful, -+ but WITHOUT ANY WARRANTY; without even the implied warranty of -+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU -+ Lesser General Public License for more details. -+ -+ You should have received a copy of the GNU Lesser General Public -+ License along with the GNU C Library; if not, write to the Free -+ Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA -+ 02111-1307 USA. */ -+ -+#if !defined _MATH_H && !defined _COMPLEX_H -+# error "Never use directly; include instead" -+#endif -+ -+#include -+ -+#if defined __USE_ISOC99 && defined _MATH_H && !defined _MATH_H_MATHDEF -+# define _MATH_H_MATHDEF 1 -+ -+/* MIPS has `float' and `double' operations. */ -+typedef float float_t; /* `float' expressions are evaluated as -+ `float'. */ -+typedef double double_t; /* `double' expressions are evaluated as -+ `double'. */ -+ -+/* The values returned by `ilogb' for 0 and NaN respectively. */ -+# define FP_ILOGB0 (-2147483647) -+# define FP_ILOGBNAN 2147483647 -+ -+#endif /* ISO C99 */ -+ -+#if ! defined __NO_LONG_DOUBLE_MATH -+/* Signal that we do not really have a `long double'. This disables the -+ declaration of all the `long double' function variants. */ -+# define __NO_LONG_DOUBLE_MATH 1 -+#endif -diff --git a/glibc-2.14.1/sysdeps/riscv/bits/nan.h b/glibc-2.14.1/sysdeps/riscv/bits/nan.h -new file mode 100644 -index 0000000..baaaa55 ---- /dev/null -+++ glibc-2.14.1/sysdeps/riscv/bits/nan.h -@@ -0,0 +1,56 @@ -+/* `NAN' constant for IEEE 754 machines. -+ Copyright (C) 1992, 1996, 1997, 1999, 2002, 2004 -+ Free Software Foundation, Inc. -+ This file is part of the GNU C Library. -+ -+ The GNU C Library is free software; you can redistribute it and/or -+ modify it under the terms of the GNU Lesser General Public -+ License as published by the Free Software Foundation; either -+ version 2.1 of the License, or (at your option) any later version. -+ -+ The GNU C Library is distributed in the hope that it will be useful, -+ but WITHOUT ANY WARRANTY; without even the implied warranty of -+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU -+ Lesser General Public License for more details. -+ -+ You should have received a copy of the GNU Lesser General Public -+ License along with the GNU C Library; if not, write to the Free -+ Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA -+ 02111-1307 USA. */ -+ -+#ifndef _MATH_H -+# error "Never use directly; include instead." -+#endif -+ -+ -+/* IEEE Not A Number (QNaN). Note that MIPS has the QNaN and SNaN patterns -+ reversed compared to most other architectures. The IEEE spec left -+ the definition of this open to implementations, and for MIPS the top -+ bit of the mantissa must be SET to indicate a SNaN. */ -+ -+#if __GNUC_PREREQ(3,3) -+ -+# define NAN (__builtin_nanf("")) -+ -+#elif defined __GNUC__ -+ -+# define NAN \ -+ (__extension__ \ -+ ((union { unsigned __l __attribute__((__mode__(__SI__))); float __d; }) \ -+ { __l: 0x7fbfffffUL }).__d) -+ -+#else -+ -+# include -+ -+# if __BYTE_ORDER == __BIG_ENDIAN -+# define __nan_bytes { 0x7f, 0xbf, 0xff, 0xff } -+# endif -+# if __BYTE_ORDER == __LITTLE_ENDIAN -+# define __nan_bytes { 0xff, 0xff, 0xbf, 0x7f } -+# endif -+ -+static union { unsigned char __c[4]; float __d; } __nan_union = { __nan_bytes }; -+# define NAN (__nan_union.__d) -+ -+#endif /* GCC. */ -diff --git a/glibc-2.14.1/sysdeps/riscv/bits/setjmp.h b/glibc-2.14.1/sysdeps/riscv/bits/setjmp.h -new file mode 100644 -index 0000000..52e2d3d ---- /dev/null -+++ glibc-2.14.1/sysdeps/riscv/bits/setjmp.h -@@ -0,0 +1,43 @@ -+/* Define the machine-dependent type `jmp_buf'. RISC-V version. -+ Copyright (C) 1992,1993,1995,1997,2000,2002,2003,2004,2005,2006 -+ Free Software Foundation, Inc. -+ This file is part of the GNU C Library. -+ -+ The GNU C Library is free software; you can redistribute it and/or -+ modify it under the terms of the GNU Lesser General Public -+ License as published by the Free Software Foundation; either -+ version 2.1 of the License, or (at your option) any later version. -+ -+ The GNU C Library is distributed in the hope that it will be useful, -+ but WITHOUT ANY WARRANTY; without even the implied warranty of -+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU -+ Lesser General Public License for more details. -+ -+ You should have received a copy of the GNU Lesser General Public -+ License along with the GNU C Library; if not, write to the Free -+ Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA -+ 02111-1307 USA. */ -+ -+#ifndef _RISCV_BITS_SETJMP_H -+#define _RISCV_BITS_SETJMP_H -+ -+typedef struct __jmp_buf_internal_tag -+ { -+ /* Program counter. */ -+ long __pc; -+ /* Callee-saved registers. */ -+ long __regs[12]; -+ /* Stack pointer. */ -+ long __sp; -+ /* Thread pointer. */ -+ long __tp; -+ /* Floating point status register. */ -+ long __fsr; -+ -+ /* Callee-saved floating point registers. -+ Note that there are an even number of preceding words in this struct, -+ so no padding will be inserted before __fpregs, even for RV32. */ -+ double __fpregs[16]; -+ } __jmp_buf[1]; -+ -+#endif /* _RISCV_BITS_SETJMP_H */ -diff --git a/glibc-2.14.1/sysdeps/riscv/bits/string.h b/glibc-2.14.1/sysdeps/riscv/bits/string.h -new file mode 100644 -index 0000000..5f9dca5 ---- /dev/null -+++ glibc-2.14.1/sysdeps/riscv/bits/string.h -@@ -0,0 +1,55 @@ -+/* This file should provide inline versions of string functions. -+ -+ Surround GCC-specific parts with #ifdef __GNUC__, and use `__extern_inline'. -+ -+ This file should define __STRING_INLINES if functions are actually defined -+ as inlines. */ -+ -+#ifndef _BITS_STRING_H -+#define _BITS_STRING_H 1 -+ -+#if defined(__GNUC__) && !defined(__cplusplus) -+ -+static inline unsigned long __libc_detect_null(unsigned long w) -+{ -+ unsigned long mask = 0x7f7f7f7f; -+ if (sizeof(long) == 8) -+ mask = ((mask << 16) << 16) | mask; -+ return ~(((w & mask) + mask) | w | mask); -+} -+ -+#define _HAVE_STRING_ARCH_memcpy 1 -+#define __use_memcpy_align(k, d, s, n) \ -+ (__builtin_constant_p(n) && (n) % (k) == 0 && (n) <= 64 && \ -+ __alignof__(*(d)) >= (k) && __alignof__(*(s)) >= (k)) -+#define memcpy(d, s, n) \ -+ (__use_memcpy_align(8, d, s, n) ? __memcpy_align8(d, s, n) : \ -+ __use_memcpy_align(4, d, s, n) ? __memcpy_align4(d, s, n) : \ -+ __memcpy_g(d, s, n)) -+ -+#define __declare_memcpy_align(size, type) \ -+ static inline void *__memcpy_align ## size(void *__restrict __dest, \ -+ __const void *__restrict __src, size_t __n) { \ -+ type *__d = (type*)__dest; \ -+ const type *__s = (const type*)__src, *__e = (const type*)(__src + __n); \ -+ while (__s < __e) { \ -+ type __t = *__s; \ -+ __d++, __s++; \ -+ *(__d-1) = __t; \ -+ } \ -+ return __dest; \ -+ } -+__declare_memcpy_align(8, long long) -+__declare_memcpy_align(4, int) -+ -+#ifdef _LIBC -+extern void *__memcpy_g (void *__restrict __dest, -+ __const void *__restrict __src, size_t __n); -+libc_hidden_proto (__memcpy_g) -+#else -+# define __memcpy_g memcpy -+#endif -+ -+#endif /* __GNUC__ && !__cplusplus */ -+ -+#endif /* bits/string.h */ -diff --git a/glibc-2.14.1/sysdeps/riscv/bits/wordsize.h b/glibc-2.14.1/sysdeps/riscv/bits/wordsize.h -new file mode 100644 -index 0000000..f956c87 ---- /dev/null -+++ glibc-2.14.1/sysdeps/riscv/bits/wordsize.h -@@ -0,0 +1,22 @@ -+/* Copyright (C) 2002, 2003 Free Software Foundation, Inc. -+ This file is part of the GNU C Library. -+ -+ The GNU C Library is free software; you can redistribute it and/or -+ modify it under the terms of the GNU Lesser General Public -+ License as published by the Free Software Foundation; either -+ version 2.1 of the License, or (at your option) any later version. -+ -+ The GNU C Library is distributed in the hope that it will be useful, -+ but WITHOUT ANY WARRANTY; without even the implied warranty of -+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU -+ Lesser General Public License for more details. -+ -+ You should have received a copy of the GNU Lesser General Public -+ License along with the GNU C Library; if not, write to the Free -+ Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA -+ 02111-1307 USA. */ -+ -+#define __WORDSIZE _RISCV_SZPTR -+#if _RISCV_SIM == _ABI64 -+# define __WORDSIZE_COMPAT32 1 -+#endif -diff --git a/glibc-2.14.1/sysdeps/riscv/bsd-_setjmp.c b/glibc-2.14.1/sysdeps/riscv/bsd-_setjmp.c -new file mode 100644 -index 0000000..0d41310 ---- /dev/null -+++ glibc-2.14.1/sysdeps/riscv/bsd-_setjmp.c -@@ -0,0 +1 @@ -+/* _setjmp is implemented in setjmp.S */ -diff --git a/glibc-2.14.1/sysdeps/riscv/bsd-setjmp.c b/glibc-2.14.1/sysdeps/riscv/bsd-setjmp.c -new file mode 100644 -index 0000000..ee7c5e3 ---- /dev/null -+++ glibc-2.14.1/sysdeps/riscv/bsd-setjmp.c -@@ -0,0 +1 @@ -+/* setjmp is implemented in setjmp.S */ -diff --git a/glibc-2.14.1/sysdeps/riscv/dl-dtprocnum.h b/glibc-2.14.1/sysdeps/riscv/dl-dtprocnum.h -new file mode 100644 -index 0000000..adf8dfa ---- /dev/null -+++ glibc-2.14.1/sysdeps/riscv/dl-dtprocnum.h -@@ -0,0 +1,33 @@ -+/* Configuration of lookup functions. MIPS version. -+ Copyright (C) 2000 Free Software Foundation, Inc. -+ This file is part of the GNU C Library. -+ -+ The GNU C Library is free software; you can redistribute it and/or -+ modify it under the terms of the GNU Lesser General Public -+ License as published by the Free Software Foundation; either -+ version 2.1 of the License, or (at your option) any later version. -+ -+ The GNU C Library is distributed in the hope that it will be useful, -+ but WITHOUT ANY WARRANTY; without even the implied warranty of -+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU -+ Lesser General Public License for more details. -+ -+ You should have received a copy of the GNU Lesser General Public -+ License along with the GNU C Library; if not, write to the Free -+ Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA -+ 02111-1307 USA. */ -+ -+/* Number of local global offset table entries. */ -+#define DT_RISCV_LOCAL_GOTNO 0x70000000 -+ -+/* Number of entries in the .dynsym section. */ -+#define DT_RISCV_SYMTABNO 0x70000001 -+ -+/* Index of first dynamic symbol in global offset table. */ -+#define DT_RISCV_GOTSYM 0x70000002 -+ -+/* Address of the base of the PLTGOT. */ -+#define DT_RISCV_PLTGOT 0x70000003 -+ -+/* Number of extra dynamic section entries for this architecture. */ -+#define DT_THISPROCNUM 4 -diff --git a/glibc-2.14.1/sysdeps/riscv/dl-machine.h b/glibc-2.14.1/sysdeps/riscv/dl-machine.h -new file mode 100644 -index 0000000..414af3f ---- /dev/null -+++ glibc-2.14.1/sysdeps/riscv/dl-machine.h -@@ -0,0 +1,559 @@ -+/* Machine-dependent ELF dynamic relocation inline functions. MIPS version. -+ Copyright (C) 1996-2001, 2002, 2003, 2004, 2005, 2006, 2007 -+ Free Software Foundation, Inc. -+ This file is part of the GNU C Library. -+ Contributed by Kazumoto Kojima . -+ -+ The GNU C Library is free software; you can redistribute it and/or -+ modify it under the terms of the GNU Lesser General Public -+ License as published by the Free Software Foundation; either -+ version 2.1 of the License, or (at your option) any later version. -+ -+ The GNU C Library is distributed in the hope that it will be useful, -+ but WITHOUT ANY WARRANTY; without even the implied warranty of -+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU -+ Lesser General Public License for more details. -+ -+ You should have received a copy of the GNU Lesser General Public -+ License along with the GNU C Library; if not, write to the Free -+ Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA -+ 02111-1307 USA. */ -+ -+/* FIXME: Profiling of shared libraries is not implemented yet. */ -+#ifndef dl_machine_h -+#define dl_machine_h -+ -+#define ELF_MACHINE_NAME "RISC-V" -+ -+/* Relocs. */ -+#define R_RISCV_COPY 24 -+#define R_RISCV_JUMP_SLOT 25 -+#define R_RISCV_TLS_DTPMOD32 38 -+#define R_RISCV_TLS_DTPREL32 39 -+#define R_RISCV_TLS_DTPMOD64 40 -+#define R_RISCV_TLS_DTPREL64 41 -+#define R_RISCV_TLS_TPREL32 47 -+#define R_RISCV_TLS_TPREL64 48 -+ -+#include -+ -+#ifndef ENTRY_POINT -+#error ENTRY_POINT needs to be defined for MIPS. -+#endif -+ -+#include -+#include -+ -+#ifndef _RTLD_PROLOGUE -+# define _RTLD_PROLOGUE(entry) \ -+ ".globl\t" __STRING(entry) "\n\t" \ -+ ".type\t" __STRING(entry) ", @function\n" \ -+ __STRING(entry) ":\n\t" -+#endif -+ -+#ifndef _RTLD_EPILOGUE -+# define _RTLD_EPILOGUE(entry) \ -+ ".size\t" __STRING(entry) ", . - " __STRING(entry) "\n\t" -+#endif -+ -+/* A reloc type used for ld.so cmdline arg lookups to reject PLT entries. -+ This only makes sense on MIPS when using PLTs, so choose the -+ PLT relocation (not encountered when not using PLTs). */ -+#define ELF_MACHINE_JMP_SLOT R_RISCV_JUMP_SLOT -+#define elf_machine_type_class(type) \ -+ ((ELF_RTYPE_CLASS_PLT * ((type) == ELF_MACHINE_JMP_SLOT \ -+ || _RISCV_SZPTR == 32 && (type) == R_RISCV_TLS_DTPREL32 \ -+ || _RISCV_SZPTR == 32 && (type) == R_RISCV_TLS_DTPMOD32 \ -+ || _RISCV_SZPTR == 32 && (type) == R_RISCV_TLS_TPREL32 \ -+ || _RISCV_SZPTR == 64 && (type) == R_RISCV_TLS_DTPREL64 \ -+ || _RISCV_SZPTR == 64 && (type) == R_RISCV_TLS_DTPMOD64 \ -+ || _RISCV_SZPTR == 64 && (type) == R_RISCV_TLS_TPREL64)) \ -+ | (ELF_RTYPE_CLASS_COPY * ((type) == R_RISCV_COPY))) -+ -+#define ELF_MACHINE_NO_RELA 1 -+ -+/* Translate a processor specific dynamic tag to the index -+ in l_info array. */ -+#define DT_RISCV(x) (DT_RISCV_##x - DT_LOPROC + DT_NUM) -+ -+#define ELF_MACHINE_DEBUG_SETUP(l,r) -+ -+/* Return nonzero iff ELF header is compatible with the running host. */ -+static inline int __attribute_used__ -+elf_machine_matches_host (const ElfW(Ehdr) *ehdr) -+{ -+ return 1; -+} -+ -+/* Return the link-time address of _DYNAMIC. Conveniently, this is the -+ first element of the GOT. This must be inlined in a function which -+ uses global data. */ -+static inline ElfW(Addr) -+elf_machine_dynamic (void) -+{ -+ extern ElfW(Addr) _GLOBAL_OFFSET_TABLE_ __attribute__ ((visibility("hidden"))); -+ return _GLOBAL_OFFSET_TABLE_; -+} -+ -+#define STRINGXP(X) __STRING(X) -+#define STRINGXV(X) STRINGV_(X) -+#define STRINGV_(...) # __VA_ARGS__ -+ -+/* Return the run-time load address of the shared object. */ -+static inline ElfW(Addr) -+elf_machine_load_address (void) -+{ -+ /* Subtract the link-time address of _DYNAMIC from its runtime address. */ -+ extern ElfW(Dyn) _DYNAMIC[] __attribute__ ((visibility("hidden"))); -+ return (char*)&_DYNAMIC - elf_machine_dynamic (); -+} -+ -+/* We can't rely on elf_machine_got_rel because _dl_object_relocation_scope -+ fiddles with global data. */ -+#define ELF_MACHINE_BEFORE_RTLD_RELOC(dynamic_info) \ -+do { \ -+ struct link_map *map = &bootstrap_map; \ -+ ElfW(Sym) *sym; \ -+ ElfW(Addr) *got; \ -+ int i, n; \ -+ \ -+ got = (ElfW(Addr) *) D_PTR (map, l_info[DT_PLTGOT]); \ -+ \ -+ if (__builtin_expect (map->l_addr == 0, 1)) \ -+ break; \ -+ \ -+ i = 2; /* got[0] and got[1] are reserved. */ \ -+ n = map->l_info[DT_RISCV (LOCAL_GOTNO)]->d_un.d_val; \ -+ \ -+ /* Add the run-time displacement to all local got entries. */ \ -+ while (i < n) \ -+ got[i++] += map->l_addr; \ -+ \ -+ /* Handle global got entries. */ \ -+ got += n; \ -+ sym = (ElfW(Sym) *) D_PTR(map, l_info[DT_SYMTAB]) \ -+ + map->l_info[DT_RISCV (GOTSYM)]->d_un.d_val; \ -+ i = (map->l_info[DT_RISCV (SYMTABNO)]->d_un.d_val \ -+ - map->l_info[DT_RISCV (GOTSYM)]->d_un.d_val); \ -+ \ -+ while (i--) \ -+ { \ -+ if (sym->st_shndx == SHN_UNDEF || sym->st_shndx == SHN_COMMON) \ -+ *got = map->l_addr + sym->st_value; \ -+ else if (ELFW(ST_TYPE) (sym->st_info) == STT_FUNC \ -+ && *got != sym->st_value) \ -+ *got += map->l_addr; \ -+ else if (ELFW(ST_TYPE) (sym->st_info) == STT_SECTION) \ -+ { \ -+ if (sym->st_other == 0) \ -+ *got += map->l_addr; \ -+ } \ -+ else \ -+ *got = map->l_addr + sym->st_value; \ -+ \ -+ got++; \ -+ sym++; \ -+ } \ -+} while(0) -+ -+/* Initial entry point code for the dynamic linker. -+ The C function `_dl_start' is the real entry point; -+ its return value is the user program's entry point. */ -+ -+#define RTLD_START asm (\ -+ ".text\n\ -+ " _RTLD_PROLOGUE(ENTRY_POINT) "\ -+ # Store &_DYNAMIC in the first entry of the GOT.\n\ -+ la a0, _DYNAMIC\n\ -+ " STRINGXP(REG_S) " a0, _GLOBAL_OFFSET_TABLE_, a1\n\ -+ move a0, sp\n\ -+ jal _dl_start\n\ -+ # Stash user entry point in s0.\n\ -+ move s0, v0\n\ -+ # See if we were run as a command with the executable file\n\ -+ # name as an extra leading argument.\n\ -+ lw v0, _dl_skip_args\n\ -+ # Load the original argument count.\n\ -+ " STRINGXP(REG_L) " a1, 0(sp)\n\ -+ # Subtract _dl_skip_args from it.\n\ -+ sub a1, a1, v0\n\ -+ # Adjust the stack pointer to skip _dl_skip_args words.\n\ -+ sll v0, v0, " STRINGXP (PTRLOG) "\n\ -+ add sp, sp, v0\n\ -+ # Save back the modified argument count.\n\ -+ " STRINGXP(REG_S) " a1, 0(sp)\n\ -+ # Call _dl_init (struct link_map *main_map, int argc, char **argv, char **env) \n\ -+ " STRINGXP(REG_L) " a0, _rtld_local\n\ -+ add a2, sp, " STRINGXP (SZREG) "\n\ -+ sll a3, a1, " STRINGXP (PTRLOG) "\n\ -+ add a3, a3, a2\n\ -+ add a3, a3, " STRINGXP (SZREG) "\n\ -+ # Call the function to run the initializers.\n\ -+ jal _dl_init_internal\n\ -+ # Pass our finalizer function to the user in v0 as per ELF ABI.\n\ -+ lla v0, _dl_fini\n\ -+ # Jump to the user entry point.\n\ -+ jr s0\n\ -+ " _RTLD_EPILOGUE(ENTRY_POINT) "\ -+ .previous" \ -+); -+ -+/* Names of the architecture-specific auditing callback functions. */ -+# ifdef __riscv64 -+# define ARCH_LA_PLTENTER mips_n64_gnu_pltenter -+# define ARCH_LA_PLTEXIT mips_n64_gnu_pltexit -+# else -+# define ARCH_LA_PLTENTER mips_n32_gnu_pltenter -+# define ARCH_LA_PLTEXIT mips_n32_gnu_pltexit -+# endif -+ -+/* Bias .got.plt entry by the offset requested by the PLT header. */ -+#define elf_machine_plt_value(map, reloc, value) (value) -+#define elf_machine_fixup_plt(map, t, reloc, reloc_addr, value) \ -+ (*(ElfW(Addr) *)(reloc_addr) = (value)) -+ -+#endif /* !dl_machine_h */ -+ -+#ifdef RESOLVE_MAP -+ -+/* Perform a relocation described by R_INFO at the location pointed to -+ by RELOC_ADDR. SYM is the relocation symbol specified by R_INFO and -+ MAP is the object containing the reloc. */ -+ -+auto inline void -+__attribute__ ((always_inline)) -+elf_machine_rel (struct link_map *map, const ElfW(Rel) *reloc, -+ const ElfW(Sym) *sym, const struct r_found_version *version, -+ void *const reloc_addr) -+{ -+ ElfW(Addr) r_info = reloc->r_info; -+ const unsigned long int r_type = ELFW(R_TYPE) (r_info); -+ ElfW(Addr) *addr_field = (ElfW(Addr) *) reloc_addr; -+ -+#if !defined RTLD_BOOTSTRAP && !defined SHARED -+ /* This is defined in rtld.c, but nowhere in the static libc.a; -+ make the reference weak so static programs can still link. This -+ declaration cannot be done when compiling rtld.c (i.e. #ifdef -+ RTLD_BOOTSTRAP) because rtld.c contains the common defn for -+ _dl_rtld_map, which is incompatible with a weak decl in the same -+ file. */ -+ weak_extern (GL(dl_rtld_map)); -+#endif -+ -+ switch (r_type) -+ { -+#if defined (USE_TLS) && !defined (RTLD_BOOTSTRAP) -+# if _RISCV_SIM == _ABI64 -+ case R_MIPS_TLS_DTPMOD64: -+ case R_MIPS_TLS_DTPREL64: -+ case R_MIPS_TLS_TPREL64: -+# else -+ case R_MIPS_TLS_DTPMOD32: -+ case R_MIPS_TLS_DTPREL32: -+ case R_MIPS_TLS_TPREL32: -+# endif -+ { -+ struct link_map *sym_map = RESOLVE_MAP (&sym, version, r_type); -+ -+ switch (r_type) -+ { -+ case R_MIPS_TLS_DTPMOD64: -+ case R_MIPS_TLS_DTPMOD32: -+ if (sym_map) -+ *addr_field = sym_map->l_tls_modid; -+ break; -+ -+ case R_MIPS_TLS_DTPREL64: -+ case R_MIPS_TLS_DTPREL32: -+ if (sym) -+ *addr_field += TLS_DTPREL_VALUE (sym); -+ break; -+ -+ case R_MIPS_TLS_TPREL32: -+ case R_MIPS_TLS_TPREL64: -+ if (sym) -+ { -+ CHECK_STATIC_TLS (map, sym_map); -+ *addr_field += TLS_TPREL_VALUE (sym_map, sym); -+ } -+ break; -+ } -+ -+ break; -+ } -+#endif -+ -+ case R_MIPS_REL32: -+ { -+ int symidx = ELFW(R_SYM) (r_info); -+ -+ if (symidx) -+ { -+ const ElfW(Word) gotsym -+ = (const ElfW(Word)) map->l_info[DT_RISCV (GOTSYM)]->d_un.d_val; -+ -+ if ((ElfW(Word))symidx < gotsym) -+ { -+ /* This wouldn't work for a symbol imported from other -+ libraries for which there's no GOT entry, but MIPS -+ requires every symbol referenced in a dynamic -+ relocation to have a GOT entry in the primary GOT, -+ so we only get here for locally-defined symbols. -+ For section symbols, we should *NOT* be adding -+ sym->st_value (per the definition of the meaning of -+ S in reloc expressions in the ELF64 MIPS ABI), -+ since it should have already been added to -+ reloc_value by the linker, but older versions of -+ GNU ld didn't add it, and newer versions don't emit -+ useless relocations to section symbols any more, so -+ it is safe to keep on adding sym->st_value, even -+ though it's not ABI compliant. Some day we should -+ bite the bullet and stop doing this. */ -+#ifndef RTLD_BOOTSTRAP -+ if (map != &GL(dl_rtld_map)) -+#endif -+ if (sym->st_value + map->l_addr) -+ *addr_field += sym->st_value + map->l_addr; -+ } -+ else -+ { -+#ifndef RTLD_BOOTSTRAP -+ const ElfW(Addr) *got -+ = (const ElfW(Addr) *) D_PTR (map, l_info[DT_PLTGOT]); -+ const ElfW(Word) local_gotno -+ = (const ElfW(Word)) -+ map->l_info[DT_RISCV (LOCAL_GOTNO)]->d_un.d_val; -+ -+ *addr_field += got[symidx + local_gotno - gotsym]; -+#endif -+ } -+ } -+ else -+#ifndef RTLD_BOOTSTRAP -+ if (map != &GL(dl_rtld_map)) -+#endif -+ if (map->l_addr) -+ *addr_field += map->l_addr; -+ } -+ break; -+#ifndef RTLD_BOOTSTRAP -+ case R_MIPS_GLOB_DAT: -+ { -+ int symidx = ELFW(R_SYM) (r_info); -+ const ElfW(Word) gotsym -+ = (const ElfW(Word)) map->l_info[DT_RISCV (GOTSYM)]->d_un.d_val; -+ -+ if (__builtin_expect ((ElfW(Word)) symidx >= gotsym, 1)) -+ { -+ const ElfW(Addr) *got -+ = (const ElfW(Addr) *) D_PTR (map, l_info[DT_PLTGOT]); -+ const ElfW(Word) local_gotno -+ = ((const ElfW(Word)) -+ map->l_info[DT_RISCV (LOCAL_GOTNO)]->d_un.d_val); -+ -+ ElfW(Addr) reloc_value = got[symidx + local_gotno - gotsym]; -+ __builtin_memcpy (reloc_addr, &reloc_value, sizeof (reloc_value)); -+ } -+ } -+ break; -+#endif -+ case R_MIPS_NONE: /* Alright, Wilbur. */ -+ break; -+ -+ case R_RISCV_JUMP_SLOT: -+ { -+ struct link_map *sym_map; -+ ElfW(Addr) value; -+ -+ sym_map = RESOLVE_MAP (&sym, version, r_type); -+ value = sym_map == NULL ? 0 : sym_map->l_addr + sym->st_value; -+ *addr_field = value; -+ -+ break; -+ } -+ -+ case R_RISCV_COPY: -+ { -+ const ElfW(Sym) *const refsym = sym; -+ struct link_map *sym_map; -+ ElfW(Addr) value; -+ -+ /* Calculate the address of the symbol. */ -+ sym_map = RESOLVE_MAP (&sym, version, r_type); -+ value = sym_map == NULL ? 0 : sym_map->l_addr + sym->st_value; -+ -+ if (__builtin_expect (sym == NULL, 0)) -+ /* This can happen in trace mode if an object could not be -+ found. */ -+ break; -+ if (__builtin_expect (sym->st_size > refsym->st_size, 0) -+ || (__builtin_expect (sym->st_size < refsym->st_size, 0) -+ && GLRO(dl_verbose))) -+ { -+ const char *strtab; -+ -+ strtab = (const void *) D_PTR (map, l_info[DT_STRTAB]); -+ _dl_error_printf ("\ -+ %s: Symbol `%s' has different size in shared object, consider re-linking\n", -+ rtld_progname ?: "", -+ strtab + refsym->st_name); -+ } -+ memcpy (reloc_addr, (void *) value, -+ MIN (sym->st_size, refsym->st_size)); -+ break; -+ } -+ -+ default: -+ _dl_reloc_bad_type (map, r_type, 0); -+ break; -+ } -+} -+ -+auto inline void -+__attribute__((always_inline)) -+elf_machine_rel_relative (ElfW(Addr) l_addr, const ElfW(Rel) *reloc, -+ void *const reloc_addr) -+{ -+ /* XXX Nothing to do. There is no relative relocation, right? */ -+} -+ -+auto inline void -+__attribute__((always_inline)) -+elf_machine_lazy_rel (struct link_map *map, -+ ElfW(Addr) l_addr, const ElfW(Rel) *reloc) -+{ -+ ElfW(Addr) *const reloc_addr = (void *) (l_addr + reloc->r_offset); -+ const unsigned int r_type = ELFW(R_TYPE) (reloc->r_info); -+ /* Check for unexpected PLT reloc type. */ -+ if (__builtin_expect (r_type == R_RISCV_JUMP_SLOT, 1)) -+ { -+ if (__builtin_expect (map->l_mach.plt, 0) == 0) -+ { -+ /* Nothing is required here since we only support lazy -+ relocation in executables. */ -+ } -+ else -+ *reloc_addr = map->l_mach.plt; -+ } -+ else -+ _dl_reloc_bad_type (map, r_type, 1); -+} -+ -+#ifndef RTLD_BOOTSTRAP -+/* Relocate GOT. */ -+auto inline void -+__attribute__((always_inline)) -+elf_machine_got_rel (struct link_map *map, int lazy) -+{ -+ ElfW(Addr) *got; -+ ElfW(Sym) *sym; -+ const ElfW(Half) *vernum; -+ int i, n, symidx; -+ -+#define RESOLVE_GOTSYM(sym,vernum,sym_index,reloc) \ -+ ({ \ -+ const ElfW(Sym) *ref = sym; \ -+ const struct r_found_version *version \ -+ = vernum ? &map->l_versions[vernum[sym_index] & 0x7fff] : NULL; \ -+ struct link_map *sym_map; \ -+ sym_map = RESOLVE_MAP (&ref, version, reloc); \ -+ ref ? sym_map->l_addr + ref->st_value : 0; \ -+ }) -+ -+ if (map->l_info[VERSYMIDX (DT_VERSYM)] != NULL) -+ vernum = (const void *) D_PTR (map, l_info[VERSYMIDX (DT_VERSYM)]); -+ else -+ vernum = NULL; -+ -+ got = (ElfW(Addr) *) D_PTR (map, l_info[DT_PLTGOT]); -+ -+ n = map->l_info[DT_RISCV (LOCAL_GOTNO)]->d_un.d_val; -+ /* The dynamic linker's local got entries have already been relocated. */ -+ if (map != &GL(dl_rtld_map)) -+ { -+ /* got[0] and got[1] are reserved. */ -+ i = 2; -+ -+ /* Add the run-time displacement to all local got entries if -+ needed. */ -+ if (__builtin_expect (map->l_addr != 0, 0)) -+ { -+ while (i < n) -+ got[i++] += map->l_addr; -+ } -+ } -+ -+ /* Handle global got entries. */ -+ got += n; -+ /* Keep track of the symbol index. */ -+ symidx = map->l_info[DT_RISCV (GOTSYM)]->d_un.d_val; -+ sym = (ElfW(Sym) *) D_PTR (map, l_info[DT_SYMTAB]) + symidx; -+ i = (map->l_info[DT_RISCV (SYMTABNO)]->d_un.d_val -+ - map->l_info[DT_RISCV (GOTSYM)]->d_un.d_val); -+ -+ /* This loop doesn't handle Quickstart. */ -+ while (i--) -+ { -+ if (sym->st_shndx == SHN_UNDEF || sym->st_shndx == SHN_COMMON) -+ *got = RESOLVE_GOTSYM (sym, vernum, symidx, R_MIPS_32); -+ else if (ELFW(ST_TYPE) (sym->st_info) == STT_FUNC -+ && *got != sym->st_value) -+ { -+ if (lazy) -+ *got += map->l_addr; -+ else -+ /* This is a lazy-binding stub, so we don't need the -+ canonical address. */ -+ *got = RESOLVE_GOTSYM (sym, vernum, symidx, R_RISCV_JUMP_SLOT); -+ } -+ else if (ELFW(ST_TYPE) (sym->st_info) == STT_SECTION) -+ { -+ if (sym->st_other == 0) -+ *got += map->l_addr; -+ } -+ else -+ *got = RESOLVE_GOTSYM (sym, vernum, symidx, R_MIPS_32); -+ -+ ++got; -+ ++sym; -+ ++symidx; -+ } -+ -+#undef RESOLVE_GOTSYM -+} -+#endif -+ -+/* Set up the loaded object described by L so its stub function -+ will jump to the on-demand fixup code __dl_runtime_resolve. */ -+ -+auto inline int -+__attribute__((always_inline)) -+elf_machine_runtime_setup (struct link_map *l, int lazy, int profile) -+{ -+# ifndef RTLD_BOOTSTRAP -+ /* Relocate global offset table. */ -+ elf_machine_got_rel (l, lazy); -+ -+ /* If using PLTs, fill in the first two entries of .got.plt. */ -+ if (l->l_info[DT_JMPREL]) -+ { -+ extern void _dl_runtime_resolve (void); -+ ElfW(Addr) *gotplt = (ElfW(Addr) *) D_PTR (l, l_info[DT_RISCV (PLTGOT)]); -+ /* If a library is prelinked but we have to relocate anyway, -+ we have to be able to undo the prelinking of .got.plt. -+ The prelinker saved the address of .plt for us here. */ -+ if (gotplt[1]) -+ l->l_mach.plt = gotplt[1] + l->l_addr; -+ gotplt[0] = (ElfW(Addr)) &_dl_runtime_resolve; -+ gotplt[1] = (ElfW(Addr)) l; -+ /* Relocate subsequent .got.plt entries. */ -+ if (l->l_addr) -+ for (gotplt += 2; *gotplt; gotplt++) -+ *gotplt += l->l_addr; -+ } -+ -+# endif -+ return lazy; -+} -+ -+#endif /* RESOLVE_MAP */ -diff --git a/glibc-2.14.1/sysdeps/riscv/dl-tls.h b/glibc-2.14.1/sysdeps/riscv/dl-tls.h -new file mode 100644 -index 0000000..8c77a70 ---- /dev/null -+++ glibc-2.14.1/sysdeps/riscv/dl-tls.h -@@ -0,0 +1,49 @@ -+/* Thread-local storage handling in the ELF dynamic linker. MIPS version. -+ Copyright (C) 2005 Free Software Foundation, Inc. -+ This file is part of the GNU C Library. -+ -+ The GNU C Library is free software; you can redistribute it and/or -+ modify it under the terms of the GNU Lesser General Public -+ License as published by the Free Software Foundation; either -+ version 2.1 of the License, or (at your option) any later version. -+ -+ The GNU C Library is distributed in the hope that it will be useful, -+ but WITHOUT ANY WARRANTY; without even the implied warranty of -+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU -+ Lesser General Public License for more details. -+ -+ You should have received a copy of the GNU Lesser General Public -+ License along with the GNU C Library; if not, write to the Free -+ Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA -+ 02111-1307 USA. */ -+ -+ -+/* Type used for the representation of TLS information in the GOT. */ -+typedef struct -+{ -+ unsigned long int ti_module; -+ unsigned long int ti_offset; -+} tls_index; -+ -+/* The thread pointer points to the first static TLS block. */ -+#define TLS_TP_OFFSET 0 -+ -+/* Dynamic thread vector pointers point 0x8000 past the start of each -+ TLS block. */ -+#define TLS_DTV_OFFSET 0x800 -+ -+/* Compute the value for a GOTTPREL reloc. */ -+#define TLS_TPREL_VALUE(sym_map, sym) \ -+ ((sym_map)->l_tls_offset + (sym)->st_value - TLS_TP_OFFSET) -+ -+/* Compute the value for a DTPREL reloc. */ -+#define TLS_DTPREL_VALUE(sym) \ -+ ((sym)->st_value - TLS_DTV_OFFSET) -+ -+extern void *__tls_get_addr (tls_index *ti); -+ -+# define GET_ADDR_OFFSET (ti->ti_offset + TLS_DTV_OFFSET) -+# define __TLS_GET_ADDR(__ti) (__tls_get_addr (__ti) - TLS_DTV_OFFSET) -+ -+/* Value used for dtv entries for which the allocation is delayed. */ -+#define TLS_DTV_UNALLOCATED ((void *) -1l) -diff --git a/glibc-2.14.1/sysdeps/riscv/dl-trampoline.S b/glibc-2.14.1/sysdeps/riscv/dl-trampoline.S -new file mode 100644 -index 0000000..2fdd45a ---- /dev/null -+++ glibc-2.14.1/sysdeps/riscv/dl-trampoline.S -@@ -0,0 +1,39 @@ -+#include -+#include -+ -+/* Assembler veneer called from the PLT header code for lazy loading. -+ The PLT header passes its own args in t0-t2. */ -+ -+ENTRY(_dl_runtime_resolve) -+ # Save arguments to stack. -+ addi sp, sp, -10*SZREG -+ REG_S ra, 9*SZREG(sp) -+ REG_S a0, 1*SZREG(sp) -+ REG_S a1, 2*SZREG(sp) -+ REG_S a2, 3*SZREG(sp) -+ REG_S a3, 4*SZREG(sp) -+ REG_S a4, 5*SZREG(sp) -+ REG_S a5, 6*SZREG(sp) -+ REG_S a6, 7*SZREG(sp) -+ REG_S a7, 8*SZREG(sp) -+ -+ # Update .got.plt and obtain runtime address of callee. -+ mv a0, t0 # link map -+ slli a1, t1, 1 # reloc offset (== twice the .got.plt offset) -+ jal _dl_fixup -+ -+ # Restore arguments from stack. -+ REG_L ra, 9*SZREG(sp) -+ REG_L a0, 1*SZREG(sp) -+ REG_L a1, 2*SZREG(sp) -+ REG_L a2, 3*SZREG(sp) -+ REG_L a3, 4*SZREG(sp) -+ REG_L a4, 5*SZREG(sp) -+ REG_L a5, 6*SZREG(sp) -+ REG_L a6, 7*SZREG(sp) -+ REG_L a7, 8*SZREG(sp) -+ addi sp, sp, 10*SZREG -+ -+ # Invoke the callee. -+ jr v0 -+END(_dl_runtime_resolve) -diff --git a/glibc-2.14.1/sysdeps/riscv/elf/configure b/glibc-2.14.1/sysdeps/riscv/elf/configure -new file mode 100644 -index 0000000..961d9c8 ---- /dev/null -+++ glibc-2.14.1/sysdeps/riscv/elf/configure -@@ -0,0 +1,128 @@ -+ -+# as_fn_set_status STATUS -+# ----------------------- -+# Set $? to STATUS, without forking. -+as_fn_set_status () -+{ -+ return $1 -+} # as_fn_set_status -+ -+# as_fn_exit STATUS -+# ----------------- -+# Exit the shell with STATUS, even in a "trap 0" or "set -e" context. -+as_fn_exit () -+{ -+ set +e -+ as_fn_set_status $1 -+ exit $1 -+} # as_fn_exit -+if expr a : '\(a\)' >/dev/null 2>&1 && -+ test "X`expr 00001 : '.*\(...\)'`" = X001; then -+ as_expr=expr -+else -+ as_expr=false -+fi -+ -+if (basename -- /) >/dev/null 2>&1 && test "X`basename -- / 2>&1`" = "X/"; then -+ as_basename=basename -+else -+ as_basename=false -+fi -+ -+as_me=`$as_basename -- "$0" || -+$as_expr X/"$0" : '.*/\([^/][^/]*\)/*$' \| \ -+ X"$0" : 'X\(//\)$' \| \ -+ X"$0" : 'X\(/\)' \| . 2>/dev/null || -+$as_echo X/"$0" | -+ sed '/^.*\/\([^/][^/]*\)\/*$/{ -+ s//\1/ -+ q -+ } -+ /^X\/\(\/\/\)$/{ -+ s//\1/ -+ q -+ } -+ /^X\/\(\/\).*/{ -+ s//\1/ -+ q -+ } -+ s/.*/./; q'` -+ -+ -+ as_lineno_1=$LINENO as_lineno_1a=$LINENO -+ as_lineno_2=$LINENO as_lineno_2a=$LINENO -+ eval 'test "x$as_lineno_1'$as_run'" != "x$as_lineno_2'$as_run'" && -+ test "x`expr $as_lineno_1'$as_run' + 1`" = "x$as_lineno_2'$as_run'"' || { -+ # Blame Lee E. McMahon (1931-1989) for sed's syntax. :-) -+ sed -n ' -+ p -+ /[$]LINENO/= -+ ' <$as_myself | -+ sed ' -+ s/[$]LINENO.*/&-/ -+ t lineno -+ b -+ :lineno -+ N -+ :loop -+ s/[$]LINENO\([^'$as_cr_alnum'_].*\n\)\(.*\)/\2\1\2/ -+ t loop -+ s/-\n.*// -+ ' >$as_me.lineno && -+ chmod +x "$as_me.lineno" || -+ { $as_echo "$as_me: error: cannot create $as_me.lineno; rerun with a POSIX shell" >&2; as_fn_exit 1; } -+ -+ # Don't try to exec as it changes $[0], causing all sort of problems -+ # (the dirname of $[0] is not the place where we might find the -+ # original and so on. Autoconf is especially sensitive to this). -+ . "./$as_me.lineno" -+ # Exit status is that of the last command. -+ exit -+} -+ -+# This file is generated from configure.in by Autoconf. DO NOT EDIT! -+ # Local configure fragment for sysdeps/riscv/elf. -+ -+if test "$usetls" != no; then -+# Check for support of thread-local storage handling in assembler and -+# linker. -+{ $as_echo "$as_me:${as_lineno-$LINENO}: checking for RISC-V TLS support" >&5 -+$as_echo_n "checking for RISC-V TLS support... " >&6; } -+if ${libc_cv_riscv_tls+:} false; then : -+ $as_echo_n "(cached) " >&6 -+else -+ cat > conftest.s <<\EOF -+ .section ".tdata", "awT", %progbits -+ .globl foo -+foo: .long 1 -+ .section ".tbss", "awT", %nobits -+ .globl bar -+bar: .skip 4 -+ .text -+ -+ la v0, __tls_get_addr -+ la.tls.gd a0, x -+ jalr v0 -+EOF -+if { ac_try='${CC-cc} -c $CFLAGS conftest.s 1>&5' -+ { { eval echo "\"\$as_me\":${as_lineno-$LINENO}: \"$ac_try\""; } >&5 -+ (eval $ac_try) 2>&5 -+ ac_status=$? -+ $as_echo "$as_me:${as_lineno-$LINENO}: \$? = $ac_status" >&5 -+ test $ac_status = 0; }; }; then -+ libc_cv_riscv_tls=yes -+else -+ libc_cv_riscv_tls=no -+fi -+rm -f conftest* -+fi -+{ $as_echo "$as_me:${as_lineno-$LINENO}: result: $libc_cv_riscv_tls" >&5 -+$as_echo "$libc_cv_riscv_tls" >&6; } -+if test $libc_cv_riscv_tls = yes; then -+ $as_echo "#define HAVE_TLS_SUPPORT 1" >>confdefs.h -+ -+fi -+fi -+ -+$as_echo "#define PI_STATIC_AND_HIDDEN 1" >>confdefs.h -+ -diff --git a/glibc-2.14.1/sysdeps/riscv/elf/configure.in b/glibc-2.14.1/sysdeps/riscv/elf/configure.in -new file mode 100644 -index 0000000..6ca00db ---- /dev/null -+++ glibc-2.14.1/sysdeps/riscv/elf/configure.in -@@ -0,0 +1,33 @@ -+GLIBC_PROVIDES dnl See aclocal.m4 in the top level source directory. -+# Local configure fragment for sysdeps/riscv/elf. -+ -+if test "$usetls" != no; then -+# Check for support of thread-local storage handling in assembler and -+# linker. -+AC_CACHE_CHECK(for RISC-V TLS support, libc_cv_riscv_tls, [dnl -+cat > conftest.s <<\EOF -+ .section ".tdata", "awT", %progbits -+ .globl foo -+foo: .long 1 -+ .section ".tbss", "awT", %nobits -+ .globl bar -+bar: .skip 4 -+ .text -+ -+ la v0, __tls_get_addr -+ la.tls.gd a0, x -+ jalr v0 -+EOF -+dnl -+if AC_TRY_COMMAND(${CC-cc} -c $CFLAGS conftest.s 1>&AS_MESSAGE_LOG_FD); then -+ libc_cv_riscv_tls=yes -+else -+ libc_cv_riscv_tls=no -+fi -+rm -f conftest*]) -+if test $libc_cv_riscv_tls = yes; then -+ AC_DEFINE(HAVE_TLS_SUPPORT) -+fi -+fi -+ -+AC_DEFINE(PI_STATIC_AND_HIDDEN) -diff --git a/glibc-2.14.1/sysdeps/riscv/elf/start.S b/glibc-2.14.1/sysdeps/riscv/elf/start.S -new file mode 100644 -index 0000000..55deb45 ---- /dev/null -+++ glibc-2.14.1/sysdeps/riscv/elf/start.S -@@ -0,0 +1,98 @@ -+/* Startup code compliant to the ELF Mips ABI. -+ Copyright (C) 1995, 1997, 2000, 2001, 2002, 2003, 2004 -+ Free Software Foundation, Inc. -+ This file is part of the GNU C Library. -+ -+ The GNU C Library is free software; you can redistribute it and/or -+ modify it under the terms of the GNU Lesser General Public -+ License as published by the Free Software Foundation; either -+ version 2.1 of the License, or (at your option) any later version. -+ -+ In addition to the permissions in the GNU Lesser General Public -+ License, the Free Software Foundation gives you unlimited -+ permission to link the compiled version of this file with other -+ programs, and to distribute those programs without any restriction -+ coming from the use of this file. (The GNU Lesser General Public -+ License restrictions do apply in other respects; for example, they -+ cover modification of the file, and distribution when not linked -+ into another program.) -+ -+ Note that people who make modified versions of this file are not -+ obligated to grant this special exception for their modified -+ versions; it is their choice whether to do so. The GNU Lesser -+ General Public License gives permission to release a modified -+ version without this exception; this exception also makes it -+ possible to release a modified version which carries forward this -+ exception. -+ -+ The GNU C Library is distributed in the hope that it will be useful, -+ but WITHOUT ANY WARRANTY; without even the implied warranty of -+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU -+ Lesser General Public License for more details. -+ -+ You should have received a copy of the GNU Lesser General Public -+ License along with the GNU C Library; if not, write to the Free -+ Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA -+ 02111-1307 USA. */ -+ -+#define __ASSEMBLY__ 1 -+#include -+#include -+#include -+ -+#ifndef ENTRY_POINT -+#error ENTRY_POINT needs to be defined for start.S on MIPS/ELF. -+#endif -+ -+/* This is the canonical entry point, usually the first thing in the text -+ segment. The SVR4/Mips ABI (pages 3-31, 3-32) says that when the entry -+ point runs, most registers' values are unspecified, except for: -+ -+ v0 ($2) Contains a function pointer to be registered with `atexit'. -+ This is how the dynamic linker arranges to have DT_FINI -+ functions called for shared libraries that have been loaded -+ before this code runs. -+ -+ sp ($29) The stack contains the arguments and environment: -+ 0(%esp) argc -+ 4(%esp) argv[0] -+ ... -+ (4*argc)(%esp) NULL -+ (4*(argc+1))(%esp) envp[0] -+ ... -+ NULL -+ ra ($31) The return address register is set to zero so that programs -+ that search backword through stack frames recognize the last -+ stack frame. -+*/ -+ -+ -+/* We need to call: -+ __libc_start_main (int (*main) (int, char **, char **), int argc, -+ char **argv, void (*init) (void), void (*fini) (void), -+ void (*rtld_fini) (void), void *stack_end) -+*/ -+ -+ .text -+ .globl ENTRY_POINT -+ .type ENTRY_POINT,@function -+ENTRY_POINT: -+ la gp, _gp -+ la a0, main -+ REG_L a1, 0(sp) /* argc */ -+ addi a2, sp, SZREG /* argv */ -+ andi sp, sp, ALMASK /* Align stack. */ -+ la a3, __libc_csu_init -+ la a4, __libc_csu_fini -+ move a5, v0 /* rtld_fini */ -+ move a6, sp /* stack_end */ -+ -+ jump __libc_start_main -+ -+/* Define a symbol for the first piece of initialized data. */ -+ .data -+ .globl __data_start -+__data_start: -+ .long 0 -+ .weak data_start -+ data_start = __data_start -diff --git a/glibc-2.14.1/sysdeps/riscv/fpu/bits/mathinline.h b/glibc-2.14.1/sysdeps/riscv/fpu/bits/mathinline.h -new file mode 100644 -index 0000000..3c8a33d ---- /dev/null -+++ glibc-2.14.1/sysdeps/riscv/fpu/bits/mathinline.h -@@ -0,0 +1,66 @@ -+/* Inline math functions for RISC-V. -+ Copyright (C) 2011 -+ Free Software Foundation, Inc. -+ This file is part of the GNU C Library. -+ Contributed by Jakub Jelinek . -+ -+ The GNU C Library is free software; you can redistribute it and/or -+ modify it under the terms of the GNU Lesser General Public -+ License as published by the Free Software Foundation; either -+ version 2.1 of the License, or (at your option) any later version. -+ -+ The GNU C Library is distributed in the hope that it will be useful, -+ but WITHOUT ANY WARRANTY; without even the implied warranty of -+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU -+ Lesser General Public License for more details. -+ -+ You should have received a copy of the GNU Lesser General Public -+ License along with the GNU C Library; if not, write to the Free -+ Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA -+ 02111-1307 USA. */ -+ -+#ifndef _MATH_H -+# error "Never use directly; include instead." -+#endif -+ -+#include -+ -+#ifdef __GNUC__ -+ -+#if defined __USE_ISOC99 -+# undef isgreater -+# undef isgreaterequal -+# undef isless -+# undef islessequal -+# undef islessgreater -+# undef isunordered -+ -+# define isgreater(x, y) ((x) > (y)) -+# define isgreaterequal(x, y) ((x) >= (y)) -+# define isless(x, y) ((x) < (y)) -+# define islessequal(x, y) ((x) <= (y)) -+# define islessgreater(x, y) (!!(isless(x, y) + isgreater(x, y))) -+# define isunordered(x, y) (((x) == (x)) + ((y) == (y)) < 2) -+ -+extern inline int __attribute_used__ __signbit (double __x) -+{ -+ union { double __d; long __i[sizeof(double)/sizeof(long)]; } __u; -+ __u.__d = __x; -+ return __u.__i[sizeof(double)/sizeof(long)-1] < 0; -+} -+ -+extern inline int __attribute_used__ __signbitf (float __x) -+{ -+ union { float __d; int __i; } __u; -+ __u.__d = __x; -+ return __u.__i < 0; -+} -+ -+#endif /* __USE_ISOC99 */ -+ -+#if (!defined __NO_MATH_INLINES || defined __LIBC_INTERNAL_MATH_INLINES) && defined __OPTIMIZE__ -+ -+/* Nothing yet. */ -+ -+#endif /* !__NO_MATH_INLINES && __OPTIMIZE__ */ -+#endif /* __GNUC__ */ -diff --git a/glibc-2.14.1/sysdeps/riscv/fpu/fclrexcpt.c b/glibc-2.14.1/sysdeps/riscv/fpu/fclrexcpt.c -new file mode 100644 -index 0000000..746dad9 ---- /dev/null -+++ glibc-2.14.1/sysdeps/riscv/fpu/fclrexcpt.c -@@ -0,0 +1,29 @@ -+/* Clear given exceptions in current floating-point environment. -+ Copyright (C) 1998, 1999, 2000, 2002 Free Software Foundation, Inc. -+ This file is part of the GNU C Library. -+ Contributed by Andreas Jaeger , 1998. -+ -+ The GNU C Library is free software; you can redistribute it and/or -+ modify it under the terms of the GNU Lesser General Public -+ License as published by the Free Software Foundation; either -+ version 2.1 of the License, or (at your option) any later version. -+ -+ The GNU C Library is distributed in the hope that it will be useful, -+ but WITHOUT ANY WARRANTY; without even the implied warranty of -+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU -+ Lesser General Public License for more details. -+ -+ You should have received a copy of the GNU Lesser General Public -+ License along with the GNU C Library; if not, write to the Free -+ Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA -+ 02111-1307 USA. */ -+ -+#include -+#include -+ -+int -+feclearexcept (int excepts) -+{ -+ asm volatile ("csrc fflags, %0" : : "r"(excepts)); -+ return 0; -+} -diff --git a/glibc-2.14.1/sysdeps/riscv/fpu/fedisblxcpt.c b/glibc-2.14.1/sysdeps/riscv/fpu/fedisblxcpt.c -new file mode 100644 -index 0000000..25eaee5 ---- /dev/null -+++ glibc-2.14.1/sysdeps/riscv/fpu/fedisblxcpt.c -@@ -0,0 +1,29 @@ -+/* Disable floating-point exceptions. -+ Copyright (C) 2000 Free Software Foundation, Inc. -+ This file is part of the GNU C Library. -+ Contributed by Andreas Jaeger , 2000. -+ -+ The GNU C Library is free software; you can redistribute it and/or -+ modify it under the terms of the GNU Lesser General Public -+ License as published by the Free Software Foundation; either -+ version 2.1 of the License, or (at your option) any later version. -+ -+ The GNU C Library is distributed in the hope that it will be useful, -+ but WITHOUT ANY WARRANTY; without even the implied warranty of -+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU -+ Lesser General Public License for more details. -+ -+ You should have received a copy of the GNU Lesser General Public -+ License along with the GNU C Library; if not, write to the Free -+ Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA -+ 02111-1307 USA. */ -+ -+#include -+#include -+ -+int -+fedisableexcept (int excepts) -+{ -+ /* FP exceptions never generate traps. */ -+ return 0; -+} -diff --git a/glibc-2.14.1/sysdeps/riscv/fpu/feenablxcpt.c b/glibc-2.14.1/sysdeps/riscv/fpu/feenablxcpt.c -new file mode 100644 -index 0000000..761c58d ---- /dev/null -+++ glibc-2.14.1/sysdeps/riscv/fpu/feenablxcpt.c -@@ -0,0 +1,29 @@ -+/* Enable floating-point exceptions. -+ Copyright (C) 2000 Free Software Foundation, Inc. -+ This file is part of the GNU C Library. -+ Contributed by Andreas Jaeger , 2000. -+ -+ The GNU C Library is free software; you can redistribute it and/or -+ modify it under the terms of the GNU Lesser General Public -+ License as published by the Free Software Foundation; either -+ version 2.1 of the License, or (at your option) any later version. -+ -+ The GNU C Library is distributed in the hope that it will be useful, -+ but WITHOUT ANY WARRANTY; without even the implied warranty of -+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU -+ Lesser General Public License for more details. -+ -+ You should have received a copy of the GNU Lesser General Public -+ License along with the GNU C Library; if not, write to the Free -+ Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA -+ 02111-1307 USA. */ -+ -+#include -+#include -+ -+int -+feenableexcept (int excepts) -+{ -+ /* FP exceptions never generate traps. */ -+ return -1; -+} -diff --git a/glibc-2.14.1/sysdeps/riscv/fpu/fegetenv.c b/glibc-2.14.1/sysdeps/riscv/fpu/fegetenv.c -new file mode 100644 -index 0000000..da5d597 ---- /dev/null -+++ glibc-2.14.1/sysdeps/riscv/fpu/fegetenv.c -@@ -0,0 +1,32 @@ -+/* Store current floating-point environment. -+ Copyright (C) 1998, 1999, 2000, 2002, 2010 Free Software Foundation, Inc. -+ This file is part of the GNU C Library. -+ Contributed by Andreas Jaeger , 1998. -+ -+ The GNU C Library is free software; you can redistribute it and/or -+ modify it under the terms of the GNU Lesser General Public -+ License as published by the Free Software Foundation; either -+ version 2.1 of the License, or (at your option) any later version. -+ -+ The GNU C Library is distributed in the hope that it will be useful, -+ but WITHOUT ANY WARRANTY; without even the implied warranty of -+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU -+ Lesser General Public License for more details. -+ -+ You should have received a copy of the GNU Lesser General Public -+ License along with the GNU C Library; if not, write to the Free -+ Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA -+ 02111-1307 USA. */ -+ -+#include -+#include -+ -+int -+fegetenv (fenv_t *envp) -+{ -+ _FPU_GETCW (*envp); -+ -+ /* Success. */ -+ return 0; -+} -+libm_hidden_def (fegetenv) -diff --git a/glibc-2.14.1/sysdeps/riscv/fpu/fegetexcept.c b/glibc-2.14.1/sysdeps/riscv/fpu/fegetexcept.c -new file mode 100644 -index 0000000..bdb4b7d ---- /dev/null -+++ glibc-2.14.1/sysdeps/riscv/fpu/fegetexcept.c -@@ -0,0 +1,29 @@ -+/* Get enabled floating-point exceptions. -+ Copyright (C) 2000 Free Software Foundation, Inc. -+ This file is part of the GNU C Library. -+ Contributed by Andreas Jaeger , 2000. -+ -+ The GNU C Library is free software; you can redistribute it and/or -+ modify it under the terms of the GNU Lesser General Public -+ License as published by the Free Software Foundation; either -+ version 2.1 of the License, or (at your option) any later version. -+ -+ The GNU C Library is distributed in the hope that it will be useful, -+ but WITHOUT ANY WARRANTY; without even the implied warranty of -+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU -+ Lesser General Public License for more details. -+ -+ You should have received a copy of the GNU Lesser General Public -+ License along with the GNU C Library; if not, write to the Free -+ Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA -+ 02111-1307 USA. */ -+ -+#include -+#include -+ -+int -+fegetexcept (void) -+{ -+ /* FP exceptions never generate traps. */ -+ return 0; -+} -diff --git a/glibc-2.14.1/sysdeps/riscv/fpu/fegetround.c b/glibc-2.14.1/sysdeps/riscv/fpu/fegetround.c -new file mode 100644 -index 0000000..47eb92f ---- /dev/null -+++ glibc-2.14.1/sysdeps/riscv/fpu/fegetround.c -@@ -0,0 +1,30 @@ -+/* Return current rounding direction. -+ Copyright (C) 1998 Free Software Foundation, Inc. -+ This file is part of the GNU C Library. -+ Contributed by Andreas Jaeger , 1998. -+ -+ The GNU C Library is free software; you can redistribute it and/or -+ modify it under the terms of the GNU Lesser General Public -+ License as published by the Free Software Foundation; either -+ version 2.1 of the License, or (at your option) any later version. -+ -+ The GNU C Library is distributed in the hope that it will be useful, -+ but WITHOUT ANY WARRANTY; without even the implied warranty of -+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU -+ Lesser General Public License for more details. -+ -+ You should have received a copy of the GNU Lesser General Public -+ License along with the GNU C Library; if not, write to the Free -+ Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA -+ 02111-1307 USA. */ -+ -+#include -+#include -+ -+int -+fegetround (void) -+{ -+ int round; -+ _FPU_GETROUND (round); -+ return round; -+} -diff --git a/glibc-2.14.1/sysdeps/riscv/fpu/feholdexcpt.c b/glibc-2.14.1/sysdeps/riscv/fpu/feholdexcpt.c -new file mode 100644 -index 0000000..3d8fa22 ---- /dev/null -+++ glibc-2.14.1/sysdeps/riscv/fpu/feholdexcpt.c -@@ -0,0 +1,32 @@ -+/* Store current floating-point environment and clear exceptions. -+ Copyright (C) 2000 Free Software Foundation, Inc. -+ This file is part of the GNU C Library. -+ Contributed by Andreas Jaeger , 2000. -+ -+ The GNU C Library is free software; you can redistribute it and/or -+ modify it under the terms of the GNU Lesser General Public -+ License as published by the Free Software Foundation; either -+ version 2.1 of the License, or (at your option) any later version. -+ -+ The GNU C Library is distributed in the hope that it will be useful, -+ but WITHOUT ANY WARRANTY; without even the implied warranty of -+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU -+ Lesser General Public License for more details. -+ -+ You should have received a copy of the GNU Lesser General Public -+ License along with the GNU C Library; if not, write to the Free -+ Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA -+ 02111-1307 USA. */ -+ -+#include -+#include -+ -+int -+feholdexcept (fenv_t *envp) -+{ -+ _FPU_GETCW (*envp); -+ _FPU_SETFLAGS (0); -+ return 0; -+} -+ -+libm_hidden_def (feholdexcept) -diff --git a/glibc-2.14.1/sysdeps/riscv/fpu/fesetenv.c b/glibc-2.14.1/sysdeps/riscv/fpu/fesetenv.c -new file mode 100644 -index 0000000..e34fdaf ---- /dev/null -+++ glibc-2.14.1/sysdeps/riscv/fpu/fesetenv.c -@@ -0,0 +1,31 @@ -+/* Install given floating-point environment. -+ Copyright (C) 1998, 1999, 2000, 2002 Free Software Foundation, Inc. -+ This file is part of the GNU C Library. -+ Contributed by Andreas Jaeger , 1998. -+ -+ The GNU C Library is free software; you can redistribute it and/or -+ modify it under the terms of the GNU Lesser General Public -+ License as published by the Free Software Foundation; either -+ version 2.1 of the License, or (at your option) any later version. -+ -+ The GNU C Library is distributed in the hope that it will be useful, -+ but WITHOUT ANY WARRANTY; without even the implied warranty of -+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU -+ Lesser General Public License for more details. -+ -+ You should have received a copy of the GNU Lesser General Public -+ License along with the GNU C Library; if not, write to the Free -+ Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA -+ 02111-1307 USA. */ -+ -+#include -+#include -+ -+int -+fesetenv (const fenv_t *envp) -+{ -+ _FPU_SETCW (envp == FE_DFL_ENV ? 0 : *envp); -+ return 0; -+} -+ -+libm_hidden_def (fesetenv) -diff --git a/glibc-2.14.1/sysdeps/riscv/fpu/fesetround.c b/glibc-2.14.1/sysdeps/riscv/fpu/fesetround.c -new file mode 100644 -index 0000000..ad80465 ---- /dev/null -+++ glibc-2.14.1/sysdeps/riscv/fpu/fesetround.c -@@ -0,0 +1,34 @@ -+/* Set current rounding direction. -+ Copyright (C) 1998 Free Software Foundation, Inc. -+ This file is part of the GNU C Library. -+ Contributed by Andreas Jaeger , 1998. -+ -+ The GNU C Library is free software; you can redistribute it and/or -+ modify it under the terms of the GNU Lesser General Public -+ License as published by the Free Software Foundation; either -+ version 2.1 of the License, or (at your option) any later version. -+ -+ The GNU C Library is distributed in the hope that it will be useful, -+ but WITHOUT ANY WARRANTY; without even the implied warranty of -+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU -+ Lesser General Public License for more details. -+ -+ You should have received a copy of the GNU Lesser General Public -+ License along with the GNU C Library; if not, write to the Free -+ Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA -+ 02111-1307 USA. */ -+ -+#include -+#include -+ -+int -+fesetround (int round) -+{ -+ int fail = round != FE_TONEAREST && round != FE_TOWARDZERO -+ && round != FE_DOWNWARD && round != FE_UPWARD; -+ if (!fail) -+ _FPU_SETROUND (round); -+ return fail; -+} -+ -+libm_hidden_def (fesetround) -diff --git a/glibc-2.14.1/sysdeps/riscv/fpu/feupdateenv.c b/glibc-2.14.1/sysdeps/riscv/fpu/feupdateenv.c -new file mode 100644 -index 0000000..51611cd ---- /dev/null -+++ glibc-2.14.1/sysdeps/riscv/fpu/feupdateenv.c -@@ -0,0 +1,35 @@ -+/* Install given floating-point environment and raise exceptions. -+ Copyright (C) 1998, 1999, 2000, 2002, 2010 Free Software Foundation, Inc. -+ This file is part of the GNU C Library. -+ Contributed by Andreas Jaeger , 1998. -+ -+ The GNU C Library is free software; you can redistribute it and/or -+ modify it under the terms of the GNU Lesser General Public -+ License as published by the Free Software Foundation; either -+ version 2.1 of the License, or (at your option) any later version. -+ -+ The GNU C Library is distributed in the hope that it will be useful, -+ but WITHOUT ANY WARRANTY; without even the implied warranty of -+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU -+ Lesser General Public License for more details. -+ -+ You should have received a copy of the GNU Lesser General Public -+ License along with the GNU C Library; if not, write to the Free -+ Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA -+ 02111-1307 USA. */ -+ -+#include -+#include -+ -+int -+feupdateenv (const fenv_t *envp) -+{ -+ fenv_t env = *envp; -+ -+ /* rm = 0; rm |= fenv.rm; flags |= fenv.flags */ -+ _FPU_SETROUND (0); -+ asm volatile ("csrs fcsr, %0" : : "r"(env)); -+ -+ return 0; -+} -+libm_hidden_def (feupdateenv) -diff --git a/glibc-2.14.1/sysdeps/riscv/fpu/fgetexcptflg.c b/glibc-2.14.1/sysdeps/riscv/fpu/fgetexcptflg.c -new file mode 100644 -index 0000000..537f5b7 ---- /dev/null -+++ glibc-2.14.1/sysdeps/riscv/fpu/fgetexcptflg.c -@@ -0,0 +1,35 @@ -+/* Store current representation for exceptions. -+ Copyright (C) 1998, 1999, 2000, 2002 Free Software Foundation, Inc. -+ This file is part of the GNU C Library. -+ Contributed by Andreas Jaeger , 1998. -+ -+ The GNU C Library is free software; you can redistribute it and/or -+ modify it under the terms of the GNU Lesser General Public -+ License as published by the Free Software Foundation; either -+ version 2.1 of the License, or (at your option) any later version. -+ -+ The GNU C Library is distributed in the hope that it will be useful, -+ but WITHOUT ANY WARRANTY; without even the implied warranty of -+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU -+ Lesser General Public License for more details. -+ -+ You should have received a copy of the GNU Lesser General Public -+ License along with the GNU C Library; if not, write to the Free -+ Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA -+ 02111-1307 USA. */ -+ -+#include -+#include -+ -+int -+fegetexceptflag (fexcept_t *flagp, int excepts) -+{ -+ fpu_control_t temp; -+ -+ /* Get the current exceptions. */ -+ _FPU_GETFLAGS (*flagp); -+ *flagp &= excepts; -+ -+ /* Success. */ -+ return 0; -+} -diff --git a/glibc-2.14.1/sysdeps/riscv/fpu/fraiseexcpt.c b/glibc-2.14.1/sysdeps/riscv/fpu/fraiseexcpt.c -new file mode 100644 -index 0000000..2a839d0 ---- /dev/null -+++ glibc-2.14.1/sysdeps/riscv/fpu/fraiseexcpt.c -@@ -0,0 +1,31 @@ -+/* Raise given exceptions. -+ Copyright (C) 2000, 2002 Free Software Foundation, Inc. -+ This file is part of the GNU C Library. -+ Contributed by Andreas Jaeger , 2000. -+ -+ The GNU C Library is free software; you can redistribute it and/or -+ modify it under the terms of the GNU Lesser General Public -+ License as published by the Free Software Foundation; either -+ version 2.1 of the License, or (at your option) any later version. -+ -+ The GNU C Library is distributed in the hope that it will be useful, -+ but WITHOUT ANY WARRANTY; without even the implied warranty of -+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU -+ Lesser General Public License for more details. -+ -+ You should have received a copy of the GNU Lesser General Public -+ License along with the GNU C Library; if not, write to the Free -+ Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA -+ 02111-1307 USA. */ -+ -+#include -+#include -+ -+int -+feraiseexcept (int excepts) -+{ -+ asm volatile ("csrs fflags, %0" : : "r"(excepts)); -+ return 0; -+} -+ -+libm_hidden_def (feraiseexcept) -diff --git a/glibc-2.14.1/sysdeps/riscv/fpu/fsetexcptflg.c b/glibc-2.14.1/sysdeps/riscv/fpu/fsetexcptflg.c -new file mode 100644 -index 0000000..c28235a ---- /dev/null -+++ glibc-2.14.1/sysdeps/riscv/fpu/fsetexcptflg.c -@@ -0,0 +1,32 @@ -+/* Set floating-point environment exception handling. -+ Copyright (C) 1998, 1999, 2000, 2002 Free Software Foundation, Inc. -+ This file is part of the GNU C Library. -+ Contributed by Hartvig Ekner , 2002. -+ -+ The GNU C Library is free software; you can redistribute it and/or -+ modify it under the terms of the GNU Lesser General Public -+ License as published by the Free Software Foundation; either -+ version 2.1 of the License, or (at your option) any later version. -+ -+ The GNU C Library is distributed in the hope that it will be useful, -+ but WITHOUT ANY WARRANTY; without even the implied warranty of -+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU -+ Lesser General Public License for more details. -+ -+ You should have received a copy of the GNU Lesser General Public -+ License along with the GNU C Library; if not, write to the Free -+ Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA -+ 02111-1307 USA. */ -+ -+#include -+#include -+ -+int -+fesetexceptflag (const fexcept_t *flagp, int excepts) -+{ -+ fexcept_t flags = *flagp; -+ asm volatile ("csrc fflags, %0" : : "r"(excepts)); -+ asm volatile ("csrs fflags, %0" : : "r"(flags & excepts)); -+ -+ return 0; -+} -diff --git a/glibc-2.14.1/sysdeps/riscv/fpu/ftestexcept.c b/glibc-2.14.1/sysdeps/riscv/fpu/ftestexcept.c -new file mode 100644 -index 0000000..8235fa1 ---- /dev/null -+++ glibc-2.14.1/sysdeps/riscv/fpu/ftestexcept.c -@@ -0,0 +1,33 @@ -+/* Test exception in current environment. -+ Copyright (C) 1998, 2010 Free Software Foundation, Inc. -+ This file is part of the GNU C Library. -+ Contributed by Andreas Jaeger , 1998. -+ -+ The GNU C Library is free software; you can redistribute it and/or -+ modify it under the terms of the GNU Lesser General Public -+ License as published by the Free Software Foundation; either -+ version 2.1 of the License, or (at your option) any later version. -+ -+ The GNU C Library is distributed in the hope that it will be useful, -+ but WITHOUT ANY WARRANTY; without even the implied warranty of -+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU -+ Lesser General Public License for more details. -+ -+ You should have received a copy of the GNU Lesser General Public -+ License along with the GNU C Library; if not, write to the Free -+ Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA -+ 02111-1307 USA. */ -+ -+#include -+#include -+ -+int -+fetestexcept (int excepts) -+{ -+ int cw; -+ -+ _FPU_GETFLAGS (cw); -+ -+ return cw & excepts; -+} -+libm_hidden_def (fetestexcept) -diff --git a/glibc-2.14.1/sysdeps/riscv/fpu/libm-test-ulps b/glibc-2.14.1/sysdeps/riscv/fpu/libm-test-ulps -new file mode 100644 -index 0000000..b514496 ---- /dev/null -+++ glibc-2.14.1/sysdeps/riscv/fpu/libm-test-ulps -@@ -0,0 +1,890 @@ -+# Begin of automatic generation -+ -+# atan2 -+Test "atan2 (-0.75, -1.0) == -2.49809154479650885165983415456218025": -+float: 3 -+ifloat: 3 -+Test "atan2 (0.75, -1.0) == 2.49809154479650885165983415456218025": -+float: 3 -+ifloat: 3 -+Test "atan2 (1.390625, 0.9296875) == 0.981498387184244311516296577615519772": -+float: 1 -+ifloat: 1 -+ -+# atanh -+Test "atanh (0.75) == 0.972955074527656652552676371721589865": -+float: 1 -+ifloat: 1 -+ -+# cacosh -+Test "Real part of: cacosh (-2 - 3 i) == 1.9833870299165354323470769028940395 - 2.1414491111159960199416055713254211 i": -+double: 1 -+float: 7 -+idouble: 1 -+ifloat: 7 -+Test "Imaginary part of: cacosh (-2 - 3 i) == 1.9833870299165354323470769028940395 - 2.1414491111159960199416055713254211 i": -+double: 1 -+float: 3 -+idouble: 1 -+ifloat: 3 -+ -+# casin -+Test "Real part of: casin (0.75 + 1.25 i) == 0.453276177638793913448921196101971749 + 1.13239363160530819522266333696834467 i": -+double: 1 -+float: 1 -+idouble: 1 -+ifloat: 1 -+ -+# casinh -+Test "Real part of: casinh (-2 - 3 i) == -1.9686379257930962917886650952454982 - 0.96465850440760279204541105949953237 i": -+double: 5 -+float: 1 -+idouble: 5 -+ifloat: 1 -+Test "Imaginary part of: casinh (-2 - 3 i) == -1.9686379257930962917886650952454982 - 0.96465850440760279204541105949953237 i": -+double: 3 -+float: 6 -+idouble: 3 -+ifloat: 6 -+Test "Real part of: casinh (0.75 + 1.25 i) == 1.03171853444778027336364058631006594 + 0.911738290968487636358489564316731207 i": -+float: 1 -+ifloat: 1 -+Test "Imaginary part of: casinh (0.75 + 1.25 i) == 1.03171853444778027336364058631006594 + 0.911738290968487636358489564316731207 i": -+double: 1 -+float: 1 -+idouble: 1 -+ifloat: 1 -+ -+# catan -+Test "Real part of: catan (-2 - 3 i) == -1.4099210495965755225306193844604208 - 0.22907268296853876629588180294200276 i": -+float: 3 -+ifloat: 3 -+Test "Imaginary part of: catan (-2 - 3 i) == -1.4099210495965755225306193844604208 - 0.22907268296853876629588180294200276 i": -+double: 1 -+float: 1 -+idouble: 1 -+ifloat: 1 -+Test "Real part of: catan (0.75 + 1.25 i) == 1.10714871779409050301706546017853704 + 0.549306144334054845697622618461262852 i": -+float: 4 -+ifloat: 4 -+ -+# catanh -+Test "Real part of: catanh (-2 - 3 i) == -0.14694666622552975204743278515471595 - 1.3389725222944935611241935759091443 i": -+double: 4 -+idouble: 4 -+Test "Imaginary part of: catanh (-2 - 3 i) == -0.14694666622552975204743278515471595 - 1.3389725222944935611241935759091443 i": -+float: 4 -+ifloat: 4 -+Test "Real part of: catanh (0.75 + 1.25 i) == 0.261492138795671927078652057366532140 + 0.996825126463918666098902241310446708 i": -+double: 1 -+idouble: 1 -+Test "Imaginary part of: catanh (0.75 + 1.25 i) == 0.261492138795671927078652057366532140 + 0.996825126463918666098902241310446708 i": -+float: 6 -+ifloat: 6 -+ -+# cbrt -+Test "cbrt (-27.0) == -3.0": -+double: 1 -+idouble: 1 -+Test "cbrt (0.75) == 0.908560296416069829445605878163630251": -+double: 1 -+idouble: 1 -+Test "cbrt (0.9921875) == 0.997389022060725270579075195353955217": -+double: 1 -+idouble: 1 -+ -+# ccos -+Test "Imaginary part of: ccos (-2 - 3 i) == -4.18962569096880723013255501961597373 - 9.10922789375533659797919726277886212 i": -+float: 1 -+ifloat: 1 -+Test "Real part of: ccos (0.75 + 1.25 i) == 1.38173873063425888530729933139078645 - 1.09193013555397466170919531722024128 i": -+double: 1 -+float: 1 -+idouble: 1 -+ifloat: 1 -+Test "Imaginary part of: ccos (0.75 + 1.25 i) == 1.38173873063425888530729933139078645 - 1.09193013555397466170919531722024128 i": -+float: 1 -+ifloat: 1 -+ -+# ccosh -+Test "Real part of: ccosh (-2 - 3 i) == -3.72454550491532256547397070325597253 + 0.511822569987384608834463849801875634 i": -+float: 1 -+ifloat: 1 -+Test "Imaginary part of: ccosh (-2 - 3 i) == -3.72454550491532256547397070325597253 + 0.511822569987384608834463849801875634 i": -+float: 1 -+ifloat: 1 -+Test "Real part of: ccosh (0.75 + 1.25 i) == 0.408242591877968807788852146397499084 + 0.780365930845853240391326216300863152 i": -+double: 1 -+float: 1 -+idouble: 1 -+ifloat: 1 -+Test "Imaginary part of: ccosh (0.75 + 1.25 i) == 0.408242591877968807788852146397499084 + 0.780365930845853240391326216300863152 i": -+float: 1 -+ifloat: 1 -+ -+# cexp -+Test "Imaginary part of: cexp (-2.0 - 3.0 i) == -0.13398091492954261346140525546115575 - 0.019098516261135196432576240858800925 i": -+float: 1 -+ifloat: 1 -+Test "Real part of: cexp (0.75 + 1.25 i) == 0.667537446429131586942201977015932112 + 2.00900045494094876258347228145863909 i": -+float: 1 -+ifloat: 1 -+ -+# clog -+Test "Imaginary part of: clog (-2 - 3 i) == 1.2824746787307683680267437207826593 - 2.1587989303424641704769327722648368 i": -+float: 3 -+ifloat: 3 -+Test "Real part of: clog (0.75 + 1.25 i) == 0.376885901188190075998919126749298416 + 1.03037682652431246378774332703115153 i": -+float: 1 -+ifloat: 1 -+ -+# clog10 -+Test "Imaginary part of: clog10 (-0 + inf i) == inf + pi/2*log10(e) i": -+float: 1 -+ifloat: 1 -+Test "Imaginary part of: clog10 (-0 - inf i) == inf - pi/2*log10(e) i": -+float: 1 -+ifloat: 1 -+Test "Imaginary part of: clog10 (-2 - 3 i) == 0.556971676153418384603252578971164214 - 0.937554462986374708541507952140189646 i": -+double: 1 -+float: 5 -+idouble: 1 -+ifloat: 5 -+Test "Imaginary part of: clog10 (-3 + inf i) == inf + pi/2*log10(e) i": -+float: 1 -+ifloat: 1 -+Test "Imaginary part of: clog10 (-3 - inf i) == inf - pi/2*log10(e) i": -+float: 1 -+ifloat: 1 -+Test "Imaginary part of: clog10 (-inf + 0 i) == inf + pi*log10(e) i": -+float: 1 -+ifloat: 1 -+Test "Imaginary part of: clog10 (-inf + 1 i) == inf + pi*log10(e) i": -+float: 1 -+ifloat: 1 -+Test "Imaginary part of: clog10 (-inf - 0 i) == inf - pi*log10(e) i": -+float: 1 -+ifloat: 1 -+Test "Imaginary part of: clog10 (-inf - 1 i) == inf - pi*log10(e) i": -+float: 1 -+ifloat: 1 -+Test "Imaginary part of: clog10 (0 + inf i) == inf + pi/2*log10(e) i": -+float: 1 -+ifloat: 1 -+Test "Imaginary part of: clog10 (0 - inf i) == inf - pi/2*log10(e) i": -+float: 1 -+ifloat: 1 -+Test "Real part of: clog10 (0.75 + 1.25 i) == 0.163679467193165171449476605077428975 + 0.447486970040493067069984724340855636 i": -+float: 1 -+ifloat: 1 -+Test "Imaginary part of: clog10 (3 + inf i) == inf + pi/2*log10(e) i": -+float: 1 -+ifloat: 1 -+Test "Imaginary part of: clog10 (3 - inf i) == inf - pi/2*log10(e) i": -+float: 1 -+ifloat: 1 -+Test "Imaginary part of: clog10 (inf + inf i) == inf + pi/4*log10(e) i": -+float: 1 -+ifloat: 1 -+Test "Imaginary part of: clog10 (inf - inf i) == inf - pi/4*log10(e) i": -+float: 1 -+ifloat: 1 -+ -+# cos -+Test "cos (M_PI_6l * 2.0) == 0.5": -+double: 1 -+float: 1 -+idouble: 1 -+ifloat: 1 -+Test "cos (M_PI_6l * 4.0) == -0.5": -+double: 2 -+float: 1 -+idouble: 2 -+ifloat: 1 -+Test "cos (pi/2) == 0": -+double: 1 -+float: 1 -+idouble: 1 -+ifloat: 1 -+ -+# cpow -+Test "Real part of: cpow (0.75 + 1.25 i, 0.0 + 1.0 i) == 0.331825439177608832276067945276730566 + 0.131338600281188544930936345230903032 i": -+float: 1 -+ifloat: 1 -+Test "Imaginary part of: cpow (0.75 + 1.25 i, 0.0 + 1.0 i) == 0.331825439177608832276067945276730566 + 0.131338600281188544930936345230903032 i": -+float: 1 -+ifloat: 1 -+Test "Real part of: cpow (0.75 + 1.25 i, 0.75 + 1.25 i) == 0.117506293914473555420279832210420483 + 0.346552747708338676483025352060418001 i": -+double: 1 -+float: 4 -+idouble: 1 -+ifloat: 4 -+Test "Real part of: cpow (0.75 + 1.25 i, 1.0 + 1.0 i) == 0.0846958290317209430433805274189191353 + 0.513285749182902449043287190519090481 i": -+double: 2 -+float: 3 -+idouble: 2 -+ifloat: 3 -+Test "Real part of: cpow (2 + 3 i, 4 + 0 i) == -119.0 - 120.0 i": -+double: 1 -+float: 4 -+idouble: 1 -+ifloat: 4 -+Test "Imaginary part of: cpow (2 + 3 i, 4 + 0 i) == -119.0 - 120.0 i": -+float: 2 -+ifloat: 2 -+Test "Imaginary part of: cpow (e + 0 i, 0 + 2 * M_PIl i) == 1.0 + 0.0 i": -+double: 2 -+float: 2 -+idouble: 2 -+ifloat: 2 -+ -+# csinh -+Test "Imaginary part of: csinh (-2 - 3 i) == 3.59056458998577995201256544779481679 - 0.530921086248519805267040090660676560 i": -+double: 1 -+idouble: 1 -+Test "Real part of: csinh (0.75 + 1.25 i) == 0.259294854551162779153349830618433028 + 1.22863452409509552219214606515777594 i": -+float: 1 -+ifloat: 1 -+Test "Imaginary part of: csinh (0.75 + 1.25 i) == 0.259294854551162779153349830618433028 + 1.22863452409509552219214606515777594 i": -+float: 1 -+ifloat: 1 -+ -+# csqrt -+Test "Real part of: csqrt (-2 + 3 i) == 0.89597747612983812471573375529004348 + 1.6741492280355400404480393008490519 i": -+float: 1 -+ifloat: 1 -+Test "Real part of: csqrt (-2 - 3 i) == 0.89597747612983812471573375529004348 - 1.6741492280355400404480393008490519 i": -+float: 1 -+ifloat: 1 -+ -+# ctan -+Test "Real part of: ctan (-2 - 3 i) == 0.376402564150424829275122113032269084e-2 - 1.00323862735360980144635859782192726 i": -+double: 1 -+idouble: 1 -+Test "Imaginary part of: ctan (0.75 + 1.25 i) == 0.160807785916206426725166058173438663 + 0.975363285031235646193581759755216379 i": -+double: 1 -+idouble: 1 -+ -+# ctanh -+Test "Real part of: ctanh (-2 - 3 i) == -0.965385879022133124278480269394560686 + 0.988437503832249372031403430350121098e-2 i": -+double: 1 -+float: 2 -+idouble: 1 -+ifloat: 2 -+Test "Imaginary part of: ctanh (0 + pi/4 i) == 0.0 + 1.0 i": -+float: 1 -+ifloat: 1 -+Test "Real part of: ctanh (0.75 + 1.25 i) == 1.37260757053378320258048606571226857 + 0.385795952609750664177596760720790220 i": -+double: 1 -+idouble: 1 -+ -+# erf -+Test "erf (1.25) == 0.922900128256458230136523481197281140": -+double: 1 -+idouble: 1 -+ -+# erfc -+Test "erfc (2.0) == 0.00467773498104726583793074363274707139": -+double: 1 -+idouble: 1 -+Test "erfc (4.125) == 0.542340079956506600531223408575531062e-8": -+double: 1 -+idouble: 1 -+ -+# exp10 -+Test "exp10 (-1) == 0.1": -+double: 2 -+float: 1 -+idouble: 2 -+ifloat: 1 -+Test "exp10 (0.75) == 5.62341325190349080394951039776481231": -+double: 1 -+float: 1 -+idouble: 1 -+ifloat: 1 -+Test "exp10 (3) == 1000": -+double: 6 -+float: 2 -+idouble: 6 -+ifloat: 2 -+ -+# expm1 -+Test "expm1 (0.75) == 1.11700001661267466854536981983709561": -+double: 1 -+idouble: 1 -+Test "expm1 (1) == M_El - 1.0": -+float: 1 -+ifloat: 1 -+ -+# hypot -+Test "hypot (-0.7, -12.4) == 12.419742348374220601176836866763271": -+float: 1 -+ifloat: 1 -+Test "hypot (-0.7, 12.4) == 12.419742348374220601176836866763271": -+float: 1 -+ifloat: 1 -+Test "hypot (-12.4, -0.7) == 12.419742348374220601176836866763271": -+float: 1 -+ifloat: 1 -+Test "hypot (-12.4, 0.7) == 12.419742348374220601176836866763271": -+float: 1 -+ifloat: 1 -+Test "hypot (0.7, -12.4) == 12.419742348374220601176836866763271": -+float: 1 -+ifloat: 1 -+Test "hypot (0.7, 12.4) == 12.419742348374220601176836866763271": -+float: 1 -+ifloat: 1 -+Test "hypot (12.4, -0.7) == 12.419742348374220601176836866763271": -+float: 1 -+ifloat: 1 -+Test "hypot (12.4, 0.7) == 12.419742348374220601176836866763271": -+float: 1 -+ifloat: 1 -+ -+# j0 -+Test "j0 (-4.0) == -3.9714980986384737228659076845169804197562E-1": -+double: 1 -+float: 1 -+idouble: 1 -+ifloat: 1 -+Test "j0 (0.75) == 0.864242275166648623555731103820923211": -+float: 1 -+ifloat: 1 -+Test "j0 (10.0) == -0.245935764451348335197760862485328754": -+double: 2 -+float: 1 -+idouble: 2 -+ifloat: 1 -+Test "j0 (2.0) == 0.223890779141235668051827454649948626": -+float: 2 -+ifloat: 2 -+Test "j0 (4.0) == -3.9714980986384737228659076845169804197562E-1": -+double: 1 -+float: 1 -+idouble: 1 -+ifloat: 1 -+Test "j0 (8.0) == 0.171650807137553906090869407851972001": -+float: 1 -+ifloat: 1 -+ -+# j1 -+Test "j1 (10.0) == 0.0434727461688614366697487680258592883": -+float: 2 -+ifloat: 2 -+Test "j1 (2.0) == 0.576724807756873387202448242269137087": -+double: 1 -+idouble: 1 -+Test "j1 (8.0) == 0.234636346853914624381276651590454612": -+double: 1 -+idouble: 1 -+ -+# jn -+Test "jn (0, -4.0) == -3.9714980986384737228659076845169804197562E-1": -+double: 1 -+float: 1 -+idouble: 1 -+ifloat: 1 -+Test "jn (0, 0.75) == 0.864242275166648623555731103820923211": -+float: 1 -+ifloat: 1 -+Test "jn (0, 10.0) == -0.245935764451348335197760862485328754": -+double: 2 -+float: 1 -+idouble: 2 -+ifloat: 1 -+Test "jn (0, 2.0) == 0.223890779141235668051827454649948626": -+float: 2 -+ifloat: 2 -+Test "jn (0, 4.0) == -3.9714980986384737228659076845169804197562E-1": -+double: 1 -+float: 1 -+idouble: 1 -+ifloat: 1 -+Test "jn (0, 8.0) == 0.171650807137553906090869407851972001": -+float: 1 -+ifloat: 1 -+Test "jn (1, 10.0) == 0.0434727461688614366697487680258592883": -+float: 2 -+ifloat: 2 -+Test "jn (1, 2.0) == 0.576724807756873387202448242269137087": -+double: 1 -+idouble: 1 -+Test "jn (1, 8.0) == 0.234636346853914624381276651590454612": -+double: 1 -+idouble: 1 -+Test "jn (10, 0.125) == 0.250543369809369890173993791865771547e-18": -+double: 1 -+float: 1 -+idouble: 1 -+ifloat: 1 -+Test "jn (10, 0.75) == 0.149621713117596814698712483621682835e-10": -+double: 1 -+float: 1 -+idouble: 1 -+ifloat: 1 -+Test "jn (10, 10.0) == 0.207486106633358857697278723518753428": -+double: 4 -+float: 3 -+idouble: 4 -+ifloat: 3 -+Test "jn (10, 2.0) == 0.251538628271673670963516093751820639e-6": -+float: 4 -+ifloat: 4 -+Test "jn (3, 0.125) == 0.406503832554912875023029337653442868e-4": -+double: 1 -+float: 1 -+idouble: 1 -+ifloat: 1 -+Test "jn (3, 0.75) == 0.848438342327410884392755236884386804e-2": -+double: 1 -+float: 1 -+idouble: 1 -+ifloat: 1 -+Test "jn (3, 10.0) == 0.0583793793051868123429354784103409563": -+double: 3 -+float: 1 -+idouble: 3 -+ifloat: 1 -+Test "jn (3, 2.0) == 0.128943249474402051098793332969239835": -+double: 1 -+float: 2 -+idouble: 1 -+ifloat: 2 -+ -+# lgamma -+Test "lgamma (0.7) == 0.260867246531666514385732417016759578": -+double: 1 -+float: 1 -+idouble: 1 -+ifloat: 1 -+Test "lgamma (1.2) == -0.853740900033158497197028392998854470e-1": -+double: 1 -+float: 2 -+idouble: 1 -+ifloat: 2 -+ -+# log10 -+Test "log10 (0.75) == -0.124938736608299953132449886193870744": -+double: 1 -+float: 2 -+idouble: 1 -+ifloat: 2 -+Test "log10 (e) == log10(e)": -+float: 1 -+ifloat: 1 -+ -+# log1p -+Test "log1p (-0.25) == -0.287682072451780927439219005993827432": -+float: 1 -+ifloat: 1 -+ -+# sincos -+Test "sincos (M_PI_6l*2.0, &sin_res, &cos_res) puts 0.5 in cos_res": -+double: 1 -+float: 1 -+idouble: 1 -+ifloat: 1 -+Test "sincos (M_PI_6l*2.0, &sin_res, &cos_res) puts 0.86602540378443864676372317075293616 in sin_res": -+double: 1 -+float: 1 -+idouble: 1 -+ifloat: 1 -+Test "sincos (pi/2, &sin_res, &cos_res) puts 0 in cos_res": -+double: 1 -+float: 1 -+idouble: 1 -+ifloat: 1 -+Test "sincos (pi/6, &sin_res, &cos_res) puts 0.86602540378443864676372317075293616 in cos_res": -+float: 1 -+ifloat: 1 -+ -+# tan -+Test "tan (pi/4) == 1": -+double: 1 -+idouble: 1 -+ -+# tgamma -+Test "tgamma (-0.5) == -2 sqrt (pi)": -+double: 1 -+float: 1 -+idouble: 1 -+ifloat: 1 -+Test "tgamma (0.5) == sqrt (pi)": -+float: 1 -+ifloat: 1 -+Test "tgamma (0.7) == 1.29805533264755778568117117915281162": -+double: 1 -+float: 1 -+idouble: 1 -+ifloat: 1 -+ -+# y0 -+Test "y0 (1.0) == 0.0882569642156769579829267660235151628": -+double: 2 -+float: 1 -+idouble: 2 -+ifloat: 1 -+Test "y0 (1.5) == 0.382448923797758843955068554978089862": -+double: 2 -+float: 1 -+idouble: 2 -+ifloat: 1 -+Test "y0 (10.0) == 0.0556711672835993914244598774101900481": -+float: 1 -+ifloat: 1 -+Test "y0 (8.0) == 0.223521489387566220527323400498620359": -+double: 1 -+float: 1 -+idouble: 1 -+ifloat: 1 -+ -+# y1 -+Test "y1 (0.125) == -5.19993611253477499595928744876579921": -+double: 1 -+idouble: 1 -+Test "y1 (1.5) == -0.412308626973911295952829820633445323": -+float: 1 -+ifloat: 1 -+Test "y1 (10.0) == 0.249015424206953883923283474663222803": -+double: 3 -+float: 1 -+idouble: 3 -+ifloat: 1 -+Test "y1 (2.0) == -0.107032431540937546888370772277476637": -+double: 1 -+float: 1 -+idouble: 1 -+ifloat: 1 -+Test "y1 (8.0) == -0.158060461731247494255555266187483550": -+double: 1 -+float: 2 -+idouble: 1 -+ifloat: 2 -+ -+# yn -+Test "yn (0, 1.0) == 0.0882569642156769579829267660235151628": -+double: 2 -+float: 1 -+idouble: 2 -+ifloat: 1 -+Test "yn (0, 1.5) == 0.382448923797758843955068554978089862": -+double: 2 -+float: 1 -+idouble: 2 -+ifloat: 1 -+Test "yn (0, 10.0) == 0.0556711672835993914244598774101900481": -+float: 1 -+ifloat: 1 -+Test "yn (0, 8.0) == 0.223521489387566220527323400498620359": -+double: 1 -+float: 1 -+idouble: 1 -+ifloat: 1 -+Test "yn (1, 0.125) == -5.19993611253477499595928744876579921": -+double: 1 -+idouble: 1 -+Test "yn (1, 1.5) == -0.412308626973911295952829820633445323": -+float: 1 -+ifloat: 1 -+Test "yn (1, 10.0) == 0.249015424206953883923283474663222803": -+double: 3 -+float: 1 -+idouble: 3 -+ifloat: 1 -+Test "yn (1, 2.0) == -0.107032431540937546888370772277476637": -+double: 1 -+float: 1 -+idouble: 1 -+ifloat: 1 -+Test "yn (1, 8.0) == -0.158060461731247494255555266187483550": -+double: 1 -+float: 2 -+idouble: 1 -+ifloat: 2 -+Test "yn (10, 0.125) == -127057845771019398.252538486899753195": -+double: 1 -+idouble: 1 -+Test "yn (10, 0.75) == -2133501638.90573424452445412893839236": -+double: 1 -+float: 1 -+idouble: 1 -+ifloat: 1 -+Test "yn (10, 1.0) == -121618014.278689189288130426667971145": -+double: 1 -+idouble: 1 -+Test "yn (10, 10.0) == -0.359814152183402722051986577343560609": -+double: 1 -+float: 1 -+idouble: 1 -+ifloat: 1 -+Test "yn (10, 2.0) == -129184.542208039282635913145923304214": -+double: 2 -+idouble: 2 -+Test "yn (3, 0.125) == -2612.69757350066712600220955744091741": -+double: 1 -+idouble: 1 -+Test "yn (3, 0.75) == -12.9877176234475433186319774484809207": -+double: 1 -+float: 1 -+idouble: 1 -+ifloat: 1 -+Test "yn (3, 10.0) == -0.251362657183837329779204747654240998": -+double: 1 -+float: 1 -+idouble: 1 -+ifloat: 1 -+Test "yn (3, 2.0) == -1.12778377684042778608158395773179238": -+double: 1 -+idouble: 1 -+ -+# Maximal error of functions: -+Function: "atan2": -+float: 3 -+ifloat: 3 -+ -+Function: "atanh": -+float: 1 -+ifloat: 1 -+ -+Function: Real part of "cacosh": -+double: 1 -+float: 7 -+idouble: 1 -+ifloat: 7 -+ -+Function: Imaginary part of "cacosh": -+double: 1 -+float: 3 -+idouble: 1 -+ifloat: 3 -+ -+Function: Real part of "casin": -+double: 1 -+float: 1 -+idouble: 1 -+ifloat: 1 -+ -+Function: Real part of "casinh": -+double: 5 -+float: 1 -+idouble: 5 -+ifloat: 1 -+ -+Function: Imaginary part of "casinh": -+double: 3 -+float: 6 -+idouble: 3 -+ifloat: 6 -+ -+Function: Real part of "catan": -+float: 4 -+ifloat: 4 -+ -+Function: Imaginary part of "catan": -+double: 1 -+float: 1 -+idouble: 1 -+ifloat: 1 -+ -+Function: Real part of "catanh": -+double: 4 -+idouble: 4 -+ -+Function: Imaginary part of "catanh": -+float: 6 -+ifloat: 6 -+ -+Function: "cbrt": -+double: 1 -+idouble: 1 -+ -+Function: Real part of "ccos": -+double: 1 -+float: 1 -+idouble: 1 -+ifloat: 1 -+ -+Function: Imaginary part of "ccos": -+float: 1 -+ifloat: 1 -+ -+Function: Real part of "ccosh": -+double: 1 -+float: 1 -+idouble: 1 -+ifloat: 1 -+ -+Function: Imaginary part of "ccosh": -+float: 1 -+ifloat: 1 -+ -+Function: Real part of "cexp": -+float: 1 -+ifloat: 1 -+ -+Function: Imaginary part of "cexp": -+float: 1 -+ifloat: 1 -+ -+Function: Real part of "clog": -+float: 1 -+ifloat: 1 -+ -+Function: Imaginary part of "clog": -+float: 3 -+ifloat: 3 -+ -+Function: Real part of "clog10": -+float: 1 -+ifloat: 1 -+ -+Function: Imaginary part of "clog10": -+double: 1 -+float: 5 -+idouble: 1 -+ifloat: 5 -+ -+Function: "cos": -+double: 2 -+float: 1 -+idouble: 2 -+ifloat: 1 -+ -+Function: Real part of "cpow": -+double: 2 -+float: 4 -+idouble: 2 -+ifloat: 4 -+ -+Function: Imaginary part of "cpow": -+double: 2 -+float: 2 -+idouble: 2 -+ifloat: 2 -+ -+Function: Real part of "csinh": -+float: 1 -+ifloat: 1 -+ -+Function: Imaginary part of "csinh": -+double: 1 -+float: 1 -+idouble: 1 -+ifloat: 1 -+ -+Function: Real part of "csqrt": -+float: 1 -+ifloat: 1 -+ -+Function: Real part of "ctan": -+double: 1 -+idouble: 1 -+ -+Function: Imaginary part of "ctan": -+double: 1 -+idouble: 1 -+ -+Function: Real part of "ctanh": -+double: 1 -+float: 2 -+idouble: 1 -+ifloat: 2 -+ -+Function: Imaginary part of "ctanh": -+float: 1 -+ifloat: 1 -+ -+Function: "erf": -+double: 1 -+idouble: 1 -+ -+Function: "erfc": -+double: 1 -+idouble: 1 -+ -+Function: "exp10": -+double: 6 -+float: 2 -+idouble: 6 -+ifloat: 2 -+ -+Function: "expm1": -+double: 1 -+float: 1 -+idouble: 1 -+ifloat: 1 -+ -+Function: "hypot": -+float: 1 -+ifloat: 1 -+ -+Function: "j0": -+double: 2 -+float: 2 -+idouble: 2 -+ifloat: 2 -+ -+Function: "j1": -+double: 1 -+float: 2 -+idouble: 1 -+ifloat: 2 -+ -+Function: "jn": -+double: 4 -+float: 4 -+idouble: 4 -+ifloat: 4 -+ -+Function: "lgamma": -+double: 1 -+float: 2 -+idouble: 1 -+ifloat: 2 -+ -+Function: "log10": -+double: 1 -+float: 2 -+idouble: 1 -+ifloat: 2 -+ -+Function: "log1p": -+float: 1 -+ifloat: 1 -+ -+Function: "sincos": -+double: 1 -+float: 1 -+idouble: 1 -+ifloat: 1 -+ -+Function: "tan": -+double: 1 -+idouble: 1 -+ -+Function: "tgamma": -+double: 1 -+float: 1 -+idouble: 1 -+ifloat: 1 -+ -+Function: "y0": -+double: 2 -+float: 1 -+idouble: 2 -+ifloat: 1 -+ -+Function: "y1": -+double: 3 -+float: 2 -+idouble: 3 -+ifloat: 2 -+ -+Function: "yn": -+double: 3 -+float: 2 -+idouble: 3 -+ifloat: 2 -+ -+# end of automatic generation -diff --git a/glibc-2.14.1/sysdeps/riscv/fpu/s_copysign.c b/glibc-2.14.1/sysdeps/riscv/fpu/s_copysign.c -new file mode 100644 -index 0000000..32dc5dc ---- /dev/null -+++ glibc-2.14.1/sysdeps/riscv/fpu/s_copysign.c -@@ -0,0 +1,9 @@ -+#include "math.h" -+ -+double __copysign(double x, double y) -+{ -+ double res; -+ asm ("fsgnj.d %0, %1, %2" : "=f"(res) : "f"(x), "f"(y)); -+ return res; -+} -+weak_alias (__copysign, copysign) -diff --git a/glibc-2.14.1/sysdeps/riscv/fpu/s_copysignf.c b/glibc-2.14.1/sysdeps/riscv/fpu/s_copysignf.c -new file mode 100644 -index 0000000..11d493b ---- /dev/null -+++ glibc-2.14.1/sysdeps/riscv/fpu/s_copysignf.c -@@ -0,0 +1,9 @@ -+#include "math.h" -+ -+float __copysignf(float x, float y) -+{ -+ float res; -+ asm ("fsgnj.s %0, %1, %2" : "=f"(res) : "f"(x), "f"(y)); -+ return res; -+} -+weak_alias (__copysignf, copysignf) -diff --git a/glibc-2.14.1/sysdeps/riscv/fpu/s_fabs.c b/glibc-2.14.1/sysdeps/riscv/fpu/s_fabs.c -new file mode 100644 -index 0000000..95f5b28 ---- /dev/null -+++ glibc-2.14.1/sysdeps/riscv/fpu/s_fabs.c -@@ -0,0 +1,9 @@ -+#include "math.h" -+ -+double __fabs(double x) -+{ -+ double res; -+ asm ("fabs.d %0, %1" : "=f"(res) : "f"(x)); -+ return res; -+} -+weak_alias (__fabs, fabs) -diff --git a/glibc-2.14.1/sysdeps/riscv/fpu/s_fabsf.c b/glibc-2.14.1/sysdeps/riscv/fpu/s_fabsf.c -new file mode 100644 -index 0000000..9df4ae6 ---- /dev/null -+++ glibc-2.14.1/sysdeps/riscv/fpu/s_fabsf.c -@@ -0,0 +1,9 @@ -+#include "math.h" -+ -+float __fabsf(float x) -+{ -+ float res; -+ asm ("fabs.s %0, %1" : "=f"(res) : "f"(x)); -+ return res; -+} -+weak_alias (__fabsf, fabsf) -diff --git a/glibc-2.14.1/sysdeps/riscv/fpu/s_fdim.c b/glibc-2.14.1/sysdeps/riscv/fpu/s_fdim.c -new file mode 100644 -index 0000000..9835f59 ---- /dev/null -+++ glibc-2.14.1/sysdeps/riscv/fpu/s_fdim.c -@@ -0,0 +1,17 @@ -+#include -+#include -+#include "fpu_control.h" -+ -+double __fdim (double x, double y) -+{ -+ double diff = x - y; -+ -+ if (x <= y) -+ return 0.0; -+ -+ if (__builtin_expect(_FCLASS(diff) & _FCLASS_INF, 0)) -+ errno = ERANGE; -+ -+ return diff; -+} -+weak_alias (__fdim, fdim) -diff --git a/glibc-2.14.1/sysdeps/riscv/fpu/s_fdimf.c b/glibc-2.14.1/sysdeps/riscv/fpu/s_fdimf.c -new file mode 100644 -index 0000000..480136c ---- /dev/null -+++ glibc-2.14.1/sysdeps/riscv/fpu/s_fdimf.c -@@ -0,0 +1,17 @@ -+#include -+#include -+#include "fpu_control.h" -+ -+float __fdimf (float x, float y) -+{ -+ float diff = x - y; -+ -+ if (x <= y) -+ return 0.0f; -+ -+ if (__builtin_expect(_FCLASS(diff) & _FCLASS_INF, 0)) -+ errno = ERANGE; -+ -+ return diff; -+} -+weak_alias (__fdimf, fdimf) -diff --git a/glibc-2.14.1/sysdeps/riscv/fpu/s_finite.c b/glibc-2.14.1/sysdeps/riscv/fpu/s_finite.c -new file mode 100644 -index 0000000..bf2135b ---- /dev/null -+++ glibc-2.14.1/sysdeps/riscv/fpu/s_finite.c -@@ -0,0 +1,9 @@ -+#include "math.h" -+#include "fpu_control.h" -+ -+int __finite(double x) -+{ -+ return _FCLASS(x) & ~(_FCLASS_INF | _FCLASS_NAN); -+} -+hidden_def (__finite) -+weak_alias (__finite, finite) -diff --git a/glibc-2.14.1/sysdeps/riscv/fpu/s_finitef.c b/glibc-2.14.1/sysdeps/riscv/fpu/s_finitef.c -new file mode 100644 -index 0000000..6448d2d ---- /dev/null -+++ glibc-2.14.1/sysdeps/riscv/fpu/s_finitef.c -@@ -0,0 +1,9 @@ -+#include "math.h" -+#include "fpu_control.h" -+ -+int __finitef(float x) -+{ -+ return _FCLASS(x) & ~(_FCLASS_INF | _FCLASS_NAN); -+} -+hidden_def (__finitef) -+weak_alias (__finitef, finitef) -diff --git a/glibc-2.14.1/sysdeps/riscv/fpu/s_fma.c b/glibc-2.14.1/sysdeps/riscv/fpu/s_fma.c -new file mode 100644 -index 0000000..797bc7d ---- /dev/null -+++ glibc-2.14.1/sysdeps/riscv/fpu/s_fma.c -@@ -0,0 +1,11 @@ -+#include -+#include -+#include -+ -+double __fma (double x, double y, double z) -+{ -+ double out; -+ asm volatile ("fmadd.d %0, %1, %2, %3" : "=f"(out) : "f"(x), "f"(y), "f"(z)); -+ return out; -+} -+weak_alias (__fma, fma) -diff --git a/glibc-2.14.1/sysdeps/riscv/fpu/s_fmaf.c b/glibc-2.14.1/sysdeps/riscv/fpu/s_fmaf.c -new file mode 100644 -index 0000000..11775f9 ---- /dev/null -+++ glibc-2.14.1/sysdeps/riscv/fpu/s_fmaf.c -@@ -0,0 +1,11 @@ -+#include -+#include -+#include -+ -+float __fmaf (float x, float y, float z) -+{ -+ float out; -+ asm volatile ("fmadd.s %0, %1, %2, %3" : "=f"(out) : "f"(x), "f"(y), "f"(z)); -+ return out; -+} -+weak_alias (__fmaf, fmaf) -diff --git a/glibc-2.14.1/sysdeps/riscv/fpu/s_fmax.c b/glibc-2.14.1/sysdeps/riscv/fpu/s_fmax.c -new file mode 100644 -index 0000000..8d2e662 ---- /dev/null -+++ glibc-2.14.1/sysdeps/riscv/fpu/s_fmax.c -@@ -0,0 +1,9 @@ -+#include -+ -+double __fmax (double x, double y) -+{ -+ double res; -+ asm ("fmax.d %0, %1, %2" : "=f"(res) : "f"(x), "f"(y)); -+ return res; -+} -+weak_alias (__fmax, fmax) -diff --git a/glibc-2.14.1/sysdeps/riscv/fpu/s_fmaxf.c b/glibc-2.14.1/sysdeps/riscv/fpu/s_fmaxf.c -new file mode 100644 -index 0000000..aa62172 ---- /dev/null -+++ glibc-2.14.1/sysdeps/riscv/fpu/s_fmaxf.c -@@ -0,0 +1,9 @@ -+#include -+ -+float __fmaxf (float x, float y) -+{ -+ float res; -+ asm ("fmax.s %0, %1, %2" : "=f"(res) : "f"(x), "f"(y)); -+ return res; -+} -+weak_alias (__fmaxf, fmaxf) -diff --git a/glibc-2.14.1/sysdeps/riscv/fpu/s_fmin.c b/glibc-2.14.1/sysdeps/riscv/fpu/s_fmin.c -new file mode 100644 -index 0000000..e4e37df ---- /dev/null -+++ glibc-2.14.1/sysdeps/riscv/fpu/s_fmin.c -@@ -0,0 +1,9 @@ -+#include -+ -+double __fmin (double x, double y) -+{ -+ double res; -+ asm ("fmin.d %0, %1, %2" : "=f"(res) : "f"(x), "f"(y)); -+ return res; -+} -+weak_alias (__fmin, fmin) -diff --git a/glibc-2.14.1/sysdeps/riscv/fpu/s_fminf.c b/glibc-2.14.1/sysdeps/riscv/fpu/s_fminf.c -new file mode 100644 -index 0000000..5d25bc2 ---- /dev/null -+++ glibc-2.14.1/sysdeps/riscv/fpu/s_fminf.c -@@ -0,0 +1,9 @@ -+#include -+ -+float __fminf (float x, float y) -+{ -+ float res; -+ asm ("fmin.s %0, %1, %2" : "=f"(res) : "f"(x), "f"(y)); -+ return res; -+} -+weak_alias (__fminf, fminf) -diff --git a/glibc-2.14.1/sysdeps/riscv/fpu/s_fpclassify.c b/glibc-2.14.1/sysdeps/riscv/fpu/s_fpclassify.c -new file mode 100644 -index 0000000..2b58c3f ---- /dev/null -+++ glibc-2.14.1/sysdeps/riscv/fpu/s_fpclassify.c -@@ -0,0 +1,18 @@ -+#include -+#include "fpu_control.h" -+#include "math_private.h" -+ -+int __fpclassify (double x) -+{ -+ int cls = _FCLASS(x); -+ if (__builtin_expect(cls & _FCLASS_NORM, _FCLASS_NORM)) -+ return FP_NORMAL; -+ if (__builtin_expect(cls & _FCLASS_ZERO, _FCLASS_ZERO)) -+ return FP_ZERO; -+ if (__builtin_expect(cls & _FCLASS_SUBNORM, _FCLASS_SUBNORM)) -+ return FP_SUBNORMAL; -+ if (__builtin_expect(cls & _FCLASS_INF, _FCLASS_INF)) -+ return FP_INFINITE; -+ return FP_NAN; -+} -+libm_hidden_def (__fpclassify) -diff --git a/glibc-2.14.1/sysdeps/riscv/fpu/s_fpclassifyf.c b/glibc-2.14.1/sysdeps/riscv/fpu/s_fpclassifyf.c -new file mode 100644 -index 0000000..fae20fa ---- /dev/null -+++ glibc-2.14.1/sysdeps/riscv/fpu/s_fpclassifyf.c -@@ -0,0 +1,18 @@ -+#include -+#include "fpu_control.h" -+#include "math_private.h" -+ -+int __fpclassifyf (float x) -+{ -+ int cls = _FCLASS(x); -+ if (__builtin_expect(cls & _FCLASS_NORM, _FCLASS_NORM)) -+ return FP_NORMAL; -+ if (__builtin_expect(cls & _FCLASS_ZERO, _FCLASS_ZERO)) -+ return FP_ZERO; -+ if (__builtin_expect(cls & _FCLASS_SUBNORM, _FCLASS_SUBNORM)) -+ return FP_SUBNORMAL; -+ if (__builtin_expect(cls & _FCLASS_INF, _FCLASS_INF)) -+ return FP_INFINITE; -+ return FP_NAN; -+} -+libm_hidden_def (__fpclassifyf) -diff --git a/glibc-2.14.1/sysdeps/riscv/fpu/s_isinf.c b/glibc-2.14.1/sysdeps/riscv/fpu/s_isinf.c -new file mode 100644 -index 0000000..339d97f ---- /dev/null -+++ glibc-2.14.1/sysdeps/riscv/fpu/s_isinf.c -@@ -0,0 +1,10 @@ -+#include "math.h" -+#include "fpu_control.h" -+ -+int __isinf(double x) -+{ -+ int cls = _FCLASS(x); -+ return -((cls & _FCLASS_MINF) ? 1 : 0) | ((cls & _FCLASS_PINF) ? 1 : 0); -+} -+hidden_def (__isinf) -+weak_alias (__isinf, isinf) -diff --git a/glibc-2.14.1/sysdeps/riscv/fpu/s_isinff.c b/glibc-2.14.1/sysdeps/riscv/fpu/s_isinff.c -new file mode 100644 -index 0000000..501342e ---- /dev/null -+++ glibc-2.14.1/sysdeps/riscv/fpu/s_isinff.c -@@ -0,0 +1,10 @@ -+#include "math.h" -+#include "fpu_control.h" -+ -+int __isinff(float x) -+{ -+ int cls = _FCLASS(x); -+ return -((cls & _FCLASS_MINF) ? 1 : 0) | ((cls & _FCLASS_PINF) ? 1 : 0); -+} -+hidden_def (__isinff) -+weak_alias (__isinff, isinff) -diff --git a/glibc-2.14.1/sysdeps/riscv/fpu/s_isnan.c b/glibc-2.14.1/sysdeps/riscv/fpu/s_isnan.c -new file mode 100644 -index 0000000..dcbb629 ---- /dev/null -+++ glibc-2.14.1/sysdeps/riscv/fpu/s_isnan.c -@@ -0,0 +1,9 @@ -+#include "math.h" -+#include "fpu_control.h" -+ -+int __isnan(double x) -+{ -+ return _FCLASS(x) & _FCLASS_NAN; -+} -+hidden_def (__isnan) -+weak_alias (__isnan, isnan) -diff --git a/glibc-2.14.1/sysdeps/riscv/fpu/s_isnanf.c b/glibc-2.14.1/sysdeps/riscv/fpu/s_isnanf.c -new file mode 100644 -index 0000000..78e9d0c ---- /dev/null -+++ glibc-2.14.1/sysdeps/riscv/fpu/s_isnanf.c -@@ -0,0 +1,9 @@ -+#include "math.h" -+#include "fpu_control.h" -+ -+int __isnanf(float x) -+{ -+ return _FCLASS(x) & _FCLASS_NAN; -+} -+hidden_def (__isnanf) -+weak_alias (__isnanf, isnanf) -diff --git a/glibc-2.14.1/sysdeps/riscv/fpu/s_signbit.c b/glibc-2.14.1/sysdeps/riscv/fpu/s_signbit.c -new file mode 100644 -index 0000000..5f99c3f ---- /dev/null -+++ glibc-2.14.1/sysdeps/riscv/fpu/s_signbit.c -@@ -0,0 +1,18 @@ -+#include -+#undef __USE_EXTERN_INLINES -+#include -+#include -+#include "math_private.h" -+ -+int __signbit (double x) -+{ -+#ifdef __riscv64 -+ int64_t hx; -+ EXTRACT_WORDS64 (hx, x); -+ return hx < 0; -+#else -+ int32_t hx; -+ GET_HIGH_WORD (hx, x); -+ return hx < 0; -+#endif -+} -diff --git a/glibc-2.14.1/sysdeps/riscv/fpu/s_signbitf.c b/glibc-2.14.1/sysdeps/riscv/fpu/s_signbitf.c -new file mode 100644 -index 0000000..6e25688 ---- /dev/null -+++ glibc-2.14.1/sysdeps/riscv/fpu/s_signbitf.c -@@ -0,0 +1,12 @@ -+#include -+#undef __USE_EXTERN_INLINES -+#include -+#include -+#include "math_private.h" -+ -+int __signbitf (float x) -+{ -+ int32_t hx; -+ GET_FLOAT_WORD (hx, x); -+ return hx < 0; -+} -diff --git a/glibc-2.14.1/sysdeps/riscv/fpu_control.h b/glibc-2.14.1/sysdeps/riscv/fpu_control.h -new file mode 100644 -index 0000000..4c36db5 ---- /dev/null -+++ glibc-2.14.1/sysdeps/riscv/fpu_control.h -@@ -0,0 +1,92 @@ -+/* FPU control word bits. Mips version. -+ Copyright (C) 1996, 1997, 1998, 1999, 2000, 2006, 2008 -+ Free Software Foundation, Inc. -+ This file is part of the GNU C Library. -+ Contributed by Olaf Flebbe and Ralf Baechle. -+ -+ The GNU C Library is free software; you can redistribute it and/or -+ modify it under the terms of the GNU Lesser General Public -+ License as published by the Free Software Foundation; either -+ version 2.1 of the License, or (at your option) any later version. -+ -+ The GNU C Library is distributed in the hope that it will be useful, -+ but WITHOUT ANY WARRANTY; without even the implied warranty of -+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU -+ Lesser General Public License for more details. -+ -+ You should have received a copy of the GNU Lesser General Public -+ License along with the GNU C Library; if not, write to the Free -+ Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA -+ 02111-1307 USA. */ -+ -+#ifndef _FPU_CONTROL_H -+#define _FPU_CONTROL_H -+ -+#include -+ -+#ifdef __riscv_soft_float -+ -+#define _FPU_RESERVED 0xffffffff -+#define _FPU_DEFAULT 0x00000000 -+typedef unsigned int fpu_control_t; -+#define _FPU_GETCW(cw) 0 -+#define _FPU_SETCW(cw) do { } while (0) -+extern fpu_control_t __fpu_control; -+ -+#else /* __mips_soft_float */ -+ -+/* rounding control */ -+#define _FPU_RC_NEAREST 0x0 -+#define _FPU_RC_ZERO 0x1 -+#define _FPU_RC_DOWN 0x2 -+#define _FPU_RC_UP 0x3 -+ -+#define _FPU_RESERVED 0 /* No reserved bits in FSR */ -+ -+/* The fdlibm code requires strict IEEE double precision arithmetic, -+ and no interrupts for exceptions, rounding to nearest. */ -+ -+#define _FPU_DEFAULT 0 -+ -+/* IEEE: same as above */ -+#define _FPU_IEEE _FPU_DEFAULT -+ -+/* Type of the control word. */ -+typedef unsigned int fpu_control_t __attribute__ ((__mode__ (__SI__))); -+ -+/* Macros for accessing the hardware control word. */ -+#define _FPU_GETCW(cw) __asm__ volatile ("frsr %0" : "=r" (cw)) -+#define _FPU_GETROUND(cw) __asm__ volatile ("frrm %0" : "=r" (cw)) -+#define _FPU_GETFLAGS(cw) __asm__ volatile ("frflags %0" : "=r" (cw)) -+#define _FPU_SETCW(cw) __asm__ volatile ("fssr %z0" : : "rJ" (cw)) -+#define _FPU_SETROUND(cw) __asm__ volatile ("fsrm %z0" : : "rJ" (cw)) -+#define _FPU_SETFLAGS(cw) __asm__ volatile ("fsflags %z0" : : "rJ" (cw)) -+ -+/* Default control word set at startup. */ -+extern fpu_control_t __fpu_control; -+ -+#define _FCLASS(x) ({ int res; \ -+ if (sizeof(x) == 4) asm ("fclass.s %0, %1" : "=r"(res) : "f"(x)); \ -+ else if (sizeof(x) == 8) asm ("fclass.d %0, %1" : "=r"(res) : "f"(x)); \ -+ else abort(); \ -+ res; }) -+ -+#define _FCLASS_MINF (1<<0) -+#define _FCLASS_MNORM (1<<1) -+#define _FCLASS_MSUBNORM (1<<2) -+#define _FCLASS_MZERO (1<<3) -+#define _FCLASS_PZERO (1<<4) -+#define _FCLASS_PSUBNORM (1<<5) -+#define _FCLASS_PNORM (1<<6) -+#define _FCLASS_PINF (1<<7) -+#define _FCLASS_SNAN (1<<8) -+#define _FCLASS_QNAN (1<<9) -+#define _FCLASS_ZERO (_FCLASS_MZERO | _FCLASS_PZERO) -+#define _FCLASS_SUBNORM (_FCLASS_MSUBNORM | _FCLASS_PSUBNORM) -+#define _FCLASS_NORM (_FCLASS_MNORM | _FCLASS_PNORM) -+#define _FCLASS_INF (_FCLASS_MINF | _FCLASS_PINF) -+#define _FCLASS_NAN (_FCLASS_SNAN | _FCLASS_QNAN) -+ -+#endif /* __mips_soft_float */ -+ -+#endif /* fpu_control.h */ -diff --git a/glibc-2.14.1/sysdeps/riscv/gccframe.h b/glibc-2.14.1/sysdeps/riscv/gccframe.h -new file mode 100644 -index 0000000..ec9311c ---- /dev/null -+++ glibc-2.14.1/sysdeps/riscv/gccframe.h -@@ -0,0 +1,22 @@ -+/* Definition of object in frame unwind info. mips version. -+ Copyright (C) 2001 Free Software Foundation, Inc. -+ This file is part of the GNU C Library. -+ -+ The GNU C Library is free software; you can redistribute it and/or -+ modify it under the terms of the GNU Lesser General Public -+ License as published by the Free Software Foundation; either -+ version 2.1 of the License, or (at your option) any later version. -+ -+ The GNU C Library is distributed in the hope that it will be useful, -+ but WITHOUT ANY WARRANTY; without even the implied warranty of -+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU -+ Lesser General Public License for more details. -+ -+ You should have received a copy of the GNU Lesser General Public -+ License along with the GNU C Library; if not, write to the Free -+ Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA -+ 02111-1307 USA. */ -+ -+#define FIRST_PSEUDO_REGISTER 76 -+ -+#include -diff --git a/glibc-2.14.1/sysdeps/riscv/ieee754.h b/glibc-2.14.1/sysdeps/riscv/ieee754.h -new file mode 100644 -index 0000000..912e088 ---- /dev/null -+++ glibc-2.14.1/sysdeps/riscv/ieee754.h -@@ -0,0 +1,325 @@ -+/* Copyright (C) 1992, 1995, 1996, 1999, 2002, 2003 -+ Free Software Foundation, Inc. -+ This file is part of the GNU C Library. -+ -+ The GNU C Library is free software; you can redistribute it and/or -+ modify it under the terms of the GNU Lesser General Public -+ License as published by the Free Software Foundation; either -+ version 2.1 of the License, or (at your option) any later version. -+ -+ The GNU C Library is distributed in the hope that it will be useful, -+ but WITHOUT ANY WARRANTY; without even the implied warranty of -+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU -+ Lesser General Public License for more details. -+ -+ You should have received a copy of the GNU Lesser General Public -+ License along with the GNU C Library; if not, write to the Free -+ Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA -+ 02111-1307 USA. */ -+ -+#ifndef _IEEE754_H -+ -+#define _IEEE754_H 1 -+#include -+ -+#include -+ -+#include -+ -+__BEGIN_DECLS -+ -+union ieee754_float -+ { -+ float f; -+ -+ /* This is the IEEE 754 single-precision format. */ -+ struct -+ { -+#if __BYTE_ORDER == __BIG_ENDIAN -+ unsigned int negative:1; -+ unsigned int exponent:8; -+ unsigned int mantissa:23; -+#endif /* Big endian. */ -+#if __BYTE_ORDER == __LITTLE_ENDIAN -+ unsigned int mantissa:23; -+ unsigned int exponent:8; -+ unsigned int negative:1; -+#endif /* Little endian. */ -+ } ieee; -+ -+ /* This format makes it easier to see if a NaN is a signalling NaN. */ -+ struct -+ { -+#if __BYTE_ORDER == __BIG_ENDIAN -+ unsigned int negative:1; -+ unsigned int exponent:8; -+ unsigned int quiet_nan:1; -+ unsigned int mantissa:22; -+#endif /* Big endian. */ -+#if __BYTE_ORDER == __LITTLE_ENDIAN -+ unsigned int mantissa:22; -+ unsigned int quiet_nan:1; -+ unsigned int exponent:8; -+ unsigned int negative:1; -+#endif /* Little endian. */ -+ } ieee_nan; -+ }; -+ -+#define IEEE754_FLOAT_BIAS 0x7f /* Added to exponent. */ -+ -+ -+union ieee754_double -+ { -+ double d; -+ -+ /* This is the IEEE 754 double-precision format. */ -+ struct -+ { -+#if __BYTE_ORDER == __BIG_ENDIAN -+ unsigned int negative:1; -+ unsigned int exponent:11; -+ /* Together these comprise the mantissa. */ -+ unsigned int mantissa0:20; -+ unsigned int mantissa1:32; -+#endif /* Big endian. */ -+#if __BYTE_ORDER == __LITTLE_ENDIAN -+# if __FLOAT_WORD_ORDER == __BIG_ENDIAN -+ unsigned int mantissa0:20; -+ unsigned int exponent:11; -+ unsigned int negative:1; -+ unsigned int mantissa1:32; -+# else -+ /* Together these comprise the mantissa. */ -+ unsigned int mantissa1:32; -+ unsigned int mantissa0:20; -+ unsigned int exponent:11; -+ unsigned int negative:1; -+# endif -+#endif /* Little endian. */ -+ } ieee; -+ -+ /* This format makes it easier to see if a NaN is a signalling NaN. */ -+ struct -+ { -+#if __BYTE_ORDER == __BIG_ENDIAN -+ unsigned int negative:1; -+ unsigned int exponent:11; -+ unsigned int quiet_nan:1; -+ /* Together these comprise the mantissa. */ -+ unsigned int mantissa0:19; -+ unsigned int mantissa1:32; -+#else -+# if __FLOAT_WORD_ORDER == __BIG_ENDIAN -+ unsigned int mantissa0:19; -+ unsigned int quiet_nan:1; -+ unsigned int exponent:11; -+ unsigned int negative:1; -+ unsigned int mantissa1:32; -+# else -+ /* Together these comprise the mantissa. */ -+ unsigned int mantissa1:32; -+ unsigned int mantissa0:19; -+ unsigned int quiet_nan:1; -+ unsigned int exponent:11; -+ unsigned int negative:1; -+# endif -+#endif -+ } ieee_nan; -+ }; -+ -+#define IEEE754_DOUBLE_BIAS 0x3ff /* Added to exponent. */ -+ -+#if LDBL_MANT_DIG == 113 -+ -+union ieee854_long_double -+ { -+ long double d; -+ -+ /* This is the IEEE 854 quad-precision format. */ -+ struct -+ { -+#if __BYTE_ORDER == __BIG_ENDIAN -+ unsigned int negative:1; -+ unsigned int exponent:15; -+ /* Together these comprise the mantissa. */ -+ unsigned int mantissa0:16; -+ unsigned int mantissa1:32; -+ unsigned int mantissa2:32; -+ unsigned int mantissa3:32; -+#endif /* Big endian. */ -+#if __BYTE_ORDER == __LITTLE_ENDIAN -+ /* Together these comprise the mantissa. */ -+ unsigned int mantissa3:32; -+ unsigned int mantissa2:32; -+ unsigned int mantissa1:32; -+ unsigned int mantissa0:16; -+ unsigned int exponent:15; -+ unsigned int negative:1; -+#endif /* Little endian. */ -+ } ieee; -+ -+ /* This format makes it easier to see if a NaN is a signalling NaN. */ -+ struct -+ { -+#if __BYTE_ORDER == __BIG_ENDIAN -+ unsigned int negative:1; -+ unsigned int exponent:15; -+ unsigned int quiet_nan:1; -+ /* Together these comprise the mantissa. */ -+ unsigned int mantissa0:15; -+ unsigned int mantissa1:32; -+ unsigned int mantissa2:32; -+ unsigned int mantissa3:32; -+#endif /* Big endian. */ -+#if __BYTE_ORDER == __LITTLE_ENDIAN -+ /* Together these comprise the mantissa. */ -+ unsigned int mantissa3:32; -+ unsigned int mantissa2:32; -+ unsigned int mantissa1:32; -+ unsigned int mantissa0:15; -+ unsigned int quiet_nan:1; -+ unsigned int exponent:15; -+ unsigned int negative:1; -+#endif /* Little endian. */ -+ } ieee_nan; -+ }; -+ -+#define IEEE854_LONG_DOUBLE_BIAS 0x3fff /* Added to exponent. */ -+ -+#elif LDBL_MANT_DIG == 64 -+ -+union ieee854_long_double -+ { -+ long double d; -+ -+ /* This is the IEEE 854 double-extended-precision format. */ -+ struct -+ { -+#if __BYTE_ORDER == __BIG_ENDIAN -+ unsigned int negative:1; -+ unsigned int exponent:15; -+ unsigned int empty:16; -+ unsigned int mantissa0:32; -+ unsigned int mantissa1:32; -+#endif -+#if __BYTE_ORDER == __LITTLE_ENDIAN -+# if __FLOAT_WORD_ORDER == __BIG_ENDIAN -+ unsigned int exponent:15; -+ unsigned int negative:1; -+ unsigned int empty:16; -+ unsigned int mantissa0:32; -+ unsigned int mantissa1:32; -+# else -+ unsigned int mantissa1:32; -+ unsigned int mantissa0:32; -+ unsigned int exponent:15; -+ unsigned int negative:1; -+ unsigned int empty:16; -+# endif -+#endif -+ } ieee; -+ -+ /* This is for NaNs in the IEEE 854 double-extended-precision format. */ -+ struct -+ { -+#if __BYTE_ORDER == __BIG_ENDIAN -+ unsigned int negative:1; -+ unsigned int exponent:15; -+ unsigned int empty:16; -+ unsigned int one:1; -+ unsigned int quiet_nan:1; -+ unsigned int mantissa0:30; -+ unsigned int mantissa1:32; -+#endif -+#if __BYTE_ORDER == __LITTLE_ENDIAN -+# if __FLOAT_WORD_ORDER == __BIG_ENDIAN -+ unsigned int exponent:15; -+ unsigned int negative:1; -+ unsigned int empty:16; -+ unsigned int mantissa0:30; -+ unsigned int quiet_nan:1; -+ unsigned int one:1; -+ unsigned int mantissa1:32; -+# else -+ unsigned int mantissa1:32; -+ unsigned int mantissa0:30; -+ unsigned int quiet_nan:1; -+ unsigned int one:1; -+ unsigned int exponent:15; -+ unsigned int negative:1; -+ unsigned int empty:16; -+# endif -+#endif -+ } ieee_nan; -+ }; -+ -+#define IEEE854_LONG_DOUBLE_BIAS 0x3fff -+ -+#elif LDBL_MANT_DIG == 53 -+ -+union ieee854_long_double -+ { -+ long double d; -+ -+ /* This is the IEEE 754 double-precision format. */ -+ struct -+ { -+#if __BYTE_ORDER == __BIG_ENDIAN -+ unsigned int negative:1; -+ unsigned int exponent:11; -+ /* Together these comprise the mantissa. */ -+ unsigned int mantissa0:20; -+ unsigned int mantissa1:32; -+#endif /* Big endian. */ -+#if __BYTE_ORDER == __LITTLE_ENDIAN -+# if __FLOAT_WORD_ORDER == __BIG_ENDIAN -+ unsigned int mantissa0:20; -+ unsigned int exponent:11; -+ unsigned int negative:1; -+ unsigned int mantissa1:32; -+# else -+ /* Together these comprise the mantissa. */ -+ unsigned int mantissa1:32; -+ unsigned int mantissa0:20; -+ unsigned int exponent:11; -+ unsigned int negative:1; -+# endif -+#endif /* Little endian. */ -+ } ieee; -+ -+ /* This format makes it easier to see if a NaN is a signalling NaN. */ -+ struct -+ { -+#if __BYTE_ORDER == __BIG_ENDIAN -+ unsigned int negative:1; -+ unsigned int exponent:11; -+ unsigned int quiet_nan:1; -+ /* Together these comprise the mantissa. */ -+ unsigned int mantissa0:19; -+ unsigned int mantissa1:32; -+#else -+# if __FLOAT_WORD_ORDER == __BIG_ENDIAN -+ unsigned int mantissa0:19; -+ unsigned int quiet_nan:1; -+ unsigned int exponent:11; -+ unsigned int negative:1; -+ unsigned int mantissa1:32; -+# else -+ /* Together these comprise the mantissa. */ -+ unsigned int mantissa1:32; -+ unsigned int mantissa0:19; -+ unsigned int quiet_nan:1; -+ unsigned int exponent:11; -+ unsigned int negative:1; -+# endif -+#endif -+ } ieee_nan; -+ }; -+ -+#define IEEE854_LONG_DOUBLE_BIAS 0x3ff /* Added to exponent. */ -+ -+#endif /* LDBL_MANT_DIG == 53 */ -+ -+__END_DECLS -+ -+#endif /* ieee754.h */ -diff --git a/glibc-2.14.1/sysdeps/riscv/jmpbuf-unwind.h b/glibc-2.14.1/sysdeps/riscv/jmpbuf-unwind.h -new file mode 100644 -index 0000000..bfa1a64 ---- /dev/null -+++ glibc-2.14.1/sysdeps/riscv/jmpbuf-unwind.h -@@ -0,0 +1,46 @@ -+/* Copyright (C) 2003, 2005, 2006 Free Software Foundation, Inc. -+ This file is part of the GNU C Library. -+ -+ The GNU C Library is free software; you can redistribute it and/or -+ modify it under the terms of the GNU Lesser General Public -+ License as published by the Free Software Foundation; either -+ version 2.1 of the License, or (at your option) any later version. -+ -+ The GNU C Library is distributed in the hope that it will be useful, -+ but WITHOUT ANY WARRANTY; without even the implied warranty of -+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU -+ Lesser General Public License for more details. -+ -+ You should have received a copy of the GNU Lesser General Public -+ License along with the GNU C Library; if not, write to the Free -+ Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA -+ 02111-1307 USA. */ -+ -+#include -+#include -+#include -+#include -+ -+/* Test if longjmp to JMPBUF would unwind the frame -+ containing a local variable at ADDRESS. */ -+#define _JMPBUF_UNWINDS(jmpbuf, address, demangle) \ -+ ((void *) (address) < (void *) demangle ((jmpbuf)[0].__sp)) -+ -+#define _JMPBUF_CFA_UNWINDS_ADJ(_jmpbuf, _context, _adj) \ -+ _JMPBUF_UNWINDS_ADJ (_jmpbuf, (void *) _Unwind_GetCFA (_context), _adj) -+ -+static inline uintptr_t __attribute__ ((unused)) -+_jmpbuf_sp (__jmp_buf regs) -+{ -+ uintptr_t sp = regs[0].__sp; -+#ifdef PTR_DEMANGLE -+ PTR_DEMANGLE (sp); -+#endif -+ return sp; -+} -+ -+#define _JMPBUF_UNWINDS_ADJ(_jmpbuf, _address, _adj) \ -+ ((uintptr_t) (_address) - (_adj) < _jmpbuf_sp (_jmpbuf) - (_adj)) -+ -+/* We use the normal longjmp for unwinding. */ -+#define __libc_unwind_longjmp(buf, val) __libc_longjmp (buf, val) -diff --git a/glibc-2.14.1/sysdeps/riscv/ldsodefs.h b/glibc-2.14.1/sysdeps/riscv/ldsodefs.h -new file mode 100644 -index 0000000..8820a08 ---- /dev/null -+++ glibc-2.14.1/sysdeps/riscv/ldsodefs.h -@@ -0,0 +1,70 @@ -+/* Run-time dynamic linker data structures for loaded ELF shared objects. -+ Copyright (C) 2000, 2002, 2003, 2006, 2007 Free Software Foundation, Inc. -+ This file is part of the GNU C Library. -+ -+ The GNU C Library is free software; you can redistribute it and/or -+ modify it under the terms of the GNU Lesser General Public -+ License as published by the Free Software Foundation; either -+ version 2.1 of the License, or (at your option) any later version. -+ -+ The GNU C Library is distributed in the hope that it will be useful, -+ but WITHOUT ANY WARRANTY; without even the implied warranty of -+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU -+ Lesser General Public License for more details. -+ -+ You should have received a copy of the GNU Lesser General Public -+ License along with the GNU C Library; if not, write to the Free -+ Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA -+ 02111-1307 USA. */ -+ -+#ifndef _MIPS_LDSODEFS_H -+#define _MIPS_LDSODEFS_H 1 -+ -+#include -+ -+struct La_mips_32_regs; -+struct La_mips_32_retval; -+struct La_mips_64_regs; -+struct La_mips_64_retval; -+ -+#define ARCH_PLTENTER_MEMBERS \ -+ Elf32_Addr (*mips_o32_gnu_pltenter) (Elf32_Sym *, unsigned int, \ -+ uintptr_t *, uintptr_t *, \ -+ const struct La_mips_32_regs *, \ -+ unsigned int *, const char *name, \ -+ long int *framesizep); \ -+ Elf32_Addr (*mips_n32_gnu_pltenter) (Elf32_Sym *, unsigned int, \ -+ uintptr_t *, uintptr_t *, \ -+ const struct La_mips_64_regs *, \ -+ unsigned int *, const char *name, \ -+ long int *framesizep); \ -+ Elf64_Addr (*mips_n64_gnu_pltenter) (Elf64_Sym *, unsigned int, \ -+ uintptr_t *, uintptr_t *, \ -+ const struct La_mips_64_regs *, \ -+ unsigned int *, const char *name, \ -+ long int *framesizep); -+ -+#define ARCH_PLTEXIT_MEMBERS \ -+ unsigned int (*mips_o32_gnu_pltexit) (Elf32_Sym *, unsigned int, \ -+ uintptr_t *, uintptr_t *, \ -+ const struct La_mips_32_regs *, \ -+ struct La_mips_32_retval *, \ -+ const char *); \ -+ unsigned int (*mips_n32_gnu_pltexit) (Elf32_Sym *, unsigned int, \ -+ uintptr_t *, uintptr_t *, \ -+ const struct La_mips_64_regs *, \ -+ struct La_mips_64_retval *, \ -+ const char *); \ -+ unsigned int (*mips_n64_gnu_pltexit) (Elf64_Sym *, unsigned int, \ -+ uintptr_t *, uintptr_t *, \ -+ const struct La_mips_64_regs *, \ -+ struct La_mips_64_retval *, \ -+ const char *); -+ -+/* The MIPS ABI specifies that the dynamic section has to be read-only. */ -+ -+#define DL_RO_DYN_SECTION 1 -+ -+#include_next -+ -+#endif -diff --git a/glibc-2.14.1/sysdeps/riscv/libc-tls.c b/glibc-2.14.1/sysdeps/riscv/libc-tls.c -new file mode 100644 -index 0000000..a3d6301 ---- /dev/null -+++ glibc-2.14.1/sysdeps/riscv/libc-tls.c -@@ -0,0 +1,37 @@ -+/* Thread-local storage handling in the ELF dynamic linker. MIPS version. -+ Copyright (C) 2005 Free Software Foundation, Inc. -+ This file is part of the GNU C Library. -+ -+ The GNU C Library is free software; you can redistribute it and/or -+ modify it under the terms of the GNU Lesser General Public -+ License as published by the Free Software Foundation; either -+ version 2.1 of the License, or (at your option) any later version. -+ -+ The GNU C Library is distributed in the hope that it will be useful, -+ but WITHOUT ANY WARRANTY; without even the implied warranty of -+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU -+ Lesser General Public License for more details. -+ -+ You should have received a copy of the GNU Lesser General Public -+ License along with the GNU C Library; if not, write to the Free -+ Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA -+ 02111-1307 USA. */ -+ -+#include -+#include -+ -+#if USE_TLS -+ -+/* On MIPS, linker optimizations are not required, so __tls_get_addr -+ can be called even in statically linked binaries. In this case module -+ must be always 1 and PT_TLS segment exist in the binary, otherwise it -+ would not link. */ -+ -+void * -+__tls_get_addr (tls_index *ti) -+{ -+ dtv_t *dtv = THREAD_DTV (); -+ return (char *) dtv[1].pointer.val + GET_ADDR_OFFSET; -+} -+ -+#endif -diff --git a/glibc-2.14.1/sysdeps/riscv/memcpy.c b/glibc-2.14.1/sysdeps/riscv/memcpy.c -new file mode 100644 -index 0000000..3706ba6 ---- /dev/null -+++ glibc-2.14.1/sysdeps/riscv/memcpy.c -@@ -0,0 +1,65 @@ -+#include -+#include -+ -+#undef memcpy -+#undef __memcpy_g -+ -+void* __memcpy_g(void* aa, const void* bb, size_t n) -+{ -+ #define BODY(a, b, t) { \ -+ t tt = *b; \ -+ a++, b++; \ -+ *(a-1) = tt; \ -+ } -+ -+ char* a = (char*)aa; -+ const char* b = (const char*)bb; -+ char* end = a+n; -+ uintptr_t msk = sizeof(long)-1; -+ if (__builtin_expect(((uintptr_t)a & msk) != ((uintptr_t)b & msk) || n < sizeof(long), 0)) -+ { -+foo: -+ if (__builtin_expect(a < end, 1)) -+ while (a < end) -+ BODY(a, b, char); -+ return aa; -+ } -+ -+ if (__builtin_expect(((uintptr_t)a & msk) != 0, 0)) -+ while ((uintptr_t)a & msk) -+ BODY(a, b, char); -+ -+ long* __restrict__ la = (long*)a; -+ const long* __restrict__ lb = (const long*)b; -+ long* lend = (long*)((uintptr_t)end & ~msk); -+ -+ if (__builtin_expect(la < lend-8, 0)) -+ { -+ while (la < lend-8) -+ { -+ *la++ = *lb++; -+ *la++ = *lb++; -+ *la++ = *lb++; -+ *la++ = *lb++; -+ *la++ = *lb++; -+ *la++ = *lb++; -+ *la++ = *lb++; -+ *la++ = *lb++; -+ *la++ = *lb++; -+ } -+ if (la == lend) -+ goto bar; -+ } -+ -+ do BODY(la, lb, long) while (la < lend); -+ -+bar: -+ a = (char*)la; -+ b = (const char*)lb; -+ if (__builtin_expect(a < end, 0)) -+ goto foo; -+ return aa; -+} -+libc_hidden_def (__memcpy_g) -+strong_alias (__memcpy_g, memcpy) -+libc_hidden_builtin_def (memcpy) -diff --git a/glibc-2.14.1/sysdeps/riscv/memset.c b/glibc-2.14.1/sysdeps/riscv/memset.c -new file mode 100644 -index 0000000..cfde2fe ---- /dev/null -+++ glibc-2.14.1/sysdeps/riscv/memset.c -@@ -0,0 +1,43 @@ -+typedef unsigned long size_t; -+//#include -+ -+void* memset(void* dst, int val, size_t n) -+{ -+ void* dst0 = dst; -+ void* end = dst + n; -+ unsigned char v = val; -+ -+ /* is dst word-aligned? */ -+ if (((long)dst & (sizeof(long)-1)) == 0) -+ { -+ long lval = v; -+ lval |= lval << 8; -+ lval |= lval << 16; -+ #ifdef __riscv64 -+ lval |= lval << 32; -+ #elif !defined(__riscv32) -+ # error -+ #endif -+ -+ /* set 4 words at a time */ -+ for ( ; dst <= end - 4*sizeof(long); dst += 4*sizeof(long)) -+ { -+ *(long*)(dst+0*sizeof(long)) = lval; -+ *(long*)(dst+1*sizeof(long)) = lval; -+ *(long*)(dst+2*sizeof(long)) = lval; -+ *(long*)(dst+3*sizeof(long)) = lval; -+ } -+ -+ /* set a word at a time */ -+ for ( ; dst <= end - sizeof(long); dst += sizeof(long)) -+ *(long*)dst = lval; -+ } -+ -+ /* set a byte at a time */ -+ for ( ; dst < end; dst++) -+ *(unsigned char*)dst = v; -+ -+ return dst0; -+} -+ -+weak_alias (memset, __GI_memset) -diff --git a/glibc-2.14.1/sysdeps/riscv/memusage.h b/glibc-2.14.1/sysdeps/riscv/memusage.h -new file mode 100644 -index 0000000..c558a06 ---- /dev/null -+++ glibc-2.14.1/sysdeps/riscv/memusage.h -@@ -0,0 +1,21 @@ -+/* Copyright (C) 2000 Free Software Foundation, Inc. -+ This file is part of the GNU C Library. -+ -+ The GNU C Library is free software; you can redistribute it and/or -+ modify it under the terms of the GNU Lesser General Public -+ License as published by the Free Software Foundation; either -+ version 2.1 of the License, or (at your option) any later version. -+ -+ The GNU C Library is distributed in the hope that it will be useful, -+ but WITHOUT ANY WARRANTY; without even the implied warranty of -+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU -+ Lesser General Public License for more details. -+ -+ You should have received a copy of the GNU Lesser General Public -+ License along with the GNU C Library; if not, write to the Free -+ Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA -+ 02111-1307 USA. */ -+ -+#define GETSP() ({ register uintptr_t stack_ptr asm ("sp"); stack_ptr; }) -+ -+#include -diff --git a/glibc-2.14.1/sysdeps/riscv/nptl/Makefile b/glibc-2.14.1/sysdeps/riscv/nptl/Makefile -new file mode 100644 -index 0000000..d0c59a5 ---- /dev/null -+++ glibc-2.14.1/sysdeps/riscv/nptl/Makefile -@@ -0,0 +1,25 @@ -+# Copyright (C) 2005 Free Software Foundation, Inc. -+# This file is part of the GNU C Library. -+# -+# The GNU C Library is free software; you can redistribute it and/or -+# modify it under the terms of the GNU Lesser General Public -+# License as published by the Free Software Foundation; either -+# version 2.1 of the License, or (at your option) any later version. -+# -+# The GNU C Library is distributed in the hope that it will be useful, -+# but WITHOUT ANY WARRANTY; without even the implied warranty of -+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU -+# Lesser General Public License for more details. -+# -+# You should have received a copy of the GNU Lesser General Public -+# License along with the GNU C Library; if not, write to the Free -+# Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA -+# 02111-1307 USA. -+ -+ifeq ($(subdir),csu) -+gen-as-const-headers += tcb-offsets.sym -+endif -+ -+ifeq ($(subdir),nptl) -+libpthread-sysdep_routines += nptl-sysdep -+endif -diff --git a/glibc-2.14.1/sysdeps/riscv/nptl/nptl-sysdep.c b/glibc-2.14.1/sysdeps/riscv/nptl/nptl-sysdep.c -new file mode 100644 -index 0000000..16c1736 ---- /dev/null -+++ glibc-2.14.1/sysdeps/riscv/nptl/nptl-sysdep.c -@@ -0,0 +1,2 @@ -+/* Pull in __syscall_error. */ -+#include -diff --git a/glibc-2.14.1/sysdeps/riscv/nptl/pthread_spin_destroy.c b/glibc-2.14.1/sysdeps/riscv/nptl/pthread_spin_destroy.c -new file mode 100644 -index 0000000..e1eed80 ---- /dev/null -+++ glibc-2.14.1/sysdeps/riscv/nptl/pthread_spin_destroy.c -@@ -0,0 +1,30 @@ -+/* Copyright (C) 2002 Free Software Foundation, Inc. -+ This file is part of the GNU C Library. -+ Contributed by Ulrich Drepper , 2002. -+ -+ The GNU C Library is free software; you can redistribute it and/or -+ modify it under the terms of the GNU Lesser General Public -+ License as published by the Free Software Foundation; either -+ version 2.1 of the License, or (at your option) any later version. -+ -+ The GNU C Library is distributed in the hope that it will be useful, -+ but WITHOUT ANY WARRANTY; without even the implied warranty of -+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU -+ Lesser General Public License for more details. -+ -+ You should have received a copy of the GNU Lesser General Public -+ License along with the GNU C Library; if not, write to the Free -+ Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA -+ 02111-1307 USA. */ -+ -+#include "pthreadP.h" -+ -+ -+#ifndef __riscv_atomic -+int -+pthread_spin_destroy (lock) -+ pthread_spinlock_t *lock; -+{ -+ return pthread_mutex_destroy(lock); -+} -+#endif -diff --git a/glibc-2.14.1/sysdeps/riscv/nptl/pthread_spin_init.c b/glibc-2.14.1/sysdeps/riscv/nptl/pthread_spin_init.c -new file mode 100644 -index 0000000..b85181a ---- /dev/null -+++ glibc-2.14.1/sysdeps/riscv/nptl/pthread_spin_init.c -@@ -0,0 +1,30 @@ -+/* pthread_spin_init -- initialize a spin lock. Generic version. -+ Copyright (C) 2003 Free Software Foundation, Inc. -+ This file is part of the GNU C Library. -+ Contributed by Paul Mackerras , 2003. -+ -+ The GNU C Library is free software; you can redistribute it and/or -+ modify it under the terms of the GNU Lesser General Public -+ License as published by the Free Software Foundation; either -+ version 2.1 of the License, or (at your option) any later version. -+ -+ The GNU C Library is distributed in the hope that it will be useful, -+ but WITHOUT ANY WARRANTY; without even the implied warranty of -+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU -+ Lesser General Public License for more details. -+ -+ You should have received a copy of the GNU Lesser General Public -+ License along with the GNU C Library; if not, write to the Free -+ Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA -+ 02111-1307 USA. */ -+ -+#include "pthreadP.h" -+ -+ -+#ifndef __riscv_atomic -+int -+pthread_spin_init (pthread_spinlock_t *lock, int pshared) -+{ -+ return pthread_mutex_init(lock, NULL); -+} -+#endif -diff --git a/glibc-2.14.1/sysdeps/riscv/nptl/pthread_spin_lock.c b/glibc-2.14.1/sysdeps/riscv/nptl/pthread_spin_lock.c -new file mode 100644 -index 0000000..0e8840b ---- /dev/null -+++ glibc-2.14.1/sysdeps/riscv/nptl/pthread_spin_lock.c -@@ -0,0 +1,39 @@ -+/* Copyright (C) 2005 Free Software Foundation, Inc. -+ This file is part of the GNU C Library. -+ -+ The GNU C Library is free software; you can redistribute it and/or -+ modify it under the terms of the GNU Lesser General Public -+ License as published by the Free Software Foundation; either -+ version 2.1 of the License, or (at your option) any later version. -+ -+ The GNU C Library is distributed in the hope that it will be useful, -+ but WITHOUT ANY WARRANTY; without even the implied warranty of -+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU -+ Lesser General Public License for more details. -+ -+ You should have received a copy of the GNU Lesser General Public -+ License along with the GNU C Library; if not, write to the Free -+ Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA -+ 02111-1307 USA. */ -+ -+#include -+ -+int pthread_spin_lock(pthread_spinlock_t* lock) -+{ -+#ifdef __riscv_atomic -+ int tmp1, tmp2; -+ -+ asm volatile ("\n\ -+ 1:lw %0, 0(%2)\n\ -+ li %1, %3\n\ -+ bnez %0, 1b\n\ -+ amoswap.w.aq %0, %1, 0(%2)\n\ -+ bnez %0, 1b" -+ : "=&r"(tmp1), "=&r"(tmp2) : "r"(lock), "i"(EBUSY) -+ ); -+ -+ return tmp1; -+#else -+ return pthread_mutex_lock(lock); -+#endif -+} -diff --git a/glibc-2.14.1/sysdeps/riscv/nptl/pthread_spin_trylock.c b/glibc-2.14.1/sysdeps/riscv/nptl/pthread_spin_trylock.c -new file mode 100644 -index 0000000..b19ec5e ---- /dev/null -+++ glibc-2.14.1/sysdeps/riscv/nptl/pthread_spin_trylock.c -@@ -0,0 +1,39 @@ -+/* Copyright (C) 2005 Free Software Foundation, Inc. -+ This file is part of the GNU C Library. -+ -+ The GNU C Library is free software; you can redistribute it and/or -+ modify it under the terms of the GNU Lesser General Public -+ License as published by the Free Software Foundation; either -+ version 2.1 of the License, or (at your option) any later version. -+ -+ The GNU C Library is distributed in the hope that it will be useful, -+ but WITHOUT ANY WARRANTY; without even the implied warranty of -+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU -+ Lesser General Public License for more details. -+ -+ You should have received a copy of the GNU Lesser General Public -+ License along with the GNU C Library; if not, write to the Free -+ Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA -+ 02111-1307 USA. */ -+ -+#include -+ -+int pthread_spin_trylock(pthread_spinlock_t* lock) -+{ -+#ifdef __riscv_atomic -+ int tmp1, tmp2; -+ -+ asm volatile ("\n\ -+ lw %0, 0(%2)\n\ -+ li %1, %3\n\ -+ bnez %0, 1f\n\ -+ amoswap.w.aq %0, %1, 0(%2)\n\ -+ 1:" -+ : "=&r"(tmp1), "=&r"(tmp2) : "r"(lock), "i"(EBUSY) -+ ); -+ -+ return tmp1; -+#else -+ return pthread_mutex_trylock(lock); -+#endif -+} -diff --git a/glibc-2.14.1/sysdeps/riscv/nptl/pthread_spin_unlock.c b/glibc-2.14.1/sysdeps/riscv/nptl/pthread_spin_unlock.c -new file mode 100644 -index 0000000..133311c ---- /dev/null -+++ glibc-2.14.1/sysdeps/riscv/nptl/pthread_spin_unlock.c -@@ -0,0 +1,33 @@ -+/* pthread_spin_unlock -- unlock a spin lock. Generic version. -+ Copyright (C) 2003 Free Software Foundation, Inc. -+ This file is part of the GNU C Library. -+ Contributed by Paul Mackerras , 2003. -+ -+ The GNU C Library is free software; you can redistribute it and/or -+ modify it under the terms of the GNU Lesser General Public -+ License as published by the Free Software Foundation; either -+ version 2.1 of the License, or (at your option) any later version. -+ -+ The GNU C Library is distributed in the hope that it will be useful, -+ but WITHOUT ANY WARRANTY; without even the implied warranty of -+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU -+ Lesser General Public License for more details. -+ -+ You should have received a copy of the GNU Lesser General Public -+ License along with the GNU C Library; if not, write to the Free -+ Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA -+ 02111-1307 USA. */ -+ -+#include "pthreadP.h" -+#include -+ -+int -+pthread_spin_unlock (pthread_spinlock_t *lock) -+{ -+#ifdef __riscv_atomic -+ asm volatile ("amoswap.w.rl x0, x0, 0(%0)" : : "r"(lock)); -+ return 0; -+#else -+ return pthread_mutex_unlock(lock); -+#endif -+} -diff --git a/glibc-2.14.1/sysdeps/riscv/nptl/pthreaddef.h b/glibc-2.14.1/sysdeps/riscv/nptl/pthreaddef.h -new file mode 100644 -index 0000000..e72b4bc ---- /dev/null -+++ glibc-2.14.1/sysdeps/riscv/nptl/pthreaddef.h -@@ -0,0 +1,39 @@ -+/* Copyright (C) 2002, 2003, 2005 Free Software Foundation, Inc. -+ This file is part of the GNU C Library. -+ -+ The GNU C Library is free software; you can redistribute it and/or -+ modify it under the terms of the GNU Lesser General Public -+ License as published by the Free Software Foundation; either -+ version 2.1 of the License, or (at your option) any later version. -+ -+ The GNU C Library is distributed in the hope that it will be useful, -+ but WITHOUT ANY WARRANTY; without even the implied warranty of -+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU -+ Lesser General Public License for more details. -+ -+ You should have received a copy of the GNU Lesser General Public -+ License along with the GNU C Library; if not, write to the Free -+ Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA -+ 02111-1307 USA. */ -+ -+/* Default stack size. */ -+#define ARCH_STACK_DEFAULT_SIZE (2 * 1024 * 1024) -+ -+/* Required stack pointer alignment at beginning. */ -+#define STACK_ALIGN 16 -+ -+/* Minimal stack size after allocating thread descriptor and guard size. */ -+#define MINIMAL_REST_STACK 2048 -+ -+/* Alignment requirement for TCB. */ -+#define TCB_ALIGNMENT 16 -+ -+ -+/* Location of current stack frame. */ -+#define CURRENT_STACK_FRAME __builtin_frame_address (0) -+ -+ -+/* XXX Until we have a better place keep the definitions here. */ -+ -+#define __exit_thread_inline(val) \ -+ INLINE_SYSCALL (exit, 1, (val)) -diff --git a/glibc-2.14.1/sysdeps/riscv/nptl/tcb-offsets.sym b/glibc-2.14.1/sysdeps/riscv/nptl/tcb-offsets.sym -new file mode 100644 -index 0000000..e0e71dc ---- /dev/null -+++ glibc-2.14.1/sysdeps/riscv/nptl/tcb-offsets.sym -@@ -0,0 +1,11 @@ -+#include -+#include -+ -+-- -+ -+-- Abuse tls.h macros to derive offsets relative to the thread register. -+#define thread_offsetof(mem) (long)(offsetof(struct pthread, mem) - TLS_TCB_OFFSET - TLS_PRE_TCB_SIZE) -+ -+MULTIPLE_THREADS_OFFSET thread_offsetof (header.multiple_threads) -+PID_OFFSET thread_offsetof (pid) -+TID_OFFSET thread_offsetof (tid) -diff --git a/glibc-2.14.1/sysdeps/riscv/nptl/tls.h b/glibc-2.14.1/sysdeps/riscv/nptl/tls.h -new file mode 100644 -index 0000000..5297ff8 ---- /dev/null -+++ glibc-2.14.1/sysdeps/riscv/nptl/tls.h -@@ -0,0 +1,164 @@ -+/* Definition for thread-local data handling. NPTL/MIPS version. -+ Copyright (C) 2005, 2007 Free Software Foundation, Inc. -+ This file is part of the GNU C Library. -+ -+ The GNU C Library is free software; you can redistribute it and/or -+ modify it under the terms of the GNU Lesser General Public -+ License as published by the Free Software Foundation; either -+ version 2.1 of the License, or (at your option) any later version. -+ -+ The GNU C Library is distributed in the hope that it will be useful, -+ but WITHOUT ANY WARRANTY; without even the implied warranty of -+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU -+ Lesser General Public License for more details. -+ -+ You should have received a copy of the GNU Lesser General Public -+ License along with the GNU C Library; if not, write to the Free -+ Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA -+ 02111-1307 USA. */ -+ -+#ifndef _TLS_H -+#define _TLS_H 1 -+ -+#include -+ -+#ifndef __ASSEMBLER__ -+# include -+# include -+# include -+ -+/* Type for the dtv. */ -+typedef union dtv -+{ -+ size_t counter; -+ struct -+ { -+ void *val; -+ bool is_static; -+ } pointer; -+} dtv_t; -+ -+register void* __thread_self asm("tp"); -+# define READ_THREAD_POINTER() ({ __thread_self; }) -+ -+#endif /* __ASSEMBLER__ */ -+ -+ -+/* We require TLS support in the tools. */ -+#ifndef HAVE_TLS_SUPPORT -+# error "TLS support is required." -+#endif -+ -+/* Signal that TLS support is available. */ -+#define USE_TLS 1 -+ -+#ifndef __ASSEMBLER__ -+ -+/* Get system call information. */ -+# include -+ -+/* The TP points to the start of the thread blocks. */ -+# define TLS_DTV_AT_TP 1 -+ -+/* Get the thread descriptor definition. */ -+# include -+ -+typedef struct -+{ -+ dtv_t *dtv; -+ void *private; -+} tcbhead_t; -+ -+/* This is the size of the initial TCB. Because our TCB is before the thread -+ pointer, we don't need this. */ -+# define TLS_INIT_TCB_SIZE 0 -+ -+/* Alignment requirements for the initial TCB. */ -+# define TLS_INIT_TCB_ALIGN __alignof__ (struct pthread) -+ -+/* This is the size of the TCB. Because our TCB is before the thread -+ pointer, we don't need this. */ -+# define TLS_TCB_SIZE 0 -+ -+/* Alignment requirements for the TCB. */ -+# define TLS_TCB_ALIGN __alignof__ (struct pthread) -+ -+/* This is the size we need before TCB - actually, it includes the TCB. */ -+# define TLS_PRE_TCB_SIZE \ -+ (sizeof (struct pthread) \ -+ + ((sizeof (tcbhead_t) + TLS_TCB_ALIGN - 1) & ~(TLS_TCB_ALIGN - 1))) -+ -+/* The thread pointer tp points to the end of the TCB. -+ The pthread_descr structure is immediately in front of the TCB. */ -+# define TLS_TCB_OFFSET 0 -+ -+/* Install the dtv pointer. The pointer passed is to the element with -+ index -1 which contain the length. */ -+# define INSTALL_DTV(tcbp, dtvp) \ -+ (((tcbhead_t *) (tcbp))[-1].dtv = (dtvp) + 1) -+ -+/* Install new dtv for current thread. */ -+# define INSTALL_NEW_DTV(dtv) \ -+ (THREAD_DTV() = (dtv)) -+ -+/* Return dtv of given thread descriptor. */ -+# define GET_DTV(tcbp) \ -+ (((tcbhead_t *) (tcbp))[-1].dtv) -+ -+/* Code to initially initialize the thread pointer. */ -+# define TLS_INIT_TP(tcbp, secondcall) \ -+ ({ __thread_self = (char*)tcbp + TLS_TCB_OFFSET; NULL; }) -+ -+/* Return the address of the dtv for the current thread. */ -+# define THREAD_DTV() \ -+ (((tcbhead_t *) (READ_THREAD_POINTER () - TLS_TCB_OFFSET))[-1].dtv) -+ -+/* Return the thread descriptor for the current thread. */ -+# define THREAD_SELF \ -+ ((struct pthread *) (READ_THREAD_POINTER () \ -+ - TLS_TCB_OFFSET - TLS_PRE_TCB_SIZE)) -+ -+/* Magic for libthread_db to know how to do THREAD_SELF. */ -+# define DB_THREAD_SELF \ -+ CONST_THREAD_AREA (32, TLS_TCB_OFFSET + TLS_PRE_TCB_SIZE) -+ -+/* Access to data in the thread descriptor is easy. */ -+# define THREAD_GETMEM(descr, member) \ -+ descr->member -+# define THREAD_GETMEM_NC(descr, member, idx) \ -+ descr->member[idx] -+# define THREAD_SETMEM(descr, member, value) \ -+ descr->member = (value) -+# define THREAD_SETMEM_NC(descr, member, idx, value) \ -+ descr->member[idx] = (value) -+ -+/* l_tls_offset == 0 is perfectly valid on MIPS, so we have to use some -+ different value to mean unset l_tls_offset. */ -+# define NO_TLS_OFFSET -1 -+ -+/* Get and set the global scope generation counter in struct pthread. */ -+#define THREAD_GSCOPE_FLAG_UNUSED 0 -+#define THREAD_GSCOPE_FLAG_USED 1 -+#define THREAD_GSCOPE_FLAG_WAIT 2 -+#define THREAD_GSCOPE_RESET_FLAG() \ -+ do \ -+ { int __res \ -+ = atomic_exchange_rel (&THREAD_SELF->header.gscope_flag, \ -+ THREAD_GSCOPE_FLAG_UNUSED); \ -+ if (__res == THREAD_GSCOPE_FLAG_WAIT) \ -+ lll_futex_wake (&THREAD_SELF->header.gscope_flag, 1, LLL_PRIVATE); \ -+ } \ -+ while (0) -+#define THREAD_GSCOPE_SET_FLAG() \ -+ do \ -+ { \ -+ THREAD_SELF->header.gscope_flag = THREAD_GSCOPE_FLAG_USED; \ -+ atomic_write_barrier (); \ -+ } \ -+ while (0) -+#define THREAD_GSCOPE_WAIT() \ -+ GL(dl_wait_lookup_done) () -+ -+#endif /* __ASSEMBLER__ */ -+ -+#endif /* tls.h */ -diff --git a/glibc-2.14.1/sysdeps/riscv/preconfigure b/glibc-2.14.1/sysdeps/riscv/preconfigure -new file mode 100644 -index 0000000..c3792e1 ---- /dev/null -+++ glibc-2.14.1/sysdeps/riscv/preconfigure -@@ -0,0 +1,21 @@ -+ccccase "$CC $CFLAGS $CPPFLAGS " in -+*" -m32 "*) mips_cc_abi=32 ;; -+*" -m64 "*) mips_cc_abi=64 ;; -+*) mips_cc_abi=default ;; -+esac -+case $config_os in -+*abi64*) mips_config_abi=64 ;; -+*abi32*) mips_config_abi=32 ;; -+*) mips_config_abi=$mips_cc_abi ;; -+esac -+case $mips_config_abi in -+default) machine=riscv/rv64 ;; -+32) machine=riscv/rv32 ;; -+esac -+machine=$machine/$config_machine -+if test $mips_config_abi != $mips_cc_abi; then -+ # This won't make it to config.make, but we want to -+ # set this in case configure tests depend on it. -+ CPPFLAGS="$CPPFLAGS -m$mips_config_abi" -+fi -+;; -diff --git a/glibc-2.14.1/sysdeps/riscv/rv32/Implies b/glibc-2.14.1/sysdeps/riscv/rv32/Implies -new file mode 100644 -index 0000000..b2313e9 ---- /dev/null -+++ glibc-2.14.1/sysdeps/riscv/rv32/Implies -@@ -0,0 +1,2 @@ -+riscv -+wordsize-32 -diff --git a/glibc-2.14.1/sysdeps/riscv/rv32/Makefile b/glibc-2.14.1/sysdeps/riscv/rv32/Makefile -new file mode 100644 -index 0000000..f9c69e3 ---- /dev/null -+++ glibc-2.14.1/sysdeps/riscv/rv32/Makefile -@@ -0,0 +1,3 @@ -+ifeq ($(filter -m32,$(CC)),) -+CC += -m32 -+endif -diff --git a/glibc-2.14.1/sysdeps/riscv/rv64/Implies b/glibc-2.14.1/sysdeps/riscv/rv64/Implies -new file mode 100644 -index 0000000..fae63bc ---- /dev/null -+++ glibc-2.14.1/sysdeps/riscv/rv64/Implies -@@ -0,0 +1,6 @@ -+ieee754/flt-32 -+ieee754/dbl-64 -+riscv/rv64/soft-fp -+riscv/rv64 -+riscv -+wordsize-64 -diff --git a/glibc-2.14.1/sysdeps/riscv/rv64/Makefile b/glibc-2.14.1/sysdeps/riscv/rv64/Makefile -new file mode 100644 -index 0000000..26b6a49 ---- /dev/null -+++ glibc-2.14.1/sysdeps/riscv/rv64/Makefile -@@ -0,0 +1,6 @@ -+# Link libc.so at its likely load address for faster dynamic linking -+LDLIBS-c.so += -Wl,--section-start=.dynamic=0x40100270 -+ -+ifeq ($(filter -m64,$(CC)),) -+CC += -m64 -+endif -diff --git a/glibc-2.14.1/sysdeps/riscv/rv64/Versions b/glibc-2.14.1/sysdeps/riscv/rv64/Versions -new file mode 100644 -index 0000000..253a65f ---- /dev/null -+++ glibc-2.14.1/sysdeps/riscv/rv64/Versions -@@ -0,0 +1,7 @@ -+libm { -+ GLIBC_2.1 { -+ # A generic bug got this omitted from other configurations' version -+ # sets, but we always had it. -+ exp2l; -+ } -+} -diff --git a/glibc-2.14.1/sysdeps/riscv/rv64/gmp-mparam.h b/glibc-2.14.1/sysdeps/riscv/rv64/gmp-mparam.h -new file mode 100644 -index 0000000..7666137 ---- /dev/null -+++ glibc-2.14.1/sysdeps/riscv/rv64/gmp-mparam.h -@@ -0,0 +1,31 @@ -+/* gmp-mparam.h -- Compiler/machine parameter header file. -+ -+Copyright (C) 1991, 1993, 1994, 2002, 2003 Free Software Foundation, Inc. -+ -+This file is part of the GNU MP Library. -+ -+The GNU MP Library is free software; you can redistribute it and/or modify -+it under the terms of the GNU Lesser General Public License as published by -+the Free Software Foundation; either version 2.1 of the License, or (at your -+option) any later version. -+ -+The GNU MP Library is distributed in the hope that it will be useful, but -+WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY -+or FITNESS FOR A PARTICULAR PURPOSE. See the GNU Lesser General Public -+License for more details. -+ -+You should have received a copy of the GNU Lesser General Public License -+along with the GNU MP Library; see the file COPYING.LIB. If not, write to -+the Free Software Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. */ -+ -+#if defined __GMP_H__ && ! defined _LONG_LONG_LIMB -+#error "Included too late for _LONG_LONG_LIMB to take effect" -+#endif -+ -+#define _LONG_LONG_LIMB -+#define BITS_PER_MP_LIMB 64 -+#define BYTES_PER_MP_LIMB 8 -+#define BITS_PER_LONGINT __WORDSIZE -+#define BITS_PER_INT 32 -+#define BITS_PER_SHORTINT 16 -+#define BITS_PER_CHAR 8 -diff --git a/glibc-2.14.1/sysdeps/riscv/rv64/libm-test-ulps b/glibc-2.14.1/sysdeps/riscv/rv64/libm-test-ulps -new file mode 100644 -index 0000000..d9df631 ---- /dev/null -+++ glibc-2.14.1/sysdeps/riscv/rv64/libm-test-ulps -@@ -0,0 +1,1245 @@ -+# Begin of automatic generation -+ -+# atan2 -+Test "atan2 (-0.00756827042671106339, -.001792735857538728036) == -1.80338464113663849327153994379639112": -+ildouble: 1 -+ldouble: 1 -+Test "atan2 (-0.75, -1.0) == -2.49809154479650885165983415456218025": -+float: 1 -+ifloat: 1 -+ildouble: 1 -+ldouble: 1 -+Test "atan2 (0.75, -1.0) == 2.49809154479650885165983415456218025": -+float: 1 -+ifloat: 1 -+ildouble: 1 -+ldouble: 1 -+Test "atan2 (1.390625, 0.9296875) == 0.981498387184244311516296577615519772": -+float: 1 -+ifloat: 1 -+ildouble: 1 -+ldouble: 1 -+ -+# atanh -+Test "atanh (0.75) == 0.972955074527656652552676371721589865": -+float: 1 -+ifloat: 1 -+ -+# cacos -+Test "Imaginary part of: cacos (0.75 + 1.25 i) == 1.11752014915610270578240049553777969 - 1.13239363160530819522266333696834467 i": -+ildouble: 1 -+ldouble: 1 -+ -+# cacosh -+Test "Imaginary part of: cacosh (-2 - 3 i) == 1.9833870299165354323470769028940395 - 2.1414491111159960199416055713254211 i": -+float: 1 -+ifloat: 1 -+ildouble: 1 -+ldouble: 1 -+ -+# casin -+Test "Real part of: casin (0.75 + 1.25 i) == 0.453276177638793913448921196101971749 + 1.13239363160530819522266333696834467 i": -+double: 1 -+float: 1 -+idouble: 1 -+ifloat: 1 -+Test "Imaginary part of: casin (0.75 + 1.25 i) == 0.453276177638793913448921196101971749 + 1.13239363160530819522266333696834467 i": -+ildouble: 1 -+ldouble: 1 -+ -+# casinh -+Test "Real part of: casinh (-2 - 3 i) == -1.9686379257930962917886650952454982 - 0.96465850440760279204541105949953237 i": -+double: 5 -+float: 1 -+idouble: 5 -+ifloat: 1 -+ildouble: 4 -+ldouble: 4 -+Test "Imaginary part of: casinh (-2 - 3 i) == -1.9686379257930962917886650952454982 - 0.96465850440760279204541105949953237 i": -+double: 3 -+float: 6 -+idouble: 3 -+ifloat: 6 -+ildouble: 2 -+ldouble: 2 -+Test "Real part of: casinh (0.75 + 1.25 i) == 1.03171853444778027336364058631006594 + 0.911738290968487636358489564316731207 i": -+float: 1 -+ifloat: 1 -+ildouble: 1 -+ldouble: 1 -+Test "Imaginary part of: casinh (0.75 + 1.25 i) == 1.03171853444778027336364058631006594 + 0.911738290968487636358489564316731207 i": -+double: 1 -+float: 1 -+idouble: 1 -+ifloat: 1 -+ildouble: 1 -+ldouble: 1 -+ -+# catan -+Test "Imaginary part of: catan (-2 - 3 i) == -1.4099210495965755225306193844604208 - 0.22907268296853876629588180294200276 i": -+double: 1 -+float: 1 -+idouble: 1 -+ifloat: 1 -+Test "Imaginary part of: catan (0.75 + 1.25 i) == 1.10714871779409050301706546017853704 + 0.549306144334054845697622618461262852 i": -+ildouble: 1 -+ldouble: 1 -+ -+# catanh -+Test "Real part of: catanh (-2 - 3 i) == -0.14694666622552975204743278515471595 - 1.3389725222944935611241935759091443 i": -+double: 4 -+idouble: 4 -+Test "Real part of: catanh (0.75 + 1.25 i) == 0.261492138795671927078652057366532140 + 0.996825126463918666098902241310446708 i": -+double: 1 -+idouble: 1 -+ildouble: 1 -+ldouble: 1 -+Test "Imaginary part of: catanh (0.75 + 1.25 i) == 0.261492138795671927078652057366532140 + 0.996825126463918666098902241310446708 i": -+ildouble: 1 -+ldouble: 1 -+ -+# cbrt -+Test "cbrt (-0.001) == -0.1": -+ildouble: 1 -+ldouble: 1 -+Test "cbrt (-27.0) == -3.0": -+double: 1 -+idouble: 1 -+Test "cbrt (0.75) == 0.908560296416069829445605878163630251": -+double: 1 -+idouble: 1 -+Test "cbrt (0.9921875) == 0.997389022060725270579075195353955217": -+double: 1 -+idouble: 1 -+ -+# ccos -+Test "Real part of: ccos (-2 - 3 i) == -4.18962569096880723013255501961597373 - 9.10922789375533659797919726277886212 i": -+ildouble: 1 -+ldouble: 1 -+Test "Imaginary part of: ccos (-2 - 3 i) == -4.18962569096880723013255501961597373 - 9.10922789375533659797919726277886212 i": -+float: 1 -+ifloat: 1 -+ildouble: 1 -+ldouble: 1 -+Test "Real part of: ccos (0.75 + 1.25 i) == 1.38173873063425888530729933139078645 - 1.09193013555397466170919531722024128 i": -+double: 1 -+float: 1 -+idouble: 1 -+ifloat: 1 -+Test "Imaginary part of: ccos (0.75 + 1.25 i) == 1.38173873063425888530729933139078645 - 1.09193013555397466170919531722024128 i": -+float: 1 -+ifloat: 1 -+ -+# ccosh -+Test "Real part of: ccosh (-2 - 3 i) == -3.72454550491532256547397070325597253 + 0.511822569987384608834463849801875634 i": -+float: 1 -+ifloat: 1 -+ildouble: 1 -+ldouble: 1 -+Test "Imaginary part of: ccosh (-2 - 3 i) == -3.72454550491532256547397070325597253 + 0.511822569987384608834463849801875634 i": -+float: 1 -+ifloat: 1 -+ildouble: 1 -+ldouble: 1 -+Test "Real part of: ccosh (0.75 + 1.25 i) == 0.408242591877968807788852146397499084 + 0.780365930845853240391326216300863152 i": -+double: 1 -+float: 1 -+idouble: 1 -+ifloat: 1 -+Test "Imaginary part of: ccosh (0.75 + 1.25 i) == 0.408242591877968807788852146397499084 + 0.780365930845853240391326216300863152 i": -+float: 1 -+ifloat: 1 -+ -+# cexp -+Test "Real part of: cexp (-2.0 - 3.0 i) == -0.13398091492954261346140525546115575 - 0.019098516261135196432576240858800925 i": -+ildouble: 1 -+ldouble: 1 -+Test "Imaginary part of: cexp (-2.0 - 3.0 i) == -0.13398091492954261346140525546115575 - 0.019098516261135196432576240858800925 i": -+float: 1 -+ifloat: 1 -+ildouble: 1 -+ldouble: 1 -+Test "Real part of: cexp (0.75 + 1.25 i) == 0.667537446429131586942201977015932112 + 2.00900045494094876258347228145863909 i": -+float: 1 -+ifloat: 1 -+Test "Imaginary part of: cexp (0.75 + 1.25 i) == 0.667537446429131586942201977015932112 + 2.00900045494094876258347228145863909 i": -+ildouble: 1 -+ldouble: 1 -+ -+# clog -+Test "Real part of: clog (0.75 + 1.25 i) == 0.376885901188190075998919126749298416 + 1.03037682652431246378774332703115153 i": -+float: 1 -+ifloat: 1 -+ildouble: 1 -+ldouble: 1 -+ -+# clog10 -+Test "Imaginary part of: clog10 (-0 + inf i) == inf + pi/2*log10(e) i": -+double: 1 -+float: 1 -+idouble: 1 -+ifloat: 1 -+Test "Imaginary part of: clog10 (-0 - inf i) == inf - pi/2*log10(e) i": -+double: 1 -+float: 1 -+idouble: 1 -+ifloat: 1 -+Test "Real part of: clog10 (-2 - 3 i) == 0.556971676153418384603252578971164214 - 0.937554462986374708541507952140189646 i": -+ildouble: 1 -+ldouble: 1 -+Test "Imaginary part of: clog10 (-2 - 3 i) == 0.556971676153418384603252578971164214 - 0.937554462986374708541507952140189646 i": -+double: 1 -+idouble: 1 -+ildouble: 1 -+ldouble: 1 -+Test "Imaginary part of: clog10 (-3 + inf i) == inf + pi/2*log10(e) i": -+double: 1 -+float: 1 -+idouble: 1 -+ifloat: 1 -+Test "Imaginary part of: clog10 (-3 - inf i) == inf - pi/2*log10(e) i": -+double: 1 -+float: 1 -+idouble: 1 -+ifloat: 1 -+Test "Imaginary part of: clog10 (-inf + 0 i) == inf + pi*log10(e) i": -+double: 1 -+float: 1 -+idouble: 1 -+ifloat: 1 -+Test "Imaginary part of: clog10 (-inf + 1 i) == inf + pi*log10(e) i": -+double: 1 -+float: 1 -+idouble: 1 -+ifloat: 1 -+Test "Imaginary part of: clog10 (-inf + inf i) == inf + 3/4 pi*log10(e) i": -+double: 1 -+idouble: 1 -+Test "Imaginary part of: clog10 (-inf - 0 i) == inf - pi*log10(e) i": -+double: 1 -+float: 1 -+idouble: 1 -+ifloat: 1 -+Test "Imaginary part of: clog10 (-inf - 1 i) == inf - pi*log10(e) i": -+double: 1 -+float: 1 -+idouble: 1 -+ifloat: 1 -+Test "Imaginary part of: clog10 (0 + inf i) == inf + pi/2*log10(e) i": -+double: 1 -+float: 1 -+idouble: 1 -+ifloat: 1 -+Test "Imaginary part of: clog10 (0 - inf i) == inf - pi/2*log10(e) i": -+double: 1 -+float: 1 -+idouble: 1 -+ifloat: 1 -+Test "Real part of: clog10 (0.75 + 1.25 i) == 0.163679467193165171449476605077428975 + 0.447486970040493067069984724340855636 i": -+float: 1 -+ifloat: 1 -+Test "Imaginary part of: clog10 (0.75 + 1.25 i) == 0.163679467193165171449476605077428975 + 0.447486970040493067069984724340855636 i": -+ildouble: 1 -+ldouble: 1 -+Test "Imaginary part of: clog10 (3 + inf i) == inf + pi/2*log10(e) i": -+double: 1 -+float: 1 -+idouble: 1 -+ifloat: 1 -+Test "Imaginary part of: clog10 (3 - inf i) == inf - pi/2*log10(e) i": -+double: 1 -+float: 1 -+idouble: 1 -+ifloat: 1 -+Test "Imaginary part of: clog10 (inf + inf i) == inf + pi/4*log10(e) i": -+double: 1 -+float: 1 -+idouble: 1 -+ifloat: 1 -+Test "Imaginary part of: clog10 (inf - inf i) == inf - pi/4*log10(e) i": -+double: 1 -+float: 1 -+idouble: 1 -+ifloat: 1 -+ -+# cos -+Test "cos (M_PI_6l * 2.0) == 0.5": -+double: 1 -+idouble: 1 -+ildouble: 1 -+ldouble: 1 -+Test "cos (M_PI_6l * 4.0) == -0.5": -+double: 2 -+float: 1 -+idouble: 2 -+ifloat: 1 -+ildouble: 1 -+ldouble: 1 -+ -+# cpow -+Test "Real part of: cpow (0.75 + 1.25 i, 0.0 + 1.0 i) == 0.331825439177608832276067945276730566 + 0.131338600281188544930936345230903032 i": -+float: 1 -+ifloat: 1 -+Test "Imaginary part of: cpow (0.75 + 1.25 i, 0.0 + 1.0 i) == 0.331825439177608832276067945276730566 + 0.131338600281188544930936345230903032 i": -+float: 1 -+ifloat: 1 -+Test "Real part of: cpow (0.75 + 1.25 i, 0.75 + 1.25 i) == 0.117506293914473555420279832210420483 + 0.346552747708338676483025352060418001 i": -+double: 1 -+float: 4 -+idouble: 1 -+ifloat: 4 -+ildouble: 4 -+ldouble: 4 -+Test "Real part of: cpow (0.75 + 1.25 i, 1.0 + 0.0 i) == 0.75 + 1.25 i": -+ildouble: 2 -+ldouble: 2 -+Test "Imaginary part of: cpow (0.75 + 1.25 i, 1.0 + 0.0 i) == 0.75 + 1.25 i": -+ildouble: 1 -+ldouble: 1 -+Test "Real part of: cpow (0.75 + 1.25 i, 1.0 + 1.0 i) == 0.0846958290317209430433805274189191353 + 0.513285749182902449043287190519090481 i": -+double: 2 -+float: 3 -+idouble: 2 -+ifloat: 3 -+ildouble: 10 -+ldouble: 10 -+Test "Real part of: cpow (2 + 0 i, 10 + 0 i) == 1024.0 + 0.0 i": -+ildouble: 2 -+ldouble: 2 -+Test "Real part of: cpow (2 + 3 i, 4 + 0 i) == -119.0 - 120.0 i": -+double: 1 -+float: 4 -+idouble: 1 -+ifloat: 4 -+ildouble: 3 -+ldouble: 3 -+Test "Imaginary part of: cpow (2 + 3 i, 4 + 0 i) == -119.0 - 120.0 i": -+float: 2 -+ifloat: 2 -+Test "Imaginary part of: cpow (e + 0 i, 0 + 2 * M_PIl i) == 1.0 + 0.0 i": -+double: 2 -+float: 2 -+idouble: 2 -+ifloat: 2 -+ildouble: 1 -+ldouble: 1 -+ -+# csin -+Test "Imaginary part of: csin (-2 - 3 i) == -9.15449914691142957346729954460983256 + 4.16890695996656435075481305885375484 i": -+ildouble: 1 -+ldouble: 1 -+Test "Real part of: csin (0.75 + 1.25 i) == 1.28722291002649188575873510790565441 + 1.17210635989270256101081285116138863 i": -+ildouble: 1 -+ldouble: 1 -+ -+# csinh -+Test "Real part of: csinh (-2 - 3 i) == 3.59056458998577995201256544779481679 - 0.530921086248519805267040090660676560 i": -+ildouble: 1 -+ldouble: 1 -+Test "Imaginary part of: csinh (-2 - 3 i) == 3.59056458998577995201256544779481679 - 0.530921086248519805267040090660676560 i": -+double: 1 -+idouble: 1 -+Test "Real part of: csinh (0.75 + 1.25 i) == 0.259294854551162779153349830618433028 + 1.22863452409509552219214606515777594 i": -+float: 1 -+ifloat: 1 -+Test "Imaginary part of: csinh (0.75 + 1.25 i) == 0.259294854551162779153349830618433028 + 1.22863452409509552219214606515777594 i": -+float: 1 -+ifloat: 1 -+ -+# csqrt -+Test "Real part of: csqrt (-2 + 3 i) == 0.89597747612983812471573375529004348 + 1.6741492280355400404480393008490519 i": -+float: 1 -+ifloat: 1 -+ildouble: 1 -+ldouble: 1 -+Test "Real part of: csqrt (-2 - 3 i) == 0.89597747612983812471573375529004348 - 1.6741492280355400404480393008490519 i": -+float: 1 -+ifloat: 1 -+ildouble: 1 -+ldouble: 1 -+Test "Imaginary part of: csqrt (0.75 + 1.25 i) == 1.05065169626078392338656675760808326 + 0.594868882070379067881984030639932657 i": -+ildouble: 1 -+ldouble: 1 -+ -+# ctan -+Test "Real part of: ctan (-2 - 3 i) == 0.376402564150424829275122113032269084e-2 - 1.00323862735360980144635859782192726 i": -+ildouble: 1 -+ldouble: 1 -+Test "Imaginary part of: ctan (-2 - 3 i) == 0.376402564150424829275122113032269084e-2 - 1.00323862735360980144635859782192726 i": -+ildouble: 1 -+ldouble: 1 -+Test "Imaginary part of: ctan (0.75 + 1.25 i) == 0.160807785916206426725166058173438663 + 0.975363285031235646193581759755216379 i": -+double: 1 -+idouble: 1 -+ildouble: 2 -+ldouble: 2 -+ -+# ctanh -+Test "Real part of: ctanh (-2 - 3 i) == -0.965385879022133124278480269394560686 + 0.988437503832249372031403430350121098e-2 i": -+double: 1 -+float: 2 -+idouble: 1 -+ifloat: 2 -+ildouble: 1 -+ldouble: 1 -+Test "Imaginary part of: ctanh (-2 - 3 i) == -0.965385879022133124278480269394560686 + 0.988437503832249372031403430350121098e-2 i": -+ildouble: 1 -+ldouble: 1 -+Test "Imaginary part of: ctanh (0 + pi/4 i) == 0.0 + 1.0 i": -+float: 1 -+ifloat: 1 -+Test "Real part of: ctanh (0.75 + 1.25 i) == 1.37260757053378320258048606571226857 + 0.385795952609750664177596760720790220 i": -+double: 1 -+idouble: 1 -+ -+# erf -+Test "erf (1.25) == 0.922900128256458230136523481197281140": -+double: 1 -+idouble: 1 -+ -+# erfc -+Test "erfc (2.0) == 0.00467773498104726583793074363274707139": -+double: 1 -+idouble: 1 -+Test "erfc (27.0) == 0.523704892378925568501606768284954709e-318": -+ildouble: 1 -+ldouble: 1 -+Test "erfc (4.125) == 0.542340079956506600531223408575531062e-8": -+double: 1 -+idouble: 1 -+ -+# exp10 -+Test "exp10 (-1) == 0.1": -+double: 2 -+float: 1 -+idouble: 2 -+ifloat: 1 -+Test "exp10 (0.75) == 5.62341325190349080394951039776481231": -+double: 1 -+float: 1 -+idouble: 1 -+ifloat: 1 -+Test "exp10 (3) == 1000": -+double: 6 -+float: 2 -+idouble: 6 -+ifloat: 2 -+ildouble: 1 -+ldouble: 1 -+ -+# exp2 -+Test "exp2 (10) == 1024": -+ildouble: 2 -+ldouble: 2 -+ -+# expm1 -+Test "expm1 (0.75) == 1.11700001661267466854536981983709561": -+double: 1 -+idouble: 1 -+Test "expm1 (1) == M_El - 1.0": -+double: 1 -+float: 1 -+idouble: 1 -+ifloat: 1 -+ildouble: 1 -+ldouble: 1 -+ -+# gamma -+Test "gamma (-0.5) == log(2*sqrt(pi))": -+ildouble: 1 -+ldouble: 1 -+ -+# hypot -+Test "hypot (-0.7, -12.4) == 12.419742348374220601176836866763271": -+float: 1 -+ifloat: 1 -+Test "hypot (-0.7, 12.4) == 12.419742348374220601176836866763271": -+float: 1 -+ifloat: 1 -+Test "hypot (-12.4, -0.7) == 12.419742348374220601176836866763271": -+float: 1 -+ifloat: 1 -+Test "hypot (-12.4, 0.7) == 12.419742348374220601176836866763271": -+float: 1 -+ifloat: 1 -+Test "hypot (0.7, -12.4) == 12.419742348374220601176836866763271": -+float: 1 -+ifloat: 1 -+Test "hypot (0.7, 12.4) == 12.419742348374220601176836866763271": -+float: 1 -+ifloat: 1 -+Test "hypot (12.4, -0.7) == 12.419742348374220601176836866763271": -+float: 1 -+ifloat: 1 -+Test "hypot (12.4, 0.7) == 12.419742348374220601176836866763271": -+float: 1 -+ifloat: 1 -+ -+# j0 -+Test "j0 (-4.0) == -3.9714980986384737228659076845169804197562E-1": -+double: 1 -+float: 1 -+idouble: 1 -+ifloat: 1 -+Test "j0 (0.75) == 0.864242275166648623555731103820923211": -+float: 1 -+ifloat: 1 -+Test "j0 (10.0) == -0.245935764451348335197760862485328754": -+double: 2 -+float: 1 -+idouble: 2 -+ifloat: 1 -+ildouble: 2 -+ldouble: 2 -+Test "j0 (2.0) == 0.223890779141235668051827454649948626": -+float: 2 -+ifloat: 2 -+ildouble: 2 -+ldouble: 2 -+Test "j0 (4.0) == -3.9714980986384737228659076845169804197562E-1": -+double: 1 -+float: 1 -+idouble: 1 -+ifloat: 1 -+Test "j0 (8.0) == 0.171650807137553906090869407851972001": -+float: 1 -+ifloat: 1 -+ildouble: 1 -+ldouble: 1 -+ -+# j1 -+Test "j1 (-1.0) == -0.440050585744933515959682203718914913": -+ildouble: 1 -+ldouble: 1 -+Test "j1 (0.75) == 0.349243602174862192523281016426251335": -+ildouble: 1 -+ldouble: 1 -+Test "j1 (1.0) == 0.440050585744933515959682203718914913": -+ildouble: 1 -+ldouble: 1 -+Test "j1 (10.0) == 0.0434727461688614366697487680258592883": -+float: 2 -+ifloat: 2 -+ildouble: 2 -+ldouble: 2 -+Test "j1 (2.0) == 0.576724807756873387202448242269137087": -+double: 1 -+idouble: 1 -+Test "j1 (8.0) == 0.234636346853914624381276651590454612": -+double: 1 -+idouble: 1 -+ildouble: 4 -+ldouble: 4 -+ -+# jn -+Test "jn (0, -4.0) == -3.9714980986384737228659076845169804197562E-1": -+double: 1 -+float: 1 -+idouble: 1 -+ifloat: 1 -+Test "jn (0, 0.75) == 0.864242275166648623555731103820923211": -+float: 1 -+ifloat: 1 -+Test "jn (0, 10.0) == -0.245935764451348335197760862485328754": -+double: 2 -+float: 1 -+idouble: 2 -+ifloat: 1 -+ildouble: 2 -+ldouble: 2 -+Test "jn (0, 2.0) == 0.223890779141235668051827454649948626": -+float: 2 -+ifloat: 2 -+ildouble: 2 -+ldouble: 2 -+Test "jn (0, 4.0) == -3.9714980986384737228659076845169804197562E-1": -+double: 1 -+float: 1 -+idouble: 1 -+ifloat: 1 -+Test "jn (0, 8.0) == 0.171650807137553906090869407851972001": -+float: 1 -+ifloat: 1 -+ildouble: 1 -+ldouble: 1 -+Test "jn (1, -1.0) == -0.440050585744933515959682203718914913": -+ildouble: 1 -+ldouble: 1 -+Test "jn (1, 0.75) == 0.349243602174862192523281016426251335": -+ildouble: 1 -+ldouble: 1 -+Test "jn (1, 1.0) == 0.440050585744933515959682203718914913": -+ildouble: 1 -+ldouble: 1 -+Test "jn (1, 10.0) == 0.0434727461688614366697487680258592883": -+float: 2 -+ifloat: 2 -+ildouble: 2 -+ldouble: 2 -+Test "jn (1, 2.0) == 0.576724807756873387202448242269137087": -+double: 1 -+idouble: 1 -+Test "jn (1, 8.0) == 0.234636346853914624381276651590454612": -+double: 1 -+idouble: 1 -+ildouble: 4 -+ldouble: 4 -+Test "jn (10, -1.0) == 0.263061512368745320699785368779050294e-9": -+ildouble: 1 -+ldouble: 1 -+Test "jn (10, 0.125) == 0.250543369809369890173993791865771547e-18": -+double: 1 -+float: 1 -+idouble: 1 -+ifloat: 1 -+ildouble: 1 -+ldouble: 1 -+Test "jn (10, 0.75) == 0.149621713117596814698712483621682835e-10": -+double: 1 -+float: 1 -+idouble: 1 -+ifloat: 1 -+ildouble: 1 -+ldouble: 1 -+Test "jn (10, 1.0) == 0.263061512368745320699785368779050294e-9": -+ildouble: 1 -+ldouble: 1 -+Test "jn (10, 10.0) == 0.207486106633358857697278723518753428": -+double: 4 -+float: 3 -+idouble: 4 -+ifloat: 3 -+ildouble: 2 -+ldouble: 2 -+Test "jn (10, 2.0) == 0.251538628271673670963516093751820639e-6": -+float: 4 -+ifloat: 4 -+Test "jn (3, 0.125) == 0.406503832554912875023029337653442868e-4": -+double: 1 -+float: 1 -+idouble: 1 -+ifloat: 1 -+Test "jn (3, 0.75) == 0.848438342327410884392755236884386804e-2": -+double: 1 -+float: 1 -+idouble: 1 -+ifloat: 1 -+Test "jn (3, 10.0) == 0.0583793793051868123429354784103409563": -+double: 3 -+float: 1 -+idouble: 3 -+ifloat: 1 -+ildouble: 2 -+ldouble: 2 -+Test "jn (3, 2.0) == 0.128943249474402051098793332969239835": -+double: 1 -+float: 2 -+idouble: 1 -+ifloat: 2 -+ -+# lgamma -+Test "lgamma (-0.5) == log(2*sqrt(pi))": -+ildouble: 1 -+ldouble: 1 -+Test "lgamma (0.7) == 0.260867246531666514385732417016759578": -+double: 1 -+float: 1 -+idouble: 1 -+ifloat: 1 -+ildouble: 1 -+ldouble: 1 -+Test "lgamma (1.2) == -0.853740900033158497197028392998854470e-1": -+double: 1 -+float: 2 -+idouble: 1 -+ifloat: 2 -+ildouble: 1 -+ldouble: 1 -+ -+# log10 -+Test "log10 (0.75) == -0.124938736608299953132449886193870744": -+double: 1 -+float: 2 -+idouble: 1 -+ifloat: 2 -+Test "log10 (e) == log10(e)": -+float: 1 -+ifloat: 1 -+ildouble: 1 -+ldouble: 1 -+ -+# log1p -+Test "log1p (-0.25) == -0.287682072451780927439219005993827432": -+float: 1 -+ifloat: 1 -+ -+# log2 -+Test "log2 (0.75) == -.415037499278843818546261056052183492": -+ildouble: 1 -+ldouble: 1 -+ -+# sincos -+Test "sincos (M_PI_6l*2.0, &sin_res, &cos_res) puts 0.5 in cos_res": -+double: 1 -+idouble: 1 -+ildouble: 1 -+ldouble: 1 -+Test "sincos (M_PI_6l*2.0, &sin_res, &cos_res) puts 0.86602540378443864676372317075293616 in sin_res": -+double: 1 -+float: 1 -+idouble: 1 -+ifloat: 1 -+ildouble: 1 -+ldouble: 1 -+Test "sincos (pi/6, &sin_res, &cos_res) puts 0.86602540378443864676372317075293616 in cos_res": -+float: 1 -+ifloat: 1 -+ -+# sqrt -+Test "sqrt (2) == M_SQRT2l": -+ildouble: 1 -+ldouble: 1 -+ -+# tanh -+Test "tanh (-0.75) == -0.635148952387287319214434357312496495": -+ildouble: 1 -+ldouble: 1 -+Test "tanh (-1.0) == -0.7615941559557648881194582826047935904": -+ildouble: 1 -+ldouble: 1 -+Test "tanh (0.75) == 0.635148952387287319214434357312496495": -+ildouble: 1 -+ldouble: 1 -+Test "tanh (1.0) == 0.7615941559557648881194582826047935904": -+ildouble: 1 -+ldouble: 1 -+ -+# tgamma -+Test "tgamma (-0.5) == -2 sqrt (pi)": -+double: 1 -+float: 1 -+idouble: 1 -+ifloat: 1 -+ildouble: 1 -+ldouble: 1 -+Test "tgamma (0.5) == sqrt (pi)": -+float: 1 -+ifloat: 1 -+Test "tgamma (0.7) == 1.29805533264755778568117117915281162": -+double: 1 -+float: 1 -+idouble: 1 -+ifloat: 1 -+Test "tgamma (4) == 6": -+ildouble: 1 -+ldouble: 1 -+ -+# y0 -+Test "y0 (1.0) == 0.0882569642156769579829267660235151628": -+double: 2 -+float: 1 -+idouble: 2 -+ifloat: 1 -+Test "y0 (1.5) == 0.382448923797758843955068554978089862": -+double: 2 -+float: 1 -+idouble: 2 -+ifloat: 1 -+Test "y0 (10.0) == 0.0556711672835993914244598774101900481": -+float: 1 -+ifloat: 1 -+ildouble: 3 -+ldouble: 3 -+Test "y0 (8.0) == 0.223521489387566220527323400498620359": -+double: 1 -+float: 1 -+idouble: 1 -+ifloat: 1 -+ildouble: 3 -+ldouble: 3 -+ -+# y1 -+Test "y1 (0.125) == -5.19993611253477499595928744876579921": -+double: 1 -+idouble: 1 -+Test "y1 (0.75) == -1.03759455076928541973767132140642198": -+ildouble: 1 -+ldouble: 1 -+Test "y1 (1.5) == -0.412308626973911295952829820633445323": -+float: 1 -+ifloat: 1 -+ildouble: 1 -+ldouble: 1 -+Test "y1 (10.0) == 0.249015424206953883923283474663222803": -+double: 3 -+float: 1 -+idouble: 3 -+ifloat: 1 -+Test "y1 (2.0) == -0.107032431540937546888370772277476637": -+double: 1 -+float: 1 -+idouble: 1 -+ifloat: 1 -+ildouble: 1 -+ldouble: 1 -+Test "y1 (8.0) == -0.158060461731247494255555266187483550": -+double: 1 -+float: 2 -+idouble: 1 -+ifloat: 2 -+ildouble: 1 -+ldouble: 1 -+ -+# yn -+Test "yn (0, 1.0) == 0.0882569642156769579829267660235151628": -+double: 2 -+float: 1 -+idouble: 2 -+ifloat: 1 -+Test "yn (0, 1.5) == 0.382448923797758843955068554978089862": -+double: 2 -+float: 1 -+idouble: 2 -+ifloat: 1 -+Test "yn (0, 10.0) == 0.0556711672835993914244598774101900481": -+float: 1 -+ifloat: 1 -+ildouble: 3 -+ldouble: 3 -+Test "yn (0, 8.0) == 0.223521489387566220527323400498620359": -+double: 1 -+float: 1 -+idouble: 1 -+ifloat: 1 -+ildouble: 3 -+ldouble: 3 -+Test "yn (1, 0.125) == -5.19993611253477499595928744876579921": -+double: 1 -+idouble: 1 -+Test "yn (1, 0.75) == -1.03759455076928541973767132140642198": -+ildouble: 1 -+ldouble: 1 -+Test "yn (1, 1.5) == -0.412308626973911295952829820633445323": -+float: 1 -+ifloat: 1 -+ildouble: 1 -+ldouble: 1 -+Test "yn (1, 10.0) == 0.249015424206953883923283474663222803": -+double: 3 -+float: 1 -+idouble: 3 -+ifloat: 1 -+Test "yn (1, 2.0) == -0.107032431540937546888370772277476637": -+double: 1 -+float: 1 -+idouble: 1 -+ifloat: 1 -+ildouble: 1 -+ldouble: 1 -+Test "yn (1, 8.0) == -0.158060461731247494255555266187483550": -+double: 1 -+float: 2 -+idouble: 1 -+ifloat: 2 -+ildouble: 1 -+ldouble: 1 -+Test "yn (10, 0.125) == -127057845771019398.252538486899753195": -+double: 1 -+idouble: 1 -+ildouble: 2 -+ldouble: 2 -+Test "yn (10, 0.75) == -2133501638.90573424452445412893839236": -+double: 1 -+float: 1 -+idouble: 1 -+ifloat: 1 -+ildouble: 5 -+ldouble: 5 -+Test "yn (10, 1.0) == -121618014.278689189288130426667971145": -+double: 1 -+idouble: 1 -+ildouble: 1 -+ldouble: 1 -+Test "yn (10, 10.0) == -0.359814152183402722051986577343560609": -+double: 1 -+float: 1 -+idouble: 1 -+ifloat: 1 -+ildouble: 2 -+ldouble: 2 -+Test "yn (10, 2.0) == -129184.542208039282635913145923304214": -+double: 2 -+idouble: 2 -+ildouble: 2 -+ldouble: 2 -+Test "yn (3, 0.125) == -2612.69757350066712600220955744091741": -+double: 1 -+idouble: 1 -+Test "yn (3, 0.75) == -12.9877176234475433186319774484809207": -+double: 1 -+float: 1 -+idouble: 1 -+ifloat: 1 -+ildouble: 2 -+ldouble: 2 -+Test "yn (3, 10.0) == -0.251362657183837329779204747654240998": -+double: 1 -+float: 1 -+idouble: 1 -+ifloat: 1 -+ildouble: 1 -+ldouble: 1 -+Test "yn (3, 2.0) == -1.12778377684042778608158395773179238": -+double: 1 -+idouble: 1 -+ -+# Maximal error of functions: -+Function: "atan2": -+float: 1 -+ifloat: 1 -+ildouble: 1 -+ldouble: 1 -+ -+Function: "atanh": -+float: 1 -+ifloat: 1 -+ -+Function: Imaginary part of "cacos": -+ildouble: 1 -+ldouble: 1 -+ -+Function: Imaginary part of "cacosh": -+float: 1 -+ifloat: 1 -+ildouble: 1 -+ldouble: 1 -+ -+Function: Real part of "casin": -+double: 1 -+float: 1 -+idouble: 1 -+ifloat: 1 -+ -+Function: Imaginary part of "casin": -+ildouble: 1 -+ldouble: 1 -+ -+Function: Real part of "casinh": -+double: 5 -+float: 1 -+idouble: 5 -+ifloat: 1 -+ildouble: 4 -+ldouble: 4 -+ -+Function: Imaginary part of "casinh": -+double: 3 -+float: 6 -+idouble: 3 -+ifloat: 6 -+ildouble: 2 -+ldouble: 2 -+ -+Function: Imaginary part of "catan": -+double: 1 -+float: 1 -+idouble: 1 -+ifloat: 1 -+ildouble: 1 -+ldouble: 1 -+ -+Function: Real part of "catanh": -+double: 4 -+idouble: 4 -+ildouble: 1 -+ldouble: 1 -+ -+Function: Imaginary part of "catanh": -+ildouble: 1 -+ldouble: 1 -+ -+Function: "cbrt": -+double: 1 -+idouble: 1 -+ildouble: 1 -+ldouble: 1 -+ -+Function: Real part of "ccos": -+double: 1 -+float: 1 -+idouble: 1 -+ifloat: 1 -+ildouble: 1 -+ldouble: 1 -+ -+Function: Imaginary part of "ccos": -+float: 1 -+ifloat: 1 -+ildouble: 1 -+ldouble: 1 -+ -+Function: Real part of "ccosh": -+double: 1 -+float: 1 -+idouble: 1 -+ifloat: 1 -+ildouble: 1 -+ldouble: 1 -+ -+Function: Imaginary part of "ccosh": -+float: 1 -+ifloat: 1 -+ildouble: 1 -+ldouble: 1 -+ -+Function: Real part of "cexp": -+float: 1 -+ifloat: 1 -+ildouble: 1 -+ldouble: 1 -+ -+Function: Imaginary part of "cexp": -+float: 1 -+ifloat: 1 -+ildouble: 1 -+ldouble: 1 -+ -+Function: Real part of "clog": -+float: 1 -+ifloat: 1 -+ildouble: 1 -+ldouble: 1 -+ -+Function: Real part of "clog10": -+float: 1 -+ifloat: 1 -+ildouble: 1 -+ldouble: 1 -+ -+Function: Imaginary part of "clog10": -+double: 1 -+float: 1 -+idouble: 1 -+ifloat: 1 -+ildouble: 1 -+ldouble: 1 -+ -+Function: "cos": -+double: 2 -+float: 1 -+idouble: 2 -+ifloat: 1 -+ildouble: 1 -+ldouble: 1 -+ -+Function: Real part of "cpow": -+double: 2 -+float: 4 -+idouble: 2 -+ifloat: 4 -+ildouble: 10 -+ldouble: 10 -+ -+Function: Imaginary part of "cpow": -+double: 2 -+float: 2 -+idouble: 2 -+ifloat: 2 -+ildouble: 1 -+ldouble: 1 -+ -+Function: Real part of "csin": -+ildouble: 1 -+ldouble: 1 -+ -+Function: Imaginary part of "csin": -+ildouble: 1 -+ldouble: 1 -+ -+Function: Real part of "csinh": -+float: 1 -+ifloat: 1 -+ildouble: 1 -+ldouble: 1 -+ -+Function: Imaginary part of "csinh": -+double: 1 -+float: 1 -+idouble: 1 -+ifloat: 1 -+ -+Function: Real part of "csqrt": -+float: 1 -+ifloat: 1 -+ildouble: 1 -+ldouble: 1 -+ -+Function: Imaginary part of "csqrt": -+ildouble: 1 -+ldouble: 1 -+ -+Function: Real part of "ctan": -+ildouble: 1 -+ldouble: 1 -+ -+Function: Imaginary part of "ctan": -+double: 1 -+idouble: 1 -+ildouble: 2 -+ldouble: 2 -+ -+Function: Real part of "ctanh": -+double: 1 -+float: 2 -+idouble: 1 -+ifloat: 2 -+ildouble: 1 -+ldouble: 1 -+ -+Function: Imaginary part of "ctanh": -+float: 1 -+ifloat: 1 -+ildouble: 1 -+ldouble: 1 -+ -+Function: "erf": -+double: 1 -+idouble: 1 -+ -+Function: "erfc": -+double: 1 -+idouble: 1 -+ildouble: 1 -+ldouble: 1 -+ -+Function: "exp10": -+double: 6 -+float: 2 -+idouble: 6 -+ifloat: 2 -+ildouble: 1 -+ldouble: 1 -+ -+Function: "exp2": -+ildouble: 2 -+ldouble: 2 -+ -+Function: "expm1": -+double: 1 -+float: 1 -+idouble: 1 -+ifloat: 1 -+ildouble: 1 -+ldouble: 1 -+ -+Function: "gamma": -+ildouble: 1 -+ldouble: 1 -+ -+Function: "hypot": -+float: 1 -+ifloat: 1 -+ -+Function: "j0": -+double: 2 -+float: 2 -+idouble: 2 -+ifloat: 2 -+ildouble: 2 -+ldouble: 2 -+ -+Function: "j1": -+double: 1 -+float: 2 -+idouble: 1 -+ifloat: 2 -+ildouble: 4 -+ldouble: 4 -+ -+Function: "jn": -+double: 4 -+float: 4 -+idouble: 4 -+ifloat: 4 -+ildouble: 4 -+ldouble: 4 -+ -+Function: "lgamma": -+double: 1 -+float: 2 -+idouble: 1 -+ifloat: 2 -+ildouble: 1 -+ldouble: 1 -+ -+Function: "log10": -+double: 1 -+float: 2 -+idouble: 1 -+ifloat: 2 -+ildouble: 1 -+ldouble: 1 -+ -+Function: "log1p": -+float: 1 -+ifloat: 1 -+ildouble: 1 -+ldouble: 1 -+ -+Function: "log2": -+ildouble: 1 -+ldouble: 1 -+ -+Function: "sincos": -+double: 1 -+float: 1 -+idouble: 1 -+ifloat: 1 -+ildouble: 1 -+ldouble: 1 -+ -+Function: "sqrt": -+ildouble: 1 -+ldouble: 1 -+ -+Function: "tan": -+double: 1 -+idouble: 1 -+ -+Function: "tanh": -+ildouble: 1 -+ldouble: 1 -+ -+Function: "tgamma": -+double: 1 -+float: 1 -+idouble: 1 -+ifloat: 1 -+ildouble: 1 -+ldouble: 1 -+ -+Function: "y0": -+double: 2 -+float: 1 -+idouble: 2 -+ifloat: 1 -+ildouble: 3 -+ldouble: 3 -+ -+Function: "y1": -+double: 3 -+float: 2 -+idouble: 3 -+ifloat: 2 -+ildouble: 1 -+ldouble: 1 -+ -+Function: "yn": -+double: 3 -+float: 2 -+idouble: 3 -+ifloat: 2 -+ildouble: 5 -+ldouble: 5 -+ -+# end of automatic generation -diff --git a/glibc-2.14.1/sysdeps/riscv/rv64/soft-fp/Makefile b/glibc-2.14.1/sysdeps/riscv/rv64/soft-fp/Makefile -new file mode 100644 -index 0000000..ada13e8 ---- /dev/null -+++ glibc-2.14.1/sysdeps/riscv/rv64/soft-fp/Makefile -@@ -0,0 +1,3 @@ -+ifeq ($(subdir),math) -+CPPFLAGS += -I../soft-fp -+endif -diff --git a/glibc-2.14.1/sysdeps/riscv/rv64/soft-fp/sfp-machine.h b/glibc-2.14.1/sysdeps/riscv/rv64/soft-fp/sfp-machine.h -new file mode 100644 -index 0000000..0bf2776 ---- /dev/null -+++ glibc-2.14.1/sysdeps/riscv/rv64/soft-fp/sfp-machine.h -@@ -0,0 +1,74 @@ -+#include -+#include -+ -+#define _FP_W_TYPE_SIZE 64 -+#define _FP_W_TYPE unsigned long long -+#define _FP_WS_TYPE signed long long -+#define _FP_I_TYPE long long -+ -+#define _FP_MUL_MEAT_S(R,X,Y) \ -+ _FP_MUL_MEAT_1_imm(_FP_WFRACBITS_S,R,X,Y) -+#define _FP_MUL_MEAT_D(R,X,Y) \ -+ _FP_MUL_MEAT_1_wide(_FP_WFRACBITS_D,R,X,Y,umul_ppmm) -+#define _FP_MUL_MEAT_Q(R,X,Y) \ -+ _FP_MUL_MEAT_2_wide_3mul(_FP_WFRACBITS_Q,R,X,Y,umul_ppmm) -+ -+#define _FP_DIV_MEAT_S(R,X,Y) _FP_DIV_MEAT_1_imm(S,R,X,Y,_FP_DIV_HELP_imm) -+#define _FP_DIV_MEAT_D(R,X,Y) _FP_DIV_MEAT_1_udiv_norm(D,R,X,Y) -+#define _FP_DIV_MEAT_Q(R,X,Y) _FP_DIV_MEAT_2_udiv(Q,R,X,Y) -+ -+#define _FP_NANFRAC_S ((_FP_QNANBIT_S << 1) - 1) -+#define _FP_NANFRAC_D ((_FP_QNANBIT_D << 1) - 1) -+#define _FP_NANFRAC_Q ((_FP_QNANBIT_Q << 1) - 1), -1 -+#define _FP_NANSIGN_S 0 -+#define _FP_NANSIGN_D 0 -+#define _FP_NANSIGN_Q 0 -+ -+#define _FP_KEEPNANFRACP 1 -+/* From my experiments it seems X is chosen unless one of the -+ NaNs is sNaN, in which case the result is NANSIGN/NANFRAC. */ -+#define _FP_CHOOSENAN(fs, wc, R, X, Y, OP) \ -+ do { \ -+ if ((_FP_FRAC_HIGH_RAW_##fs(X) | \ -+ _FP_FRAC_HIGH_RAW_##fs(Y)) & _FP_QNANBIT_##fs) \ -+ { \ -+ R##_s = _FP_NANSIGN_##fs; \ -+ _FP_FRAC_SET_##wc(R,_FP_NANFRAC_##fs); \ -+ } \ -+ else \ -+ { \ -+ R##_s = X##_s; \ -+ _FP_FRAC_COPY_##wc(R,X); \ -+ } \ -+ R##_c = FP_CLS_NAN; \ -+ } while (0) -+ -+#define _FP_DECL_EX fpu_control_t _fcw -+ -+#define FP_ROUNDMODE (_fcw >> 5) -+ -+#define FP_RND_NEAREST FE_TONEAREST -+#define FP_RND_ZERO FE_TOWARDZERO -+#define FP_RND_PINF FE_UPWARD -+#define FP_RND_MINF FE_DOWNWARD -+ -+#define FP_EX_INVALID FE_INVALID -+#define FP_EX_OVERFLOW FE_OVERFLOW -+#define FP_EX_UNDERFLOW FE_UNDERFLOW -+#define FP_EX_DIVZERO FE_DIVBYZERO -+#define FP_EX_INEXACT FE_INEXACT -+ -+#ifdef __mips_hard_float -+#define FP_INIT_ROUNDMODE \ -+do { \ -+ _FPU_GETCW (_fcw); \ -+} while (0) -+ -+#define FP_HANDLE_EXCEPTIONS \ -+do { \ -+ if (__builtin_expect (_fex, 0)) \ -+ _FPU_SETCW (_fcw | _fex); \ -+} while (0) -+#else -+#define FP_INIT_ROUNDMODE _fcw = 0 /* no exceptions; FP_RND_NEAREST */ -+#endif -diff --git a/glibc-2.14.1/sysdeps/riscv/setjmp.S b/glibc-2.14.1/sysdeps/riscv/setjmp.S -new file mode 100644 -index 0000000..07559c5 ---- /dev/null -+++ glibc-2.14.1/sysdeps/riscv/setjmp.S -@@ -0,0 +1,83 @@ -+/* Copyright (C) 1996, 1997, 2000, 2002, 2003, 2004 -+ Free Software Foundation, Inc. -+ This file is part of the GNU C Library. -+ -+ The GNU C Library is free software; you can redistribute it and/or -+ modify it under the terms of the GNU Lesser General Public -+ License as published by the Free Software Foundation; either -+ version 2.1 of the License, or (at your option) any later version. -+ -+ The GNU C Library is distributed in the hope that it will be useful, -+ but WITHOUT ANY WARRANTY; without even the implied warranty of -+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU -+ Lesser General Public License for more details. -+ -+ You should have received a copy of the GNU Lesser General Public -+ License along with the GNU C Library; if not, write to the Free -+ Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA -+ 02111-1307 USA. */ -+ -+#include -+#include -+ -+ENTRY (_setjmp) -+ li a1, 0 -+ j __sigsetjmp -+END (_setjmp) -+ENTRY (setjmp) -+ li a1, 1 -+ /* Fallthrough */ -+END (setjmp) -+ENTRY (__sigsetjmp) -+ REG_S ra, 0*SZREG(a0) -+ REG_S s0, 1*SZREG(a0) -+ REG_S s1, 2*SZREG(a0) -+ REG_S s2, 3*SZREG(a0) -+ REG_S s3, 4*SZREG(a0) -+ REG_S s4, 5*SZREG(a0) -+ REG_S s5, 6*SZREG(a0) -+ REG_S s6, 7*SZREG(a0) -+ REG_S s7, 8*SZREG(a0) -+ REG_S s8, 9*SZREG(a0) -+ REG_S s9, 10*SZREG(a0) -+ REG_S s10,11*SZREG(a0) -+ REG_S s11,12*SZREG(a0) -+ REG_S sp, 13*SZREG(a0) -+ REG_S tp, 14*SZREG(a0) -+ -+#ifdef __riscv_hard_float -+ frsr a3 -+ -+ fsd fs0, 16*SZREG+ 0*8(a0) -+ fsd fs1, 16*SZREG+ 1*8(a0) -+ fsd fs2, 16*SZREG+ 2*8(a0) -+ fsd fs3, 16*SZREG+ 3*8(a0) -+ fsd fs4, 16*SZREG+ 4*8(a0) -+ fsd fs5, 16*SZREG+ 5*8(a0) -+ fsd fs6, 16*SZREG+ 6*8(a0) -+ fsd fs7, 16*SZREG+ 7*8(a0) -+ fsd fs8, 16*SZREG+ 8*8(a0) -+ fsd fs9, 16*SZREG+ 9*8(a0) -+ fsd fs10,16*SZREG+10*8(a0) -+ fsd fs11,16*SZREG+11*8(a0) -+ fsd fs12,16*SZREG+12*8(a0) -+ fsd fs13,16*SZREG+13*8(a0) -+ fsd fs14,16*SZREG+14*8(a0) -+ fsd fs15,16*SZREG+15*8(a0) -+ -+ REG_S a3, 15*SZREG(a0) -+#endif -+ -+#if defined NOT_IN_libc && defined IS_IN_rtld -+ /* In ld.so we never save the signal mask. */ -+ li v0, 0 -+ ret -+#else -+ /* Make a tail call to __sigjmp_save; it takes the same args. */ -+ j __sigjmp_save -+#endif -+ -+ -+END(__sigsetjmp) -+ -+weak_alias(_setjmp, __GI__setjmp) -diff --git a/glibc-2.14.1/sysdeps/riscv/sgidefs.h b/glibc-2.14.1/sysdeps/riscv/sgidefs.h -new file mode 100644 -index 0000000..34a6e61 ---- /dev/null -+++ glibc-2.14.1/sysdeps/riscv/sgidefs.h -@@ -0,0 +1,41 @@ -+/* Copyright (C) 1996, 1997, 1998, 2003, 2004 Free Software Foundation, Inc. -+ This file is part of the GNU C Library. -+ Contributed by Ralf Baechle . -+ -+ The GNU C Library is free software; you can redistribute it and/or -+ modify it under the terms of the GNU Lesser General Public -+ License as published by the Free Software Foundation; either -+ version 2.1 of the License, or (at your option) any later version. -+ -+ The GNU C Library is distributed in the hope that it will be useful, -+ but WITHOUT ANY WARRANTY; without even the implied warranty of -+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU -+ Lesser General Public License for more details. -+ -+ You should have received a copy of the GNU Lesser General Public -+ License along with the GNU C Library; if not, write to the Free -+ Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA -+ 02111-1307 USA. */ -+ -+#ifndef _SGIDEFS_H -+#define _SGIDEFS_H 1 -+ -+/* -+ * Subprogram calling convention -+ */ -+#ifndef _ABIO32 -+# define _ABIO32 1 -+#endif -+#define _RISCV_SIM_ABI32 _ABIO32 -+ -+#ifndef _ABIN32 -+# define _ABIN32 2 -+#endif -+#define _RISCV_SIM_NABI32 _ABIN32 -+ -+#ifndef _ABI64 -+# define _ABI64 3 -+#endif -+#define _RISCV_SIM_ABI64 _ABI64 -+ -+#endif /* sgidefs.h */ -diff --git a/glibc-2.14.1/sysdeps/riscv/soft-fp/sfp-machine.h b/glibc-2.14.1/sysdeps/riscv/soft-fp/sfp-machine.h -new file mode 100644 -index 0000000..3b2a40f ---- /dev/null -+++ glibc-2.14.1/sysdeps/riscv/soft-fp/sfp-machine.h -@@ -0,0 +1,47 @@ -+#define _FP_W_TYPE_SIZE 32 -+#define _FP_W_TYPE unsigned long -+#define _FP_WS_TYPE signed long -+#define _FP_I_TYPE long -+ -+#define _FP_MUL_MEAT_S(R,X,Y) \ -+ _FP_MUL_MEAT_1_wide(_FP_WFRACBITS_S,R,X,Y,umul_ppmm) -+#define _FP_MUL_MEAT_D(R,X,Y) \ -+ _FP_MUL_MEAT_2_wide(_FP_WFRACBITS_D,R,X,Y,umul_ppmm) -+#define _FP_MUL_MEAT_Q(R,X,Y) \ -+ _FP_MUL_MEAT_4_wide(_FP_WFRACBITS_Q,R,X,Y,umul_ppmm) -+ -+#define _FP_DIV_MEAT_S(R,X,Y) _FP_DIV_MEAT_1_udiv_norm(S,R,X,Y) -+#define _FP_DIV_MEAT_D(R,X,Y) _FP_DIV_MEAT_2_udiv(D,R,X,Y) -+#define _FP_DIV_MEAT_Q(R,X,Y) _FP_DIV_MEAT_4_udiv(Q,R,X,Y) -+ -+#define _FP_NANFRAC_S ((_FP_QNANBIT_S << 1) - 1) -+#define _FP_NANFRAC_D ((_FP_QNANBIT_D << 1) - 1), -1 -+#define _FP_NANFRAC_Q ((_FP_QNANBIT_Q << 1) - 1), -1, -1, -1 -+#define _FP_NANSIGN_S 0 -+#define _FP_NANSIGN_D 0 -+#define _FP_NANSIGN_Q 0 -+ -+#define _FP_KEEPNANFRACP 1 -+/* From my experiments it seems X is chosen unless one of the -+ NaNs is sNaN, in which case the result is NANSIGN/NANFRAC. */ -+#define _FP_CHOOSENAN(fs, wc, R, X, Y, OP) \ -+ do { \ -+ if ((_FP_FRAC_HIGH_RAW_##fs(X) | \ -+ _FP_FRAC_HIGH_RAW_##fs(Y)) & _FP_QNANBIT_##fs) \ -+ { \ -+ R##_s = _FP_NANSIGN_##fs; \ -+ _FP_FRAC_SET_##wc(R,_FP_NANFRAC_##fs); \ -+ } \ -+ else \ -+ { \ -+ R##_s = X##_s; \ -+ _FP_FRAC_COPY_##wc(R,X); \ -+ } \ -+ R##_c = FP_CLS_NAN; \ -+ } while (0) -+ -+#define FP_EX_INVALID (1 << 4) -+#define FP_EX_DIVZERO (1 << 3) -+#define FP_EX_OVERFLOW (1 << 2) -+#define FP_EX_UNDERFLOW (1 << 1) -+#define FP_EX_INEXACT (1 << 0) -diff --git a/glibc-2.14.1/sysdeps/riscv/stackinfo.h b/glibc-2.14.1/sysdeps/riscv/stackinfo.h -new file mode 100644 -index 0000000..7a5e3e0 ---- /dev/null -+++ glibc-2.14.1/sysdeps/riscv/stackinfo.h -@@ -0,0 +1,34 @@ -+/* Copyright (C) 2000, 2010 Free Software Foundation, Inc. -+ This file is part of the GNU C Library. -+ -+ The GNU C Library is free software; you can redistribute it and/or -+ modify it under the terms of the GNU Lesser General Public -+ License as published by the Free Software Foundation; either -+ version 2.1 of the License, or (at your option) any later version. -+ -+ The GNU C Library is distributed in the hope that it will be useful, -+ but WITHOUT ANY WARRANTY; without even the implied warranty of -+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU -+ Lesser General Public License for more details. -+ -+ You should have received a copy of the GNU Lesser General Public -+ License along with the GNU C Library; if not, write to the Free -+ Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA -+ 02111-1307 USA. */ -+ -+/* This file contains a bit of information about the stack allocation -+ of the processor. */ -+ -+#ifndef _STACKINFO_H -+#define _STACKINFO_H 1 -+ -+#include -+ -+/* On MIPS the stack grows down. */ -+#define _STACK_GROWS_DOWN 1 -+ -+/* Default to an executable stack. PF_X can be overridden if PT_GNU_STACK is -+ * present, but it is presumed absent. */ -+#define DEFAULT_STACK_PERMS (PF_R|PF_W|PF_X) -+ -+#endif /* stackinfo.h */ -diff --git a/glibc-2.14.1/sysdeps/riscv/strcmp.S b/glibc-2.14.1/sysdeps/riscv/strcmp.S -new file mode 100644 -index 0000000..2db21ea ---- /dev/null -+++ glibc-2.14.1/sysdeps/riscv/strcmp.S -@@ -0,0 +1,129 @@ -+# Artisanally coded in California by A. Shell Waterman -+ -+#include -+#include -+ -+#if BYTE_ORDER != LITTLE_ENDIAN -+# error -+#endif -+ -+ENTRY(strcmp) -+ or v1, a0, a1 -+ li t2, -1 -+ and v1, v1, SZREG-1 -+ li v0, 0 -+ bnez v1, .Lmisaligned -+ -+#if SZREG == 4 -+ li t3, 0x7f7f7f7f -+#else -+ ld t3, mask -+#endif -+ -+ .macro check_one_word i n -+ REG_L a2, \i*SZREG(a0) -+ REG_L a3, \i*SZREG(a1) -+ -+ and t0, a2, t3 -+ or t1, a2, t3 -+ add t0, t0, t3 -+ or t0, t0, t1 -+ -+ bne t0, t2, .Lnull\i -+ .if \i+1-\n -+ bne a2, a3, .Lmismatch -+ .else -+ add a0, a0, \n*SZREG -+ add a1, a1, \n*SZREG -+ beq a2, a3, .Lloop -+ # fall through to .Lmismatch -+ .endif -+ .endm -+ -+ .macro foundnull i n -+ .ifne \i -+ .Lnull\i: -+ add a0, a0, \i*SZREG -+ add a1, a1, \i*SZREG -+ .ifeq \i-1 -+ .Lnull0: -+ .endif -+ bne a2, a3, .Lmisaligned -+ ret -+ .endif -+ .endm -+ -+.Lloop: -+ # examine full words -+ check_one_word 0 4 -+ check_one_word 1 4 -+ check_one_word 2 4 -+ check_one_word 3 4 -+ # backwards branch to .Lloop contained above -+ -+.Lmismatch: -+ # words don't match, but a2 has no null byte. -+#ifdef __riscv64 -+ sll a0, a2, 48 -+ sll a1, a3, 48 -+ bne a0, a1, .Lmismatch_upper -+ sll a0, a2, 32 -+ sll a1, a3, 32 -+ bne a0, a1, .Lmismatch_upper -+#endif -+ sll a0, a2, 16 -+ sll a1, a3, 16 -+ bne a0, a1, .Lmismatch_upper -+ -+ srl a0, a2, 8*SZREG-16 -+ srl a1, a3, 8*SZREG-16 -+ sub v0, a0, a1 -+ and v1, v0, 0xff -+ bnez v1, 1f -+ ret -+ -+.Lmismatch_upper: -+ srl a0, a0, 8*SZREG-16 -+ srl a1, a1, 8*SZREG-16 -+ sub v0, a0, a1 -+ and v1, v0, 0xff -+ bnez v1, 1f -+ ret -+ -+1:and a0, a0, 0xff -+ and a1, a1, 0xff -+ sub v0, a0, a1 -+ ret -+ -+.Lmisaligned: -+ # misaligned -+ lbu v0, 0(a0) -+ lbu v1, 0(a1) -+ add a0, a0, 1 -+ add a1, a1, 1 -+ bne v0, v1, 1f -+ bnez v0, .Lmisaligned -+ -+1: -+ sub v0, v0, v1 -+ ret -+ -+ # cases in which a null byte was detected -+ foundnull 0, 4 -+ foundnull 1, 4 -+ foundnull 2, 4 -+ foundnull 3, 4 -+ -+END(strcmp) -+ -+weak_alias(strcmp, __GI_strcmp) -+ -+#if SZREG == 8 -+#ifdef __PIC__ -+.section .rodata.cst8,"aM",@progbits,8 -+#else -+.section .srodata.cst8,"aM",@progbits,8 -+#endif -+.align 3 -+mask: .8byte 0x7f7f7f7f7f7f7f7f -+#endif -diff --git a/glibc-2.14.1/sysdeps/riscv/strcpy.c b/glibc-2.14.1/sysdeps/riscv/strcpy.c -new file mode 100644 -index 0000000..c01c506 ---- /dev/null -+++ glibc-2.14.1/sysdeps/riscv/strcpy.c -@@ -0,0 +1,54 @@ -+#include -+#include -+ -+#undef strcpy -+ -+char* strcpy(char* dst, const char* src) -+{ -+ char* dst0 = dst; -+ -+ int misaligned = ((uintptr_t)dst | (uintptr_t)src) & (sizeof(long)-1); -+ if (__builtin_expect(!misaligned, 1)) -+ { -+ long* ldst = (long*)dst; -+ const long* lsrc = (const long*)src; -+ -+ while (!__libc_detect_null(*lsrc)) -+ *ldst++ = *lsrc++; -+ -+ dst = (char*)ldst; -+ src = (const char*)lsrc; -+ -+ char c0 = src[0]; -+ char c1 = src[1]; -+ char c2 = src[2]; -+ if (!(*dst++ = c0)) return dst0; -+ if (!(*dst++ = c1)) return dst0; -+ char c3 = src[3]; -+ if (!(*dst++ = c2)) return dst0; -+ if (sizeof(long) == 4) goto out; -+ char c4 = src[4]; -+ if (!(*dst++ = c3)) return dst0; -+ char c5 = src[5]; -+ if (!(*dst++ = c4)) return dst0; -+ char c6 = src[6]; -+ if (!(*dst++ = c5)) return dst0; -+ if (!(*dst++ = c6)) return dst0; -+ -+out: -+ *dst++ = 0; -+ return dst0; -+ } -+ -+ char ch; -+ do -+ { -+ ch = *src; -+ src++; -+ dst++; -+ *(dst-1) = ch; -+ } while(ch); -+ -+ return dst0; -+} -+libc_hidden_def(strcpy) -diff --git a/glibc-2.14.1/sysdeps/riscv/strlen.c b/glibc-2.14.1/sysdeps/riscv/strlen.c -new file mode 100644 -index 0000000..2630f46 ---- /dev/null -+++ glibc-2.14.1/sysdeps/riscv/strlen.c -@@ -0,0 +1,38 @@ -+#include -+#include -+ -+#undef strlen -+ -+size_t strlen(const char* str) -+{ -+ const char* start = str; -+ -+ if (__builtin_expect((uintptr_t)str & (sizeof(long)-1), 0)) do -+ { -+ char ch = *str; -+ str++; -+ if (!ch) -+ return str - start - 1; -+ } while ((uintptr_t)str & (sizeof(long)-1)); -+ -+ unsigned long* ls = (unsigned long*)str; -+ while (!__libc_detect_null(*ls++)) -+ ; -+ asm volatile ("" : "+r"(ls)); /* prevent "optimization" */ -+ -+ str = (const char*)ls; -+ size_t ret = str - start, sl = sizeof(long); -+ -+ char c0 = str[0-sl], c1 = str[1-sl], c2 = str[2-sl], c3 = str[3-sl]; -+ if (c0 == 0) return ret + 0 - sl; -+ if (c1 == 0) return ret + 1 - sl; -+ if (c2 == 0) return ret + 2 - sl; -+ if (sl == 4 || c3 == 0) return ret + 3 - sl; -+ -+ c0 = str[4-sl], c1 = str[5-sl], c2 = str[6-sl], c3 = str[7-sl]; -+ if (c0 == 0) return ret + 4 - sl; -+ if (c1 == 0) return ret + 5 - sl; -+ if (c2 == 0) return ret + 6 - sl; -+ return ret + 7 - sl; -+} -+libc_hidden_def(strlen) -diff --git a/glibc-2.14.1/sysdeps/riscv/sys/asm.h b/glibc-2.14.1/sysdeps/riscv/sys/asm.h -new file mode 100644 -index 0000000..fc30999 ---- /dev/null -+++ glibc-2.14.1/sysdeps/riscv/sys/asm.h -@@ -0,0 +1,69 @@ -+/* copyright (c) 1997, 1998, 2002, 2003, 2004, 2005 -+ Free Software Foundation, Inc. -+ This file is part of the GNU C Library. -+ Contributed by Ralf Baechle . -+ -+ The GNU C Library is free software; you can redistribute it and/or -+ modify it under the terms of the GNU Lesser General Public -+ License as published by the Free Software Foundation; either -+ version 2.1 of the License, or (at your option) any later version. -+ -+ The GNU C Library is distributed in the hope that it will be useful, -+ but WITHOUT ANY WARRANTY; without even the implied warranty of -+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU -+ Lesser General Public License for more details. -+ -+ You should have received a copy of the GNU Lesser General Public -+ License along with the GNU C Library; if not, write to the Free -+ Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA -+ 02111-1307 USA. */ -+ -+#ifndef _SYS_ASM_H -+#define _SYS_ASM_H -+ -+/* -+ * Macros to handle different pointer/register sizes for 32/64-bit code -+ */ -+#ifdef __riscv64 -+# define PTR .dword -+# define PTRLOG 3 -+# define SZREG 8 -+# define REG_S sd -+# define REG_L ld -+#else -+# define PTR .word -+# define PTRLOG 2 -+# define SZREG 4 -+# define REG_S sw -+# define REG_L lw -+#endif -+ -+/* -+ * LEAF - declare leaf routine -+ */ -+#define LEAF(symbol) \ -+ .globl symbol; \ -+ .align 2; \ -+ .type symbol,@function; \ -+symbol: -+ -+/* -+ * NESTED - declare nested routine entry point -+ */ -+#define NESTED(symbol, framesize, rpc) LEAF(symbol) -+ -+/* -+ * END - mark end of function -+ */ -+#ifndef END -+# define END(function) \ -+ .size function,.-function -+#endif -+ -+/* -+ * Stack alignment -+ */ -+#define ALSZ 15 -+#define ALMASK ~15 -+ -+#endif /* sys/asm.h */ -diff --git a/glibc-2.14.1/sysdeps/riscv/tcb-offsets.sym b/glibc-2.14.1/sysdeps/riscv/tcb-offsets.sym -new file mode 100644 -index 0000000..e0e71dc ---- /dev/null -+++ glibc-2.14.1/sysdeps/riscv/tcb-offsets.sym -@@ -0,0 +1,11 @@ -+#include -+#include -+ -+-- -+ -+-- Abuse tls.h macros to derive offsets relative to the thread register. -+#define thread_offsetof(mem) (long)(offsetof(struct pthread, mem) - TLS_TCB_OFFSET - TLS_PRE_TCB_SIZE) -+ -+MULTIPLE_THREADS_OFFSET thread_offsetof (header.multiple_threads) -+PID_OFFSET thread_offsetof (pid) -+TID_OFFSET thread_offsetof (tid) -diff --git a/glibc-2.14.1/sysdeps/riscv/tst-audit.h b/glibc-2.14.1/sysdeps/riscv/tst-audit.h -new file mode 100644 -index 0000000..ac011fc ---- /dev/null -+++ glibc-2.14.1/sysdeps/riscv/tst-audit.h -@@ -0,0 +1,33 @@ -+/* Definitions for testing PLT entry/exit auditing. ARM version. -+ -+ Copyright (C) 2005 Free Software Foundation, Inc. -+ -+ This file is part of the GNU C Library. -+ -+ The GNU C Library is free software; you can redistribute it and/or -+ modify it under the terms of the GNU Lesser General Public -+ License as published by the Free Software Foundation; either -+ version 2.1 of the License, or (at your option) any later version. -+ -+ The GNU C Library is distributed in the hope that it will be useful, -+ but WITHOUT ANY WARRANTY; without even the implied warranty of -+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU -+ Lesser General Public License for more details. -+ -+ You should have received a copy of the GNU Lesser General Public -+ License along with the GNU C Library; if not, write to the Free -+ Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA -+ 02111-1307 USA. */ -+ -+#include -+ -+#if _RISCV_SIM == _ABI32 -+#define pltenter la_mips_n32_gnu_pltenter -+#define pltexit la_mips_n32_gnu_pltexit -+#else -+#define pltenter la_mips_n64_gnu_pltenter -+#define pltexit la_mips_n64_gnu_pltexit -+#endif -+#define La_regs La_mips_64_regs -+#define La_retval La_mips_64_retval -+#define int_retval lrv_v0 -diff --git a/glibc-2.14.1/sysdeps/unix/riscv/pipe.S b/glibc-2.14.1/sysdeps/unix/riscv/pipe.S -new file mode 100644 -index 0000000..d6c4e4a ---- /dev/null -+++ glibc-2.14.1/sysdeps/unix/riscv/pipe.S -@@ -0,0 +1,34 @@ -+/* Copyright (C) 1992, 1995, 1997, 2000, 2002 Free Software Foundation, Inc. -+ This file is part of the GNU C Library. -+ Contributed by Brendan Kehoe (brendan@zen.org). -+ -+ The GNU C Library is free software; you can redistribute it and/or -+ modify it under the terms of the GNU Lesser General Public -+ License as published by the Free Software Foundation; either -+ version 2.1 of the License, or (at your option) any later version. -+ -+ The GNU C Library is distributed in the hope that it will be useful, -+ but WITHOUT ANY WARRANTY; without even the implied warranty of -+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU -+ Lesser General Public License for more details. -+ -+ You should have received a copy of the GNU Lesser General Public -+ License along with the GNU C Library; if not, write to the Free -+ Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA -+ 02111-1307 USA. */ -+ -+#include -+ -+SYSCALL__ (pipe, 1) -+ /* Plop in the two descriptors. */ -+/* sw v0, 0(a0) -+ sw v1, 4(a0) -+ -+*/ -+ /* Go out with a clean status. */ -+ move v0, zero -+ ret -+PSEUDO_END(__pipe) -+ -+libc_hidden_def (__pipe) -+weak_alias (__pipe, pipe) -diff --git a/glibc-2.14.1/sysdeps/unix/riscv/rt-sysdep.c b/glibc-2.14.1/sysdeps/unix/riscv/rt-sysdep.c -new file mode 100644 -index 0000000..3ff5595 ---- /dev/null -+++ glibc-2.14.1/sysdeps/unix/riscv/rt-sysdep.c -@@ -0,0 +1 @@ -+#include -diff --git a/glibc-2.14.1/sysdeps/unix/riscv/sysdep.c b/glibc-2.14.1/sysdeps/unix/riscv/sysdep.c -new file mode 100644 -index 0000000..308eced ---- /dev/null -+++ glibc-2.14.1/sysdeps/unix/riscv/sysdep.c -@@ -0,0 +1,43 @@ -+/* Copyright (C) 1992, 1993, 1994, 1997, 1998, 1999, 2000, 2002, 2003 -+ Free Software Foundation, Inc. -+ This file is part of the GNU C Library. -+ Contributed by Brendan Kehoe (brendan@zen.org). -+ -+ The GNU C Library is free software; you can redistribute it and/or -+ modify it under the terms of the GNU Lesser General Public -+ License as published by the Free Software Foundation; either -+ version 2.1 of the License, or (at your option) any later version. -+ -+ The GNU C Library is distributed in the hope that it will be useful, -+ but WITHOUT ANY WARRANTY; without even the implied warranty of -+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU -+ Lesser General Public License for more details. -+ -+ You should have received a copy of the GNU Lesser General Public -+ License along with the GNU C Library; if not, write to the Free -+ Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA -+ 02111-1307 USA. */ -+ -+#include -+#include -+ -+long __syscall_error() -+{ -+ register long v0 asm("v0"); -+ -+ /* Referencing errno may call a function, clobbering v0. */ -+ long errno_val = -v0; -+ -+#if defined (EWOULDBLOCK_sys) && EWOULDBLOCK_sys != EAGAIN -+ /* We translate the system's EWOULDBLOCK error into EAGAIN. -+ The GNU C library always defines EWOULDBLOCK==EAGAIN. -+ EWOULDBLOCK_sys is the original number. */ -+ -+ if (errno_val == EWOULDBLOCK_sys) -+ errno_val = EAGAIN; -+#endif -+ -+ errno = errno_val; -+ -+ return -1; -+} -diff --git a/glibc-2.14.1/sysdeps/unix/riscv/sysdep.h b/glibc-2.14.1/sysdeps/unix/riscv/sysdep.h -new file mode 100644 -index 0000000..910afd5 ---- /dev/null -+++ glibc-2.14.1/sysdeps/unix/riscv/sysdep.h -@@ -0,0 +1,72 @@ -+/* Copyright (C) 1992, 1995, 1997, 1999, 2000, 2002, 2003, 2004 -+ Free Software Foundation, Inc. -+ This file is part of the GNU C Library. -+ Contributed by Brendan Kehoe (brendan@zen.org). -+ -+ The GNU C Library is free software; you can redistribute it and/or -+ modify it under the terms of the GNU Lesser General Public -+ License as published by the Free Software Foundation; either -+ version 2.1 of the License, or (at your option) any later version. -+ -+ The GNU C Library is distributed in the hope that it will be useful, -+ but WITHOUT ANY WARRANTY; without even the implied warranty of -+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU -+ Lesser General Public License for more details. -+ -+ You should have received a copy of the GNU Lesser General Public -+ License along with the GNU C Library; if not, write to the Free -+ Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA -+ 02111-1307 USA. */ -+ -+#include -+ -+#ifdef __ASSEMBLER__ -+ -+#include -+ -+#define ENTRY(name) LEAF(name) -+ -+#undef END -+#define END(function) \ -+ .size function,.-function -+ -+#define ret ret -+ -+#undef PSEUDO_END -+#define PSEUDO_END(sym) .size sym,.-sym -+ -+#define PSEUDO_NOERRNO(name, syscall_name, args) \ -+ .align 2; \ -+ ENTRY(name) \ -+ li v0, SYS_ify(syscall_name); \ -+ scall -+ -+#undef PSEUDO_END_NOERRNO -+#define PSEUDO_END_NOERRNO(sym) .size sym,.-sym -+ -+#define ret_NOERRNO ret -+ -+#define PSEUDO_ERRVAL(name, syscall_name, args) \ -+ PSEUDO_NOERRNO(name, syscall_name, args) -+ -+#undef PSEUDO_END_ERRVAL -+#define PSEUDO_END_ERRVAL(sym) PSEUDO_END_NOERRNO(sym) -+ -+#define ret_ERRVAL ret -+ -+#define r0 v0 -+#define r1 v1 -+#define MOVE(x,y) move y , x -+ -+#define L(label) .L ## label -+ -+#define PSEUDO(name, syscall_name, args) \ -+ .align 2; \ -+ 99: j __syscall_error; \ -+ ENTRY(name) \ -+ li v0, SYS_ify(syscall_name); \ -+ scall; \ -+ bltz v0, 99b; \ -+L(syse1): -+ -+#endif -diff --git a/glibc-2.14.1/sysdeps/unix/sysv/linux/riscv/Implies b/glibc-2.14.1/sysdeps/unix/sysv/linux/riscv/Implies -new file mode 100644 -index 0000000..72096a4 ---- /dev/null -+++ glibc-2.14.1/sysdeps/unix/sysv/linux/riscv/Implies -@@ -0,0 +1,2 @@ -+# This needs to change to support rv32 -+unix/sysv/linux/riscv/rv64 -diff --git a/glibc-2.14.1/sysdeps/unix/sysv/linux/riscv/Makefile b/glibc-2.14.1/sysdeps/unix/sysv/linux/riscv/Makefile -new file mode 100644 -index 0000000..4d96756 ---- /dev/null -+++ glibc-2.14.1/sysdeps/unix/sysv/linux/riscv/Makefile -@@ -0,0 +1,139 @@ -+ifeq ($(subdir),signal) -+#sysdep_routines += sigsuspend -+endif -+ -+ifeq ($(subdir),misc) -+ -+no_syscall_list_h = 1 -+ -+# A callable macro that expands to a shell command. Preprocess file $(1) -+# using ABI option $(2) and see which macros it defines. Print FOO for each -+# macro of the form __NR$(3)_FOO, filtering out ABI-specific __NR macros -+# that have a prefix other than $(3). -+mips_list_syscalls = $(filter-out -m%,$(CC)) -E -x c $(+includes) \ -+ $(sysincludes) -D_LIBC -dM -m$(2) $(1) | \ -+ sed -n 's@^\#define __NR$(3)_\([^ ]*\) .*@\1@p' | \ -+ sed -e '/^[ON]32_/d' -e '/^N64_/d' -e '/^64_/d' | \ -+ LC_ALL=C sort -+ -+# Generate a list of SYS_* macros from the linux __NR macros. -+# -+# Before version 2.6, linux had separate 32-bit and 64-bit MIPS ports, -+# each with its own set of headers. The ports were merged for 2.6 and -+# this merged port defines the syscalls in a slightly different way. -+# There are therefore three sets of headers that we need to consider: -+# -+# (1) Headers from the separate 32-bit MIPS port. They just define -+# a single list of __NR macros. -+# -+# (2) Headers from the separate 64-bit MIPS port. They unconditionally -+# define syscalls for all three ABIs, with o32 syscalls prefixed -+# by __NR_O32, n32 syscalls prefixed by __NR_N32 and n64 syscalls -+# prefixed by plain __NR. -+# -+# (3) Headers from the combined port. They use the _RISCV_SIM macro to -+# define the right set of syscalls for the current ABI. The syscalls -+# themselves have no special ABI prefix, but the headers also define: -+# -+# __NR_O32_Linux{,_syscalls} -+# __NR_N32_Linux{,_syscalls} -+# __NR_64_Linux{,_syscalls} -+# -+# In case (1) we just want a simple list of SYS_* macros. In cases (2) -+# and (3) we want a file that will work for all three ABIs, regardless -+# of which ABI we are currently using. We also want the file to work -+# if the user later moves from (2) to (3). Thus the file we create -+# for (2) and (3) has the form: -+# -+# #if _RISCV_SIM == _ABIN32 -+# # ifdef __NR_N32_open -+# # define SYS_n32syscall1 __NR_N32_n32syscall1 -+# # ... -+# # else -+# # define SYS_n32syscall1 __NR_n32syscall1 -+# # ... -+# # endif -+# #elif _RISCV_SIM == _ABI64 -+# # define SYS_n64syscall1 __NR_n64syscall1 -+# # ... -+# #else -+# # ifdef __NR_O32_open -+# # define SYS_o32syscall1 __NR_O32_o32syscall1 -+# # ... -+# # else -+# # define SYS_o32syscall1 __NR_o32syscall1 -+# # ... -+# # endif -+# #endif -+# -+# Here, __NR_N32_open and __NR_O32_open are used to detect case (2) -+# over case (3). The n64 SYS_* macros can always use the normal -+# ABI-less names. -+$(objpfx)syscall-%.h $(objpfx)syscall-%.d: ../sysdeps/unix/sysv/linux/mips/sys/syscall.h -+ $(make-target-directory) -+ $(CC) -E -x c $(+includes) $(sysincludes) -D_LIBC $< -MD -MP \ -+ -MF $(@:.h=.d)-t -MT '$(@:.d=.h) $(@:.h=.d)' > /dev/null -+ { \ -+ echo '/* Generated at libc build time from kernel syscall list. */';\ -+ echo ''; \ -+ echo '#ifndef _SYSCALL_H'; \ -+ echo '# error "Never use directly; include instead."'; \ -+ echo '#endif'; \ -+ echo ''; \ -+ echo '#include '; \ -+ rm -f $(@:.d=.h).new32 $(@:.d=.h).newn32 $(@:.d=.h).new64; \ -+ $(call mips_list_syscalls,$<,n32,_N32) > $(@:.d=.h).newn32; \ -+ if test -s $(@:.d=.h).newn32; then \ -+ if grep open $(@:.d=.h).newn32 > /dev/null; then \ -+ $(call mips_list_syscalls,$<,32,_O32) > $(@:.d=.h).new32; \ -+ $(call mips_list_syscalls,$<,64,) > $(@:.d=.h).new64; \ -+ else \ -+ $(call mips_list_syscalls,$<,32,) > $(@:.d=.h).new32; \ -+ $(call mips_list_syscalls,$<,n32,) > $(@:.d=.h).newn32; \ -+ $(call mips_list_syscalls,$<,64,) > $(@:.d=.h).new64; \ -+ fi; \ -+ echo '#if _RISCV_SIM == _ABIN32'; \ -+ echo '# ifdef __NR_N32_open'; \ -+ sed 's@\(.*\)@# define SYS_\1 __NR_N32_\1@' < $(@:.d=.h).newn32; \ -+ echo '# else'; \ -+ sed 's@\(.*\)@# define SYS_\1 __NR_\1@' < $(@:.d=.h).newn32; \ -+ echo '# endif'; \ -+ echo '#elif _RISCV_SIM == _ABI64'; \ -+ sed 's@\(.*\)@# define SYS_\1 __NR_\1@' < $(@:.d=.h).new64; \ -+ echo '#else'; \ -+ echo '# ifdef __NR_O32_open'; \ -+ sed 's@\(.*\)@# define SYS_\1 __NR_O32_\1@' < $(@:.d=.h).new32; \ -+ echo '# else'; \ -+ sed 's@\(.*\)@# define SYS_\1 __NR_\1@' < $(@:.d=.h).new32; \ -+ echo '# endif'; \ -+ echo '#endif'; \ -+ else \ -+ $(CC) -E -x c $(+includes) $(sysincludes) -D_LIBC -dM $< | \ -+ sed -n 's@^\#define __NR_\([^ ]*\) .*@\#define SYS_\1 __NR_\1@p' | \ -+ LC_ALL=C sort; \ -+ fi; \ -+ rm -f $(@:.d=.h).new32 $(@:.d=.h).newn32 $(@:.d=.h).new64; \ -+ } > $(@:.d=.h).new -+ mv -f $(@:.d=.h).new $(@:.d=.h) -+ifneq (,$(objpfx)) -+ sed $(sed-remove-objpfx) $(@:.h=.d)-t > $(@:.h=.d)-t2 -+ rm -f $(@:.h=.d)-t -+ mv -f $(@:.h=.d)-t2 $(@:.h=.d) -+else -+ mv -f $(@:.h=.d)-t $(@:.h=.d) -+endif -+endif -+ -+ifeq ($(subdir),elf) -+ifeq ($(build-shared),yes) -+# This is needed for DSO loading from static binaries. -+sysdep-dl-routines += dl-static -+sysdep_routines += dl-static -+sysdep-rtld-routines += dl-static -+endif -+endif -+ -+ifeq ($(subdir),stdlib) -+sysdep_routines += __start_context -+gen-as-const-headers += ucontext_i.sym -+endif -diff --git a/glibc-2.14.1/sysdeps/unix/sysv/linux/riscv/Versions b/glibc-2.14.1/sysdeps/unix/sysv/linux/riscv/Versions -new file mode 100644 -index 0000000..a56322a ---- /dev/null -+++ glibc-2.14.1/sysdeps/unix/sysv/linux/riscv/Versions -@@ -0,0 +1,40 @@ -+ld { -+ GLIBC_PRIVATE { -+ # used for loading by static libraries -+ _dl_var_init; -+ } -+} -+libc { -+ # The comment lines with "#errlist-compat" are magic; see errlist-compat.awk. -+ # When you get an error from errlist-compat.awk, you need to add a new -+ # version here. Don't do this blindly, since this means changing the ABI -+ # for all GNU/Linux configurations. -+ -+ GLIBC_2.0 { -+ #errlist-compat 123 -+ _sys_errlist; sys_errlist; _sys_nerr; sys_nerr; -+ -+ # Exception handling support functions from libgcc -+ __register_frame; __register_frame_table; __deregister_frame; -+ __frame_state_for; __register_frame_info_table; -+ -+ # Needed by gcc: -+ _flush_cache; -+ -+ # c* -+ cachectl; cacheflush; -+ -+ # s* -+ sysmips; -+ } -+ GLIBC_2.2 { -+ #errlist-compat 1134 -+ _sys_errlist; sys_errlist; _sys_nerr; sys_nerr; -+ -+ # _* -+ _test_and_set; -+ } -+ GLIBC_2.11 { -+ fallocate64; -+ } -+} -diff --git a/glibc-2.14.1/sysdeps/unix/sysv/linux/riscv/____longjmp_chk.S b/glibc-2.14.1/sysdeps/unix/sysv/linux/riscv/____longjmp_chk.S -new file mode 100644 -index 0000000..e903c7e ---- /dev/null -+++ glibc-2.14.1/sysdeps/unix/sysv/linux/riscv/____longjmp_chk.S -@@ -0,0 +1,2 @@ -+#define __longjmp ____longjmp_chk -+#include <__longjmp.S> -diff --git a/glibc-2.14.1/sysdeps/unix/sysv/linux/riscv/__start_context.S b/glibc-2.14.1/sysdeps/unix/sysv/linux/riscv/__start_context.S -new file mode 100644 -index 0000000..7408289 ---- /dev/null -+++ glibc-2.14.1/sysdeps/unix/sysv/linux/riscv/__start_context.S -@@ -0,0 +1,38 @@ -+/* Modify saved context. -+ Copyright (C) 2009 Free Software Foundation, Inc. -+ This file is part of the GNU C Library. -+ Contributed by Maciej W. Rozycki . -+ -+ The GNU C Library is free software; you can redistribute it and/or -+ modify it under the terms of the GNU Lesser General Public -+ License as published by the Free Software Foundation; either -+ version 2.1 of the License, or (at your option) any later version. -+ -+ The GNU C Library is distributed in the hope that it will be useful, -+ but WITHOUT ANY WARRANTY; without even the implied warranty of -+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU -+ Lesser General Public License for more details. -+ -+ You should have received a copy of the GNU Lesser General Public -+ License along with the GNU C Library; if not, write to the Free -+ Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA -+ 02110-1301, USA. */ -+ -+#include -+#include -+ -+#include "ucontext_i.h" -+ -+ .text -+LEAF (__start_context) -+ move a0, zero -+ beqz s0, 1f -+ -+ /* setcontext (ucp) */ -+ move a0, s0 -+ jal __setcontext -+ move a0, v0 -+ -+1: jal HIDDEN_JUMPTARGET (exit) -+ -+PSEUDO_END (__start_context) -diff --git a/glibc-2.14.1/sysdeps/unix/sysv/linux/riscv/_test_and_set.c b/glibc-2.14.1/sysdeps/unix/sysv/linux/riscv/_test_and_set.c -new file mode 100644 -index 0000000..9fd48f7 ---- /dev/null -+++ glibc-2.14.1/sysdeps/unix/sysv/linux/riscv/_test_and_set.c -@@ -0,0 +1,30 @@ -+/* Copyright (C) 2000 Free Software Foundation, Inc. -+ This file is part of the GNU C Library. -+ Contributed by Maciej W. Rozycki , 2000. -+ -+ The GNU C Library is free software; you can redistribute it and/or -+ modify it under the terms of the GNU Lesser General Public -+ License as published by the Free Software Foundation; either -+ version 2.1 of the License, or (at your option) any later version. -+ -+ The GNU C Library is distributed in the hope that it will be useful, -+ but WITHOUT ANY WARRANTY; without even the implied warranty of -+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU -+ Lesser General Public License for more details. -+ -+ You should have received a copy of the GNU Lesser General Public -+ License along with the GNU C Library; if not, write to the Free -+ Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA -+ 02111-1307 USA. */ -+ -+/* Define the real-function versions of all inline functions -+ defined in sys/tas.h */ -+ -+#include -+ -+#define _EXTERN_INLINE -+#ifndef __USE_EXTERN_INLINES -+# define __USE_EXTERN_INLINES 1 -+#endif -+ -+#include "sys/tas.h" -diff --git a/glibc-2.14.1/sysdeps/unix/sysv/linux/riscv/bits/atomic.h b/glibc-2.14.1/sysdeps/unix/sysv/linux/riscv/bits/atomic.h -new file mode 100644 -index 0000000..82b9006 ---- /dev/null -+++ glibc-2.14.1/sysdeps/unix/sysv/linux/riscv/bits/atomic.h -@@ -0,0 +1,53 @@ -+/* Low-level functions for atomic operations. Mips version. -+ Copyright (C) 2005 Free Software Foundation, Inc. -+ This file is part of the GNU C Library. -+ -+ The GNU C Library is free software; you can redistribute it and/or -+ modify it under the terms of the GNU Lesser General Public -+ License as published by the Free Software Foundation; either -+ version 2.1 of the License, or (at your option) any later version. -+ -+ The GNU C Library is distributed in the hope that it will be useful, -+ but WITHOUT ANY WARRANTY; without even the implied warranty of -+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU -+ Lesser General Public License for more details. -+ -+ You should have received a copy of the GNU Lesser General Public -+ License along with the GNU C Library; if not, write to the Free -+ Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA -+ 02111-1307 USA. */ -+ -+#ifndef _LINUX_RISCV_BITS_ATOMIC_H -+#define _LINUX_RISCV_BITS_ATOMIC_H 1 -+ -+#include_next -+ -+#ifndef __riscv_atomic -+ -+#include -+#include -+ -+#define __arch_compare_and_exchange_val_8_acq(mem, newval, oldval) \ -+ (abort (), (__typeof (*mem)) 0) -+ -+#define __arch_compare_and_exchange_val_16_acq(mem, newval, oldval) \ -+ (abort (), (__typeof (*mem)) 0) -+ -+/* The only basic operation needed is compare and exchange. */ -+#define __arch_compare_and_exchange_val_32_acq(mem, newval, oldval) \ -+ ({ \ -+ INTERNAL_SYSCALL_DECL (__err); \ -+ INTERNAL_SYSCALL (sysriscv, __err, 4, \ -+ RISCV_ATOMIC_CMPXCHG, mem, oldval, newval); \ -+ }) -+ -+#define __arch_compare_and_exchange_val_64_acq(mem, newval, oldval) \ -+ ({ \ -+ INTERNAL_SYSCALL_DECL (__err); \ -+ INTERNAL_SYSCALL (sysriscv, __err, 4, \ -+ RISCV_ATOMIC_CMPXCHG64, mem, oldval, newval); \ -+ }) -+ -+#endif /* __riscv_atomic */ -+ -+#endif /* bits/atomic.h */ -diff --git a/glibc-2.14.1/sysdeps/unix/sysv/linux/riscv/bits/endian.h b/glibc-2.14.1/sysdeps/unix/sysv/linux/riscv/bits/endian.h -new file mode 100644 -index 0000000..6caa0bd ---- /dev/null -+++ glibc-2.14.1/sysdeps/unix/sysv/linux/riscv/bits/endian.h -@@ -0,0 +1,16 @@ -+/* The MIPS architecture has selectable endianness. -+ Linux/MIPS exists in two both little and big endian flavours and we -+ want to be able to share the installed headerfiles between both, -+ so we define __BYTE_ORDER based on GCC's predefines. */ -+ -+#ifndef _ENDIAN_H -+# error "Never use directly; include instead." -+#endif -+ -+#ifdef __RISCVEB__ -+# define __BYTE_ORDER __BIG_ENDIAN -+#else -+# ifdef __RISCVEL__ -+# define __BYTE_ORDER __LITTLE_ENDIAN -+# endif -+#endif -diff --git a/glibc-2.14.1/sysdeps/unix/sysv/linux/riscv/bits/fcntl.h b/glibc-2.14.1/sysdeps/unix/sysv/linux/riscv/bits/fcntl.h -new file mode 100644 -index 0000000..d075e04 ---- /dev/null -+++ glibc-2.14.1/sysdeps/unix/sysv/linux/riscv/bits/fcntl.h -@@ -0,0 +1,278 @@ -+/* O_*, F_*, FD_* bit values for Linux. -+ Copyright (C) 1995, 1996, 1997, 1998, 2000, 2002, 2003, 2004, 2006, -+ 2007, 2009, 2010 Free Software Foundation, Inc. -+ This file is part of the GNU C Library. -+ -+ The GNU C Library is free software; you can redistribute it and/or -+ modify it under the terms of the GNU Lesser General Public -+ License as published by the Free Software Foundation; either -+ version 2.1 of the License, or (at your option) any later version. -+ -+ The GNU C Library is distributed in the hope that it will be useful, -+ but WITHOUT ANY WARRANTY; without even the implied warranty of -+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU -+ Lesser General Public License for more details. -+ -+ You should have received a copy of the GNU Lesser General Public -+ License along with the GNU C Library; if not, write to the Free -+ Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA -+ 02111-1307 USA. */ -+ -+#ifndef _FCNTL_H -+# error "Never use directly; include instead." -+#endif -+ -+#include -+#include -+#ifdef __USE_GNU -+# include -+#endif -+ -+ -+/* open/fcntl - O_SYNC is only implemented on blocks devices and on files -+ located on an ext2 file system */ -+#define O_ACCMODE 00000003 -+#define O_RDONLY 00000000 -+#define O_WRONLY 00000001 -+#define O_RDWR 00000002 -+#define O_CREAT 00000100 /* not fcntl */ -+#define O_EXCL 00000200 /* not fcntl */ -+#define O_NOCTTY 00000400 /* not fcntl */ -+#define O_TRUNC 00001000 /* not fcntl */ -+#define O_APPEND 00002000 -+#define O_NONBLOCK 00004000 -+#define O_DSYNC 00010000 /* used to be O_SYNC, see below */ -+#define O_DIRECT 00040000 /* direct disk access hint */ -+#define O_LARGEFILE 00100000 -+#define O_DIRECTORY 00200000 /* must be a directory */ -+#define O_NOFOLLOW 00400000 /* don't follow links */ -+#define O_NOATIME 01000000 -+#define O_CLOEXEC 02000000 /* set close_on_exec */ -+#define __O_SYNC 04000000 -+#define O_SYNC (__O_SYNC|O_DSYNC) -+#define O_PATH 010000000 -+#define O_NDELAY O_NONBLOCK -+ -+/* Values for the second argument to `fcntl'. */ -+#define F_DUPFD 0 /* dup */ -+#define F_GETFD 1 /* get close_on_exec */ -+#define F_SETFD 2 /* set/clear close_on_exec */ -+#define F_GETFL 3 /* get file->f_flags */ -+#define F_SETFL 4 /* set file->f_flags */ -+ -+#define F_GETLK64 33 /* Get record locking info. */ -+#define F_SETLK64 34 /* Set record locking info (non-blocking). */ -+#define F_SETLKW64 35 /* Set record locking info (blocking). */ -+ -+#if _RISCV_SIM == _ABI32 -+#define F_GETLK F_GETLK64 -+#define F_SETLK F_SETLK64 -+#define F_SETLKW F_SETLKW64 -+#else -+#define F_GETLK 5 -+#define F_SETLK 6 -+#define F_SETLKW 7 -+#endif -+ -+#define F_SETOWN 8 /* for sockets. */ -+#define F_GETOWN 9 /* for sockets. */ -+ -+#define F_SETSIG 10 /* for sockets. */ -+#define F_GETSIG 11 /* for sockets. */ -+#define F_SETOWN_EX 15 -+#define F_GETOWN_EX 16 -+ -+#ifdef __USE_GNU -+# define F_SETLEASE 1024 /* Set a lease. */ -+# define F_GETLEASE 1025 /* Enquire what lease is active. */ -+# define F_NOTIFY 1026 /* Request notfications on a directory. */ -+# define F_SETPIPE_SZ 1031 /* Set pipe page size array. */ -+# define F_GETPIPE_SZ 1032 /* Set pipe page size array. */ -+#endif -+#ifdef __USE_XOPEN2K8 -+# define F_DUPFD_CLOEXEC 1030 /* Duplicate file descriptor with -+ close-on-exit set. */ -+#endif -+ -+/* For F_[GET|SET]FD. */ -+#define FD_CLOEXEC 1 /* actually anything with low bit set goes */ -+ -+/* For posix fcntl() and `l_type' field of a `struct flock' for lockf(). */ -+#define F_RDLCK 0 /* Read lock. */ -+#define F_WRLCK 1 /* Write lock. */ -+#define F_UNLCK 2 /* Remove lock. */ -+ -+/* For old implementation of bsd flock(). */ -+#define F_EXLCK 4 /* or 3 */ -+#define F_SHLCK 8 /* or 4 */ -+ -+#ifdef __USE_BSD -+/* Operations for bsd flock(), also used by the kernel implementation. */ -+# define LOCK_SH 1 /* shared lock */ -+# define LOCK_EX 2 /* exclusive lock */ -+# define LOCK_NB 4 /* or'd with one of the above to prevent -+ blocking */ -+# define LOCK_UN 8 /* remove lock */ -+#endif -+ -+#ifdef __USE_GNU -+# define LOCK_MAND 32 /* This is a mandatory flock: */ -+# define LOCK_READ 64 /* ... which allows concurrent read operations. */ -+# define LOCK_WRITE 128 /* ... which allows concurrent write operations. */ -+# define LOCK_RW 192 /* ... Which allows concurrent read & write operations. */ -+#endif -+ -+#ifdef __USE_GNU -+/* Types of directory notifications that may be requested with F_NOTIFY. */ -+# define DN_ACCESS 0x00000001 /* File accessed. */ -+# define DN_MODIFY 0x00000002 /* File modified. */ -+# define DN_CREATE 0x00000004 /* File created. */ -+# define DN_DELETE 0x00000008 /* File removed. */ -+# define DN_RENAME 0x00000010 /* File renamed. */ -+# define DN_ATTRIB 0x00000020 /* File changed attibutes. */ -+# define DN_MULTISHOT 0x80000000 /* Don't remove notifier. */ -+#endif -+ -+struct flock -+ { -+ short int l_type; /* Type of lock: F_RDLCK, F_WRLCK, or F_UNLCK. */ -+ short int l_whence; /* Where `l_start' is relative to (like `lseek'). */ -+#ifndef __USE_FILE_OFFSET64 -+ __off_t l_start; /* Offset where the lock begins. */ -+ __off_t l_len; /* Size of the locked area; zero means until EOF. */ -+#if _RISCV_SIM != _ABI64 -+ /* The 64-bit flock structure, used by the n64 ABI, and for 64-bit -+ fcntls in o32 and n32, never has this field. */ -+ long int l_sysid; -+#endif -+#else -+ __off64_t l_start; /* Offset where the lock begins. */ -+ __off64_t l_len; /* Size of the locked area; zero means until EOF. */ -+#endif -+ __pid_t l_pid; /* Process holding the lock. */ -+#if ! defined __USE_FILE_OFFSET64 && _RISCV_SIM != _ABI64 -+ /* The 64-bit flock structure, used by the n64 ABI, and for 64-bit -+ flock in o32 and n32, never has this field. */ -+ long int pad[4]; -+#endif -+ }; -+typedef struct flock flock_t; -+ -+#ifdef __USE_LARGEFILE64 -+struct flock64 -+ { -+ short int l_type; /* Type of lock: F_RDLCK, F_WRLCK, or F_UNLCK. */ -+ short int l_whence; /* Where `l_start' is relative to (like `lseek'). */ -+ __off64_t l_start; /* Offset where the lock begins. */ -+ __off64_t l_len; /* Size of the locked area; zero means until EOF. */ -+ __pid_t l_pid; /* Process holding the lock. */ -+ }; -+#endif -+ -+#ifdef __USE_GNU -+/* Owner types. */ -+enum __pid_type -+ { -+ F_OWNER_TID = 0, /* Kernel thread. */ -+ F_OWNER_PID, /* Process. */ -+ F_OWNER_PGRP, /* Process group. */ -+ F_OWNER_GID = F_OWNER_PGRP /* Alternative, obsolete name. */ -+ }; -+ -+/* Structure to use with F_GETOWN_EX and F_SETOWN_EX. */ -+struct f_owner_ex -+ { -+ enum __pid_type type; /* Owner type of ID. */ -+ __pid_t pid; /* ID of owner. */ -+ }; -+#endif -+ -+/* Define some more compatibility macros to be backward compatible with -+ BSD systems which did not managed to hide these kernel macros. */ -+#ifdef __USE_BSD -+# define FAPPEND O_APPEND -+# define FFSYNC O_FSYNC -+# define FASYNC O_ASYNC -+# define FNONBLOCK O_NONBLOCK -+# define FNDELAY O_NDELAY -+#endif /* Use BSD. */ -+ -+/* Advise to `posix_fadvise'. */ -+#ifdef __USE_XOPEN2K -+# define POSIX_FADV_NORMAL 0 /* No further special treatment. */ -+# define POSIX_FADV_RANDOM 1 /* Expect random page references. */ -+# define POSIX_FADV_SEQUENTIAL 2 /* Expect sequential page references. */ -+# define POSIX_FADV_WILLNEED 3 /* Will need these pages. */ -+# define POSIX_FADV_DONTNEED 4 /* Don't need these pages. */ -+# define POSIX_FADV_NOREUSE 5 /* Data will be accessed once. */ -+#endif -+ -+ -+#ifdef __USE_GNU -+/* Flags for SYNC_FILE_RANGE. */ -+# define SYNC_FILE_RANGE_WAIT_BEFORE 1 /* Wait upon writeout of all pages -+ in the range before performing the -+ write. */ -+# define SYNC_FILE_RANGE_WRITE 2 /* Initiate writeout of all those -+ dirty pages in the range which are -+ not presently under writeback. */ -+# define SYNC_FILE_RANGE_WAIT_AFTER 4 /* Wait upon writeout of all pages in -+ the range after performing the -+ write. */ -+ -+/* Flags for SPLICE and VMSPLICE. */ -+# define SPLICE_F_MOVE 1 /* Move pages instead of copying. */ -+# define SPLICE_F_NONBLOCK 2 /* Don't block on the pipe splicing -+ (but we may still block on the fd -+ we splice from/to). */ -+# define SPLICE_F_MORE 4 /* Expect more data. */ -+# define SPLICE_F_GIFT 8 /* Pages passed in are a gift. */ -+#endif -+ -+__BEGIN_DECLS -+ -+#ifdef __USE_GNU -+ -+/* Provide kernel hint to read ahead. */ -+extern ssize_t readahead (int __fd, __off64_t __offset, size_t __count) -+ __THROW; -+ -+ -+/* Selective file content synch'ing. */ -+extern int sync_file_range (int __fd, __off64_t __offset, __off64_t __count, -+ unsigned int __flags); -+ -+ -+/* Splice address range into a pipe. */ -+extern ssize_t vmsplice (int __fdout, const struct iovec *__iov, -+ size_t __count, unsigned int __flags); -+ -+/* Splice two files together. */ -+extern ssize_t splice (int __fdin, __off64_t *__offin, int __fdout, -+ __off64_t *__offout, size_t __len, -+ unsigned int __flags); -+ -+/* In-kernel implementation of tee for pipe buffers. */ -+extern ssize_t tee (int __fdin, int __fdout, size_t __len, -+ unsigned int __flags); -+ -+/* Reserve storage for the data of the file associated with FD. */ -+# ifndef __USE_FILE_OFFSET64 -+extern int fallocate (int __fd, int __mode, __off_t __offset, __off_t __len); -+# else -+# ifdef __REDIRECT -+extern int __REDIRECT (fallocate, (int __fd, int __mode, __off64_t __offset, -+ __off64_t __len), -+ fallocate64); -+# else -+# define fallocate fallocate64 -+# endif -+# endif -+# ifdef __USE_LARGEFILE64 -+extern int fallocate64 (int __fd, int __mode, __off64_t __offset, -+ __off64_t __len); -+# endif -+ -+#endif -+ -+__END_DECLS -diff --git a/glibc-2.14.1/sysdeps/unix/sysv/linux/riscv/bits/mman.h b/glibc-2.14.1/sysdeps/unix/sysv/linux/riscv/bits/mman.h -new file mode 100644 -index 0000000..d67fa94 ---- /dev/null -+++ glibc-2.14.1/sysdeps/unix/sysv/linux/riscv/bits/mman.h -@@ -0,0 +1,112 @@ -+/* Definitions for POSIX memory map interface. Linux/MIPS version. -+ Copyright (C) 1997, 2000, 2003, 2004, 2005, 2006, 2009, 2011 -+ Free Software Foundation, Inc. -+ This file is part of the GNU C Library. -+ -+ The GNU C Library is free software; you can redistribute it and/or -+ modify it under the terms of the GNU Lesser General Public -+ License as published by the Free Software Foundation; either -+ version 2.1 of the License, or (at your option) any later version. -+ -+ The GNU C Library is distributed in the hope that it will be useful, -+ but WITHOUT ANY WARRANTY; without even the implied warranty of -+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU -+ Lesser General Public License for more details. -+ -+ You should have received a copy of the GNU Lesser General Public -+ License along with the GNU C Library; if not, write to the Free -+ Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA -+ 02111-1307 USA. */ -+ -+#ifndef _SYS_MMAN_H -+# error "Never use directly; include instead." -+#endif -+ -+/* The following definitions basically come from the kernel headers. -+ But the kernel header is not namespace clean. */ -+ -+ -+/* Protections are chosen from these bits, OR'd together. The -+ implementation does not necessarily support PROT_EXEC or PROT_WRITE -+ without PROT_READ. The only guarantees are that no writing will be -+ allowed without PROT_WRITE and no access will be allowed for PROT_NONE. */ -+ -+#define PROT_READ 0x1 /* Page can be read. */ -+#define PROT_WRITE 0x2 /* Page can be written. */ -+#define PROT_EXEC 0x4 /* Page can be executed. */ -+#define PROT_NONE 0x0 /* Page can not be accessed. */ -+#define PROT_GROWSDOWN 0x01000000 /* Extend change to start of -+ growsdown vma (mprotect only). */ -+#define PROT_GROWSUP 0x02000000 /* Extend change to start of -+ growsup vma (mprotect only). */ -+ -+/* Sharing types (must choose one and only one of these). */ -+#define MAP_SHARED 0x01 /* Share changes. */ -+#define MAP_PRIVATE 0x02 /* Changes are private. */ -+#ifdef __USE_MISC -+# define MAP_TYPE 0x0f /* Mask for type of mapping. */ -+#endif -+ -+/* Other flags. */ -+#define MAP_FIXED 0x10 /* Interpret addr exactly. */ -+#ifdef __USE_MISC -+# define MAP_FILE 0 -+# define MAP_ANONYMOUS 0x20 /* Don't use a file. */ -+# define MAP_ANON MAP_ANONYMOUS -+# define MAP_RENAME MAP_ANONYMOUS -+#endif -+ -+/* These are Linux-specific. */ -+#ifdef __USE_MISC -+# define MAP_GROWSDOWN 0x0100 /* stack-like segment */ -+# define MAP_DENYWRITE 0x0800 /* ETXTBSY */ -+# define MAP_EXECUTABLE 0x1000 /* mark it as an executable */ -+# define MAP_LOCKED 0x2000 /* pages are locked */ -+# define MAP_NORESERVE 0x4000 /* don't check for reservations */ -+# define MAP_POPULATE 0x8000 /* populate (prefault) pagetables */ -+# define MAP_NONBLOCK 0x10000 /* do not block on IO */ -+# define MAP_STACK 0x20000 /* give out an address that is best suited for process/thread stacks */ -+# define MAP_HUGETLB 0x40000 /* create a huge page mapping */ -+#endif -+ -+/* Flags to `msync'. */ -+#define MS_ASYNC 1 /* Sync memory asynchronously. */ -+#define MS_SYNC 4 /* Synchronous memory sync. */ -+#define MS_INVALIDATE 2 /* Invalidate the caches. */ -+ -+/* Flags for `mlockall'. */ -+#define MCL_CURRENT 1 /* Lock all currently mapped pages. */ -+#define MCL_FUTURE 2 /* Lock all additions to address -+ space. */ -+ -+/* Flags for `mremap'. */ -+#ifdef __USE_GNU -+# define MREMAP_MAYMOVE 1 -+# define MREMAP_FIXED 2 -+#endif -+ -+/* Advice to `madvise'. */ -+#ifdef __USE_BSD -+# define MADV_NORMAL 0 /* No further special treatment. */ -+# define MADV_RANDOM 1 /* Expect random page references. */ -+# define MADV_SEQUENTIAL 2 /* Expect sequential page references. */ -+# define MADV_WILLNEED 3 /* Will need these pages. */ -+# define MADV_DONTNEED 4 /* Don't need these pages. */ -+# define MADV_REMOVE 9 /* Remove these pages and resources. */ -+# define MADV_DONTFORK 10 /* Do not inherit across fork. */ -+# define MADV_DOFORK 11 /* Do inherit across fork. */ -+# define MADV_MERGEABLE 12 /* KSM may merge identical pages. */ -+# define MADV_UNMERGEABLE 13 /* KSM may not merge identical pages. */ -+# define MADV_HUGEPAGE 14 /* Worth backing with hugepages. */ -+# define MADV_NOHUGEPAGE 15 /* Not worth backing with hugepages. */ -+# define MADV_HWPOISON 100 /* Poison a page for testing. */ -+#endif -+ -+/* The POSIX people had to invent similar names for the same things. */ -+#ifdef __USE_XOPEN2K -+# define POSIX_MADV_NORMAL 0 /* No further special treatment. */ -+# define POSIX_MADV_RANDOM 1 /* Expect random page references. */ -+# define POSIX_MADV_SEQUENTIAL 2 /* Expect sequential page references. */ -+# define POSIX_MADV_WILLNEED 3 /* Will need these pages. */ -+# define POSIX_MADV_DONTNEED 4 /* Don't need these pages. */ -+#endif -diff --git a/glibc-2.14.1/sysdeps/unix/sysv/linux/riscv/bits/msq.h b/glibc-2.14.1/sysdeps/unix/sysv/linux/riscv/bits/msq.h -new file mode 100644 -index 0000000..422218a ---- /dev/null -+++ glibc-2.14.1/sysdeps/unix/sysv/linux/riscv/bits/msq.h -@@ -0,0 +1,83 @@ -+/* Copyright (C) 1995, 1996, 1997, 2000, 2002 Free Software Foundation, Inc. -+ This file is part of the GNU C Library. -+ -+ The GNU C Library is free software; you can redistribute it and/or -+ modify it under the terms of the GNU Lesser General Public -+ License as published by the Free Software Foundation; either -+ version 2.1 of the License, or (at your option) any later version. -+ -+ The GNU C Library is distributed in the hope that it will be useful, -+ but WITHOUT ANY WARRANTY; without even the implied warranty of -+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU -+ Lesser General Public License for more details. -+ -+ You should have received a copy of the GNU Lesser General Public -+ License along with the GNU C Library; if not, write to the Free -+ Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA -+ 02111-1307 USA. */ -+ -+#ifndef _SYS_MSG_H -+# error "Never use directly; include instead." -+#endif -+ -+#include -+#include -+ -+/* Define options for message queue functions. */ -+#define MSG_NOERROR 010000 /* no error if message is too big */ -+#ifdef __USE_GNU -+# define MSG_EXCEPT 020000 /* recv any msg except of specified type */ -+#endif -+ -+/* Types used in the structure definition. */ -+typedef unsigned long int msgqnum_t; -+typedef unsigned long int msglen_t; -+ -+/* Structure of record for one message inside the kernel. -+ The type `struct msg' is opaque. */ -+struct msqid_ds -+{ -+ struct ipc_perm msg_perm; /* structure describing operation permission */ -+ __time_t msg_stime; /* time of last msgsnd command */ -+#if __WORDSIZE == 32 -+ unsigned long int __unused1; -+#endif -+ __time_t msg_rtime; /* time of last msgrcv command */ -+#if __WORDSIZE == 32 -+ unsigned long int __unused2; -+#endif -+ __time_t msg_ctime; /* time of last change */ -+#if __WORDSIZE == 32 -+ unsigned long int __unused3; -+#endif -+ unsigned long int __msg_cbytes; /* current number of bytes on queue */ -+ msgqnum_t msg_qnum; /* number of messages currently on queue */ -+ msglen_t msg_qbytes; /* max number of bytes allowed on queue */ -+ __pid_t msg_lspid; /* pid of last msgsnd() */ -+ __pid_t msg_lrpid; /* pid of last msgrcv() */ -+ unsigned long int __unused4; -+ unsigned long int __unused5; -+}; -+ -+#ifdef __USE_MISC -+ -+# define msg_cbytes __msg_cbytes -+ -+/* ipcs ctl commands */ -+# define MSG_STAT 11 -+# define MSG_INFO 12 -+ -+/* buffer for msgctl calls IPC_INFO, MSG_INFO */ -+struct msginfo -+ { -+ int msgpool; -+ int msgmap; -+ int msgmax; -+ int msgmnb; -+ int msgmni; -+ int msgssz; -+ int msgtql; -+ unsigned short int msgseg; -+ }; -+ -+#endif /* __USE_MISC */ -diff --git a/glibc-2.14.1/sysdeps/unix/sysv/linux/riscv/bits/sem.h b/glibc-2.14.1/sysdeps/unix/sysv/linux/riscv/bits/sem.h -new file mode 100644 -index 0000000..6282de9 ---- /dev/null -+++ glibc-2.14.1/sysdeps/unix/sysv/linux/riscv/bits/sem.h -@@ -0,0 +1,85 @@ -+/* Copyright (C) 1995, 1996, 1997, 1998, 2000, 2001 Free Software Foundation, Inc. -+ This file is part of the GNU C Library. -+ -+ The GNU C Library is free software; you can redistribute it and/or -+ modify it under the terms of the GNU Lesser General Public -+ License as published by the Free Software Foundation; either -+ version 2.1 of the License, or (at your option) any later version. -+ -+ The GNU C Library is distributed in the hope that it will be useful, -+ but WITHOUT ANY WARRANTY; without even the implied warranty of -+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU -+ Lesser General Public License for more details. -+ -+ You should have received a copy of the GNU Lesser General Public -+ License along with the GNU C Library; if not, write to the Free -+ Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA -+ 02111-1307 USA. */ -+ -+#ifndef _SYS_SEM_H -+# error "Never include directly; use instead." -+#endif -+ -+#include -+ -+/* Flags for `semop'. */ -+#define SEM_UNDO 0x1000 /* undo the operation on exit */ -+ -+/* Commands for `semctl'. */ -+#define GETPID 11 /* get sempid */ -+#define GETVAL 12 /* get semval */ -+#define GETALL 13 /* get all semval's */ -+#define GETNCNT 14 /* get semncnt */ -+#define GETZCNT 15 /* get semzcnt */ -+#define SETVAL 16 /* set semval */ -+#define SETALL 17 /* set all semval's */ -+ -+ -+/* Data structure describing a set of semaphores. */ -+struct semid_ds -+{ -+ struct ipc_perm sem_perm; /* operation permission struct */ -+ __time_t sem_otime; /* last semop() time */ -+ __time_t sem_ctime; /* last time changed by semctl() */ -+ unsigned long int sem_nsems; /* number of semaphores in set */ -+ unsigned long int __unused1; -+ unsigned long int __unused2; -+}; -+ -+/* The user should define a union like the following to use it for arguments -+ for `semctl'. -+ -+ union semun -+ { -+ int val; <= value for SETVAL -+ struct semid_ds *buf; <= buffer for IPC_STAT & IPC_SET -+ unsigned short int *array; <= array for GETALL & SETALL -+ struct seminfo *__buf; <= buffer for IPC_INFO -+ }; -+ -+ Previous versions of this file used to define this union but this is -+ incorrect. One can test the macro _SEM_SEMUN_UNDEFINED to see whether -+ one must define the union or not. */ -+#define _SEM_SEMUN_UNDEFINED 1 -+ -+#ifdef __USE_MISC -+ -+/* ipcs ctl cmds */ -+# define SEM_STAT 18 -+# define SEM_INFO 19 -+ -+struct seminfo -+{ -+ int semmap; -+ int semmni; -+ int semmns; -+ int semmnu; -+ int semmsl; -+ int semopm; -+ int semume; -+ int semusz; -+ int semvmx; -+ int semaem; -+}; -+ -+#endif /* __USE_MISC */ -diff --git a/glibc-2.14.1/sysdeps/unix/sysv/linux/riscv/bits/sigcontext.h b/glibc-2.14.1/sysdeps/unix/sysv/linux/riscv/bits/sigcontext.h -new file mode 100644 -index 0000000..3e9d7f0 ---- /dev/null -+++ glibc-2.14.1/sysdeps/unix/sysv/linux/riscv/bits/sigcontext.h -@@ -0,0 +1,33 @@ -+/* Copyright (C) 1996, 1997, 1998, 2003, 2004, 2006 Free Software -+ Foundation, Inc. This file is part of the GNU C Library. -+ -+ The GNU C Library is free software; you can redistribute it and/or -+ modify it under the terms of the GNU Lesser General Public -+ License as published by the Free Software Foundation; either -+ version 2.1 of the License, or (at your option) any later version. -+ -+ The GNU C Library is distributed in the hope that it will be useful, -+ but WITHOUT ANY WARRANTY; without even the implied warranty of -+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU -+ Lesser General Public License for more details. -+ -+ You should have received a copy of the GNU Lesser General Public -+ License along with the GNU C Library; if not, write to the Free -+ Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA -+ 02111-1307 USA. */ -+ -+#ifndef _BITS_SIGCONTEXT_H -+#define _BITS_SIGCONTEXT_H 1 -+ -+#if !defined _SIGNAL_H && !defined _SYS_UCONTEXT_H -+# error "Never use directly; include instead." -+#endif -+ -+struct sigcontext { -+ /* gregs[0] holds the program counter. */ -+ unsigned long gregs[32]; -+ double fpregs[32]; -+ unsigned long fsr; -+}; -+ -+#endif -diff --git a/glibc-2.14.1/sysdeps/unix/sysv/linux/riscv/brk.c b/glibc-2.14.1/sysdeps/unix/sysv/linux/riscv/brk.c -new file mode 100644 -index 0000000..8201409 ---- /dev/null -+++ glibc-2.14.1/sysdeps/unix/sysv/linux/riscv/brk.c -@@ -0,0 +1,60 @@ -+/* brk system call for Linux/MIPS. -+ Copyright (C) 2000, 2005, 2006 Free Software Foundation, Inc. -+ This file is part of the GNU C Library. -+ -+ The GNU C Library is free software; you can redistribute it and/or -+ modify it under the terms of the GNU Lesser General Public -+ License as published by the Free Software Foundation; either -+ version 2.1 of the License, or (at your option) any later version. -+ -+ The GNU C Library is distributed in the hope that it will be useful, -+ but WITHOUT ANY WARRANTY; without even the implied warranty of -+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU -+ Lesser General Public License for more details. -+ -+ You should have received a copy of the GNU Lesser General Public -+ License along with the GNU C Library; if not, write to the Free -+ Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA -+ 02111-1307 USA. */ -+ -+#include -+#include -+#include -+ -+void *__curbrk = 0; -+ -+/* Old braindamage in GCC's crtstuff.c requires this symbol in an attempt -+ to work around different old braindamage in the old Linux/x86 ELF -+ dynamic linker. Sigh. */ -+weak_alias (__curbrk, ___brk_addr) -+ -+int -+__brk (void *addr) -+{ -+ void *newbrk; -+ -+ { -+ register long res asm ("v0"); -+ register void* arg asm ("a0"); -+ -+ res = SYS_ify (brk); -+ arg = addr; -+ -+ asm ("scall" /* Perform the system call. */ -+ : "+r" (res) -+ : "r" (arg) -+ : __SYSCALL_CLOBBERS); -+ -+ newbrk = (void *) res; -+ } -+ __curbrk = newbrk; -+ -+ if (newbrk < addr) -+ { -+ __set_errno (ENOMEM); -+ return -1; -+ } -+ -+ return 0; -+} -+weak_alias (__brk, brk) -diff --git a/glibc-2.14.1/sysdeps/unix/sysv/linux/riscv/clone.S b/glibc-2.14.1/sysdeps/unix/sysv/linux/riscv/clone.S -new file mode 100644 -index 0000000..67b2146 ---- /dev/null -+++ glibc-2.14.1/sysdeps/unix/sysv/linux/riscv/clone.S -@@ -0,0 +1,119 @@ -+/* Copyright (C) 1996, 1997, 2000, 2003, 2005 Free Software Foundation, Inc. -+ This file is part of the GNU C Library. -+ Contributed by Ralf Baechle , 1996. -+ -+ The GNU C Library is free software; you can redistribute it and/or -+ modify it under the terms of the GNU Lesser General Public -+ License as published by the Free Software Foundation; either -+ version 2.1 of the License, or (at your option) any later version. -+ -+ The GNU C Library is distributed in the hope that it will be useful, -+ but WITHOUT ANY WARRANTY; without even the implied warranty of -+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU -+ Lesser General Public License for more details. -+ -+ You should have received a copy of the GNU Lesser General Public -+ License along with the GNU C Library; if not, write to the Free -+ Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA -+ 02111-1307 USA. */ -+ -+/* clone() is even more special than fork() as it mucks with stacks -+ and invokes a function in the right context after its all over. */ -+ -+#include -+#include -+#define _ERRNO_H 1 -+#include -+#ifdef RESET_PID -+#include -+#include "tcb-offsets.h" -+#endif -+ -+#define CLONE_VM 0x00000100 -+#define CLONE_THREAD 0x00010000 -+ -+/* int clone(int (*fn)(void *arg), void *child_stack, int flags, void *arg, -+ void *parent_tidptr, void *tls, void *child_tidptr) */ -+ -+ .text -+LEAF(__clone) -+ -+ /* Sanity check arguments. */ -+ li v0,EINVAL -+ beqz a0,L(error) /* No NULL function pointers. */ -+ beqz a1,L(error) /* No NULL stack pointers. */ -+ -+ addi a1,a1,-32 /* Reserve argument save space. */ -+ REG_S a0,0(a1) /* Save function pointer. */ -+ REG_S a3,SZREG(a1) /* Save argument pointer. */ -+#ifdef RESET_PID -+ REG_S a2,(SZREG*2)(a1) /* Save clone flags. */ -+#endif -+ -+ move a0,a2 -+ -+ /* Shuffle in the last three arguments - arguments 5, 6, and 7 to -+ this function, but arguments 3, 4, and 5 to the syscall. */ -+ move a2,a4 -+ move a3,a5 -+ move a4,a6 -+ -+ /* Do the system call */ -+ li v0,__NR_clone -+ scall -+ -+ bltz v0,L(error) -+ beqz v0,L(thread_start) -+ -+ /* Successful return from the parent */ -+ ret -+ -+ /* Something bad happened -- no child created */ -+L(error): -+ j __syscall_error -+ END(__clone) -+ -+/* Load up the arguments to the function. Put this block of code in -+ its own function so that we can terminate the stack trace with our -+ debug info. */ -+ -+ENTRY(__thread_start) -+L(thread_start): -+ /* The stackframe has been created on entry of clone(). */ -+ -+#ifdef RESET_PID -+ /* Check and see if we need to reset the PID. */ -+ REG_L a0,(SZREG*2)(sp) -+ li a1,CLONE_THREAD -+ and a1,a0,a1 -+ beqz a1,L(restore_pid) -+L(donepid): -+#endif -+ -+ /* Restore the arg for user's function. */ -+ REG_L v0,0(sp) /* Function pointer. */ -+ REG_L a0,SZREG(sp) /* Argument pointer. */ -+ -+ /* Call the user's function. */ -+ jalr v0 -+ -+ /* Call _exit rather than doing it inline for breakpoint purposes. */ -+ move a0,v0 -+ j _exit -+ -+#ifdef RESET_PID -+L(restore_pid): -+ and a1,a0,CLONE_VM -+ li v0,-1 -+ bnez a1,L(gotpid) -+ li v0,__NR_getpid -+ scall -+L(gotpid): -+ sw v0,PID_OFFSET(tp) -+ sw v0,TID_OFFSET(tp) -+ b L(donepid) -+#endif -+ -+ END(__thread_start) -+ -+weak_alias (__clone, clone) -diff --git a/glibc-2.14.1/sysdeps/unix/sysv/linux/riscv/configure b/glibc-2.14.1/sysdeps/unix/sysv/linux/riscv/configure -new file mode 100644 -index 0000000..038022f ---- /dev/null -+++ glibc-2.14.1/sysdeps/unix/sysv/linux/riscv/configure -@@ -0,0 +1,28 @@ -+# This file is generated from configure.in by Autoconf. DO NOT EDIT! -+ # Local configure fragment for sysdeps/unix/sysv/linux/riscv. -+ -+case "$prefix" in -+/usr | /usr/) -+ # 32-bit libraries on bi-arch platforms go in /lib32 instead of /lib. -+ # Allow earlier configure scripts to handle libc_cv_slibdir, libdir, -+ # and libc_cv_localedir. -+ test -n "$libc_cv_slibdir" || \ -+ case $machine in -+ riscv/rv32* ) -+ libc_cv_slibdir="/lib32" -+ if test "$libdir" = '${exec_prefix}/lib'; then -+ libdir='${exec_prefix}/lib32'; -+ # Locale data can be shared between 32bit and 64bit libraries -+ libc_cv_localedir='${exec_prefix}/lib/locale' -+ fi -+ ;; -+ *) -+ libc_cv_slibdir="/lib" -+ ;; -+ esac -+esac -+ -+if test -z "$arch_minimum_kernel"; then -+ arch_minimum_kernel=2.4.1 -+ libc_cv_gcc_unwind_find_fde=no -+fi -diff --git a/glibc-2.14.1/sysdeps/unix/sysv/linux/riscv/configure.in b/glibc-2.14.1/sysdeps/unix/sysv/linux/riscv/configure.in -new file mode 100644 -index 0000000..87d0cd3 ---- /dev/null -+++ glibc-2.14.1/sysdeps/unix/sysv/linux/riscv/configure.in -@@ -0,0 +1,29 @@ -+sinclude(./aclocal.m4)dnl Autoconf lossage -+GLIBC_PROVIDES dnl See aclocal.m4 in the top level source directory. -+# Local configure fragment for sysdeps/unix/sysv/linux/riscv. -+ -+case "$prefix" in -+/usr | /usr/) -+ # 32-bit libraries on bi-arch platforms go in /lib32 instead of /lib. -+ # Allow earlier configure scripts to handle libc_cv_slibdir, libdir, -+ # and libc_cv_localedir. -+ test -n "$libc_cv_slibdir" || \ -+ case $machine in -+ riscv/rv32* ) -+ libc_cv_slibdir="/lib32" -+ if test "$libdir" = '${exec_prefix}/lib'; then -+ libdir='${exec_prefix}/lib32'; -+ # Locale data can be shared between 32bit and 64bit libraries -+ libc_cv_localedir='${exec_prefix}/lib/locale' -+ fi -+ ;; -+ *) -+ libc_cv_slibdir="/lib" -+ ;; -+ esac -+esac -+ -+if test -z "$arch_minimum_kernel"; then -+ arch_minimum_kernel=2.4.1 -+ libc_cv_gcc_unwind_find_fde=no -+fi -diff --git a/glibc-2.14.1/sysdeps/unix/sysv/linux/riscv/dl-cache.h b/glibc-2.14.1/sysdeps/unix/sysv/linux/riscv/dl-cache.h -new file mode 100644 -index 0000000..8ef4822 ---- /dev/null -+++ glibc-2.14.1/sysdeps/unix/sysv/linux/riscv/dl-cache.h -@@ -0,0 +1,45 @@ -+/* Support for reading /etc/ld.so.cache files written by Linux ldconfig. -+ Copyright (C) 2003, 2007 Free Software Foundation, Inc. -+ This file is part of the GNU C Library. -+ -+ The GNU C Library is free software; you can redistribute it and/or -+ modify it under the terms of the GNU Lesser General Public -+ License as published by the Free Software Foundation; either -+ version 2.1 of the License, or (at your option) any later version. -+ -+ The GNU C Library is distributed in the hope that it will be useful, -+ but WITHOUT ANY WARRANTY; without even the implied warranty of -+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU -+ Lesser General Public License for more details. -+ -+ You should have received a copy of the GNU Lesser General Public -+ License along with the GNU C Library; if not, write to the Free -+ Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA -+ 02111-1307 USA. */ -+ -+#include -+ -+#define add_system_dir(dir) \ -+ do \ -+ { \ -+ size_t len = strlen (dir); \ -+ char path[len + 3]; \ -+ memcpy (path, dir, len + 1); \ -+ if (len >= 6 \ -+ && (! memcmp (path + len - 6, "/lib64", 6) \ -+ || ! memcmp (path + len - 6, "/lib32", 6))) \ -+ { \ -+ len -= 2; \ -+ path[len] = '\0'; \ -+ } \ -+ add_dir (path); \ -+ if (len >= 4 && ! memcmp (path + len - 4, "/lib", 4)) \ -+ { \ -+ memcpy (path + len, "32", 3); \ -+ add_dir (path); \ -+ memcpy (path + len, "64", 3); \ -+ add_dir (path); \ -+ } \ -+ } while (0) -+ -+#include_next -diff --git a/glibc-2.14.1/sysdeps/unix/sysv/linux/riscv/dl-static.c b/glibc-2.14.1/sysdeps/unix/sysv/linux/riscv/dl-static.c -new file mode 100644 -index 0000000..3a99e7e ---- /dev/null -+++ glibc-2.14.1/sysdeps/unix/sysv/linux/riscv/dl-static.c -@@ -0,0 +1,92 @@ -+/* Variable initialization. MIPS version. -+ Copyright (C) 2001, 2002, 2003, 2005 Free Software Foundation, Inc. -+ This file is part of the GNU C Library. -+ -+ The GNU C Library is free software; you can redistribute it and/or -+ modify it under the terms of the GNU Lesser General Public -+ License as published by the Free Software Foundation; either -+ version 2.1 of the License, or (at your option) any later version. -+ -+ The GNU C Library is distributed in the hope that it will be useful, -+ but WITHOUT ANY WARRANTY; without even the implied warranty of -+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU -+ Lesser General Public License for more details. -+ -+ You should have received a copy of the GNU Lesser General Public -+ License along with the GNU C Library; if not, write to the Free -+ Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA -+ 02111-1307 USA. */ -+ -+#include -+ -+#ifdef SHARED -+ -+void -+_dl_var_init (void *array[]) -+{ -+ /* It has to match "variables" below. */ -+ enum -+ { -+ DL_PAGESIZE = 0 -+ }; -+ -+ GLRO(dl_pagesize) = *((size_t *) array[DL_PAGESIZE]); -+} -+ -+#else -+#include -+ -+__libc_lock_define_initialized_recursive (static, _dl_static_lock) -+ -+static void *variables[] = -+{ -+ &GLRO(dl_pagesize) -+}; -+ -+static void -+_dl_unprotect_relro (struct link_map *l) -+{ -+ ElfW(Addr) start = ((l->l_addr + l->l_relro_addr) -+ & ~(GLRO(dl_pagesize) - 1)); -+ ElfW(Addr) end = ((l->l_addr + l->l_relro_addr + l->l_relro_size) -+ & ~(GLRO(dl_pagesize) - 1)); -+ -+ if (start != end) -+ __mprotect ((void *) start, end - start, PROT_READ | PROT_WRITE); -+} -+ -+void -+_dl_static_init (struct link_map *l) -+{ -+ struct link_map *rtld_map = l; -+ struct r_scope_elem **scope; -+ const ElfW(Sym) *ref = NULL; -+ lookup_t loadbase; -+ void (*f) (void *[]); -+ size_t i; -+ -+ __libc_lock_lock_recursive (_dl_static_lock); -+ -+ loadbase = _dl_lookup_symbol_x ("_dl_var_init", l, &ref, l->l_local_scope, -+ NULL, 0, 1, NULL); -+ -+ for (scope = l->l_local_scope; *scope != NULL; scope++) -+ for (i = 0; i < (*scope)->r_nlist; i++) -+ if ((*scope)->r_list[i] == loadbase) -+ { -+ rtld_map = (*scope)->r_list[i]; -+ break; -+ } -+ -+ if (ref != NULL) -+ { -+ f = (void (*) (void *[])) DL_SYMBOL_ADDRESS (loadbase, ref); -+ _dl_unprotect_relro (rtld_map); -+ f (variables); -+ _dl_protect_relro (rtld_map); -+ } -+ -+ __libc_lock_unlock_recursive (_dl_static_lock); -+} -+ -+#endif -diff --git a/glibc-2.14.1/sysdeps/unix/sysv/linux/riscv/fcntl.c b/glibc-2.14.1/sysdeps/unix/sysv/linux/riscv/fcntl.c -new file mode 100644 -index 0000000..ea951bc ---- /dev/null -+++ glibc-2.14.1/sysdeps/unix/sysv/linux/riscv/fcntl.c -@@ -0,0 +1 @@ -+#include -diff --git a/glibc-2.14.1/sysdeps/unix/sysv/linux/riscv/ftruncate64.c b/glibc-2.14.1/sysdeps/unix/sysv/linux/riscv/ftruncate64.c -new file mode 100644 -index 0000000..a46e22f ---- /dev/null -+++ glibc-2.14.1/sysdeps/unix/sysv/linux/riscv/ftruncate64.c -@@ -0,0 +1,76 @@ -+/* Copyright (C) 1997,1998,1999,2000,2001,2002,2003,2005,2006 -+ Free Software Foundation, Inc. -+ This file is part of the GNU C Library. -+ -+ The GNU C Library is free software; you can redistribute it and/or -+ modify it under the terms of the GNU Lesser General Public -+ License as published by the Free Software Foundation; either -+ version 2.1 of the License, or (at your option) any later version. -+ -+ The GNU C Library is distributed in the hope that it will be useful, -+ but WITHOUT ANY WARRANTY; without even the implied warranty of -+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU -+ Lesser General Public License for more details. -+ -+ You should have received a copy of the GNU Lesser General Public -+ License along with the GNU C Library; if not, write to the Free -+ Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA -+ 02111-1307 USA. */ -+ -+#include -+#include -+#include -+#include -+ -+#include -+#include -+ -+#include -+ -+#ifdef __NR_ftruncate64 -+#ifndef __ASSUME_TRUNCATE64_SYSCALL -+/* The variable is shared between all wrappers around *truncate64 calls. */ -+extern int __have_no_truncate64; -+#endif -+ -+/* Truncate the file FD refers to to LENGTH bytes. */ -+int -+__ftruncate64 (int fd, off64_t length) -+{ -+#ifndef __ASSUME_TRUNCATE64_SYSCALL -+ if (! __have_no_truncate64) -+#endif -+ { -+ unsigned int low = length & 0xffffffff; -+ unsigned int high = length >> 32; -+#ifndef __ASSUME_TRUNCATE64_SYSCALL -+ int saved_errno = errno; -+#endif -+ int result = INLINE_SYSCALL (ftruncate64, 4, fd, 0, -+ __LONG_LONG_PAIR (high, low)); -+#ifndef __ASSUME_TRUNCATE64_SYSCALL -+ if (result != -1 || errno != ENOSYS) -+#endif -+ return result; -+ -+#ifndef __ASSUME_TRUNCATE64_SYSCALL -+ __set_errno (saved_errno); -+ __have_no_truncate64 = 1; -+#endif -+ } -+ -+#ifndef __ASSUME_TRUNCATE64_SYSCALL -+ if ((off_t) length != length) -+ { -+ __set_errno (EINVAL); -+ return -1; -+ } -+ return __ftruncate (fd, (off_t) length); -+#endif -+} -+weak_alias (__ftruncate64, ftruncate64) -+ -+#else -+/* Use the generic implementation. */ -+# include -+#endif -diff --git a/glibc-2.14.1/sysdeps/unix/sysv/linux/riscv/getcontext.S b/glibc-2.14.1/sysdeps/unix/sysv/linux/riscv/getcontext.S -new file mode 100644 -index 0000000..c849ddd ---- /dev/null -+++ glibc-2.14.1/sysdeps/unix/sysv/linux/riscv/getcontext.S -@@ -0,0 +1,86 @@ -+/* Save current context. -+ Copyright (C) 2009 Free Software Foundation, Inc. -+ This file is part of the GNU C Library. -+ Contributed by Maciej W. Rozycki . -+ -+ The GNU C Library is free software; you can redistribute it and/or -+ modify it under the terms of the GNU Lesser General Public -+ License as published by the Free Software Foundation; either -+ version 2.1 of the License, or (at your option) any later version. -+ -+ The GNU C Library is distributed in the hope that it will be useful, -+ but WITHOUT ANY WARRANTY; without even the implied warranty of -+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU -+ Lesser General Public License for more details. -+ -+ You should have received a copy of the GNU Lesser General Public -+ License along with the GNU C Library; if not, write to the Free -+ Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA -+ 02110-1301, USA. */ -+ -+#include -+#include -+ -+#include "ucontext_i.h" -+ -+/* int getcontext (ucontext_t *ucp) */ -+ -+ .text -+LEAF (__getcontext) -+ REG_S ra, MCONTEXT_PC(a0) -+ REG_S ra, ( 1 * SZREG + MCONTEXT_GREGS)(a0) -+ REG_S s0, ( 2 * SZREG + MCONTEXT_GREGS)(a0) -+ REG_S s1, ( 3 * SZREG + MCONTEXT_GREGS)(a0) -+ REG_S s2, ( 4 * SZREG + MCONTEXT_GREGS)(a0) -+ REG_S s3, ( 5 * SZREG + MCONTEXT_GREGS)(a0) -+ REG_S s4, ( 6 * SZREG + MCONTEXT_GREGS)(a0) -+ REG_S s5, ( 7 * SZREG + MCONTEXT_GREGS)(a0) -+ REG_S s6, ( 8 * SZREG + MCONTEXT_GREGS)(a0) -+ REG_S s7, ( 9 * SZREG + MCONTEXT_GREGS)(a0) -+ REG_S s8, (10 * SZREG + MCONTEXT_GREGS)(a0) -+ REG_S s9, (11 * SZREG + MCONTEXT_GREGS)(a0) -+ REG_S s10,(12 * SZREG + MCONTEXT_GREGS)(a0) -+ REG_S s11,(13 * SZREG + MCONTEXT_GREGS)(a0) -+ REG_S sp, (14 * SZREG + MCONTEXT_GREGS)(a0) -+ REG_S tp, (15 * SZREG + MCONTEXT_GREGS)(a0) -+ -+#ifdef __riscv_hard_float -+ frsr v1 -+ -+ fsd fs0, ( 0 * 8 + MCONTEXT_FPREGS)(a0) -+ fsd fs1, ( 1 * 8 + MCONTEXT_FPREGS)(a0) -+ fsd fs2, ( 2 * 8 + MCONTEXT_FPREGS)(a0) -+ fsd fs3, ( 3 * 8 + MCONTEXT_FPREGS)(a0) -+ fsd fs4, ( 4 * 8 + MCONTEXT_FPREGS)(a0) -+ fsd fs5, ( 5 * 8 + MCONTEXT_FPREGS)(a0) -+ fsd fs6, ( 6 * 8 + MCONTEXT_FPREGS)(a0) -+ fsd fs7, ( 7 * 8 + MCONTEXT_FPREGS)(a0) -+ fsd fs8, ( 8 * 8 + MCONTEXT_FPREGS)(a0) -+ fsd fs9, ( 9 * 8 + MCONTEXT_FPREGS)(a0) -+ fsd fs10,(10 * 8 + MCONTEXT_FPREGS)(a0) -+ fsd fs11,(11 * 8 + MCONTEXT_FPREGS)(a0) -+ fsd fs12,(12 * 8 + MCONTEXT_FPREGS)(a0) -+ fsd fs13,(13 * 8 + MCONTEXT_FPREGS)(a0) -+ fsd fs14,(14 * 8 + MCONTEXT_FPREGS)(a0) -+ fsd fs15,(15 * 8 + MCONTEXT_FPREGS)(a0) -+ -+ sw v1, MCONTEXT_FSR(a0) -+#endif /* __mips_hard_float */ -+ -+/* rt_sigprocmask (SIG_BLOCK, NULL, &ucp->uc_sigmask, _NSIG8) */ -+ li a3, _NSIG8 -+ add a2, a0, UCONTEXT_SIGMASK -+ move a1, zero -+ li a0, SIG_BLOCK -+ -+ li v0, SYS_ify (rt_sigprocmask) -+ scall -+ bltz v0, 99f -+ -+ ret -+ -+99: j __syscall_error -+ -+PSEUDO_END (__getcontext) -+ -+weak_alias (__getcontext, getcontext) -diff --git a/glibc-2.14.1/sysdeps/unix/sysv/linux/riscv/getmsg.c b/glibc-2.14.1/sysdeps/unix/sysv/linux/riscv/getmsg.c -new file mode 100644 -index 0000000..3a1fa08 ---- /dev/null -+++ glibc-2.14.1/sysdeps/unix/sysv/linux/riscv/getmsg.c -@@ -0,0 +1 @@ -+#include -diff --git a/glibc-2.14.1/sysdeps/unix/sysv/linux/riscv/getsysstats.c b/glibc-2.14.1/sysdeps/unix/sysv/linux/riscv/getsysstats.c -new file mode 100644 -index 0000000..8053033 ---- /dev/null -+++ glibc-2.14.1/sysdeps/unix/sysv/linux/riscv/getsysstats.c -@@ -0,0 +1,37 @@ -+/* Determine various system internal values, Linux/MIPS version. -+ Copyright (C) 2001, 2009 Free Software Foundation, Inc. -+ This file is part of the GNU C Library. -+ -+ The GNU C Library is free software; you can redistribute it and/or -+ modify it under the terms of the GNU Lesser General Public -+ License as published by the Free Software Foundation; either -+ version 2.1 of the License, or (at your option) any later version. -+ -+ The GNU C Library is distributed in the hope that it will be useful, -+ but WITHOUT ANY WARRANTY; without even the implied warranty of -+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU -+ Lesser General Public License for more details. -+ -+ You should have received a copy of the GNU Lesser General Public -+ License along with the GNU C Library; if not, write to the Free -+ Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA -+ 02111-1307 USA. */ -+ -+ -+/* We need to define a special parser for /proc/cpuinfo. */ -+#define GET_NPROCS_PARSER(FD, BUFFER, CP, RE, BUFFER_END, RESULT) \ -+ do \ -+ { \ -+ (RESULT) = 0; \ -+ /* Read all lines and count the lines starting with the string \ -+ "cpu model". We don't have to fear extremely long lines since \ -+ the kernel will not generate them. 8192 bytes are really \ -+ enough. */ \ -+ char *l; \ -+ while ((l = next_line (FD, BUFFER, &CP, &RE, BUFFER_END)) != NULL) \ -+ if (strncmp (l, "cpu model", 9) == 0) \ -+ ++(RESULT); \ -+ } \ -+ while (0) -+ -+#include -diff --git a/glibc-2.14.1/sysdeps/unix/sysv/linux/riscv/ipc_priv.h b/glibc-2.14.1/sysdeps/unix/sysv/linux/riscv/ipc_priv.h -new file mode 100644 -index 0000000..67883be ---- /dev/null -+++ glibc-2.14.1/sysdeps/unix/sysv/linux/riscv/ipc_priv.h -@@ -0,0 +1 @@ -+#include -diff --git a/glibc-2.14.1/sysdeps/unix/sysv/linux/riscv/kernel-features.h b/glibc-2.14.1/sysdeps/unix/sysv/linux/riscv/kernel-features.h -new file mode 100644 -index 0000000..151ed7c ---- /dev/null -+++ glibc-2.14.1/sysdeps/unix/sysv/linux/riscv/kernel-features.h -@@ -0,0 +1,41 @@ -+/* Set flags signalling availability of kernel features based on given -+ kernel version number. -+ Copyright (C) 1999-2003, 2004, 2005, 2006 Free Software Foundation, Inc. -+ This file is part of the GNU C Library. -+ -+ The GNU C Library is free software; you can redistribute it and/or -+ modify it under the terms of the GNU Lesser General Public -+ License as published by the Free Software Foundation; either -+ version 2.1 of the License, or (at your option) any later version. -+ -+ The GNU C Library is distributed in the hope that it will be useful, -+ but WITHOUT ANY WARRANTY; without even the implied warranty of -+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU -+ Lesser General Public License for more details. -+ -+ You should have received a copy of the GNU Lesser General Public -+ License along with the GNU C Library; if not, write to the Free -+ Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA -+ 02111-1307 USA. */ -+ -+#include -+ -+#if _RISCV_SIM == _ABIN32 -+# define __ASSUME_FCNTL64 1 -+#endif -+ -+#define __ASSUME_EVENTFD2 1 -+#define __ASSUME_SIGNALFD4 1 -+#define __ASSUME_CLONE_THREAD_FLAGS 1 -+#define __ASSUME_TGKILL 1 -+#define __ASSUME_UTIMES 1 -+#define __ASSUME_O_CLOEXEC 1 -+#define __ASSUME_SOCK_CLOEXEC 1 -+#define __ASSUME_IN_NONBLOCK 1 -+#define __ASSUME_PIPE2 1 -+#define __ASSUME_EVENTFD2 1 -+#define __ASSUME_SIGNALFD4 1 -+#define __ASSUME_DUP3 1 -+#define __ASSUME_ACCEPT4 1 -+ -+#include_next -diff --git a/glibc-2.14.1/sysdeps/unix/sysv/linux/riscv/kernel_rt_sigframe.h b/glibc-2.14.1/sysdeps/unix/sysv/linux/riscv/kernel_rt_sigframe.h -new file mode 100644 -index 0000000..edf8d45 ---- /dev/null -+++ glibc-2.14.1/sysdeps/unix/sysv/linux/riscv/kernel_rt_sigframe.h -@@ -0,0 +1,10 @@ -+/* Linux kernel RT signal frame. */ -+typedef struct kernel_rt_sigframe -+ { -+ uint32_t rs_ass[4]; -+ uint32_t rs_code[2]; -+ struct siginfo rs_info; -+ struct ucontext rs_uc; -+ uint32_t rs_altcode[8] __attribute__ ((__aligned__ (1 << 7))); -+ } -+kernel_rt_sigframe_t; -diff --git a/glibc-2.14.1/sysdeps/unix/sysv/linux/riscv/kernel_stat.h b/glibc-2.14.1/sysdeps/unix/sysv/linux/riscv/kernel_stat.h -new file mode 100644 -index 0000000..e898d21 ---- /dev/null -+++ glibc-2.14.1/sysdeps/unix/sysv/linux/riscv/kernel_stat.h -@@ -0,0 +1,66 @@ -+#ifndef __ASM_GENERIC_STAT_H -+#define __ASM_GENERIC_STAT_H -+ -+/* -+ * Everybody gets this wrong and has to stick with it for all -+ * eternity. Hopefully, this version gets used by new architectures -+ * so they don't fall into the same traps. -+ * -+ * stat64 is copied from powerpc64, with explicit padding added. -+ * stat is the same structure layout on 64-bit, without the 'long long' -+ * types. -+ * -+ * By convention, 64 bit architectures use the stat interface, while -+ * 32 bit architectures use the stat64 interface. Note that we don't -+ * provide an __old_kernel_stat here, which new architecture should -+ * not have to start with. -+ */ -+ -+#ifdef _RISCV_SIM == _ABI64 -+ -+#define STAT_HAVE_NSEC 1 -+ -+struct kernel_stat { -+ unsigned long st_dev; /* Device. */ -+ unsigned long st_ino; /* File serial number. */ -+ unsigned int st_mode; /* File mode. */ -+ unsigned int st_nlink; /* Link count. */ -+ unsigned int st_uid; /* User ID of the file's owner. */ -+ unsigned int st_gid; /* Group ID of the file's group. */ -+ unsigned long st_rdev; /* Device number, if device. */ -+ unsigned long __pad1; -+ long st_size; /* Size of file, in bytes. */ -+ int st_blksize; /* Optimal block size for I/O. */ -+ int __pad2; -+ long st_blocks; /* Number 512-byte blocks allocated. */ -+ struct timespec st_atim; -+ struct timespec st_mtim; -+ struct timespec st_ctim; -+ unsigned int __unused4; -+ unsigned int __unused5; -+}; -+ -+/* This matches struct stat64 in glibc2.1. Only used for 32 bit. */ -+#else -+struct kernel_stat { -+ unsigned long long st_dev; /* Device. */ -+ unsigned long long st_ino; /* File serial number. */ -+ unsigned int st_mode; /* File mode. */ -+ unsigned int st_nlink; /* Link count. */ -+ unsigned int st_uid; /* User ID of the file's owner. */ -+ unsigned int st_gid; /* Group ID of the file's group. */ -+ unsigned long long st_rdev; /* Device number, if device. */ -+ unsigned long long __pad1; -+ long long st_size; /* Size of file, in bytes. */ -+ int st_blksize; /* Optimal block size for I/O. */ -+ int __pad2; -+ long long st_blocks; /* Number 512-byte blocks allocated. */ -+ struct timespec st_atim; -+ struct timespec st_mtim; -+ struct timespec st_ctim; -+ unsigned int __unused4; -+ unsigned int __unused5; -+}; -+#endif -+ -+#endif /* __ASM_GENERIC_STAT_H */ -diff --git a/glibc-2.14.1/sysdeps/unix/sysv/linux/riscv/ldsodefs.h b/glibc-2.14.1/sysdeps/unix/sysv/linux/riscv/ldsodefs.h -new file mode 100644 -index 0000000..8d5efec ---- /dev/null -+++ glibc-2.14.1/sysdeps/unix/sysv/linux/riscv/ldsodefs.h -@@ -0,0 +1,33 @@ -+/* Run-time dynamic linker data structures for loaded ELF shared objects. MIPS. -+ Copyright (C) 2001, 2003 Free Software Foundation, Inc. -+ This file is part of the GNU C Library. -+ -+ The GNU C Library is free software; you can redistribute it and/or -+ modify it under the terms of the GNU Lesser General Public -+ License as published by the Free Software Foundation; either -+ version 2.1 of the License, or (at your option) any later version. -+ -+ The GNU C Library is distributed in the hope that it will be useful, -+ but WITHOUT ANY WARRANTY; without even the implied warranty of -+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU -+ Lesser General Public License for more details. -+ -+ You should have received a copy of the GNU Lesser General Public -+ License along with the GNU C Library; if not, write to the Free -+ Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA -+ 02111-1307 USA. */ -+ -+#ifndef _LDSODEFS_H -+ -+/* Get the real definitions. */ -+#include_next -+ -+/* Now define our stuff. */ -+ -+/* We need special support to initialize DSO loaded for statically linked -+ binaries. */ -+extern void _dl_static_init (struct link_map *map); -+#undef DL_STATIC_INIT -+#define DL_STATIC_INIT(map) _dl_static_init (map) -+ -+#endif /* ldsodefs.h */ -diff --git a/glibc-2.14.1/sysdeps/unix/sysv/linux/riscv/libc-abis b/glibc-2.14.1/sysdeps/unix/sysv/linux/riscv/libc-abis -new file mode 100644 -index 0000000..f180a03 ---- /dev/null -+++ glibc-2.14.1/sysdeps/unix/sysv/linux/riscv/libc-abis -@@ -0,0 +1,13 @@ -+# See the copy of this file in libc for detailed explanations. This -+# copy needs to include all libc definitions applicable to MIPS; only -+# one copy will be used. -+# -+# Feature Name Configuration -+# ------------ ------------- -+# -+# MIPS PLTs. -+MIPS_PLT mips*-*-linux* -+# -+# Unique symbol definitions for C++. -+# Architecture independent, all ELF targets (== all targets) -+UNIQUE -diff --git a/glibc-2.14.1/sysdeps/unix/sysv/linux/riscv/lockf64.c b/glibc-2.14.1/sysdeps/unix/sysv/linux/riscv/lockf64.c -new file mode 100644 -index 0000000..a88f5a7 ---- /dev/null -+++ glibc-2.14.1/sysdeps/unix/sysv/linux/riscv/lockf64.c -@@ -0,0 +1 @@ -+#include -diff --git a/glibc-2.14.1/sysdeps/unix/sysv/linux/riscv/makecontext.c b/glibc-2.14.1/sysdeps/unix/sysv/linux/riscv/makecontext.c -new file mode 100644 -index 0000000..a0f0304 ---- /dev/null -+++ glibc-2.14.1/sysdeps/unix/sysv/linux/riscv/makecontext.c -@@ -0,0 +1,43 @@ -+#include -+#include -+#include -+#include -+#include -+ -+void __makecontext (ucontext_t *ucp, void (*func) (void), int argc, -+ long a0, long a1, long a2, long a3, -+ long a4, ...) -+{ -+ extern void __start_context(void); -+ long i, sp; -+ va_list vl; -+ -+ va_start(vl, a4); -+ assert(REG_NARGS == 8); -+ -+ /* Set up the stack. */ -+ sp = ((long)ucp->uc_stack.ss_sp + ucp->uc_stack.ss_size) & ALMASK; -+ -+ /* Put args in a0-a7, then put any remaining args on the stack. */ -+ ucp->uc_mcontext.gregs[REG_A0 + 0] = a0; -+ ucp->uc_mcontext.gregs[REG_A0 + 1] = a1; -+ ucp->uc_mcontext.gregs[REG_A0 + 2] = a2; -+ ucp->uc_mcontext.gregs[REG_A0 + 3] = a3; -+ ucp->uc_mcontext.gregs[REG_A0 + 4] = a4; -+ if (__builtin_expect(argc > 5, 0)) -+ { -+ long reg_args = argc < REG_NARGS ? argc : REG_NARGS; -+ sp = (sp - (argc - reg_args) * sizeof(long)) & ALMASK; -+ for (i = 5; i < reg_args; i++) -+ ucp->uc_mcontext.gregs[REG_A0 + i] = va_arg(vl, long); -+ for (i = 0; i < argc - reg_args; i++) -+ ((long*)sp)[i] = va_arg(vl, long); -+ } -+ -+ ucp->uc_mcontext.gregs[REG_S0] = (long)ucp->uc_link; -+ ucp->uc_mcontext.gregs[REG_SP] = sp; -+ ucp->uc_mcontext.gregs[REG_PC] = (long)func; -+ ucp->uc_mcontext.gregs[REG_RA] = (long)&__start_context; -+} -+ -+weak_alias (__makecontext, makecontext) -diff --git a/glibc-2.14.1/sysdeps/unix/sysv/linux/riscv/nptl/bits/local_lim.h b/glibc-2.14.1/sysdeps/unix/sysv/linux/riscv/nptl/bits/local_lim.h -new file mode 100644 -index 0000000..c6fae63 ---- /dev/null -+++ glibc-2.14.1/sysdeps/unix/sysv/linux/riscv/nptl/bits/local_lim.h -@@ -0,0 +1,101 @@ -+/* Minimum guaranteed maximum values for system limits. MIPS Linux version. -+ Copyright (C) 1993-1998,2000,2002,2003,2004,2007,2008 -+ Free Software Foundation, Inc. -+ This file is part of the GNU C Library. -+ -+ The GNU C Library is free software; you can redistribute it and/or -+ modify it under the terms of the GNU Lesser General Public License as -+ published by the Free Software Foundation; either version 2.1 of the -+ License, or (at your option) any later version. -+ -+ The GNU C Library is distributed in the hope that it will be useful, -+ but WITHOUT ANY WARRANTY; without even the implied warranty of -+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU -+ Lesser General Public License for more details. -+ -+ You should have received a copy of the GNU Lesser General Public -+ License along with the GNU C Library; see the file COPYING.LIB. If not, -+ write to the Free Software Foundation, Inc., 59 Temple Place - Suite 330, -+ Boston, MA 02111-1307, USA. */ -+ -+/* The kernel header pollutes the namespace with the NR_OPEN symbol -+ and defines LINK_MAX although filesystems have different maxima. A -+ similar thing is true for OPEN_MAX: the limit can be changed at -+ runtime and therefore the macro must not be defined. Remove this -+ after including the header if necessary. */ -+#ifndef NR_OPEN -+# define __undef_NR_OPEN -+#endif -+#ifndef LINK_MAX -+# define __undef_LINK_MAX -+#endif -+#ifndef OPEN_MAX -+# define __undef_OPEN_MAX -+#endif -+#ifndef ARG_MAX -+# define __undef_ARG_MAX -+#endif -+ -+/* The kernel sources contain a file with all the needed information. */ -+#include -+ -+/* Have to remove NR_OPEN? */ -+#ifdef __undef_NR_OPEN -+# undef NR_OPEN -+# undef __undef_NR_OPEN -+#endif -+/* Have to remove LINK_MAX? */ -+#ifdef __undef_LINK_MAX -+# undef LINK_MAX -+# undef __undef_LINK_MAX -+#endif -+/* Have to remove OPEN_MAX? */ -+#ifdef __undef_OPEN_MAX -+# undef OPEN_MAX -+# undef __undef_OPEN_MAX -+#endif -+/* Have to remove ARG_MAX? */ -+#ifdef __undef_ARG_MAX -+# undef ARG_MAX -+# undef __undef_ARG_MAX -+#endif -+ -+/* The number of data keys per process. */ -+#define _POSIX_THREAD_KEYS_MAX 128 -+/* This is the value this implementation supports. */ -+#define PTHREAD_KEYS_MAX 1024 -+ -+/* Controlling the iterations of destructors for thread-specific data. */ -+#define _POSIX_THREAD_DESTRUCTOR_ITERATIONS 4 -+/* Number of iterations this implementation does. */ -+#define PTHREAD_DESTRUCTOR_ITERATIONS _POSIX_THREAD_DESTRUCTOR_ITERATIONS -+ -+/* The number of threads per process. */ -+#define _POSIX_THREAD_THREADS_MAX 64 -+/* We have no predefined limit on the number of threads. */ -+#undef PTHREAD_THREADS_MAX -+ -+/* Maximum amount by which a process can descrease its asynchronous I/O -+ priority level. */ -+#define AIO_PRIO_DELTA_MAX 20 -+ -+/* Minimum size for a thread. At least two pages with 64k pages. */ -+#define PTHREAD_STACK_MIN 131072 -+ -+/* Maximum number of timer expiration overruns. */ -+#define DELAYTIMER_MAX 2147483647 -+ -+/* Maximum tty name length. */ -+#define TTY_NAME_MAX 32 -+ -+/* Maximum login name length. This is arbitrary. */ -+#define LOGIN_NAME_MAX 256 -+ -+/* Maximum host name length. */ -+#define HOST_NAME_MAX 64 -+ -+/* Maximum message queue priority level. */ -+#define MQ_PRIO_MAX 32768 -+ -+/* Maximum value the semaphore can have. */ -+#define SEM_VALUE_MAX (2147483647) -diff --git a/glibc-2.14.1/sysdeps/unix/sysv/linux/riscv/nptl/bits/pthreadtypes.h b/glibc-2.14.1/sysdeps/unix/sysv/linux/riscv/nptl/bits/pthreadtypes.h -new file mode 100644 -index 0000000..97af317 ---- /dev/null -+++ glibc-2.14.1/sysdeps/unix/sysv/linux/riscv/nptl/bits/pthreadtypes.h -@@ -0,0 +1,233 @@ -+/* Machine-specific pthread type layouts. MIPS version. -+ Copyright (C) 2005, 2006 Free Software Foundation, Inc. -+ This file is part of the GNU C Library. -+ -+ The GNU C Library is free software; you can redistribute it and/or -+ modify it under the terms of the GNU Lesser General Public -+ License as published by the Free Software Foundation; either -+ version 2.1 of the License, or (at your option) any later version. -+ -+ The GNU C Library is distributed in the hope that it will be useful, -+ but WITHOUT ANY WARRANTY; without even the implied warranty of -+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU -+ Lesser General Public License for more details. -+ -+ You should have received a copy of the GNU Lesser General Public -+ License along with the GNU C Library; if not, write to the Free -+ Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA -+ 02111-1307 USA. */ -+ -+#ifndef _BITS_PTHREADTYPES_H -+#define _BITS_PTHREADTYPES_H 1 -+ -+#include -+ -+#if _RISCV_SIM == _ABI64 -+# define __SIZEOF_PTHREAD_ATTR_T 56 -+# define __SIZEOF_PTHREAD_MUTEX_T 40 -+# define __SIZEOF_PTHREAD_MUTEXATTR_T 4 -+# define __SIZEOF_PTHREAD_COND_T 48 -+# define __SIZEOF_PTHREAD_CONDATTR_T 4 -+# define __SIZEOF_PTHREAD_RWLOCK_T 56 -+# define __SIZEOF_PTHREAD_RWLOCKATTR_T 8 -+# define __SIZEOF_PTHREAD_BARRIER_T 32 -+# define __SIZEOF_PTHREAD_BARRIERATTR_T 4 -+#else -+# define __SIZEOF_PTHREAD_ATTR_T 36 -+# define __SIZEOF_PTHREAD_MUTEX_T 24 -+# define __SIZEOF_PTHREAD_MUTEXATTR_T 4 -+# define __SIZEOF_PTHREAD_COND_T 48 -+# define __SIZEOF_PTHREAD_CONDATTR_T 4 -+# define __SIZEOF_PTHREAD_RWLOCK_T 32 -+# define __SIZEOF_PTHREAD_RWLOCKATTR_T 8 -+# define __SIZEOF_PTHREAD_BARRIER_T 20 -+# define __SIZEOF_PTHREAD_BARRIERATTR_T 4 -+#endif -+ -+ -+/* Thread identifiers. The structure of the attribute type is -+ deliberately not exposed. */ -+typedef unsigned long int pthread_t; -+ -+ -+typedef union -+{ -+ char __size[__SIZEOF_PTHREAD_ATTR_T]; -+ long int __align; -+} pthread_attr_t; -+ -+ -+#if _RISCV_SIM == _ABI64 -+typedef struct __pthread_internal_list -+{ -+ struct __pthread_internal_list *__prev; -+ struct __pthread_internal_list *__next; -+} __pthread_list_t; -+#else -+typedef struct __pthread_internal_slist -+{ -+ struct __pthread_internal_slist *__next; -+} __pthread_slist_t; -+#endif -+ -+ -+/* Data structures for mutex handling. The structure of the attribute -+ type is deliberately not exposed. */ -+typedef union -+{ -+ struct __pthread_mutex_s -+ { -+ int __lock; -+ unsigned int __count; -+ int __owner; -+#if _RISCV_SIM == _ABI64 -+ unsigned int __nusers; -+#endif -+ /* KIND must stay at this position in the structure to maintain -+ binary compatibility. */ -+ int __kind; -+#if _RISCV_SIM == _ABI64 -+ int __spins; -+ __pthread_list_t __list; -+# define __PTHREAD_MUTEX_HAVE_PREV 1 -+#else -+ unsigned int __nusers; -+ __extension__ union -+ { -+ int __spins; -+ __pthread_slist_t __list; -+ }; -+#endif -+ } __data; -+ char __size[__SIZEOF_PTHREAD_MUTEX_T]; -+ long int __align; -+} pthread_mutex_t; -+ -+typedef union -+{ -+ char __size[__SIZEOF_PTHREAD_MUTEXATTR_T]; -+ int __align; -+} pthread_mutexattr_t; -+ -+ -+/* Data structure for conditional variable handling. The structure of -+ the attribute type is deliberately not exposed. */ -+typedef union -+{ -+ struct -+ { -+ int __lock; -+ unsigned int __futex; -+ __extension__ unsigned long long int __total_seq; -+ __extension__ unsigned long long int __wakeup_seq; -+ __extension__ unsigned long long int __woken_seq; -+ void *__mutex; -+ unsigned int __nwaiters; -+ unsigned int __broadcast_seq; -+ } __data; -+ char __size[__SIZEOF_PTHREAD_COND_T]; -+ __extension__ long long int __align; -+} pthread_cond_t; -+ -+typedef union -+{ -+ char __size[__SIZEOF_PTHREAD_CONDATTR_T]; -+ int __align; -+} pthread_condattr_t; -+ -+ -+/* Keys for thread-specific data */ -+typedef unsigned int pthread_key_t; -+ -+ -+/* Once-only execution */ -+typedef int pthread_once_t; -+ -+ -+#if defined __USE_UNIX98 || defined __USE_XOPEN2K -+/* Data structure for read-write lock variable handling. The -+ structure of the attribute type is deliberately not exposed. */ -+typedef union -+{ -+# if _RISCV_SIM == _ABI64 -+ struct -+ { -+ int __lock; -+ unsigned int __nr_readers; -+ unsigned int __readers_wakeup; -+ unsigned int __writer_wakeup; -+ unsigned int __nr_readers_queued; -+ unsigned int __nr_writers_queued; -+ int __writer; -+ int __shared; -+ unsigned long int __pad1; -+ unsigned long int __pad2; -+ /* FLAGS must stay at this position in the structure to maintain -+ binary compatibility. */ -+ unsigned int __flags; -+ } __data; -+# else -+ struct -+ { -+ int __lock; -+ unsigned int __nr_readers; -+ unsigned int __readers_wakeup; -+ unsigned int __writer_wakeup; -+ unsigned int __nr_readers_queued; -+ unsigned int __nr_writers_queued; -+#if __BYTE_ORDER == __BIG_ENDIAN -+ unsigned char __pad1; -+ unsigned char __pad2; -+ unsigned char __shared; -+ /* FLAGS must stay at this position in the structure to maintain -+ binary compatibility. */ -+ unsigned char __flags; -+#else -+ /* FLAGS must stay at this position in the structure to maintain -+ binary compatibility. */ -+ unsigned char __flags; -+ unsigned char __shared; -+ unsigned char __pad1; -+ unsigned char __pad2; -+#endif -+ int __writer; -+ } __data; -+# endif -+ char __size[__SIZEOF_PTHREAD_RWLOCK_T]; -+ long int __align; -+} pthread_rwlock_t; -+ -+typedef union -+{ -+ char __size[__SIZEOF_PTHREAD_RWLOCKATTR_T]; -+ long int __align; -+} pthread_rwlockattr_t; -+#endif -+ -+ -+#ifdef __USE_XOPEN2K -+/* POSIX spinlock data type. */ -+#ifdef __riscv_atomic -+typedef volatile int pthread_spinlock_t; -+#else -+typedef pthread_mutex_t pthread_spinlock_t; -+#endif -+ -+ -+/* POSIX barriers data type. The structure of the type is -+ deliberately not exposed. */ -+typedef union -+{ -+ char __size[__SIZEOF_PTHREAD_BARRIER_T]; -+ long int __align; -+} pthread_barrier_t; -+ -+typedef union -+{ -+ char __size[__SIZEOF_PTHREAD_BARRIERATTR_T]; -+ int __align; -+} pthread_barrierattr_t; -+#endif -+ -+ -+#endif /* bits/pthreadtypes.h */ -diff --git a/glibc-2.14.1/sysdeps/unix/sysv/linux/riscv/nptl/bits/semaphore.h b/glibc-2.14.1/sysdeps/unix/sysv/linux/riscv/nptl/bits/semaphore.h -new file mode 100644 -index 0000000..28f8595 ---- /dev/null -+++ glibc-2.14.1/sysdeps/unix/sysv/linux/riscv/nptl/bits/semaphore.h -@@ -0,0 +1,37 @@ -+/* Copyright (C) 2002, 2005, 2007 Free Software Foundation, Inc. -+ This file is part of the GNU C Library. -+ -+ The GNU C Library is free software; you can redistribute it and/or -+ modify it under the terms of the GNU Lesser General Public -+ License as published by the Free Software Foundation; either -+ version 2.1 of the License, or (at your option) any later version. -+ -+ The GNU C Library is distributed in the hope that it will be useful, -+ but WITHOUT ANY WARRANTY; without even the implied warranty of -+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU -+ Lesser General Public License for more details. -+ -+ You should have received a copy of the GNU Lesser General Public -+ License along with the GNU C Library; if not, write to the Free -+ Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA -+ 02111-1307 USA. */ -+ -+#ifndef _SEMAPHORE_H -+# error "Never use directly; include instead." -+#endif -+ -+#if _RISCV_SIM == _ABI64 -+# define __SIZEOF_SEM_T 32 -+#else -+# define __SIZEOF_SEM_T 16 -+#endif -+ -+/* Value returned if `sem_open' failed. */ -+#define SEM_FAILED ((sem_t *) 0) -+ -+ -+typedef union -+{ -+ char __size[__SIZEOF_SEM_T]; -+ long int __align; -+} sem_t; -diff --git a/glibc-2.14.1/sysdeps/unix/sysv/linux/riscv/nptl/clone.S b/glibc-2.14.1/sysdeps/unix/sysv/linux/riscv/nptl/clone.S -new file mode 100644 -index 0000000..4106a34 ---- /dev/null -+++ glibc-2.14.1/sysdeps/unix/sysv/linux/riscv/nptl/clone.S -@@ -0,0 +1,2 @@ -+#define RESET_PID -+#include -diff --git a/glibc-2.14.1/sysdeps/unix/sysv/linux/riscv/nptl/createthread.c b/glibc-2.14.1/sysdeps/unix/sysv/linux/riscv/nptl/createthread.c -new file mode 100644 -index 0000000..5b2234f ---- /dev/null -+++ glibc-2.14.1/sysdeps/unix/sysv/linux/riscv/nptl/createthread.c -@@ -0,0 +1,24 @@ -+/* Copyright (C) 2005 Free Software Foundation, Inc. -+ This file is part of the GNU C Library. -+ -+ The GNU C Library is free software; you can redistribute it and/or -+ modify it under the terms of the GNU Lesser General Public -+ License as published by the Free Software Foundation; either -+ version 2.1 of the License, or (at your option) any later version. -+ -+ The GNU C Library is distributed in the hope that it will be useful, -+ but WITHOUT ANY WARRANTY; without even the implied warranty of -+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU -+ Lesser General Public License for more details. -+ -+ You should have received a copy of the GNU Lesser General Public -+ License along with the GNU C Library; if not, write to the Free -+ Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA -+ 02111-1307 USA. */ -+ -+/* Value passed to 'clone' for initialization of the thread register. */ -+#define TLS_VALUE ((void *) (pd) \ -+ + TLS_TCB_OFFSET + TLS_PRE_TCB_SIZE) -+ -+/* Get the real implementation. */ -+#include -diff --git a/glibc-2.14.1/sysdeps/unix/sysv/linux/riscv/nptl/fork.c b/glibc-2.14.1/sysdeps/unix/sysv/linux/riscv/nptl/fork.c -new file mode 100644 -index 0000000..d31889e ---- /dev/null -+++ glibc-2.14.1/sysdeps/unix/sysv/linux/riscv/nptl/fork.c -@@ -0,0 +1 @@ -+#include -diff --git a/glibc-2.14.1/sysdeps/unix/sysv/linux/riscv/nptl/lowlevellock.h b/glibc-2.14.1/sysdeps/unix/sysv/linux/riscv/nptl/lowlevellock.h -new file mode 100644 -index 0000000..3d1916e ---- /dev/null -+++ glibc-2.14.1/sysdeps/unix/sysv/linux/riscv/nptl/lowlevellock.h -@@ -0,0 +1,263 @@ -+/* Copyright (C) 2003, 2004, 2005, 2006, 2007, 2008, -+ 2009 Free Software Foundation, Inc. -+ This file is part of the GNU C Library. -+ -+ The GNU C Library is free software; you can redistribute it and/or -+ modify it under the terms of the GNU Lesser General Public -+ License as published by the Free Software Foundation; either -+ version 2.1 of the License, or (at your option) any later version. -+ -+ The GNU C Library is distributed in the hope that it will be useful, -+ but WITHOUT ANY WARRANTY; without even the implied warranty of -+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU -+ Lesser General Public License for more details. -+ -+ You should have received a copy of the GNU Lesser General Public -+ License along with the GNU C Library; if not, write to the Free -+ Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA -+ 02111-1307 USA. */ -+ -+#ifndef _LOWLEVELLOCK_H -+#define _LOWLEVELLOCK_H 1 -+ -+#include -+#include -+#include -+#include -+#include -+#include -+ -+#define FUTEX_WAIT 0 -+#define FUTEX_WAKE 1 -+#define FUTEX_REQUEUE 3 -+#define FUTEX_CMP_REQUEUE 4 -+#define FUTEX_WAKE_OP 5 -+#define FUTEX_OP_CLEAR_WAKE_IF_GT_ONE ((4 << 24) | 1) -+#define FUTEX_LOCK_PI 6 -+#define FUTEX_UNLOCK_PI 7 -+#define FUTEX_TRYLOCK_PI 8 -+#define FUTEX_WAIT_BITSET 9 -+#define FUTEX_WAKE_BITSET 10 -+#define FUTEX_PRIVATE_FLAG 128 -+#define FUTEX_CLOCK_REALTIME 256 -+ -+#define FUTEX_BITSET_MATCH_ANY 0xffffffff -+ -+/* Values for 'private' parameter of locking macros. Yes, the -+ definition seems to be backwards. But it is not. The bit will be -+ reversed before passing to the system call. */ -+#define LLL_PRIVATE 0 -+#define LLL_SHARED FUTEX_PRIVATE_FLAG -+ -+ -+#if !defined NOT_IN_libc || defined IS_IN_rtld -+/* In libc.so or ld.so all futexes are private. */ -+# ifdef __ASSUME_PRIVATE_FUTEX -+# define __lll_private_flag(fl, private) \ -+ ((fl) | FUTEX_PRIVATE_FLAG) -+# else -+# define __lll_private_flag(fl, private) \ -+ ((fl) | THREAD_GETMEM (THREAD_SELF, header.private_futex)) -+# endif -+#else -+# ifdef __ASSUME_PRIVATE_FUTEX -+# define __lll_private_flag(fl, private) \ -+ (((fl) | FUTEX_PRIVATE_FLAG) ^ (private)) -+# else -+# define __lll_private_flag(fl, private) \ -+ (__builtin_constant_p (private) \ -+ ? ((private) == 0 \ -+ ? ((fl) | THREAD_GETMEM (THREAD_SELF, header.private_futex)) \ -+ : (fl)) \ -+ : ((fl) | (((private) ^ FUTEX_PRIVATE_FLAG) \ -+ & THREAD_GETMEM (THREAD_SELF, header.private_futex)))) -+# endif -+#endif -+ -+ -+#define lll_futex_wait(futexp, val, private) \ -+ lll_futex_timed_wait(futexp, val, NULL, private) -+ -+#define lll_futex_timed_wait(futexp, val, timespec, private) \ -+ ({ \ -+ INTERNAL_SYSCALL_DECL (__err); \ -+ long int __ret; \ -+ __ret = INTERNAL_SYSCALL (futex, __err, 4, (long) (futexp), \ -+ __lll_private_flag (FUTEX_WAIT, private), \ -+ (val), (timespec)); \ -+ INTERNAL_SYSCALL_ERROR_P (__ret, __err) ? -__ret : __ret; \ -+ }) -+ -+#define lll_futex_wake(futexp, nr, private) \ -+ ({ \ -+ INTERNAL_SYSCALL_DECL (__err); \ -+ long int __ret; \ -+ __ret = INTERNAL_SYSCALL (futex, __err, 4, (long) (futexp), \ -+ __lll_private_flag (FUTEX_WAKE, private), \ -+ (nr), 0); \ -+ INTERNAL_SYSCALL_ERROR_P (__ret, __err) ? -__ret : __ret; \ -+ }) -+ -+#define lll_robust_dead(futexv, private) \ -+ do \ -+ { \ -+ int *__futexp = &(futexv); \ -+ atomic_or (__futexp, FUTEX_OWNER_DIED); \ -+ lll_futex_wake (__futexp, 1, private); \ -+ } \ -+ while (0) -+ -+/* Returns non-zero if error happened, zero if success. */ -+#define lll_futex_requeue(futexp, nr_wake, nr_move, mutex, val, private) \ -+ ({ \ -+ INTERNAL_SYSCALL_DECL (__err); \ -+ long int __ret; \ -+ __ret = INTERNAL_SYSCALL (futex, __err, 6, (long) (futexp), \ -+ __lll_private_flag (FUTEX_CMP_REQUEUE, private),\ -+ (nr_wake), (nr_move), (mutex), (val)); \ -+ INTERNAL_SYSCALL_ERROR_P (__ret, __err); \ -+ }) -+ -+/* Returns non-zero if error happened, zero if success. */ -+#define lll_futex_wake_unlock(futexp, nr_wake, nr_wake2, futexp2, private) \ -+ ({ \ -+ INTERNAL_SYSCALL_DECL (__err); \ -+ long int __ret; \ -+ \ -+ __ret = INTERNAL_SYSCALL (futex, __err, 6, (futexp), \ -+ __lll_private_flag (FUTEX_WAKE_OP, private), \ -+ (nr_wake), (nr_wake2), (futexp2), \ -+ FUTEX_OP_CLEAR_WAKE_IF_GT_ONE); \ -+ INTERNAL_SYSCALL_ERROR_P (__ret, __err); \ -+ }) -+ -+#define lll_trylock(futex) \ -+ ({ \ -+ atomic_compare_and_exchange_val_acq (&(futex), 1, 0) != 0; \ -+ }) -+ -+#define lll_cond_trylock(futex) \ -+ ({ \ -+ atomic_compare_and_exchange_val_acq (&(futex), 2, 0) != 0; \ -+ }) -+ -+#define lll_robust_trylock(futex, id) \ -+ ({ \ -+ atomic_compare_and_exchange_val_acq (&(futex), id, 0) != 0; \ -+ }) -+ -+extern void __lll_lock_wait_private (int *futex) attribute_hidden; -+extern void __lll_lock_wait (int *futex, int private) attribute_hidden; -+extern int __lll_robust_lock_wait (int *futex, int private) attribute_hidden; -+ -+#define lll_lock(futex, private) \ -+ ({ \ -+ int val = atomic_compare_and_exchange_val_acq (&(futex), 1, 0); \ -+ \ -+ if (__builtin_expect (val != 0, 0)) \ -+ { \ -+ if (__builtin_constant_p (private) && private == LLL_PRIVATE) \ -+ __lll_lock_wait_private (&(futex)); \ -+ else \ -+ __lll_lock_wait (&(futex), private); \ -+ } \ -+ }) -+ -+#define lll_robust_lock(futex, id, private) \ -+ ({ \ -+ int result = 0; \ -+ if (atomic_compare_and_exchange_bool_acq (&(futex), id, 0) != 0) \ -+ result = __lll_robust_lock_wait (&(futex), private); \ -+ result; \ -+ }) -+ -+#define lll_cond_lock(futex, private) \ -+ ({ \ -+ int val = atomic_compare_and_exchange_val_acq (&(futex), 2, 0); \ -+ \ -+ if (__builtin_expect (val != 0, 0)) \ -+ __lll_lock_wait (&(futex), private); \ -+ }) -+ -+#define lll_robust_cond_lock(futex, id, private) \ -+ lll_robust_lock (futex, (id) | FUTEX_WAITERS, private) -+ -+ -+extern int __lll_timedlock_wait (int *futex, const struct timespec *, -+ int private) attribute_hidden; -+extern int __lll_robust_timedlock_wait (int *futex, const struct timespec *, -+ int private) attribute_hidden; -+ -+#define lll_timedlock(futex, abstime, private) \ -+ ({ \ -+ int val = atomic_compare_and_exchange_val_acq (&(futex), 1, 0); \ -+ int result = 0; \ -+ \ -+ if (__builtin_expect (val != 0, 0)) \ -+ result = __lll_timedlock_wait (&(futex), abstime, private); \ -+ result; \ -+ }) -+ -+#define lll_robust_timedlock(futex, abstime, id, private) \ -+ ({ \ -+ int result = 0; \ -+ if (atomic_compare_and_exchange_bool_acq (&(futex), id, 0) != 0) \ -+ result = __lll_robust_timedlock_wait (&(futex), abstime, private); \ -+ result; \ -+ }) -+ -+#define lll_unlock(lock, private) \ -+ ((void) ({ \ -+ int *__futex = &(lock); \ -+ int __val = atomic_exchange_rel (__futex, 0); \ -+ if (__builtin_expect (__val > 1, 0)) \ -+ lll_futex_wake (__futex, 1, private); \ -+ })) -+ -+#define lll_robust_unlock(lock, private) \ -+ ((void) ({ \ -+ int *__futex = &(lock); \ -+ int __val = atomic_exchange_rel (__futex, 0); \ -+ if (__builtin_expect (__val & FUTEX_WAITERS, 0)) \ -+ lll_futex_wake (__futex, 1, private); \ -+ })) -+ -+#define lll_islocked(futex) \ -+ (futex != 0) -+ -+ -+/* Our internal lock implementation is identical to the binary-compatible -+ mutex implementation. */ -+ -+/* Initializers for lock. */ -+#define LLL_LOCK_INITIALIZER (0) -+#define LLL_LOCK_INITIALIZER_LOCKED (1) -+ -+/* The states of a lock are: -+ 0 - untaken -+ 1 - taken by one user -+ >1 - taken by more users */ -+ -+/* The kernel notifies a process which uses CLONE_CLEARTID via futex -+ wakeup when the clone terminates. The memory location contains the -+ thread ID while the clone is running and is reset to zero -+ afterwards. */ -+#define lll_wait_tid(tid) \ -+ do { \ -+ __typeof (tid) __tid; \ -+ while ((__tid = (tid)) != 0) \ -+ lll_futex_wait (&(tid), __tid, LLL_SHARED); \ -+ } while (0) -+ -+extern int __lll_timedwait_tid (int *, const struct timespec *) -+ attribute_hidden; -+ -+#define lll_timedwait_tid(tid, abstime) \ -+ ({ \ -+ int __res = 0; \ -+ if ((tid) != 0) \ -+ __res = __lll_timedwait_tid (&(tid), (abstime)); \ -+ __res; \ -+ }) -+ -+#endif /* lowlevellock.h */ -diff --git a/glibc-2.14.1/sysdeps/unix/sysv/linux/riscv/nptl/pt-vfork.S b/glibc-2.14.1/sysdeps/unix/sysv/linux/riscv/nptl/pt-vfork.S -new file mode 100644 -index 0000000..1fdbb26 ---- /dev/null -+++ glibc-2.14.1/sysdeps/unix/sysv/linux/riscv/nptl/pt-vfork.S -@@ -0,0 +1,36 @@ -+/* Copyright (C) 2005, 2006 Free Software Foundation, Inc. -+ This file is part of the GNU C Library. -+ -+ The GNU C Library is free software; you can redistribute it and/or -+ modify it under the terms of the GNU Lesser General Public -+ License as published by the Free Software Foundation; either -+ version 2.1 of the License, or (at your option) any later version. -+ -+ The GNU C Library is distributed in the hope that it will be useful, -+ but WITHOUT ANY WARRANTY; without even the implied warranty of -+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU -+ Lesser General Public License for more details. -+ -+ You should have received a copy of the GNU Lesser General Public -+ License along with the GNU C Library; if not, write to the Free -+ Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA -+ 02111-1307 USA. */ -+ -+#include -+#include "tcb-offsets.h" -+ -+/* Save the PID value. */ -+#define SAVE_PID \ -+ lw t0, PID_OFFSET(tp); /* Load the saved PID. */ \ -+ neg t0, t0; /* Negate it. */ \ -+ sw t0, PID_OFFSET(tp); /* Store the temporary PID. */ -+ -+/* Restore the old PID value in the parent. */ -+#define RESTORE_PID \ -+ beqz v0, 1f; /* If we are the parent... */ \ -+ lw t0, PID_OFFSET(tp); /* Load the saved PID. */ \ -+ neg t0, t0; /* Re-negate it. */ \ -+ sw t0, PID_OFFSET(tp); /* Restore the PID. */ \ -+1: -+ -+#include -diff --git a/glibc-2.14.1/sysdeps/unix/sysv/linux/riscv/nptl/sysdep-cancel.h b/glibc-2.14.1/sysdeps/unix/sysv/linux/riscv/nptl/sysdep-cancel.h -new file mode 100644 -index 0000000..029b444 ---- /dev/null -+++ glibc-2.14.1/sysdeps/unix/sysv/linux/riscv/nptl/sysdep-cancel.h -@@ -0,0 +1,156 @@ -+/* Copyright (C) 2003, 2004, 2005, 2006 Free Software Foundation, Inc. -+ This file is part of the GNU C Library. -+ -+ The GNU C Library is free software; you can redistribute it and/or -+ modify it under the terms of the GNU Lesser General Public -+ License as published by the Free Software Foundation; either -+ version 2.1 of the License, or (at your option) any later version. -+ -+ The GNU C Library is distributed in the hope that it will be useful, -+ but WITHOUT ANY WARRANTY; without even the implied warranty of -+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU -+ Lesser General Public License for more details. -+ -+ You should have received a copy of the GNU Lesser General Public -+ License along with the GNU C Library; if not, write to the Free -+ Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA -+ 02111-1307 USA. */ -+ -+#include -+#include -+#include -+#ifndef __ASSEMBLER__ -+# include -+#endif -+#include -+ -+/* Gas will put the initial save of $gp into the CIE, because it appears to -+ happen before any instructions. So we use cfi_same_value instead of -+ cfi_restore. */ -+ -+#if !defined NOT_IN_libc || defined IS_IN_libpthread || defined IS_IN_librt -+ -+#ifdef __PIC__ -+# undef PSEUDO -+# define PSEUDO(name, syscall_name, args) \ -+ .align 2; \ -+ L(pseudo_start): \ -+ cfi_startproc; \ -+ cfi_adjust_cfa_offset (STKSPACE); \ -+ 99: RESTORESTK; \ -+ j __syscall_error; \ -+ .type __##syscall_name##_nocancel, @function; \ -+ .globl __##syscall_name##_nocancel; \ -+ __##syscall_name##_nocancel: \ -+ SAVESTK; \ -+ li v0, SYS_ify(syscall_name); \ -+ scall; \ -+ bltz v0, SYSCALL_ERROR_LABEL; \ -+ RESTORESTK; \ -+ ret; \ -+ .size __##syscall_name##_nocancel,.-__##syscall_name##_nocancel; \ -+ ENTRY (name) \ -+ SAVESTK; \ -+ SINGLE_THREAD_P(v1); \ -+ bnez v1, L(pseudo_cancel); \ -+ li v0, SYS_ify(syscall_name); \ -+ scall; \ -+ bltz v0, SYSCALL_ERROR_LABEL; \ -+ RESTORESTK; \ -+ ret; \ -+ L(pseudo_cancel): \ -+ cfi_adjust_cfa_offset (STKSPACE); \ -+ REG_S ra, STKOFF_RA(sp); \ -+ cfi_rel_offset (ra, STKOFF_RA); \ -+ PUSHARGS_##args; /* save syscall args */ \ -+ CENABLE; \ -+ REG_S v0, STKOFF_SVMSK(sp); /* save mask */ \ -+ POPARGS_##args; /* restore syscall args */ \ -+ li v0, SYS_ify (syscall_name); \ -+ scall; \ -+ REG_S v0, STKOFF_SC_V0(sp); /* save syscall result */ \ -+ REG_L a0, STKOFF_SVMSK(sp); /* pass mask as arg1 */ \ -+ CDISABLE; \ -+ REG_L v0, STKOFF_SC_V0(sp); /* restore syscall result */ \ -+ REG_L ra, STKOFF_RA(sp); /* restore return address */ \ -+ bltz v0, SYSCALL_ERROR_LABEL; \ -+ RESTORESTK; \ -+ L(pseudo_end): -+ -+ -+ # undef PSEUDO_END -+ # define PSEUDO_END(sym) cfi_endproc; .size sym,.-sym -+ -+ #endif -+ -+# define PUSHARGS_0 /* nothing to do */ -+# define PUSHARGS_1 PUSHARGS_0 REG_S a0, STKOFF_A0(sp); cfi_rel_offset (a0, STKOFF_A0); -+# define PUSHARGS_2 PUSHARGS_1 REG_S a1, STKOFF_A1(sp); cfi_rel_offset (a1, STKOFF_A1); -+# define PUSHARGS_3 PUSHARGS_2 REG_S a2, STKOFF_A2(sp); cfi_rel_offset (a2, STKOFF_A2); -+# define PUSHARGS_4 PUSHARGS_3 REG_S a3, STKOFF_A3(sp); cfi_rel_offset (a3, STKOFF_A3); -+# define PUSHARGS_5 PUSHARGS_4 REG_S a4, STKOFF_A4(sp); cfi_rel_offset (a3, STKOFF_A4); -+# define PUSHARGS_6 PUSHARGS_5 REG_S a5, STKOFF_A5(sp); cfi_rel_offset (a3, STKOFF_A5); -+ -+# define POPARGS_0 /* nothing to do */ -+# define POPARGS_1 POPARGS_0 REG_L a0, STKOFF_A0(sp); -+# define POPARGS_2 POPARGS_1 REG_L a1, STKOFF_A1(sp); -+# define POPARGS_3 POPARGS_2 REG_L a2, STKOFF_A2(sp); -+# define POPARGS_4 POPARGS_3 REG_L a3, STKOFF_A3(sp); -+# define POPARGS_5 POPARGS_4 REG_L a4, STKOFF_A4(sp); -+# define POPARGS_6 POPARGS_5 REG_L a5, STKOFF_A5(sp); -+ -+/* Save an even number of slots. Should be 0 if an even number of slots -+ are used below, or SZREG if an odd number are used. */ -+# define STK_PAD 0 -+ -+/* Place values that we are more likely to use later in this sequence, i.e. -+ closer to the SP at function entry. If you do that, the are more -+ likely to already be in your d-cache. */ -+# define STKOFF_A5 (STK_PAD) -+# define STKOFF_A4 (STKOFF_A5 + SZREG) -+# define STKOFF_A3 (STKOFF_A4 + SZREG) -+# define STKOFF_A2 (STKOFF_A3 + SZREG) /* MT and more args. */ -+# define STKOFF_A1 (STKOFF_A2 + SZREG) /* MT and 2 args. */ -+# define STKOFF_A0 (STKOFF_A1 + SZREG) /* MT and 1 arg. */ -+# define STKOFF_RA (STKOFF_A0 + SZREG) /* Used if MT. */ -+# define STKOFF_SC_V0 (STKOFF_RA + SZREG) /* Used if MT. */ -+# define STKOFF_SVMSK (STKOFF_SC_V0 + SZREG) /* Used if MT. */ -+ -+# define STKSPACE (STKOFF_SVMSK + SZREG) -+# define SAVESTK addi sp, sp, -STKSPACE; cfi_adjust_cfa_offset(STKSPACE) -+# define RESTORESTK addi sp, sp, STKSPACE; cfi_adjust_cfa_offset(-STKSPACE) -+ -+# ifdef IS_IN_libpthread -+# define CENABLE jal __pthread_enable_asynccancel -+# define CDISABLE jal __pthread_disable_asynccancel -+# elif defined IS_IN_librt -+# define CENABLE jal __librt_enable_asynccancel -+# define CDISABLE jal __librt_disable_asynccancel -+# else -+# define CENABLE jal __libc_enable_asynccancel -+# define CDISABLE jal __libc_disable_asynccancel -+# endif -+ -+# ifndef __ASSEMBLER__ -+# define SINGLE_THREAD_P \ -+ __builtin_expect (THREAD_GETMEM (THREAD_SELF, \ -+ header.multiple_threads) \ -+ == 0, 1) -+# else -+# include "tcb-offsets.h" -+# define SINGLE_THREAD_P(reg) \ -+ lw reg, MULTIPLE_THREADS_OFFSET(tp) -+#endif -+ -+#elif !defined __ASSEMBLER__ -+ -+# define SINGLE_THREAD_P 1 -+# define NO_CANCELLATION 1 -+ -+#endif -+ -+#ifndef __ASSEMBLER__ -+# define RTLD_SINGLE_THREAD_P \ -+ __builtin_expect (THREAD_GETMEM (THREAD_SELF, \ -+ header.multiple_threads) == 0, 1) -+#endif -diff --git a/glibc-2.14.1/sysdeps/unix/sysv/linux/riscv/nptl/vfork.S b/glibc-2.14.1/sysdeps/unix/sysv/linux/riscv/nptl/vfork.S -new file mode 100644 -index 0000000..7fabe8a ---- /dev/null -+++ glibc-2.14.1/sysdeps/unix/sysv/linux/riscv/nptl/vfork.S -@@ -0,0 +1,41 @@ -+/* Copyright (C) 2005, 2006 Free Software Foundation, Inc. -+ This file is part of the GNU C Library. -+ -+ The GNU C Library is free software; you can redistribute it and/or -+ modify it under the terms of the GNU Lesser General Public -+ License as published by the Free Software Foundation; either -+ version 2.1 of the License, or (at your option) any later version. -+ -+ The GNU C Library is distributed in the hope that it will be useful, -+ but WITHOUT ANY WARRANTY; without even the implied warranty of -+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU -+ Lesser General Public License for more details. -+ -+ You should have received a copy of the GNU Lesser General Public -+ License along with the GNU C Library; if not, write to the Free -+ Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA -+ 02111-1307 USA. */ -+ -+#include -+#include "tcb-offsets.h" -+ -+/* Save the PID value. */ -+#define SAVE_PID \ -+ lw t0, PID_OFFSET(tp); /* Load the saved PID. */ \ -+ neg t0, t0; /* Negate it. */ \ -+ bnez t0, 1f; /* If it was zero... */ \ -+ li t0, 0x80000000; /* use 0x80000000 instead. */ \ -+1: sw t0, PID_OFFSET(tp); /* Store the temporary PID. */ -+ -+/* Restore the old PID value in the parent. */ -+#define RESTORE_PID \ -+ beqz v0, 1f; /* If we are the parent... */ \ -+ lw t0, PID_OFFSET(tp); /* Load the saved PID. */ \ -+ neg t0, t0; /* Re-negate it. */ \ -+ li t1, 0x80000000; /* Load 0x80000000... */ \ -+ bne t0, t1, 2f; /* ... compare against it... */ \ -+ li t0, 0; /* ... use 0 instead. */ \ -+2: sw t0, PID_OFFSET(tp); /* Restore the PID. */ \ -+1: -+ -+#include -diff --git a/glibc-2.14.1/sysdeps/unix/sysv/linux/riscv/pipe.S b/glibc-2.14.1/sysdeps/unix/sysv/linux/riscv/pipe.S -new file mode 100644 -index 0000000..ed3af63 ---- /dev/null -+++ glibc-2.14.1/sysdeps/unix/sysv/linux/riscv/pipe.S -@@ -0,0 +1 @@ -+#include -diff --git a/glibc-2.14.1/sysdeps/unix/sysv/linux/riscv/pread.c b/glibc-2.14.1/sysdeps/unix/sysv/linux/riscv/pread.c -new file mode 100644 -index 0000000..a6a42d2 ---- /dev/null -+++ glibc-2.14.1/sysdeps/unix/sysv/linux/riscv/pread.c -@@ -0,0 +1,109 @@ -+/* Copyright (C) 1997, 1998, 2000, 2002, 2003, 2004 -+ Free Software Foundation, Inc. -+ This file is part of the GNU C Library. -+ Contributed by Ulrich Drepper , 1997. -+ -+ The GNU C Library is free software; you can redistribute it and/or -+ modify it under the terms of the GNU Lesser General Public -+ License as published by the Free Software Foundation; either -+ version 2.1 of the License, or (at your option) any later version. -+ -+ The GNU C Library is distributed in the hope that it will be useful, -+ but WITHOUT ANY WARRANTY; without even the implied warranty of -+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU -+ Lesser General Public License for more details. -+ -+ You should have received a copy of the GNU Lesser General Public -+ License along with the GNU C Library; if not, write to the Free -+ Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA -+ 02111-1307 USA. */ -+ -+#include -+#include -+#ifndef NO_SGIDEFS_H -+#include -+#endif -+#include -+#include -+ -+#include -+#include -+#include -+ -+#include -+ -+#ifdef __NR_pread64 /* Newer kernels renamed but it's the same. */ -+# ifdef __NR_pread -+# error "__NR_pread and __NR_pread64 both defined???" -+# endif -+# define __NR_pread __NR_pread64 -+#endif -+ -+#if defined __NR_pread || __ASSUME_PREAD_SYSCALL > 0 -+ -+# if __ASSUME_PREAD_SYSCALL == 0 -+static ssize_t __emulate_pread (int fd, void *buf, size_t count, -+ off_t offset) internal_function; -+# endif -+ -+ssize_t -+__libc_pread (fd, buf, count, offset) -+ int fd; -+ void *buf; -+ size_t count; -+ off_t offset; -+{ -+ ssize_t result; -+ -+#if _RISCV_SIM != _ABI64 -+ assert (sizeof (offset) == 4); -+#endif -+ -+ if (SINGLE_THREAD_P) -+ { -+ /* First try the syscall. */ -+#if _RISCV_SIM == _ABIN32 || _RISCV_SIM == _ABI64 -+ result = INLINE_SYSCALL (pread, 4, fd, CHECK_N (buf, count), count, -+ offset); -+#else -+ result = INLINE_SYSCALL (pread, 6, fd, CHECK_N (buf, count), count, 0, -+ __LONG_LONG_PAIR (offset >> 31, offset)); -+#endif -+# if __ASSUME_PREAD_SYSCALL == 0 -+ if (result == -1 && errno == ENOSYS) -+ /* No system call available. Use the emulation. */ -+ result = __emulate_pread (fd, buf, count, offset); -+# endif -+ return result; -+ } -+ -+ int oldtype = LIBC_CANCEL_ASYNC (); -+ -+ /* First try the syscall. */ -+#if _RISCV_SIM == _ABIN32 || _RISCV_SIM == _ABI64 -+ result = INLINE_SYSCALL (pread, 4, fd, CHECK_N (buf, count), count, offset); -+#else -+ result = INLINE_SYSCALL (pread, 6, fd, CHECK_N (buf, count), count, 0, -+ __LONG_LONG_PAIR (offset >> 31, offset)); -+#endif -+# if __ASSUME_PREAD_SYSCALL == 0 -+ if (result == -1 && errno == ENOSYS) -+ /* No system call available. Use the emulation. */ -+ result = __emulate_pread (fd, buf, count, offset); -+# endif -+ -+ LIBC_CANCEL_RESET (oldtype); -+ -+ return result; -+} -+ -+strong_alias (__libc_pread, __pread) -+weak_alias (__libc_pread, pread) -+ -+# define __libc_pread(fd, buf, count, offset) \ -+ static internal_function __emulate_pread (fd, buf, count, offset) -+#endif -+ -+#if __ASSUME_PREAD_SYSCALL == 0 -+# include -+#endif -diff --git a/glibc-2.14.1/sysdeps/unix/sysv/linux/riscv/pread64.c b/glibc-2.14.1/sysdeps/unix/sysv/linux/riscv/pread64.c -new file mode 100644 -index 0000000..03701b8 ---- /dev/null -+++ glibc-2.14.1/sysdeps/unix/sysv/linux/riscv/pread64.c -@@ -0,0 +1,107 @@ -+/* Copyright (C) 1997, 1998, 2000, 2002, 2003, 2004 -+ Free Software Foundation, Inc. -+ This file is part of the GNU C Library. -+ Contributed by Ulrich Drepper , 1997. -+ -+ The GNU C Library is free software; you can redistribute it and/or -+ modify it under the terms of the GNU Lesser General Public -+ License as published by the Free Software Foundation; either -+ version 2.1 of the License, or (at your option) any later version. -+ -+ The GNU C Library is distributed in the hope that it will be useful, -+ but WITHOUT ANY WARRANTY; without even the implied warranty of -+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU -+ Lesser General Public License for more details. -+ -+ You should have received a copy of the GNU Lesser General Public -+ License along with the GNU C Library; if not, write to the Free -+ Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA -+ 02111-1307 USA. */ -+ -+#include -+#ifndef NO_SGIDEFS_H -+#include -+#endif -+#include -+#include -+ -+#include -+#include -+#include -+ -+#include -+ -+#ifdef __NR_pread64 /* Newer kernels renamed but it's the same. */ -+# ifdef __NR_pread -+# error "__NR_pread and __NR_pread64 both defined???" -+# endif -+# define __NR_pread __NR_pread64 -+#endif -+ -+#if defined __NR_pread || __ASSUME_PREAD_SYSCALL > 0 -+ -+# if __ASSUME_PREAD_SYSCALL == 0 -+static ssize_t __emulate_pread64 (int fd, void *buf, size_t count, -+ off64_t offset) internal_function; -+# endif -+ -+ssize_t -+__libc_pread64 (fd, buf, count, offset) -+ int fd; -+ void *buf; -+ size_t count; -+ off64_t offset; -+{ -+ ssize_t result; -+ -+ -+ if (SINGLE_THREAD_P) -+ { -+ /* First try the syscall. */ -+#if _RISCV_SIM == _ABIN32 || _RISCV_SIM == _ABI64 -+ result = INLINE_SYSCALL (pread, 4, fd, CHECK_N (buf, count), count, -+ offset); -+#else -+ result = INLINE_SYSCALL (pread, 6, fd, CHECK_N (buf, count), count, 0, -+ __LONG_LONG_PAIR ((off_t) (offset >> 32), -+ (off_t) (offset & 0xffffffff))); -+#endif -+# if __ASSUME_PREAD_SYSCALL == 0 -+ if (result == -1 && errno == ENOSYS) -+ /* No system call available. Use the emulation. */ -+ result = __emulate_pread64 (fd, buf, count, offset); -+# endif -+ return result; -+ } -+ -+ int oldtype = LIBC_CANCEL_ASYNC (); -+ -+ /* First try the syscall. */ -+#if _RISCV_SIM == _ABIN32 || _RISCV_SIM == _ABI64 -+ result = INLINE_SYSCALL (pread, 4, fd, CHECK_N (buf, count), count, offset); -+#else -+ result = INLINE_SYSCALL (pread, 6, fd, CHECK_N (buf, count), count, 0, -+ __LONG_LONG_PAIR ((off_t) (offset >> 32), -+ (off_t) (offset & 0xffffffff))); -+#endif -+# if __ASSUME_PREAD_SYSCALL == 0 -+ if (result == -1 && errno == ENOSYS) -+ /* No system call available. Use the emulation. */ -+ result = __emulate_pread64 (fd, buf, count, offset); -+# endif -+ -+ LIBC_CANCEL_RESET (oldtype); -+ -+ return result; -+} -+ -+weak_alias (__libc_pread64, __pread64) -+weak_alias (__libc_pread64, pread64) -+ -+# define __libc_pread64(fd, buf, count, offset) \ -+ static internal_function __emulate_pread64 (fd, buf, count, offset) -+#endif -+ -+#if __ASSUME_PREAD_SYSCALL == 0 -+# include -+#endif -diff --git a/glibc-2.14.1/sysdeps/unix/sysv/linux/riscv/profil-counter.h b/glibc-2.14.1/sysdeps/unix/sysv/linux/riscv/profil-counter.h -new file mode 100644 -index 0000000..8a6a0bc ---- /dev/null -+++ glibc-2.14.1/sysdeps/unix/sysv/linux/riscv/profil-counter.h -@@ -0,0 +1,2 @@ -+/* We can use the ix86 version. */ -+#include -diff --git a/glibc-2.14.1/sysdeps/unix/sysv/linux/riscv/pthread_once.c b/glibc-2.14.1/sysdeps/unix/sysv/linux/riscv/pthread_once.c -new file mode 100644 -index 0000000..2a94504 ---- /dev/null -+++ glibc-2.14.1/sysdeps/unix/sysv/linux/riscv/pthread_once.c -@@ -0,0 +1 @@ -+#include -diff --git a/glibc-2.14.1/sysdeps/unix/sysv/linux/riscv/putmsg.c b/glibc-2.14.1/sysdeps/unix/sysv/linux/riscv/putmsg.c -new file mode 100644 -index 0000000..ebc1680 ---- /dev/null -+++ glibc-2.14.1/sysdeps/unix/sysv/linux/riscv/putmsg.c -@@ -0,0 +1 @@ -+#include -diff --git a/glibc-2.14.1/sysdeps/unix/sysv/linux/riscv/pwrite.c b/glibc-2.14.1/sysdeps/unix/sysv/linux/riscv/pwrite.c -new file mode 100644 -index 0000000..370262d ---- /dev/null -+++ glibc-2.14.1/sysdeps/unix/sysv/linux/riscv/pwrite.c -@@ -0,0 +1,109 @@ -+/* Copyright (C) 1997, 1998, 2000, 2002, 2003, 2004 -+ Free Software Foundation, Inc. -+ This file is part of the GNU C Library. -+ Contributed by Ulrich Drepper , 1997. -+ -+ The GNU C Library is free software; you can redistribute it and/or -+ modify it under the terms of the GNU Lesser General Public -+ License as published by the Free Software Foundation; either -+ version 2.1 of the License, or (at your option) any later version. -+ -+ The GNU C Library is distributed in the hope that it will be useful, -+ but WITHOUT ANY WARRANTY; without even the implied warranty of -+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU -+ Lesser General Public License for more details. -+ -+ You should have received a copy of the GNU Lesser General Public -+ License along with the GNU C Library; if not, write to the Free -+ Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA -+ 02111-1307 USA. */ -+ -+#include -+#include -+#ifndef NO_SGIDEFS_H -+#include -+#endif -+#include -+#include -+ -+#include -+#include -+#include -+ -+#include -+ -+#ifdef __NR_pwrite64 /* Newer kernels renamed but it's the same. */ -+# ifdef __NR_pwrite -+# error "__NR_pwrite and __NR_pwrite64 both defined???" -+# endif -+# define __NR_pwrite __NR_pwrite64 -+#endif -+ -+#if defined __NR_pwrite || __ASSUME_PWRITE_SYSCALL > 0 -+ -+# if __ASSUME_PWRITE_SYSCALL == 0 -+static ssize_t __emulate_pwrite (int fd, const void *buf, size_t count, -+ off_t offset) internal_function; -+# endif -+ -+ssize_t -+__libc_pwrite (fd, buf, count, offset) -+ int fd; -+ const void *buf; -+ size_t count; -+ off_t offset; -+{ -+ ssize_t result; -+ -+#if _RISCV_SIM != _ABI64 -+ assert (sizeof (offset) == 4); -+#endif -+ -+ if (SINGLE_THREAD_P) -+ { -+ /* First try the syscall. */ -+#if _RISCV_SIM == _ABIN32 || _RISCV_SIM == _ABI64 -+ result = INLINE_SYSCALL (pwrite, 4, fd, CHECK_N (buf, count), count, -+ offset); -+#else -+ result = INLINE_SYSCALL (pwrite, 6, fd, CHECK_N (buf, count), count, 0, -+ __LONG_LONG_PAIR (offset >> 31, offset)); -+#endif -+# if __ASSUME_PWRITE_SYSCALL == 0 -+ if (result == -1 && errno == ENOSYS) -+ /* No system call available. Use the emulation. */ -+ result = __emulate_pwrite (fd, buf, count, offset); -+# endif -+ return result; -+ } -+ -+ int oldtype = LIBC_CANCEL_ASYNC (); -+ -+ /* First try the syscall. */ -+#if _RISCV_SIM == _ABIN32 || _RISCV_SIM == _ABI64 -+ result = INLINE_SYSCALL (pwrite, 4, fd, CHECK_N (buf, count), count, offset); -+#else -+ result = INLINE_SYSCALL (pwrite, 6, fd, CHECK_N (buf, count), count, 0, -+ __LONG_LONG_PAIR (offset >> 31, offset)); -+#endif -+# if __ASSUME_PWRITE_SYSCALL == 0 -+ if (result == -1 && errno == ENOSYS) -+ /* No system call available. Use the emulation. */ -+ result = __emulate_pwrite (fd, buf, count, offset); -+# endif -+ -+ LIBC_CANCEL_RESET (oldtype); -+ -+ return result; -+} -+ -+strong_alias (__libc_pwrite, __pwrite) -+weak_alias (__libc_pwrite, pwrite) -+ -+# define __libc_pwrite(fd, buf, count, offset) \ -+ static internal_function __emulate_pwrite (fd, buf, count, offset) -+#endif -+ -+#if __ASSUME_PWRITE_SYSCALL == 0 -+# include -+#endif -diff --git a/glibc-2.14.1/sysdeps/unix/sysv/linux/riscv/pwrite64.c b/glibc-2.14.1/sysdeps/unix/sysv/linux/riscv/pwrite64.c -new file mode 100644 -index 0000000..edcaa23 ---- /dev/null -+++ glibc-2.14.1/sysdeps/unix/sysv/linux/riscv/pwrite64.c -@@ -0,0 +1,108 @@ -+/* Copyright (C) 1997, 1998, 2000, 2002, 2003, 2004 -+ Free Software Foundation, Inc. -+ This file is part of the GNU C Library. -+ Contributed by Ralf Baechle , 1998. -+ -+ The GNU C Library is free software; you can redistribute it and/or -+ modify it under the terms of the GNU Lesser General Public -+ License as published by the Free Software Foundation; either -+ version 2.1 of the License, or (at your option) any later version. -+ -+ The GNU C Library is distributed in the hope that it will be useful, -+ but WITHOUT ANY WARRANTY; without even the implied warranty of -+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU -+ Lesser General Public License for more details. -+ -+ You should have received a copy of the GNU Lesser General Public -+ License along with the GNU C Library; if not, write to the Free -+ Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA -+ 02111-1307 USA. */ -+ -+#include -+#ifndef NO_SGIDEFS_H -+#include -+#endif -+#include -+#include -+ -+#include -+#include -+#include -+ -+#include -+ -+#ifdef __NR_pwrite64 /* Newer kernels renamed but it's the same. */ -+# ifdef __NR_pwrite -+# error "__NR_pwrite and __NR_pwrite64 both defined???" -+# endif -+# define __NR_pwrite __NR_pwrite64 -+#endif -+ -+#if defined __NR_pwrite || __ASSUME_PWRITE_SYSCALL > 0 -+ -+# if __ASSUME_PWRITE_SYSCALL == 0 -+static ssize_t __emulate_pwrite64 (int fd, const void *buf, size_t count, -+ off64_t offset) internal_function; -+# endif -+ -+ssize_t -+__libc_pwrite64 (fd, buf, count, offset) -+ int fd; -+ const void *buf; -+ size_t count; -+ off64_t offset; -+{ -+ ssize_t result; -+ -+ if (SINGLE_THREAD_P) -+ { -+ /* First try the syscall. */ -+#if _RISCV_SIM == _ABIN32 || _RISCV_SIM == _ABI64 -+ result = INLINE_SYSCALL (pwrite, 4, fd, CHECK_N (buf, count), count, -+ offset); -+#else -+ result = INLINE_SYSCALL (pwrite, 6, fd, CHECK_N (buf, count), count, 0, -+ __LONG_LONG_PAIR ((off_t) (offset >> 32), -+ (off_t) (offset & 0xffffffff))); -+#endif -+# if __ASSUME_PWRITE_SYSCALL == 0 -+ if (result == -1 && errno == ENOSYS) -+ /* No system call available. Use the emulation. */ -+ result = __emulate_pwrite64 (fd, buf, count, offset); -+# endif -+ -+ return result; -+ } -+ -+ int oldtype = LIBC_CANCEL_ASYNC (); -+ -+ /* First try the syscall. */ -+#if _RISCV_SIM == _ABIN32 || _RISCV_SIM == _ABI64 -+ result = INLINE_SYSCALL (pwrite, 4, fd, CHECK_N (buf, count), count, offset); -+#else -+ result = INLINE_SYSCALL (pwrite, 6, fd, CHECK_N (buf, count), count, 0, -+ __LONG_LONG_PAIR ((off_t) (offset >> 32), -+ (off_t) (offset & 0xffffffff))); -+#endif -+# if __ASSUME_PWRITE_SYSCALL == 0 -+ if (result == -1 && errno == ENOSYS) -+ /* No system call available. Use the emulation. */ -+ result = __emulate_pwrite64 (fd, buf, count, offset); -+# endif -+ -+ LIBC_CANCEL_RESET (oldtype); -+ -+ return result; -+} -+ -+weak_alias (__libc_pwrite64, __pwrite64) -+libc_hidden_weak (__pwrite64) -+weak_alias (__libc_pwrite64, pwrite64) -+ -+# define __libc_pwrite64(fd, buf, count, offset) \ -+ static internal_function __emulate_pwrite64 (fd, buf, count, offset) -+#endif -+ -+#if __ASSUME_PWRITE_SYSCALL == 0 -+# include -+#endif -diff --git a/glibc-2.14.1/sysdeps/unix/sysv/linux/riscv/register-dump.h b/glibc-2.14.1/sysdeps/unix/sysv/linux/riscv/register-dump.h -new file mode 100644 -index 0000000..2b1ec56 ---- /dev/null -+++ glibc-2.14.1/sysdeps/unix/sysv/linux/riscv/register-dump.h -@@ -0,0 +1,65 @@ -+/* Dump registers. -+ Copyright (C) 2000, 2001, 2002, 2006 Free Software Foundation, Inc. -+ This file is part of the GNU C Library. -+ Contributed by Andreas Jaeger , 2000. -+ -+ The GNU C Library is free software; you can redistribute it and/or -+ modify it under the terms of the GNU Lesser General Public -+ License as published by the Free Software Foundation; either -+ version 2.1 of the License, or (at your option) any later version. -+ -+ The GNU C Library is distributed in the hope that it will be useful, -+ but WITHOUT ANY WARRANTY; without even the implied warranty of -+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU -+ Lesser General Public License for more details. -+ -+ You should have received a copy of the GNU Lesser General Public -+ License along with the GNU C Library; if not, write to the Free -+ Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA -+ 02111-1307 USA. */ -+ -+#include -+#include -+#include -+ -+static void -+hexvalue (unsigned long int value, char *buf, size_t len) -+{ -+ char *cp = _itoa_word (value, buf + len, 16, 0); -+ while (cp > buf) -+ *--cp = '0'; -+} -+ -+#define REGDUMP_NREGS 32 -+#define REGDUMP_PER_LINE (80 / (__WORDSIZE/4 + 4)) -+ -+static void -+register_dump (int fd, struct ucontext *ctx) -+{ -+ int i; -+ char regvalue[__WORDSIZE/4 + 1]; -+ char str[82 * ((REGDUMP_NREGS + REGDUMP_PER_LINE - 1) / REGDUMP_PER_LINE)]; -+ -+ static const char names[REGDUMP_NREGS][4] = { -+ "pc", "ra", "s0", "s1", "s2", "s3", "s4", "s5", -+ "s6", "s7", "s8", "s9", "sA", "sB", "sp", "tp", -+ "v0", "v1", "a0", "a1", "a2", "a3", "a4", "a5", -+ "a6", "a7", "t0", "t1", "t2", "t3", "t4", "gp" -+ }; -+ -+ str[0] = 0; -+ for (i = 0; i < REGDUMP_NREGS; i++) -+ { -+ strcat (str, names[i]); -+ strcat (str, " "); -+ hexvalue (ctx->uc_mcontext.gregs[i], regvalue, __WORDSIZE/4); -+ strcat (str, regvalue); -+ -+ if ((i + 1) % REGDUMP_PER_LINE == 0) -+ strcat (str, "\n"); -+ } -+ -+ write (fd, str, strlen (str)); -+} -+ -+#define REGISTER_DUMP register_dump (fd, ctx) -diff --git a/glibc-2.14.1/sysdeps/unix/sysv/linux/riscv/rv32/accept4.c b/glibc-2.14.1/sysdeps/unix/sysv/linux/riscv/rv32/accept4.c -new file mode 100644 -index 0000000..98a41f9 ---- /dev/null -+++ glibc-2.14.1/sysdeps/unix/sysv/linux/riscv/rv32/accept4.c -@@ -0,0 +1,32 @@ -+/* Copyright (C) 2008, 2009 Free Software Foundation, Inc. -+ This file is part of the GNU C Library. -+ -+ The GNU C Library is free software; you can redistribute it and/or -+ modify it under the terms of the GNU Lesser General Public -+ License as published by the Free Software Foundation; either -+ version 2.1 of the License, or (at your option) any later version. -+ -+ The GNU C Library is distributed in the hope that it will be useful, -+ but WITHOUT ANY WARRANTY; without even the implied warranty of -+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU -+ Lesser General Public License for more details. -+ -+ You should have received a copy of the GNU Lesser General Public -+ License along with the GNU C Library; if not, write to the Free -+ Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA -+ 02111-1307 USA. */ -+ -+/* Avoid accept4.c trying to use a definition based on the socketcall -+ syscall and internal_accept4.S. */ -+ -+#include -+#include -+#include -+ -+#include -+#include -+#include -+ -+#undef __NR_socketcall -+ -+#include -diff --git a/glibc-2.14.1/sysdeps/unix/sysv/linux/riscv/rv32/fxstatat.c b/glibc-2.14.1/sysdeps/unix/sysv/linux/riscv/rv32/fxstatat.c -new file mode 100644 -index 0000000..0f8b313 ---- /dev/null -+++ glibc-2.14.1/sysdeps/unix/sysv/linux/riscv/rv32/fxstatat.c -@@ -0,0 +1 @@ -+#include -diff --git a/glibc-2.14.1/sysdeps/unix/sysv/linux/riscv/rv32/internal_accept4.S b/glibc-2.14.1/sysdeps/unix/sysv/linux/riscv/rv32/internal_accept4.S -new file mode 100644 -index 0000000..30434d7 ---- /dev/null -+++ glibc-2.14.1/sysdeps/unix/sysv/linux/riscv/rv32/internal_accept4.S -@@ -0,0 +1,2 @@ -+/* MIPS does not have socket.S and the socketcall syscall should -+ generally be avoided, though it exists. */ -diff --git a/glibc-2.14.1/sysdeps/unix/sysv/linux/riscv/rv32/internal_recvmmsg.S b/glibc-2.14.1/sysdeps/unix/sysv/linux/riscv/rv32/internal_recvmmsg.S -new file mode 100644 -index 0000000..30434d7 ---- /dev/null -+++ glibc-2.14.1/sysdeps/unix/sysv/linux/riscv/rv32/internal_recvmmsg.S -@@ -0,0 +1,2 @@ -+/* MIPS does not have socket.S and the socketcall syscall should -+ generally be avoided, though it exists. */ -diff --git a/glibc-2.14.1/sysdeps/unix/sysv/linux/riscv/rv32/posix_fadvise.c b/glibc-2.14.1/sysdeps/unix/sysv/linux/riscv/rv32/posix_fadvise.c -new file mode 100644 -index 0000000..04c952d ---- /dev/null -+++ glibc-2.14.1/sysdeps/unix/sysv/linux/riscv/rv32/posix_fadvise.c -@@ -0,0 +1,42 @@ -+/* Copyright (C) 2007 Free Software Foundation, Inc. -+ This file is part of the GNU C Library. -+ -+ The GNU C Library is free software; you can redistribute it and/or -+ modify it under the terms of the GNU Lesser General Public -+ License as published by the Free Software Foundation; either -+ version 2.1 of the License, or (at your option) any later version. -+ -+ The GNU C Library is distributed in the hope that it will be useful, -+ but WITHOUT ANY WARRANTY; without even the implied warranty of -+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU -+ Lesser General Public License for more details. -+ -+ You should have received a copy of the GNU Lesser General Public -+ License along with the GNU C Library; if not, write to the Free -+ Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA -+ 02111-1307 USA. */ -+ -+#include -+#include -+#include -+ -+/* Advice the system about the expected behaviour of the application with -+ respect to the file associated with FD. */ -+ -+int -+posix_fadvise (int fd, off_t offset, off_t len, int advise) -+{ -+/* MIPS kernel only has NR_fadvise64 which acts as NR_fadvise64_64 */ -+#ifdef __NR_fadvise64 -+ INTERNAL_SYSCALL_DECL (err); -+ int ret = INTERNAL_SYSCALL (fadvise64, err, 7, fd, 0, -+ __LONG_LONG_PAIR (offset >> 31, offset), -+ __LONG_LONG_PAIR (len >> 31, len), -+ advise); -+ if (INTERNAL_SYSCALL_ERROR_P (ret, err)) -+ return INTERNAL_SYSCALL_ERRNO (ret, err); -+ return 0; -+#else -+ return ENOSYS; -+#endif -+} -diff --git a/glibc-2.14.1/sysdeps/unix/sysv/linux/riscv/rv32/posix_fadvise64.c b/glibc-2.14.1/sysdeps/unix/sysv/linux/riscv/rv32/posix_fadvise64.c -new file mode 100644 -index 0000000..715d37e ---- /dev/null -+++ glibc-2.14.1/sysdeps/unix/sysv/linux/riscv/rv32/posix_fadvise64.c -@@ -0,0 +1,61 @@ -+/* Copyright (C) 2007 Free Software Foundation, Inc. -+ This file is part of the GNU C Library. -+ -+ The GNU C Library is free software; you can redistribute it and/or -+ modify it under the terms of the GNU Lesser General Public -+ License as published by the Free Software Foundation; either -+ version 2.1 of the License, or (at your option) any later version. -+ -+ The GNU C Library is distributed in the hope that it will be useful, -+ but WITHOUT ANY WARRANTY; without even the implied warranty of -+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU -+ Lesser General Public License for more details. -+ -+ You should have received a copy of the GNU Lesser General Public -+ License along with the GNU C Library; if not, write to the Free -+ Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA -+ 02111-1307 USA. */ -+ -+#include -+#include -+#include -+ -+/* Advice the system about the expected behaviour of the application with -+ respect to the file associated with FD. */ -+ -+int -+__posix_fadvise64_l64 (int fd, off64_t offset, off64_t len, int advise) -+{ -+/* MIPS kernel only has NR_fadvise64 which acts as NR_fadvise64_64 */ -+#ifdef __NR_fadvise64 -+ INTERNAL_SYSCALL_DECL (err); -+ int ret = INTERNAL_SYSCALL (fadvise64, err, 7, fd, 0, -+ __LONG_LONG_PAIR ((long) (offset >> 32), -+ (long) offset), -+ __LONG_LONG_PAIR ((long) (len >> 32), -+ (long) len), -+ advise); -+ if (INTERNAL_SYSCALL_ERROR_P (ret, err)) -+ return INTERNAL_SYSCALL_ERRNO (ret, err); -+ return 0; -+#else -+ return ENOSYS; -+#endif -+} -+ -+#include -+ -+#if SHLIB_COMPAT(libc, GLIBC_2_2, GLIBC_2_3_3) -+ -+int -+attribute_compat_text_section -+__posix_fadvise64_l32 (int fd, off64_t offset, size_t len, int advise) -+{ -+ return __posix_fadvise64_l64 (fd, offset, len, advise); -+} -+ -+versioned_symbol (libc, __posix_fadvise64_l64, posix_fadvise64, GLIBC_2_3_3); -+compat_symbol (libc, __posix_fadvise64_l32, posix_fadvise64, GLIBC_2_2); -+#else -+strong_alias (__posix_fadvise64_l64, posix_fadvise64); -+#endif -diff --git a/glibc-2.14.1/sysdeps/unix/sysv/linux/riscv/rv32/readahead.c b/glibc-2.14.1/sysdeps/unix/sysv/linux/riscv/rv32/readahead.c -new file mode 100644 -index 0000000..b5b967c ---- /dev/null -+++ glibc-2.14.1/sysdeps/unix/sysv/linux/riscv/rv32/readahead.c -@@ -0,0 +1 @@ -+#include -diff --git a/glibc-2.14.1/sysdeps/unix/sysv/linux/riscv/rv32/recvmmsg.c b/glibc-2.14.1/sysdeps/unix/sysv/linux/riscv/rv32/recvmmsg.c -new file mode 100644 -index 0000000..ceb88ee ---- /dev/null -+++ glibc-2.14.1/sysdeps/unix/sysv/linux/riscv/rv32/recvmmsg.c -@@ -0,0 +1,31 @@ -+/* Copyright (C) 2010 Free Software Foundation, Inc. -+ This file is part of the GNU C Library. -+ -+ The GNU C Library is free software; you can redistribute it and/or -+ modify it under the terms of the GNU Lesser General Public -+ License as published by the Free Software Foundation; either -+ version 2.1 of the License, or (at your option) any later version. -+ -+ The GNU C Library is distributed in the hope that it will be useful, -+ but WITHOUT ANY WARRANTY; without even the implied warranty of -+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU -+ Lesser General Public License for more details. -+ -+ You should have received a copy of the GNU Lesser General Public -+ License along with the GNU C Library; if not, write to the Free -+ Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA -+ 02111-1307 USA. */ -+ -+/* Avoid recvmmsg.c trying to use a definition based on the socketcall -+ syscall and internal_recvmmsg.S. */ -+ -+#include -+#include -+ -+#include -+#include -+#include -+ -+#undef __NR_socketcall -+ -+#include -diff --git a/glibc-2.14.1/sysdeps/unix/sysv/linux/riscv/rv32/sync_file_range.c b/glibc-2.14.1/sysdeps/unix/sysv/linux/riscv/rv32/sync_file_range.c -new file mode 100644 -index 0000000..13a21b0 ---- /dev/null -+++ glibc-2.14.1/sysdeps/unix/sysv/linux/riscv/rv32/sync_file_range.c -@@ -0,0 +1,47 @@ -+/* Selective file content synch'ing. -+ Copyright (C) 2006, 2007 Free Software Foundation, Inc. -+ This file is part of the GNU C Library. -+ -+ The GNU C Library is free software; you can redistribute it and/or -+ modify it under the terms of the GNU Lesser General Public -+ License as published by the Free Software Foundation; either -+ version 2.1 of the License, or (at your option) any later version. -+ -+ The GNU C Library is distributed in the hope that it will be useful, -+ but WITHOUT ANY WARRANTY; without even the implied warranty of -+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU -+ Lesser General Public License for more details. -+ -+ You should have received a copy of the GNU Lesser General Public -+ License along with the GNU C Library; if not, write to the Free -+ Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA -+ 02111-1307 USA. */ -+ -+#include -+#include -+#include -+ -+#include -+#include -+ -+ -+#ifdef __NR_sync_file_range -+int -+sync_file_range (int fd, __off64_t from, __off64_t to, unsigned int flags) -+{ -+ return INLINE_SYSCALL (sync_file_range, 7, fd, 0, -+ __LONG_LONG_PAIR ((long) (from >> 32), (long) from), -+ __LONG_LONG_PAIR ((long) (to >> 32), (long) to), -+ flags); -+} -+#else -+int -+sync_file_range (int fd, __off64_t from, __off64_t to, unsigned int flags) -+{ -+ __set_errno (ENOSYS); -+ return -1; -+} -+stub_warning (sync_file_range) -+ -+# include -+#endif -diff --git a/glibc-2.14.1/sysdeps/unix/sysv/linux/riscv/rv32/syscalls.list b/glibc-2.14.1/sysdeps/unix/sysv/linux/riscv/rv32/syscalls.list -new file mode 100644 -index 0000000..f357b5c ---- /dev/null -+++ glibc-2.14.1/sysdeps/unix/sysv/linux/riscv/rv32/syscalls.list -@@ -0,0 +1,5 @@ -+# File name Caller Syscall name # args Strong name Weak names -+ -+prlimit64 EXTRA prlimit64 i:iipp prlimit64 -+ -+fanotify_mark EXTRA fanotify_mark i:iiiiis fanotify_mark -diff --git a/glibc-2.14.1/sysdeps/unix/sysv/linux/riscv/rv64/Makefile b/glibc-2.14.1/sysdeps/unix/sysv/linux/riscv/rv64/Makefile -new file mode 100644 -index 0000000..0a37c5b ---- /dev/null -+++ glibc-2.14.1/sysdeps/unix/sysv/linux/riscv/rv64/Makefile -@@ -0,0 +1,9 @@ -+ifeq ($(subdir),socket) -+CFLAGS-recv.c += -fexceptions -+CFLAGS-send.c += -fexceptions -+endif -+ -+ifeq ($(subdir),nptl) -+CFLAGS-recv.c += -fexceptions -+CFLAGS-send.c += -fexceptions -+endif -diff --git a/glibc-2.14.1/sysdeps/unix/sysv/linux/riscv/rv64/fallocate.c b/glibc-2.14.1/sysdeps/unix/sysv/linux/riscv/rv64/fallocate.c -new file mode 100644 -index 0000000..d3b7218 ---- /dev/null -+++ glibc-2.14.1/sysdeps/unix/sysv/linux/riscv/rv64/fallocate.c -@@ -0,0 +1 @@ -+#include -diff --git a/glibc-2.14.1/sysdeps/unix/sysv/linux/riscv/rv64/fallocate64.c b/glibc-2.14.1/sysdeps/unix/sysv/linux/riscv/rv64/fallocate64.c -new file mode 100644 -index 0000000..fb2b681 ---- /dev/null -+++ glibc-2.14.1/sysdeps/unix/sysv/linux/riscv/rv64/fallocate64.c -@@ -0,0 +1 @@ -+/* fallocate64 is in fallocate.c */ -diff --git a/glibc-2.14.1/sysdeps/unix/sysv/linux/riscv/rv64/glob64.c b/glibc-2.14.1/sysdeps/unix/sysv/linux/riscv/rv64/glob64.c -new file mode 100644 -index 0000000..33918ea ---- /dev/null -+++ glibc-2.14.1/sysdeps/unix/sysv/linux/riscv/rv64/glob64.c -@@ -0,0 +1 @@ -+/* glob64 is in glob.c */ -diff --git a/glibc-2.14.1/sysdeps/unix/sysv/linux/riscv/rv64/ldconfig.h b/glibc-2.14.1/sysdeps/unix/sysv/linux/riscv/rv64/ldconfig.h -new file mode 100644 -index 0000000..43fca83 ---- /dev/null -+++ glibc-2.14.1/sysdeps/unix/sysv/linux/riscv/rv64/ldconfig.h -@@ -0,0 +1,26 @@ -+/* Copyright (C) 2001, 2002, 2003 Free Software Foundation, Inc. -+ This file is part of the GNU C Library. -+ -+ The GNU C Library is free software; you can redistribute it and/or -+ modify it under the terms of the GNU Lesser General Public -+ License as published by the Free Software Foundation; either -+ version 2.1 of the License, or (at your option) any later version. -+ -+ The GNU C Library is distributed in the hope that it will be useful, -+ but WITHOUT ANY WARRANTY; without even the implied warranty of -+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU -+ Lesser General Public License for more details. -+ -+ You should have received a copy of the GNU Lesser General Public -+ License along with the GNU C Library; if not, write to the Free -+ Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA -+ 02111-1307 USA. */ -+ -+#include -+ -+#define SYSDEP_KNOWN_INTERPRETER_NAMES \ -+ { "/lib32/ld.so.1", FLAG_ELF_LIBC6 }, \ -+ { "/lib/ld.so.1", FLAG_ELF_LIBC6 }, -+#define SYSDEP_KNOWN_LIBRARY_NAMES \ -+ { "libc.so.6", FLAG_ELF_LIBC6 }, \ -+ { "libm.so.6", FLAG_ELF_LIBC6 }, -diff --git a/glibc-2.14.1/sysdeps/unix/sysv/linux/riscv/rv64/ldd-rewrite.sed b/glibc-2.14.1/sysdeps/unix/sysv/linux/riscv/rv64/ldd-rewrite.sed -new file mode 100644 -index 0000000..2c32732 ---- /dev/null -+++ glibc-2.14.1/sysdeps/unix/sysv/linux/riscv/rv64/ldd-rewrite.sed -@@ -0,0 +1 @@ -+s_^\(RTLDLIST=\)\(.*lib\)\(\|32\|64\)\(/[^/]*\.so\.[0-9.]*\)[ ]*$_\1"\232\4 \264\4 \2\4"_ -diff --git a/glibc-2.14.1/sysdeps/unix/sysv/linux/riscv/rv64/llseek.c b/glibc-2.14.1/sysdeps/unix/sysv/linux/riscv/rv64/llseek.c -new file mode 100644 -index 0000000..24013a8 ---- /dev/null -+++ glibc-2.14.1/sysdeps/unix/sysv/linux/riscv/rv64/llseek.c -@@ -0,0 +1 @@ -+/* lseek() is 64-bit capable already. */ -diff --git a/glibc-2.14.1/sysdeps/unix/sysv/linux/riscv/rv64/posix_fadvise.c b/glibc-2.14.1/sysdeps/unix/sysv/linux/riscv/rv64/posix_fadvise.c -new file mode 100644 -index 0000000..0287b83 ---- /dev/null -+++ glibc-2.14.1/sysdeps/unix/sysv/linux/riscv/rv64/posix_fadvise.c -@@ -0,0 +1 @@ -+#include -diff --git a/glibc-2.14.1/sysdeps/unix/sysv/linux/riscv/rv64/posix_fadvise64.c b/glibc-2.14.1/sysdeps/unix/sysv/linux/riscv/rv64/posix_fadvise64.c -new file mode 100644 -index 0000000..c9f72c4 ---- /dev/null -+++ glibc-2.14.1/sysdeps/unix/sysv/linux/riscv/rv64/posix_fadvise64.c -@@ -0,0 +1 @@ -+/* posix_fadvise64 is in posix_fadvise.c */ -diff --git a/glibc-2.14.1/sysdeps/unix/sysv/linux/riscv/rv64/posix_fallocate.c b/glibc-2.14.1/sysdeps/unix/sysv/linux/riscv/rv64/posix_fallocate.c -new file mode 100644 -index 0000000..b3fe81b ---- /dev/null -+++ glibc-2.14.1/sysdeps/unix/sysv/linux/riscv/rv64/posix_fallocate.c -@@ -0,0 +1 @@ -+#include -diff --git a/glibc-2.14.1/sysdeps/unix/sysv/linux/riscv/rv64/posix_fallocate64.c b/glibc-2.14.1/sysdeps/unix/sysv/linux/riscv/rv64/posix_fallocate64.c -new file mode 100644 -index 0000000..f466f13 ---- /dev/null -+++ glibc-2.14.1/sysdeps/unix/sysv/linux/riscv/rv64/posix_fallocate64.c -@@ -0,0 +1 @@ -+/* posix_fallocate64 is in posix_fallocate.c */ -diff --git a/glibc-2.14.1/sysdeps/unix/sysv/linux/riscv/rv64/preadv64.c b/glibc-2.14.1/sysdeps/unix/sysv/linux/riscv/rv64/preadv64.c -new file mode 100644 -index 0000000..fd9320c ---- /dev/null -+++ glibc-2.14.1/sysdeps/unix/sysv/linux/riscv/rv64/preadv64.c -@@ -0,0 +1 @@ -+/* Empty since the preadv syscall is equivalent. */ -diff --git a/glibc-2.14.1/sysdeps/unix/sysv/linux/riscv/rv64/pwritev64.c b/glibc-2.14.1/sysdeps/unix/sysv/linux/riscv/rv64/pwritev64.c -new file mode 100644 -index 0000000..8b72a29 ---- /dev/null -+++ glibc-2.14.1/sysdeps/unix/sysv/linux/riscv/rv64/pwritev64.c -@@ -0,0 +1 @@ -+/* Empty since the pwritev syscall is equivalent. */ -diff --git a/glibc-2.14.1/sysdeps/unix/sysv/linux/riscv/rv64/syscalls.list b/glibc-2.14.1/sysdeps/unix/sysv/linux/riscv/rv64/syscalls.list -new file mode 100644 -index 0000000..ee443cb ---- /dev/null -+++ glibc-2.14.1/sysdeps/unix/sysv/linux/riscv/rv64/syscalls.list -@@ -0,0 +1,17 @@ -+# File name Caller Syscall name Args Strong name Weak names -+ -+lseek - lseek Ci:iii __libc_lseek __lseek lseek __llseek llseek __libc_lseek64 __lseek64 lseek64 -+prlimit EXTRA prlimit64 i:iipp prlimit prlimit64 -+fanotify_mark EXTRA fanotify_mark i:iiiis fanotify_mark -+ -+# Semaphore and shm system calls. msgctl, shmctl, and semctl have C -+# wrappers (to set __IPC_64). -+msgget - msgget i:ii __msgget msgget -+msgrcv - msgrcv Ci:ibnii __msgrcv msgrcv -+msgsnd - msgsnd Ci:ibni __msgsnd msgsnd -+shmat - shmat i:ipi __shmat shmat -+shmdt - shmdt i:s __shmdt shmdt -+shmget - shmget i:iii __shmget shmget -+semop - semop i:ipi __semop semop -+semtimedop - semtimedop i:ipip semtimedop -+semget - semget i:iii __semget semget -diff --git a/glibc-2.14.1/sysdeps/unix/sysv/linux/riscv/rv64/umount.c b/glibc-2.14.1/sysdeps/unix/sysv/linux/riscv/rv64/umount.c -new file mode 100644 -index 0000000..e7c5690 ---- /dev/null -+++ glibc-2.14.1/sysdeps/unix/sysv/linux/riscv/rv64/umount.c -@@ -0,0 +1,31 @@ -+/* Copyright (C) 2000, 2001 Free Software Foundation, Inc. -+ This file is part of the GNU C Library. -+ Contributed by David Huggins-Daines , 2000. -+ -+ The GNU C Library is free software; you can redistribute it and/or -+ modify it under the terms of the GNU Lesser General Public -+ License as published by the Free Software Foundation; either -+ version 2.1 of the License, or (at your option) any later version. -+ -+ The GNU C Library is distributed in the hope that it will be useful, -+ but WITHOUT ANY WARRANTY; without even the implied warranty of -+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU -+ Lesser General Public License for more details. -+ -+ You should have received a copy of the GNU Lesser General Public -+ License along with the GNU C Library; if not, write to the Free -+ Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA -+ 02111-1307 USA. */ -+ -+/* Since we don't have an oldumount system call, do what the kernel -+ does down here. */ -+ -+extern long int __umount2 (const char *name, int flags); -+ -+long int -+__umount (const char *name) -+{ -+ return __umount2 (name, 0); -+} -+ -+weak_alias (__umount, umount); -diff --git a/glibc-2.14.1/sysdeps/unix/sysv/linux/riscv/setcontext.S b/glibc-2.14.1/sysdeps/unix/sysv/linux/riscv/setcontext.S -new file mode 100644 -index 0000000..07b6f71 ---- /dev/null -+++ glibc-2.14.1/sysdeps/unix/sysv/linux/riscv/setcontext.S -@@ -0,0 +1,100 @@ -+/* Set current context. -+ Copyright (C) 2009 Free Software Foundation, Inc. -+ This file is part of the GNU C Library. -+ Contributed by Maciej W. Rozycki . -+ -+ The GNU C Library is free software; you can redistribute it and/or -+ modify it under the terms of the GNU Lesser General Public -+ License as published by the Free Software Foundation; either -+ version 2.1 of the License, or (at your option) any later version. -+ -+ The GNU C Library is distributed in the hope that it will be useful, -+ but WITHOUT ANY WARRANTY; without even the implied warranty of -+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU -+ Lesser General Public License for more details. -+ -+ You should have received a copy of the GNU Lesser General Public -+ License along with the GNU C Library; if not, write to the Free -+ Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA -+ 02110-1301, USA. */ -+ -+#include -+#include -+ -+#include "ucontext_i.h" -+ -+/* int setcontext (const ucontext_t *ucp) */ -+ -+ .text -+LEAF (__setcontext) -+ -+ mv t0, a0 /* t0 <- ucp */ -+ -+/* rt_sigprocmask (SIG_SETMASK, &ucp->uc_sigmask, NULL, _NSIG8) */ -+ li a3, _NSIG8 -+ move a2, zero -+ add a1, a0, UCONTEXT_SIGMASK -+ li a0, SIG_SETMASK -+ -+ li v0, SYS_ify (rt_sigprocmask) -+ scall -+ -+ bltz v0, 99f -+ -+#ifdef __riscv_hard_float -+ lw v1, MCONTEXT_FSR(t0) -+ -+ fld fs0, ( 0 * 8 + MCONTEXT_FPREGS)(t0) -+ fld fs1, ( 1 * 8 + MCONTEXT_FPREGS)(t0) -+ fld fs2, ( 2 * 8 + MCONTEXT_FPREGS)(t0) -+ fld fs3, ( 3 * 8 + MCONTEXT_FPREGS)(t0) -+ fld fs4, ( 4 * 8 + MCONTEXT_FPREGS)(t0) -+ fld fs5, ( 5 * 8 + MCONTEXT_FPREGS)(t0) -+ fld fs6, ( 6 * 8 + MCONTEXT_FPREGS)(t0) -+ fld fs7, ( 7 * 8 + MCONTEXT_FPREGS)(t0) -+ fld fs8, ( 8 * 8 + MCONTEXT_FPREGS)(t0) -+ fld fs9, ( 9 * 8 + MCONTEXT_FPREGS)(t0) -+ fld fs10,(10 * 8 + MCONTEXT_FPREGS)(t0) -+ fld fs11,(11 * 8 + MCONTEXT_FPREGS)(t0) -+ fld fs12,(12 * 8 + MCONTEXT_FPREGS)(t0) -+ fld fs13,(13 * 8 + MCONTEXT_FPREGS)(t0) -+ fld fs14,(14 * 8 + MCONTEXT_FPREGS)(t0) -+ fld fs15,(15 * 8 + MCONTEXT_FPREGS)(t0) -+ -+ fssr v1 -+#endif /* __mips_hard_float */ -+ -+ /* Note the contents of argument registers will be random -+ unless makecontext() has been called. */ -+ REG_L v1, MCONTEXT_PC(t0) -+ REG_L ra, ( 1 * SZREG + MCONTEXT_GREGS)(t0) -+ REG_L s0, ( 2 * SZREG + MCONTEXT_GREGS)(t0) -+ REG_L s1, ( 3 * SZREG + MCONTEXT_GREGS)(t0) -+ REG_L s2, ( 4 * SZREG + MCONTEXT_GREGS)(t0) -+ REG_L s3, ( 5 * SZREG + MCONTEXT_GREGS)(t0) -+ REG_L s4, ( 6 * SZREG + MCONTEXT_GREGS)(t0) -+ REG_L s5, ( 7 * SZREG + MCONTEXT_GREGS)(t0) -+ REG_L s6, ( 8 * SZREG + MCONTEXT_GREGS)(t0) -+ REG_L s7, ( 9 * SZREG + MCONTEXT_GREGS)(t0) -+ REG_L s8, (10 * SZREG + MCONTEXT_GREGS)(t0) -+ REG_L s9, (11 * SZREG + MCONTEXT_GREGS)(t0) -+ REG_L s10,(12 * SZREG + MCONTEXT_GREGS)(t0) -+ REG_L s11,(13 * SZREG + MCONTEXT_GREGS)(t0) -+ REG_L sp, (14 * SZREG + MCONTEXT_GREGS)(t0) -+ REG_L tp, (15 * SZREG + MCONTEXT_GREGS)(t0) -+ REG_L a0, (18 * SZREG + MCONTEXT_GREGS)(t0) -+ REG_L a1, (19 * SZREG + MCONTEXT_GREGS)(t0) -+ REG_L a2, (20 * SZREG + MCONTEXT_GREGS)(t0) -+ REG_L a3, (21 * SZREG + MCONTEXT_GREGS)(t0) -+ REG_L a4, (22 * SZREG + MCONTEXT_GREGS)(t0) -+ REG_L a5, (23 * SZREG + MCONTEXT_GREGS)(t0) -+ REG_L a6, (24 * SZREG + MCONTEXT_GREGS)(t0) -+ REG_L a7, (25 * SZREG + MCONTEXT_GREGS)(t0) -+ -+ jr v1 -+ -+99: j __syscall_error -+ -+PSEUDO_END (__setcontext) -+ -+weak_alias (__setcontext, setcontext) -diff --git a/glibc-2.14.1/sysdeps/unix/sysv/linux/riscv/sigcontextinfo.h b/glibc-2.14.1/sysdeps/unix/sysv/linux/riscv/sigcontextinfo.h -new file mode 100644 -index 0000000..ea01f8e ---- /dev/null -+++ glibc-2.14.1/sysdeps/unix/sysv/linux/riscv/sigcontextinfo.h -@@ -0,0 +1,29 @@ -+/* Copyright (C) 2000, 2001, 2003, 2004 Free Software Foundation, Inc. -+ This file is part of the GNU C Library. -+ Contributed by Andreas Jaeger , 2000. -+ -+ The GNU C Library is free software; you can redistribute it and/or -+ modify it under the terms of the GNU Lesser General Public -+ License as published by the Free Software Foundation; either -+ version 2.1 of the License, or (at your option) any later version. -+ -+ The GNU C Library is distributed in the hope that it will be useful, -+ but WITHOUT ANY WARRANTY; without even the implied warranty of -+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU -+ Lesser General Public License for more details. -+ -+ You should have received a copy of the GNU Lesser General Public -+ License along with the GNU C Library; if not, write to the Free -+ Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA -+ 02111-1307 USA. */ -+ -+#include -+ -+#define SIGCONTEXT siginfo_t *_si, struct ucontext * -+#define SIGCONTEXT_EXTRA_ARGS _si, -+#define GET_PC(ctx) ((void *) ctx->uc_mcontext.gregs[REG_PC]) -+#define GET_FRAME(ctx) ((void *) ctx->uc_mcontext.gregs[REG_S0]) -+#define GET_STACK(ctx) ((void *) ctx->uc_mcontext.gregs[REG_SP]) -+ -+#define CALL_SIGHANDLER(handler, signo, ctx) \ -+ (handler)((signo), SIGCONTEXT_EXTRA_ARGS (ctx)) -diff --git a/glibc-2.14.1/sysdeps/unix/sysv/linux/riscv/socket.S b/glibc-2.14.1/sysdeps/unix/sysv/linux/riscv/socket.S -new file mode 100644 -index 0000000..1f66cd4 ---- /dev/null -+++ glibc-2.14.1/sysdeps/unix/sysv/linux/riscv/socket.S -@@ -0,0 +1,91 @@ -+/* Copyright (C) 1997, 1998, 2002, 2003 Free Software Foundation, Inc. -+ This file is part of the GNU C Library. -+ Contributed by Miguel de Icaza , 1997. -+ -+ The GNU C Library is free software; you can redistribute it and/or -+ modify it under the terms of the GNU Lesser General Public -+ License as published by the Free Software Foundation; either -+ version 2.1 of the License, or (at your option) any later version. -+ -+ The GNU C Library is distributed in the hope that it will be useful, -+ but WITHOUT ANY WARRANTY; without even the implied warranty of -+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU -+ Lesser General Public License for more details. -+ -+ You should have received a copy of the GNU Lesser General Public -+ License along with the GNU C Library; if not, write to the Free -+ Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA -+ 02111-1307 USA. */ -+ -+#include -+#include -+ -+#define P(a, b) P2(a, b) -+#define P2(a, b) a##b -+ -+#ifndef NARGS -+#ifdef socket -+#error NARGS not defined -+#endif -+#define NARGS 3 -+#endif -+ -+ .text -+/* The socket-oriented system calls are handled unusually in Linux. -+ They are all gated through the single `socketcall' system call number. -+ `socketcall' takes two arguments: the first is the subcode, specifying -+ which socket function is being called; and the second is a pointer to -+ the arguments to the specific function. -+ -+ The .S files for the other calls just #define socket and #include this. */ -+ -+#ifndef __socket -+# ifndef NO_WEAK_ALIAS -+# define __socket P(__,socket) -+# else -+# define __socket socket -+# endif -+#endif -+ -+LEAF (__socket) -+ -+ addi sp, sp, -SZREG*NARGS -+ -+ REG_S a0, 0*SZREG(sp) -+ REG_S a1, 1*SZREG(sp) -+#if NARGS > 2 -+ REG_S a2, 2*SZREG(sp) -+#if NARGS > 3 -+ REG_S a3, 3*SZREG(sp) -+#if NARGS > 4 -+ REG_S a4, 4*SZREG(sp) -+#if NARGS > 5 -+ REG_S a5, 5*SZREG(sp) -+#endif -+#endif -+#endif -+#endif -+ -+#if defined NEED_CANCELLATION && defined CENABLE -+ SINGLE_THREAD_P(a0) -+ bnez a0, 1f -+#endif -+ li a0, P(SOCKOP_,socket) /* arg 1: socket subfunction */ -+ move a1, sp /* arg 2: parameter block */ -+ li v0, SYS_ify (rt_sigprocmask) -+ scall -+ -+ addi sp, sp, SZREG*NARGS -+ bltz v0, 99f -+ -+#if defined NEED_CANCELLATION && defined CENABLE -+1:sbreak -+#endif -+ -+99: j __syscall_error -+ -+END (__socket) -+ -+#ifndef NO_WEAK_ALIAS -+weak_alias (__socket, socket) -+#endif -diff --git a/glibc-2.14.1/sysdeps/unix/sysv/linux/riscv/swapcontext.S b/glibc-2.14.1/sysdeps/unix/sysv/linux/riscv/swapcontext.S -new file mode 100644 -index 0000000..76ec343 ---- /dev/null -+++ glibc-2.14.1/sysdeps/unix/sysv/linux/riscv/swapcontext.S -@@ -0,0 +1,138 @@ -+/* Save and set current context. -+ Copyright (C) 2009 Free Software Foundation, Inc. -+ This file is part of the GNU C Library. -+ Contributed by Maciej W. Rozycki . -+ -+ The GNU C Library is free software; you can redistribute it and/or -+ modify it under the terms of the GNU Lesser General Public -+ License as published by the Free Software Foundation; either -+ version 2.1 of the License, or (at your option) any later version. -+ -+ The GNU C Library is distributed in the hope that it will be useful, -+ but WITHOUT ANY WARRANTY; without even the implied warranty of -+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU -+ Lesser General Public License for more details. -+ -+ You should have received a copy of the GNU Lesser General Public -+ License along with the GNU C Library; if not, write to the Free -+ Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA -+ 02110-1301, USA. */ -+ -+#include -+#include -+ -+#include "ucontext_i.h" -+ -+/* int swapcontext (ucontext_t *oucp, const ucontext_t *ucp) */ -+ -+LEAF (__swapcontext) -+ mv t0, a1 /* t0 <- ucp */ -+ -+ REG_S ra, MCONTEXT_PC(a0) -+ REG_S ra, ( 1 * SZREG + MCONTEXT_GREGS)(a0) -+ REG_S s0, ( 2 * SZREG + MCONTEXT_GREGS)(a0) -+ REG_S s1, ( 3 * SZREG + MCONTEXT_GREGS)(a0) -+ REG_S s2, ( 4 * SZREG + MCONTEXT_GREGS)(a0) -+ REG_S s3, ( 5 * SZREG + MCONTEXT_GREGS)(a0) -+ REG_S s4, ( 6 * SZREG + MCONTEXT_GREGS)(a0) -+ REG_S s5, ( 7 * SZREG + MCONTEXT_GREGS)(a0) -+ REG_S s6, ( 8 * SZREG + MCONTEXT_GREGS)(a0) -+ REG_S s7, ( 9 * SZREG + MCONTEXT_GREGS)(a0) -+ REG_S s8, (10 * SZREG + MCONTEXT_GREGS)(a0) -+ REG_S s9, (11 * SZREG + MCONTEXT_GREGS)(a0) -+ REG_S s10,(12 * SZREG + MCONTEXT_GREGS)(a0) -+ REG_S s11,(13 * SZREG + MCONTEXT_GREGS)(a0) -+ REG_S sp, (14 * SZREG + MCONTEXT_GREGS)(a0) -+ REG_S tp, (15 * SZREG + MCONTEXT_GREGS)(a0) -+ -+#ifdef __riscv_hard_float -+ frsr v1 -+ -+ fsd fs0, ( 0 * 8 + MCONTEXT_FPREGS)(a0) -+ fsd fs1, ( 1 * 8 + MCONTEXT_FPREGS)(a0) -+ fsd fs2, ( 2 * 8 + MCONTEXT_FPREGS)(a0) -+ fsd fs3, ( 3 * 8 + MCONTEXT_FPREGS)(a0) -+ fsd fs4, ( 4 * 8 + MCONTEXT_FPREGS)(a0) -+ fsd fs5, ( 5 * 8 + MCONTEXT_FPREGS)(a0) -+ fsd fs6, ( 6 * 8 + MCONTEXT_FPREGS)(a0) -+ fsd fs7, ( 7 * 8 + MCONTEXT_FPREGS)(a0) -+ fsd fs8, ( 8 * 8 + MCONTEXT_FPREGS)(a0) -+ fsd fs9, ( 9 * 8 + MCONTEXT_FPREGS)(a0) -+ fsd fs10,(10 * 8 + MCONTEXT_FPREGS)(a0) -+ fsd fs11,(11 * 8 + MCONTEXT_FPREGS)(a0) -+ fsd fs12,(12 * 8 + MCONTEXT_FPREGS)(a0) -+ fsd fs13,(13 * 8 + MCONTEXT_FPREGS)(a0) -+ fsd fs14,(14 * 8 + MCONTEXT_FPREGS)(a0) -+ fsd fs15,(15 * 8 + MCONTEXT_FPREGS)(a0) -+ -+ sw v1, MCONTEXT_FSR(a0) -+#endif /* __mips_hard_float */ -+ -+/* rt_sigprocmask (SIG_SETMASK, &ucp->uc_sigmask, NULL, _NSIG8) */ -+ li a3, _NSIG8 -+ add a2, a0, UCONTEXT_SIGMASK -+ add a1, a1, UCONTEXT_SIGMASK -+ li a0, SIG_SETMASK -+ -+ li v0, SYS_ify (rt_sigprocmask) -+ scall -+ -+ bltz v0, 99f -+ -+#ifdef __riscv_hard_float -+ lw v1, MCONTEXT_FSR(t0) -+ -+ fld fs0, ( 0 * 8 + MCONTEXT_FPREGS)(t0) -+ fld fs1, ( 1 * 8 + MCONTEXT_FPREGS)(t0) -+ fld fs2, ( 2 * 8 + MCONTEXT_FPREGS)(t0) -+ fld fs3, ( 3 * 8 + MCONTEXT_FPREGS)(t0) -+ fld fs4, ( 4 * 8 + MCONTEXT_FPREGS)(t0) -+ fld fs5, ( 5 * 8 + MCONTEXT_FPREGS)(t0) -+ fld fs6, ( 6 * 8 + MCONTEXT_FPREGS)(t0) -+ fld fs7, ( 7 * 8 + MCONTEXT_FPREGS)(t0) -+ fld fs8, ( 8 * 8 + MCONTEXT_FPREGS)(t0) -+ fld fs9, ( 9 * 8 + MCONTEXT_FPREGS)(t0) -+ fld fs10,(10 * 8 + MCONTEXT_FPREGS)(t0) -+ fld fs11,(11 * 8 + MCONTEXT_FPREGS)(t0) -+ fld fs12,(12 * 8 + MCONTEXT_FPREGS)(t0) -+ fld fs13,(13 * 8 + MCONTEXT_FPREGS)(t0) -+ fld fs14,(14 * 8 + MCONTEXT_FPREGS)(t0) -+ fld fs15,(15 * 8 + MCONTEXT_FPREGS)(t0) -+ -+ fssr v1 -+#endif /* __mips_hard_float */ -+ -+ /* Note the contents of argument registers will be random -+ unless makecontext() has been called. */ -+ REG_L v1, MCONTEXT_PC(t0) -+ REG_L ra, ( 1 * SZREG + MCONTEXT_GREGS)(t0) -+ REG_L s0, ( 2 * SZREG + MCONTEXT_GREGS)(t0) -+ REG_L s1, ( 3 * SZREG + MCONTEXT_GREGS)(t0) -+ REG_L s2, ( 4 * SZREG + MCONTEXT_GREGS)(t0) -+ REG_L s3, ( 5 * SZREG + MCONTEXT_GREGS)(t0) -+ REG_L s4, ( 6 * SZREG + MCONTEXT_GREGS)(t0) -+ REG_L s5, ( 7 * SZREG + MCONTEXT_GREGS)(t0) -+ REG_L s6, ( 8 * SZREG + MCONTEXT_GREGS)(t0) -+ REG_L s7, ( 9 * SZREG + MCONTEXT_GREGS)(t0) -+ REG_L s8, (10 * SZREG + MCONTEXT_GREGS)(t0) -+ REG_L s9, (11 * SZREG + MCONTEXT_GREGS)(t0) -+ REG_L s10,(12 * SZREG + MCONTEXT_GREGS)(t0) -+ REG_L s11,(13 * SZREG + MCONTEXT_GREGS)(t0) -+ REG_L sp, (14 * SZREG + MCONTEXT_GREGS)(t0) -+ REG_L tp, (15 * SZREG + MCONTEXT_GREGS)(t0) -+ REG_L a0, (18 * SZREG + MCONTEXT_GREGS)(t0) -+ REG_L a1, (19 * SZREG + MCONTEXT_GREGS)(t0) -+ REG_L a2, (20 * SZREG + MCONTEXT_GREGS)(t0) -+ REG_L a3, (21 * SZREG + MCONTEXT_GREGS)(t0) -+ REG_L a4, (22 * SZREG + MCONTEXT_GREGS)(t0) -+ REG_L a5, (23 * SZREG + MCONTEXT_GREGS)(t0) -+ REG_L a6, (24 * SZREG + MCONTEXT_GREGS)(t0) -+ REG_L a7, (25 * SZREG + MCONTEXT_GREGS)(t0) -+ -+ jr v1 -+ -+99: j __syscall_error -+ -+PSEUDO_END (__swapcontext) -+ -+weak_alias (__swapcontext, swapcontext) -diff --git a/glibc-2.14.1/sysdeps/unix/sysv/linux/riscv/sys/cachectl.h b/glibc-2.14.1/sysdeps/unix/sysv/linux/riscv/sys/cachectl.h -new file mode 100644 -index 0000000..3d9f914 ---- /dev/null -+++ glibc-2.14.1/sysdeps/unix/sysv/linux/riscv/sys/cachectl.h -@@ -0,0 +1,42 @@ -+/* Copyright (C) 1995, 1996, 1997, 2000, 2009 Free Software Foundation, Inc. -+ This file is part of the GNU C Library. -+ -+ The GNU C Library is free software; you can redistribute it and/or -+ modify it under the terms of the GNU Lesser General Public -+ License as published by the Free Software Foundation; either -+ version 2.1 of the License, or (at your option) any later version. -+ -+ The GNU C Library is distributed in the hope that it will be useful, -+ but WITHOUT ANY WARRANTY; without even the implied warranty of -+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU -+ Lesser General Public License for more details. -+ -+ You should have received a copy of the GNU Lesser General Public -+ License along with the GNU C Library; if not, write to the Free -+ Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA -+ 02111-1307 USA. */ -+ -+#ifndef _SYS_CACHECTL_H -+#define _SYS_CACHECTL_H 1 -+ -+#include -+ -+/* -+ * Get the kernel definition for the op bits. -+ */ -+#include -+ -+__BEGIN_DECLS -+ -+#ifdef __USE_MISC -+extern int cachectl (void *__addr, __const int __nbytes, __const int __op) __THROW; -+#endif -+extern int __cachectl (void *__addr, __const int __nbytes, __const int __op) __THROW; -+#ifdef __USE_MISC -+extern int cacheflush (void *__addr, __const int __nbytes, __const int __op) __THROW; -+#endif -+extern int _flush_cache (char *__addr, __const int __nbytes, __const int __op) __THROW; -+ -+__END_DECLS -+ -+#endif /* sys/cachectl.h */ -diff --git a/glibc-2.14.1/sysdeps/unix/sysv/linux/riscv/sys/epoll.h b/glibc-2.14.1/sysdeps/unix/sysv/linux/riscv/sys/epoll.h -new file mode 100644 -index 0000000..6d2ec8e ---- /dev/null -+++ glibc-2.14.1/sysdeps/unix/sysv/linux/riscv/sys/epoll.h -@@ -0,0 +1,144 @@ -+/* Copyright (C) 2002-2006, 2007, 2008 Free Software Foundation, Inc. -+ This file is part of the GNU C Library. -+ -+ The GNU C Library is free software; you can redistribute it and/or -+ modify it under the terms of the GNU Lesser General Public -+ License as published by the Free Software Foundation; either -+ version 2.1 of the License, or (at your option) any later version. -+ -+ The GNU C Library is distributed in the hope that it will be useful, -+ but WITHOUT ANY WARRANTY; without even the implied warranty of -+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU -+ Lesser General Public License for more details. -+ -+ You should have received a copy of the GNU Lesser General Public -+ License along with the GNU C Library; if not, write to the Free -+ Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA -+ 02111-1307 USA. */ -+ -+#ifndef _SYS_EPOLL_H -+#define _SYS_EPOLL_H 1 -+ -+#include -+#include -+ -+/* Get __sigset_t. */ -+#include -+ -+#ifndef __sigset_t_defined -+# define __sigset_t_defined -+typedef __sigset_t sigset_t; -+#endif -+ -+ -+/* Flags to be passed to epoll_create1. */ -+enum -+ { -+ EPOLL_CLOEXEC = 02000000, -+#define EPOLL_CLOEXEC EPOLL_CLOEXEC -+ EPOLL_NONBLOCK = 0200 -+#define EPOLL_NONBLOCK EPOLL_NONBLOCK -+ }; -+ -+ -+enum EPOLL_EVENTS -+ { -+ EPOLLIN = 0x001, -+#define EPOLLIN EPOLLIN -+ EPOLLPRI = 0x002, -+#define EPOLLPRI EPOLLPRI -+ EPOLLOUT = 0x004, -+#define EPOLLOUT EPOLLOUT -+ EPOLLRDNORM = 0x040, -+#define EPOLLRDNORM EPOLLRDNORM -+ EPOLLRDBAND = 0x080, -+#define EPOLLRDBAND EPOLLRDBAND -+ EPOLLWRNORM = 0x100, -+#define EPOLLWRNORM EPOLLWRNORM -+ EPOLLWRBAND = 0x200, -+#define EPOLLWRBAND EPOLLWRBAND -+ EPOLLMSG = 0x400, -+#define EPOLLMSG EPOLLMSG -+ EPOLLERR = 0x008, -+#define EPOLLERR EPOLLERR -+ EPOLLHUP = 0x010, -+#define EPOLLHUP EPOLLHUP -+ EPOLLRDHUP = 0x2000, -+#define EPOLLRDHUP EPOLLRDHUP -+ EPOLLONESHOT = (1 << 30), -+#define EPOLLONESHOT EPOLLONESHOT -+ EPOLLET = (1 << 31) -+#define EPOLLET EPOLLET -+ }; -+ -+ -+/* Valid opcodes ( "op" parameter ) to issue to epoll_ctl(). */ -+#define EPOLL_CTL_ADD 1 /* Add a file descriptor to the interface. */ -+#define EPOLL_CTL_DEL 2 /* Remove a file descriptor from the interface. */ -+#define EPOLL_CTL_MOD 3 /* Change file descriptor epoll_event structure. */ -+ -+ -+typedef union epoll_data -+{ -+ void *ptr; -+ int fd; -+ uint32_t u32; -+ uint64_t u64; -+} epoll_data_t; -+ -+struct epoll_event -+{ -+ uint32_t events; /* Epoll events */ -+ epoll_data_t data; /* User data variable */ -+}; -+ -+ -+__BEGIN_DECLS -+ -+/* Creates an epoll instance. Returns an fd for the new instance. -+ The "size" parameter is a hint specifying the number of file -+ descriptors to be associated with the new instance. The fd -+ returned by epoll_create() should be closed with close(). */ -+extern int epoll_create (int __size) __THROW; -+ -+/* Same as epoll_create but with an FLAGS parameter. The unused SIZE -+ parameter has been dropped. */ -+extern int epoll_create1 (int __flags) __THROW; -+ -+ -+/* Manipulate an epoll instance "epfd". Returns 0 in case of success, -+ -1 in case of error ( the "errno" variable will contain the -+ specific error code ) The "op" parameter is one of the EPOLL_CTL_* -+ constants defined above. The "fd" parameter is the target of the -+ operation. The "event" parameter describes which events the caller -+ is interested in and any associated user data. */ -+extern int epoll_ctl (int __epfd, int __op, int __fd, -+ struct epoll_event *__event) __THROW; -+ -+ -+/* Wait for events on an epoll instance "epfd". Returns the number of -+ triggered events returned in "events" buffer. Or -1 in case of -+ error with the "errno" variable set to the specific error code. The -+ "events" parameter is a buffer that will contain triggered -+ events. The "maxevents" is the maximum number of events to be -+ returned ( usually size of "events" ). The "timeout" parameter -+ specifies the maximum wait time in milliseconds (-1 == infinite). -+ -+ This function is a cancellation point and therefore not marked with -+ __THROW. */ -+extern int epoll_wait (int __epfd, struct epoll_event *__events, -+ int __maxevents, int __timeout); -+ -+ -+/* Same as epoll_wait, but the thread's signal mask is temporarily -+ and atomically replaced with the one provided as parameter. -+ -+ This function is a cancellation point and therefore not marked with -+ __THROW. */ -+extern int epoll_pwait (int __epfd, struct epoll_event *__events, -+ int __maxevents, int __timeout, -+ __const __sigset_t *__ss); -+ -+__END_DECLS -+ -+#endif /* sys/epoll.h */ -diff --git a/glibc-2.14.1/sysdeps/unix/sysv/linux/riscv/sys/eventfd.h b/glibc-2.14.1/sysdeps/unix/sysv/linux/riscv/sys/eventfd.h -new file mode 100644 -index 0000000..b30d09a ---- /dev/null -+++ glibc-2.14.1/sysdeps/unix/sysv/linux/riscv/sys/eventfd.h -@@ -0,0 +1,54 @@ -+/* Copyright (C) 2007, 2008, 2009 Free Software Foundation, Inc. -+ This file is part of the GNU C Library. -+ -+ The GNU C Library is free software; you can redistribute it and/or -+ modify it under the terms of the GNU Lesser General Public -+ License as published by the Free Software Foundation; either -+ version 2.1 of the License, or (at your option) any later version. -+ -+ The GNU C Library is distributed in the hope that it will be useful, -+ but WITHOUT ANY WARRANTY; without even the implied warranty of -+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU -+ Lesser General Public License for more details. -+ -+ You should have received a copy of the GNU Lesser General Public -+ License along with the GNU C Library; if not, write to the Free -+ Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA -+ 02111-1307 USA. */ -+ -+#ifndef _SYS_EVENTFD_H -+#define _SYS_EVENTFD_H 1 -+ -+#include -+ -+ -+/* Type for event counter. */ -+typedef uint64_t eventfd_t; -+ -+/* Flags for signalfd. */ -+enum -+ { -+ EFD_SEMAPHORE = 1, -+#define EFD_SEMAPHORE EFD_SEMAPHORE -+ EFD_CLOEXEC = 02000000, -+#define EFD_CLOEXEC EFD_CLOEXEC -+ EFD_NONBLOCK = 0200 -+#define EFD_NONBLOCK EFD_NONBLOCK -+ }; -+ -+ -+__BEGIN_DECLS -+ -+/* Return file descriptor for generic event channel. Set initial -+ value to COUNT. */ -+extern int eventfd (int __count, int __flags) __THROW; -+ -+/* Read event counter and possibly wait for events. */ -+extern int eventfd_read (int __fd, eventfd_t *__value); -+ -+/* Increment event counter. */ -+extern int eventfd_write (int __fd, eventfd_t __value); -+ -+__END_DECLS -+ -+#endif /* sys/eventfd.h */ -diff --git a/glibc-2.14.1/sysdeps/unix/sysv/linux/riscv/sys/inotify.h b/glibc-2.14.1/sysdeps/unix/sysv/linux/riscv/sys/inotify.h -new file mode 100644 -index 0000000..d1d0509 ---- /dev/null -+++ glibc-2.14.1/sysdeps/unix/sysv/linux/riscv/sys/inotify.h -@@ -0,0 +1,107 @@ -+/* Copyright (C) 2005, 2006, 2008, 2009, 2010 Free Software Foundation, Inc. -+ This file is part of the GNU C Library. -+ -+ The GNU C Library is free software; you can redistribute it and/or -+ modify it under the terms of the GNU Lesser General Public -+ License as published by the Free Software Foundation; either -+ version 2.1 of the License, or (at your option) any later version. -+ -+ The GNU C Library is distributed in the hope that it will be useful, -+ but WITHOUT ANY WARRANTY; without even the implied warranty of -+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU -+ Lesser General Public License for more details. -+ -+ You should have received a copy of the GNU Lesser General Public -+ License along with the GNU C Library; if not, write to the Free -+ Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA -+ 02111-1307 USA. */ -+ -+#ifndef _SYS_INOTIFY_H -+#define _SYS_INOTIFY_H 1 -+ -+#include -+ -+ -+/* Flags for the parameter of inotify_init1. */ -+enum -+ { -+ IN_CLOEXEC = 02000000, -+#define IN_CLOEXEC IN_CLOEXEC -+ IN_NONBLOCK = 0200 -+#define IN_NONBLOCK IN_NONBLOCK -+ }; -+ -+ -+/* Structure describing an inotify event. */ -+struct inotify_event -+{ -+ int wd; /* Watch descriptor. */ -+ uint32_t mask; /* Watch mask. */ -+ uint32_t cookie; /* Cookie to synchronize two events. */ -+ uint32_t len; /* Length (including NULs) of name. */ -+ char name __flexarr; /* Name. */ -+}; -+ -+ -+/* Supported events suitable for MASK parameter of INOTIFY_ADD_WATCH. */ -+#define IN_ACCESS 0x00000001 /* File was accessed. */ -+#define IN_MODIFY 0x00000002 /* File was modified. */ -+#define IN_ATTRIB 0x00000004 /* Metadata changed. */ -+#define IN_CLOSE_WRITE 0x00000008 /* Writtable file was closed. */ -+#define IN_CLOSE_NOWRITE 0x00000010 /* Unwrittable file closed. */ -+#define IN_CLOSE (IN_CLOSE_WRITE | IN_CLOSE_NOWRITE) /* Close. */ -+#define IN_OPEN 0x00000020 /* File was opened. */ -+#define IN_MOVED_FROM 0x00000040 /* File was moved from X. */ -+#define IN_MOVED_TO 0x00000080 /* File was moved to Y. */ -+#define IN_MOVE (IN_MOVED_FROM | IN_MOVED_TO) /* Moves. */ -+#define IN_CREATE 0x00000100 /* Subfile was created. */ -+#define IN_DELETE 0x00000200 /* Subfile was deleted. */ -+#define IN_DELETE_SELF 0x00000400 /* Self was deleted. */ -+#define IN_MOVE_SELF 0x00000800 /* Self was moved. */ -+ -+/* Events sent by the kernel. */ -+#define IN_UNMOUNT 0x00002000 /* Backing fs was unmounted. */ -+#define IN_Q_OVERFLOW 0x00004000 /* Event queued overflowed. */ -+#define IN_IGNORED 0x00008000 /* File was ignored. */ -+ -+/* Helper events. */ -+#define IN_CLOSE (IN_CLOSE_WRITE | IN_CLOSE_NOWRITE) /* Close. */ -+#define IN_MOVE (IN_MOVED_FROM | IN_MOVED_TO) /* Moves. */ -+ -+/* Special flags. */ -+#define IN_ONLYDIR 0x01000000 /* Only watch the path if it is a -+ directory. */ -+#define IN_DONT_FOLLOW 0x02000000 /* Do not follow a sym link. */ -+#define IN_EXCL_UNLINK 0x04000000 /* Exclude events on unlinked -+ objects. */ -+#define IN_MASK_ADD 0x20000000 /* Add to the mask of an already -+ existing watch. */ -+#define IN_ISDIR 0x40000000 /* Event occurred against dir. */ -+#define IN_ONESHOT 0x80000000 /* Only send event once. */ -+ -+/* All events which a program can wait on. */ -+#define IN_ALL_EVENTS (IN_ACCESS | IN_MODIFY | IN_ATTRIB | IN_CLOSE_WRITE \ -+ | IN_CLOSE_NOWRITE | IN_OPEN | IN_MOVED_FROM \ -+ | IN_MOVED_TO | IN_CREATE | IN_DELETE \ -+ | IN_DELETE_SELF | IN_MOVE_SELF) -+ -+ -+__BEGIN_DECLS -+ -+/* Create and initialize inotify instance. */ -+extern int inotify_init (void) __THROW; -+ -+/* Create and initialize inotify instance. */ -+extern int inotify_init1 (int __flags) __THROW; -+ -+/* Add watch of object NAME to inotify instance FD. Notify about -+ events specified by MASK. */ -+extern int inotify_add_watch (int __fd, const char *__name, uint32_t __mask) -+ __THROW; -+ -+/* Remove the watch specified by WD from the inotify instance FD. */ -+extern int inotify_rm_watch (int __fd, int __wd) __THROW; -+ -+__END_DECLS -+ -+#endif /* sys/inotify.h */ -diff --git a/glibc-2.14.1/sysdeps/unix/sysv/linux/riscv/sys/procfs.h b/glibc-2.14.1/sysdeps/unix/sysv/linux/riscv/sys/procfs.h -new file mode 100644 -index 0000000..ce11419 ---- /dev/null -+++ glibc-2.14.1/sysdeps/unix/sysv/linux/riscv/sys/procfs.h -@@ -0,0 +1,128 @@ -+/* Copyright (C) 1996, 1997, 1999, 2000, 2002, 2003, 2004 -+ Free Software Foundation, Inc. -+ This file is part of the GNU C Library. -+ -+ The GNU C Library is free software; you can redistribute it and/or -+ modify it under the terms of the GNU Lesser General Public -+ License as published by the Free Software Foundation; either -+ version 2.1 of the License, or (at your option) any later version. -+ -+ The GNU C Library is distributed in the hope that it will be useful, -+ but WITHOUT ANY WARRANTY; without even the implied warranty of -+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU -+ Lesser General Public License for more details. -+ -+ You should have received a copy of the GNU Lesser General Public -+ License along with the GNU C Library; if not, write to the Free -+ Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA -+ 02111-1307 USA. */ -+ -+#ifndef _SYS_PROCFS_H -+#define _SYS_PROCFS_H 1 -+ -+/* This is somehow modelled after the file of the same name on SysVr4 -+ systems. It provides a definition of the core file format for ELF -+ used on Linux. */ -+ -+#include -+#include -+#include -+#include -+#include -+#include -+ -+/* ELF register definitions */ -+#define ELF_NGREG 45 -+#define ELF_NFPREG 33 -+ -+#if _RISCV_SIM == _ABIN32 -+__extension__ typedef unsigned long long elf_greg_t; -+#else -+typedef unsigned long elf_greg_t; -+#endif -+typedef elf_greg_t elf_gregset_t[ELF_NGREG]; -+ -+typedef double elf_fpreg_t; -+typedef elf_fpreg_t elf_fpregset_t[ELF_NFPREG]; -+ -+__BEGIN_DECLS -+ -+struct elf_siginfo -+ { -+ int si_signo; /* Signal number. */ -+ int si_code; /* Extra code. */ -+ int si_errno; /* Errno. */ -+ }; -+ -+ -+/* Definitions to generate Intel SVR4-like core files. These mostly -+ have the same names as the SVR4 types with "elf_" tacked on the -+ front to prevent clashes with linux definitions, and the typedef -+ forms have been avoided. This is mostly like the SVR4 structure, -+ but more Linuxy, with things that Linux does not support and which -+ gdb doesn't really use excluded. Fields present but not used are -+ marked with "XXX". */ -+struct elf_prstatus -+ { -+ struct elf_siginfo pr_info; /* Info associated with signal. */ -+ short int pr_cursig; /* Current signal. */ -+#if _RISCV_SIM == _ABIN32 -+ __extension__ unsigned long long int pr_sigpend; -+ __extension__ unsigned long long int pr_sighold; -+#else -+ unsigned long int pr_sigpend; /* Set of pending signals. */ -+ unsigned long int pr_sighold; /* Set of held signals. */ -+#endif -+ __pid_t pr_pid; -+ __pid_t pr_ppid; -+ __pid_t pr_pgrp; -+ __pid_t pr_sid; -+ struct timeval pr_utime; /* User time. */ -+ struct timeval pr_stime; /* System time. */ -+ struct timeval pr_cutime; /* Cumulative user time. */ -+ struct timeval pr_cstime; /* Cumulative system time. */ -+ elf_gregset_t pr_reg; /* GP registers. */ -+ int pr_fpvalid; /* True if math copro being used. */ -+ }; -+ -+ -+#define ELF_PRARGSZ (80) /* Number of chars for args */ -+ -+struct elf_prpsinfo -+ { -+ char pr_state; /* Numeric process state. */ -+ char pr_sname; /* Char for pr_state. */ -+ char pr_zomb; /* Zombie. */ -+ char pr_nice; /* Nice val. */ -+#if _RISCV_SIM == _ABIN32 -+ __extension__ unsigned long long int pr_flag; -+#else -+ unsigned long int pr_flag; /* Flags. */ -+#endif -+ long pr_uid; -+ long pr_gid; -+ int pr_pid, pr_ppid, pr_pgrp, pr_sid; -+ /* Lots missing */ -+ char pr_fname[16]; /* Filename of executable. */ -+ char pr_psargs[ELF_PRARGSZ]; /* Initial part of arg list. */ -+ }; -+ -+ -+/* Addresses. */ -+typedef void *psaddr_t; -+ -+/* Register sets. Linux has different names. */ -+typedef elf_gregset_t prgregset_t; -+typedef elf_fpregset_t prfpregset_t; -+ -+/* We don't have any differences between processes and threads, -+ therefore habe only ine PID type. */ -+typedef __pid_t lwpid_t; -+ -+ -+typedef struct elf_prstatus prstatus_t; -+typedef struct elf_prpsinfo prpsinfo_t; -+ -+__END_DECLS -+ -+#endif /* sys/procfs.h */ -diff --git a/glibc-2.14.1/sysdeps/unix/sysv/linux/riscv/sys/signalfd.h b/glibc-2.14.1/sysdeps/unix/sysv/linux/riscv/sys/signalfd.h -new file mode 100644 -index 0000000..08923c0 ---- /dev/null -+++ glibc-2.14.1/sysdeps/unix/sysv/linux/riscv/sys/signalfd.h -@@ -0,0 +1,66 @@ -+/* Copyright (C) 2007, 2008 Free Software Foundation, Inc. -+ This file is part of the GNU C Library. -+ -+ The GNU C Library is free software; you can redistribute it and/or -+ modify it under the terms of the GNU Lesser General Public -+ License as published by the Free Software Foundation; either -+ version 2.1 of the License, or (at your option) any later version. -+ -+ The GNU C Library is distributed in the hope that it will be useful, -+ but WITHOUT ANY WARRANTY; without even the implied warranty of -+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU -+ Lesser General Public License for more details. -+ -+ You should have received a copy of the GNU Lesser General Public -+ License along with the GNU C Library; if not, write to the Free -+ Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA -+ 02111-1307 USA. */ -+ -+#ifndef _SYS_SIGNALFD_H -+#define _SYS_SIGNALFD_H 1 -+ -+#define __need_sigset_t -+#include -+#include -+ -+ -+struct signalfd_siginfo -+{ -+ uint32_t ssi_signo; -+ int32_t ssi_errno; -+ int32_t ssi_code; -+ uint32_t ssi_pid; -+ uint32_t ssi_uid; -+ int32_t ssi_fd; -+ uint32_t ssi_tid; -+ uint32_t ssi_band; -+ uint32_t ssi_overrun; -+ uint32_t ssi_trapno; -+ int32_t ssi_status; -+ int32_t ssi_int; -+ uint64_t ssi_ptr; -+ uint64_t ssi_utime; -+ uint64_t ssi_stime; -+ uint64_t ssi_addr; -+ uint8_t __pad[48]; -+}; -+ -+/* Flags for signalfd. */ -+enum -+ { -+ SFD_CLOEXEC = 02000000, -+#define SFD_CLOEXEC SFD_CLOEXEC -+ SFD_NONBLOCK = 0200 -+#define SFD_NONBLOCK SFD_NONBLOCK -+ }; -+ -+__BEGIN_DECLS -+ -+/* Request notification for delivery of signals in MASK to be -+ performed using descriptor FD.*/ -+extern int signalfd (int __fd, const sigset_t *__mask, int __flags) -+ __THROW __nonnull ((2)); -+ -+__END_DECLS -+ -+#endif /* sys/signalfd.h */ -diff --git a/glibc-2.14.1/sysdeps/unix/sysv/linux/riscv/sys/syscall.h b/glibc-2.14.1/sysdeps/unix/sysv/linux/riscv/sys/syscall.h -new file mode 100644 -index 0000000..57d646e ---- /dev/null -+++ glibc-2.14.1/sysdeps/unix/sysv/linux/riscv/sys/syscall.h -@@ -0,0 +1,35 @@ -+/* Copyright (C) 1995, 1996, 1997, 2003 Free Software Foundation, Inc. -+ This file is part of the GNU C Library. -+ -+ The GNU C Library is free software; you can redistribute it and/or -+ modify it under the terms of the GNU Lesser General Public -+ License as published by the Free Software Foundation; either -+ version 2.1 of the License, or (at your option) any later version. -+ -+ The GNU C Library is distributed in the hope that it will be useful, -+ but WITHOUT ANY WARRANTY; without even the implied warranty of -+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU -+ Lesser General Public License for more details. -+ -+ You should have received a copy of the GNU Lesser General Public -+ License along with the GNU C Library; if not, write to the Free -+ Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA -+ 02111-1307 USA. */ -+ -+#ifndef _SYSCALL_H -+#define _SYSCALL_H 1 -+ -+/* This file should list the numbers of the system the system knows. -+ But instead of duplicating this we use the information available -+ from the kernel sources. */ -+#include -+ -+#ifndef _LIBC -+/* The Linux kernel header file defines macros `__NR_', but some -+ programs expect the traditional form `SYS_'. So in building libc -+ we scan the kernel's list and produce with macros for -+ all the `SYS_' names. */ -+# include -+#endif -+ -+#endif -diff --git a/glibc-2.14.1/sysdeps/unix/sysv/linux/riscv/sys/sysmips.h b/glibc-2.14.1/sysdeps/unix/sysv/linux/riscv/sys/sysmips.h -new file mode 100644 -index 0000000..aefc52e ---- /dev/null -+++ glibc-2.14.1/sysdeps/unix/sysv/linux/riscv/sys/sysmips.h -@@ -0,0 +1,43 @@ -+/* Copyright (C) 1995, 1997, 2000, 2001, 2009 Free Software Foundation, Inc. -+ This file is part of the GNU C Library. -+ -+ The GNU C Library is free software; you can redistribute it and/or -+ modify it under the terms of the GNU Lesser General Public -+ License as published by the Free Software Foundation; either -+ version 2.1 of the License, or (at your option) any later version. -+ -+ The GNU C Library is distributed in the hope that it will be useful, -+ but WITHOUT ANY WARRANTY; without even the implied warranty of -+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU -+ Lesser General Public License for more details. -+ -+ You should have received a copy of the GNU Lesser General Public -+ License along with the GNU C Library; if not, write to the Free -+ Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA -+ 02111-1307 USA. */ -+ -+#ifndef _SYS_SYSMIPS_H -+#define _SYS_SYSMIPS_H 1 -+ -+#include -+ -+/* -+ * Commands for the sysmips(2) call -+ * -+ * sysmips(2) is deprecated - though some existing software uses it. -+ * We only support the following commands. Sysmips exists for compatibility -+ * purposes only so new software should avoid it. -+ */ -+#define SETNAME 1 /* set hostname */ -+#define FLUSH_CACHE 3 /* writeback and invalidate caches */ -+#define MIPS_FIXADE 7 /* control address error fixing */ -+#define MIPS_RDNVRAM 10 /* read NVRAM */ -+#define MIPS_ATOMIC_SET 2001 /* atomically set variable */ -+ -+__BEGIN_DECLS -+ -+extern int sysmips (__const int __cmd, ...) __THROW; -+ -+__END_DECLS -+ -+#endif /* sys/sysmips.h */ -diff --git a/glibc-2.14.1/sysdeps/unix/sysv/linux/riscv/sys/tas.h b/glibc-2.14.1/sysdeps/unix/sysv/linux/riscv/sys/tas.h -new file mode 100644 -index 0000000..8f27db2 ---- /dev/null -+++ glibc-2.14.1/sysdeps/unix/sysv/linux/riscv/sys/tas.h -@@ -0,0 +1,51 @@ -+/* Copyright (C) 2000, 2002, 2003, 2004, 2007, 2009 -+ Free Software Foundation, Inc. -+ This file is part of the GNU C Library. -+ Contributed by Maciej W. Rozycki , 2000. -+ -+ The GNU C Library is free software; you can redistribute it and/or -+ modify it under the terms of the GNU Lesser General Public -+ License as published by the Free Software Foundation; either -+ version 2.1 of the License, or (at your option) any later version. -+ -+ The GNU C Library is distributed in the hope that it will be useful, -+ but WITHOUT ANY WARRANTY; without even the implied warranty of -+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU -+ Lesser General Public License for more details. -+ -+ You should have received a copy of the GNU Lesser General Public -+ License along with the GNU C Library; if not, write to the Free -+ Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA -+ 02111-1307 USA. */ -+ -+#ifndef _SYS_TAS_H -+#define _SYS_TAS_H 1 -+ -+#include -+#include -+ -+__BEGIN_DECLS -+ -+extern int _test_and_set (int *__p, int __v) __THROW; -+ -+#ifdef __USE_EXTERN_INLINES -+ -+# ifndef _EXTERN_INLINE -+# define _EXTERN_INLINE __extern_inline -+# endif -+ -+_EXTERN_INLINE int -+__NTH (_test_and_set (int *__p, int __v)) -+{ -+ int __r = __sync_lock_test_and_set(__p, __v); -+ -+ __sync_synchronize(); -+ -+ return __r; -+} -+ -+#endif /* __USE_EXTERN_INLINES */ -+ -+__END_DECLS -+ -+#endif /* sys/tas.h */ -diff --git a/glibc-2.14.1/sysdeps/unix/sysv/linux/riscv/sys/timerfd.h b/glibc-2.14.1/sysdeps/unix/sysv/linux/riscv/sys/timerfd.h -new file mode 100644 -index 0000000..ebd37ff ---- /dev/null -+++ glibc-2.14.1/sysdeps/unix/sysv/linux/riscv/sys/timerfd.h -@@ -0,0 +1,60 @@ -+/* Copyright (C) 2008 Free Software Foundation, Inc. -+ This file is part of the GNU C Library. -+ -+ The GNU C Library is free software; you can redistribute it and/or -+ modify it under the terms of the GNU Lesser General Public -+ License as published by the Free Software Foundation; either -+ version 2.1 of the License, or (at your option) any later version. -+ -+ The GNU C Library is distributed in the hope that it will be useful, -+ but WITHOUT ANY WARRANTY; without even the implied warranty of -+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU -+ Lesser General Public License for more details. -+ -+ You should have received a copy of the GNU Lesser General Public -+ License along with the GNU C Library; if not, write to the Free -+ Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA -+ 02111-1307 USA. */ -+ -+#ifndef _SYS_TIMERFD_H -+#define _SYS_TIMERFD_H 1 -+ -+#include -+ -+ -+/* Bits to be set in the FLAGS parameter of `timerfd_create'. */ -+enum -+ { -+ TFD_CLOEXEC = 02000000, -+#define TFD_CLOEXEC TFD_CLOEXEC -+ TFD_NONBLOCK = 0200 -+#define TFD_NONBLOCK TFD_NONBLOCK -+ }; -+ -+ -+/* Bits to be set in the FLAGS parameter of `timerfd_settime'. */ -+enum -+ { -+ TFD_TIMER_ABSTIME = 1 << 0 -+#define TFD_TIMER_ABSTIME TFD_TIMER_ABSTIME -+ }; -+ -+ -+__BEGIN_DECLS -+ -+/* Return file descriptor for new interval timer source. */ -+extern int timerfd_create (clockid_t __clock_id, int __flags) __THROW; -+ -+/* Set next expiration time of interval timer source UFD to UTMR. If -+ FLAGS has the TFD_TIMER_ABSTIME flag set the timeout value is -+ absolute. Optionally return the old expiration time in OTMR. */ -+extern int timerfd_settime (int __ufd, int __flags, -+ __const struct itimerspec *__utmr, -+ struct itimerspec *__otmr) __THROW; -+ -+/* Return the next expiration time of UFD. */ -+extern int timerfd_gettime (int __ufd, struct itimerspec *__otmr) __THROW; -+ -+__END_DECLS -+ -+#endif /* sys/timerfd.h */ -diff --git a/glibc-2.14.1/sysdeps/unix/sysv/linux/riscv/sys/ucontext.h b/glibc-2.14.1/sysdeps/unix/sysv/linux/riscv/sys/ucontext.h -new file mode 100644 -index 0000000..b81ce52 ---- /dev/null -+++ glibc-2.14.1/sysdeps/unix/sysv/linux/riscv/sys/ucontext.h -@@ -0,0 +1,66 @@ -+/* Copyright (C) 1997, 1998, 2000, 2003, 2004, 2006, 2009 Free Software -+ Foundation, Inc. This file is part of the GNU C Library. -+ -+ The GNU C Library is free software; you can redistribute it and/or -+ modify it under the terms of the GNU Lesser General Public -+ License as published by the Free Software Foundation; either -+ version 2.1 of the License, or (at your option) any later version. -+ -+ The GNU C Library is distributed in the hope that it will be useful, -+ but WITHOUT ANY WARRANTY; without even the implied warranty of -+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU -+ Lesser General Public License for more details. -+ -+ You should have received a copy of the GNU Lesser General Public -+ License along with the GNU C Library; if not, write to the Free -+ Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA -+ 02111-1307 USA. */ -+ -+/* Don't rely on this, the interface is currently messed up and may need to -+ be broken to be fixed. */ -+#ifndef _SYS_UCONTEXT_H -+#define _SYS_UCONTEXT_H 1 -+ -+#include -+#include -+ -+/* We need the signal context definitions even if they are not used -+ included in . */ -+#include -+ -+/* Type for general register. Even in o32 we assume 64-bit registers, -+ like the kernel. */ -+__extension__ typedef unsigned long long int greg_t; -+ -+/* Number of general registers. */ -+#define NGREG 32 -+#define NFPREG 32 -+ -+#define REG_PC 0 -+#define REG_RA 1 -+#define REG_S0 2 -+#define REG_A0 18 -+#define REG_NARGS 8 -+#define REG_SP 14 -+#define REG_TP 15 -+ -+/* Container for all general registers. */ -+typedef greg_t gregset_t[NGREG]; -+ -+/* Container for all FPU registers. */ -+typedef double fpregset_t[NFPREG]; -+ -+/* Context to describe whole processor state. */ -+typedef struct sigcontext mcontext_t; -+ -+/* Userlevel context. */ -+typedef struct ucontext -+ { -+ unsigned long int uc_flags; -+ struct ucontext *uc_link; -+ stack_t uc_stack; -+ mcontext_t uc_mcontext; -+ __sigset_t uc_sigmask; -+ } ucontext_t; -+ -+#endif /* sys/ucontext.h */ -diff --git a/glibc-2.14.1/sysdeps/unix/sysv/linux/riscv/sys/user.h b/glibc-2.14.1/sysdeps/unix/sysv/linux/riscv/sys/user.h -new file mode 100644 -index 0000000..5522050 ---- /dev/null -+++ glibc-2.14.1/sysdeps/unix/sysv/linux/riscv/sys/user.h -@@ -0,0 +1,219 @@ -+/* Copyright (C) 2002, 2003, 2004 Free Software Foundation, Inc. -+ This file is part of the GNU C Library. -+ -+ The GNU C Library is free software; you can redistribute it and/or -+ modify it under the terms of the GNU Lesser General Public -+ License as published by the Free Software Foundation; either -+ version 2.1 of the License, or (at your option) any later version. -+ -+ The GNU C Library is distributed in the hope that it will be useful, -+ but WITHOUT ANY WARRANTY; without even the implied warranty of -+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU -+ Lesser General Public License for more details. -+ -+ You should have received a copy of the GNU Lesser General Public -+ License along with the GNU C Library; if not, write to the Free -+ Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA -+ 02111-1307 USA. */ -+ -+#ifndef _SYS_USER_H -+#define _SYS_USER_H 1 -+ -+#include -+ -+/* The whole purpose of this file is for GDB and GDB only. Don't read -+ too much into it. Don't use it for anything other than GDB unless -+ you know what you are doing. */ -+ -+/* #include */ -+/* Instead of including the kernel header, that will vary depending on -+ whether the 32- or the 64-bit kernel is installed, we paste its -+ contents here. Note that the fact that the file is inline here, -+ instead of included separately, doesn't change in any way the -+ licensing status of a program that includes user.h. Since this is -+ for gdb alone, and gdb is GPLed, no surprises here. */ -+#if _RISCV_SIM == _ABIO32 -+/* -+ * Various register offset definitions for debuggers, core file -+ * examiners and whatnot. -+ * -+ * This file is subject to the terms and conditions of the GNU General Public -+ * License. See the file "COPYING" in the main directory of this archive -+ * for more details. -+ * -+ * Copyright (C) 1995, 1999 by Ralf Baechle -+ */ -+#ifndef __ASM_MIPS_REG_H -+#define __ASM_MIPS_REG_H -+ -+/* -+ * This defines/structures correspond to the register layout on stack - -+ * if the order here is changed, it needs to be updated in -+ * include/asm-mips/stackframe.h -+ */ -+#define EF_REG0 6 -+#define EF_REG1 7 -+#define EF_REG2 8 -+#define EF_REG3 9 -+#define EF_REG4 10 -+#define EF_REG5 11 -+#define EF_REG6 12 -+#define EF_REG7 13 -+#define EF_REG8 14 -+#define EF_REG9 15 -+#define EF_REG10 16 -+#define EF_REG11 17 -+#define EF_REG12 18 -+#define EF_REG13 19 -+#define EF_REG14 20 -+#define EF_REG15 21 -+#define EF_REG16 22 -+#define EF_REG17 23 -+#define EF_REG18 24 -+#define EF_REG19 25 -+#define EF_REG20 26 -+#define EF_REG21 27 -+#define EF_REG22 28 -+#define EF_REG23 29 -+#define EF_REG24 30 -+#define EF_REG25 31 -+/* -+ * k0/k1 unsaved -+ */ -+#define EF_REG28 34 -+#define EF_REG29 35 -+#define EF_REG30 36 -+#define EF_REG31 37 -+ -+/* -+ * Saved special registers -+ */ -+#define EF_LO 38 -+#define EF_HI 39 -+ -+#define EF_CP0_EPC 40 -+#define EF_CP0_BADVADDR 41 -+#define EF_CP0_STATUS 42 -+#define EF_CP0_CAUSE 43 -+ -+#define EF_SIZE 180 /* size in bytes */ -+ -+#endif /* __ASM_MIPS_REG_H */ -+ -+#else /* _RISCV_SIM != _ABIO32 */ -+ -+/* -+ * Various register offset definitions for debuggers, core file -+ * examiners and whatnot. -+ * -+ * This file is subject to the terms and conditions of the GNU General Public -+ * License. See the file "COPYING" in the main directory of this archive -+ * for more details. -+ * -+ * Copyright (C) 1995, 1999 Ralf Baechle -+ * Copyright (C) 1995, 1999 Silicon Graphics -+ */ -+#ifndef _ASM_REG_H -+#define _ASM_REG_H -+ -+/* -+ * This defines/structures correspond to the register layout on stack - -+ * if the order here is changed, it needs to be updated in -+ * include/asm-mips/stackframe.h -+ */ -+#define EF_REG0 0 -+#define EF_REG1 1 -+#define EF_REG2 2 -+#define EF_REG3 3 -+#define EF_REG4 4 -+#define EF_REG5 5 -+#define EF_REG6 6 -+#define EF_REG7 7 -+#define EF_REG8 8 -+#define EF_REG9 9 -+#define EF_REG10 10 -+#define EF_REG11 11 -+#define EF_REG12 12 -+#define EF_REG13 13 -+#define EF_REG14 14 -+#define EF_REG15 15 -+#define EF_REG16 16 -+#define EF_REG17 17 -+#define EF_REG18 18 -+#define EF_REG19 19 -+#define EF_REG20 20 -+#define EF_REG21 21 -+#define EF_REG22 22 -+#define EF_REG23 23 -+#define EF_REG24 24 -+#define EF_REG25 25 -+/* -+ * k0/k1 unsaved -+ */ -+#define EF_REG28 28 -+#define EF_REG29 29 -+#define EF_REG30 30 -+#define EF_REG31 31 -+ -+/* -+ * Saved special registers -+ */ -+#define EF_LO 32 -+#define EF_HI 33 -+ -+#define EF_CP0_EPC 34 -+#define EF_CP0_BADVADDR 35 -+#define EF_CP0_STATUS 36 -+#define EF_CP0_CAUSE 37 -+ -+#define EF_SIZE 304 /* size in bytes */ -+ -+#endif /* _ASM_REG_H */ -+ -+#endif /* _RISCV_SIM != _ABIO32 */ -+ -+#if _RISCV_SIM == _ABIO32 -+ -+struct user -+{ -+ unsigned long regs[EF_SIZE/4+64]; /* integer and fp regs */ -+ size_t u_tsize; /* text size (pages) */ -+ size_t u_dsize; /* data size (pages) */ -+ size_t u_ssize; /* stack size (pages) */ -+ unsigned long start_code; /* text starting address */ -+ unsigned long start_data; /* data starting address */ -+ unsigned long start_stack; /* stack starting address */ -+ long int signal; /* signal causing core dump */ -+ void* u_ar0; /* help gdb find registers */ -+ unsigned long magic; /* identifies a core file */ -+ char u_comm[32]; /* user command name */ -+}; -+ -+#else -+ -+struct user { -+ __extension__ unsigned long regs[EF_SIZE/8+64]; /* integer and fp regs */ -+ __extension__ unsigned long u_tsize; /* text size (pages) */ -+ __extension__ unsigned long u_dsize; /* data size (pages) */ -+ __extension__ unsigned long u_ssize; /* stack size (pages) */ -+ __extension__ unsigned long long start_code; /* text starting address */ -+ __extension__ unsigned long long start_data; /* data starting address */ -+ __extension__ unsigned long long start_stack; /* stack starting address */ -+ __extension__ long long signal; /* signal causing core dump */ -+ __extension__ unsigned long long u_ar0; /* help gdb find registers */ -+ __extension__ unsigned long long magic; /* identifies a core file */ -+ char u_comm[32]; /* user command name */ -+}; -+ -+#endif -+ -+#define PAGE_SHIFT 12 -+#define PAGE_SIZE (1UL << PAGE_SHIFT) -+#define PAGE_MASK (~(PAGE_SIZE-1)) -+#define NBPG PAGE_SIZE -+#define UPAGES 1 -+#define HOST_TEXT_START_ADDR (u.start_code) -+#define HOST_DATA_START_ADDR (u.start_data) -+#define HOST_STACK_END_ADDR (u.start_stack + u.u_ssize * NBPG) -+ -+#endif /* _SYS_USER_H */ -diff --git a/glibc-2.14.1/sysdeps/unix/sysv/linux/riscv/syscall.c b/glibc-2.14.1/sysdeps/unix/sysv/linux/riscv/syscall.c -new file mode 100644 -index 0000000..0dcf09f ---- /dev/null -+++ glibc-2.14.1/sysdeps/unix/sysv/linux/riscv/syscall.c -@@ -0,0 +1,36 @@ -+/* Copyright (C) 2001, 2002, 2003, 2005 Free Software Foundation, Inc. -+ This file is part of the GNU C Library. -+ -+ The GNU C Library is free software; you can redistribute it and/or -+ modify it under the terms of the GNU Lesser General Public -+ License as published by the Free Software Foundation; either -+ version 2.1 of the License, or (at your option) any later version. -+ -+ The GNU C Library is distributed in the hope that it will be useful, -+ but WITHOUT ANY WARRANTY; without even the implied warranty of -+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU -+ Lesser General Public License for more details. -+ -+ You should have received a copy of the GNU Lesser General Public -+ License along with the GNU C Library; if not, write to the Free -+ Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA -+ 02111-1307 USA. */ -+ -+#include -+ -+long syscall (long syscall_number, long arg1, long arg2, long arg3, -+ long arg4, long arg5, long arg6, long arg7) -+{ -+ long ret, err; -+ -+ ret = INTERNAL_SYSCALL_NCS(syscall_number, err, 7, arg1, arg2, arg3, arg4, -+ arg5, arg6, arg7); -+ -+ if (INTERNAL_SYSCALL_ERROR_P(ret, err)) -+ { -+ __set_errno(INTERNAL_SYSCALL_ERRNO(ret, err)); -+ ret = -1; -+ } -+ -+ return ret; -+} -diff --git a/glibc-2.14.1/sysdeps/unix/sysv/linux/riscv/syscalls.list b/glibc-2.14.1/sysdeps/unix/sysv/linux/riscv/syscalls.list -new file mode 100644 -index 0000000..518f2a2 ---- /dev/null -+++ glibc-2.14.1/sysdeps/unix/sysv/linux/riscv/syscalls.list -@@ -0,0 +1,31 @@ -+# File name Caller Syscall name Args Strong name Weak names -+ -+# -+# Calls for compatibility with existing MIPS OS implementations and -+# compilers. -+# -+cachectl - cachectl i:pii __cachectl cachectl -+cacheflush - cacheflush i:pii _flush_cache cacheflush -+sysmips - sysmips i:iiii __sysmips sysmips -+ -+# -+# Socket functions; Linux/MIPS doesn't use the socketcall(2) wrapper; -+# it's provided for compatibility, though. -+# -+accept - accept Ci:iBN __libc_accept __accept accept -+bind - bind i:ipi __bind bind -+connect - connect Ci:ipi __libc_connect __connect_internal __connect connect -+getpeername - getpeername i:ipp __getpeername getpeername -+getsockname - getsockname i:ipp __getsockname getsockname -+getsockopt - getsockopt i:iiiBN __getsockopt getsockopt -+listen - listen i:ii __listen listen -+recv - recv Ci:ibni __libc_recv __recv recv -+recvfrom - recvfrom Ci:ibniBN __libc_recvfrom __recvfrom recvfrom -+recvmsg - recvmsg Ci:ipi __libc_recvmsg __recvmsg recvmsg -+send - send Ci:ibni __libc_send __send send -+sendmsg - sendmsg Ci:ipi __libc_sendmsg __sendmsg sendmsg -+sendto - sendto Ci:ibnibn __libc_sendto __sendto sendto -+setsockopt - setsockopt i:iiibn __setsockopt setsockopt -+shutdown - shutdown i:ii __shutdown shutdown -+socket - socket i:iii __socket socket -+socketpair - socketpair i:iiif __socketpair socketpair -diff --git a/glibc-2.14.1/sysdeps/unix/sysv/linux/riscv/sysdep.h b/glibc-2.14.1/sysdeps/unix/sysv/linux/riscv/sysdep.h -new file mode 100644 -index 0000000..782cb94 ---- /dev/null -+++ glibc-2.14.1/sysdeps/unix/sysv/linux/riscv/sysdep.h -@@ -0,0 +1,247 @@ -+/* Copyright (C) 2000, 2002, 2003, 2004, 2005, 2006, 2009 -+ Free Software Foundation, Inc. -+ This file is part of the GNU C Library. -+ -+ The GNU C Library is free software; you can redistribute it and/or -+ modify it under the terms of the GNU Lesser General Public -+ License as published by the Free Software Foundation; either -+ version 2.1 of the License, or (at your option) any later version. -+ -+ The GNU C Library is distributed in the hope that it will be useful, -+ but WITHOUT ANY WARRANTY; without even the implied warranty of -+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU -+ Lesser General Public License for more details. -+ -+ You should have received a copy of the GNU Lesser General Public -+ License along with the GNU C Library; if not, write to the Free -+ Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA -+ 02111-1307 USA. */ -+ -+#ifndef _LINUX_MIPS_SYSDEP_H -+#define _LINUX_MIPS_SYSDEP_H 1 -+ -+/* There is some commonality. */ -+#include -+ -+#include -+ -+/* In order to get __set_errno() definition in INLINE_SYSCALL. */ -+#ifndef __ASSEMBLER__ -+#include -+#endif -+ -+/* For Linux we can use the system call table in the header file -+ /usr/include/asm/unistd.h -+ of the kernel. But these symbols do not follow the SYS_* syntax -+ so we have to redefine the `SYS_ify' macro here. */ -+#undef SYS_ify -+#ifdef __STDC__ -+# define SYS_ify(syscall_name) __NR_##syscall_name -+#else -+# define SYS_ify(syscall_name) __NR_/**/syscall_name -+#endif -+ -+#ifdef __ASSEMBLER__ -+ -+/* We don't want the label for the error handler to be visible in the symbol -+ table when we define it here. */ -+#ifdef __PIC__ -+# define SYSCALL_ERROR_LABEL 99b -+#endif -+ -+#else /* ! __ASSEMBLER__ */ -+ -+/* Define a macro which expands into the inline wrapper code for a system -+ call. */ -+#undef INLINE_SYSCALL -+#define INLINE_SYSCALL(name, nr, args...) \ -+ ({ INTERNAL_SYSCALL_DECL(err); \ -+ long result_var = INTERNAL_SYSCALL (name, err, nr, args); \ -+ if ( INTERNAL_SYSCALL_ERROR_P (result_var, err) ) \ -+ { \ -+ __set_errno (INTERNAL_SYSCALL_ERRNO (result_var, err)); \ -+ result_var = -1L; \ -+ } \ -+ result_var; }) -+ -+#undef INTERNAL_SYSCALL_DECL -+#define INTERNAL_SYSCALL_DECL(err) do { } while (0) -+ -+#undef INTERNAL_SYSCALL_ERROR_P -+#define INTERNAL_SYSCALL_ERROR_P(val, err) ((long) (val) < 0) -+ -+#undef INTERNAL_SYSCALL_ERRNO -+#define INTERNAL_SYSCALL_ERRNO(val, err) (-val) -+ -+#undef INTERNAL_SYSCALL -+#define INTERNAL_SYSCALL(name, err, nr, args...) \ -+ internal_syscall##nr (SYS_ify (name), err, args) -+ -+#undef INTERNAL_SYSCALL_NCS -+#define INTERNAL_SYSCALL_NCS(number, err, nr, args...) \ -+ internal_syscall##nr (number, err, args) -+ -+#define internal_syscall0(number, err, dummy...) \ -+({ \ -+ long _sys_result; \ -+ \ -+ { \ -+ register long __v0 asm("v0") = number; \ -+ __asm__ volatile ( \ -+ "scall\n\t" \ -+ : "+r" (__v0) \ -+ : "r" (__v0) \ -+ : __SYSCALL_CLOBBERS); \ -+ _sys_result = __v0; \ -+ } \ -+ _sys_result; \ -+}) -+ -+#define internal_syscall1(number, err, arg0) \ -+({ \ -+ long _sys_result; \ -+ \ -+ { \ -+ register long __v0 asm("v0") = number; \ -+ register long __a0 asm("a0") = (long) (arg0); \ -+ __asm__ volatile ( \ -+ "scall\n\t" \ -+ : "+r" (__v0) \ -+ : "r" (__v0), "r"(__a0) \ -+ : __SYSCALL_CLOBBERS); \ -+ _sys_result = __v0; \ -+ } \ -+ _sys_result; \ -+}) -+ -+#define internal_syscall2(number, err, arg0, arg1) \ -+({ \ -+ long _sys_result; \ -+ \ -+ { \ -+ register long __v0 asm("v0") = number; \ -+ register long __a0 asm("a0") = (long) (arg0); \ -+ register long __a1 asm("a1") = (long) (arg1); \ -+ __asm__ volatile ( \ -+ "scall\n\t" \ -+ : "+r" (__v0) \ -+ : "r" (__v0), "r"(__a0), "r"(__a1) \ -+ : __SYSCALL_CLOBBERS); \ -+ _sys_result = __v0; \ -+ } \ -+ _sys_result; \ -+}) -+ -+#define internal_syscall3(number, err, arg0, arg1, arg2) \ -+({ \ -+ long _sys_result; \ -+ \ -+ { \ -+ register long __v0 asm("v0") = number; \ -+ register long __a0 asm("a0") = (long) (arg0); \ -+ register long __a1 asm("a1") = (long) (arg1); \ -+ register long __a2 asm("a2") = (long) (arg2); \ -+ __asm__ volatile ( \ -+ "scall\n\t" \ -+ : "+r" (__v0) \ -+ : "r" (__v0), "r"(__a0), "r"(__a1), "r"(__a2) \ -+ : __SYSCALL_CLOBBERS); \ -+ _sys_result = __v0; \ -+ } \ -+ _sys_result; \ -+}) -+ -+#define internal_syscall4(number, err, arg0, arg1, arg2, arg3) \ -+({ \ -+ long _sys_result; \ -+ \ -+ { \ -+ register long __v0 asm("v0") = number; \ -+ register long __a0 asm("a0") = (long) (arg0); \ -+ register long __a1 asm("a1") = (long) (arg1); \ -+ register long __a2 asm("a2") = (long) (arg2); \ -+ register long __a3 asm("a3") = (long) (arg3); \ -+ __asm__ volatile ( \ -+ "scall\n\t" \ -+ : "+r" (__v0) \ -+ : "r" (__v0), "r"(__a0), "r"(__a1), "r"(__a2), "r"(__a3) \ -+ : __SYSCALL_CLOBBERS); \ -+ _sys_result = __v0; \ -+ } \ -+ _sys_result; \ -+}) -+ -+#define internal_syscall5(number, err, arg0, arg1, arg2, arg3, arg4) \ -+({ \ -+ long _sys_result; \ -+ \ -+ { \ -+ register long __v0 asm("v0") = number; \ -+ register long __a0 asm("a0") = (long) (arg0); \ -+ register long __a1 asm("a1") = (long) (arg1); \ -+ register long __a2 asm("a2") = (long) (arg2); \ -+ register long __a3 asm("a3") = (long) (arg3); \ -+ register long __a4 asm("a4") = (long) (arg4); \ -+ __asm__ volatile ( \ -+ "scall\n\t" \ -+ : "+r" (__v0) \ -+ : "r" (__v0), "r"(__a0), "r"(__a1), "r"(__a2), "r"(__a3), "r"(__a4) \ -+ : __SYSCALL_CLOBBERS); \ -+ _sys_result = __v0; \ -+ } \ -+ _sys_result; \ -+}) -+ -+#define internal_syscall6(number, err, arg0, arg1, arg2, arg3, arg4, arg5) \ -+({ \ -+ long _sys_result; \ -+ \ -+ { \ -+ register long __v0 asm("v0") = number; \ -+ register long __a0 asm("a0") = (long) (arg0); \ -+ register long __a1 asm("a1") = (long) (arg1); \ -+ register long __a2 asm("a2") = (long) (arg2); \ -+ register long __a3 asm("a3") = (long) (arg3); \ -+ register long __a4 asm("a4") = (long) (arg4); \ -+ register long __a5 asm("a5") = (long) (arg5); \ -+ __asm__ volatile ( \ -+ "scall\n\t" \ -+ : "+r" (__v0) \ -+ : "r" (__v0), "r"(__a0), "r"(__a1), "r"(__a2), "r"(__a3), "r"(__a4), "r"(__a5) \ -+ : __SYSCALL_CLOBBERS); \ -+ _sys_result = __v0; \ -+ } \ -+ _sys_result; \ -+}) -+ -+#define internal_syscall7(number, err, arg0, arg1, arg2, arg3, arg4, arg5, arg6) \ -+({ \ -+ long _sys_result; \ -+ \ -+ { \ -+ register long __v0 asm("v0") = number; \ -+ register long __a0 asm("a0") = (long) (arg0); \ -+ register long __a1 asm("a1") = (long) (arg1); \ -+ register long __a2 asm("a2") = (long) (arg2); \ -+ register long __a3 asm("a3") = (long) (arg3); \ -+ register long __a4 asm("a4") = (long) (arg4); \ -+ register long __a5 asm("a5") = (long) (arg5); \ -+ register long __a6 asm("a6") = (long) (arg6); \ -+ __asm__ volatile ( \ -+ "scall\n\t" \ -+ : "+r" (__v0) \ -+ : "r" (__v0), "r"(__a0), "r"(__a1), "r"(__a2), "r"(__a3), "r"(__a4), "r"(__a5), "r"(__a6) \ -+ : __SYSCALL_CLOBBERS); \ -+ _sys_result = __v0; \ -+ } \ -+ _sys_result; \ -+}) -+ -+#define __SYSCALL_CLOBBERS "v1", "memory" -+#endif /* __ASSEMBLER__ */ -+ -+/* Pointer mangling is not supported. */ -+#define PTR_MANGLE(var) (void) (var) -+#define PTR_DEMANGLE(var) (void) (var) -+ -+#endif /* linux/mips/sysdep.h */ -diff --git a/glibc-2.14.1/sysdeps/unix/sysv/linux/riscv/truncate64.c b/glibc-2.14.1/sysdeps/unix/sysv/linux/riscv/truncate64.c -new file mode 100644 -index 0000000..01cc148 ---- /dev/null -+++ glibc-2.14.1/sysdeps/unix/sysv/linux/riscv/truncate64.c -@@ -0,0 +1,76 @@ -+/* Copyright (C) 1997,1998,1999,2000,2002,2003,2005,2006 -+ Free Software Foundation, Inc. -+ This file is part of the GNU C Library. -+ -+ The GNU C Library is free software; you can redistribute it and/or -+ modify it under the terms of the GNU Lesser General Public -+ License as published by the Free Software Foundation; either -+ version 2.1 of the License, or (at your option) any later version. -+ -+ The GNU C Library is distributed in the hope that it will be useful, -+ but WITHOUT ANY WARRANTY; without even the implied warranty of -+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU -+ Lesser General Public License for more details. -+ -+ You should have received a copy of the GNU Lesser General Public -+ License along with the GNU C Library; if not, write to the Free -+ Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA -+ 02111-1307 USA. */ -+ -+#include -+#include -+#include -+#include -+ -+#include -+#include -+#include -+ -+#include -+ -+#ifdef __NR_truncate64 -+#ifndef __ASSUME_TRUNCATE64_SYSCALL -+/* The variable is shared between all wrappers around *truncate64 calls. */ -+int __have_no_truncate64; -+#endif -+ -+/* Truncate the file FD refers to to LENGTH bytes. */ -+int -+truncate64 (const char *path, off64_t length) -+{ -+#ifndef __ASSUME_TRUNCATE64_SYSCALL -+ if (! __have_no_truncate64) -+#endif -+ { -+ unsigned int low = length & 0xffffffff; -+ unsigned int high = length >> 32; -+#ifndef __ASSUME_TRUNCATE64_SYSCALL -+ int saved_errno = errno; -+#endif -+ int result = INLINE_SYSCALL (truncate64, 4, CHECK_STRING (path), 0, -+ __LONG_LONG_PAIR (high, low)); -+#ifndef __ASSUME_TRUNCATE64_SYSCALL -+ if (result != -1 || errno != ENOSYS) -+#endif -+ return result; -+ -+#ifndef __ASSUME_TRUNCATE64_SYSCALL -+ __set_errno (saved_errno); -+ __have_no_truncate64 = 1; -+#endif -+ } -+ -+#ifndef __ASSUME_TRUNCATE64_SYSCALL -+ if ((off_t) length != length) -+ { -+ __set_errno (EINVAL); -+ return -1; -+ } -+ return truncate (path, (off_t) length); -+#endif -+} -+ -+#else -+/* Use the generic implementation. */ -+# include -+#endif -diff --git a/glibc-2.14.1/sysdeps/unix/sysv/linux/riscv/ucontext_i.sym b/glibc-2.14.1/sysdeps/unix/sysv/linux/riscv/ucontext_i.sym -new file mode 100644 -index 0000000..8eddf9a ---- /dev/null -+++ glibc-2.14.1/sysdeps/unix/sysv/linux/riscv/ucontext_i.sym -@@ -0,0 +1,42 @@ -+#include -+#include -+#include -+#include -+ -+#include -+ -+-- Constants used by the rt_sigprocmask call. -+ -+SIG_BLOCK -+SIG_SETMASK -+ -+_NSIG8 (_NSIG / 8) -+ -+-- Offsets of the fields in the kernel rt_sigframe_t structure. -+#define rt_sigframe(member) offsetof (kernel_rt_sigframe_t, member) -+ -+RT_SIGFRAME_UCONTEXT rt_sigframe (rs_uc) -+ -+RT_SIGFRAME_SIZE sizeof (kernel_rt_sigframe_t) -+ -+-- Offsets of the fields in the ucontext_t structure. -+#define ucontext(member) offsetof (ucontext_t, member) -+#define stack(member) ucontext (uc_stack.member) -+#define mcontext(member) ucontext (uc_mcontext.member) -+ -+UCONTEXT_FLAGS ucontext (uc_flags) -+UCONTEXT_LINK ucontext (uc_link) -+UCONTEXT_STACK ucontext (uc_stack) -+UCONTEXT_MCONTEXT ucontext (uc_mcontext) -+UCONTEXT_SIGMASK ucontext (uc_sigmask) -+ -+STACK_SP stack (ss_sp) -+STACK_SIZE stack (ss_size) -+STACK_FLAGS stack (ss_flags) -+ -+MCONTEXT_GREGS mcontext (gregs) -+MCONTEXT_FPREGS mcontext (fpregs) -+MCONTEXT_PC mcontext (gregs) -+MCONTEXT_FSR mcontext (fsr) -+ -+UCONTEXT_SIZE sizeof (ucontext_t) -diff --git a/glibc-2.14.1/sysdeps/unix/sysv/linux/riscv/ustat.c b/glibc-2.14.1/sysdeps/unix/sysv/linux/riscv/ustat.c -new file mode 100644 -index 0000000..a309f71 ---- /dev/null -+++ glibc-2.14.1/sysdeps/unix/sysv/linux/riscv/ustat.c -@@ -0,0 +1,37 @@ -+/* Copyright (C) 1997, 1998, 2000, 2003 Free Software Foundation, Inc. -+ This file is part of the GNU C Library. -+ Contributed by Ulrich Drepper , 1997. -+ -+ The GNU C Library is free software; you can redistribute it and/or -+ modify it under the terms of the GNU Lesser General Public -+ License as published by the Free Software Foundation; either -+ version 2.1 of the License, or (at your option) any later version. -+ -+ The GNU C Library is distributed in the hope that it will be useful, -+ but WITHOUT ANY WARRANTY; without even the implied warranty of -+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU -+ Lesser General Public License for more details. -+ -+ You should have received a copy of the GNU Lesser General Public -+ License along with the GNU C Library; if not, write to the Free -+ Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA -+ 02111-1307 USA. */ -+ -+#include -+#include -+#include -+ -+#include -+#include -+#include -+ -+int -+ustat (dev_t dev, struct ustat *ubuf) -+{ -+ unsigned long k_dev; -+ -+ /* We must convert the value to dev_t type used by the kernel. */ -+ k_dev = ((major (dev) & 0xff) << 8) | (minor (dev) & 0xff); -+ -+ return INLINE_SYSCALL (ustat, 2, k_dev, CHECK_1 (ubuf)); -+} -diff --git a/glibc-2.14.1/sysdeps/unix/sysv/linux/riscv/vfork.S b/glibc-2.14.1/sysdeps/unix/sysv/linux/riscv/vfork.S -new file mode 100644 -index 0000000..cc30fe5 ---- /dev/null -+++ glibc-2.14.1/sysdeps/unix/sysv/linux/riscv/vfork.S -@@ -0,0 +1,65 @@ -+/* Copyright (C) 2005 Free Software Foundation, Inc. -+ This file is part of the GNU C Library. -+ -+ The GNU C Library is free software; you can redistribute it and/or -+ modify it under the terms of the GNU Lesser General Public -+ License as published by the Free Software Foundation; either -+ version 2.1 of the License, or (at your option) any later version. -+ -+ The GNU C Library is distributed in the hope that it will be useful, -+ but WITHOUT ANY WARRANTY; without even the implied warranty of -+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU -+ Lesser General Public License for more details. -+ -+ You should have received a copy of the GNU Lesser General Public -+ License along with the GNU C Library; if not, write to the Free -+ Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA -+ 02111-1307 USA. */ -+ -+/* vfork() is just a special case of clone(). */ -+ -+#include -+#include -+#include -+#include -+ -+#ifndef SAVE_PID -+#define SAVE_PID -+#endif -+ -+#ifndef RESTORE_PID -+#define RESTORE_PID -+#endif -+ -+ -+/* int vfork() */ -+ -+ .text -+LEAF(__vfork) -+ -+ SAVE_PID -+ -+ li a0, 0x4111 /* CLONE_VM | CLONE_VFORK | SIGCHLD */ -+ move a1, sp -+ li a2, 0 -+ li a3, 0 -+ li a4, 0 -+ -+ /* Do the system call */ -+ li v0,__NR_clone -+ scall -+ -+ bltz v0,L(error) -+ -+ RESTORE_PID -+ -+ ret -+ -+ /* Something bad happened -- no child created. */ -+L(error): -+ j __syscall_error -+ -+ END(__vfork) -+ -+libc_hidden_def(__vfork) -+weak_alias (__vfork, vfork)