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recipes-kernel: Update to the 5.3 kernel

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Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
This commit is contained in:
Alistair Francis
2019-08-05 14:57:30 -07:00
committed by Khem Raj
parent 1b726bf8bb
commit df313e796d
13 changed files with 419 additions and 356 deletions
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6
recipes-kernel/linux/files/freedom-u540/0004-PCI-microsemi-Add-host-driver-for-Microsemi-PCIe-con.patch → recipes-kernel/linux/files/freedom-u540/0001-PCI-microsemi-Add-host-driver-for-Microsemi-PCIe-con.patch
View File

@@ -1,7 +1,7 @@
From 85fac9c69c09dd6d288b3a07960040e9aa4eb0ad Mon Sep 17 00:00:00 2001
From 3e5cd0fb40635b75140d8cc3b38d66eaaefcf901 Mon Sep 17 00:00:00 2001
From: Daire McNamara <daire.mcnamara@microchip.com>
Date: Fri, 15 Feb 2019 16:24:24 +0000
Subject: [PATCH 4/6] PCI: microsemi: Add host driver for Microsemi PCIe
Subject: [PATCH 1/4] PCI: microsemi: Add host driver for Microsemi PCIe
controller
This patch adds support to the Microsemi/Microchip PolarFire
@@ -17,7 +17,7 @@ Upstream-Status: Inappropriate [not author]
create mode 100644 drivers/pci/controller/pcie-microsemi.c
diff --git a/drivers/pci/controller/Kconfig b/drivers/pci/controller/Kconfig
index 011c57cae4b0..e22364792bca 100644
index fe9f9f13ce11..800b0b61dedf 100644
--- a/drivers/pci/controller/Kconfig
+++ b/drivers/pci/controller/Kconfig
@@ -281,5 +281,13 @@ config VMD

39
recipes-kernel/linux/files/freedom-u540/0001-macb-bindings-doc-add-sifive-fu540-c000-binding.patch
View File

@@ -1,39 +0,0 @@
From a4a5f99e31e85a6f159c62f224e826ed38f027e9 Mon Sep 17 00:00:00 2001
From: Yash Shah <yash.shah@sifive.com>
Date: Tue, 18 Jun 2019 13:26:07 +0530
Subject: [PATCH 1/6] macb: bindings doc: add sifive fu540-c000 binding
Add the compatibility string documentation for SiFive FU540-C0000
interface.
On the FU540, this driver also needs to read and write registers in a
management IP block that monitors or drives boundary signals for the
GEMGXL IP block that are not directly mapped to GEMGXL registers.
Therefore, add additional range to "reg" property for SiFive GEMGXL
management IP registers.
Signed-off-by: Yash Shah <yash.shah@sifive.com>
Reviewed-by: Paul Walmsley <paul.walmsley@sifive.com>
Upstream-Status: Accepted [5.3]
---
Documentation/devicetree/bindings/net/macb.txt | 3 +++
1 file changed, 3 insertions(+)
diff --git a/Documentation/devicetree/bindings/net/macb.txt b/Documentation/devicetree/bindings/net/macb.txt
index 9c5e94482b5f..63c73fafe26d 100644
--- a/Documentation/devicetree/bindings/net/macb.txt
+++ b/Documentation/devicetree/bindings/net/macb.txt
@@ -15,8 +15,11 @@ Required properties:
Use "atmel,sama5d4-gem" for the GEM IP (10/100) available on Atmel sama5d4 SoCs.
Use "cdns,zynq-gem" Xilinx Zynq-7xxx SoC.
Use "cdns,zynqmp-gem" for Zynq Ultrascale+ MPSoC.
+ Use "sifive,fu540-macb" for SiFive FU540-C000 SoC.
Or the generic form: "cdns,emac".
- reg: Address and length of the register set for the device
+ For "sifive,fu540-macb", second range is required to specify the
+ address and length of the registers for GEMGXL Management block.
- interrupts: Should contain macb interrupt
- phy-mode: See ethernet.txt file in the same directory.
- clock-names: Tuple listing input clock names.
--
2.22.0

4
recipes-kernel/linux/files/freedom-u540/0005-Microsemi-PCIe-expansion-board-DT-entry.patch → recipes-kernel/linux/files/freedom-u540/0002-Microsemi-PCIe-expansion-board-DT-entry.patch
View File

@@ -1,7 +1,7 @@
From b290b577a77f91233c0e68cab85436a8de2ebbd0 Mon Sep 17 00:00:00 2001
From b1103ea299e49c03555f12f080a1607969fd7e66 Mon Sep 17 00:00:00 2001
From: Atish Patra <atish.patra@wdc.com>
Date: Fri, 21 Jun 2019 12:36:21 -0700
Subject: [PATCH 5/6] Microsemi PCIe expansion board DT entry.
Subject: [PATCH 2/4] Microsemi PCIe expansion board DT entry.
Signed-off-by: Atish Patra <atish.patra@wdc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>

189
recipes-kernel/linux/files/freedom-u540/0002-macb-Add-support-for-SiFive-FU540-C000.patch
View File

@@ -1,189 +0,0 @@
From 4181aa6e771dcc09b62eb3495bd09bf151b8bd9d Mon Sep 17 00:00:00 2001
From: Yash Shah <yash.shah@sifive.com>
Date: Tue, 18 Jun 2019 13:26:08 +0530
Subject: [PATCH 2/6] macb: Add support for SiFive FU540-C000
The management IP block is tightly coupled with the Cadence MACB IP
block on the FU540, and manages many of the boundary signals from the
MACB IP. This patch only controls the tx_clk input signal to the MACB
IP. Future patches may add support for monitoring or controlling other
IP boundary signals.
Signed-off-by: Yash Shah <yash.shah@sifive.com>
Upstream-Status: Accepted [5.3]
---
drivers/net/ethernet/cadence/macb_main.c | 123 +++++++++++++++++++++++
1 file changed, 123 insertions(+)
diff --git a/drivers/net/ethernet/cadence/macb_main.c b/drivers/net/ethernet/cadence/macb_main.c
index 262a28ff81fc..111bf51a8405 100644
--- a/drivers/net/ethernet/cadence/macb_main.c
+++ b/drivers/net/ethernet/cadence/macb_main.c
@@ -7,6 +7,7 @@
#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
#include <linux/clk.h>
+#include <linux/clk-provider.h>
#include <linux/crc32.h>
#include <linux/module.h>
#include <linux/moduleparam.h>
@@ -37,6 +38,15 @@
#include <linux/pm_runtime.h>
#include "macb.h"
+/* This structure is only used for MACB on SiFive FU540 devices */
+struct sifive_fu540_macb_mgmt {
+ void __iomem *reg;
+ unsigned long rate;
+ struct clk_hw hw;
+};
+
+static struct sifive_fu540_macb_mgmt *mgmt;
+
#define MACB_RX_BUFFER_SIZE 128
#define RX_BUFFER_MULTIPLE 64 /* bytes */
@@ -3943,6 +3953,116 @@ static int at91ether_init(struct platform_device *pdev)
return 0;
}
+static unsigned long fu540_macb_tx_recalc_rate(struct clk_hw *hw,
+ unsigned long parent_rate)
+{
+ return mgmt->rate;
+}
+
+static long fu540_macb_tx_round_rate(struct clk_hw *hw, unsigned long rate,
+ unsigned long *parent_rate)
+{
+ if (WARN_ON(rate < 2500000))
+ return 2500000;
+ else if (rate == 2500000)
+ return 2500000;
+ else if (WARN_ON(rate < 13750000))
+ return 2500000;
+ else if (WARN_ON(rate < 25000000))
+ return 25000000;
+ else if (rate == 25000000)
+ return 25000000;
+ else if (WARN_ON(rate < 75000000))
+ return 25000000;
+ else if (WARN_ON(rate < 125000000))
+ return 125000000;
+ else if (rate == 125000000)
+ return 125000000;
+
+ WARN_ON(rate > 125000000);
+
+ return 125000000;
+}
+
+static int fu540_macb_tx_set_rate(struct clk_hw *hw, unsigned long rate,
+ unsigned long parent_rate)
+{
+ rate = fu540_macb_tx_round_rate(hw, rate, &parent_rate);
+ if (rate != 125000000)
+ iowrite32(1, mgmt->reg);
+ else
+ iowrite32(0, mgmt->reg);
+ mgmt->rate = rate;
+
+ return 0;
+}
+
+static const struct clk_ops fu540_c000_ops = {
+ .recalc_rate = fu540_macb_tx_recalc_rate,
+ .round_rate = fu540_macb_tx_round_rate,
+ .set_rate = fu540_macb_tx_set_rate,
+};
+
+static int fu540_c000_clk_init(struct platform_device *pdev, struct clk **pclk,
+ struct clk **hclk, struct clk **tx_clk,
+ struct clk **rx_clk, struct clk **tsu_clk)
+{
+ struct clk_init_data init;
+ int err = 0;
+
+ err = macb_clk_init(pdev, pclk, hclk, tx_clk, rx_clk, tsu_clk);
+ if (err)
+ return err;
+
+ mgmt = devm_kzalloc(&pdev->dev, sizeof(*mgmt), GFP_KERNEL);
+ if (!mgmt)
+ return -ENOMEM;
+
+ init.name = "sifive-gemgxl-mgmt";
+ init.ops = &fu540_c000_ops;
+ init.flags = 0;
+ init.num_parents = 0;
+
+ mgmt->rate = 0;
+ mgmt->hw.init = &init;
+
+ *tx_clk = clk_register(NULL, &mgmt->hw);
+ if (IS_ERR(*tx_clk))
+ return PTR_ERR(*tx_clk);
+
+ err = clk_prepare_enable(*tx_clk);
+ if (err)
+ dev_err(&pdev->dev, "failed to enable tx_clk (%u)\n", err);
+ else
+ dev_info(&pdev->dev, "Registered clk switch '%s'\n", init.name);
+
+ return 0;
+}
+
+static int fu540_c000_init(struct platform_device *pdev)
+{
+ struct resource *res;
+
+ res = platform_get_resource(pdev, IORESOURCE_MEM, 1);
+ if (!res)
+ return -ENODEV;
+
+ mgmt->reg = ioremap(res->start, resource_size(res));
+ if (!mgmt->reg)
+ return -ENOMEM;
+
+ return macb_init(pdev);
+}
+
+static const struct macb_config fu540_c000_config = {
+ .caps = MACB_CAPS_GIGABIT_MODE_AVAILABLE | MACB_CAPS_JUMBO |
+ MACB_CAPS_GEM_HAS_PTP,
+ .dma_burst_length = 16,
+ .clk_init = fu540_c000_clk_init,
+ .init = fu540_c000_init,
+ .jumbo_max_len = 10240,
+};
+
static const struct macb_config at91sam9260_config = {
.caps = MACB_CAPS_USRIO_HAS_CLKEN | MACB_CAPS_USRIO_DEFAULT_IS_MII_GMII,
.clk_init = macb_clk_init,
@@ -4032,6 +4152,7 @@ static const struct of_device_id macb_dt_ids[] = {
{ .compatible = "cdns,emac", .data = &emac_config },
{ .compatible = "cdns,zynqmp-gem", .data = &zynqmp_config},
{ .compatible = "cdns,zynq-gem", .data = &zynq_config },
+ { .compatible = "sifive,fu540-macb", .data = &fu540_c000_config },
{ /* sentinel */ }
};
MODULE_DEVICE_TABLE(of, macb_dt_ids);
@@ -4239,6 +4360,7 @@ static int macb_probe(struct platform_device *pdev)
err_disable_clocks:
clk_disable_unprepare(tx_clk);
+ clk_unregister(tx_clk);
clk_disable_unprepare(hclk);
clk_disable_unprepare(pclk);
clk_disable_unprepare(rx_clk);
@@ -4273,6 +4395,7 @@ static int macb_remove(struct platform_device *pdev)
pm_runtime_dont_use_autosuspend(&pdev->dev);
if (!pm_runtime_suspended(&pdev->dev)) {
clk_disable_unprepare(bp->tx_clk);
+ clk_unregister(bp->tx_clk);
clk_disable_unprepare(bp->hclk);
clk_disable_unprepare(bp->pclk);
clk_disable_unprepare(bp->rx_clk);
--
2.22.0

4
recipes-kernel/linux/files/freedom-u540/0006-HACK-Revert-of-device-Really-only-set-bus-DMA-mask-w.patch → recipes-kernel/linux/files/freedom-u540/0003-HACK-Revert-of-device-Really-only-set-bus-DMA-mask-w.patch
View File

@@ -1,7 +1,7 @@
From 41fce8c7589f76b6cd09d56db0f4ddd971a6dbd6 Mon Sep 17 00:00:00 2001
From 3b579413ed231e51625b5f5b5f672d10fc570628 Mon Sep 17 00:00:00 2001
From: Alistair Francis <alistair.francis@wdc.com>
Date: Thu, 21 Feb 2019 16:29:37 -0800
Subject: [PATCH 6/6] HACK: Revert "of/device: Really only set bus DMA mask
Subject: [PATCH 3/4] HACK: Revert "of/device: Really only set bus DMA mask
when appropriate"
This reverts commit 6778be4e520959659b27a441c06a84c9cb009085.

62
recipes-kernel/linux/files/freedom-u540/0003-riscv-dts-Add-DT-node-for-SiFive-FU540-Ethernet-cont.patch
View File

@@ -1,62 +0,0 @@
From 9955158a18bd876a2e9b6028d28e930ae71fee93 Mon Sep 17 00:00:00 2001
From: Yash Shah <yash.shah@sifive.com>
Date: Fri, 21 Jun 2019 16:23:49 +0530
Subject: [PATCH 3/6] riscv: dts: Add DT node for SiFive FU540 Ethernet
controller driver
DT node for SiFive FU540-C000 GEMGXL Ethernet controller driver added
Signed-off-by: Yash Shah <yash.shah@sifive.com>
Reviewed-by: Anup Patel <anup@brainfault.org>
Upstream-Status: Accepted [5.3]
---
arch/riscv/boot/dts/sifive/fu540-c000.dtsi | 16 ++++++++++++++++
.../boot/dts/sifive/hifive-unleashed-a00.dts | 9 +++++++++
2 files changed, 25 insertions(+)
diff --git a/arch/riscv/boot/dts/sifive/fu540-c000.dtsi b/arch/riscv/boot/dts/sifive/fu540-c000.dtsi
index 40983491b95f..56e009ad4cbe 100644
--- a/arch/riscv/boot/dts/sifive/fu540-c000.dtsi
+++ b/arch/riscv/boot/dts/sifive/fu540-c000.dtsi
@@ -217,5 +217,21 @@
#size-cells = <0>;
status = "disabled";
};
+ eth0: ethernet@10090000 {
+ compatible = "sifive,fu540-macb";
+ interrupt-parent = <&plic0>;
+ interrupts = <53>;
+ reg = <0x0 0x10090000 0x0 0x2000
+ 0x0 0x100a0000 0x0 0x1000>;
+ reg-names = "control";
+ status = "disabled";
+ local-mac-address = [00 00 00 00 00 00];
+ clock-names = "pclk", "hclk";
+ clocks = <&prci PRCI_CLK_GEMGXLPLL>,
+ <&prci PRCI_CLK_GEMGXLPLL>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+
};
};
diff --git a/arch/riscv/boot/dts/sifive/hifive-unleashed-a00.dts b/arch/riscv/boot/dts/sifive/hifive-unleashed-a00.dts
index 0b55c53c08c7..85c17a7980cd 100644
--- a/arch/riscv/boot/dts/sifive/hifive-unleashed-a00.dts
+++ b/arch/riscv/boot/dts/sifive/hifive-unleashed-a00.dts
@@ -76,3 +76,12 @@
disable-wp;
};
};
+
+&eth0 {
+ status = "okay";
+ phy-mode = "gmii";
+ phy-handle = <&phy1>;
+ phy1: ethernet-phy@0 {
+ reg = <0>;
+ };
+};
--
2.22.0

87
recipes-kernel/linux/files/freedom-u540/0004-drm-radeon-handle-PCIe-root-ports-with-addressing-li.patch Normal file
View File

@@ -0,0 +1,87 @@
From 891eabc400e036085cc1321f1fb02ef45bf9db2d Mon Sep 17 00:00:00 2001
From: Christoph Hellwig <hch@lst.de>
Date: Wed, 14 Aug 2019 16:47:10 +0200
Subject: [PATCH 1/4] drm/radeon: handle PCIe root ports with addressing
limitations
radeon uses a need_dma32 flag to indicate to the drm core that some
allocations need to be done using GFP_DMA32, but it only checks the
device addressing capabilities to make that decision. Unfortunately
PCIe root ports that have limited addressing exist as well. Use the
dma_addressing_limited instead to also take those into account.
Reported-by: Atish Patra <Atish.Patra@wdc.com>
Signed-off-by: Christoph Hellwig <hch@lst.de>
Reviewed-by: Christian K?nig <christian.koenig@amd.com>
Upstream-Status: Submitted
---
drivers/gpu/drm/radeon/radeon.h | 1 -
drivers/gpu/drm/radeon/radeon_device.c | 12 +++++-------
drivers/gpu/drm/radeon/radeon_ttm.c | 2 +-
3 files changed, 6 insertions(+), 9 deletions(-)
diff --git a/drivers/gpu/drm/radeon/radeon.h b/drivers/gpu/drm/radeon/radeon.h
index 32808e50be12..1a0b22526a75 100644
--- a/drivers/gpu/drm/radeon/radeon.h
+++ b/drivers/gpu/drm/radeon/radeon.h
@@ -2387,7 +2387,6 @@ struct radeon_device {
struct radeon_wb wb;
struct radeon_dummy_page dummy_page;
bool shutdown;
- bool need_dma32;
bool need_swiotlb;
bool accel_working;
bool fastfb_working; /* IGP feature*/
diff --git a/drivers/gpu/drm/radeon/radeon_device.c b/drivers/gpu/drm/radeon/radeon_device.c
index dceb554e5674..b8cc05826667 100644
--- a/drivers/gpu/drm/radeon/radeon_device.c
+++ b/drivers/gpu/drm/radeon/radeon_device.c
@@ -1365,27 +1365,25 @@ int radeon_device_init(struct radeon_device *rdev,
else
rdev->mc.mc_mask = 0xffffffffULL; /* 32 bit MC */
- /* set DMA mask + need_dma32 flags.
+ /* set DMA mask.
* PCIE - can handle 40-bits.
* IGP - can handle 40-bits
* AGP - generally dma32 is safest
* PCI - dma32 for legacy pci gart, 40 bits on newer asics
*/
- rdev->need_dma32 = false;
+ dma_bits = 40;
if (rdev->flags & RADEON_IS_AGP)
- rdev->need_dma32 = true;
+ dma_bits = 32;
if ((rdev->flags & RADEON_IS_PCI) &&
(rdev->family <= CHIP_RS740))
- rdev->need_dma32 = true;
+ dma_bits = 32;
#ifdef CONFIG_PPC64
if (rdev->family == CHIP_CEDAR)
- rdev->need_dma32 = true;
+ dma_bits = 32;
#endif
- dma_bits = rdev->need_dma32 ? 32 : 40;
r = pci_set_dma_mask(rdev->pdev, DMA_BIT_MASK(dma_bits));
if (r) {
- rdev->need_dma32 = true;
dma_bits = 32;
pr_warn("radeon: No suitable DMA available\n");
}
diff --git a/drivers/gpu/drm/radeon/radeon_ttm.c b/drivers/gpu/drm/radeon/radeon_ttm.c
index fb3696bc616d..116a27b25dc4 100644
--- a/drivers/gpu/drm/radeon/radeon_ttm.c
+++ b/drivers/gpu/drm/radeon/radeon_ttm.c
@@ -794,7 +794,7 @@ int radeon_ttm_init(struct radeon_device *rdev)
r = ttm_bo_device_init(&rdev->mman.bdev,
&radeon_bo_driver,
rdev->ddev->anon_inode->i_mapping,
- rdev->need_dma32);
+ dma_addressing_limited(&rdev->pdev->dev));
if (r) {
DRM_ERROR("failed initializing buffer object driver(%d).\n", r);
return r;
--
2.22.0

35
recipes-kernel/linux/files/freedom-u540/0005-drm-amdgpu-handle-PCIe-root-ports-with-addressing-li.patch Normal file
View File

@@ -0,0 +1,35 @@
From 448a652898ae2058ba685fb594247cb00261c95d Mon Sep 17 00:00:00 2001
From: Christoph Hellwig <hch@lst.de>
Date: Wed, 14 Aug 2019 16:56:35 +0200
Subject: [PATCH 2/4] drm/amdgpu: handle PCIe root ports with addressing
limitations
amdgpu uses a need_dma32 flag to indicate to the drm core that some
allocations need to be done using GFP_DMA32, but it only checks the
device addressing capabilities to make that decision. Unfortunately
PCIe root ports that have limited addressing exist as well. Use the
dma_addressing_limited instead to also take those into account.
Signed-off-by: Christoph Hellwig <hch@lst.de>
Reviewed-by: Christian K?nig <christian.koenig@amd.com>
Upstream-Status: Submitted
---
drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c
index e51b48ac48eb..91f128b43b6a 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c
@@ -1728,7 +1728,7 @@ int amdgpu_ttm_init(struct amdgpu_device *adev)
r = ttm_bo_device_init(&adev->mman.bdev,
&amdgpu_bo_driver,
adev->ddev->anon_inode->i_mapping,
- adev->need_dma32);
+ dma_addressing_limited(adev->dev));
if (r) {
DRM_ERROR("failed initializing buffer object driver(%d).\n", r);
return r;
--
2.22.0

43
recipes-kernel/linux/files/freedom-u540/0006-drm-radeon-simplify-and-cleanup-setting-the-dma-mask.patch Normal file
View File

@@ -0,0 +1,43 @@
From 04e16cec9c195e5c161123db0ad911a5d534d643 Mon Sep 17 00:00:00 2001
From: Christoph Hellwig <hch@lst.de>
Date: Wed, 14 Aug 2019 16:54:37 +0200
Subject: [PATCH 3/4] drm/radeon: simplify and cleanup setting the dma mask
Use dma_set_mask_and_coherent to set both masks in one go, and remove
the no longer required fallback, as the kernel now always accepts
larger than required DMA masks. Fail the driver probe if we can't
set the DMA mask, as that means the system can only support a larger
mask.
Signed-off-by: Christoph Hellwig <hch@lst.de>
Reviewed-by: Christian K?nig <christian.koenig@amd.com>
Upstream-Status: Submitted
---
drivers/gpu/drm/radeon/radeon_device.c | 9 ++-------
1 file changed, 2 insertions(+), 7 deletions(-)
diff --git a/drivers/gpu/drm/radeon/radeon_device.c b/drivers/gpu/drm/radeon/radeon_device.c
index b8cc05826667..88eb7cb522bb 100644
--- a/drivers/gpu/drm/radeon/radeon_device.c
+++ b/drivers/gpu/drm/radeon/radeon_device.c
@@ -1382,15 +1382,10 @@ int radeon_device_init(struct radeon_device *rdev,
dma_bits = 32;
#endif
- r = pci_set_dma_mask(rdev->pdev, DMA_BIT_MASK(dma_bits));
+ r = dma_set_mask_and_coherent(&rdev->pdev->dev, DMA_BIT_MASK(dma_bits));
if (r) {
- dma_bits = 32;
pr_warn("radeon: No suitable DMA available\n");
- }
- r = pci_set_consistent_dma_mask(rdev->pdev, DMA_BIT_MASK(dma_bits));
- if (r) {
- pci_set_consistent_dma_mask(rdev->pdev, DMA_BIT_MASK(32));
- pr_warn("radeon: No coherent DMA available\n");
+ return r;
}
rdev->need_swiotlb = drm_need_swiotlb(dma_bits);
--
2.22.0

45
recipes-kernel/linux/files/freedom-u540/0007-HACK-radeon-Don-t-set-PCI-DMA-mask.patch
View File

@@ -1,45 +0,0 @@
From 820e6a80587c0191c630641583e8d98687942146 Mon Sep 17 00:00:00 2001
From: Alistair Francis <alistair.francis@wdc.com>
Date: Wed, 27 Feb 2019 15:31:29 -0800
Subject: [PATCH 10/10] HACK: radeon: Don't set PCI DMA mask
Setting a PCI DMA mask when running on RISC-V results in these messages
beeing seen during boot:
[drm:r600_ring_test] *ERROR* radeon: ring 0 test failed (scratch(0x8504)=0xCAFEDEAD)
radeon 0000:04:00.0: disabling GPU acceleration
and results with a partially working graphcis card. By not setting a DMA
mask the messages aren't seen and the GPU works.
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Upstream-Status: Denied
---
drivers/gpu/drm/radeon/radeon_device.c | 11 +++++------
1 file changed, 5 insertions(+), 6 deletions(-)
diff --git a/drivers/gpu/drm/radeon/radeon_device.c b/drivers/gpu/drm/radeon/radeon_device.c
index 53f29a115104..add186346544 100644
--- a/drivers/gpu/drm/radeon/radeon_device.c
+++ b/drivers/gpu/drm/radeon/radeon_device.c
@@ -1377,12 +1377,11 @@ int radeon_device_init(struct radeon_device *rdev,
#endif
dma_bits = rdev->need_dma32 ? 32 : 40;
- r = pci_set_dma_mask(rdev->pdev, DMA_BIT_MASK(dma_bits));
- if (r) {
- rdev->need_dma32 = true;
- dma_bits = 32;
- pr_warn("radeon: No suitable DMA available\n");
- }
+
+ rdev->need_dma32 = true;
+ dma_bits = 32;
+ pr_warn("radeon: No suitable DMA available\n");
+
r = pci_set_consistent_dma_mask(rdev->pdev, DMA_BIT_MASK(dma_bits));
if (r) {
pci_set_consistent_dma_mask(rdev->pdev, DMA_BIT_MASK(32));
--
2.21.0

238
recipes-kernel/linux/files/freedom-u540/0007-drm-amdgpu-simplify-and-cleanup-setting-the-dma-mask.patch Normal file
View File

@@ -0,0 +1,238 @@
From fa405da57ff49a34a7ab754e70fe43b584919a96 Mon Sep 17 00:00:00 2001
From: Christoph Hellwig <hch@lst.de>
Date: Wed, 14 Aug 2019 17:00:14 +0200
Subject: [PATCH 4/4] drm/amdgpu: simplify and cleanup setting the dma mask
Use dma_set_mask_and_coherent to set both masks in one go, and remove
the no longer required fallback, as the kernel now always accepts
larger than required DMA masks. Fail the driver probe if we can't
set the DMA mask, as that means the system can only support a larger
mask.
Signed-off-by: Christoph Hellwig <hch@lst.de>
Reviewed-by: Christian K?nig <christian.koenig@amd.com>
Upstream-Status: Submitted
---
drivers/gpu/drm/amd/amdgpu/amdgpu.h | 1 -
drivers/gpu/drm/amd/amdgpu/gmc_v10_0.c | 21 ++-------------------
drivers/gpu/drm/amd/amdgpu/gmc_v6_0.c | 15 +++------------
drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c | 20 +++-----------------
drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c | 20 +++-----------------
drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c | 20 +++-----------------
6 files changed, 14 insertions(+), 83 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu.h b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
index 8199d201b43a..ab562c27bb44 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
@@ -758,7 +758,6 @@ struct amdgpu_device {
int usec_timeout;
const struct amdgpu_asic_funcs *asic_funcs;
bool shutdown;
- bool need_dma32;
bool need_swiotlb;
bool accel_working;
struct notifier_block acpi_nb;
diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v10_0.c b/drivers/gpu/drm/amd/amdgpu/gmc_v10_0.c
index 5eeb72fcc123..05c8872eb8d3 100644
--- a/drivers/gpu/drm/amd/amdgpu/gmc_v10_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gmc_v10_0.c
@@ -590,7 +590,6 @@ static unsigned gmc_v10_0_get_vbios_fb_size(struct amdgpu_device *adev)
static int gmc_v10_0_sw_init(void *handle)
{
int r;
- int dma_bits;
struct amdgpu_device *adev = (struct amdgpu_device *)handle;
gfxhub_v2_0_init(adev);
@@ -637,26 +636,10 @@ static int gmc_v10_0_sw_init(void *handle)
else
adev->gmc.stolen_size = 9 * 1024 *1024;
- /*
- * Set DMA mask + need_dma32 flags.
- * PCIE - can handle 44-bits.
- * IGP - can handle 44-bits
- * PCI - dma32 for legacy pci gart, 44 bits on navi10
- */
- adev->need_dma32 = false;
- dma_bits = adev->need_dma32 ? 32 : 44;
-
- r = pci_set_dma_mask(adev->pdev, DMA_BIT_MASK(dma_bits));
+ r = dma_set_mask_and_coherent(adev->dev, DMA_BIT_MASK(44));
if (r) {
- adev->need_dma32 = true;
- dma_bits = 32;
printk(KERN_WARNING "amdgpu: No suitable DMA available.\n");
- }
-
- r = pci_set_consistent_dma_mask(adev->pdev, DMA_BIT_MASK(dma_bits));
- if (r) {
- pci_set_consistent_dma_mask(adev->pdev, DMA_BIT_MASK(32));
- printk(KERN_WARNING "amdgpu: No coherent DMA available.\n");
+ return r;
}
r = gmc_v10_0_mc_init(adev);
diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v6_0.c b/drivers/gpu/drm/amd/amdgpu/gmc_v6_0.c
index ca8dbe91cc8b..14073b506afe 100644
--- a/drivers/gpu/drm/amd/amdgpu/gmc_v6_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gmc_v6_0.c
@@ -839,7 +839,6 @@ static unsigned gmc_v6_0_get_vbios_fb_size(struct amdgpu_device *adev)
static int gmc_v6_0_sw_init(void *handle)
{
int r;
- int dma_bits;
struct amdgpu_device *adev = (struct amdgpu_device *)handle;
if (adev->flags & AMD_IS_APU) {
@@ -862,20 +861,12 @@ static int gmc_v6_0_sw_init(void *handle)
adev->gmc.mc_mask = 0xffffffffffULL;
- adev->need_dma32 = false;
- dma_bits = adev->need_dma32 ? 32 : 40;
- r = pci_set_dma_mask(adev->pdev, DMA_BIT_MASK(dma_bits));
+ r = dma_set_mask_and_coherent(adev->dev, DMA_BIT_MASK(44));
if (r) {
- adev->need_dma32 = true;
- dma_bits = 32;
dev_warn(adev->dev, "amdgpu: No suitable DMA available.\n");
+ return r;
}
- r = pci_set_consistent_dma_mask(adev->pdev, DMA_BIT_MASK(dma_bits));
- if (r) {
- pci_set_consistent_dma_mask(adev->pdev, DMA_BIT_MASK(32));
- dev_warn(adev->dev, "amdgpu: No coherent DMA available.\n");
- }
- adev->need_swiotlb = drm_need_swiotlb(dma_bits);
+ adev->need_swiotlb = drm_need_swiotlb(44);
r = gmc_v6_0_init_microcode(adev);
if (r) {
diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c b/drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c
index 57f80065d57a..ca32915fbecb 100644
--- a/drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c
@@ -959,7 +959,6 @@ static unsigned gmc_v7_0_get_vbios_fb_size(struct amdgpu_device *adev)
static int gmc_v7_0_sw_init(void *handle)
{
int r;
- int dma_bits;
struct amdgpu_device *adev = (struct amdgpu_device *)handle;
if (adev->flags & AMD_IS_APU) {
@@ -990,25 +989,12 @@ static int gmc_v7_0_sw_init(void *handle)
*/
adev->gmc.mc_mask = 0xffffffffffULL; /* 40 bit MC */
- /* set DMA mask + need_dma32 flags.
- * PCIE - can handle 40-bits.
- * IGP - can handle 40-bits
- * PCI - dma32 for legacy pci gart, 40 bits on newer asics
- */
- adev->need_dma32 = false;
- dma_bits = adev->need_dma32 ? 32 : 40;
- r = pci_set_dma_mask(adev->pdev, DMA_BIT_MASK(dma_bits));
+ r = dma_set_mask_and_coherent(adev->dev, DMA_BIT_MASK(40));
if (r) {
- adev->need_dma32 = true;
- dma_bits = 32;
pr_warn("amdgpu: No suitable DMA available\n");
+ return r;
}
- r = pci_set_consistent_dma_mask(adev->pdev, DMA_BIT_MASK(dma_bits));
- if (r) {
- pci_set_consistent_dma_mask(adev->pdev, DMA_BIT_MASK(32));
- pr_warn("amdgpu: No coherent DMA available\n");
- }
- adev->need_swiotlb = drm_need_swiotlb(dma_bits);
+ adev->need_swiotlb = drm_need_swiotlb(40);
r = gmc_v7_0_init_microcode(adev);
if (r) {
diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c b/drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c
index 9238280d1ff7..909a8764703e 100644
--- a/drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c
@@ -1079,7 +1079,6 @@ static unsigned gmc_v8_0_get_vbios_fb_size(struct amdgpu_device *adev)
static int gmc_v8_0_sw_init(void *handle)
{
int r;
- int dma_bits;
struct amdgpu_device *adev = (struct amdgpu_device *)handle;
if (adev->flags & AMD_IS_APU) {
@@ -1116,25 +1115,12 @@ static int gmc_v8_0_sw_init(void *handle)
*/
adev->gmc.mc_mask = 0xffffffffffULL; /* 40 bit MC */
- /* set DMA mask + need_dma32 flags.
- * PCIE - can handle 40-bits.
- * IGP - can handle 40-bits
- * PCI - dma32 for legacy pci gart, 40 bits on newer asics
- */
- adev->need_dma32 = false;
- dma_bits = adev->need_dma32 ? 32 : 40;
- r = pci_set_dma_mask(adev->pdev, DMA_BIT_MASK(dma_bits));
+ r = dma_set_mask_and_coherent(adev->dev, DMA_BIT_MASK(40));
if (r) {
- adev->need_dma32 = true;
- dma_bits = 32;
pr_warn("amdgpu: No suitable DMA available\n");
+ return r;
}
- r = pci_set_consistent_dma_mask(adev->pdev, DMA_BIT_MASK(dma_bits));
- if (r) {
- pci_set_consistent_dma_mask(adev->pdev, DMA_BIT_MASK(32));
- pr_warn("amdgpu: No coherent DMA available\n");
- }
- adev->need_swiotlb = drm_need_swiotlb(dma_bits);
+ adev->need_swiotlb = drm_need_swiotlb(40);
r = gmc_v8_0_init_microcode(adev);
if (r) {
diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c b/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c
index 73f3b79ab131..38b91a407e6c 100644
--- a/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c
@@ -968,7 +968,6 @@ static unsigned gmc_v9_0_get_vbios_fb_size(struct amdgpu_device *adev)
static int gmc_v9_0_sw_init(void *handle)
{
int r;
- int dma_bits;
struct amdgpu_device *adev = (struct amdgpu_device *)handle;
gfxhub_v1_0_init(adev);
@@ -1030,25 +1029,12 @@ static int gmc_v9_0_sw_init(void *handle)
*/
adev->gmc.mc_mask = 0xffffffffffffULL; /* 48 bit MC */
- /* set DMA mask + need_dma32 flags.
- * PCIE - can handle 44-bits.
- * IGP - can handle 44-bits
- * PCI - dma32 for legacy pci gart, 44 bits on vega10
- */
- adev->need_dma32 = false;
- dma_bits = adev->need_dma32 ? 32 : 44;
- r = pci_set_dma_mask(adev->pdev, DMA_BIT_MASK(dma_bits));
+ r = dma_set_mask_and_coherent(adev->dev, DMA_BIT_MASK(44));
if (r) {
- adev->need_dma32 = true;
- dma_bits = 32;
printk(KERN_WARNING "amdgpu: No suitable DMA available.\n");
+ return r;
}
- r = pci_set_consistent_dma_mask(adev->pdev, DMA_BIT_MASK(dma_bits));
- if (r) {
- pci_set_consistent_dma_mask(adev->pdev, DMA_BIT_MASK(32));
- printk(KERN_WARNING "amdgpu: No coherent DMA available.\n");
- }
- adev->need_swiotlb = drm_need_swiotlb(dma_bits);
+ adev->need_swiotlb = drm_need_swiotlb(44);
if (adev->gmc.xgmi.supported) {
r = gfxhub_v1_1_get_xgmi_info(adev);
--
2.22.0

5
recipes-kernel/linux/linux-mainline-common.inc
View File

@@ -10,13 +10,8 @@ LINUX_VERSION_EXTENSION = ""
PV = "${LINUX_VERSION}+git${SRCPV}"
DEPENDS_append = " libgcc"
KCONFIG_MODE="--alldefconfig"
KERNEL_CC_append = " ${TOOLCHAIN_OPTIONS} ${SECURITY_NOPIE_CFLAGS}"
KERNEL_LD_append = " -no-pie"
COMPATIBLE_MACHINE = "(qemuriscv32|qemuriscv64|freedom-u540)"
KERNEL_FEATURES_remove = "features/debug/printk.scc"

18
recipes-kernel/linux/linux-mainline_5.2.bb → recipes-kernel/linux/linux-mainline_5.3.bb
View File

@@ -1,22 +1,22 @@
require recipes-kernel/linux/linux-mainline-common.inc
LINUX_VERSION ?= "5.2.x"
LINUX_VERSION ?= "5.3.x"
KERNEL_VERSION_SANITY_SKIP="1"
BRANCH = "linux-5.2.y"
BRANCH = "linux-5.3.y"
SRCREV = "${AUTOREV}"
SRC_URI = " \
git://git.kernel.org/pub/scm/linux/kernel/git/stable/linux.git;branch=${BRANCH} \
"
SRC_URI_append_freedom-u540 = " \
file://0001-macb-bindings-doc-add-sifive-fu540-c000-binding.patch \
file://0002-macb-Add-support-for-SiFive-FU540-C000.patch \
file://0003-riscv-dts-Add-DT-node-for-SiFive-FU540-Ethernet-cont.patch \
file://0004-PCI-microsemi-Add-host-driver-for-Microsemi-PCIe-con.patch \
file://0005-Microsemi-PCIe-expansion-board-DT-entry.patch \
file://0006-HACK-Revert-of-device-Really-only-set-bus-DMA-mask-w.patch \
file://0007-HACK-radeon-Don-t-set-PCI-DMA-mask.patch \
file://0001-PCI-microsemi-Add-host-driver-for-Microsemi-PCIe-con.patch \
file://0002-Microsemi-PCIe-expansion-board-DT-entry.patch \
file://0003-HACK-Revert-of-device-Really-only-set-bus-DMA-mask-w.patch \
file://0004-drm-radeon-handle-PCIe-root-ports-with-addressing-li.patch \
file://0005-drm-amdgpu-handle-PCIe-root-ports-with-addressing-li.patch \
file://0006-drm-radeon-simplify-and-cleanup-setting-the-dma-mask.patch \
file://0007-drm-amdgpu-simplify-and-cleanup-setting-the-dma-mask.patch \
"
KERNEL_DEVICETREE_freedom-u540 = "sifive/${RISCV_SBI_FDT}"