mirror of
https://github.com/thead-yocto-mirror/meta-riscv
synced 2026-09-16 12:14:20 +02:00
d6be7444f5
Update to the latest version of the RISC-V Spike ISA Simulator. Signed-off-by: pino-kim <sungwon.pino@gmail.com>
26 lines
760 B
BlitzBasic
26 lines
760 B
BlitzBasic
SUMMARY = "RISC-V Spike ISA Simulator"
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DESCRIPTION = "RISC-V Spike ISA Simulator"
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LICENSE = "GPLv2+"
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LIC_FILES_CHKSUM = "file://${COREBASE}/meta/COPYING.GPLv2;md5=751419260aa954499f7abaabaa882bbe"
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SRCREV = "65c8ac48af16235097084b413c10c7bff576b331"
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SRC_URI = "git://github.com/riscv/riscv-isa-sim.git \
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file://spike-makefile.patch"
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DEPENDS = "riscv-fesvr dtc-native"
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RDEPENDS_nativesdk-riscv-spike = "nativesdk-riscv-fesvr"
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inherit autotools cross-canadian
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S = "${WORKDIR}/git"
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do_configure_prepend () {
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touch ${S}/softfloat/softfloat.ac
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if [ ! -e ${S}/acinclude.m4 ]; then
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cp ${S}/aclocal.m4 ${S}/acinclude.m4
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fi
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}
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BBCLASSEXTEND = "native nativesdk"
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COMPATIBLE_HOST_class-target = "(riscv64|riscv32).*-linux"
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