mirror of
https://github.com/thead-yocto-mirror/npu-ax3386-kernel
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392 lines
14 KiB
C
392 lines
14 KiB
C
/*!
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*****************************************************************************
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* Copyright (c) Imagination Technologies Ltd.
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*
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* The contents of this file are subject to the MIT license as set out below.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
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* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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* THE SOFTWARE.
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*
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* Alternatively, the contents of this file may be used under the terms of the
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* GNU General Public License Version 2 ("GPL")in which case the provisions of
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* GPL are applicable instead of those above.
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*
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* If you wish to allow use of your version of this file only under the terms
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* of GPL, and not to allow others to use your version of this file under the
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* terms of the MIT license, indicate your decision by deleting the provisions
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* above and replace them with the notice and other provisions required by GPL
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* as set out in the file called "GPLHEADER" included in this distribution. If
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* you do not delete the provisions above, a recipient may use your version of
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* this file under the terms of either the MIT license or GPL.
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*
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* This License is also included in this distribution in the file called
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* "MIT_COPYING".
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*
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*****************************************************************************/
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#ifndef VHA_REGS_H
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#define VHA_REGS_H
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#include "../vha_io.h"
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#if defined(HW_AX3)
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#include <hwdefs/vha_cr_magna.h>
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#else
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#error "No HW layout defined"
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#endif
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#if defined(CFG_SYS_MAGNA)
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#include <hwdefs/magna_system.h>
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#endif
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#define HW_SERIES (28U)
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/* General register macros */
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#define VHA_GET_FIELD_FULL_MASK(reg, field) \
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(VHA_CR_BITMASK(reg, field) >> VHA_CR_##reg##_##field##_SHIFT)
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#define VHA_SET_FIELD_SIMPLE_VAL(reg, field, type) \
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(VHA_CR_##reg##_##field##_##type)
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#define VHA_SET_FIELD_SIMPLE_FULL(reg, field) \
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VHA_CR_BITMASK(reg, field)
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#define VHA_WM_ID_TO_MASK(i) (1 << i)
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#define VHA_CORE_ID_TO_MASK(i) (1 << i)
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#define VHA_WM_MASK_TO_ID(m) ({ \
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uint8_t _ret_ = m; \
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WARN_ON(!_ret_); \
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do { \
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if (!_ret_) break; \
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_ret_ = ffs(_ret_) - 1; \
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} while (0); \
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_ret_; \
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})
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#define VHA_CORE_MASK_TO_ID(m) VHA_WM_MASK_TO_ID(m)
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#define VHA_CORE_MASK_TO_NUM(m) ({ \
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uint8_t _ret_ = m; \
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WARN_ON(!_ret_); \
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do { \
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if (!_ret_) break; \
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_ret_ = _ret_ - ((_ret_ >> 1) & 0x55); \
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_ret_ = (_ret_ & 0x33) + ((_ret_ >> 2) & 0x33); \
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_ret_ = (((_ret_ + (_ret_ >> 4)) & 0x0F) * 0x01); \
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} while (0); \
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_ret_; \
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})
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#if defined(CONFIG_VHA_DUMMY)
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#define VHA_LOCK_WM()
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#define VHA_UNLOCK_WM()
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#else
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#define VHA_LOCK_WM() spin_lock_irq(&vha->irq_lock)
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#define VHA_UNLOCK_WM() spin_unlock(&vha->irq_lock)
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#endif
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#define VHA_SELECT_WM(wm) ({ \
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uint64_t reg = 0;\
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uint8_t c = 10;\
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IOWRITE64_CR_PDUMP(VHA_CR_SETBITS(TLC_WM_INDIRECT, ADDRESS, (uint64_t)wm), \
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TLC_WM_INDIRECT); \
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do { \
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reg = IOREAD64_CR_REGIO(TLC_WM_INDIRECT); \
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c--;\
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} while ((reg != wm) && c > 0); \
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WARN_ON(c == 0); \
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})
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/* Clock calibration defines. */
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#define VHA_CALIBRATION_WM_ID 0
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#define VHA_CALIBRATION_CORE_ID 0
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#define VHA_CALIBRATION_CORE_MASK (1 << VHA_CALIBRATION_CORE_ID)
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/* Event macro definitions */
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#define VHA_SYS_EVENT_TYPE(name) \
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VHA_CR_BITMASK(SYS_EVENT_TYPE, name)
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#define VHA_WM_EVENT_TYPE(name) \
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VHA_CR_BITMASK(WM_EVENT_TYPE, name)
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#define VHA_CORE_EVENT_TYPE(name) \
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VHA_CR_BITMASK(CORE_EVENT_TYPE, name)
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#define VHA_IC_EVENT_TYPE(name) \
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VHA_CR_BITMASK(INTERCONNECT_EVENT_TYPE, name)
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#define VHA_SYS_EVENTS ( \
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VHA_SYS_EVENT_TYPE(RAM_INIT_DONE ) | \
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VHA_SYS_EVENT_TYPE(MEMBUS_RESET_DONE))
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#ifdef VHA_SCF
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#define VHA_SYS_SCF_ERR_EVENTS ( \
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VHA_SYS_EVENT_TYPE(LOGIC_ERROR ) | \
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VHA_SYS_EVENT_TYPE(RAM_CORRECTION ) | \
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VHA_SYS_EVENT_TYPE(RAM_DETECTION ) | \
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VHA_SYS_EVENT_TYPE(MMU_PARITY_ERROR) | \
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VHA_SYS_EVENT_TYPE(AXI_MEMORY_PARITY_ERROR))
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#else
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#define VHA_SYS_SCF_ERR_EVENTS (0)
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#endif
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#define VHA_SYS_ERR_EVENTS ( \
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VHA_SYS_SCF_ERR_EVENTS | \
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VHA_SYS_EVENT_TYPE(LSYNC_INV_REQ ) | \
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VHA_SYS_EVENT_TYPE(SYS_MEM_WDT ) | \
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VHA_SYS_EVENT_TYPE(MMU_PAGE_FAULT ) | \
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VHA_SYS_EVENT_TYPE(AXI_ERROR ))
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#define VHA_SYS_EVENTS_DEFAULT ( \
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VHA_SYS_EVENTS | \
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VHA_SYS_ERR_EVENTS)
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#define VHA_WM_EVENTS ( \
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VHA_WM_EVENT_TYPE(RESPONSE_FIFO_READY))
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#ifdef VHA_SCF
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#define VHA_WM_SCF_ERR_EVENTS ( \
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VHA_WM_EVENT_TYPE(LOGIC_FAULT ))
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#else
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#define VHA_WM_SCF_ERR_EVENTS (0)
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#endif
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#define VHA_WM_ERR_EVENTS ( \
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VHA_WM_SCF_ERR_EVENTS | \
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VHA_WM_EVENT_TYPE(WM_WL_WDT ) | \
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VHA_WM_EVENT_TYPE(WM_WL_IDLE_WDT) | \
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VHA_WM_EVENT_TYPE(WM_SOCIF_WDT ))
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#define VHA_WM_EVENTS_DEFAULT ( \
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VHA_WM_EVENTS | \
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VHA_WM_ERR_EVENTS)
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#define VHA_CORE_EVENTS ( \
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VHA_CORE_EVENT_TYPE(CNN_COMPLETE ))
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#ifdef VHA_SCF
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#define VHA_CORE_SCF_ERR_EVENTS ( \
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VHA_CORE_EVENT_TYPE(RAM_CORRECTION ) | \
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VHA_CORE_EVENT_TYPE(RAM_DETECTION ) | \
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VHA_CORE_EVENT_TYPE(LOGIC_ERROR ))
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#else
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#define VHA_CORE_SCF_ERR_EVENTS (0)
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#endif
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#define VHA_CORE_ERR_EVENTS ( \
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VHA_CORE_SCF_ERR_EVENTS | \
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VHA_CORE_EVENT_TYPE(CNN_ERROR ) | \
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VHA_CORE_EVENT_TYPE(CORE_SYNC_ERROR ) | \
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VHA_CORE_EVENT_TYPE(CORE_WDT ) | \
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VHA_CORE_EVENT_TYPE(CORE_MEM_WDT ))
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#define VHA_CORE_EVENTS_DEFAULT ( \
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VHA_CORE_EVENTS | \
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VHA_CORE_ERR_EVENTS)
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#define VHA_IC_EVENTS (0)
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#ifdef VHA_SCF
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#define VHA_IC_SCF_ERR_EVENTS ( \
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VHA_IC_EVENT_TYPE(LOGIC_ERROR ))
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#else
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#define VHA_IC_SCF_ERR_EVENTS (0)
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#endif
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#define VHA_IC_ERR_EVENTS ( \
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VHA_IC_SCF_ERR_EVENTS | \
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VHA_IC_EVENT_TYPE(LOCKSTEP_ERROR) | \
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VHA_IC_EVENT_TYPE(SOCIF_READ_MISMATCH) | \
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VHA_IC_EVENT_TYPE(SOCIF_READ_UNRESPONSIVE))
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#define VHA_IC_EVENTS_DEFAULT ( \
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VHA_IC_EVENTS | \
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VHA_IC_ERR_EVENTS)
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/* Clock macro definitions */
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#define VHA_CLOCKS_MULTI_ALL 0xff
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#define VHA_SPREAD_MASK(m) \
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(((m * 0x0101010101010101ULL & 0x8040201008040201ULL) * \
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0x0102040810204081ULL >> 49) & 0x5555)
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#define VHA_SET_CLOCKS(mask, mode) \
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(VHA_SPREAD_MASK(mask) * VHA_CR_SYS_CLK_CTRL0_MODE_##mode)
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/* As REGBANK is a NOTOFF register, define its OFF to be AUTO by default. */
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#define VHA_CR_SYS_CLK_CTRL0_REGBANK_OFF \
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VHA_CR_SYS_CLK_CTRL0_REGBANK_AUTO
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#define VHA_SYS_CLOCK_MODE(name, mode) \
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VHA_CR_SYS_CLK_CTRL0_##name##_##mode
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#define VHA_SYS_CLOCK_MODE_MULTI(name, mode, mask) \
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(VHA_SET_CLOCKS(mask, mode) << VHA_CR_SYS_CLK_CTRL0_##name##0_SHIFT)
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#define VHA_SYS_CLOCK_MODE_MULTI_ALL(name, mode) \
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(VHA_SET_CLOCKS(VHA_CLOCKS_MULTI_ALL, mode) << \
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VHA_CR_SYS_CLK_CTRL0_##name##0_SHIFT)
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#define VHA_SYS_CLOCKS_DEFAULT(mode) ( (\
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VHA_SYS_CLOCK_MODE(REGBANK, mode) | \
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VHA_SYS_CLOCK_MODE(SOCM, mode) | \
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VHA_SYS_CLOCK_MODE(LSYNC, mode) | \
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VHA_SYS_CLOCK_MODE(SLC, mode) | \
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VHA_SYS_CLOCK_MODE(AXI, mode) | \
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VHA_SYS_CLOCK_MODE(INTERCONNECT, mode) | \
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VHA_SYS_CLOCK_MODE_MULTI_ALL(WM, mode) | \
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VHA_SYS_CLOCK_MODE_MULTI_ALL(NOC, mode) | \
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VHA_SYS_CLOCK_MODE_MULTI_ALL(CORE, mode) \
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) & VHA_CR_SYS_CLK_CTRL0_MASKFULL)
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#define VHA_SYS_CLOCKS_RESET(mode) ( (\
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VHA_SYS_CLOCK_MODE(REGBANK, mode) | \
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VHA_SYS_CLOCK_MODE(SOCM, mode) | \
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VHA_SYS_CLOCK_MODE(LSYNC, mode) | \
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VHA_SYS_CLOCK_MODE(SLC, mode) | \
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VHA_SYS_CLOCK_MODE(AXI, mode) | \
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VHA_SYS_CLOCK_MODE(INTERCONNECT, mode) | \
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VHA_SYS_CLOCK_MODE_MULTI_ALL(WM, mode) | \
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VHA_SYS_CLOCK_MODE_MULTI_ALL(NOC, mode) \
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) & VHA_CR_SYS_CLK_CTRL0_MASKFULL)
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#define VHA_SYS_CLOCKS_CORE_FULL_MASK ( \
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~(VHA_CR_SYS_CLK_CTRL0_CORE7_CLRMSK) | \
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~(VHA_CR_SYS_CLK_CTRL0_CORE6_CLRMSK) | \
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~(VHA_CR_SYS_CLK_CTRL0_CORE5_CLRMSK) | \
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~(VHA_CR_SYS_CLK_CTRL0_CORE4_CLRMSK) | \
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~(VHA_CR_SYS_CLK_CTRL0_CORE3_CLRMSK) | \
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~(VHA_CR_SYS_CLK_CTRL0_CORE2_CLRMSK) | \
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~(VHA_CR_SYS_CLK_CTRL0_CORE1_CLRMSK) | \
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~(VHA_CR_SYS_CLK_CTRL0_CORE0_CLRMSK))
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#define VHA_MAIN_CLOCK_MODE(name, mode) \
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VHA_CR_CLK_CTRL0_##name##_##mode \
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#define VHA_MAIN_CLOCKS_DEFAULT(mode) ( (\
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VHA_MAIN_CLOCK_MODE(CNN_CORE_XBAR, mode) | \
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VHA_MAIN_CLOCK_MODE(CNN_MMM, mode) | \
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VHA_MAIN_CLOCK_MODE(CNN_EWO, mode) | \
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VHA_MAIN_CLOCK_MODE(CNN_PACK, mode) | \
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VHA_MAIN_CLOCK_MODE(CNN_OIN, mode) | \
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VHA_MAIN_CLOCK_MODE(CNN_POOL, mode) | \
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VHA_MAIN_CLOCK_MODE(CNN_SB, mode) | \
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VHA_MAIN_CLOCK_MODE(CNN_XBAR, mode) | \
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VHA_MAIN_CLOCK_MODE(CNN_NORM, mode) | \
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VHA_MAIN_CLOCK_MODE(CNN_ACT, mode) | \
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VHA_MAIN_CLOCK_MODE(CNN_ACCUM, mode) | \
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VHA_MAIN_CLOCK_MODE(CNN_CNV, mode) | \
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VHA_MAIN_CLOCK_MODE(CNN_CBUF, mode) | \
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VHA_MAIN_CLOCK_MODE(CNN_IBUF, mode) | \
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VHA_MAIN_CLOCK_MODE(CNN_CMD, mode) | \
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VHA_MAIN_CLOCK_MODE(CNN, mode) | \
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VHA_MAIN_CLOCK_MODE(CNN_TRS_A, mode) | \
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VHA_MAIN_CLOCK_MODE(CNN_TRS_B, mode) | \
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VHA_MAIN_CLOCK_MODE(MEMBUS_RESET, mode) | \
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VHA_MAIN_CLOCK_MODE(BWM, mode) | \
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VHA_MAIN_CLOCK_MODE(LOCM, mode) | \
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VHA_MAIN_CLOCK_MODE(NOC, mode) | \
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VHA_MAIN_CLOCK_MODE(ARB, mode) | \
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VHA_MAIN_CLOCK_MODE(BIF, mode) \
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) & VHA_CR_CLK_CTRL0_MASKFULL)
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/* Response status macro definitions. */
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#define VHA_WM_RESPONSE_STATUS(name) \
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VHA_CR_BITMASK(WM_RESPONSE_FIFO_WL_STATUS, name)
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#define VHA_WM_RESPONSE_SUCCESS ( \
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VHA_WM_RESPONSE_STATUS(SUCCESS))
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#define VHA_WM_RESPONSE_ERROR_CODE(name) \
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(VHA_CR_WM_RESPONSE_FIFO_WL_STATUS_WL_ERROR_CODE_##name)
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#define VHA_WM_RESPONSE_GET_ERROR_CODE(s) \
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VHA_CR_GETBITS(WM_RESPONSE_FIFO_WL_STATUS, ERROR_CODE, s)
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#define VHA_WM_RESPONSE_GET_FAILED_CORE_IDX(s) \
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VHA_CR_GETBITS(WM_RESPONSE_FIFO_WL_STATUS, FAILED_CORE_IDX, s)
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/* Core status macro definitions. */
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#define VHA_CORE_STATUS(name) \
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VHA_CR_BITMASK(CORE_EVENT_HOST_STATUS, name)
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/* IC status macro definitions. */
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#define VHA_IC_STATUS(name) \
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VHA_CR_BITMASK(INTERCONNECT_EVENT_HOST_STATUS, name)
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/* Confirmation writes error indication. */
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/* There is a fake error bit set in the VHA_CR_WM_RESPONSE_FIFO_WL_STATUS reg
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* to indicate confirmation writes error detected with software. */
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#define VHA_REG_CONF_ERROR_SHIFT (63)
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#define VHA_REG_CONF_ERROR_CLRMSK (0x7fffffffffffffffULL)
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#define VHA_REG_CONF_ERROR_EN (0x8000000000000000ULL)
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#define VHA_REG_SET_CONF_ERROR(r) \
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(r |= VHA_REG_CONF_ERROR_EN)
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#define VHA_REG_CLR_CONF_ERROR(r) \
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(r &= VHA_REG_CONF_ERROR_CLRMSK)
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#define VHA_REG_GET_CONF_ERROR(r) \
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((r & VHA_REG_CONF_ERROR_EN) >> VHA_REG_CONF_ERROR_SHIFT)
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/* Parity error indication. */
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/* As not all regs with PARITY bit have LOGIC_ERROR bit to identify parity
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* error, there's a fake parity bit set in these regs to indicate parity
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* errors detected with software. */
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#define VHA_REG_PARITY_ERROR_SHIFT (62)
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#define VHA_REG_PARITY_ERROR_CLRMSK (0xBfffffffffffffffULL)
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#define VHA_REG_PARITY_ERROR_EN (0x4000000000000000ULL)
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#define VHA_REG_SET_PARITY_ERROR(r) \
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(r |= VHA_REG_PARITY_ERROR_EN)
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#define VHA_REG_CLR_PARITY_ERROR(r) \
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(r &= VHA_REG_PARITY_ERROR_CLRMSK)
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#define VHA_REG_GET_PARITY_ERROR(r) \
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((r & VHA_REG_PARITY_ERROR_EN) >> VHA_REG_PARITY_ERROR_SHIFT)
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/* Workload id mismatch indication. */
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/* There is a fake error bit set in the VHA_CR_WM_RESPONSE_FIFO_WL_STATUS reg
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* to indicate workload id mismatch error detected with software. */
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#define VHA_REG_WL_ID_MISMATCH_ERROR_SHIFT (61)
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#define VHA_REG_WL_ID_MISMATCH_ERROR_CLRMSK (0xDfffffffffffffffULL)
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#define VHA_REG_WL_ID_MISMATCH_ERROR_EN (0x2000000000000000ULL)
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#define VHA_REG_SET_WL_ID_MISMATCH_ERROR(r) \
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(r |= VHA_REG_WL_ID_MISMATCH_ERROR_EN)
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#define VHA_REG_CLR_WL_ID_MISMATCH_ERROR(r) \
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(r &= VHA_REG_WL_ID_MISMATCH_ERROR_CLRMSK)
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#define VHA_REG_GET_WL_ID_MISMATCH_ERROR(r) \
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((r & VHA_REG_WL_ID_MISMATCH_ERROR_EN) >> VHA_REG_WL_ID_MISMATCH_ERROR_SHIFT)
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/* CRC mismatch indication. */
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/* There is a fake error bit set in the VHA_CR_WM_RESPONSE_FIFO_WL_STATUS reg
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* to indicate workload id mismatch error detected with software. */
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#define VHA_REG_COMBINED_CRC_ERROR_SHIFT (60)
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#define VHA_REG_COMBINED_CRC_ERROR_CLRMSK (0xEFFFFFFFFFFFFFFFULL)
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#define VHA_REG_COMBINED_CRC_ERROR_EN (0x1000000000000000ULL)
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#define VHA_REG_SET_COMBINED_CRC_ERROR(r) \
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(r |= VHA_REG_COMBINED_CRC_ERROR_EN)
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#define VHA_REG_CLR_COMBINED_CRC_ERROR(r) \
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(r &= VHA_REG_COMBINED_CRC_ERROR_CLRMSK)
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#define VHA_REG_GET_COMBINED_CRC_ERROR(r) \
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((r & VHA_REG_COMBINED_CRC_ERROR_EN) >> VHA_REG_COMBINED_CRC_ERROR_SHIFT)
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/* General core error indication. */
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/* There is a fake error bit set in the VHA_CR_WM_EVENT_STATUS reg
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* to indicate that core error was detected for one of the assigned cores. */
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#define VHA_REG_WM_CORE_ERROR_SHIFT (24)
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#define VHA_REG_WM_CORE_ERROR_CLRMSK (0xfffffffffeffffffULL)
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#define VHA_REG_WM_CORE_ERROR_EN (0x0000000001000000ULL)
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#define VHA_REG_SET_WM_CORE_ERROR(r) \
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(r |= VHA_REG_WM_CORE_ERROR_EN)
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#define VHA_REG_CLR_WM_CORE_ERROR(r) \
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(r &= VHA_REG_WM_CORE_ERROR_CLRMSK)
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#define VHA_REG_GET_WM_CORE_ERROR(r) \
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((r & VHA_REG_WM_CORE_ERROR_EN) >> VHA_REG_WM_CORE_ERROR_SHIFT)
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/* General interconnect error indication. */
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/* There is a fake error bit set in the VHA_CR_WM_EVENT_STATUS reg
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* to indicate that interconnect error was detected for one of the assigned ones. */
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#define VHA_REG_WM_IC_ERROR_SHIFT (25)
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#define VHA_REG_WM_IC_ERROR_CLRMSK (0xfffffffffdffffffULL)
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#define VHA_REG_WM_IC_ERROR_EN (0x0000000002000000ULL)
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#define VHA_REG_SET_WM_IC_ERROR(r) \
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(r |= VHA_REG_WM_IC_ERROR_EN)
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#define VHA_REG_CLR_WM_IC_ERROR(r) \
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(r &= VHA_REG_WM_IC_ERROR_CLRMSK)
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#define VHA_REG_GET_WM_IC_ERROR(r) \
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((r & VHA_REG_WM_IC_ERROR_EN) >> VHA_REG_WM_IC_ERROR_SHIFT)
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#endif /* VHA_REGS_H */
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