mirror of
https://github.com/thead-yocto-mirror/npu-ax3386-kernel
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191 lines
7.0 KiB
C
191 lines
7.0 KiB
C
/*
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*****************************************************************************
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* Copyright (c) Imagination Technologies Ltd.
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*
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* The contents of this file are subject to the MIT license as set out below.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
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* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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* THE SOFTWARE.
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*
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* Alternatively, the contents of this file may be used under the terms of the
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* GNU General Public License Version 2 ("GPL")in which case the provisions of
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* GPL are applicable instead of those above.
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*
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* If you wish to allow use of your version of this file only under the terms
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* of GPL, and not to allow others to use your version of this file under the
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* terms of the MIT license, indicate your decision by deleting the provisions
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* above and replace them with the notice and other provisions required by GPL
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* as set out in the file called "GPLHEADER" included in this distribution. If
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* you do not delete the provisions above, a recipient may use your version of
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* this file under the terms of either the MIT license or GPL.
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*
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* This License is also included in this distribution in the file called
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* "MIT_COPYING".
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*
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*****************************************************************************/
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#include <linux/device.h>
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#include <linux/moduleparam.h>
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#include "vha_common.h"
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#include "vha_plat.h"
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#include "vha_regs.h"
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static long cnn_wdt_cycles = VHA_CORE_WDT_CYCLES;
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module_param(cnn_wdt_cycles, long, 0444);
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MODULE_PARM_DESC(cnn_wdt_cycles,
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"CNN hw watchdog expiration cycles, -1=use estimated cycles, 0=disable watchdog, >0=predefined");
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static uint32_t cnn_wdt_cycles_margin = 40;
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module_param(cnn_wdt_cycles_margin, uint, 0444);
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MODULE_PARM_DESC(cnn_wdt_cycles_margin,
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"CNN estimated hw watchdog percentage overhead. default:40% additional margin added");
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void vha_dev_mh_setup(struct vha_dev *vha, int ctx_id, struct vha_mh_config_regs *regs)
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{
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uint64_t val64 = 0;
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uint8_t burst = ilog2(VHA_CORE_MH_MAX_BURST_LENGTH/32);
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WARN_ON(burst & ~VHA_CR_MH_CONTROL_MAX_BURST_LENGTH_MASK);
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val64 |= VHA_CR_SETBITS(CNN_CMD_MH_CONTROL,
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MAX_BURST_LENGTH, burst);
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val64 |= VHA_CR_SETBITS(CNN_CMD_MH_CONTROL,
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GPU_PIPE_COHERENT, VHA_CORE_MH_GPU_PIPE_COHERENT_TYPE);
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val64 |= VHA_CR_SETBITS(CNN_CMD_MH_CONTROL,
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SLC_CACHE_POLICY, VHA_CORE_MH_SLC_CACHE_POLICY_TYPE);
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val64 |= VHA_CR_SETBITS(CNN_CMD_MH_CONTROL,
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PERSISTENCE, VHA_CORE_MH_PERSISTENCE_PRIO);
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img_pdump_printf("-- CNN mem hierarchy setup CTXT_PASID:%d\n", ctx_id);
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val64 |= VHA_CR_SETBITS(CNN_CMD_MH_CONTROL,
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CTXT_PASID, ctx_id);
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/* Note: CMD reg has different layout than IBUF,CBUF,ABUFF,OUPACK */
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IOWRITE64_PDUMP(val64, VHA_CR_CNN_CMD_MH_CONTROL);
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val64 = 0;
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val64 |= VHA_CR_SETBITS(CNN_IBUF_MH_CONTROL,
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MAX_BURST_LENGTH, burst);
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val64 |= VHA_CR_SETBITS(CNN_IBUF_MH_CONTROL,
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GPU_PIPE_COHERENT, VHA_CORE_MH_GPU_PIPE_COHERENT_TYPE);
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val64 |= VHA_CR_SETBITS(CNN_IBUF_MH_CONTROL,
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PERSISTENCE, VHA_CORE_MH_PERSISTENCE_PRIO);
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IOWRITE64_PDUMP(val64, VHA_CR_CNN_IBUF_MH_CONTROL);
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IOWRITE64_PDUMP(val64, VHA_CR_CNN_CBUF_MH_CONTROL);
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IOWRITE64_PDUMP(val64, VHA_CR_CNN_ABUF_MH_CONTROL);
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IOWRITE64_PDUMP(val64, VHA_CR_CNN_OUTPACK_MH_CONTROL);
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IOWRITE64_PDUMP(val64, VHA_CR_CNN_ELEMENTOPS_MH_CONTROL);
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}
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void vha_dev_hwwdt_setup(struct vha_dev *vha, uint64_t cycles, uint64_t mode)
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{
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if (!mode)
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mode = VHA_CR_CNN_WDT_CTRL_CNN_WDT_CTRL_KICK_PASS;
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dev_dbg(vha->dev, "%s: cycles:%llx mode:%llx\n", __func__, cycles, mode);
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/* Note: Do not pdump the main watchdog as it may trigger
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* during memory latency/stalling testing */
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if (cycles) {
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IOWRITE64(vha->reg_base, VHA_CR_CNN_WDT_COMPAREMATCH,
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cycles & VHA_CR_CNN_WDT_COMPAREMATCH_MASKFULL);
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IOWRITE64(vha->reg_base, VHA_CR_CNN_WDT_CTRL,
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mode & VHA_CR_CNN_WDT_CTRL_CNN_WDT_CTRL_MASK);
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} else {
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IOWRITE64(vha->reg_base, VHA_CR_CNN_WDT_CTRL,
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VHA_CR_CNN_WDT_CTRL_CNN_WDT_CTRL_NONE);
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}
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/* Clear timer value just for sanity */
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IOWRITE64(vha->reg_base, VHA_CR_CNN_WDT_TIMER, 0);
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/* Note: We are not enabling MEM_WDT because it will not detect
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* issues due to the BIF/MMU or the customers memory fabric.
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* We could in theory enable this in customer systems,
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* but there is always a risk that it would result in false negatives
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* if there memory latency went very high temporarily.
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* HW team set this watchdog externally */
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#if 0
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IOWRITE64(vha->reg_base, VHA_CR_CNN_MEM_WDT_COMPAREMATCH, 0xfffff);
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IOWRITE64(vha->reg_base, VHA_CR_CNN_MEM_WDT_CTRL,
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VHA_CR_CNN_MEM_WDT_CTRL_CNN_MEM_WDT_CTRL_KICK_PASS);
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/* Clear timer value */
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IOWRITE64(vha->reg_base + VHA_CR_CNN_MEM_WDT_TIMER, 0);
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#endif
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}
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int vha_dev_hwwdt_calculate(struct vha_dev *vha, struct vha_cmd *cmd,
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uint64_t *cycles, uint64_t *mode)
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{
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const struct vha_user_cnn_submit_cmd *user_cmd =
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(struct vha_user_cnn_submit_cmd *)&cmd->user_cmd;
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if (!cycles || !mode)
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return -EINVAL;
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if (user_cmd && user_cmd->estimated_cycles && cnn_wdt_cycles == -1) {
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/* allow 40%, by default, above the estimated cycle count.
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* Clamp at uint32_t maximum */
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uint64_t wdt_cycles = user_cmd->estimated_cycles;
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uint64_t margin = wdt_cycles * cnn_wdt_cycles_margin;
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do_div(margin, 100UL);
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dev_dbg(vha->dev,
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"%s: estimated wdt cycles:%llx + margin:%llx\n",
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__func__, wdt_cycles, margin);
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wdt_cycles += margin;
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if (wdt_cycles > 0xffffffff)
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wdt_cycles = 0xffffffff;
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/* estimated cycle is per segment */
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*cycles = wdt_cycles;
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*mode = VHA_CR_CNN_WDT_CTRL_CNN_WDT_CTRL_KICK;
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} else {
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/* default value is per pass.
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* If default is 0 cycles it disables the watchdog */
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*cycles = cnn_wdt_cycles;
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*mode = VHA_CR_CNN_WDT_CTRL_CNN_WDT_CTRL_KICK_PASS;
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}
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vha->wdt_mode = *mode;
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return 0;
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}
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int vha_dev_prepare(struct vha_dev *vha)
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{
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/* Nothing to do */
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return 0;
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}
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void vha_dev_setup(struct vha_dev *vha)
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{
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vha->is_ready = true;
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}
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void vha_dev_wait(struct vha_dev *vha)
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{
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/* Nothing to do */
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}
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uint32_t vha_dev_kick_prepare(struct vha_dev *vha,
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struct vha_cmd *cmd, int ctx_id)
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{
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/* write to the START bit */
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uint32_t val = (min(2048U, cmd->stream_size)/32-1)
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<< VHA_CR_OS(CNN_CONTROL_CMD_SIZE_MIN1_SHIFT);
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val |= VHA_CR_OS(CNN_CONTROL_START_EN);
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return val;
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}
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