diff --git a/arch/riscv/Kconfig b/arch/riscv/Kconfig index 94ca69844..8d9715b87 100644 --- a/arch/riscv/Kconfig +++ b/arch/riscv/Kconfig @@ -393,42 +393,14 @@ config FPU If you don't know what to do here, say Y. config VECTOR - bool "VECTOR support" - default n - -choice VECTOR_VERSION - prompt "Vector Version" - depends on VECTOR - default VECTOR_1_0 - -config VECTOR_1_0 - bool "VECTOR 1.0 support" - help - Say N here if you want to disable all vector 1.0 related procedure - in the kernel. - - If you don't know what to do here, say Y. - -config VECTOR_0_7 bool "VECTOR 0.7 support" + default y help Say N here if you want to disable all vector 0.7 related procedure in the kernel. If you don't know what to do here, say Y. -endchoice - -config VLEN_256 - bool "VECTOR VLEN 256" - depends on VECTOR - default n - -config VECTOR_EMU - bool "VECTOR e64 emulate for c906 v1" - depends on VECTOR - default n - config THEAD_ISA bool "T-HEAD extension ISA in AFLAGS with -march=_xtheadc" default n diff --git a/arch/riscv/Makefile b/arch/riscv/Makefile index 25109ba9e..1d609c3f3 100644 --- a/arch/riscv/Makefile +++ b/arch/riscv/Makefile @@ -52,8 +52,7 @@ riscv-march-$(CONFIG_ARCH_RV32I) := rv32ima riscv-march-$(CONFIG_ARCH_RV64I) := rv64ima riscv-march-$(CONFIG_FPU) := $(riscv-march-y)fd riscv-march-$(CONFIG_RISCV_ISA_C) := $(riscv-march-y)c -riscv-march-$(CONFIG_VECTOR_1_0) := $(riscv-march-y)v -riscv-march-$(CONFIG_VECTOR_0_7) := $(riscv-march-y)v0p7 +riscv-march-$(CONFIG_VECTOR) := $(riscv-march-y)v0p7 riscv-march-$(CONFIG_THEAD_ISA) := $(riscv-march-y)_xtheadc # Newer binutils versions default to ISA spec version 20191213 which moves some diff --git a/arch/riscv/include/asm/csr.h b/arch/riscv/include/asm/csr.h index 2eab1caf4..983165ea1 100644 --- a/arch/riscv/include/asm/csr.h +++ b/arch/riscv/include/asm/csr.h @@ -26,19 +26,11 @@ #define SR_VS_OFF _AC(0x00000000, UL) -#if (defined(CONFIG_VECTOR_1_0) && defined(__THEAD_VERSION__)) -#define SR_VS _AC(0x00000600, UL) /* Vector Status */ -#define SR_VS_INITIAL _AC(0x00000200, UL) -#define SR_VS_CLEAN _AC(0x00000400, UL) -#define SR_VS_DIRTY _AC(0x00000600, UL) -#else #define SR_VS _AC(0x01800000, UL) /* Vector Status */ #define SR_VS_INITIAL _AC(0x00800000, UL) #define SR_VS_CLEAN _AC(0x01000000, UL) #define SR_VS_DIRTY _AC(0x01800000, UL) -#endif - #define SR_XS _AC(0x00018000, UL) /* Extension Status */ #define SR_XS_OFF _AC(0x00000000, UL) #define SR_XS_INITIAL _AC(0x00008000, UL) diff --git a/arch/riscv/kernel/vector.S b/arch/riscv/kernel/vector.S index 88221a1a4..7bfcd96e5 100644 --- a/arch/riscv/kernel/vector.S +++ b/arch/riscv/kernel/vector.S @@ -20,14 +20,6 @@ #include #include -#if (defined(CONFIG_VECTOR_1_0) && defined(__THEAD_VERSION__)) -#define V_ST vse8.v -#define V_LD vle8.v -#else -#define V_ST vsb.v -#define V_LD vlb.v -#endif - ENTRY(__vstate_save) li a2, TASK_THREAD_V0 add a0, a0, a2 @@ -46,81 +38,14 @@ ENTRY(__vstate_save) csrr t0, CSR_VTYPE sd t0, TASK_THREAD_VTYPE_V0(a0) -#ifdef CONFIG_VLEN_256 - vsetvli t0, x0, e8,m1 - V_ST v0, (a0) - addi a0, a0, RISCV_VECTOR_VLENB - V_ST v1, (a0) - addi a0, a0, RISCV_VECTOR_VLENB - V_ST v2, (a0) - addi a0, a0, RISCV_VECTOR_VLENB - V_ST v3, (a0) - addi a0, a0, RISCV_VECTOR_VLENB - V_ST v4, (a0) - addi a0, a0, RISCV_VECTOR_VLENB - V_ST v5, (a0) - addi a0, a0, RISCV_VECTOR_VLENB - V_ST v6, (a0) - addi a0, a0, RISCV_VECTOR_VLENB - V_ST v7, (a0) - addi a0, a0, RISCV_VECTOR_VLENB - V_ST v8, (a0) - addi a0, a0, RISCV_VECTOR_VLENB - V_ST v9, (a0) - addi a0, a0, RISCV_VECTOR_VLENB - V_ST v10, (a0) - addi a0, a0, RISCV_VECTOR_VLENB - V_ST v11, (a0) - addi a0, a0, RISCV_VECTOR_VLENB - V_ST v12, (a0) - addi a0, a0, RISCV_VECTOR_VLENB - V_ST v13, (a0) - addi a0, a0, RISCV_VECTOR_VLENB - V_ST v14, (a0) - addi a0, a0, RISCV_VECTOR_VLENB - V_ST v15, (a0) - addi a0, a0, RISCV_VECTOR_VLENB - V_ST v16, (a0) - addi a0, a0, RISCV_VECTOR_VLENB - V_ST v17, (a0) - addi a0, a0, RISCV_VECTOR_VLENB - V_ST v18, (a0) - addi a0, a0, RISCV_VECTOR_VLENB - V_ST v19, (a0) - addi a0, a0, RISCV_VECTOR_VLENB - V_ST v20, (a0) - addi a0, a0, RISCV_VECTOR_VLENB - V_ST v21, (a0) - addi a0, a0, RISCV_VECTOR_VLENB - V_ST v22, (a0) - addi a0, a0, RISCV_VECTOR_VLENB - V_ST v23, (a0) - addi a0, a0, RISCV_VECTOR_VLENB - V_ST v24, (a0) - addi a0, a0, RISCV_VECTOR_VLENB - V_ST v25, (a0) - addi a0, a0, RISCV_VECTOR_VLENB - V_ST v26, (a0) - addi a0, a0, RISCV_VECTOR_VLENB - V_ST v27, (a0) - addi a0, a0, RISCV_VECTOR_VLENB - V_ST v28, (a0) - addi a0, a0, RISCV_VECTOR_VLENB - V_ST v29, (a0) - addi a0, a0, RISCV_VECTOR_VLENB - V_ST v30, (a0) - addi a0, a0, RISCV_VECTOR_VLENB - V_ST v31, (a0) -#else vsetvli t0, x0, e8,m8 - V_ST v0, (a0) + vsb.v v0, (a0) addi a0, a0, RISCV_VECTOR_VLENB*8 - V_ST v8, (a0) + vsb.v v8, (a0) addi a0, a0, RISCV_VECTOR_VLENB*8 - V_ST v16, (a0) + vsb.v v16, (a0) addi a0, a0, RISCV_VECTOR_VLENB*8 - V_ST v24, (a0) -#endif + vsb.v v24, (a0) csrc sstatus, t1 ret @@ -134,81 +59,14 @@ ENTRY(__vstate_restore) li t1, (SR_VS | SR_FS) csrs sstatus, t1 -#ifdef CONFIG_VLEN_256 - vsetvli t0, x0, e8,m1 - V_LD v0, (a0) - addi a0, a0, RISCV_VECTOR_VLENB - V_LD v1, (a0) - addi a0, a0, RISCV_VECTOR_VLENB - V_LD v2, (a0) - addi a0, a0, RISCV_VECTOR_VLENB - V_LD v3, (a0) - addi a0, a0, RISCV_VECTOR_VLENB - V_LD v4, (a0) - addi a0, a0, RISCV_VECTOR_VLENB - V_LD v5, (a0) - addi a0, a0, RISCV_VECTOR_VLENB - V_LD v6, (a0) - addi a0, a0, RISCV_VECTOR_VLENB - V_LD v7, (a0) - addi a0, a0, RISCV_VECTOR_VLENB - V_LD v8, (a0) - addi a0, a0, RISCV_VECTOR_VLENB - V_LD v9, (a0) - addi a0, a0, RISCV_VECTOR_VLENB - V_LD v10, (a0) - addi a0, a0, RISCV_VECTOR_VLENB - V_LD v11, (a0) - addi a0, a0, RISCV_VECTOR_VLENB - V_LD v12, (a0) - addi a0, a0, RISCV_VECTOR_VLENB - V_LD v13, (a0) - addi a0, a0, RISCV_VECTOR_VLENB - V_LD v14, (a0) - addi a0, a0, RISCV_VECTOR_VLENB - V_LD v15, (a0) - addi a0, a0, RISCV_VECTOR_VLENB - V_LD v16, (a0) - addi a0, a0, RISCV_VECTOR_VLENB - V_LD v17, (a0) - addi a0, a0, RISCV_VECTOR_VLENB - V_LD v18, (a0) - addi a0, a0, RISCV_VECTOR_VLENB - V_LD v19, (a0) - addi a0, a0, RISCV_VECTOR_VLENB - V_LD v20, (a0) - addi a0, a0, RISCV_VECTOR_VLENB - V_LD v21, (a0) - addi a0, a0, RISCV_VECTOR_VLENB - V_LD v22, (a0) - addi a0, a0, RISCV_VECTOR_VLENB - V_LD v23, (a0) - addi a0, a0, RISCV_VECTOR_VLENB - V_LD v24, (a0) - addi a0, a0, RISCV_VECTOR_VLENB - V_LD v25, (a0) - addi a0, a0, RISCV_VECTOR_VLENB - V_LD v26, (a0) - addi a0, a0, RISCV_VECTOR_VLENB - V_LD v27, (a0) - addi a0, a0, RISCV_VECTOR_VLENB - V_LD v28, (a0) - addi a0, a0, RISCV_VECTOR_VLENB - V_LD v29, (a0) - addi a0, a0, RISCV_VECTOR_VLENB - V_LD v30, (a0) - addi a0, a0, RISCV_VECTOR_VLENB - V_LD v31, (a0) -#else vsetvli t0, x0, e8,m8 - V_LD v0, (a0) + vlb.v v0, (a0) addi a0, a0, RISCV_VECTOR_VLENB*8 - V_LD v8, (a0) + vlb.v v8, (a0) addi a0, a0, RISCV_VECTOR_VLENB*8 - V_LD v16, (a0) + vlb.v v16, (a0) addi a0, a0, RISCV_VECTOR_VLENB*8 - V_LD v24, (a0) -#endif + vlb.v v24, (a0) mv a0, t2 ld t0, TASK_THREAD_VSTART_V0(a0) @@ -219,16 +77,9 @@ ENTRY(__vstate_restore) csrw CSR_VXRM, t0 ld t0, TASK_THREAD_VL_V0(a0) ld t2, TASK_THREAD_VTYPE_V0(a0) -#ifdef CONFIG_VECTOR_EMU - srli t3, t2, 63 - bne t3,zero,1f -#endif + vsetvl t3, t0, t2 -#ifdef CONFIG_VECTOR_EMU - j 2f -1: vsetvli zero,zero,e64,m2,d1 -2: -#endif + csrc sstatus, t1 ret ENDPROC(__vstate_restore)