From 40ef3b0976effabc6e9698d7ca33a0f8856e575c Mon Sep 17 00:00:00 2001 From: Robert Nelson Date: Fri, 28 Apr 2023 18:05:24 -0500 Subject: [PATCH] sync: device-tree changes from main repo Signed-off-by: Robert Nelson --- .../dts/thead/light-beagle-bone-buses.dtsi | 761 ++++++++++++++++++ .../riscv/boot/dts/thead/light-beagle-ref.dts | 326 +++----- arch/riscv/boot/dts/thead/light-beagle.dts | 3 +- arch/riscv/boot/dts/thead/light.dtsi | 4 + .../dt-bindings/board/light-fm-bone-pins.h | 293 +++++++ include/dt-bindings/pinctrl/light.h | 53 ++ 6 files changed, 1238 insertions(+), 202 deletions(-) create mode 100644 arch/riscv/boot/dts/thead/light-beagle-bone-buses.dtsi create mode 100644 include/dt-bindings/board/light-fm-bone-pins.h create mode 100644 include/dt-bindings/pinctrl/light.h diff --git a/arch/riscv/boot/dts/thead/light-beagle-bone-buses.dtsi b/arch/riscv/boot/dts/thead/light-beagle-bone-buses.dtsi new file mode 100644 index 000000000..ab1eb1885 --- /dev/null +++ b/arch/riscv/boot/dts/thead/light-beagle-bone-buses.dtsi @@ -0,0 +1,761 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (C) 2022 BeagleBoard.org - https://beagleboard.org/ + */ + +#include +#include + +/********/ +/* LEDs */ +/********/ +&{/} { + gpio-leds { + compatible = "gpio-leds"; + pinctrl-names = "default"; + + /* macro: BONE_LED() */ + #define BONE_LED(PX_YY)\ + bone_led_##PX_YY##: led_##PX_YY {\ + status = "disabled";\ + linux,default-trigger = "default-off";\ + gpios = ;\ + pinctrl-0 = < &##PX_YY##_gpio_pin >;\ + }; + + /*P8 header Bone LEDs*/ + BONE_LED(P8_03) + BONE_LED(P8_04) + BONE_LED(P8_05) + BONE_LED(P8_06) + BONE_LED(P8_07) + BONE_LED(P8_08) + BONE_LED(P8_09) + BONE_LED(P8_10) + BONE_LED(P8_11) + BONE_LED(P8_12) + BONE_LED(P8_13) + BONE_LED(P8_14) + BONE_LED(P8_15) + BONE_LED(P8_16) + BONE_LED(P8_17) + BONE_LED(P8_18) + BONE_LED(P8_19) + BONE_LED(P8_20) + BONE_LED(P8_21) + BONE_LED(P8_22) + BONE_LED(P8_23) + BONE_LED(P8_24) + BONE_LED(P8_25) + BONE_LED(P8_26) + BONE_LED(P8_27) + BONE_LED(P8_28) + BONE_LED(P8_29) + BONE_LED(P8_30) + BONE_LED(P8_31) + BONE_LED(P8_32) + BONE_LED(P8_33) + BONE_LED(P8_34) + BONE_LED(P8_35) + BONE_LED(P8_36) + BONE_LED(P8_37) + BONE_LED(P8_38) + BONE_LED(P8_39) + BONE_LED(P8_40) + BONE_LED(P8_41) + BONE_LED(P8_42) + BONE_LED(P8_43) + BONE_LED(P8_44) + BONE_LED(P8_45) + BONE_LED(P8_46) + + /*P9 header Bone LEDs*/ + BONE_LED(P9_11) + BONE_LED(P9_12) + BONE_LED(P9_13) + BONE_LED(P9_14) + BONE_LED(P9_15) + BONE_LED(P9_16) + BONE_LED(P9_17) + BONE_LED(P9_18) + BONE_LED(P9_19) + BONE_LED(P9_20) + BONE_LED(P9_21) + BONE_LED(P9_22) + BONE_LED(P9_23) + BONE_LED(P9_24) + BONE_LED(P9_25) + BONE_LED(P9_26) + BONE_LED(P9_27) + BONE_LED(P9_28) + BONE_LED(P9_29) + BONE_LED(P9_30) + BONE_LED(P9_31) + BONE_LED(P9_41) + BONE_LED(P9_42) + + /*mikroBus*/ + BONE_LED(mb_pwm) + BONE_LED(mb_rst) + BONE_LED(mb_int) + BONE_LED(mb_rxd) + BONE_LED(mb_txd) + BONE_LED(mb_cs) + BONE_LED(mb_sck) + BONE_LED(mb_mosi) + BONE_LED(mb_miso) + BONE_LED(mb_scl) + BONE_LED(mb_sda) + }; + + /* Dummy driver to request setup for cape header pins */ + cape_header: pinmux_dummy { + compatible = "gpio-leds"; + pinctrl-names = "default"; + status = "okay"; + pinctrl-0 = < + &P8_03_gpio_pin + &P8_04_gpio_pin + &P8_05_gpio_pin + &P8_06_gpio_pin + &P8_07_gpio_pin + &P8_08_gpio_pin + &P8_09_gpio_pin + &P8_10_gpio_pin + &P8_11_gpio_pin + &P8_12_gpio_pin + &P8_13_gpio_pin + &P8_14_gpio_pin + &P8_15_gpio_pin + &P8_16_gpio_pin + &P8_17_gpio_pin + &P8_18_gpio_pin + &P8_19_gpio_pin + &P8_20_gpio_pin + &P8_21_gpio_pin + &P8_22_gpio_pin + &P8_23_gpio_pin + &P8_24_gpio_pin + &P8_25_gpio_pin + &P8_26_gpio_pin + &P8_27_gpio_pin + &P8_28_gpio_pin + &P8_29_gpio_pin + &P8_30_gpio_pin + &P8_31_gpio_pin + &P8_32_gpio_pin + &P8_33_gpio_pin + &P8_34_gpio_pin + &P8_35_gpio_pin + &P8_36_gpio_pin + &P8_37_gpio_pin + &P8_38_gpio_pin + &P8_39_gpio_pin + &P8_40_gpio_pin + &P8_41_gpio_pin + &P8_42_gpio_pin + &P8_43_gpio_pin + &P8_44_gpio_pin + &P8_45_gpio_pin + &P8_46_gpio_pin + &P9_11_gpio_pin + &P9_12_gpio_pin + &P9_13_gpio_pin + &P9_14_gpio_pin + &P9_15_gpio_pin + &P9_16_gpio_pin + &P9_17_gpio_pin + &P9_18_gpio_pin + &P9_19_gpio_pin + &P9_20_gpio_pin + &P9_21_gpio_pin + &P9_22_gpio_pin + &P9_23_gpio_pin + &P9_24_gpio_pin + &P9_25_gpio_pin + &P9_26_gpio_pin + &P9_27_gpio_pin + &P9_28_gpio_pin + &P9_29_gpio_pin + &P9_30_gpio_pin + &P9_31_gpio_pin + &P9_41_gpio_pin + &P9_42_gpio_pin + >; + }; +}; + +/* macro: BONE_PIN( , , ) */ +#define BONE_PIN(XX,ZZ,QQ) \ + padctrl_##XX { \ + XX##_##ZZ##_pin: pinmux_##XX##_##ZZ##_pin \ + { thead,pins = < QQ >; }; \ + }; + +/* Full P8/P9 header mode definitions */ + +/* P8_01 - GND */ +/* P8_02 - GND */ + +/* P8_03 (Ball:J34) GPIO1_21_MUX*/ +BONE_PIN(P8_03, default, P8_03(MUX_MODE3, (PIN_INPUT | STRENGTH_MID))) +BONE_PIN(P8_03, gpio, P8_03(MUX_MODE3, (PIN_INPUT | STRENGTH_MID))) +BONE_PIN(P8_03, gpio_pu, P8_03(MUX_MODE3, (PIN_INPUT_PULLUP | STRENGTH_MID))) +BONE_PIN(P8_03, gpio_pd, P8_03(MUX_MODE3, (PIN_INPUT_PULLDOWN | STRENGTH_MID))) + +/* P8_04 (Ball:J35) GPIO1_22_MUX*/ +BONE_PIN(P8_04, default, P8_04(MUX_MODE3, (PIN_INPUT | STRENGTH_MID))) +BONE_PIN(P8_04, gpio, P8_04(MUX_MODE3, (PIN_INPUT | STRENGTH_MID))) +BONE_PIN(P8_04, gpio_pu, P8_04(MUX_MODE3, (PIN_INPUT_PULLUP | STRENGTH_MID))) +BONE_PIN(P8_04, gpio_pd, P8_04(MUX_MODE3, (PIN_INPUT_PULLDOWN | STRENGTH_MID))) + +/* P8_05 (Ball:K32) GPIO1_23_MUX*/ +BONE_PIN(P8_05, default, P8_05(MUX_MODE3, (PIN_INPUT | STRENGTH_MID))) +BONE_PIN(P8_05, gpio, P8_05(MUX_MODE3, (PIN_INPUT | STRENGTH_MID))) +BONE_PIN(P8_05, gpio_pu, P8_05(MUX_MODE3, (PIN_INPUT_PULLUP | STRENGTH_MID))) +BONE_PIN(P8_05, gpio_pd, P8_05(MUX_MODE3, (PIN_INPUT_PULLDOWN | STRENGTH_MID))) + +/* P8_06 (Ball:K33) GPIO1_24_MUX*/ +BONE_PIN(P8_06, default, P8_06(MUX_MODE3, (PIN_INPUT | STRENGTH_MID))) +BONE_PIN(P8_06, gpio, P8_06(MUX_MODE3, (PIN_INPUT | STRENGTH_MID))) +BONE_PIN(P8_06, gpio_pu, P8_06(MUX_MODE3, (PIN_INPUT_PULLUP | STRENGTH_MID))) +BONE_PIN(P8_06, gpio_pd, P8_06(MUX_MODE3, (PIN_INPUT_PULLDOWN | STRENGTH_MID))) + +/* P8_07 (Ball:K34) GPIO1_25_MUX*/ +BONE_PIN(P8_07, default, P8_07(MUX_MODE3, (PIN_INPUT | STRENGTH_MID))) +BONE_PIN(P8_07, gpio, P8_07(MUX_MODE3, (PIN_INPUT | STRENGTH_MID))) +BONE_PIN(P8_07, gpio_pu, P8_07(MUX_MODE3, (PIN_INPUT_PULLUP | STRENGTH_MID))) +BONE_PIN(P8_07, gpio_pd, P8_07(MUX_MODE3, (PIN_INPUT_PULLDOWN | STRENGTH_MID))) + +/* P8_08 (Ball:K35) GPIO1_26_MUX*/ +BONE_PIN(P8_08, default, P8_08(MUX_MODE0, (PIN_INPUT | STRENGTH_MID))) +BONE_PIN(P8_08, gpio, P8_08(MUX_MODE0, (PIN_INPUT | STRENGTH_MID))) +BONE_PIN(P8_08, gpio_pu, P8_08(MUX_MODE0, (PIN_INPUT_PULLUP | STRENGTH_MID))) +BONE_PIN(P8_08, gpio_pd, P8_08(MUX_MODE0, (PIN_INPUT_PULLDOWN | STRENGTH_MID))) + +/* P8_09 (Ball:K36) GPIO1_27_MUX*/ +BONE_PIN(P8_09, default, P8_09(MUX_MODE0, (PIN_INPUT | STRENGTH_MID))) +BONE_PIN(P8_09, gpio, P8_09(MUX_MODE0, (PIN_INPUT | STRENGTH_MID))) +BONE_PIN(P8_09, gpio_pu, P8_09(MUX_MODE0, (PIN_INPUT_PULLUP | STRENGTH_MID))) +BONE_PIN(P8_09, gpio_pd, P8_09(MUX_MODE0, (PIN_INPUT_PULLDOWN | STRENGTH_MID))) + +/* P8_10 (Ball:K37) GPIO1_28_MUX*/ +BONE_PIN(P8_10, default, P8_10(MUX_MODE0, (PIN_INPUT | STRENGTH_MID))) +BONE_PIN(P8_10, gpio, P8_10(MUX_MODE0, (PIN_INPUT | STRENGTH_MID))) +BONE_PIN(P8_10, gpio_pu, P8_10(MUX_MODE0, (PIN_INPUT_PULLUP | STRENGTH_MID))) +BONE_PIN(P8_10, gpio_pd, P8_10(MUX_MODE0, (PIN_INPUT_PULLDOWN | STRENGTH_MID))) + +/* P8_11 (Ball:L32) GPIO1_29_MUX*/ +BONE_PIN(P8_11, default, P8_11(MUX_MODE0, (PIN_INPUT | STRENGTH_MID))) +BONE_PIN(P8_11, gpio, P8_11(MUX_MODE0, (PIN_INPUT | STRENGTH_MID))) +BONE_PIN(P8_11, gpio_pu, P8_11(MUX_MODE0, (PIN_INPUT_PULLUP | STRENGTH_MID))) +BONE_PIN(P8_11, gpio_pd, P8_11(MUX_MODE0, (PIN_INPUT_PULLDOWN | STRENGTH_MID))) + +/* P8_12 (Ball:L33) GPIO1_30_MUX*/ +BONE_PIN(P8_12, default, P8_12(MUX_MODE0, (PIN_INPUT | STRENGTH_MID))) +BONE_PIN(P8_12, gpio, P8_12(MUX_MODE0, (PIN_INPUT | STRENGTH_MID))) +BONE_PIN(P8_12, gpio_pu, P8_12(MUX_MODE0, (PIN_INPUT_PULLUP | STRENGTH_MID))) +BONE_PIN(P8_12, gpio_pd, P8_12(MUX_MODE0, (PIN_INPUT_PULLDOWN | STRENGTH_MID))) + +/* P8_13 (Ball:C6) GPIO3_2_MUX*/ +BONE_PIN(P8_13, default, P8_13(MUX_MODE0, (PIN_INPUT | STRENGTH_MID))) +BONE_PIN(P8_13, gpio, P8_13(MUX_MODE0, (PIN_INPUT | STRENGTH_MID))) +BONE_PIN(P8_13, gpio_pu, P8_13(MUX_MODE0, (PIN_INPUT_PULLUP | STRENGTH_MID))) +BONE_PIN(P8_13, gpio_pd, P8_13(MUX_MODE0, (PIN_INPUT_PULLDOWN | STRENGTH_MID))) +BONE_PIN(P8_13, pwm, P8_13(MUX_MODE1, (PIN_OUTPUT | STRENGTH_MID))) + +/* P8_14 (Ball:E29) CLK_OUT_3_MUX*/ +BONE_PIN(P8_14, default, P8_14(MUX_MODE3, (PIN_INPUT | STRENGTH_MID))) +BONE_PIN(P8_14, gpio, P8_14(MUX_MODE3, (PIN_INPUT | STRENGTH_MID))) +BONE_PIN(P8_14, gpio_pu, P8_14(MUX_MODE3, (PIN_INPUT_PULLUP | STRENGTH_MID))) +BONE_PIN(P8_14, gpio_pd, P8_14(MUX_MODE3, (PIN_INPUT_PULLDOWN | STRENGTH_MID))) + +/* P8_15 (Ball:A6) GPIO3_0_MUX*/ +BONE_PIN(P8_15, default, P8_15(MUX_MODE0, (PIN_INPUT | STRENGTH_MID))) +BONE_PIN(P8_15, gpio, P8_15(MUX_MODE0, (PIN_INPUT | STRENGTH_MID))) +BONE_PIN(P8_15, gpio_pu, P8_15(MUX_MODE0, (PIN_INPUT_PULLUP | STRENGTH_MID))) +BONE_PIN(P8_15, gpio_pd, P8_15(MUX_MODE0, (PIN_INPUT_PULLDOWN | STRENGTH_MID))) + +/* P8_16 (Ball:F34) GPIO0_20_MUX*/ +BONE_PIN(P8_16, default, P8_16(MUX_MODE0, (PIN_INPUT | STRENGTH_MID))) +BONE_PIN(P8_16, gpio, P8_16(MUX_MODE0, (PIN_INPUT | STRENGTH_MID))) +BONE_PIN(P8_16, gpio_pu, P8_16(MUX_MODE0, (PIN_INPUT_PULLUP | STRENGTH_MID))) +BONE_PIN(P8_16, gpio_pd, P8_16(MUX_MODE0, (PIN_INPUT_PULLDOWN | STRENGTH_MID))) +BONE_PIN(P8_16, uart, P8_16(MUX_MODE1, (PIN_OUTPUT | STRENGTH_MID))) + +/* P8_17 (Ball:B6) GPIO3_1_MUX*/ +BONE_PIN(P8_17, default, P8_17(MUX_MODE0, (PIN_INPUT | STRENGTH_MID))) +BONE_PIN(P8_17, gpio, P8_17(MUX_MODE0, (PIN_INPUT | STRENGTH_MID))) +BONE_PIN(P8_17, gpio_pu, P8_17(MUX_MODE0, (PIN_INPUT_PULLUP | STRENGTH_MID))) +BONE_PIN(P8_17, gpio_pd, P8_17(MUX_MODE0, (PIN_INPUT_PULLDOWN | STRENGTH_MID))) + +/* P8_18 (Ball:B34) GPIO1_5_MUX*/ +BONE_PIN(P8_18, default, P8_18(MUX_MODE0, (PIN_INPUT | STRENGTH_MID))) +BONE_PIN(P8_18, gpio, P8_18(MUX_MODE0, (PIN_INPUT | STRENGTH_MID))) +BONE_PIN(P8_18, gpio_pu, P8_18(MUX_MODE0, (PIN_INPUT_PULLUP | STRENGTH_MID))) +BONE_PIN(P8_18, gpio_pd, P8_18(MUX_MODE0, (PIN_INPUT_PULLDOWN | STRENGTH_MID))) + +/* P8_19 (Ball:D6) GPIO3_3_MUX*/ +BONE_PIN(P8_19, default, P8_19(MUX_MODE0, (PIN_INPUT | STRENGTH_MID))) +BONE_PIN(P8_19, gpio, P8_19(MUX_MODE0, (PIN_INPUT | STRENGTH_MID))) +BONE_PIN(P8_19, gpio_pu, P8_19(MUX_MODE0, (PIN_INPUT_PULLUP | STRENGTH_MID))) +BONE_PIN(P8_19, gpio_pd, P8_19(MUX_MODE0, (PIN_INPUT_PULLDOWN | STRENGTH_MID))) +BONE_PIN(P8_19, pwm, P8_19(MUX_MODE1, (PIN_OUTPUT | STRENGTH_MID))) + +/* P8_20 (Ball:C34) GPIO1_6_MUX*/ +BONE_PIN(P8_20, default, P8_20(MUX_MODE0, (PIN_INPUT | STRENGTH_MID))) +BONE_PIN(P8_20, gpio, P8_20(MUX_MODE0, (PIN_INPUT | STRENGTH_MID))) +BONE_PIN(P8_20, gpio_pu, P8_20(MUX_MODE0, (PIN_INPUT_PULLUP | STRENGTH_MID))) +BONE_PIN(P8_20, gpio_pd, P8_20(MUX_MODE0, (PIN_INPUT_PULLDOWN | STRENGTH_MID))) + +/* P8_21 (Ball:D34) GPIO1_7_MUX*/ +BONE_PIN(P8_21, default, P8_21(MUX_MODE0, (PIN_INPUT | STRENGTH_MID))) +BONE_PIN(P8_21, gpio, P8_21(MUX_MODE0, (PIN_INPUT | STRENGTH_MID))) +BONE_PIN(P8_21, gpio_pu, P8_21(MUX_MODE0, (PIN_INPUT_PULLUP | STRENGTH_MID))) +BONE_PIN(P8_21, gpio_pd, P8_21(MUX_MODE0, (PIN_INPUT_PULLDOWN | STRENGTH_MID))) +BONE_PIN(P8_21, spi, P8_21(MUX_MODE1, (PIN_OUTPUT | STRENGTH_MID))) + +/* P8_22 (Ball:B35) GPIO1_8_MUX*/ +BONE_PIN(P8_22, default, P8_22(MUX_MODE0, (PIN_INPUT | STRENGTH_MID))) +BONE_PIN(P8_22, gpio, P8_22(MUX_MODE0, (PIN_INPUT | STRENGTH_MID))) +BONE_PIN(P8_22, gpio_pu, P8_22(MUX_MODE0, (PIN_INPUT_PULLUP | STRENGTH_MID))) +BONE_PIN(P8_22, gpio_pd, P8_22(MUX_MODE0, (PIN_INPUT_PULLDOWN | STRENGTH_MID))) +BONE_PIN(P8_22, spi, P8_22(MUX_MODE1, (PIN_OUTPUT | STRENGTH_MID))) + +/* P8_23 (Ball:A36) GPIO1_9_MUX*/ +BONE_PIN(P8_23, default, P8_23(MUX_MODE0, (PIN_INPUT | STRENGTH_MID))) +BONE_PIN(P8_23, gpio, P8_23(MUX_MODE0, (PIN_INPUT | STRENGTH_MID))) +BONE_PIN(P8_23, gpio_pu, P8_23(MUX_MODE0, (PIN_INPUT_PULLUP | STRENGTH_MID))) +BONE_PIN(P8_23, gpio_pd, P8_23(MUX_MODE0, (PIN_INPUT_PULLDOWN | STRENGTH_MID))) +BONE_PIN(P8_23, spi, P8_23(MUX_MODE1, (PIN_OUTPUT | STRENGTH_MID))) + +/* P8_24 (Ball:B36) GPIO1_10_MUX*/ +BONE_PIN(P8_24, default, P8_24(MUX_MODE0, (PIN_INPUT | STRENGTH_MID))) +BONE_PIN(P8_24, gpio, P8_24(MUX_MODE0, (PIN_INPUT | STRENGTH_MID))) +BONE_PIN(P8_24, gpio_pu, P8_24(MUX_MODE0, (PIN_INPUT_PULLUP | STRENGTH_MID))) +BONE_PIN(P8_24, gpio_pd, P8_24(MUX_MODE0, (PIN_INPUT_PULLDOWN | STRENGTH_MID))) +BONE_PIN(P8_24, spi, P8_24(MUX_MODE1, (PIN_INPUT | STRENGTH_MID))) + +/* P8_25 (Ball:B37) GPIO1_11_MUX*/ +BONE_PIN(P8_25, default, P8_25(MUX_MODE0, (PIN_INPUT | STRENGTH_MID))) +BONE_PIN(P8_25, gpio, P8_25(MUX_MODE0, (PIN_INPUT | STRENGTH_MID))) +BONE_PIN(P8_25, gpio_pu, P8_25(MUX_MODE0, (PIN_INPUT_PULLUP | STRENGTH_MID))) +BONE_PIN(P8_25, gpio_pd, P8_25(MUX_MODE0, (PIN_INPUT_PULLDOWN | STRENGTH_MID))) + +/* P8_26 (Ball:C36) GPIO1_12_MUX*/ +BONE_PIN(P8_26, default, P8_26(MUX_MODE0, (PIN_INPUT | STRENGTH_MID))) +BONE_PIN(P8_26, gpio, P8_26(MUX_MODE0, (PIN_INPUT | STRENGTH_MID))) +BONE_PIN(P8_26, gpio_pu, P8_26(MUX_MODE0, (PIN_INPUT_PULLUP | STRENGTH_MID))) +BONE_PIN(P8_26, gpio_pd, P8_26(MUX_MODE0, (PIN_INPUT_PULLDOWN | STRENGTH_MID))) + +/* P8_27 (Ball:D37) GPIO1_15_MUX*/ +BONE_PIN(P8_27, default, P8_27(MUX_MODE0, (PIN_INPUT | STRENGTH_MID))) +BONE_PIN(P8_27, gpio, P8_27(MUX_MODE0, (PIN_INPUT | STRENGTH_MID))) +BONE_PIN(P8_27, gpio_pu, P8_27(MUX_MODE0, (PIN_INPUT_PULLUP | STRENGTH_MID))) +BONE_PIN(P8_27, gpio_pd, P8_27(MUX_MODE0, (PIN_INPUT_PULLDOWN | STRENGTH_MID))) + +/* P8_28 (Ball:E34) GPIO1_16_MUX*/ +BONE_PIN(P8_28, default, P8_28(MUX_MODE0, (PIN_INPUT | STRENGTH_MID))) +BONE_PIN(P8_28, gpio, P8_28(MUX_MODE0, (PIN_INPUT | STRENGTH_MID))) +BONE_PIN(P8_28, gpio_pu, P8_28(MUX_MODE0, (PIN_INPUT_PULLUP | STRENGTH_MID))) +BONE_PIN(P8_28, gpio_pd, P8_28(MUX_MODE0, (PIN_INPUT_PULLDOWN | STRENGTH_MID))) + +/* P8_29 (Ball:D36) GPIO1_14_MUX*/ +BONE_PIN(P8_29, default, P8_29(MUX_MODE0, (PIN_INPUT | STRENGTH_MID))) +BONE_PIN(P8_29, gpio, P8_29(MUX_MODE0, (PIN_INPUT | STRENGTH_MID))) +BONE_PIN(P8_29, gpio_pu, P8_29(MUX_MODE0, (PIN_INPUT_PULLUP | STRENGTH_MID))) +BONE_PIN(P8_29, gpio_pd, P8_29(MUX_MODE0, (PIN_INPUT_PULLDOWN | STRENGTH_MID))) +BONE_PIN(P8_29, uart, P8_29(MUX_MODE1, (PIN_INPUT | STRENGTH_MID))) + +/* P8_30 (Ball:D35) GPIO1_13_MUX*/ +BONE_PIN(P8_30, default, P8_30(MUX_MODE0, (PIN_INPUT | STRENGTH_MID))) +BONE_PIN(P8_30, gpio, P8_30(MUX_MODE0, (PIN_INPUT | STRENGTH_MID))) +BONE_PIN(P8_30, gpio_pu, P8_30(MUX_MODE0, (PIN_INPUT_PULLUP | STRENGTH_MID))) +BONE_PIN(P8_30, gpio_pd, P8_30(MUX_MODE0, (PIN_INPUT_PULLDOWN | STRENGTH_MID))) +BONE_PIN(P8_30, uart, P8_30(MUX_MODE1, (PIN_OUTPUT | STRENGTH_MID))) + +/* P8_31 (Ball:D33) GPIO1_3_MUX*/ +BONE_PIN(P8_31, default, P8_31(MUX_MODE0, (PIN_INPUT | STRENGTH_MID))) +BONE_PIN(P8_31, gpio, P8_31(MUX_MODE0, (PIN_INPUT | STRENGTH_MID))) +BONE_PIN(P8_31, gpio_pu, P8_31(MUX_MODE0, (PIN_INPUT_PULLUP | STRENGTH_MID))) +BONE_PIN(P8_31, gpio_pd, P8_31(MUX_MODE0, (PIN_INPUT_PULLDOWN | STRENGTH_MID))) + +/* P8_32 (Ball:A34) GPIO1_4_MUX*/ +BONE_PIN(P8_32, default, P8_32(MUX_MODE0, (PIN_INPUT | STRENGTH_MID))) +BONE_PIN(P8_32, gpio, P8_32(MUX_MODE0, (PIN_INPUT | STRENGTH_MID))) +BONE_PIN(P8_32, gpio_pu, P8_32(MUX_MODE0, (PIN_INPUT_PULLUP | STRENGTH_MID))) +BONE_PIN(P8_32, gpio_pd, P8_32(MUX_MODE0, (PIN_INPUT_PULLDOWN | STRENGTH_MID))) + +/* P8_33 (Ball:C33) GPIO1_2_MUX*/ +BONE_PIN(P8_33, default, P8_33(MUX_MODE0, (PIN_INPUT | STRENGTH_MID))) +BONE_PIN(P8_33, gpio, P8_33(MUX_MODE0, (PIN_INPUT | STRENGTH_MID))) +BONE_PIN(P8_33, gpio_pu, P8_33(MUX_MODE0, (PIN_INPUT_PULLUP | STRENGTH_MID))) +BONE_PIN(P8_33, gpio_pd, P8_33(MUX_MODE0, (PIN_INPUT_PULLDOWN | STRENGTH_MID))) + +/* P8_34 (Ball:E32) GPIO1_0_MUX*/ +BONE_PIN(P8_34, default, P8_34(MUX_MODE0, (PIN_INPUT | STRENGTH_MID))) +BONE_PIN(P8_34, gpio, P8_34(MUX_MODE0, (PIN_INPUT | STRENGTH_MID))) +BONE_PIN(P8_34, gpio_pu, P8_34(MUX_MODE0, (PIN_INPUT_PULLUP | STRENGTH_MID))) +BONE_PIN(P8_34, gpio_pd, P8_34(MUX_MODE0, (PIN_INPUT_PULLDOWN | STRENGTH_MID))) + +/* P8_35 (Ball:A32) GPIO1_1_MUX*/ +BONE_PIN(P8_35, default, P8_35(MUX_MODE0, (PIN_INPUT | STRENGTH_MID))) +BONE_PIN(P8_35, gpio, P8_35(MUX_MODE0, (PIN_INPUT | STRENGTH_MID))) +BONE_PIN(P8_35, gpio_pu, P8_35(MUX_MODE0, (PIN_INPUT_PULLUP | STRENGTH_MID))) +BONE_PIN(P8_35, gpio_pd, P8_35(MUX_MODE0, (PIN_INPUT_PULLDOWN | STRENGTH_MID))) + +/* P8_36 (Ball:D32) GPIO0_31_MUX*/ +BONE_PIN(P8_36, default, P8_36(MUX_MODE0, (PIN_INPUT | STRENGTH_MID))) +BONE_PIN(P8_36, gpio, P8_36(MUX_MODE0, (PIN_INPUT | STRENGTH_MID))) +BONE_PIN(P8_36, gpio_pu, P8_36(MUX_MODE0, (PIN_INPUT_PULLUP | STRENGTH_MID))) +BONE_PIN(P8_36, gpio_pd, P8_36(MUX_MODE0, (PIN_INPUT_PULLDOWN | STRENGTH_MID))) + +/* P8_37 (Ball:B32) GPIO0_29_MUX*/ +BONE_PIN(P8_37, default, P8_37(MUX_MODE0, (PIN_INPUT | STRENGTH_MID))) +BONE_PIN(P8_37, gpio, P8_37(MUX_MODE0, (PIN_INPUT | STRENGTH_MID))) +BONE_PIN(P8_37, gpio_pu, P8_37(MUX_MODE0, (PIN_INPUT_PULLUP | STRENGTH_MID))) +BONE_PIN(P8_37, gpio_pd, P8_37(MUX_MODE0, (PIN_INPUT_PULLDOWN | STRENGTH_MID))) + +/* P8_38 (Ball:C32) GPIO0_30_MUX*/ +BONE_PIN(P8_38, default, P8_38(MUX_MODE0, (PIN_INPUT | STRENGTH_MID))) +BONE_PIN(P8_38, gpio, P8_38(MUX_MODE0, (PIN_INPUT | STRENGTH_MID))) +BONE_PIN(P8_38, gpio_pu, P8_38(MUX_MODE0, (PIN_INPUT_PULLUP | STRENGTH_MID))) +BONE_PIN(P8_38, gpio_pd, P8_38(MUX_MODE0, (PIN_INPUT_PULLDOWN | STRENGTH_MID))) + +/* P8_39 (Ball:D31) GPIO0_27_MUX*/ +BONE_PIN(P8_39, default, P8_39(MUX_MODE0, (PIN_INPUT | STRENGTH_MID))) +BONE_PIN(P8_39, gpio, P8_39(MUX_MODE0, (PIN_INPUT | STRENGTH_MID))) +BONE_PIN(P8_39, gpio_pu, P8_39(MUX_MODE0, (PIN_INPUT_PULLUP | STRENGTH_MID))) +BONE_PIN(P8_39, gpio_pd, P8_39(MUX_MODE0, (PIN_INPUT_PULLDOWN | STRENGTH_MID))) +BONE_PIN(P8_39, i2c, P8_39(MUX_MODE2, (PIN_OUTPUT | STRENGTH_MID))) + +/* P8_40 (Ball:E31) GPIO0_28_MUX*/ +BONE_PIN(P8_40, default, P8_40(MUX_MODE0, (PIN_INPUT | STRENGTH_MID))) +BONE_PIN(P8_40, gpio, P8_40(MUX_MODE0, (PIN_INPUT | STRENGTH_MID))) +BONE_PIN(P8_40, gpio_pu, P8_40(MUX_MODE0, (PIN_INPUT_PULLUP | STRENGTH_MID))) +BONE_PIN(P8_40, gpio_pd, P8_40(MUX_MODE0, (PIN_INPUT_PULLDOWN | STRENGTH_MID))) +BONE_PIN(P8_40, i2c, P8_40(MUX_MODE2, (PIN_INPUT | STRENGTH_MID))) + +/* P8_41 (Ball:F30) GPIO0_25_MUX*/ +BONE_PIN(P8_41, default, P8_41(MUX_MODE0, (PIN_INPUT | STRENGTH_MID))) +BONE_PIN(P8_41, gpio, P8_41(MUX_MODE0, (PIN_INPUT | STRENGTH_MID))) +BONE_PIN(P8_41, gpio_pu, P8_41(MUX_MODE0, (PIN_INPUT_PULLUP | STRENGTH_MID))) +BONE_PIN(P8_41, gpio_pd, P8_41(MUX_MODE0, (PIN_INPUT_PULLDOWN | STRENGTH_MID))) + +/* P8_42 (Ball:C31) GPIO0_26_MUX*/ +BONE_PIN(P8_42, default, P8_42(MUX_MODE0, (PIN_INPUT | STRENGTH_MID))) +BONE_PIN(P8_42, gpio, P8_42(MUX_MODE0, (PIN_INPUT | STRENGTH_MID))) +BONE_PIN(P8_42, gpio_pu, P8_42(MUX_MODE0, (PIN_INPUT_PULLUP | STRENGTH_MID))) +BONE_PIN(P8_42, gpio_pd, P8_42(MUX_MODE0, (PIN_INPUT_PULLDOWN | STRENGTH_MID))) + +/* P8_43 (Ball:C30) GPIO0_23_MUX*/ +BONE_PIN(P8_43, default, P8_43(MUX_MODE0, (PIN_INPUT | STRENGTH_MID))) +BONE_PIN(P8_43, gpio, P8_43(MUX_MODE0, (PIN_INPUT | STRENGTH_MID))) +BONE_PIN(P8_43, gpio_pu, P8_43(MUX_MODE0, (PIN_INPUT_PULLUP | STRENGTH_MID))) +BONE_PIN(P8_43, gpio_pd, P8_43(MUX_MODE0, (PIN_INPUT_PULLDOWN | STRENGTH_MID))) +BONE_PIN(P8_43, i2c, P8_43(MUX_MODE2, (PIN_OUTPUT | STRENGTH_MID))) + +/* P8_44 (Ball:D30) GPIO0_24_MUX*/ +BONE_PIN(P8_44, default, P8_44(MUX_MODE0, (PIN_INPUT | STRENGTH_MID))) +BONE_PIN(P8_44, gpio, P8_44(MUX_MODE0, (PIN_INPUT | STRENGTH_MID))) +BONE_PIN(P8_44, gpio_pu, P8_44(MUX_MODE0, (PIN_INPUT_PULLUP | STRENGTH_MID))) +BONE_PIN(P8_44, gpio_pd, P8_44(MUX_MODE0, (PIN_INPUT_PULLDOWN | STRENGTH_MID))) + +/* P8_45 (Ball:F36) GPIO0_21_MUX*/ +BONE_PIN(P8_45, default, P8_45(MUX_MODE0, (PIN_INPUT | STRENGTH_MID))) +BONE_PIN(P8_45, gpio, P8_45(MUX_MODE0, (PIN_INPUT | STRENGTH_MID))) +BONE_PIN(P8_45, gpio_pu, P8_45(MUX_MODE0, (PIN_INPUT_PULLUP | STRENGTH_MID))) +BONE_PIN(P8_45, gpio_pd, P8_45(MUX_MODE0, (PIN_INPUT_PULLDOWN | STRENGTH_MID))) +BONE_PIN(P8_45, uart, P8_45(MUX_MODE1, (PIN_INPUT | STRENGTH_MID))) + +/* P8_46 (Ball:D29) GPIO0_22_MUX*/ +BONE_PIN(P8_46, default, P8_46(MUX_MODE0, (PIN_INPUT | STRENGTH_MID))) +BONE_PIN(P8_46, gpio, P8_46(MUX_MODE0, (PIN_INPUT | STRENGTH_MID))) +BONE_PIN(P8_46, gpio_pu, P8_46(MUX_MODE0, (PIN_INPUT_PULLUP | STRENGTH_MID))) +BONE_PIN(P8_46, gpio_pd, P8_46(MUX_MODE0, (PIN_INPUT_PULLDOWN | STRENGTH_MID))) +BONE_PIN(P8_46, i2c, P8_46(MUX_MODE2, (PIN_OUTPUT | STRENGTH_MID))) + +/* Full P9 header mode definitions */ +/* P9_01 - GND */ +/* P9_02 - GND */ +/* P9_03 - VOUT_3V3 */ +/* P9_04 - VOUT_3V3 */ +/* P9_05 - VIN */ +/* P9_06 - VIN */ +/* P9_07 - VOUT_SYS */ +/* P9_08 - VOUT_SYS */ +/* P9_09 - ONKEY# */ +/* P9_10 - RESET# */ + +/* P9_11 (Ball:M32) UART1_TXD_MUX*/ +BONE_PIN(P9_11, default, P9_11(MUX_MODE3, (PIN_INPUT | STRENGTH_MID))) +BONE_PIN(P9_11, gpio, P9_11(MUX_MODE3, (PIN_INPUT | STRENGTH_MID))) +BONE_PIN(P9_11, gpio_pu, P9_11(MUX_MODE3, (PIN_INPUT_PULLUP | STRENGTH_MID))) +BONE_PIN(P9_11, gpio_pd, P9_11(MUX_MODE3, (PIN_INPUT_PULLDOWN | STRENGTH_MID))) +BONE_PIN(P9_11, uart, P9_11(MUX_MODE0, (PIN_INPUT | STRENGTH_MID))) + +/* P9_12 (Ball:H1) QSPI0_CSN0_MUX*/ +BONE_PIN(P9_12, default, P9_12(MUX_MODE3, (PIN_INPUT | STRENGTH_MID))) +BONE_PIN(P9_12, gpio, P9_12(MUX_MODE3, (PIN_INPUT | STRENGTH_MID))) +BONE_PIN(P9_12, gpio_pu, P9_12(MUX_MODE3, (PIN_INPUT_PULLUP | STRENGTH_MID))) +BONE_PIN(P9_12, gpio_pd, P9_12(MUX_MODE3, (PIN_INPUT_PULLDOWN | STRENGTH_MID))) +BONE_PIN(P9_12, pwm, P9_12(MUX_MODE1, (PIN_OUTPUT| STRENGTH_MID))) +BONE_PIN(P9_12, i2c, P9_12(MUX_MODE2, (PIN_INPUT | STRENGTH_MID))) + +/* P9_13 (Ball:M33) UART1_RXD_MUX*/ +BONE_PIN(P9_13, default, P9_13(MUX_MODE3, (PIN_INPUT | STRENGTH_MID))) +BONE_PIN(P9_13, gpio, P9_13(MUX_MODE3, (PIN_INPUT | STRENGTH_MID))) +BONE_PIN(P9_13, gpio_pu, P9_13(MUX_MODE3, (PIN_INPUT_PULLUP | STRENGTH_MID))) +BONE_PIN(P9_13, gpio_pd, P9_13(MUX_MODE3, (PIN_INPUT_PULLDOWN | STRENGTH_MID))) +BONE_PIN(P9_13, uart, P9_13(MUX_MODE0, (PIN_INPUT | STRENGTH_MID))) + +/* P9_14 (Ball:K3) QSPI0_D1_MISO_MUX*/ +BONE_PIN(P9_14, default, P9_14(MUX_MODE3, (PIN_INPUT | STRENGTH_MID))) +BONE_PIN(P9_14, gpio, P9_14(MUX_MODE3, (PIN_INPUT | STRENGTH_MID))) +BONE_PIN(P9_14, gpio_pu, P9_14(MUX_MODE3, (PIN_INPUT_PULLUP | STRENGTH_MID))) +BONE_PIN(P9_14, gpio_pd, P9_14(MUX_MODE3, (PIN_INPUT_PULLDOWN | STRENGTH_MID))) +BONE_PIN(P9_14, pwm, P9_14(MUX_MODE1, (PIN_OUTPUT | STRENGTH_MID))) + +/* P9_15 (Ball:K2) QSPI0_D2_WP_MUX*/ +BONE_PIN(P9_15, default, P9_15(MUX_MODE3, (PIN_INPUT | STRENGTH_MID))) +BONE_PIN(P9_15, gpio, P9_15(MUX_MODE3, (PIN_INPUT | STRENGTH_MID))) +BONE_PIN(P9_15, gpio_pu, P9_15(MUX_MODE3, (PIN_INPUT_PULLUP | STRENGTH_MID))) +BONE_PIN(P9_15, gpio_pd, P9_15(MUX_MODE3, (PIN_INPUT_PULLDOWN | STRENGTH_MID))) +BONE_PIN(P9_15, pwm, P9_15(MUX_MODE1, (PIN_OUTPUT | STRENGTH_MID))) + +/* P9_16 (Ball:J3) QSPI0_D0_MOSI_MUX*/ +BONE_PIN(P9_16, default, P9_16(MUX_MODE3, (PIN_INPUT | STRENGTH_MID))) +BONE_PIN(P9_16, gpio, P9_16(MUX_MODE3, (PIN_INPUT | STRENGTH_MID))) +BONE_PIN(P9_16, gpio_pu, P9_16(MUX_MODE3, (PIN_INPUT_PULLUP | STRENGTH_MID))) +BONE_PIN(P9_16, gpio_pd, P9_16(MUX_MODE3, (PIN_INPUT_PULLDOWN | STRENGTH_MID))) +BONE_PIN(P9_16, pwm, P9_16(MUX_MODE1, (PIN_OUTPUT | STRENGTH_MID))) + +/* P9_17 (Ball:H32) QSPI1_CSN0_MUX*/ +BONE_PIN(P9_17, default, P9_17(MUX_MODE3, (PIN_INPUT | STRENGTH_MID))) +BONE_PIN(P9_17, gpio, P9_17(MUX_MODE3, (PIN_INPUT | STRENGTH_MID))) +BONE_PIN(P9_17, gpio_pu, P9_17(MUX_MODE3, (PIN_INPUT_PULLUP | STRENGTH_MID))) +BONE_PIN(P9_17, gpio_pd, P9_17(MUX_MODE3, (PIN_INPUT_PULLDOWN | STRENGTH_MID))) + +/* P9_18 (Ball:G35) QSPI1_D0_MOSI_MUX*/ +BONE_PIN(P9_18, default, P9_18(MUX_MODE3, (PIN_INPUT | STRENGTH_MID))) +BONE_PIN(P9_18, gpio, P9_18(MUX_MODE3, (PIN_INPUT | STRENGTH_MID))) +BONE_PIN(P9_18, gpio_pu, P9_18(MUX_MODE3, (PIN_INPUT_PULLUP | STRENGTH_MID))) +BONE_PIN(P9_18, gpio_pd, P9_18(MUX_MODE3, (PIN_INPUT_PULLDOWN | STRENGTH_MID))) +BONE_PIN(P9_18, i2c, P9_18(MUX_MODE2, (PIN_INPUT | STRENGTH_MID))) + +/* P9_19 (Ball:G4) I2C2_SCL_MUX*/ +BONE_PIN(P9_19, default, P9_19(MUX_MODE3, (PIN_INPUT | STRENGTH_MID))) +BONE_PIN(P9_19, gpio, P9_19(MUX_MODE3, (PIN_INPUT | STRENGTH_MID))) +BONE_PIN(P9_19, gpio_pu, P9_19(MUX_MODE3, (PIN_INPUT_PULLUP | STRENGTH_MID))) +BONE_PIN(P9_19, gpio_pd, P9_19(MUX_MODE3, (PIN_INPUT_PULLDOWN | STRENGTH_MID))) +BONE_PIN(P9_19, i2c, P9_19(MUX_MODE0, (PIN_OUTPUT | STRENGTH_MID))) +BONE_PIN(P9_19, uart, P9_19(MUX_MODE1, (PIN_OUTPUT | STRENGTH_MID))) + +/* P9_20 (Ball:G3) I2C2_SDA_MUX*/ +BONE_PIN(P9_20, default, P9_20(MUX_MODE3, (PIN_INPUT | STRENGTH_MID))) +BONE_PIN(P9_20, gpio, P9_20(MUX_MODE3, (PIN_INPUT | STRENGTH_MID))) +BONE_PIN(P9_20, gpio_pu, P9_20(MUX_MODE3, (PIN_INPUT_PULLUP | STRENGTH_MID))) +BONE_PIN(P9_20, gpio_pd, P9_20(MUX_MODE3, (PIN_INPUT_PULLDOWN | STRENGTH_MID))) +BONE_PIN(P9_20, i2c, P9_20(MUX_MODE0, (PIN_INPUT | STRENGTH_MID))) +BONE_PIN(P9_20, uart, P9_20(MUX_MODE1, (PIN_INPUT | STRENGTH_MID))) + +/* P9_21 (Ball:G34) QSPI1_D1_MISO_MUX*/ +BONE_PIN(P9_21, default, P9_21(MUX_MODE3, (PIN_INPUT | STRENGTH_MID))) +BONE_PIN(P9_21, gpio, P9_21(MUX_MODE3, (PIN_INPUT | STRENGTH_MID))) +BONE_PIN(P9_21, gpio_pu, P9_21(MUX_MODE3, (PIN_INPUT_PULLUP | STRENGTH_MID))) +BONE_PIN(P9_21, gpio_pd, P9_21(MUX_MODE3, (PIN_INPUT_PULLDOWN | STRENGTH_MID))) + +/* P9_22 (Ball:H34) QSPI1_SCLK_MUX*/ +BONE_PIN(P9_22, default, P9_22(MUX_MODE3, (PIN_INPUT | STRENGTH_MID))) +BONE_PIN(P9_22, gpio, P9_22(MUX_MODE3, (PIN_INPUT | STRENGTH_MID))) +BONE_PIN(P9_22, gpio_pu, P9_22(MUX_MODE3, (PIN_INPUT_PULLUP | STRENGTH_MID))) +BONE_PIN(P9_22, gpio_pd, P9_22(MUX_MODE3, (PIN_INPUT_PULLDOWN | STRENGTH_MID))) + +/* P9_23 (Ball:K1) QSPI0_D3_HOLD_MUX*/ +BONE_PIN(P9_23, default, P9_23(MUX_MODE3, (PIN_INPUT | STRENGTH_MID))) +BONE_PIN(P9_23, gpio, P9_23(MUX_MODE3, (PIN_INPUT | STRENGTH_MID))) +BONE_PIN(P9_23, gpio_pu, P9_23(MUX_MODE3, (PIN_INPUT_PULLUP | STRENGTH_MID))) +BONE_PIN(P9_23, gpio_pd, P9_23(MUX_MODE3, (PIN_INPUT_PULLDOWN | STRENGTH_MID))) + +/* P9_24 (Ball:G33) QSPI1_D2_WP_MUX*/ +BONE_PIN(P9_24, default, P9_24(MUX_MODE3, (PIN_INPUT | STRENGTH_MID))) +BONE_PIN(P9_24, gpio, P9_24(MUX_MODE3, (PIN_INPUT | STRENGTH_MID))) +BONE_PIN(P9_24, gpio_pu, P9_24(MUX_MODE3, (PIN_INPUT_PULLUP | STRENGTH_MID))) +BONE_PIN(P9_24, gpio_pd, P9_24(MUX_MODE3, (PIN_INPUT_PULLDOWN | STRENGTH_MID))) +BONE_PIN(P9_24, uart, P9_24(MUX_MODE2, (PIN_OUTPUT | STRENGTH_MID))) + +/* P9_25 (Ball:F5) GPIO2_18_MUX*/ +BONE_PIN(P9_25, default, P9_25(MUX_MODE0, (PIN_INPUT | STRENGTH_MID))) +BONE_PIN(P9_25, gpio, P9_25(MUX_MODE0, (PIN_INPUT | STRENGTH_MID))) +BONE_PIN(P9_25, gpio_pu, P9_25(MUX_MODE0, (PIN_INPUT_PULLUP | STRENGTH_MID))) +BONE_PIN(P9_25, gpio_pd, P9_25(MUX_MODE0, (PIN_INPUT_PULLDOWN | STRENGTH_MID))) + +/* P9_26 (Ball:F37) QSPI1_D3_HOLD_MUX*/ +BONE_PIN(P9_26, default, P9_26(MUX_MODE3, (PIN_INPUT | STRENGTH_MID))) +BONE_PIN(P9_26, gpio, P9_26(MUX_MODE3, (PIN_INPUT | STRENGTH_MID))) +BONE_PIN(P9_26, gpio_pu, P9_26(MUX_MODE3, (PIN_INPUT_PULLUP | STRENGTH_MID))) +BONE_PIN(P9_26, gpio_pd, P9_26(MUX_MODE3, (PIN_INPUT_PULLDOWN | STRENGTH_MID))) +BONE_PIN(P9_26, uart, P9_26(MUX_MODE2, (PIN_INPUT | STRENGTH_MID))) + +/* P9_27 (Ball:E4) GPIO2_19_MUX*/ +BONE_PIN(P9_27, default, P9_27(MUX_MODE0, (PIN_INPUT | STRENGTH_MID))) +BONE_PIN(P9_27, gpio, P9_27(MUX_MODE0, (PIN_INPUT | STRENGTH_MID))) +BONE_PIN(P9_27, gpio_pu, P9_27(MUX_MODE0, (PIN_INPUT_PULLUP | STRENGTH_MID))) +BONE_PIN(P9_27, gpio_pd, P9_27(MUX_MODE0, (PIN_INPUT_PULLDOWN | STRENGTH_MID))) + +/* P9_28 (Ball:E3) SPI_CSN_MUX*/ +BONE_PIN(P9_28, default, P9_28(MUX_MODE3, (PIN_INPUT | STRENGTH_MID))) +BONE_PIN(P9_28, gpio, P9_28(MUX_MODE3, (PIN_INPUT | STRENGTH_MID))) +BONE_PIN(P9_28, gpio_pu, P9_28(MUX_MODE3, (PIN_INPUT_PULLUP | STRENGTH_MID))) +BONE_PIN(P9_28, gpio_pd, P9_28(MUX_MODE3, (PIN_INPUT_PULLDOWN | STRENGTH_MID))) +BONE_PIN(P9_28, uart, P9_28(MUX_MODE1, (PIN_INPUT | STRENGTH_MID))) + +/* P9_29 (Ball:F1) SPI_MISO_MUX*/ +BONE_PIN(P9_29, default, P9_29(MUX_MODE3, (PIN_INPUT | STRENGTH_MID))) +BONE_PIN(P9_29, gpio, P9_29(MUX_MODE3, (PIN_INPUT | STRENGTH_MID))) +BONE_PIN(P9_29, gpio_pu, P9_29(MUX_MODE3, (PIN_INPUT_PULLUP | STRENGTH_MID))) +BONE_PIN(P9_29, gpio_pd, P9_29(MUX_MODE3, (PIN_INPUT_PULLDOWN | STRENGTH_MID))) +BONE_PIN(P9_29, spi, P9_29(MUX_MODE0, (PIN_INPUT | STRENGTH_MID))) + +/* P9_30 (Ball:F2) SPI_MOSI_MUX*/ +BONE_PIN(P9_30, default, P9_30(MUX_MODE3, (PIN_INPUT | STRENGTH_MID))) +BONE_PIN(P9_30, gpio, P9_30(MUX_MODE3, (PIN_INPUT | STRENGTH_MID))) +BONE_PIN(P9_30, gpio_pu, P9_30(MUX_MODE3, (PIN_INPUT_PULLUP | STRENGTH_MID))) +BONE_PIN(P9_30, gpio_pd, P9_30(MUX_MODE3, (PIN_INPUT_PULLDOWN | STRENGTH_MID))) +BONE_PIN(P9_30, spi, P9_30(MUX_MODE0, (PIN_OUTPUT | STRENGTH_MID))) + +/* P9_31 (Ball:D3) SPI_SCLK_MUX*/ +BONE_PIN(P9_31, default, P9_31(MUX_MODE3, (PIN_INPUT | STRENGTH_MID))) +BONE_PIN(P9_31, gpio, P9_31(MUX_MODE3, (PIN_INPUT | STRENGTH_MID))) +BONE_PIN(P9_31, gpio_pu, P9_31(MUX_MODE3, (PIN_INPUT_PULLUP | STRENGTH_MID))) +BONE_PIN(P9_31, gpio_pd, P9_31(MUX_MODE3, (PIN_INPUT_PULLDOWN | STRENGTH_MID))) +BONE_PIN(P9_31, spi, P9_31(MUX_MODE0, (PIN_INPUT_PULLDOWN | STRENGTH_MID))) +BONE_PIN(P9_31, uart, P9_31(MUX_MODE1, (PIN_INPUT_PULLDOWN | STRENGTH_MID))) + +/* P9_32 - GND */ +/* P9_33 - ADC_VIN_CH4 */ +/* P9_34 - GND */ +/* P9_35 - ADC_VIN_CH6 */ +/* P9_36 - ADC_VIN_CH5 */ +/* P9_37 - ADC_VIN_CH2 */ +/* P9_38 - ADC_VIN_CH3 */ +/* P9_39 - ADC_VIN_CH0 */ +/* P9_39 - ADC_VIN_CH1 */ + +/* P9_41 (Ball:D2) GPIO2_13_MUX*/ +BONE_PIN(P9_41, default, P9_41(MUX_MODE0, (PIN_INPUT | STRENGTH_MID))) +BONE_PIN(P9_41, gpio, P9_41(MUX_MODE0, (PIN_INPUT | STRENGTH_MID))) +BONE_PIN(P9_41, gpio_pu, P9_41(MUX_MODE0, (PIN_INPUT_PULLUP | STRENGTH_MID))) +BONE_PIN(P9_41, gpio_pd, P9_41(MUX_MODE0, (PIN_INPUT_PULLDOWN | STRENGTH_MID))) + +/* P9_42 (Ball:H3) QSPI0_SCLK_MUX*/ +BONE_PIN(P9_42, default, P9_42(MUX_MODE3, (PIN_INPUT | STRENGTH_MID))) +BONE_PIN(P9_42, gpio, P9_42(MUX_MODE3, (PIN_INPUT | STRENGTH_MID))) +BONE_PIN(P9_42, gpio_pu, P9_42(MUX_MODE3, (PIN_INPUT_PULLUP | STRENGTH_MID))) +BONE_PIN(P9_42, gpio_pd, P9_42(MUX_MODE3, (PIN_INPUT_PULLDOWN | STRENGTH_MID))) +BONE_PIN(P9_42, pwm, P9_42(MUX_MODE1, (PIN_INPUT_PULLDOWN | STRENGTH_MID))) + +/* P9_43 - GND */ +/* P9_44 - GND */ +/* P9_45 - GND */ +/* P9_46 - GND */ + +/* mikroBus port*/ + +/*PWM*/ +BONE_PIN(mb_pwm, gpio, mb_pwm(MUX_MODE3, (PIN_INPUT | STRENGTH_MID))) +BONE_PIN(mb_pwm, pwm, mb_pwm(MUX_MODE1, (PIN_OUTPUT | STRENGTH_MID))) + +/*GPIO*/ +BONE_PIN(mb_rst, gpio, mb_rst(MUX_MODE3, (PIN_INPUT | STRENGTH_MID))) +BONE_PIN(mb_int, gpio, mb_int(MUX_MODE0, (PIN_INPUT | STRENGTH_MID))) + +/*UART*/ +BONE_PIN(mb_rxd, gpio, mb_rxd(MUX_MODE3, (PIN_INPUT | STRENGTH_MID))) +BONE_PIN(mb_txd, gpio, mb_txd(MUX_MODE3, (PIN_INPUT | STRENGTH_MID))) + +BONE_PIN(mb_rxd, uart, mb_rxd(MUX_MODE1, (PIN_INPUT | STRENGTH_MID))) +BONE_PIN(mb_txd, uart, mb_txd(MUX_MODE1, (PIN_INPUT | STRENGTH_MID))) + +/*SPI*/ +BONE_PIN(mb_cs, gpio, mb_cs(MUX_MODE3, (PIN_INPUT | STRENGTH_MID))) +BONE_PIN(mb_sck, gpio, mb_sck(MUX_MODE3, (PIN_INPUT | STRENGTH_MID))) +BONE_PIN(mb_mosi, gpio, mb_mosi(MUX_MODE3, (PIN_INPUT | STRENGTH_MID))) +BONE_PIN(mb_miso, gpio, mb_miso(MUX_MODE3, (PIN_INPUT | STRENGTH_MID))) + +BONE_PIN(mb_cs, spi, mb_cs(MUX_MODE3, (PIN_OUTPUT | STRENGTH_MID))) +BONE_PIN(mb_sck, spi, mb_sck(MUX_MODE0, (PIN_INPUT | STRENGTH_MID))) +BONE_PIN(mb_mosi, spi, mb_mosi(MUX_MODE0, (PIN_INPUT | STRENGTH_MID))) +BONE_PIN(mb_miso, spi, mb_miso(MUX_MODE0, (PIN_INPUT | STRENGTH_MID))) + +/*I2C*/ +BONE_PIN(mb_scl, gpio, mb_scl(MUX_MODE0, (PIN_INPUT | STRENGTH_MID))) +BONE_PIN(mb_sda, gpio, mb_sda(MUX_MODE0, (PIN_INPUT | STRENGTH_MID))) + +BONE_PIN(mb_scl, i2c, mb_scl(MUX_MODE1, (PIN_INPUT | STRENGTH_MID))) +BONE_PIN(mb_sda, i2c, mb_sda(MUX_MODE1, (PIN_INPUT | STRENGTH_MID))) + +&{/} { + aliases { + mikrobus0 = &bone_mikrobus0; + }; + + bone_mikrobus0: linux-mikrobus { + compatible = "linux,mikrobus"; + status = "disabled"; + pinctrl-names = "default", "pwm_default", "pwm_gpio", + "uart_default", "uart_gpio", "i2c_default", + "i2c_gpio", "spi_default", "spi_gpio"; + pinctrl-0 = < + &mb_rst_gpio_pin + &mb_int_gpio_pin + >; + pinctrl-1 = <&mb_pwm_pwm_pin>; + pinctrl-2 = <&mb_pwm_gpio_pin>; + pinctrl-3 = < + &mb_txd_uart_pin + &mb_rxd_uart_pin + >; + pinctrl-4 = < + &mb_txd_gpio_pin + &mb_rxd_gpio_pin + >; + pinctrl-5 = < + &mb_scl_i2c_pin + &mb_sda_i2c_pin + >; + pinctrl-6 = < + &mb_scl_gpio_pin + &mb_sda_gpio_pin + >; + pinctrl-7 = < + &mb_cs_spi_pin + &mb_sck_spi_pin + &mb_mosi_spi_pin + &mb_miso_spi_pin + >; + pinctrl-8 = < + &mb_cs_gpio_pin + &mb_sck_gpio_pin + &mb_mosi_gpio_pin + &mb_miso_gpio_pin + >; + + i2c-adaptor = <&i2c4>; + spi-master = <0>; + spi-cs = <0 1>; + uart = <&uart3>; + pwms = <&pwm 2 5000000>; + mikrobus-gpios = , /*mb_pwm*/ + , /*mb_rst*/ + , /*mb_int*/ + , /*mb_rxd*/ + , /*mb_txd*/ + , /*mb_cs*/ + , /*mb_sck*/ + , /*mb_mosi*/ + , /*mb_miso*/ + , /*mb_scl*/ + ; /*mb_sda*/ + }; +}; diff --git a/arch/riscv/boot/dts/thead/light-beagle-ref.dts b/arch/riscv/boot/dts/thead/light-beagle-ref.dts index a99f46190..0b2387c18 100644 --- a/arch/riscv/boot/dts/thead/light-beagle-ref.dts +++ b/arch/riscv/boot/dts/thead/light-beagle-ref.dts @@ -1,6 +1,8 @@ /* SPDX-License-Identifier: GPL-2.0 */ /* * Copyright (C) 2021 Alibaba Group Holding Limited. + * Copyright (C) 2022 BeagleBoard.org - https://beagleboard.org/ + * Copyright (C) 2022 Deepak Khatri */ /dts-v1/; @@ -25,11 +27,54 @@ leds { compatible = "gpio-leds"; - status = "disabled"; - led0 { - label = "SYS_STATUS"; - gpios = <&gpio1_porta 15 0>; /* GPIO_ACTIVE_HIGH: 0 */ - default-state = "off"; + pinctrl-names = "default"; + pinctrl-0 = <&led_pins_default &pinctrl_bt>; + + led-0 { + label = "beaglebone:green:usr0"; + gpios = <&ao_gpio4_porta 8 GPIO_ACTIVE_HIGH>; + linux,default-trigger = "heartbeat"; + //function = LED_FUNCTION_HEARTBEAT; + }; + + led-1 { + label = "beaglebone:green:usr1"; + gpios = <&ao_gpio4_porta 9 GPIO_ACTIVE_HIGH>; + linux,default-trigger = "mmc0"; + //function = LED_FUNCTION_DISK_ACTIVITY; + }; + + led-2 { + label = "beaglebone:green:usr2"; + gpios = <&ao_gpio4_porta 10 GPIO_ACTIVE_HIGH>; + linux,default-trigger = "cpu"; + //function = LED_FUNCTION_CPU; + }; + + led-3 { + label = "beaglebone:green:usr3"; + gpios = <&ao_gpio4_porta 11 GPIO_ACTIVE_HIGH>; + linux,default-trigger = "mmc1"; + //function = LED_FUNCTION_DISK_ACTIVITY; + }; + + led-4 { + label = "beaglebone:green:usr4"; + gpios = <&ao_gpio4_porta 12 GPIO_ACTIVE_HIGH>; + linux,default-trigger = "netdev"; + //function = LED_FUNCTION_WLAN; + }; + + led-5 { + label = "shutdown-gpios"; + gpios = <&gpio2_porta 28 GPIO_ACTIVE_HIGH>; + default-state = "on"; + }; + + led-6 { + label = "device-wakeup-gpios"; + gpios = <&gpio2_porta 29 GPIO_ACTIVE_HIGH>; + default-state = "on"; }; }; @@ -205,60 +250,9 @@ regulator-name = "vref-1v8"; regulator-min-microvolt = <1800000>; regulator-max-microvolt = <1800000>; - status = "okay"; - }; - - reg_tp_pwr_en: regulator-pwr-en { - compatible = "regulator-fixed"; - regulator-name = "PWR_EN"; - regulator-min-microvolt = <2800000>; - regulator-max-microvolt = <2800000>; - gpio = <&gpio1_porta 12 1>; - enable-active-high; - regulator-always-on; - }; - -/* - wcn_wifi: wireless-wlan { - compatible = "wlan-platdata"; - clock-names = "clk_wifi"; - ref-clock-frequency = <24000000>; - keep_wifi_power_on; - pinctrl-names = "default"; - wifi_chip_type = "rtl8723ds"; - WIFI,poweren_gpio = <&gpio2_porta 29 0>; - WIFI,reset_n = <&gpio2_porta 22 0>; status = "okay"; }; - wcn_bt: wireless-bluetooth { - compatible = "bluetooth-platdata"; - pinctrl-names = "default", "rts_gpio"; - BT,power_gpio = <&gpio2_porta 29 0>; - status = "okay"; - }; -*/ - - gpio-keys { - compatible = "gpio-keys"; - pinctrl-0 = <&pinctrl_volume>; - pinctrl-names = "default"; - key-volumedown { - label = "Volume Down Key"; - linux,code = ; - debounce-interval = <1>; - gpios = <&gpio1_porta 19 0x1>; - }; -/* - key-volumeup { - label = "Volume Up Key"; - linux,code = ; - debounce-interval = <1>; - gpios = <&gpio2_porta 25 0x1>; - }; -*/ - }; - aon: aon { compatible = "thead,light-aon"; mbox-names = "aon"; @@ -290,44 +284,6 @@ regulator-always-on; }; - soc_vdd_3v3_en_reg: soc_vdd_3v3_en { - compatible = "regulator-fixed"; - regulator-name = "soc_vdd_3v3_en"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - gpio = <&gpio0_porta 30 1>; - enable-active-high; - regulator-always-on; - }; - - soc_lcd0_bias_en_reg: soc_lcd0_bias_en { - compatible = "regulator-fixed"; - regulator-name = "soc_lcd0_bias_en"; - regulator-min-microvolt = <5700000>; - regulator-max-microvolt = <5700000>; - gpio = <&gpio1_porta 10 1>; - enable-active-high; - }; - - soc_vdd18_lcd0_en_reg: soc_lcd0_en { - compatible = "regulator-fixed"; - regulator-name = "soc_lcd0_en"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - gpio = <&gpio1_porta 9 1>; - enable-active-high; - }; - - soc_vdd5v_se_en_reg: soc_vdd5v_se_en { - compatible = "regulator-fixed"; - regulator-name = "soc_vdd5v_se_en"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - gpio = <&gpio2_porta 14 1>; - enable-active-high; - regulator-always-on; - }; - soc_wcn33_en_reg: soc_wcn33_en { compatible = "regulator-fixed"; regulator-name = "soc_wcn33_en"; @@ -348,61 +304,6 @@ regulator-always-on; }; - - soc_avdd28_rgb_reg: soc_avdd28_rgb { - compatible = "regulator-fixed"; - regulator-name = "soc_avdd28_rgb"; - regulator-min-microvolt = <2800000>; - regulator-max-microvolt = <2800000>; - gpio = <&gpio1_porta 15 1>; - enable-active-high; - }; - - soc_dovdd18_rgb_reg: soc_dovdd18_rgb { - compatible = "regulator-fixed"; - regulator-name = "soc_dovdd18_rgb"; - regulator-min-microvolt = <2800000>; - regulator-max-microvolt = <2800000>; - gpio = <&gpio1_porta 13 1>; - enable-active-high; - }; - - soc_dvdd12_rgb_reg: soc_dvdd12_rgb { - compatible = "regulator-fixed"; - regulator-name = "soc_dvdd12_rgb"; - regulator-min-microvolt = <2800000>; - regulator-max-microvolt = <2800000>; - gpio = <&gpio1_porta 14 1>; - enable-active-high; - }; - - soc_avdd25_ir_reg: soc_avdd25_ir { - compatible = "regulator-fixed"; - regulator-name = "soc_avdd25_ir"; - regulator-min-microvolt = <2500000>; - regulator-max-microvolt = <2500000>; - gpio = <&gpio0_porta 28 1>; - enable-active-high; - }; - - soc_dovdd18_ir_reg: soc_dovdd18_ir { - compatible = "regulator-fixed"; - regulator-name = "soc_dovdd18_ir"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - gpio = <&gpio1_porta 13 1>; - enable-active-high; - }; - - soc_dvdd12_ir_reg: soc_dvdd12_ir { - compatible = "regulator-fixed"; - regulator-name = "soc_dvdd12_ir"; - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <1200000>; - gpio = <&gpio0_porta 29 1>; - enable-active-high; - }; - aon_reg_dialog: light-dialog-reg { compatible = "thead,light-dialog-pmic-ant"; status = "okay"; @@ -624,10 +525,11 @@ w25q,fast-read; }; - spidev@1 { - compatible = "spidev"; + channel@1 { + compatible = "rohm,dh2228fv"; + //symlink = "bone/spi/0.1"; #address-cells = <0x1>; - #size-cells = <0x1>; + #size-cells = <0x0>; reg = <0x1>; spi-max-frequency = <50000000>; }; @@ -637,6 +539,25 @@ clock-frequency = <100000000>; }; +&uart4 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart4>; + symlink = "bone/uart/bluetooth"; + uart-has-rtscts; + status = "okay"; + + //bluetooth { + // // WIP: AP6203BM: BCM43013 + // compatible = "brcm,bcm4330-bt"; + // pinctrl-names = "default"; + // pinctrl-0 = <&pinctrl_bt>; + // max-speed = <3000000>; + // shutdown-gpios = <&gpio2_porta 28 GPIO_ACTIVE_HIGH>; + // device-wakeup-gpios = <&gpio2_porta 29 GPIO_ACTIVE_HIGH>; + // host-wakeup-gpios = <&gpio2_porta 30 GPIO_ACTIVE_HIGH>; + //}; +}; + &qspi0 { num-cs = <1>; cs-gpios = <&gpio2_porta 3 0>; @@ -663,10 +584,11 @@ compatible = "snps,dw-apb-ssi"; num-cs = <1>; cs-gpios = <&gpio0_porta 1 0>; - status = "okay"; + status = "disabled"; - spidev@0 { - compatible = "spidev"; + channel@0 { + compatible = "rohm,dh2228fv"; + //symlink = "bone/spi/1.1"; #address-cells = <0x1>; #size-cells = <0x1>; reg = <0x0>; @@ -744,7 +666,7 @@ }; &padctrl0_apsys { /* right-pinctrl */ - light-evb-padctrl0 { + light_padctrl0: light-evb-padctrl0 { /* * Pin Configuration Node: * Format: @@ -793,12 +715,20 @@ thead,pins = < FM_GPIO3_2 0x1 0x208 /* pwm0 */ >; - }; }; + + pinctrl_bt: btgrp { + thead,pins = < + FM_SDIO1_WPRTN 0x3 0x72 + FM_SDIO1_DETN 0x3 0x72 + FM_GPIO2_30 0x0 0x72 + >; + }; + }; }; &padctrl1_apsys { /* left-pinctrl */ - light-evb-padctrl1 { + light_padctrl1: light-evb-padctrl1 { /* * Pin Configuration Node: * Format: @@ -837,18 +767,24 @@ FM_QSPI1_D2_WP 0x1 0x238 FM_QSPI1_D3_HOLD 0x1 0x238 >; - }; - - pinctrl_volume: volume_grp { - thead,pins = < - FM_CLK_OUT_2 0x3 0x208 - >; - }; }; + }; }; +/* + PIN , 0x0, 0x1, 0x2, 0x3, 0x4, 0x5 + AUDIO_PA8, AUDIO_PA8, NULL, NULL, GPIO4_8, NULL, NULL + AUDIO_PA9, AUDIO_PA9, NULL, NULL, GPIO4_9, NULL, NULL + AUDIO_PA10, AUDIO_PA10, NULL, NULL, GPIO4_10, NULL, NULL + AUDIO_PA11, AUDIO_PA11, NULL, NULL, GPIO4_11, NULL, NULL + AUDIO_PA12, AUDIO_PA12, NULL, NULL, GPIO4_12, NULL, NULL +*/ + +#define FM_AUDIO_PA8_AUDIO_PA8 0x00 +#define FM_AUDIO_PA8_GPIO 0x03 + &padctrl_aosys { - light-aon-padctrl { + light_padctrl: light-aon-padctrl { /* * Pin Configuration Node: * Format: @@ -866,12 +802,26 @@ >; }; + led_pins_default: leds0_grp { + thead,pins = < + FM_AUDIO_PA8 0x3 0x72 + FM_AUDIO_PA9 0x3 0x72 + FM_AUDIO_PA10 0x3 0x72 + FM_AUDIO_PA11 0x3 0x72 + FM_AUDIO_PA12 0x3 0x72 + >; + }; }; }; &i2c0 { clock-frequency = <400000>; status = "okay"; + + eeprom@50 { + compatible = "atmel,24c32"; + reg = <0x50>; + }; }; &i2c1 { @@ -968,40 +918,6 @@ status = "okay"; }; -&vvcam_sensor0 { - sensor_name = "SC2310"; - sensor_regulators = "DOVDD18_RGB", "DVDD12_RGB", "AVDD28_RGB"; - sensor_regulator_timing_us = <70 50 20>; - sensor_pdn = <&gpio1_porta 21 0>; //powerdown pin / shutdown pin - sensor_rst = <&gpio1_porta 16 0>; - sensor_pdn_delay_us = <4000>; //powerdown pin / shutdown pin actived till I2C ready - DOVDD18_RGB-supply = <&soc_dovdd18_rgb_reg>; - DVDD12_RGB-supply = <&soc_dvdd12_rgb_reg>; - AVDD28_RGB-supply = <&soc_avdd28_rgb_reg>; - i2c_reg_width = /bits/ 8 <2>; - i2c_data_width = /bits/ 8 <1>; - i2c_addr = /bits/ 8 <0x30>; - i2c_bus = /bits/ 8 <3>; - status = "okay"; -}; - -&vvcam_sensor1 { - sensor_name = "SC132GS"; - sensor_regulators = "DOVDD18_IR", "DVDD12_IR", "AVDD25_IR"; - sensor_regulator_timing_us = <70 1000 2000>; - i2c_addr = /bits/ 8 <0x31>; - sensor_pdn = <&gpio1_porta 28 0>; //powerdown pin / shutdown pin - sensor_rst = <&gpio1_porta 24 0>; - sensor_pdn_delay_us = <2000>; //powerdown pin / shutdown pin actived till I2C ready - DOVDD18_IR-supply = <&soc_dovdd18_ir_reg>; - DVDD12_IR-supply = <&soc_dvdd12_ir_reg>; - AVDD25_IR-supply = <&soc_avdd25_ir_reg>; - i2c_reg_width = /bits/ 8 <2>; - i2c_data_width = /bits/ 8 <1>; - i2c_bus = /bits/ 8 <2>; - status = "okay"; -}; - &vvcam_sensor2 { sensor_name = "GC5035"; sensor_regulators = "DOVDD18_SCAN", "DVDD12_SCAN", "AVDD28_SCAN"; @@ -2303,7 +2219,7 @@ }; &light_i2s { - status = "okay"; + status = "disabled"; }; &i2s0 { @@ -2325,12 +2241,14 @@ 300000 650000 800000 700000 1500000 800000 + 1848000 1000000 >; light,dvddm-operating-points = < /* kHz uV */ 300000 800000 800000 800000 1500000 800000 + 1848000 1000000 >; }; c910_1: cpu@1 { @@ -2339,12 +2257,14 @@ 300000 650000 800000 700000 1500000 800000 + 1848000 1000000 >; light,dvddm-operating-points = < /* kHz uV */ 300000 800000 800000 800000 1500000 800000 + 1848000 1000000 >; }; c910_2: cpu@2 { @@ -2354,12 +2274,14 @@ 300000 650000 800000 700000 1500000 800000 + 1848000 1000000 >; light,dvddm-operating-points = < /* kHz uV */ 300000 800000 800000 800000 1500000 800000 + 1848000 1000000 >; }; c910_3: cpu@3 { @@ -2369,12 +2291,14 @@ 300000 650000 800000 700000 1500000 800000 + 1848000 1000000 >; light,dvddm-operating-points = < /* kHz uV */ 300000 800000 800000 800000 1500000 800000 + 1848000 1000000 >; }; }; diff --git a/arch/riscv/boot/dts/thead/light-beagle.dts b/arch/riscv/boot/dts/thead/light-beagle.dts index 2258e8bac..cf4859e6e 100644 --- a/arch/riscv/boot/dts/thead/light-beagle.dts +++ b/arch/riscv/boot/dts/thead/light-beagle.dts @@ -8,7 +8,6 @@ #include "light-beagle-ref.dts" / { - bcmdhd_wlan { compatible = "android,bcmdhd_wlan"; @@ -713,3 +712,5 @@ video12: tuningtool }; }; }; + +#include "light-beagle-bone-buses.dtsi" \ No newline at end of file diff --git a/arch/riscv/boot/dts/thead/light.dtsi b/arch/riscv/boot/dts/thead/light.dtsi index af281ef35..818c7014c 100644 --- a/arch/riscv/boot/dts/thead/light.dtsi +++ b/arch/riscv/boot/dts/thead/light.dtsi @@ -8,6 +8,7 @@ #include #include #include +#include #include #include #include @@ -810,6 +811,7 @@ }; pwm: pwm@ffec01c000 { + status = "disabled"; compatible = "thead,pwm-light"; reg = <0xff 0xec01c000 0x0 0x4000>; #pwm-cells = <2>; @@ -1023,6 +1025,7 @@ }; qspi0: spi@ffea000000 { + status = "disabled"; compatible = "snps,dw-apb-ssi-quad"; reg = <0xff 0xea000000 0x0 0x1000>; pinctrl-names = "default"; @@ -1035,6 +1038,7 @@ }; qspi1: spi@fff8000000 { + status = "disabled"; compatible = "snps,dw-apb-ssi-quad"; reg = <0xff 0xf8000000 0x0 0x1000>; pinctrl-names = "default"; diff --git a/include/dt-bindings/board/light-fm-bone-pins.h b/include/dt-bindings/board/light-fm-bone-pins.h new file mode 100644 index 000000000..1919f572b --- /dev/null +++ b/include/dt-bindings/board/light-fm-bone-pins.h @@ -0,0 +1,293 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (C) 2020 - 2023 BeagleBoard.org - https://beagleboard.org/ + * Copyright (C) 2020 - 2023 Deepak Khatri + * Copyright (C) 2021 Jason Kridner + * See Cape Interface Spec page for more info on Bone Buses + * https://docs.beagleboard.org/0.0/boards/capes/cape-interface-spec.html + */ + +#ifndef _DT_BINDINGS_BOARD_TH1520_BONE_PINS_H +#define _DT_BINDINGS_BOARD_TH1520_BONE_PINS_H + +#define bb_device 1 +#define board_soc TH1520 + +/* +* GPIO port macros +* +* gpio0: &gpio0_porta +* gpio1: &gpio1_porta +* gpio2: &gpio2_porta +* gpio3: &gpio3_porta +* ao_gpio4: &ao_gpio4_porta +* ao_gpio: &ao_gpio_porta +* +*/ + +// P8 cape header +#define gpio_P8_03 &gpio1_porta 21 +#define gpio_P8_04 &gpio1_porta 22 +#define gpio_P8_05 &gpio1_porta 23 +#define gpio_P8_06 &gpio1_porta 24 +#define gpio_P8_07 &gpio1_porta 25 +#define gpio_P8_08 &gpio1_porta 26 +#define gpio_P8_09 &gpio1_porta 27 +#define gpio_P8_10 &gpio1_porta 28 +#define gpio_P8_11 &gpio1_porta 29 +#define gpio_P8_12 &gpio1_porta 30 +#define gpio_P8_13 &gpio3_porta 2 +#define gpio_P8_14 &gpio1_porta 20 +#define gpio_P8_15 &gpio3_porta 0 +#define gpio_P8_16 &gpio0_porta 20 +#define gpio_P8_17 &gpio3_porta 1 +#define gpio_P8_18 &gpio1_porta 5 +#define gpio_P8_19 &gpio3_porta 3 +#define gpio_P8_20 &gpio1_porta 6 +#define gpio_P8_21 &gpio1_porta 7 +#define gpio_P8_22 &gpio1_porta 8 +#define gpio_P8_23 &gpio1_porta 9 +#define gpio_P8_24 &gpio1_porta 10 +#define gpio_P8_25 &gpio1_porta 11 +#define gpio_P8_26 &gpio1_porta 12 +#define gpio_P8_27 &gpio1_porta 15 +#define gpio_P8_28 &gpio1_porta 16 +#define gpio_P8_29 &gpio1_porta 14 +#define gpio_P8_30 &gpio1_porta 13 +#define gpio_P8_31 &gpio1_porta 3 +#define gpio_P8_32 &gpio1_porta 4 +#define gpio_P8_33 &gpio1_porta 2 +#define gpio_P8_34 &gpio1_porta 0 +#define gpio_P8_35 &gpio1_porta 1 +#define gpio_P8_36 &gpio0_porta 31 +#define gpio_P8_37 &gpio0_porta 29 +#define gpio_P8_38 &gpio0_porta 30 +#define gpio_P8_39 &gpio0_porta 27 +#define gpio_P8_40 &gpio0_porta 28 +#define gpio_P8_41 &gpio0_porta 25 +#define gpio_P8_42 &gpio0_porta 26 +#define gpio_P8_43 &gpio0_porta 23 +#define gpio_P8_44 &gpio0_porta 24 +#define gpio_P8_45 &gpio0_porta 21 +#define gpio_P8_46 &gpio0_porta 22 + +// P9 cape header +#define gpio_P9_11 &gpio0_porta 10 +#define gpio_P9_12 &gpio2_porta 3 +#define gpio_P9_13 &gpio0_porta 11 +#define gpio_P9_14 &gpio2_porta 6 +#define gpio_P9_15 &gpio2_porta 7 +#define gpio_P9_16 &gpio2_porta 5 +#define gpio_P9_17 &gpio0_porta 1 +#define gpio_P9_18 &gpio0_porta 2 +#define gpio_P9_19 &gpio2_porta 9 +#define gpio_P9_20 &gpio2_porta 10 +#define gpio_P9_21 &gpio0_porta 3 +#define gpio_P9_22 &gpio0_porta 0 +#define gpio_P9_23 &gpio2_porta 8 +#define gpio_P9_24 &gpio0_porta 4 +#define gpio_P9_25 &gpio2_porta 18 +#define gpio_P9_26 &gpio0_porta 5 +#define gpio_P9_27 &gpio2_porta 19 +#define gpio_P9_28 &gpio2_porta 15 +#define gpio_P9_29 &gpio2_porta 17 +#define gpio_P9_30 &gpio2_porta 16 +#define gpio_P9_31 &gpio2_porta 14 +#define gpio_P9_41 &gpio2_porta 13 +#define gpio_P9_42 &gpio2_porta 2 + +// mikroBus port +#define gpio_mb_pwm &gpio2_porta 4 +#define gpio_mb_rst &ao_gpio4_porta 3 +#define gpio_mb_int &gpio2_porta 21 +#define gpio_mb_rxd &gpio0_porta 17 +#define gpio_mb_txd &gpio0_porta 16 +#define gpio_mb_cs &gpio2_porta 20 +#define gpio_mb_sck &gpio2_porta 14 +#define gpio_mb_miso &gpio2_porta 17 +#define gpio_mb_mosi &gpio2_porta 16 +#define gpio_mb_scl &gpio0_porta 18 +#define gpio_mb_sda &gpio0_porta 19 + +/* +* padctrl macros +* +* left-pinctrl (gpio0,gpio1): &light_padctrl1 +* right-pinctrl (gpio2,gpio3): &light_padctrl0 +* aon-pinctrl (ao_gpio4,ao_gpio): &light_padctrl +* +*/ + +// P8 cape header +#define padctrl_P8_03 &light_padctrl1 +#define padctrl_P8_04 &light_padctrl1 +#define padctrl_P8_05 &light_padctrl1 +#define padctrl_P8_06 &light_padctrl1 +#define padctrl_P8_07 &light_padctrl1 +#define padctrl_P8_08 &light_padctrl1 +#define padctrl_P8_09 &light_padctrl1 +#define padctrl_P8_10 &light_padctrl1 +#define padctrl_P8_11 &light_padctrl1 +#define padctrl_P8_12 &light_padctrl1 +#define padctrl_P8_13 &light_padctrl0 +#define padctrl_P8_14 &light_padctrl1 +#define padctrl_P8_15 &light_padctrl0 +#define padctrl_P8_16 &light_padctrl1 +#define padctrl_P8_17 &light_padctrl0 +#define padctrl_P8_18 &light_padctrl1 +#define padctrl_P8_19 &light_padctrl0 +#define padctrl_P8_20 &light_padctrl1 +#define padctrl_P8_21 &light_padctrl1 +#define padctrl_P8_22 &light_padctrl1 +#define padctrl_P8_23 &light_padctrl1 +#define padctrl_P8_24 &light_padctrl1 +#define padctrl_P8_25 &light_padctrl1 +#define padctrl_P8_26 &light_padctrl1 +#define padctrl_P8_27 &light_padctrl1 +#define padctrl_P8_28 &light_padctrl1 +#define padctrl_P8_29 &light_padctrl1 +#define padctrl_P8_30 &light_padctrl1 +#define padctrl_P8_31 &light_padctrl1 +#define padctrl_P8_32 &light_padctrl1 +#define padctrl_P8_33 &light_padctrl1 +#define padctrl_P8_34 &light_padctrl1 +#define padctrl_P8_35 &light_padctrl1 +#define padctrl_P8_36 &light_padctrl1 +#define padctrl_P8_37 &light_padctrl1 +#define padctrl_P8_38 &light_padctrl1 +#define padctrl_P8_39 &light_padctrl1 +#define padctrl_P8_40 &light_padctrl1 +#define padctrl_P8_41 &light_padctrl1 +#define padctrl_P8_42 &light_padctrl1 +#define padctrl_P8_43 &light_padctrl1 +#define padctrl_P8_44 &light_padctrl1 +#define padctrl_P8_45 &light_padctrl1 +#define padctrl_P8_46 &light_padctrl1 + +// P9 cape header +#define padctrl_P9_11 &light_padctrl1 +#define padctrl_P9_12 &light_padctrl0 +#define padctrl_P9_13 &light_padctrl1 +#define padctrl_P9_14 &light_padctrl0 +#define padctrl_P9_15 &light_padctrl0 +#define padctrl_P9_16 &light_padctrl0 +#define padctrl_P9_17 &light_padctrl1 +#define padctrl_P9_18 &light_padctrl1 +#define padctrl_P9_19 &light_padctrl0 +#define padctrl_P9_20 &light_padctrl0 +#define padctrl_P9_21 &light_padctrl1 +#define padctrl_P9_22 &light_padctrl1 +#define padctrl_P9_23 &light_padctrl0 +#define padctrl_P9_24 &light_padctrl1 +#define padctrl_P9_25 &light_padctrl0 +#define padctrl_P9_26 &light_padctrl1 +#define padctrl_P9_27 &light_padctrl0 +#define padctrl_P9_28 &light_padctrl0 +#define padctrl_P9_29 &light_padctrl0 +#define padctrl_P9_30 &light_padctrl0 +#define padctrl_P9_31 &light_padctrl0 +#define padctrl_P9_41 &light_padctrl0 +#define padctrl_P9_42 &light_padctrl0 + +// mikroBus port +#define padctrl_mb_pwm &light_padctrl0 +#define padctrl_mb_rst &light_padctrl +#define padctrl_mb_int &light_padctrl0 +#define padctrl_mb_rxd &light_padctrl1 +#define padctrl_mb_txd &light_padctrl1 +#define padctrl_mb_cs &light_padctrl0 +#define padctrl_mb_sck &light_padctrl0 +#define padctrl_mb_miso &light_padctrl0 +#define padctrl_mb_mosi &light_padctrl0 +#define padctrl_mb_scl &light_padctrl1 +#define padctrl_mb_sda &light_padctrl1 + +/* +* Cape compatibility PinMuxing macros +*/ + +// P8 cape header +#define P8_03(muxmode, config) FM_GPIO1_21 muxmode config +#define P8_04(muxmode, config) FM_GPIO1_22 muxmode config +#define P8_05(muxmode, config) FM_GPIO1_23 muxmode config +#define P8_06(muxmode, config) FM_GPIO1_24 muxmode config +#define P8_07(muxmode, config) FM_GPIO1_25 muxmode config +#define P8_08(muxmode, config) FM_GPIO1_26 muxmode config +#define P8_09(muxmode, config) FM_GPIO1_27 muxmode config +#define P8_10(muxmode, config) FM_GPIO1_28 muxmode config +#define P8_11(muxmode, config) FM_GPIO1_29 muxmode config +#define P8_12(muxmode, config) FM_GPIO1_30 muxmode config +#define P8_13(muxmode, config) FM_GPIO3_2 muxmode config +#define P8_14(muxmode, config) FM_CLK_OUT_3 muxmode config +#define P8_15(muxmode, config) FM_GPIO3_0 muxmode config +#define P8_16(muxmode, config) FM_GPIO0_20 muxmode config +#define P8_17(muxmode, config) FM_GPIO3_1 muxmode config +#define P8_18(muxmode, config) FM_GPIO1_5 muxmode config +#define P8_19(muxmode, config) FM_GPIO3_3 muxmode config +#define P8_20(muxmode, config) FM_GPIO1_6 muxmode config +#define P8_21(muxmode, config) FM_GPIO1_7 muxmode config +#define P8_22(muxmode, config) FM_GPIO1_8 muxmode config +#define P8_23(muxmode, config) FM_GPIO1_9 muxmode config +#define P8_24(muxmode, config) FM_GPIO1_10 muxmode config +#define P8_25(muxmode, config) FM_GPIO1_11 muxmode config +#define P8_26(muxmode, config) FM_GPIO1_12 muxmode config +#define P8_27(muxmode, config) FM_GPIO1_15 muxmode config +#define P8_28(muxmode, config) FM_GPIO1_16 muxmode config +#define P8_29(muxmode, config) FM_GPIO1_14 muxmode config +#define P8_30(muxmode, config) FM_GPIO1_13 muxmode config +#define P8_31(muxmode, config) FM_GPIO1_3 muxmode config +#define P8_32(muxmode, config) FM_GPIO1_4 muxmode config +#define P8_33(muxmode, config) FM_GPIO1_2 muxmode config +#define P8_34(muxmode, config) FM_GPIO1_0 muxmode config +#define P8_35(muxmode, config) FM_GPIO1_1 muxmode config +#define P8_36(muxmode, config) FM_GPIO0_31 muxmode config +#define P8_37(muxmode, config) FM_GPIO0_29 muxmode config +#define P8_38(muxmode, config) FM_GPIO0_30 muxmode config +#define P8_39(muxmode, config) FM_GPIO0_27 muxmode config +#define P8_40(muxmode, config) FM_GPIO0_28 muxmode config +#define P8_41(muxmode, config) FM_GPIO0_25 muxmode config +#define P8_42(muxmode, config) FM_GPIO0_26 muxmode config +#define P8_43(muxmode, config) FM_GPIO0_23 muxmode config +#define P8_44(muxmode, config) FM_GPIO0_24 muxmode config +#define P8_45(muxmode, config) FM_GPIO0_21 muxmode config +#define P8_46(muxmode, config) FM_GPIO0_22 muxmode config + +// P9 cape header +#define P9_11(muxmode, config) FM_UART1_TXD muxmode config +#define P9_12(muxmode, config) FM_QSPI0_CSN0 muxmode config +#define P9_13(muxmode, config) FM_UART1_RXD muxmode config +#define P9_14(muxmode, config) FM_QSPI0_D1_MISO muxmode config +#define P9_15(muxmode, config) FM_QSPI0_D2_WP muxmode config +#define P9_16(muxmode, config) FM_QSPI0_D0_MOSI muxmode config +#define P9_17(muxmode, config) FM_QSPI1_CSN0 muxmode config +#define P9_18(muxmode, config) FM_QSPI1_D0_MOSI muxmode config +#define P9_19(muxmode, config) FM_I2C2_SCL muxmode config +#define P9_20(muxmode, config) FM_I2C2_SDA muxmode config +#define P9_21(muxmode, config) FM_QSPI1_D1_MISO muxmode config +#define P9_22(muxmode, config) FM_QSPI1_SCLK muxmode config +#define P9_23(muxmode, config) FM_QSPI0_D3_HOLD muxmode config +#define P9_24(muxmode, config) FM_QSPI1_D2_WP muxmode config +#define P9_25(muxmode, config) FM_GPIO2_18 muxmode config +#define P9_26(muxmode, config) FM_QSPI1_D3_HOLD muxmode config +#define P9_27(muxmode, config) FM_GPIO2_19 muxmode config +#define P9_28(muxmode, config) FM_SPI_CSN muxmode config +#define P9_29(muxmode, config) FM_SPI_MISO muxmode config +#define P9_30(muxmode, config) FM_SPI_MOSI muxmode config +#define P9_31(muxmode, config) FM_SPI_SCLK muxmode config +#define P9_41(muxmode, config) FM_GPIO2_13 muxmode config +#define P9_42(muxmode, config) FM_QSPI0_SCLK muxmode config + +// mikroBus port +#define mb_pwm(muxmode, config) FM_QSPI0_CSN1 muxmode config +#define mb_rst(muxmode, config) FM_AUDIO_PA3 muxmode config +#define mb_int(muxmode, config) FM_GPIO2_21 muxmode config +#define mb_rxd(muxmode, config) FM_UART3_RXD muxmode config +#define mb_txd(muxmode, config) FM_UART3_TXD muxmode config +#define mb_cs(muxmode, config) FM_GPIO2_20 muxmode config +#define mb_sck(muxmode, config) FM_SPI_SCLK muxmode config +#define mb_miso(muxmode, config) FM_SPI_MISO muxmode config +#define mb_mosi(muxmode, config) FM_SPI_MOSI muxmode config +#define mb_scl(muxmode, config) FM_GPIO0_18 muxmode config +#define mb_sda(muxmode, config) FM_GPIO0_19 muxmode config + +#endif diff --git a/include/dt-bindings/pinctrl/light.h b/include/dt-bindings/pinctrl/light.h new file mode 100644 index 000000000..f07e43afb --- /dev/null +++ b/include/dt-bindings/pinctrl/light.h @@ -0,0 +1,53 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (C) 2023 BeagleBoard.org - https://beagleboard.org/ + * Copyright (C) 2023 Deepak Khatri + */ + +#ifndef _LIGHT_H +#define _LIGHT_H + +#define MUX_MODE0 0x0 +#define MUX_MODE1 0x1 +#define MUX_MODE2 0x2 +#define MUX_MODE3 0x3 +#define MUX_MODE4 0x4 +#define MUX_MODE5 0x5 + +#define INPUT_ENABLE_SHIFT (9) +#define SLEW_RATE_SHIFT (8) +#define SCHMITT_TRIGGER_SHIFT (7) +#define STRONG_PULLUP_SHIFT (6) +#define PULL_SELECT_SHIFT (5) +#define PULL_ENABLE_SHIFT (4) +#define DRIVE_STRENGTH_BIT3_SHIFT (3) +#define DRIVE_STRENGTH_BIT2_SHIFT (2) +#define DRIVE_STRENGTH_BIT1_SHIFT (1) +#define DRIVE_STRENGTH_BIT0_SHIFT (0) + +#define PULL_ENA (1 << PULL_ENABLE_SHIFT) +#define PULL_UP (1 << PULL_SELECT_SHIFT) +#define INPUT_EN (1 << INPUT_ENABLE_SHIFT) +#define SLEWCONTROL (1 << SLEW_RATE_SHIFT) +#define STRONG_PULLUP (1 << STRONG_PULLUP_SHIFT) + +#define DS3 (1 << DRIVE_STRENGTH_BIT3_SHIFT) +#define DS2 (1 << DRIVE_STRENGTH_BIT2_SHIFT) +#define DS1 (1 << DRIVE_STRENGTH_BIT1_SHIFT) +#define DS0 (1 << DRIVE_STRENGTH_BIT0_SHIFT) + +#define STRENGTH_LOW (DS0 | DS2) +#define STRENGTH_MID (DS1 | DS3) +#define STRENGTH_HIGH (DS0 | DS1 | DS2 | DS3) + +#define PIN_OUTPUT 0 +#define PIN_OUTPUT_PULLDOWN (PIN_OUTPUT | PULL_ENA) +#define PIN_OUTPUT_PULLUP (PIN_OUTPUT | PULL_ENA | PULL_UP) +#define PIN_OUTPUT_STRONG_PULLUP (PIN_OUTPUT | PULL_ENA | PULL_UP | STRONG_PULLUP) + +#define PIN_INPUT INPUT_EN +#define PIN_INPUT_PULLDOWN (PULL_ENA | INPUT_EN) +#define PIN_INPUT_PULLUP (PULL_ENA | INPUT_EN | PULL_UP) +#define PIN_INPUT_STRONG_PULLUP (PULL_ENA | INPUT_EN | PULL_UP | STRONG_PULLUP) + +#endif \ No newline at end of file