mirror of
https://github.com/revyos/thead-kernel.git
synced 2026-09-17 21:02:13 +02:00
Kernel: Add gpu_bxm img-rogue driver
This commit is contained in:
Mingzheng Xing
108
drivers/gpu/drm/img-rogue/include/system/rgx_tc/apollo_regs.h
Normal file
108
drivers/gpu/drm/img-rogue/include/system/rgx_tc/apollo_regs.h
Normal file
@@ -0,0 +1,108 @@
|
||||
/*************************************************************************/ /*!
|
||||
@File
|
||||
@Title System Description Header
|
||||
@Copyright Copyright (c) Imagination Technologies Ltd. All Rights Reserved
|
||||
@Description This header provides system-specific declarations and macros
|
||||
@License Dual MIT/GPLv2
|
||||
|
||||
The contents of this file are subject to the MIT license as set out below.
|
||||
|
||||
Permission is hereby granted, free of charge, to any person obtaining a copy
|
||||
of this software and associated documentation files (the "Software"), to deal
|
||||
in the Software without restriction, including without limitation the rights
|
||||
to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
|
||||
copies of the Software, and to permit persons to whom the Software is
|
||||
furnished to do so, subject to the following conditions:
|
||||
|
||||
The above copyright notice and this permission notice shall be included in
|
||||
all copies or substantial portions of the Software.
|
||||
|
||||
Alternatively, the contents of this file may be used under the terms of
|
||||
the GNU General Public License Version 2 ("GPL") in which case the provisions
|
||||
of GPL are applicable instead of those above.
|
||||
|
||||
If you wish to allow use of your version of this file only under the terms of
|
||||
GPL, and not to allow others to use your version of this file under the terms
|
||||
of the MIT license, indicate your decision by deleting the provisions above
|
||||
and replace them with the notice and other provisions required by GPL as set
|
||||
out in the file called "GPL-COPYING" included in this distribution. If you do
|
||||
not delete the provisions above, a recipient may use your version of this file
|
||||
under the terms of either the MIT license or GPL.
|
||||
|
||||
This License is also included in this distribution in the file called
|
||||
"MIT-COPYING".
|
||||
|
||||
EXCEPT AS OTHERWISE STATED IN A NEGOTIATED AGREEMENT: (A) THE SOFTWARE IS
|
||||
PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING
|
||||
BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR
|
||||
PURPOSE AND NONINFRINGEMENT; AND (B) IN NO EVENT SHALL THE AUTHORS OR
|
||||
COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
|
||||
IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
|
||||
CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
|
||||
*/ /**************************************************************************/
|
||||
|
||||
#if !defined(APOLLO_REGS_H)
|
||||
#define APOLLO_REGS_H
|
||||
|
||||
#include "tc_clocks.h"
|
||||
|
||||
/* TC TCF5 */
|
||||
#define TC5_SYS_APOLLO_REG_PCI_BASENUM (1)
|
||||
#define TC5_SYS_APOLLO_REG_PDP2_OFFSET (0x800000)
|
||||
#define TC5_SYS_APOLLO_REG_PDP2_SIZE (0x7C4)
|
||||
|
||||
#define TC5_SYS_APOLLO_REG_PDP2_FBDC_OFFSET (0xA00000)
|
||||
#define TC5_SYS_APOLLO_REG_PDP2_FBDC_SIZE (0x14)
|
||||
|
||||
#define TC5_SYS_APOLLO_REG_HDMI_OFFSET (0xC00000)
|
||||
#define TC5_SYS_APOLLO_REG_HDMI_SIZE (0x1C)
|
||||
|
||||
/* TC ES2 */
|
||||
#define TCF_TEMP_SENSOR_SPI_OFFSET 0xe
|
||||
#define TCF_TEMP_SENSOR_TO_C(raw) (((raw) * 248 / 4096) - 54)
|
||||
|
||||
/* Number of bytes that are broken */
|
||||
#define SYS_DEV_MEM_BROKEN_BYTES (1024 * 1024)
|
||||
#define SYS_DEV_MEM_REGION_SIZE (0x40000000 - SYS_DEV_MEM_BROKEN_BYTES)
|
||||
|
||||
/* Apollo reg on base register 0 */
|
||||
#define SYS_APOLLO_REG_PCI_BASENUM (0)
|
||||
#define SYS_APOLLO_REG_REGION_SIZE (0x00010000)
|
||||
|
||||
#define SYS_APOLLO_REG_SYS_OFFSET (0x0000)
|
||||
#define SYS_APOLLO_REG_SYS_SIZE (0x0400)
|
||||
|
||||
#define SYS_APOLLO_REG_PLL_OFFSET (0x1000)
|
||||
#define SYS_APOLLO_REG_PLL_SIZE (0x0400)
|
||||
|
||||
#define SYS_APOLLO_REG_HOST_OFFSET (0x4050)
|
||||
#define SYS_APOLLO_REG_HOST_SIZE (0x0014)
|
||||
|
||||
#define SYS_APOLLO_REG_PDP1_OFFSET (0xC000)
|
||||
#define SYS_APOLLO_REG_PDP1_SIZE (0x2000)
|
||||
|
||||
/* Offsets for flashing Apollo PROMs from base 0 */
|
||||
#define APOLLO_FLASH_STAT_OFFSET (0x4058)
|
||||
#define APOLLO_FLASH_DATA_WRITE_OFFSET (0x4050)
|
||||
#define APOLLO_FLASH_RESET_OFFSET (0x4060)
|
||||
|
||||
#define APOLLO_FLASH_FIFO_STATUS_MASK (0xF)
|
||||
#define APOLLO_FLASH_FIFO_STATUS_SHIFT (0)
|
||||
#define APOLLO_FLASH_PROGRAM_STATUS_MASK (0xF)
|
||||
#define APOLLO_FLASH_PROGRAM_STATUS_SHIFT (16)
|
||||
|
||||
#define APOLLO_FLASH_PROG_COMPLETE_BIT (0x1)
|
||||
#define APOLLO_FLASH_PROG_PROGRESS_BIT (0x2)
|
||||
#define APOLLO_FLASH_PROG_FAILED_BIT (0x4)
|
||||
#define APOLLO_FLASH_INV_FILETYPE_BIT (0x8)
|
||||
|
||||
#define APOLLO_FLASH_FIFO_SIZE (8)
|
||||
|
||||
/* RGX reg on base register 1 */
|
||||
#define SYS_RGX_REG_PCI_BASENUM (1)
|
||||
#define SYS_RGX_REG_REGION_SIZE (0x7FFFF)
|
||||
|
||||
/* Device memory (including HP mapping) on base register 2 */
|
||||
#define SYS_DEV_MEM_PCI_BASENUM (2)
|
||||
|
||||
#endif /* APOLLO_REGS_H */
|
||||
68
drivers/gpu/drm/img-rogue/include/system/rgx_tc/bonnie_tcf.h
Normal file
68
drivers/gpu/drm/img-rogue/include/system/rgx_tc/bonnie_tcf.h
Normal file
@@ -0,0 +1,68 @@
|
||||
/*************************************************************************/ /*!
|
||||
@Copyright Copyright (c) Imagination Technologies Ltd. All Rights Reserved
|
||||
@License Dual MIT/GPLv2
|
||||
|
||||
The contents of this file are subject to the MIT license as set out below.
|
||||
|
||||
Permission is hereby granted, free of charge, to any person obtaining a copy
|
||||
of this software and associated documentation files (the "Software"), to deal
|
||||
in the Software without restriction, including without limitation the rights
|
||||
to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
|
||||
copies of the Software, and to permit persons to whom the Software is
|
||||
furnished to do so, subject to the following conditions:
|
||||
|
||||
The above copyright notice and this permission notice shall be included in
|
||||
all copies or substantial portions of the Software.
|
||||
|
||||
Alternatively, the contents of this file may be used under the terms of
|
||||
the GNU General Public License Version 2 ("GPL") in which case the provisions
|
||||
of GPL are applicable instead of those above.
|
||||
|
||||
If you wish to allow use of your version of this file only under the terms of
|
||||
GPL, and not to allow others to use your version of this file under the terms
|
||||
of the MIT license, indicate your decision by deleting the provisions above
|
||||
and replace them with the notice and other provisions required by GPL as set
|
||||
out in the file called "GPL-COPYING" included in this distribution. If you do
|
||||
not delete the provisions above, a recipient may use your version of this file
|
||||
under the terms of either the MIT license or GPL.
|
||||
|
||||
This License is also included in this distribution in the file called
|
||||
"MIT-COPYING".
|
||||
|
||||
EXCEPT AS OTHERWISE STATED IN A NEGOTIATED AGREEMENT: (A) THE SOFTWARE IS
|
||||
PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING
|
||||
BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR
|
||||
PURPOSE AND NONINFRINGEMENT; AND (B) IN NO EVENT SHALL THE AUTHORS OR
|
||||
COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
|
||||
IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
|
||||
CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
|
||||
*/ /**************************************************************************/
|
||||
|
||||
/* bonnie_tcf.h - Bonnie TCF register definitions */
|
||||
|
||||
/* tab size 4 */
|
||||
|
||||
#ifndef BONNIE_TCF_DEFS_H
|
||||
#define BONNIE_TCF_DEFS_H
|
||||
|
||||
#define BONNIE_TCF_OFFSET_BONNIETC_REGBANK 0x00000000
|
||||
#define BONNIE_TCF_OFFSET_TC_IFACE_COUNTERS 0x00004000
|
||||
#define BONNIE_TCF_OFFSET_TC_TEST_MODULE_IMGV4_RTM_TOP 0x00008000
|
||||
#define BONNIE_TCF_OFFSET_TC_TEST_MODULE_TCF_SCRATCH_PAD_SECN 0x0000C000
|
||||
#define BONNIE_TCF_OFFSET_TC_TEST_MODULE_TCF_SCRATCH_PAD_DBG 0x00010000
|
||||
#define BONNIE_TCF_OFFSET_MULTI_CLK_ALIGN 0x00014000
|
||||
#define BONNIE_TCF_OFFSET_ALIGN_DATA_TX 0x00018000
|
||||
#define BONNIE_TCF_OFFSET_SAI_RX_1 0x0001C000
|
||||
#define BONNIE_TCF_OFFSET_SAI_RX_SDR 0x00040000
|
||||
#define BONNIE_TCF_OFFSET_SAI_TX_1 0x00044000
|
||||
#define BONNIE_TCF_OFFSET_SAI_TX_SDR 0x00068000
|
||||
|
||||
#define BONNIE_TCF_OFFSET_SAI_RX_DELTA 0x00004000
|
||||
#define BONNIE_TCF_OFFSET_SAI_TX_DELTA 0x00004000
|
||||
|
||||
#define BONNIE_TCF_OFFSET_SAI_CLK_TAPS 0x0000000C
|
||||
#define BONNIE_TCF_OFFSET_SAI_EYES 0x00000010
|
||||
#define BONNIE_TCF_OFFSET_SAI_TRAIN_ACK 0x00000018
|
||||
|
||||
|
||||
#endif /* BONNIE_TCF_DEFS_H */
|
||||
326
drivers/gpu/drm/img-rogue/include/system/rgx_tc/odin_defs.h
Normal file
326
drivers/gpu/drm/img-rogue/include/system/rgx_tc/odin_defs.h
Normal file
@@ -0,0 +1,326 @@
|
||||
/****************************************************************************
|
||||
@Copyright Copyright (c) Imagination Technologies Ltd. All Rights Reserved
|
||||
@Description Odin Memory Map - View from PCIe
|
||||
@License Dual MIT/GPLv2
|
||||
|
||||
The contents of this file are subject to the MIT license as set out below.
|
||||
|
||||
Permission is hereby granted, free of charge, to any person obtaining a copy
|
||||
of this software and associated documentation files (the "Software"), to deal
|
||||
in the Software without restriction, including without limitation the rights
|
||||
to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
|
||||
copies of the Software, and to permit persons to whom the Software is
|
||||
furnished to do so, subject to the following conditions:
|
||||
|
||||
The above copyright notice and this permission notice shall be included in
|
||||
all copies or substantial portions of the Software.
|
||||
|
||||
Alternatively, the contents of this file may be used under the terms of
|
||||
the GNU General Public License Version 2 ("GPL") in which case the provisions
|
||||
of GPL are applicable instead of those above.
|
||||
|
||||
If you wish to allow use of your version of this file only under the terms of
|
||||
GPL, and not to allow others to use your version of this file under the terms
|
||||
of the MIT license, indicate your decision by deleting the provisions above
|
||||
and replace them with the notice and other provisions required by GPL as set
|
||||
out in the file called "GPL-COPYING" included in this distribution. If you do
|
||||
not delete the provisions above, a recipient may use your version of this file
|
||||
under the terms of either the MIT license or GPL.
|
||||
|
||||
This License is also included in this distribution in the file called
|
||||
"MIT-COPYING".
|
||||
|
||||
EXCEPT AS OTHERWISE STATED IN A NEGOTIATED AGREEMENT: (A) THE SOFTWARE IS
|
||||
PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING
|
||||
BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR
|
||||
PURPOSE AND NONINFRINGEMENT; AND (B) IN NO EVENT SHALL THE AUTHORS OR
|
||||
COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
|
||||
IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
|
||||
CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
|
||||
****************************************************************************/
|
||||
|
||||
#ifndef _ODIN_DEFS_H_
|
||||
#define _ODIN_DEFS_H_
|
||||
|
||||
/* These defines have not been autogenerated */
|
||||
|
||||
#define PCI_VENDOR_ID_ODIN (0x1AEE)
|
||||
#define DEVICE_ID_ODIN (0x1010)
|
||||
#define DEVICE_ID_TBA (0x1CF2)
|
||||
|
||||
/* PCI BAR 0 contains the PDP regs and the Odin system regs */
|
||||
#define ODN_SYS_BAR 0
|
||||
#define ODN_SYS_REGION_SIZE 0x000800000 /* 8MB */
|
||||
|
||||
#define ODN_SYS_REGS_OFFSET 0
|
||||
#define ODN_SYS_REGS_SIZE 0x000400000 /* 4MB */
|
||||
|
||||
#define ODN_PDP_REGS_OFFSET 0x000440000
|
||||
#define ODN_PDP_REGS_SIZE 0x000040000 /* 256k */
|
||||
|
||||
#define ODN_PDP2_REGS_OFFSET 0x000480000
|
||||
#define ODN_PDP2_REGS_SIZE 0x000040000 /* 256k */
|
||||
|
||||
#define ODN_PDP2_PFIM_OFFSET 0x000500000
|
||||
#define ODN_PDP2_PFIM_SIZE 0x000040000 /* 256k */
|
||||
|
||||
#define ODIN_DMA_REGS_OFFSET 0x0004C0000
|
||||
#define ODIN_DMA_REGS_SIZE 0x000040000 /* 256k */
|
||||
|
||||
#define ODIN_DMA_CHAN_REGS_SIZE 0x000001000 /* 4k */
|
||||
|
||||
/* PCI BAR 2 contains the Device Under Test SOCIF 64MB region */
|
||||
#define ODN_DUT_SOCIF_BAR 2
|
||||
#define ODN_DUT_SOCIF_OFFSET 0x000000000
|
||||
#define ODN_DUT_SOCIF_SIZE 0x004000000 /* 64MB */
|
||||
|
||||
/* PCI BAR 4 contains the on-board 1GB DDR memory */
|
||||
#define ODN_DDR_BAR 4
|
||||
#define ODN_DDR_MEM_OFFSET 0x000000000
|
||||
#define ODN_DDR_MEM_SIZE 0x040000000 /* 1GB */
|
||||
|
||||
/* Odin system register banks */
|
||||
#define ODN_REG_BANK_CORE 0x00000
|
||||
#define ODN_REG_BANK_TCF_SPI_MASTER 0x02000
|
||||
#define ODN_REG_BANK_ODN_CLK_BLK 0x0A000
|
||||
#define ODN_REG_BANK_ODN_MCU_COMMUNICATOR 0x0C000
|
||||
#define ODN_REG_BANK_DB_TYPE_ID 0x0C200
|
||||
#define ODN_REG_BANK_DB_TYPE_ID_TYPE_TCFVUOCTA 0x000000C6U
|
||||
#define ODN_REG_BANK_DB_TYPE_ID_TYPE_MASK 0x000000C0U
|
||||
#define ODN_REG_BANK_DB_TYPE_ID_TYPE_SHIFT 0x6
|
||||
#define ODN_REG_BANK_ODN_I2C 0x0E000
|
||||
#define ODN_REG_BANK_MULTI_CLK_ALIGN 0x20000
|
||||
#define ODN_REG_BANK_ALIGN_DATA_TX 0x22000
|
||||
#define ODN_REG_BANK_SAI_RX_DDR_0 0x24000
|
||||
#define ODN_REG_BANK_SAI_RX_DDR(n) (ODN_REG_BANK_SAI_RX_DDR_0 + (0x02000*n))
|
||||
#define ODN_REG_BANK_SAI_TX_DDR_0 0x3A000
|
||||
#define ODN_REG_BANK_SAI_TX_DDR(n) (ODN_REG_BANK_SAI_TX_DDR_0 + (0x02000*n))
|
||||
#define ODN_REG_BANK_SAI_TX_SDR 0x4E000
|
||||
|
||||
/* Odin SPI regs */
|
||||
#define ODN_SPI_MST_ADDR_RDNWR 0x0000
|
||||
#define ODN_SPI_MST_WDATA 0x0004
|
||||
#define ODN_SPI_MST_RDATA 0x0008
|
||||
#define ODN_SPI_MST_STATUS 0x000C
|
||||
#define ODN_SPI_MST_GO 0x0010
|
||||
|
||||
|
||||
/*
|
||||
Odin CLK regs - the odn_clk_blk module defs are not auto generated
|
||||
*/
|
||||
#define ODN_PDP_P_CLK_OUT_DIVIDER_REG1 0x620
|
||||
#define ODN_PDP_PCLK_ODIV1_LO_TIME_MASK 0x0000003FU
|
||||
#define ODN_PDP_PCLK_ODIV1_LO_TIME_SHIFT 0
|
||||
#define ODN_PDP_PCLK_ODIV1_HI_TIME_MASK 0x00000FC0U
|
||||
#define ODN_PDP_PCLK_ODIV1_HI_TIME_SHIFT 6
|
||||
|
||||
#define ODN_PDP_P_CLK_OUT_DIVIDER_REG2 0x624
|
||||
#define ODN_PDP_PCLK_ODIV2_NOCOUNT_MASK 0x00000040U
|
||||
#define ODN_PDP_PCLK_ODIV2_NOCOUNT_SHIFT 6
|
||||
#define ODN_PDP_PCLK_ODIV2_EDGE_MASK 0x00000080U
|
||||
#define ODN_PDP_PCLK_ODIV2_EDGE_SHIFT 7
|
||||
|
||||
#define ODN_PDP_P_CLK_OUT_DIVIDER_REG3 0x61C
|
||||
|
||||
#define ODN_PDP_M_CLK_OUT_DIVIDER_REG1 0x628
|
||||
#define ODN_PDP_MCLK_ODIV1_LO_TIME_MASK 0x0000003FU
|
||||
#define ODN_PDP_MCLK_ODIV1_LO_TIME_SHIFT 0
|
||||
#define ODN_PDP_MCLK_ODIV1_HI_TIME_MASK 0x00000FC0U
|
||||
#define ODN_PDP_MCLK_ODIV1_HI_TIME_SHIFT 6
|
||||
|
||||
#define ODN_PDP_M_CLK_OUT_DIVIDER_REG2 0x62C
|
||||
#define ODN_PDP_MCLK_ODIV2_NOCOUNT_MASK 0x00000040U
|
||||
#define ODN_PDP_MCLK_ODIV2_NOCOUNT_SHIFT 6
|
||||
#define ODN_PDP_MCLK_ODIV2_EDGE_MASK 0x00000080U
|
||||
#define ODN_PDP_MCLK_ODIV2_EDGE_SHIFT 7
|
||||
|
||||
#define ODN_PDP_P_CLK_MULTIPLIER_REG1 0x650
|
||||
#define ODN_PDP_PCLK_MUL1_LO_TIME_MASK 0x0000003FU
|
||||
#define ODN_PDP_PCLK_MUL1_LO_TIME_SHIFT 0
|
||||
#define ODN_PDP_PCLK_MUL1_HI_TIME_MASK 0x00000FC0U
|
||||
#define ODN_PDP_PCLK_MUL1_HI_TIME_SHIFT 6
|
||||
|
||||
#define ODN_PDP_P_CLK_MULTIPLIER_REG2 0x654
|
||||
#define ODN_PDP_PCLK_MUL2_NOCOUNT_MASK 0x00000040U
|
||||
#define ODN_PDP_PCLK_MUL2_NOCOUNT_SHIFT 6
|
||||
#define ODN_PDP_PCLK_MUL2_EDGE_MASK 0x00000080U
|
||||
#define ODN_PDP_PCLK_MUL2_EDGE_SHIFT 7
|
||||
|
||||
#define ODN_PDP_P_CLK_MULTIPLIER_REG3 0x64C
|
||||
|
||||
#define ODN_PDP_P_CLK_IN_DIVIDER_REG 0x658
|
||||
#define ODN_PDP_PCLK_IDIV_LO_TIME_MASK 0x0000003FU
|
||||
#define ODN_PDP_PCLK_IDIV_LO_TIME_SHIFT 0
|
||||
#define ODN_PDP_PCLK_IDIV_HI_TIME_MASK 0x00000FC0U
|
||||
#define ODN_PDP_PCLK_IDIV_HI_TIME_SHIFT 6
|
||||
#define ODN_PDP_PCLK_IDIV_NOCOUNT_MASK 0x00001000U
|
||||
#define ODN_PDP_PCLK_IDIV_NOCOUNT_SHIFT 12
|
||||
#define ODN_PDP_PCLK_IDIV_EDGE_MASK 0x00002000U
|
||||
#define ODN_PDP_PCLK_IDIV_EDGE_SHIFT 13
|
||||
|
||||
/*
|
||||
* DUT core clock input divider, multiplier and out divider.
|
||||
*/
|
||||
#define ODN_DUT_CORE_CLK_OUT_DIVIDER1 (0x0028)
|
||||
#define ODN_DUT_CORE_CLK_OUT_DIVIDER1_HI_TIME_MASK (0x00000FC0U)
|
||||
#define ODN_DUT_CORE_CLK_OUT_DIVIDER1_HI_TIME_SHIFT (6)
|
||||
#define ODN_DUT_CORE_CLK_OUT_DIVIDER1_LO_TIME_MASK (0x0000003FU)
|
||||
#define ODN_DUT_CORE_CLK_OUT_DIVIDER1_LO_TIME_SHIFT (0)
|
||||
|
||||
#define ODN_DUT_CORE_CLK_OUT_DIVIDER2 (0x002C)
|
||||
#define ODN_DUT_CORE_CLK_OUT_DIVIDER2_EDGE_MASK (0x00000080U)
|
||||
#define ODN_DUT_CORE_CLK_OUT_DIVIDER2_EDGE_SHIFT (7)
|
||||
#define ODN_DUT_CORE_CLK_OUT_DIVIDER2_NOCOUNT_MASK (0x00000040U)
|
||||
#define ODN_DUT_CORE_CLK_OUT_DIVIDER2_NOCOUNT_SHIFT (6)
|
||||
|
||||
#define ODN_DUT_CORE_CLK_MULTIPLIER1 (0x0050)
|
||||
#define ODN_DUT_CORE_CLK_MULTIPLIER1_HI_TIME_MASK (0x00000FC0U)
|
||||
#define ODN_DUT_CORE_CLK_MULTIPLIER1_HI_TIME_SHIFT (6)
|
||||
#define ODN_DUT_CORE_CLK_MULTIPLIER1_LO_TIME_MASK (0x0000003FU)
|
||||
#define ODN_DUT_CORE_CLK_MULTIPLIER1_LO_TIME_SHIFT (0)
|
||||
|
||||
#define ODN_DUT_CORE_CLK_MULTIPLIER2 (0x0054)
|
||||
#define ODN_DUT_CORE_CLK_MULTIPLIER2_FRAC_MASK (0x00007000U)
|
||||
#define ODN_DUT_CORE_CLK_MULTIPLIER2_FRAC_SHIFT (12)
|
||||
#define ODN_DUT_CORE_CLK_MULTIPLIER2_FRAC_EN_MASK (0x00000800U)
|
||||
#define ODN_DUT_CORE_CLK_MULTIPLIER2_FRAC_EN_SHIFT (11)
|
||||
#define ODN_DUT_CORE_CLK_MULTIPLIER2_EDGE_MASK (0x00000080U)
|
||||
#define ODN_DUT_CORE_CLK_MULTIPLIER2_EDGE_SHIFT (7)
|
||||
#define ODN_DUT_CORE_CLK_MULTIPLIER2_NOCOUNT_MASK (0x00000040U)
|
||||
#define ODN_DUT_CORE_CLK_MULTIPLIER2_NOCOUNT_SHIFT (6)
|
||||
|
||||
#define ODN_DUT_CORE_CLK_IN_DIVIDER1 (0x0058)
|
||||
#define ODN_DUT_CORE_CLK_IN_DIVIDER1_EDGE_MASK (0x00002000U)
|
||||
#define ODN_DUT_CORE_CLK_IN_DIVIDER1_EDGE_SHIFT (13)
|
||||
#define ODN_DUT_CORE_CLK_IN_DIVIDER1_NOCOUNT_MASK (0x00001000U)
|
||||
#define ODN_DUT_CORE_CLK_IN_DIVIDER1_NOCOUNT_SHIFT (12)
|
||||
#define ODN_DUT_CORE_CLK_IN_DIVIDER1_HI_TIME_MASK (0x00000FC0U)
|
||||
#define ODN_DUT_CORE_CLK_IN_DIVIDER1_HI_TIME_SHIFT (6)
|
||||
#define ODN_DUT_CORE_CLK_IN_DIVIDER1_LO_TIME_MASK (0x0000003FU)
|
||||
#define ODN_DUT_CORE_CLK_IN_DIVIDER1_LO_TIME_SHIFT (0)
|
||||
|
||||
/*
|
||||
* DUT interface clock input divider, multiplier and out divider.
|
||||
*/
|
||||
#define ODN_DUT_IFACE_CLK_OUT_DIVIDER1 (0x0220)
|
||||
#define ODN_DUT_IFACE_CLK_OUT_DIVIDER1_HI_TIME_MASK (0x00000FC0U)
|
||||
#define ODN_DUT_IFACE_CLK_OUT_DIVIDER1_HI_TIME_SHIFT (6)
|
||||
#define ODN_DUT_IFACE_CLK_OUT_DIVIDER1_LO_TIME_MASK (0x0000003FU)
|
||||
#define ODN_DUT_IFACE_CLK_OUT_DIVIDER1_LO_TIME_SHIFT (0)
|
||||
|
||||
#define ODN_DUT_IFACE_CLK_OUT_DIVIDER2 (0x0224)
|
||||
#define ODN_DUT_IFACE_CLK_OUT_DIVIDER2_EDGE_MASK (0x00000080U)
|
||||
#define ODN_DUT_IFACE_CLK_OUT_DIVIDER2_EDGE_SHIFT (7)
|
||||
#define ODN_DUT_IFACE_CLK_OUT_DIVIDER2_NOCOUNT_MASK (0x00000040U)
|
||||
#define ODN_DUT_IFACE_CLK_OUT_DIVIDER2_NOCOUNT_SHIFT (6)
|
||||
|
||||
#define ODN_DUT_IFACE_CLK_MULTIPLIER1 (0x0250)
|
||||
#define ODN_DUT_IFACE_CLK_MULTIPLIER1_HI_TIME_MASK (0x00000FC0U)
|
||||
#define ODN_DUT_IFACE_CLK_MULTIPLIER1_HI_TIME_SHIFT (6)
|
||||
#define ODN_DUT_IFACE_CLK_MULTIPLIER1_LO_TIME_MASK (0x0000003FU)
|
||||
#define ODN_DUT_IFACE_CLK_MULTIPLIER1_LO_TIME_SHIFT (0)
|
||||
|
||||
#define ODN_DUT_IFACE_CLK_MULTIPLIER2 (0x0254)
|
||||
#define ODN_DUT_IFACE_CLK_MULTIPLIER2_FRAC_MASK (0x00007000U)
|
||||
#define ODN_DUT_IFACE_CLK_MULTIPLIER2_FRAC_SHIFT (12)
|
||||
#define ODN_DUT_IFACE_CLK_MULTIPLIER2_FRAC_EN_MASK (0x00000800U)
|
||||
#define ODN_DUT_IFACE_CLK_MULTIPLIER2_FRAC_EN_SHIFT (11)
|
||||
#define ODN_DUT_IFACE_CLK_MULTIPLIER2_EDGE_MASK (0x00000080U)
|
||||
#define ODN_DUT_IFACE_CLK_MULTIPLIER2_EDGE_SHIFT (7)
|
||||
#define ODN_DUT_IFACE_CLK_MULTIPLIER2_NOCOUNT_MASK (0x00000040U)
|
||||
#define ODN_DUT_IFACE_CLK_MULTIPLIER2_NOCOUNT_SHIFT (6)
|
||||
|
||||
#define ODN_DUT_IFACE_CLK_IN_DIVIDER1 (0x0258)
|
||||
#define ODN_DUT_IFACE_CLK_IN_DIVIDER1_EDGE_MASK (0x00002000U)
|
||||
#define ODN_DUT_IFACE_CLK_IN_DIVIDER1_EDGE_SHIFT (13)
|
||||
#define ODN_DUT_IFACE_CLK_IN_DIVIDER1_NOCOUNT_MASK (0x00001000U)
|
||||
#define ODN_DUT_IFACE_CLK_IN_DIVIDER1_NOCOUNT_SHIFT (12)
|
||||
#define ODN_DUT_IFACE_CLK_IN_DIVIDER1_HI_TIME_MASK (0x00000FC0U)
|
||||
#define ODN_DUT_IFACE_CLK_IN_DIVIDER1_HI_TIME_SHIFT (6)
|
||||
#define ODN_DUT_IFACE_CLK_IN_DIVIDER1_LO_TIME_MASK (0x0000003FU)
|
||||
#define ODN_DUT_IFACE_CLK_IN_DIVIDER1_LO_TIME_SHIFT (0)
|
||||
|
||||
|
||||
/*
|
||||
* Min max values from Xilinx Virtex7 data sheet DS183, for speed grade 2
|
||||
* All in Hz
|
||||
*/
|
||||
#define ODN_INPUT_CLOCK_SPEED (100000000U)
|
||||
#define ODN_INPUT_CLOCK_SPEED_MIN (10000000U)
|
||||
#define ODN_INPUT_CLOCK_SPEED_MAX (933000000U)
|
||||
#define ODN_OUTPUT_CLOCK_SPEED_MIN (4690000U)
|
||||
#define ODN_OUTPUT_CLOCK_SPEED_MAX (933000000U)
|
||||
#define ODN_VCO_MIN (600000000U)
|
||||
#define ODN_VCO_MAX (1440000000U)
|
||||
#define ODN_PFD_MIN (10000000U)
|
||||
#define ODN_PFD_MAX (500000000U)
|
||||
|
||||
/*
|
||||
* Max values that can be set in DRP registers
|
||||
*/
|
||||
#define ODN_OREG_VALUE_MAX (126.875f)
|
||||
#define ODN_MREG_VALUE_MAX (126.875f)
|
||||
#define ODN_DREG_VALUE_MAX (126U)
|
||||
|
||||
|
||||
#define ODN_MMCM_LOCK_STATUS_DUT_CORE (0x00000001U)
|
||||
#define ODN_MMCM_LOCK_STATUS_DUT_IF (0x00000002U)
|
||||
#define ODN_MMCM_LOCK_STATUS_PDPP (0x00000008U)
|
||||
|
||||
/*
|
||||
Odin interrupt flags
|
||||
*/
|
||||
#define ODN_INTERRUPT_ENABLE_PDP1 (1 << ODN_INTERRUPT_ENABLE_PDP1_SHIFT)
|
||||
#define ODN_INTERRUPT_ENABLE_PDP2 (1 << ODN_INTERRUPT_ENABLE_PDP2_SHIFT)
|
||||
#define ODN_INTERRUPT_ENABLE_DUT (1 << ODN_INTERRUPT_ENABLE_DUT_SHIFT)
|
||||
#define ODN_INTERRUPT_STATUS_PDP1 (1 << ODN_INTERRUPT_STATUS_PDP1_SHIFT)
|
||||
#define ODN_INTERRUPT_STATUS_PDP2 (1 << ODN_INTERRUPT_STATUS_PDP2_SHIFT)
|
||||
#define ODN_INTERRUPT_STATUS_DUT (1 << ODN_INTERRUPT_STATUS_DUT_SHIFT)
|
||||
#define ODN_INTERRUPT_CLEAR_PDP1 (1 << ODN_INTERRUPT_CLR_PDP1_SHIFT)
|
||||
#define ODN_INTERRUPT_CLEAR_PDP2 (1 << ODN_INTERRUPT_CLR_PDP2_SHIFT)
|
||||
#define ODN_INTERRUPT_CLEAR_DUT (1 << ODN_INTERRUPT_CLR_DUT_SHIFT)
|
||||
|
||||
#define ODN_INTERRUPT_ENABLE_CDMA (1 << ODN_INTERRUPT_ENABLE_CDMA_SHIFT)
|
||||
#define ODN_INTERRUPT_STATUS_CDMA (1 << ODN_INTERRUPT_STATUS_CDMA_SHIFT)
|
||||
#define ODN_INTERRUPT_CLEAR_CDMA (1 << ODN_INTERRUPT_CLR_CDMA_SHIFT)
|
||||
|
||||
#define ODN_INTERRUPT_ENABLE_CDMA2 (1 << (ODN_INTERRUPT_ENABLE_CDMA_SHIFT + 1))
|
||||
#define ODN_INTERRUPT_STATUS_CDMA2 (1 << (ODN_INTERRUPT_STATUS_CDMA_SHIFT + 1))
|
||||
#define ODN_INTERRUPT_CLEAR_CDMA2 (1 << (ODN_INTERRUPT_CLR_CDMA_SHIFT + 1))
|
||||
|
||||
/*
|
||||
Other defines
|
||||
*/
|
||||
#define ODN_STREAM_OFF 0
|
||||
#define ODN_STREAM_ON 1
|
||||
#define ODN_SYNC_GEN_DISABLE 0
|
||||
#define ODN_SYNC_GEN_ENABLE 1
|
||||
#define ODN_INTERLACE_DISABLE 0
|
||||
#define ODN_INTERLACE_ENABLE 1
|
||||
#define ODN_PIXEL_CLOCK_INVERTED 1
|
||||
#define ODN_HSYNC_POLARITY_ACTIVE_HIGH 1
|
||||
|
||||
#define ODN_PDP_INTCLR_ALL 0x000FFFFFU
|
||||
#define ODN_PDP_INTSTAT_ALL_OURUN_MASK 0x000FFFF0U
|
||||
|
||||
/*
|
||||
DMA defs
|
||||
*/
|
||||
#define ODN_CDMA_ADDR_WIDTH 35
|
||||
#define ODN_DMA_HW_DESC_HEAP_SIZE 0x100000
|
||||
#define ODN_DMA_CHAN_RX 0
|
||||
#define ODN_DMA_CHAN_TX 1
|
||||
|
||||
#define ODIN_DMA_TX_CHAN_NAME "tx"
|
||||
#define ODIN_DMA_RX_CHAN_NAME "rx"
|
||||
|
||||
/*
|
||||
FBC defs
|
||||
*/
|
||||
#define ODIN_PFIM_RELNUM (005U)
|
||||
|
||||
#endif /* _ODIN_DEFS_H_ */
|
||||
|
||||
/*****************************************************************************
|
||||
End of file (odn_defs.h)
|
||||
*****************************************************************************/
|
||||
8540
drivers/gpu/drm/img-rogue/include/system/rgx_tc/odin_pdp_regs.h
Normal file
8540
drivers/gpu/drm/img-rogue/include/system/rgx_tc/odin_pdp_regs.h
Normal file
File diff suppressed because it is too large
Load Diff
1026
drivers/gpu/drm/img-rogue/include/system/rgx_tc/odin_regs.h
Normal file
1026
drivers/gpu/drm/img-rogue/include/system/rgx_tc/odin_regs.h
Normal file
File diff suppressed because it is too large
Load Diff
183
drivers/gpu/drm/img-rogue/include/system/rgx_tc/orion_defs.h
Normal file
183
drivers/gpu/drm/img-rogue/include/system/rgx_tc/orion_defs.h
Normal file
@@ -0,0 +1,183 @@
|
||||
/****************************************************************************
|
||||
@Copyright Copyright (c) Imagination Technologies Ltd. All Rights Reserved
|
||||
@Description Orion Memory Map - View from PCIe
|
||||
@License Dual MIT/GPLv2
|
||||
|
||||
The contents of this file are subject to the MIT license as set out below.
|
||||
|
||||
Permission is hereby granted, free of charge, to any person obtaining a copy
|
||||
of this software and associated documentation files (the "Software"), to deal
|
||||
in the Software without restriction, including without limitation the rights
|
||||
to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
|
||||
copies of the Software, and to permit persons to whom the Software is
|
||||
furnished to do so, subject to the following conditions:
|
||||
|
||||
The above copyright notice and this permission notice shall be included in
|
||||
all copies or substantial portions of the Software.
|
||||
|
||||
Alternatively, the contents of this file may be used under the terms of
|
||||
the GNU General Public License Version 2 ("GPL") in which case the provisions
|
||||
of GPL are applicable instead of those above.
|
||||
|
||||
If you wish to allow use of your version of this file only under the terms of
|
||||
GPL, and not to allow others to use your version of this file under the terms
|
||||
of the MIT license, indicate your decision by deleting the provisions above
|
||||
and replace them with the notice and other provisions required by GPL as set
|
||||
out in the file called "GPL-COPYING" included in this distribution. If you do
|
||||
not delete the provisions above, a recipient may use your version of this file
|
||||
under the terms of either the MIT license or GPL.
|
||||
|
||||
This License is also included in this distribution in the file called
|
||||
"MIT-COPYING".
|
||||
|
||||
EXCEPT AS OTHERWISE STATED IN A NEGOTIATED AGREEMENT: (A) THE SOFTWARE IS
|
||||
PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING
|
||||
BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR
|
||||
PURPOSE AND NONINFRINGEMENT; AND (B) IN NO EVENT SHALL THE AUTHORS OR
|
||||
COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
|
||||
IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
|
||||
CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
|
||||
****************************************************************************/
|
||||
|
||||
#ifndef _ORION_DEFS_H_
|
||||
#define _ORION_DEFS_H_
|
||||
|
||||
/*
|
||||
* These defines have not been autogenerated
|
||||
* Only values different from Odin will be included here
|
||||
*/
|
||||
|
||||
#define DEVICE_ID_ORION 0x1020
|
||||
|
||||
/* Odin system register banks */
|
||||
#define SRS_REG_BANK_ODN_CLK_BLK 0x02000
|
||||
|
||||
/*
|
||||
* Orion CLK regs - the srs_clk_blk module defs are not auto generated
|
||||
*/
|
||||
#define SRS_PDP_P_CLK_OUT_DIVIDER_REG1 0x620
|
||||
#define SRS_PDP_PCLK_ODIV1_LO_TIME_MASK 0x0000003FU
|
||||
#define SRS_PDP_PCLK_ODIV1_LO_TIME_SHIFT 0
|
||||
#define SRS_PDP_PCLK_ODIV1_HI_TIME_MASK 0x00000FC0U
|
||||
#define SRS_PDP_PCLK_ODIV1_HI_TIME_SHIFT 6
|
||||
|
||||
#define SRS_PDP_P_CLK_OUT_DIVIDER_REG2 0x624
|
||||
#define SRS_PDP_PCLK_ODIV2_NOCOUNT_MASK 0x00000040U
|
||||
#define SRS_PDP_PCLK_ODIV2_NOCOUNT_SHIFT 6
|
||||
#define SRS_PDP_PCLK_ODIV2_EDGE_MASK 0x00000080U
|
||||
#define SRS_PDP_PCLK_ODIV2_EDGE_SHIFT 7
|
||||
#define SRS_PDP_PCLK_ODIV2_FRAC_MASK 0x00007C00U
|
||||
#define SRS_PDP_PCLK_ODIV2_FRAC_SHIFT 10
|
||||
|
||||
#define SRS_PDP_P_CLK_OUT_DIVIDER_REG3 0x61C
|
||||
|
||||
#define SRS_PDP_M_CLK_OUT_DIVIDER_REG1 0x628
|
||||
#define SRS_PDP_MCLK_ODIV1_LO_TIME_MASK 0x0000003FU
|
||||
#define SRS_PDP_MCLK_ODIV1_LO_TIME_SHIFT 0
|
||||
#define SRS_PDP_MCLK_ODIV1_HI_TIME_MASK 0x00000FC0U
|
||||
#define SRS_PDP_MCLK_ODIV1_HI_TIME_SHIFT 6
|
||||
|
||||
#define SRS_PDP_M_CLK_OUT_DIVIDER_REG2 0x62C
|
||||
#define SRS_PDP_MCLK_ODIV2_NOCOUNT_MASK 0x00000040U
|
||||
#define SRS_PDP_MCLK_ODIV2_NOCOUNT_SHIFT 6
|
||||
#define SRS_PDP_MCLK_ODIV2_EDGE_MASK 0x00000080U
|
||||
#define SRS_PDP_MCLK_ODIV2_EDGE_SHIFT 7
|
||||
|
||||
#define SRS_PDP_P_CLK_MULTIPLIER_REG1 0x650
|
||||
#define SRS_PDP_PCLK_MUL1_LO_TIME_MASK 0x0000003FU
|
||||
#define SRS_PDP_PCLK_MUL1_LO_TIME_SHIFT 0
|
||||
#define SRS_PDP_PCLK_MUL1_HI_TIME_MASK 0x00000FC0U
|
||||
#define SRS_PDP_PCLK_MUL1_HI_TIME_SHIFT 6
|
||||
|
||||
#define SRS_PDP_P_CLK_MULTIPLIER_REG2 0x654
|
||||
#define SRS_PDP_PCLK_MUL2_NOCOUNT_MASK 0x00000040U
|
||||
#define SRS_PDP_PCLK_MUL2_NOCOUNT_SHIFT 6
|
||||
#define SRS_PDP_PCLK_MUL2_EDGE_MASK 0x00000080U
|
||||
#define SRS_PDP_PCLK_MUL2_EDGE_SHIFT 7
|
||||
#define SRS_PDP_PCLK_MUL2_FRAC_MASK 0x00007C00U
|
||||
#define SRS_PDP_PCLK_MUL2_FRAC_SHIFT 10
|
||||
|
||||
#define SRS_PDP_P_CLK_MULTIPLIER_REG3 0x64C
|
||||
|
||||
#define SRS_PDP_P_CLK_IN_DIVIDER_REG 0x658
|
||||
#define SRS_PDP_PCLK_IDIV_LO_TIME_MASK 0x0000003FU
|
||||
#define SRS_PDP_PCLK_IDIV_LO_TIME_SHIFT 0
|
||||
#define SRS_PDP_PCLK_IDIV_HI_TIME_MASK 0x00000FC0U
|
||||
#define SRS_PDP_PCLK_IDIV_HI_TIME_SHIFT 6
|
||||
#define SRS_PDP_PCLK_IDIV_NOCOUNT_MASK 0x00001000U
|
||||
#define SRS_PDP_PCLK_IDIV_NOCOUNT_SHIFT 12
|
||||
#define SRS_PDP_PCLK_IDIV_EDGE_MASK 0x00002000U
|
||||
#define SRS_PDP_PCLK_IDIV_EDGE_SHIFT 13
|
||||
|
||||
/*
|
||||
* DUT core clock input divider, DUT reference clock input divider
|
||||
*/
|
||||
#define SRS_DUT_CORE_CLK_OUT_DIVIDER1 0x0020
|
||||
#define SRS_DUT_CORE_CLK_OUT_DIVIDER1_HI_TIME_MASK 0x00000FC0U
|
||||
#define SRS_DUT_CORE_CLK_OUT_DIVIDER1_HI_TIME_SHIFT 6
|
||||
#define SRS_DUT_CORE_CLK_OUT_DIVIDER1_LO_TIME_MASK 0x0000003FU
|
||||
#define SRS_DUT_CORE_CLK_OUT_DIVIDER1_LO_TIME_SHIFT 0
|
||||
|
||||
#define SRS_DUT_CORE_CLK_OUT_DIVIDER2 0x0024
|
||||
#define SRS_DUT_CORE_CLK_OUT_DIVIDER2_EDGE_MASK 0x00000080U
|
||||
#define SRS_DUT_CORE_CLK_OUT_DIVIDER2_EDGE_SHIFT 7
|
||||
#define SRS_DUT_CORE_CLK_OUT_DIVIDER2_NOCOUNT_MASK 0x00000040U
|
||||
#define SRS_DUT_CORE_CLK_OUT_DIVIDER2_NOCOUNT_SHIFT 6
|
||||
|
||||
#define SRS_DUT_REF_CLK_OUT_DIVIDER1 0x0028
|
||||
#define SRS_DUT_REF_CLK_OUT_DIVIDER1_HI_TIME_MASK 0x00000FC0U
|
||||
#define SRS_DUT_REF_CLK_OUT_DIVIDER1_HI_TIME_SHIFT 6
|
||||
#define SRS_DUT_REF_CLK_OUT_DIVIDER1_LO_TIME_MASK 0x0000003FU
|
||||
#define SRS_DUT_REF_CLK_OUT_DIVIDER1_LO_TIME_SHIFT 0
|
||||
|
||||
#define SRS_DUT_REF_CLK_OUT_DIVIDER2 0x002C
|
||||
#define SRS_DUT_REF_CLK_OUT_DIVIDER2_EDGE_MASK 0x00000080U
|
||||
#define SRS_DUT_REF_CLK_OUT_DIVIDER2_EDGE_SHIFT 7
|
||||
#define SRS_DUT_REF_CLK_OUT_DIVIDER2_NOCOUNT_MASK 0x00000040U
|
||||
#define SRS_DUT_REF_CLK_OUT_DIVIDER2_NOCOUNT_SHIFT 6
|
||||
|
||||
/*
|
||||
* DUT interface reference clock input divider
|
||||
*/
|
||||
|
||||
#define SRS_DUT_MEM_CLK_OUT_DIVIDER1 0x0228
|
||||
#define SRS_DUT_MEM_CLK_OUT_DIVIDER1_HI_TIME_MASK 0x00000FC0U
|
||||
#define SRS_DUT_MEM_CLK_OUT_DIVIDER1_HI_TIME_SHIFT 6
|
||||
#define SRS_DUT_MEM_CLK_OUT_DIVIDER1_LO_TIME_MASK 0x0000003FU
|
||||
#define SRS_DUT_MEM_CLK_OUT_DIVIDER1_LO_TIME_SHIFT 0
|
||||
|
||||
#define SRS_DUT_MEM_CLK_OUT_DIVIDER2 0x022C
|
||||
#define SRS_DUT_MEM_CLK_OUT_DIVIDER2_EDGE_MASK 0x00000080U
|
||||
#define SRS_DUT_MEM_CLK_OUT_DIVIDER2_EDGE_SHIFT 7
|
||||
#define SRS_DUT_MEM_CLK_OUT_DIVIDER2_NOCOUNT_MASK 0x00000040U
|
||||
#define SRS_DUT_MEM_CLK_OUT_DIVIDER2_NOCOUNT_SHIFT 6
|
||||
|
||||
/*
|
||||
* Min max values from Xilinx Virtex Ultrascale data sheet DS893,
|
||||
* for speed grade 1. All in Hz.
|
||||
*/
|
||||
#define SRS_INPUT_CLOCK_SPEED 100000000U
|
||||
#define SRS_INPUT_CLOCK_SPEED_MIN 10000000U
|
||||
#define SRS_INPUT_CLOCK_SPEED_MAX 800000000U
|
||||
#define SRS_OUTPUT_CLOCK_SPEED_MIN 4690000U
|
||||
#define SRS_OUTPUT_CLOCK_SPEED_MAX 630000000U
|
||||
#define SRS_VCO_MIN 600000000U
|
||||
#define SRS_VCO_MAX 1200000000U
|
||||
#define SRS_PFD_MIN 10000000U
|
||||
#define SRS_PFD_MAX 450000000U
|
||||
|
||||
/*
|
||||
* Orion interrupt flags
|
||||
*/
|
||||
#define SRS_INTERRUPT_ENABLE_PDP1 (1 << SRS_INTERRUPT_ENABLE_PDP_SHIFT)
|
||||
#define SRS_INTERRUPT_ENABLE_DUT (1 << SRS_INTERRUPT_ENABLE_DUT_SHIFT)
|
||||
#define SRS_INTERRUPT_STATUS_PDP1 (1 << SRS_INTERRUPT_STATUS_PDP_SHIFT)
|
||||
#define SRS_INTERRUPT_STATUS_DUT (1 << SRS_INTERRUPT_STATUS_DUT_SHIFT)
|
||||
#define SRS_INTERRUPT_CLEAR_PDP1 (1 << SRS_INTERRUPT_CLR_PDP_SHIFT)
|
||||
#define SRS_INTERRUPT_CLEAR_DUT (1 << SRS_INTERRUPT_CLR_DUT_SHIFT)
|
||||
|
||||
#endif /* _ORION_DEFS_H_ */
|
||||
|
||||
/*****************************************************************************
|
||||
End of file (orion_defs.h)
|
||||
*****************************************************************************/
|
||||
439
drivers/gpu/drm/img-rogue/include/system/rgx_tc/orion_regs.h
Normal file
439
drivers/gpu/drm/img-rogue/include/system/rgx_tc/orion_regs.h
Normal file
@@ -0,0 +1,439 @@
|
||||
/******************************************************************************
|
||||
@Title Orion system control register definitions
|
||||
@Copyright Copyright (c) Imagination Technologies Ltd. All Rights Reserved
|
||||
@Description Orion FPGA register defs for Sirius RTL
|
||||
@Author Autogenerated
|
||||
@License Dual MIT/GPLv2
|
||||
|
||||
The contents of this file are subject to the MIT license as set out below.
|
||||
|
||||
Permission is hereby granted, free of charge, to any person obtaining a copy
|
||||
of this software and associated documentation files (the "Software"), to deal
|
||||
in the Software without restriction, including without limitation the rights
|
||||
to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
|
||||
copies of the Software, and to permit persons to whom the Software is
|
||||
furnished to do so, subject to the following conditions:
|
||||
|
||||
The above copyright notice and this permission notice shall be included in
|
||||
all copies or substantial portions of the Software.
|
||||
|
||||
Alternatively, the contents of this file may be used under the terms of
|
||||
the GNU General Public License Version 2 ("GPL") in which case the provisions
|
||||
of GPL are applicable instead of those above.
|
||||
|
||||
If you wish to allow use of your version of this file only under the terms of
|
||||
GPL, and not to allow others to use your version of this file under the terms
|
||||
of the MIT license, indicate your decision by deleting the provisions above
|
||||
and replace them with the notice and other provisions required by GPL as set
|
||||
out in the file called "GPL-COPYING" included in this distribution. If you do
|
||||
not delete the provisions above, a recipient may use your version of this file
|
||||
under the terms of either the MIT license or GPL.
|
||||
|
||||
This License is also included in this distribution in the file called
|
||||
"MIT-COPYING".
|
||||
|
||||
EXCEPT AS OTHERWISE STATED IN A NEGOTIATED AGREEMENT: (A) THE SOFTWARE IS
|
||||
PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING
|
||||
BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR
|
||||
PURPOSE AND NONINFRINGEMENT; AND (B) IN NO EVENT SHALL THE AUTHORS OR
|
||||
COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
|
||||
IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
|
||||
CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
|
||||
******************************************************************************/
|
||||
|
||||
#ifndef _OUT_DRV_H_
|
||||
#define _OUT_DRV_H_
|
||||
|
||||
/*
|
||||
Register ID
|
||||
*/
|
||||
#define SRS_CORE_ID 0x0000
|
||||
#define SRS_ID_VARIANT_MASK 0x0000FFFFU
|
||||
#define SRS_ID_VARIANT_SHIFT 0
|
||||
#define SRS_ID_VARIANT_SIGNED 0
|
||||
|
||||
#define SRS_ID_ID_MASK 0xFFFF0000U
|
||||
#define SRS_ID_ID_SHIFT 16
|
||||
#define SRS_ID_ID_SIGNED 0
|
||||
|
||||
/*
|
||||
Register REVISION
|
||||
*/
|
||||
#define SRS_CORE_REVISION 0x0004
|
||||
#define SRS_REVISION_MINOR_MASK 0x000000FFU
|
||||
#define SRS_REVISION_MINOR_SHIFT 0
|
||||
#define SRS_REVISION_MINOR_SIGNED 0
|
||||
|
||||
#define SRS_REVISION_MAJOR_MASK 0x00000F00U
|
||||
#define SRS_REVISION_MAJOR_SHIFT 8
|
||||
#define SRS_REVISION_MAJOR_SIGNED 0
|
||||
|
||||
/*
|
||||
Register CHANGE_SET
|
||||
*/
|
||||
#define SRS_CORE_CHANGE_SET 0x0008
|
||||
#define SRS_CHANGE_SET_SET_MASK 0xFFFFFFFFU
|
||||
#define SRS_CHANGE_SET_SET_SHIFT 0
|
||||
#define SRS_CHANGE_SET_SET_SIGNED 0
|
||||
|
||||
/*
|
||||
Register USER_ID
|
||||
*/
|
||||
#define SRS_CORE_USER_ID 0x000C
|
||||
#define SRS_USER_ID_ID_MASK 0x0000000FU
|
||||
#define SRS_USER_ID_ID_SHIFT 0
|
||||
#define SRS_USER_ID_ID_SIGNED 0
|
||||
|
||||
/*
|
||||
Register USER_BUILD
|
||||
*/
|
||||
#define SRS_CORE_USER_BUILD 0x0010
|
||||
#define SRS_USER_BUILD_BUILD_MASK 0xFFFFFFFFU
|
||||
#define SRS_USER_BUILD_BUILD_SHIFT 0
|
||||
#define SRS_USER_BUILD_BUILD_SIGNED 0
|
||||
|
||||
/*
|
||||
Register SOFT_RESETN
|
||||
*/
|
||||
#define SRS_CORE_SOFT_RESETN 0x0080
|
||||
#define SRS_SOFT_RESETN_DDR_MASK 0x00000001U
|
||||
#define SRS_SOFT_RESETN_DDR_SHIFT 0
|
||||
#define SRS_SOFT_RESETN_DDR_SIGNED 0
|
||||
|
||||
#define SRS_SOFT_RESETN_USB_MASK 0x00000002U
|
||||
#define SRS_SOFT_RESETN_USB_SHIFT 1
|
||||
#define SRS_SOFT_RESETN_USB_SIGNED 0
|
||||
|
||||
#define SRS_SOFT_RESETN_PDP_MASK 0x00000004U
|
||||
#define SRS_SOFT_RESETN_PDP_SHIFT 2
|
||||
#define SRS_SOFT_RESETN_PDP_SIGNED 0
|
||||
|
||||
#define SRS_SOFT_RESETN_GIST_MASK 0x00000008U
|
||||
#define SRS_SOFT_RESETN_GIST_SHIFT 3
|
||||
#define SRS_SOFT_RESETN_GIST_SIGNED 0
|
||||
|
||||
/*
|
||||
Register DUT_SOFT_RESETN
|
||||
*/
|
||||
#define SRS_CORE_DUT_SOFT_RESETN 0x0084
|
||||
#define SRS_DUT_SOFT_RESETN_EXTERNAL_MASK 0x00000001U
|
||||
#define SRS_DUT_SOFT_RESETN_EXTERNAL_SHIFT 0
|
||||
#define SRS_DUT_SOFT_RESETN_EXTERNAL_SIGNED 0
|
||||
|
||||
/*
|
||||
Register SOFT_AUTO_RESETN
|
||||
*/
|
||||
#define SRS_CORE_SOFT_AUTO_RESETN 0x0088
|
||||
#define SRS_SOFT_AUTO_RESETN_CFG_MASK 0x00000001U
|
||||
#define SRS_SOFT_AUTO_RESETN_CFG_SHIFT 0
|
||||
#define SRS_SOFT_AUTO_RESETN_CFG_SIGNED 0
|
||||
|
||||
/*
|
||||
Register CLK_GEN_RESET
|
||||
*/
|
||||
#define SRS_CORE_CLK_GEN_RESET 0x0090
|
||||
#define SRS_CLK_GEN_RESET_DUT_CORE_MMCM_MASK 0x00000001U
|
||||
#define SRS_CLK_GEN_RESET_DUT_CORE_MMCM_SHIFT 0
|
||||
#define SRS_CLK_GEN_RESET_DUT_CORE_MMCM_SIGNED 0
|
||||
|
||||
#define SRS_CLK_GEN_RESET_DUT_IF_MMCM_MASK 0x00000002U
|
||||
#define SRS_CLK_GEN_RESET_DUT_IF_MMCM_SHIFT 1
|
||||
#define SRS_CLK_GEN_RESET_DUT_IF_MMCM_SIGNED 0
|
||||
|
||||
#define SRS_CLK_GEN_RESET_MULTI_MMCM_MASK 0x00000004U
|
||||
#define SRS_CLK_GEN_RESET_MULTI_MMCM_SHIFT 2
|
||||
#define SRS_CLK_GEN_RESET_MULTI_MMCM_SIGNED 0
|
||||
|
||||
#define SRS_CLK_GEN_RESET_PDP_MMCM_MASK 0x00000008U
|
||||
#define SRS_CLK_GEN_RESET_PDP_MMCM_SHIFT 3
|
||||
#define SRS_CLK_GEN_RESET_PDP_MMCM_SIGNED 0
|
||||
|
||||
/*
|
||||
Register DUT_MEM
|
||||
*/
|
||||
#define SRS_CORE_DUT_MEM 0x0120
|
||||
#define SRS_DUT_MEM_READ_RESPONSE_LATENCY_MASK 0x0000FFFFU
|
||||
#define SRS_DUT_MEM_READ_RESPONSE_LATENCY_SHIFT 0
|
||||
#define SRS_DUT_MEM_READ_RESPONSE_LATENCY_SIGNED 0
|
||||
|
||||
#define SRS_DUT_MEM_WRITE_RESPONSE_LATENCY_MASK 0xFFFF0000U
|
||||
#define SRS_DUT_MEM_WRITE_RESPONSE_LATENCY_SHIFT 16
|
||||
#define SRS_DUT_MEM_WRITE_RESPONSE_LATENCY_SIGNED 0
|
||||
|
||||
/*
|
||||
Register APM
|
||||
*/
|
||||
#define SRS_CORE_APM 0x0150
|
||||
#define SRS_APM_RESET_EVENT_MASK 0x00000001U
|
||||
#define SRS_APM_RESET_EVENT_SHIFT 0
|
||||
#define SRS_APM_RESET_EVENT_SIGNED 0
|
||||
|
||||
#define SRS_APM_CAPTURE_EVENT_MASK 0x00000002U
|
||||
#define SRS_APM_CAPTURE_EVENT_SHIFT 1
|
||||
#define SRS_APM_CAPTURE_EVENT_SIGNED 0
|
||||
|
||||
/*
|
||||
Register NUM_GPIO
|
||||
*/
|
||||
#define SRS_CORE_NUM_GPIO 0x0180
|
||||
#define SRS_NUM_GPIO_NUMBER_MASK 0x0000000FU
|
||||
#define SRS_NUM_GPIO_NUMBER_SHIFT 0
|
||||
#define SRS_NUM_GPIO_NUMBER_SIGNED 0
|
||||
|
||||
/*
|
||||
Register GPIO_EN
|
||||
*/
|
||||
#define SRS_CORE_GPIO_EN 0x0184
|
||||
#define SRS_GPIO_EN_DIRECTION_MASK 0x000000FFU
|
||||
#define SRS_GPIO_EN_DIRECTION_SHIFT 0
|
||||
#define SRS_GPIO_EN_DIRECTION_SIGNED 0
|
||||
|
||||
/*
|
||||
Register GPIO
|
||||
*/
|
||||
#define SRS_CORE_GPIO 0x0188
|
||||
#define SRS_GPIO_GPIO_MASK 0x000000FFU
|
||||
#define SRS_GPIO_GPIO_SHIFT 0
|
||||
#define SRS_GPIO_GPIO_SIGNED 0
|
||||
|
||||
/*
|
||||
Register SPI_MASTER_IFACE
|
||||
*/
|
||||
#define SRS_CORE_SPI_MASTER_IFACE 0x018C
|
||||
#define SRS_SPI_MASTER_IFACE_ENABLE_MASK 0x00000001U
|
||||
#define SRS_SPI_MASTER_IFACE_ENABLE_SHIFT 0
|
||||
#define SRS_SPI_MASTER_IFACE_ENABLE_SIGNED 0
|
||||
|
||||
/*
|
||||
Register SRS_IP_STATUS
|
||||
*/
|
||||
#define SRS_CORE_SRS_IP_STATUS 0x0200
|
||||
#define SRS_SRS_IP_STATUS_PCIE_USER_LNK_UP_MASK 0x00000001U
|
||||
#define SRS_SRS_IP_STATUS_PCIE_USER_LNK_UP_SHIFT 0
|
||||
#define SRS_SRS_IP_STATUS_PCIE_USER_LNK_UP_SIGNED 0
|
||||
|
||||
#define SRS_SRS_IP_STATUS_MIG_INIT_CALIB_COMPLETE_MASK 0x00000002U
|
||||
#define SRS_SRS_IP_STATUS_MIG_INIT_CALIB_COMPLETE_SHIFT 1
|
||||
#define SRS_SRS_IP_STATUS_MIG_INIT_CALIB_COMPLETE_SIGNED 0
|
||||
|
||||
#define SRS_SRS_IP_STATUS_GIST_SLV_C2C_CONFIG_ERROR_OUT_MASK 0x00000004U
|
||||
#define SRS_SRS_IP_STATUS_GIST_SLV_C2C_CONFIG_ERROR_OUT_SHIFT 2
|
||||
#define SRS_SRS_IP_STATUS_GIST_SLV_C2C_CONFIG_ERROR_OUT_SIGNED 0
|
||||
|
||||
#define SRS_SRS_IP_STATUS_GIST_MST_C2C_CONFIG_ERROR_OUT_MASK 0x00000008U
|
||||
#define SRS_SRS_IP_STATUS_GIST_MST_C2C_CONFIG_ERROR_OUT_SHIFT 3
|
||||
#define SRS_SRS_IP_STATUS_GIST_MST_C2C_CONFIG_ERROR_OUT_SIGNED 0
|
||||
|
||||
/*
|
||||
Register CORE_CONTROL
|
||||
*/
|
||||
#define SRS_CORE_CORE_CONTROL 0x0204
|
||||
#define SRS_CORE_CONTROL_BAR4_OFFSET_MASK 0x0000001FU
|
||||
#define SRS_CORE_CONTROL_BAR4_OFFSET_SHIFT 0
|
||||
#define SRS_CORE_CONTROL_BAR4_OFFSET_SIGNED 0
|
||||
|
||||
#define SRS_CORE_CONTROL_HDMI_MONITOR_OVERRIDE_MASK 0x00000300U
|
||||
#define SRS_CORE_CONTROL_HDMI_MONITOR_OVERRIDE_SHIFT 8
|
||||
#define SRS_CORE_CONTROL_HDMI_MONITOR_OVERRIDE_SIGNED 0
|
||||
|
||||
#define SRS_CORE_CONTROL_HDMI_MODULE_EN_MASK 0x00001C00U
|
||||
#define SRS_CORE_CONTROL_HDMI_MODULE_EN_SHIFT 10
|
||||
#define SRS_CORE_CONTROL_HDMI_MODULE_EN_SIGNED 0
|
||||
|
||||
/*
|
||||
Register REG_BANK_STATUS
|
||||
*/
|
||||
#define SRS_CORE_REG_BANK_STATUS 0x0208
|
||||
#define SRS_REG_BANK_STATUS_ARB_SLV_RD_TIMEOUT_MASK 0xFFFFFFFFU
|
||||
#define SRS_REG_BANK_STATUS_ARB_SLV_RD_TIMEOUT_SHIFT 0
|
||||
#define SRS_REG_BANK_STATUS_ARB_SLV_RD_TIMEOUT_SIGNED 0
|
||||
|
||||
/*
|
||||
Register MMCM_LOCK_STATUS
|
||||
*/
|
||||
#define SRS_CORE_MMCM_LOCK_STATUS 0x020C
|
||||
#define SRS_MMCM_LOCK_STATUS_DUT_CORE_MASK 0x00000001U
|
||||
#define SRS_MMCM_LOCK_STATUS_DUT_CORE_SHIFT 0
|
||||
#define SRS_MMCM_LOCK_STATUS_DUT_CORE_SIGNED 0
|
||||
|
||||
#define SRS_MMCM_LOCK_STATUS_DUT_IF_MASK 0x00000002U
|
||||
#define SRS_MMCM_LOCK_STATUS_DUT_IF_SHIFT 1
|
||||
#define SRS_MMCM_LOCK_STATUS_DUT_IF_SIGNED 0
|
||||
|
||||
#define SRS_MMCM_LOCK_STATUS_MULTI_MASK 0x00000004U
|
||||
#define SRS_MMCM_LOCK_STATUS_MULTI_SHIFT 2
|
||||
#define SRS_MMCM_LOCK_STATUS_MULTI_SIGNED 0
|
||||
|
||||
#define SRS_MMCM_LOCK_STATUS_PDP_MASK 0x00000008U
|
||||
#define SRS_MMCM_LOCK_STATUS_PDP_SHIFT 3
|
||||
#define SRS_MMCM_LOCK_STATUS_PDP_SIGNED 0
|
||||
|
||||
/*
|
||||
Register GIST_STATUS
|
||||
*/
|
||||
#define SRS_CORE_GIST_STATUS 0x0210
|
||||
#define SRS_GIST_STATUS_MST_MASK 0x000001FFU
|
||||
#define SRS_GIST_STATUS_MST_SHIFT 0
|
||||
#define SRS_GIST_STATUS_MST_SIGNED 0
|
||||
|
||||
#define SRS_GIST_STATUS_SLV_MASK 0x001FF000U
|
||||
#define SRS_GIST_STATUS_SLV_SHIFT 12
|
||||
#define SRS_GIST_STATUS_SLV_SIGNED 0
|
||||
|
||||
#define SRS_GIST_STATUS_SLV_OUT_MASK 0x03000000U
|
||||
#define SRS_GIST_STATUS_SLV_OUT_SHIFT 24
|
||||
#define SRS_GIST_STATUS_SLV_OUT_SIGNED 0
|
||||
|
||||
#define SRS_GIST_STATUS_MST_OUT_MASK 0x70000000U
|
||||
#define SRS_GIST_STATUS_MST_OUT_SHIFT 28
|
||||
#define SRS_GIST_STATUS_MST_OUT_SIGNED 0
|
||||
|
||||
/*
|
||||
Register SENSOR_BOARD
|
||||
*/
|
||||
#define SRS_CORE_SENSOR_BOARD 0x0214
|
||||
#define SRS_SENSOR_BOARD_ID_MASK 0x00000003U
|
||||
#define SRS_SENSOR_BOARD_ID_SHIFT 0
|
||||
#define SRS_SENSOR_BOARD_ID_SIGNED 0
|
||||
|
||||
/*
|
||||
Register INTERRUPT_STATUS
|
||||
*/
|
||||
#define SRS_CORE_INTERRUPT_STATUS 0x0218
|
||||
#define SRS_INTERRUPT_STATUS_DUT_MASK 0x00000001U
|
||||
#define SRS_INTERRUPT_STATUS_DUT_SHIFT 0
|
||||
#define SRS_INTERRUPT_STATUS_DUT_SIGNED 0
|
||||
|
||||
#define SRS_INTERRUPT_STATUS_PDP_MASK 0x00000002U
|
||||
#define SRS_INTERRUPT_STATUS_PDP_SHIFT 1
|
||||
#define SRS_INTERRUPT_STATUS_PDP_SIGNED 0
|
||||
|
||||
#define SRS_INTERRUPT_STATUS_I2C_MASK 0x00000004U
|
||||
#define SRS_INTERRUPT_STATUS_I2C_SHIFT 2
|
||||
#define SRS_INTERRUPT_STATUS_I2C_SIGNED 0
|
||||
|
||||
#define SRS_INTERRUPT_STATUS_SPI_MASK 0x00000008U
|
||||
#define SRS_INTERRUPT_STATUS_SPI_SHIFT 3
|
||||
#define SRS_INTERRUPT_STATUS_SPI_SIGNED 0
|
||||
|
||||
#define SRS_INTERRUPT_STATUS_APM_MASK 0x00000010U
|
||||
#define SRS_INTERRUPT_STATUS_APM_SHIFT 4
|
||||
#define SRS_INTERRUPT_STATUS_APM_SIGNED 0
|
||||
|
||||
#define SRS_INTERRUPT_STATUS_OS_IRQ_MASK 0x00001FE0U
|
||||
#define SRS_INTERRUPT_STATUS_OS_IRQ_SHIFT 5
|
||||
#define SRS_INTERRUPT_STATUS_OS_IRQ_SIGNED 0
|
||||
|
||||
#define SRS_INTERRUPT_STATUS_IRQ_TEST_MASK 0x40000000U
|
||||
#define SRS_INTERRUPT_STATUS_IRQ_TEST_SHIFT 30
|
||||
#define SRS_INTERRUPT_STATUS_IRQ_TEST_SIGNED 0
|
||||
|
||||
#define SRS_INTERRUPT_STATUS_MASTER_STATUS_MASK 0x80000000U
|
||||
#define SRS_INTERRUPT_STATUS_MASTER_STATUS_SHIFT 31
|
||||
#define SRS_INTERRUPT_STATUS_MASTER_STATUS_SIGNED 0
|
||||
|
||||
/*
|
||||
Register INTERRUPT_ENABLE
|
||||
*/
|
||||
#define SRS_CORE_INTERRUPT_ENABLE 0x021C
|
||||
#define SRS_INTERRUPT_ENABLE_DUT_MASK 0x00000001U
|
||||
#define SRS_INTERRUPT_ENABLE_DUT_SHIFT 0
|
||||
#define SRS_INTERRUPT_ENABLE_DUT_SIGNED 0
|
||||
|
||||
#define SRS_INTERRUPT_ENABLE_PDP_MASK 0x00000002U
|
||||
#define SRS_INTERRUPT_ENABLE_PDP_SHIFT 1
|
||||
#define SRS_INTERRUPT_ENABLE_PDP_SIGNED 0
|
||||
|
||||
#define SRS_INTERRUPT_ENABLE_I2C_MASK 0x00000004U
|
||||
#define SRS_INTERRUPT_ENABLE_I2C_SHIFT 2
|
||||
#define SRS_INTERRUPT_ENABLE_I2C_SIGNED 0
|
||||
|
||||
#define SRS_INTERRUPT_ENABLE_SPI_MASK 0x00000008U
|
||||
#define SRS_INTERRUPT_ENABLE_SPI_SHIFT 3
|
||||
#define SRS_INTERRUPT_ENABLE_SPI_SIGNED 0
|
||||
|
||||
#define SRS_INTERRUPT_ENABLE_APM_MASK 0x00000010U
|
||||
#define SRS_INTERRUPT_ENABLE_APM_SHIFT 4
|
||||
#define SRS_INTERRUPT_ENABLE_APM_SIGNED 0
|
||||
|
||||
#define SRS_INTERRUPT_ENABLE_OS_IRQ_MASK 0x00001FE0U
|
||||
#define SRS_INTERRUPT_ENABLE_OS_IRQ_SHIFT 5
|
||||
#define SRS_INTERRUPT_ENABLE_OS_IRQ_SIGNED 0
|
||||
|
||||
#define SRS_INTERRUPT_ENABLE_IRQ_TEST_MASK 0x40000000U
|
||||
#define SRS_INTERRUPT_ENABLE_IRQ_TEST_SHIFT 30
|
||||
#define SRS_INTERRUPT_ENABLE_IRQ_TEST_SIGNED 0
|
||||
|
||||
#define SRS_INTERRUPT_ENABLE_MASTER_ENABLE_MASK 0x80000000U
|
||||
#define SRS_INTERRUPT_ENABLE_MASTER_ENABLE_SHIFT 31
|
||||
#define SRS_INTERRUPT_ENABLE_MASTER_ENABLE_SIGNED 0
|
||||
|
||||
/*
|
||||
Register INTERRUPT_CLR
|
||||
*/
|
||||
#define SRS_CORE_INTERRUPT_CLR 0x0220
|
||||
#define SRS_INTERRUPT_CLR_DUT_MASK 0x00000001U
|
||||
#define SRS_INTERRUPT_CLR_DUT_SHIFT 0
|
||||
#define SRS_INTERRUPT_CLR_DUT_SIGNED 0
|
||||
|
||||
#define SRS_INTERRUPT_CLR_PDP_MASK 0x00000002U
|
||||
#define SRS_INTERRUPT_CLR_PDP_SHIFT 1
|
||||
#define SRS_INTERRUPT_CLR_PDP_SIGNED 0
|
||||
|
||||
#define SRS_INTERRUPT_CLR_I2C_MASK 0x00000004U
|
||||
#define SRS_INTERRUPT_CLR_I2C_SHIFT 2
|
||||
#define SRS_INTERRUPT_CLR_I2C_SIGNED 0
|
||||
|
||||
#define SRS_INTERRUPT_CLR_SPI_MASK 0x00000008U
|
||||
#define SRS_INTERRUPT_CLR_SPI_SHIFT 3
|
||||
#define SRS_INTERRUPT_CLR_SPI_SIGNED 0
|
||||
|
||||
#define SRS_INTERRUPT_CLR_APM_MASK 0x00000010U
|
||||
#define SRS_INTERRUPT_CLR_APM_SHIFT 4
|
||||
#define SRS_INTERRUPT_CLR_APM_SIGNED 0
|
||||
|
||||
#define SRS_INTERRUPT_CLR_OS_IRQ_MASK 0x00001FE0U
|
||||
#define SRS_INTERRUPT_CLR_OS_IRQ_SHIFT 5
|
||||
#define SRS_INTERRUPT_CLR_OS_IRQ_SIGNED 0
|
||||
|
||||
#define SRS_INTERRUPT_CLR_IRQ_TEST_MASK 0x40000000U
|
||||
#define SRS_INTERRUPT_CLR_IRQ_TEST_SHIFT 30
|
||||
#define SRS_INTERRUPT_CLR_IRQ_TEST_SIGNED 0
|
||||
|
||||
#define SRS_INTERRUPT_CLR_MASTER_CLEAR_MASK 0x80000000U
|
||||
#define SRS_INTERRUPT_CLR_MASTER_CLEAR_SHIFT 31
|
||||
#define SRS_INTERRUPT_CLR_MASTER_CLEAR_SIGNED 0
|
||||
|
||||
/*
|
||||
Register INTERRUPT_TEST
|
||||
*/
|
||||
#define SRS_CORE_INTERRUPT_TEST 0x0224
|
||||
#define SRS_INTERRUPT_TEST_INTERRUPT_TEST_MASK 0x00000001U
|
||||
#define SRS_INTERRUPT_TEST_INTERRUPT_TEST_SHIFT 0
|
||||
#define SRS_INTERRUPT_TEST_INTERRUPT_TEST_SIGNED 0
|
||||
|
||||
/*
|
||||
Register INTERRUPT_TIMEOUT_CLR
|
||||
*/
|
||||
#define SRS_CORE_INTERRUPT_TIMEOUT_CLR 0x0228
|
||||
#define SRS_INTERRUPT_TIMEOUT_CLR_INTERRUPT_MST_TIMEOUT_CLR_MASK 0x00000002U
|
||||
#define SRS_INTERRUPT_TIMEOUT_CLR_INTERRUPT_MST_TIMEOUT_CLR_SHIFT 1
|
||||
#define SRS_INTERRUPT_TIMEOUT_CLR_INTERRUPT_MST_TIMEOUT_CLR_SIGNED 0
|
||||
|
||||
#define SRS_INTERRUPT_TIMEOUT_CLR_INTERRUPT_MST_TIMEOUT_MASK 0x00000001U
|
||||
#define SRS_INTERRUPT_TIMEOUT_CLR_INTERRUPT_MST_TIMEOUT_SHIFT 0
|
||||
#define SRS_INTERRUPT_TIMEOUT_CLR_INTERRUPT_MST_TIMEOUT_SIGNED 0
|
||||
|
||||
/*
|
||||
Register INTERRUPT_TIMEOUT
|
||||
*/
|
||||
#define SRS_CORE_INTERRUPT_TIMEOUT 0x022C
|
||||
#define SRS_INTERRUPT_TIMEOUT_INTERRUPT_TIMEOUT_THRESHOLD_COUNTER_MASK 0xFFFFFFFFU
|
||||
#define SRS_INTERRUPT_TIMEOUT_INTERRUPT_TIMEOUT_THRESHOLD_COUNTER_SHIFT 0
|
||||
#define SRS_INTERRUPT_TIMEOUT_INTERRUPT_TIMEOUT_THRESHOLD_COUNTER_SIGNED 0
|
||||
|
||||
#endif /* _OUT_DRV_H_ */
|
||||
|
||||
/******************************************************************************
|
||||
End of file (orion_regs.h)
|
||||
******************************************************************************/
|
||||
75
drivers/gpu/drm/img-rogue/include/system/rgx_tc/pdp_regs.h
Normal file
75
drivers/gpu/drm/img-rogue/include/system/rgx_tc/pdp_regs.h
Normal file
@@ -0,0 +1,75 @@
|
||||
/*************************************************************************/ /*!
|
||||
@Copyright Copyright (c) Imagination Technologies Ltd. All Rights Reserved
|
||||
@License Dual MIT/GPLv2
|
||||
|
||||
The contents of this file are subject to the MIT license as set out below.
|
||||
|
||||
Permission is hereby granted, free of charge, to any person obtaining a copy
|
||||
of this software and associated documentation files (the "Software"), to deal
|
||||
in the Software without restriction, including without limitation the rights
|
||||
to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
|
||||
copies of the Software, and to permit persons to whom the Software is
|
||||
furnished to do so, subject to the following conditions:
|
||||
|
||||
The above copyright notice and this permission notice shall be included in
|
||||
all copies or substantial portions of the Software.
|
||||
|
||||
Alternatively, the contents of this file may be used under the terms of
|
||||
the GNU General Public License Version 2 ("GPL") in which case the provisions
|
||||
of GPL are applicable instead of those above.
|
||||
|
||||
If you wish to allow use of your version of this file only under the terms of
|
||||
GPL, and not to allow others to use your version of this file under the terms
|
||||
of the MIT license, indicate your decision by deleting the provisions above
|
||||
and replace them with the notice and other provisions required by GPL as set
|
||||
out in the file called "GPL-COPYING" included in this distribution. If you do
|
||||
not delete the provisions above, a recipient may use your version of this file
|
||||
under the terms of either the MIT license or GPL.
|
||||
|
||||
This License is also included in this distribution in the file called
|
||||
"MIT-COPYING".
|
||||
|
||||
EXCEPT AS OTHERWISE STATED IN A NEGOTIATED AGREEMENT: (A) THE SOFTWARE IS
|
||||
PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING
|
||||
BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR
|
||||
PURPOSE AND NONINFRINGEMENT; AND (B) IN NO EVENT SHALL THE AUTHORS OR
|
||||
COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
|
||||
IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
|
||||
CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
|
||||
*/ /**************************************************************************/
|
||||
|
||||
#if !defined(__PDP_REGS_H__)
|
||||
#define __PDP_REGS_H__
|
||||
|
||||
/*************************************************************************/ /*!
|
||||
PCI Device Information
|
||||
*/ /**************************************************************************/
|
||||
|
||||
#define DCPDP_VENDOR_ID_POWERVR (0x1010)
|
||||
|
||||
#define DCPDP_DEVICE_ID_PCI_APOLLO_FPGA (0x1CF1)
|
||||
#define DCPDP_DEVICE_ID_PCIE_APOLLO_FPGA (0x1CF2)
|
||||
|
||||
/*************************************************************************/ /*!
|
||||
PCI Device Base Address Information
|
||||
*/ /**************************************************************************/
|
||||
|
||||
/* PLL and PDP registers on base address register 0 */
|
||||
#define DCPDP_REG_PCI_BASENUM (0)
|
||||
|
||||
#define DCPDP_PCI_PLL_REG_OFFSET (0x1000)
|
||||
#define DCPDP_PCI_PLL_REG_SIZE (0x0400)
|
||||
|
||||
#define DCPDP_PCI_PDP_REG_OFFSET (0xC000)
|
||||
#define DCPDP_PCI_PDP_REG_SIZE (0x2000)
|
||||
|
||||
/*************************************************************************/ /*!
|
||||
Misc register information
|
||||
*/ /**************************************************************************/
|
||||
|
||||
/* This information isn't captured in tcf_rgbpdp_regs.h so define it here */
|
||||
#define DCPDP_STR1SURF_FORMAT_ARGB8888 (0xE)
|
||||
#define DCPDP_STR1ADDRCTRL_BASE_ADDR_SHIFT (4)
|
||||
#define DCPDP_STR1POSN_STRIDE_SHIFT (4)
|
||||
|
||||
#endif /* !defined(__PDP_REGS_H__) */
|
||||
69
drivers/gpu/drm/img-rogue/include/system/rgx_tc/pfim_defs.h
Normal file
69
drivers/gpu/drm/img-rogue/include/system/rgx_tc/pfim_defs.h
Normal file
@@ -0,0 +1,69 @@
|
||||
/******************************************************************************
|
||||
@Title Odin PFIM definitions
|
||||
@Copyright Copyright (c) Imagination Technologies Ltd. All Rights Reserved
|
||||
@Description Odin register defs for PDP-FBDC Interface Module
|
||||
@License Dual MIT/GPLv2
|
||||
|
||||
The contents of this file are subject to the MIT license as set out below.
|
||||
|
||||
Permission is hereby granted, free of charge, to any person obtaining a copy
|
||||
of this software and associated documentation files (the "Software"), to deal
|
||||
in the Software without restriction, including without limitation the rights
|
||||
to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
|
||||
copies of the Software, and to permit persons to whom the Software is
|
||||
furnished to do so, subject to the following conditions:
|
||||
|
||||
The above copyright notice and this permission notice shall be included in
|
||||
all copies or substantial portions of the Software.
|
||||
|
||||
Alternatively, the contents of this file may be used under the terms of
|
||||
the GNU General Public License Version 2 ("GPL") in which case the provisions
|
||||
of GPL are applicable instead of those above.
|
||||
|
||||
If you wish to allow use of your version of this file only under the terms of
|
||||
GPL, and not to allow others to use your version of this file under the terms
|
||||
of the MIT license, indicate your decision by deleting the provisions above
|
||||
and replace them with the notice and other provisions required by GPL as set
|
||||
out in the file called "GPL-COPYING" included in this distribution. If you do
|
||||
not delete the provisions above, a recipient may use your version of this file
|
||||
under the terms of either the MIT license or GPL.
|
||||
|
||||
This License is also included in this distribution in the file called
|
||||
"MIT-COPYING".
|
||||
|
||||
EXCEPT AS OTHERWISE STATED IN A NEGOTIATED AGREEMENT: (A) THE SOFTWARE IS
|
||||
PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING
|
||||
BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR
|
||||
PURPOSE AND NONINFRINGEMENT; AND (B) IN NO EVENT SHALL THE AUTHORS OR
|
||||
COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
|
||||
IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
|
||||
CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
|
||||
******************************************************************************/
|
||||
|
||||
#ifndef _PFIM_DEFS_H_
|
||||
#define _PFIM_DEFS_H_
|
||||
|
||||
/* Supported FBC modes */
|
||||
#define ODIN_PFIM_MOD_LINEAR (0x00)
|
||||
#define ODIN_PFIM_FBCDC_8X8_V12 (0x01)
|
||||
#define ODIN_PFIM_FBCDC_16X4_V12 (0x02)
|
||||
#define ODIN_PFIM_FBCDC_MAX (0x03)
|
||||
|
||||
/* Supported pixel formats */
|
||||
#define ODN_PFIM_PIXFMT_NONE (0x00)
|
||||
#define ODN_PFIM_PIXFMT_ARGB8888 (0x0C)
|
||||
#define ODN_PFIM_PIXFMT_RGB565 (0x05)
|
||||
|
||||
/* Tile types */
|
||||
#define ODN_PFIM_TILETYPE_8X8 (0x01)
|
||||
#define ODN_PFIM_TILETYPE_16X4 (0x02)
|
||||
#define ODN_PFIM_TILETYPE_32x2 (0x03)
|
||||
|
||||
#define PFIM_ROUNDUP(X, Y) (((X) + ((Y) - 1U)) & ~((Y) - 1U))
|
||||
#define PFIM_RND_TAG (0x10)
|
||||
|
||||
#endif /* _PFIM_DEFS_H_ */
|
||||
|
||||
/******************************************************************************
|
||||
End of file (pfim_defs.h)
|
||||
******************************************************************************/
|
||||
265
drivers/gpu/drm/img-rogue/include/system/rgx_tc/pfim_regs.h
Normal file
265
drivers/gpu/drm/img-rogue/include/system/rgx_tc/pfim_regs.h
Normal file
@@ -0,0 +1,265 @@
|
||||
/******************************************************************************
|
||||
@Title Odin PFIM control register definitions
|
||||
@Copyright Copyright (c) Imagination Technologies Ltd. All Rights Reserved
|
||||
@Description Odin register defs for PDP-FBDC Interface Module
|
||||
@License Dual MIT/GPLv2
|
||||
|
||||
The contents of this file are subject to the MIT license as set out below.
|
||||
|
||||
Permission is hereby granted, free of charge, to any person obtaining a copy
|
||||
of this software and associated documentation files (the "Software"), to deal
|
||||
in the Software without restriction, including without limitation the rights
|
||||
to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
|
||||
copies of the Software, and to permit persons to whom the Software is
|
||||
furnished to do so, subject to the following conditions:
|
||||
|
||||
The above copyright notice and this permission notice shall be included in
|
||||
all copies or substantial portions of the Software.
|
||||
|
||||
Alternatively, the contents of this file may be used under the terms of
|
||||
the GNU General Public License Version 2 ("GPL") in which case the provisions
|
||||
of GPL are applicable instead of those above.
|
||||
|
||||
If you wish to allow use of your version of this file only under the terms of
|
||||
GPL, and not to allow others to use your version of this file under the terms
|
||||
of the MIT license, indicate your decision by deleting the provisions above
|
||||
and replace them with the notice and other provisions required by GPL as set
|
||||
out in the file called "GPL-COPYING" included in this distribution. If you do
|
||||
not delete the provisions above, a recipient may use your version of this file
|
||||
under the terms of either the MIT license or GPL.
|
||||
|
||||
This License is also included in this distribution in the file called
|
||||
"MIT-COPYING".
|
||||
|
||||
EXCEPT AS OTHERWISE STATED IN A NEGOTIATED AGREEMENT: (A) THE SOFTWARE IS
|
||||
PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING
|
||||
BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR
|
||||
PURPOSE AND NONINFRINGEMENT; AND (B) IN NO EVENT SHALL THE AUTHORS OR
|
||||
COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
|
||||
IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
|
||||
CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
|
||||
******************************************************************************/
|
||||
#ifndef _PFIM_REGS_H_
|
||||
#define _PFIM_REGS_H_
|
||||
|
||||
/*
|
||||
Register CR_PFIM_NUM_TILES
|
||||
*/
|
||||
#define CR_PFIM_NUM_TILES 0x0000
|
||||
#define CR_PFIM_NUM_TILES_MASK 0x007FFFFFU
|
||||
#define CR_PFIM_NUM_TILES_SHIFT 0
|
||||
#define CR_PFIM_NUM_TILES_SIGNED 0
|
||||
|
||||
/*
|
||||
Register CR_PFIM_TILES_PER_LINE
|
||||
*/
|
||||
#define CR_PFIM_TILES_PER_LINE 0x0004
|
||||
#define CR_PFIM_TILES_PER_LINE_PFIM_TILES_PER_LINE_MASK 0x000000FFU
|
||||
#define CR_PFIM_TILES_PER_LINE_PFIM_TILES_PER_LINE_SHIFT 0
|
||||
#define CR_PFIM_TILES_PER_LINE_PFIM_TILES_PER_LINE_SIGNED 0
|
||||
|
||||
/*
|
||||
Register CR_PFIM_FBDC_YARGB_BASE_ADDR_LSB
|
||||
*/
|
||||
#define CR_PFIM_FBDC_YARGB_BASE_ADDR_LSB 0x0008
|
||||
#define CR_PFIM_FBDC_YARGB_BASE_ADDR_LSB_MASK 0xFFFFFFFFU
|
||||
#define CR_PFIM_FBDC_YARGB_BASE_ADDR_LSB_SHIFT 0
|
||||
#define CR_PFIM_FBDC_YARGB_BASE_ADDR_LSB_SIGNED 0
|
||||
|
||||
/*
|
||||
Register CR_PFIM_FBDC_YARGB_BASE_ADDR_MSB
|
||||
*/
|
||||
#define CR_PFIM_FBDC_YARGB_BASE_ADDR_MSB 0x000C
|
||||
#define CR_PFIM_FBDC_YARGB_BASE_ADDR_MSB_MASK 0x00000003U
|
||||
#define CR_PFIM_FBDC_YARGB_BASE_ADDR_MSB_SHIFT 0
|
||||
#define CR_PFIM_FBDC_YARGB_BASE_ADDR_MSB_SIGNED 0
|
||||
|
||||
/*
|
||||
Register CR_PFIM_FBDC_UV_BASE_ADDR_LSB
|
||||
*/
|
||||
#define CR_PFIM_FBDC_UV_BASE_ADDR_LSB 0x0010
|
||||
#define CR_PFIM_FBDC_UV_BASE_ADDR_LSB_MASK 0xFFFFFFFFU
|
||||
#define CR_PFIM_FBDC_UV_BASE_ADDR_LSB_SHIFT 0
|
||||
#define CR_PFIM_FBDC_UV_BASE_ADDR_LSB_SIGNED 0
|
||||
|
||||
/*
|
||||
Register CR_PFIM_FBDC_UV_BASE_ADDR_MSB
|
||||
*/
|
||||
#define CR_PFIM_FBDC_UV_BASE_ADDR_MSB 0x0014
|
||||
#define CR_PFIM_FBDC_UV_BASE_ADDR_MSB_MASK 0x00000003U
|
||||
#define CR_PFIM_FBDC_UV_BASE_ADDR_MSB_SHIFT 0
|
||||
#define CR_PFIM_FBDC_UV_BASE_ADDR_MSB_SIGNED 0
|
||||
|
||||
/*
|
||||
Register CR_PFIM_PDP_Y_BASE_ADDR
|
||||
*/
|
||||
#define CR_PFIM_PDP_Y_BASE_ADDR 0x0018
|
||||
#define CR_PFIM_PDP_Y_BASE_ADDR_MASK 0xFFFFFFFFU
|
||||
#define CR_PFIM_PDP_Y_BASE_ADDR_SHIFT 0
|
||||
#define CR_PFIM_PDP_Y_BASE_ADDR_SIGNED 0
|
||||
|
||||
/*
|
||||
Register CR_PFIM_PDP_UV_BASE_ADDR
|
||||
*/
|
||||
#define CR_PFIM_PDP_UV_BASE_ADDR 0x001C
|
||||
#define CR_PFIM_PDP_UV_BASE_ADDR_MASK 0xFFFFFFFFU
|
||||
#define CR_PFIM_PDP_UV_BASE_ADDR_SHIFT 0
|
||||
#define CR_PFIM_PDP_UV_BASE_ADDR_SIGNED 0
|
||||
|
||||
/*
|
||||
Register CR_PFIM_FBDC_REQ_CONTEXT
|
||||
*/
|
||||
#define CR_PFIM_FBDC_REQ_CONTEXT 0x0020
|
||||
#define CR_PFIM_FBDC_REQ_CONTEXT_MASK 0x00000007U
|
||||
#define CR_PFIM_FBDC_REQ_CONTEXT_SHIFT 0
|
||||
#define CR_PFIM_FBDC_REQ_CONTEXT_SIGNED 0
|
||||
|
||||
/*
|
||||
Register CR_PFIM_FBDC_REQ_TAG
|
||||
*/
|
||||
#define CR_PFIM_FBDC_REQ_TAG 0x0024
|
||||
#define CR_PFIM_FBDC_REQ_TAG_YARGB_MASK 0x00000003U
|
||||
#define CR_PFIM_FBDC_REQ_TAG_YARGB_SHIFT 0
|
||||
#define CR_PFIM_FBDC_REQ_TAG_YARGB_SIGNED 0
|
||||
|
||||
#define CR_PFIM_FBDC_REQ_TAG_UV_MASK 0x00000030U
|
||||
#define CR_PFIM_FBDC_REQ_TAG_UV_SHIFT 4
|
||||
#define CR_PFIM_FBDC_REQ_TAG_UV_SIGNED 0
|
||||
|
||||
/*
|
||||
Register CR_PFIM_FBDC_REQ_SB_TAG
|
||||
*/
|
||||
#define CR_PFIM_FBDC_REQ_SB_TAG 0x0028
|
||||
#define CR_PFIM_FBDC_REQ_SB_TAG_YARGB_MASK 0x00000003U
|
||||
#define CR_PFIM_FBDC_REQ_SB_TAG_YARGB_SHIFT 0
|
||||
#define CR_PFIM_FBDC_REQ_SB_TAG_YARGB_SIGNED 0
|
||||
|
||||
#define CR_PFIM_FBDC_REQ_SB_TAG_UV_MASK 0x00000030U
|
||||
#define CR_PFIM_FBDC_REQ_SB_TAG_UV_SHIFT 4
|
||||
#define CR_PFIM_FBDC_REQ_SB_TAG_UV_SIGNED 0
|
||||
|
||||
/*
|
||||
Register CR_PFIM_FBDC_HDR_INVAL_REQ
|
||||
*/
|
||||
#define CR_PFIM_FBDC_HDR_INVAL_REQ 0x002C
|
||||
#define CR_PFIM_FBDC_HDR_INVAL_REQ_MASK 0x00000001U
|
||||
#define CR_PFIM_FBDC_HDR_INVAL_REQ_SHIFT 0
|
||||
#define CR_PFIM_FBDC_HDR_INVAL_REQ_SIGNED 0
|
||||
|
||||
/*
|
||||
Register CR_PFIM_FBDC_PIX_FORMAT
|
||||
*/
|
||||
#define CR_PFIM_FBDC_PIX_FORMAT 0x0030
|
||||
#define CR_PFIM_FBDC_PIX_FORMAT_FBDC_PIX_FMT_MASK 0x0000007FU
|
||||
#define CR_PFIM_FBDC_PIX_FORMAT_FBDC_PIX_FMT_SHIFT 0
|
||||
#define CR_PFIM_FBDC_PIX_FORMAT_FBDC_PIX_FMT_SIGNED 0
|
||||
|
||||
/*
|
||||
Register CR_PFIM_FBDC_CR_CH0123_VAL0
|
||||
*/
|
||||
#define CR_PFIM_FBDC_CR_CH0123_VAL0 0x0034
|
||||
#define CR_PFIM_FBDC_CR_CH0123_VAL0_MASK 0xFFFFFFFFU
|
||||
#define CR_PFIM_FBDC_CR_CH0123_VAL0_SHIFT 0
|
||||
#define CR_PFIM_FBDC_CR_CH0123_VAL0_SIGNED 0
|
||||
|
||||
/*
|
||||
Register CR_PFIM_FBDC_CR_CH0123_VAL1
|
||||
*/
|
||||
#define CR_PFIM_FBDC_CR_CH0123_VAL1 0x0038
|
||||
#define CR_PFIM_FBDC_CR_CH0123_VAL1_MASK 0xFFFFFFFFU
|
||||
#define CR_PFIM_FBDC_CR_CH0123_VAL1_SHIFT 0
|
||||
#define CR_PFIM_FBDC_CR_CH0123_VAL1_SIGNED 0
|
||||
|
||||
/*
|
||||
Register CR_PFIM_FBDC_CR_Y_VAL0
|
||||
*/
|
||||
#define CR_PFIM_FBDC_CR_Y_VAL0 0x003C
|
||||
#define CR_PFIM_FBDC_CR_Y_VAL0_MASK 0x000003FFU
|
||||
#define CR_PFIM_FBDC_CR_Y_VAL0_SHIFT 0
|
||||
#define CR_PFIM_FBDC_CR_Y_VAL0_SIGNED 0
|
||||
|
||||
/*
|
||||
Register CR_PFIM_FBDC_CR_UV_VAL0
|
||||
*/
|
||||
#define CR_PFIM_FBDC_CR_UV_VAL0 0x0040
|
||||
#define CR_PFIM_FBDC_CR_UV_VAL0_MASK 0x000003FFU
|
||||
#define CR_PFIM_FBDC_CR_UV_VAL0_SHIFT 0
|
||||
#define CR_PFIM_FBDC_CR_UV_VAL0_SIGNED 0
|
||||
|
||||
/*
|
||||
Register CR_PFIM_FBDC_CR_Y_VAL1
|
||||
*/
|
||||
#define CR_PFIM_FBDC_CR_Y_VAL1 0x0044
|
||||
#define CR_PFIM_FBDC_CR_Y_VAL1_MASK 0x000003FFU
|
||||
#define CR_PFIM_FBDC_CR_Y_VAL1_SHIFT 0
|
||||
#define CR_PFIM_FBDC_CR_Y_VAL1_SIGNED 0
|
||||
|
||||
/*
|
||||
Register CR_PFIM_FBDC_CR_UV_VAL1
|
||||
*/
|
||||
#define CR_PFIM_FBDC_CR_UV_VAL1 0x0048
|
||||
#define CR_PFIM_FBDC_CR_UV_VAL1_MASK 0x000003FFU
|
||||
#define CR_PFIM_FBDC_CR_UV_VAL1_SHIFT 0
|
||||
#define CR_PFIM_FBDC_CR_UV_VAL1_SIGNED 0
|
||||
|
||||
/*
|
||||
Register CR_PFIM_FBDC_FILTER_ENABLE
|
||||
*/
|
||||
#define CR_PFIM_FBDC_FILTER_ENABLE 0x004C
|
||||
#define CR_PFIM_FBDC_FILTER_ENABLE_MASK 0x00000001U
|
||||
#define CR_PFIM_FBDC_FILTER_ENABLE_SHIFT 0
|
||||
#define CR_PFIM_FBDC_FILTER_ENABLE_SIGNED 0
|
||||
|
||||
/*
|
||||
Register CR_PFIM_FBDC_FILTER_STATUS
|
||||
*/
|
||||
#define CR_PFIM_FBDC_FILTER_STATUS 0x0050
|
||||
#define CR_PFIM_FBDC_FILTER_STATUS_MASK 0x0000000FU
|
||||
#define CR_PFIM_FBDC_FILTER_STATUS_SHIFT 0
|
||||
#define CR_PFIM_FBDC_FILTER_STATUS_SIGNED 0
|
||||
|
||||
/*
|
||||
Register CR_PFIM_FBDC_FILTER_CLEAR
|
||||
*/
|
||||
#define CR_PFIM_FBDC_FILTER_CLEAR 0x0054
|
||||
#define CR_PFIM_FBDC_FILTER_CLEAR_MASK 0x0000000FU
|
||||
#define CR_PFIM_FBDC_FILTER_CLEAR_SHIFT 0
|
||||
#define CR_PFIM_FBDC_FILTER_CLEAR_SIGNED 0
|
||||
|
||||
/*
|
||||
Register CR_PFIM_FBDC_TILE_TYPE
|
||||
*/
|
||||
#define CR_PFIM_FBDC_TILE_TYPE 0x0058
|
||||
#define CR_PFIM_FBDC_TILE_TYPE_MASK 0x00000003U
|
||||
#define CR_PFIM_FBDC_TILE_TYPE_SHIFT 0
|
||||
#define CR_PFIM_FBDC_TILE_TYPE_SIGNED 0
|
||||
|
||||
/*
|
||||
Register CR_PFIM_FBDC_CLEAR_COLOUR_LSB
|
||||
*/
|
||||
#define CR_PFIM_FBDC_CLEAR_COLOUR_LSB 0x005C
|
||||
#define CR_PFIM_FBDC_CLEAR_COLOUR_LSB_MASK 0xFFFFFFFFU
|
||||
#define CR_PFIM_FBDC_CLEAR_COLOUR_LSB_SHIFT 0
|
||||
#define CR_PFIM_FBDC_CLEAR_COLOUR_LSB_SIGNED 0
|
||||
|
||||
/*
|
||||
Register CR_PFIM_FBDC_CLEAR_COLOUR_MSB
|
||||
*/
|
||||
#define CR_PFIM_FBDC_CLEAR_COLOUR_MSB 0x0060
|
||||
#define CR_PFIM_FBDC_CLEAR_COLOUR_MSB_MASK 0xFFFFFFFFU
|
||||
#define CR_PFIM_FBDC_CLEAR_COLOUR_MSB_SHIFT 0
|
||||
#define CR_PFIM_FBDC_CLEAR_COLOUR_MSB_SIGNED 0
|
||||
|
||||
/*
|
||||
Register CR_PFIM_FBDC_REQ_LOSSY
|
||||
*/
|
||||
#define CR_PFIM_FBDC_REQ_LOSSY 0x0064
|
||||
#define CR_PFIM_FBDC_REQ_LOSSY_MASK 0x00000001U
|
||||
#define CR_PFIM_FBDC_REQ_LOSSY_SHIFT 0
|
||||
#define CR_PFIM_FBDC_REQ_LOSSY_SIGNED 0
|
||||
|
||||
#endif /* _PFIM_REGS_H_ */
|
||||
|
||||
/******************************************************************************
|
||||
End of file (pfim_regs.h)
|
||||
******************************************************************************/
|
||||
1018
drivers/gpu/drm/img-rogue/include/system/rgx_tc/tcf_clk_ctrl.h
Normal file
1018
drivers/gpu/drm/img-rogue/include/system/rgx_tc/tcf_clk_ctrl.h
Normal file
File diff suppressed because it is too large
Load Diff
311
drivers/gpu/drm/img-rogue/include/system/rgx_tc/tcf_pll.h
Normal file
311
drivers/gpu/drm/img-rogue/include/system/rgx_tc/tcf_pll.h
Normal file
@@ -0,0 +1,311 @@
|
||||
/*************************************************************************/ /*!
|
||||
@Title Test Chip Framework PDP register definitions
|
||||
@Copyright Copyright (c) Imagination Technologies Ltd. All Rights Reserved
|
||||
@Description Autogenerated C -- do not edit
|
||||
Generated from tcf_pll.def
|
||||
@License Dual MIT/GPLv2
|
||||
|
||||
The contents of this file are subject to the MIT license as set out below.
|
||||
|
||||
Permission is hereby granted, free of charge, to any person obtaining a copy
|
||||
of this software and associated documentation files (the "Software"), to deal
|
||||
in the Software without restriction, including without limitation the rights
|
||||
to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
|
||||
copies of the Software, and to permit persons to whom the Software is
|
||||
furnished to do so, subject to the following conditions:
|
||||
|
||||
The above copyright notice and this permission notice shall be included in
|
||||
all copies or substantial portions of the Software.
|
||||
|
||||
Alternatively, the contents of this file may be used under the terms of
|
||||
the GNU General Public License Version 2 ("GPL") in which case the provisions
|
||||
of GPL are applicable instead of those above.
|
||||
|
||||
If you wish to allow use of your version of this file only under the terms of
|
||||
GPL, and not to allow others to use your version of this file under the terms
|
||||
of the MIT license, indicate your decision by deleting the provisions above
|
||||
and replace them with the notice and other provisions required by GPL as set
|
||||
out in the file called "GPL-COPYING" included in this distribution. If you do
|
||||
not delete the provisions above, a recipient may use your version of this file
|
||||
under the terms of either the MIT license or GPL.
|
||||
|
||||
This License is also included in this distribution in the file called
|
||||
"MIT-COPYING".
|
||||
|
||||
EXCEPT AS OTHERWISE STATED IN A NEGOTIATED AGREEMENT: (A) THE SOFTWARE IS
|
||||
PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING
|
||||
BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR
|
||||
PURPOSE AND NONINFRINGEMENT; AND (B) IN NO EVENT SHALL THE AUTHORS OR
|
||||
COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
|
||||
IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
|
||||
CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
|
||||
*/ /**************************************************************************/
|
||||
|
||||
#if !defined(_TCF_PLL_H_)
|
||||
#define _TCF_PLL_H_
|
||||
|
||||
/*
|
||||
Register PLL_DDR2_CLK0
|
||||
*/
|
||||
#define TCF_PLL_PLL_DDR2_CLK0 0x0000
|
||||
#define DDR2_PLL_CLK0_PHS_MASK 0x00300000U
|
||||
#define DDR2_PLL_CLK0_PHS_SHIFT 20
|
||||
#define DDR2_PLL_CLK0_PHS_SIGNED 0
|
||||
|
||||
#define DDR2_PLL_CLK0_MS_MASK 0x00030000U
|
||||
#define DDR2_PLL_CLK0_MS_SHIFT 16
|
||||
#define DDR2_PLL_CLK0_MS_SIGNED 0
|
||||
|
||||
#define DDR2_PLL_CLK0_FREQ_MASK 0x000001FFU
|
||||
#define DDR2_PLL_CLK0_FREQ_SHIFT 0
|
||||
#define DDR2_PLL_CLK0_FREQ_SIGNED 0
|
||||
|
||||
/*
|
||||
Register PLL_DDR2_CLK1TO5
|
||||
*/
|
||||
#define TCF_PLL_PLL_DDR2_CLK1TO5 0x0008
|
||||
#define DDR2_PLL_CLK1TO5_PHS_MASK 0x3FF00000U
|
||||
#define DDR2_PLL_CLK1TO5_PHS_SHIFT 20
|
||||
#define DDR2_PLL_CLK1TO5_PHS_SIGNED 0
|
||||
|
||||
#define DDR2_PLL_CLK1TO5_MS_MASK 0x000FFC00U
|
||||
#define DDR2_PLL_CLK1TO5_MS_SHIFT 10
|
||||
#define DDR2_PLL_CLK1TO5_MS_SIGNED 0
|
||||
|
||||
#define DDR2_PLL_CLK1TO5_FREQ_MASK 0x000003FFU
|
||||
#define DDR2_PLL_CLK1TO5_FREQ_SHIFT 0
|
||||
#define DDR2_PLL_CLK1TO5_FREQ_SIGNED 0
|
||||
|
||||
/*
|
||||
Register PLL_DDR2_DRP_GO
|
||||
*/
|
||||
#define TCF_PLL_PLL_DDR2_DRP_GO 0x0010
|
||||
#define PLL_DDR2_DRP_GO_MASK 0x00000001U
|
||||
#define PLL_DDR2_DRP_GO_SHIFT 0
|
||||
#define PLL_DDR2_DRP_GO_SIGNED 0
|
||||
|
||||
/*
|
||||
Register PLL_PDP_CLK0
|
||||
*/
|
||||
#define TCF_PLL_PLL_PDP_CLK0 0x0018
|
||||
#define PDP_PLL_CLK0_PHS_MASK 0x00300000U
|
||||
#define PDP_PLL_CLK0_PHS_SHIFT 20
|
||||
#define PDP_PLL_CLK0_PHS_SIGNED 0
|
||||
|
||||
#define PDP_PLL_CLK0_MS_MASK 0x00030000U
|
||||
#define PDP_PLL_CLK0_MS_SHIFT 16
|
||||
#define PDP_PLL_CLK0_MS_SIGNED 0
|
||||
|
||||
#define PDP_PLL_CLK0_FREQ_MASK 0x000001FFU
|
||||
#define PDP_PLL_CLK0_FREQ_SHIFT 0
|
||||
#define PDP_PLL_CLK0_FREQ_SIGNED 0
|
||||
|
||||
/*
|
||||
Register PLL_PDP_CLK1TO5
|
||||
*/
|
||||
#define TCF_PLL_PLL_PDP_CLK1TO5 0x0020
|
||||
#define PDP_PLL_CLK1TO5_PHS_MASK 0x3FF00000U
|
||||
#define PDP_PLL_CLK1TO5_PHS_SHIFT 20
|
||||
#define PDP_PLL_CLK1TO5_PHS_SIGNED 0
|
||||
|
||||
#define PDP_PLL_CLK1TO5_MS_MASK 0x000FFC00U
|
||||
#define PDP_PLL_CLK1TO5_MS_SHIFT 10
|
||||
#define PDP_PLL_CLK1TO5_MS_SIGNED 0
|
||||
|
||||
#define PDP_PLL_CLK1TO5_FREQ_MASK 0x000003FFU
|
||||
#define PDP_PLL_CLK1TO5_FREQ_SHIFT 0
|
||||
#define PDP_PLL_CLK1TO5_FREQ_SIGNED 0
|
||||
|
||||
/*
|
||||
Register PLL_PDP_DRP_GO
|
||||
*/
|
||||
#define TCF_PLL_PLL_PDP_DRP_GO 0x0028
|
||||
#define PLL_PDP_DRP_GO_MASK 0x00000001U
|
||||
#define PLL_PDP_DRP_GO_SHIFT 0
|
||||
#define PLL_PDP_DRP_GO_SIGNED 0
|
||||
|
||||
/*
|
||||
Register PLL_PDP2_CLK0
|
||||
*/
|
||||
#define TCF_PLL_PLL_PDP2_CLK0 0x0030
|
||||
#define PDP2_PLL_CLK0_PHS_MASK 0x00300000U
|
||||
#define PDP2_PLL_CLK0_PHS_SHIFT 20
|
||||
#define PDP2_PLL_CLK0_PHS_SIGNED 0
|
||||
|
||||
#define PDP2_PLL_CLK0_MS_MASK 0x00030000U
|
||||
#define PDP2_PLL_CLK0_MS_SHIFT 16
|
||||
#define PDP2_PLL_CLK0_MS_SIGNED 0
|
||||
|
||||
#define PDP2_PLL_CLK0_FREQ_MASK 0x000001FFU
|
||||
#define PDP2_PLL_CLK0_FREQ_SHIFT 0
|
||||
#define PDP2_PLL_CLK0_FREQ_SIGNED 0
|
||||
|
||||
/*
|
||||
Register PLL_PDP2_CLK1TO5
|
||||
*/
|
||||
#define TCF_PLL_PLL_PDP2_CLK1TO5 0x0038
|
||||
#define PDP2_PLL_CLK1TO5_PHS_MASK 0x3FF00000U
|
||||
#define PDP2_PLL_CLK1TO5_PHS_SHIFT 20
|
||||
#define PDP2_PLL_CLK1TO5_PHS_SIGNED 0
|
||||
|
||||
#define PDP2_PLL_CLK1TO5_MS_MASK 0x000FFC00U
|
||||
#define PDP2_PLL_CLK1TO5_MS_SHIFT 10
|
||||
#define PDP2_PLL_CLK1TO5_MS_SIGNED 0
|
||||
|
||||
#define PDP2_PLL_CLK1TO5_FREQ_MASK 0x000003FFU
|
||||
#define PDP2_PLL_CLK1TO5_FREQ_SHIFT 0
|
||||
#define PDP2_PLL_CLK1TO5_FREQ_SIGNED 0
|
||||
|
||||
/*
|
||||
Register PLL_PDP2_DRP_GO
|
||||
*/
|
||||
#define TCF_PLL_PLL_PDP2_DRP_GO 0x0040
|
||||
#define PLL_PDP2_DRP_GO_MASK 0x00000001U
|
||||
#define PLL_PDP2_DRP_GO_SHIFT 0
|
||||
#define PLL_PDP2_DRP_GO_SIGNED 0
|
||||
|
||||
/*
|
||||
Register PLL_CORE_CLK0
|
||||
*/
|
||||
#define TCF_PLL_PLL_CORE_CLK0 0x0048
|
||||
#define CORE_PLL_CLK0_PHS_MASK 0x00300000U
|
||||
#define CORE_PLL_CLK0_PHS_SHIFT 20
|
||||
#define CORE_PLL_CLK0_PHS_SIGNED 0
|
||||
|
||||
#define CORE_PLL_CLK0_MS_MASK 0x00030000U
|
||||
#define CORE_PLL_CLK0_MS_SHIFT 16
|
||||
#define CORE_PLL_CLK0_MS_SIGNED 0
|
||||
|
||||
#define CORE_PLL_CLK0_FREQ_MASK 0x000001FFU
|
||||
#define CORE_PLL_CLK0_FREQ_SHIFT 0
|
||||
#define CORE_PLL_CLK0_FREQ_SIGNED 0
|
||||
|
||||
/*
|
||||
Register PLL_CORE_CLK1TO5
|
||||
*/
|
||||
#define TCF_PLL_PLL_CORE_CLK1TO5 0x0050
|
||||
#define CORE_PLL_CLK1TO5_PHS_MASK 0x3FF00000U
|
||||
#define CORE_PLL_CLK1TO5_PHS_SHIFT 20
|
||||
#define CORE_PLL_CLK1TO5_PHS_SIGNED 0
|
||||
|
||||
#define CORE_PLL_CLK1TO5_MS_MASK 0x000FFC00U
|
||||
#define CORE_PLL_CLK1TO5_MS_SHIFT 10
|
||||
#define CORE_PLL_CLK1TO5_MS_SIGNED 0
|
||||
|
||||
#define CORE_PLL_CLK1TO5_FREQ_MASK 0x000003FFU
|
||||
#define CORE_PLL_CLK1TO5_FREQ_SHIFT 0
|
||||
#define CORE_PLL_CLK1TO5_FREQ_SIGNED 0
|
||||
|
||||
/*
|
||||
Register PLL_CORE_DRP_GO
|
||||
*/
|
||||
#define TCF_PLL_PLL_CORE_DRP_GO 0x0058
|
||||
#define PLL_CORE_DRP_GO_MASK 0x00000001U
|
||||
#define PLL_CORE_DRP_GO_SHIFT 0
|
||||
#define PLL_CORE_DRP_GO_SIGNED 0
|
||||
|
||||
/*
|
||||
Register PLL_SYSIF_CLK0
|
||||
*/
|
||||
#define TCF_PLL_PLL_SYSIF_CLK0 0x0060
|
||||
#define SYSIF_PLL_CLK0_PHS_MASK 0x00300000U
|
||||
#define SYSIF_PLL_CLK0_PHS_SHIFT 20
|
||||
#define SYSIF_PLL_CLK0_PHS_SIGNED 0
|
||||
|
||||
#define SYSIF_PLL_CLK0_MS_MASK 0x00030000U
|
||||
#define SYSIF_PLL_CLK0_MS_SHIFT 16
|
||||
#define SYSIF_PLL_CLK0_MS_SIGNED 0
|
||||
|
||||
#define SYSIF_PLL_CLK0_FREQ_MASK 0x000001FFU
|
||||
#define SYSIF_PLL_CLK0_FREQ_SHIFT 0
|
||||
#define SYSIF_PLL_CLK0_FREQ_SIGNED 0
|
||||
|
||||
/*
|
||||
Register PLL_SYSIF_CLK1TO5
|
||||
*/
|
||||
#define TCF_PLL_PLL_SYSIF_CLK1TO5 0x0068
|
||||
#define SYSIF_PLL_CLK1TO5_PHS_MASK 0x3FF00000U
|
||||
#define SYSIF_PLL_CLK1TO5_PHS_SHIFT 20
|
||||
#define SYSIF_PLL_CLK1TO5_PHS_SIGNED 0
|
||||
|
||||
#define SYSIF_PLL_CLK1TO5_MS_MASK 0x000FFC00U
|
||||
#define SYSIF_PLL_CLK1TO5_MS_SHIFT 10
|
||||
#define SYSIF_PLL_CLK1TO5_MS_SIGNED 0
|
||||
|
||||
#define SYSIF_PLL_CLK1TO5_FREQ_MASK 0x000003FFU
|
||||
#define SYSIF_PLL_CLK1TO5_FREQ_SHIFT 0
|
||||
#define SYSIF_PLL_CLK1TO5_FREQ_SIGNED 0
|
||||
|
||||
/*
|
||||
Register PLL_SYS_DRP_GO
|
||||
*/
|
||||
#define TCF_PLL_PLL_SYS_DRP_GO 0x0070
|
||||
#define PLL_SYS_DRP_GO_MASK 0x00000001U
|
||||
#define PLL_SYS_DRP_GO_SHIFT 0
|
||||
#define PLL_SYS_DRP_GO_SIGNED 0
|
||||
|
||||
/*
|
||||
Register PLL_MEMIF_CLK0
|
||||
*/
|
||||
#define TCF_PLL_PLL_MEMIF_CLK0 0x0078
|
||||
#define MEMIF_PLL_CLK0_PHS_MASK 0x00300000U
|
||||
#define MEMIF_PLL_CLK0_PHS_SHIFT 20
|
||||
#define MEMIF_PLL_CLK0_PHS_SIGNED 0
|
||||
|
||||
#define MEMIF_PLL_CLK0_MS_MASK 0x00030000U
|
||||
#define MEMIF_PLL_CLK0_MS_SHIFT 16
|
||||
#define MEMIF_PLL_CLK0_MS_SIGNED 0
|
||||
|
||||
#define MEMIF_PLL_CLK0_FREQ_MASK 0x000001FFU
|
||||
#define MEMIF_PLL_CLK0_FREQ_SHIFT 0
|
||||
#define MEMIF_PLL_CLK0_FREQ_SIGNED 0
|
||||
|
||||
/*
|
||||
Register PLL_MEMIF_CLK1TO5
|
||||
*/
|
||||
#define TCF_PLL_PLL_MEMIF_CLK1TO5 0x0080
|
||||
#define MEMIF_PLL_CLK1TO5_PHS_MASK 0x3FF00000U
|
||||
#define MEMIF_PLL_CLK1TO5_PHS_SHIFT 20
|
||||
#define MEMIF_PLL_CLK1TO5_PHS_SIGNED 0
|
||||
|
||||
#define MEMIF_PLL_CLK1TO5_MS_MASK 0x000FFC00U
|
||||
#define MEMIF_PLL_CLK1TO5_MS_SHIFT 10
|
||||
#define MEMIF_PLL_CLK1TO5_MS_SIGNED 0
|
||||
|
||||
#define MEMIF_PLL_CLK1TO5_FREQ_MASK 0x000003FFU
|
||||
#define MEMIF_PLL_CLK1TO5_FREQ_SHIFT 0
|
||||
#define MEMIF_PLL_CLK1TO5_FREQ_SIGNED 0
|
||||
|
||||
/*
|
||||
Register PLL_MEM_DRP_GO
|
||||
*/
|
||||
#define TCF_PLL_PLL_MEM_DRP_GO 0x0088
|
||||
#define PLL_MEM_DRP_GO_MASK 0x00000001U
|
||||
#define PLL_MEM_DRP_GO_SHIFT 0
|
||||
#define PLL_MEM_DRP_GO_SIGNED 0
|
||||
|
||||
/*
|
||||
Register PLL_ALL_DRP_GO
|
||||
*/
|
||||
#define TCF_PLL_PLL_ALL_DRP_GO 0x0090
|
||||
#define PLL_ALL_DRP_GO_MASK 0x00000001U
|
||||
#define PLL_ALL_DRP_GO_SHIFT 0
|
||||
#define PLL_ALL_DRP_GO_SIGNED 0
|
||||
|
||||
/*
|
||||
Register PLL_DRP_STATUS
|
||||
*/
|
||||
#define TCF_PLL_PLL_DRP_STATUS 0x0098
|
||||
#define PLL_LOCKS_MASK 0x00003F00U
|
||||
#define PLL_LOCKS_SHIFT 8
|
||||
#define PLL_LOCKS_SIGNED 0
|
||||
|
||||
#define PLL_DRP_GOOD_MASK 0x0000003FU
|
||||
#define PLL_DRP_GOOD_SHIFT 0
|
||||
#define PLL_DRP_GOOD_SIGNED 0
|
||||
|
||||
#endif /* !defined(_TCF_PLL_H_) */
|
||||
|
||||
/*****************************************************************************
|
||||
End of file (tcf_pll.h)
|
||||
*****************************************************************************/
|
||||
@@ -0,0 +1,559 @@
|
||||
/*************************************************************************/ /*!
|
||||
@Title Test Chip Framework PDP register definitions
|
||||
@Copyright Copyright (c) Imagination Technologies Ltd. All Rights Reserved
|
||||
@Description Autogenerated C -- do not edit
|
||||
Generated from: tcf_rgbpdp_regs.def
|
||||
@License Dual MIT/GPLv2
|
||||
|
||||
The contents of this file are subject to the MIT license as set out below.
|
||||
|
||||
Permission is hereby granted, free of charge, to any person obtaining a copy
|
||||
of this software and associated documentation files (the "Software"), to deal
|
||||
in the Software without restriction, including without limitation the rights
|
||||
to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
|
||||
copies of the Software, and to permit persons to whom the Software is
|
||||
furnished to do so, subject to the following conditions:
|
||||
|
||||
The above copyright notice and this permission notice shall be included in
|
||||
all copies or substantial portions of the Software.
|
||||
|
||||
Alternatively, the contents of this file may be used under the terms of
|
||||
the GNU General Public License Version 2 ("GPL") in which case the provisions
|
||||
of GPL are applicable instead of those above.
|
||||
|
||||
If you wish to allow use of your version of this file only under the terms of
|
||||
GPL, and not to allow others to use your version of this file under the terms
|
||||
of the MIT license, indicate your decision by deleting the provisions above
|
||||
and replace them with the notice and other provisions required by GPL as set
|
||||
out in the file called "GPL-COPYING" included in this distribution. If you do
|
||||
not delete the provisions above, a recipient may use your version of this file
|
||||
under the terms of either the MIT license or GPL.
|
||||
|
||||
This License is also included in this distribution in the file called
|
||||
"MIT-COPYING".
|
||||
|
||||
EXCEPT AS OTHERWISE STATED IN A NEGOTIATED AGREEMENT: (A) THE SOFTWARE IS
|
||||
PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING
|
||||
BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR
|
||||
PURPOSE AND NONINFRINGEMENT; AND (B) IN NO EVENT SHALL THE AUTHORS OR
|
||||
COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
|
||||
IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
|
||||
CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
|
||||
*/ /**************************************************************************/
|
||||
|
||||
#if !defined(_TCF_RGBPDP_REGS_H_)
|
||||
#define _TCF_RGBPDP_REGS_H_
|
||||
|
||||
/*
|
||||
Register PVR_TCF_RGBPDP_STR1SURF
|
||||
*/
|
||||
#define TCF_RGBPDP_PVR_TCF_RGBPDP_STR1SURF 0x0000
|
||||
#define STR1HEIGHT_MASK 0x000007FFU
|
||||
#define STR1HEIGHT_SHIFT 0
|
||||
#define STR1HEIGHT_SIGNED 0
|
||||
|
||||
#define STR1WIDTH_MASK 0x003FF800U
|
||||
#define STR1WIDTH_SHIFT 11
|
||||
#define STR1WIDTH_SIGNED 0
|
||||
|
||||
#define STR1PIXFMT_MASK 0x0F000000U
|
||||
#define STR1PIXFMT_SHIFT 24
|
||||
#define STR1PIXFMT_SIGNED 0
|
||||
|
||||
/*
|
||||
Register PVR_TCF_RGBPDP_STR1ADDRCTRL
|
||||
*/
|
||||
#define TCF_RGBPDP_PVR_TCF_RGBPDP_STR1ADDRCTRL 0x0004
|
||||
#define STR1BASE_MASK 0x03FFFFFFU
|
||||
#define STR1BASE_SHIFT 0
|
||||
#define STR1BASE_SIGNED 0
|
||||
|
||||
#define STR1INTFIELD_MASK 0x40000000U
|
||||
#define STR1INTFIELD_SHIFT 30
|
||||
#define STR1INTFIELD_SIGNED 0
|
||||
|
||||
#define STR1STREN_MASK 0x80000000U
|
||||
#define STR1STREN_SHIFT 31
|
||||
#define STR1STREN_SIGNED 0
|
||||
|
||||
/*
|
||||
Register PVR_PDP_STR1POSN
|
||||
*/
|
||||
#define TCF_RGBPDP_PVR_PDP_STR1POSN 0x0008
|
||||
#define STR1STRIDE_MASK 0x000003FFU
|
||||
#define STR1STRIDE_SHIFT 0
|
||||
#define STR1STRIDE_SIGNED 0
|
||||
|
||||
/*
|
||||
Register PVR_TCF_RGBPDP_MEMCTRL
|
||||
*/
|
||||
#define TCF_RGBPDP_PVR_TCF_RGBPDP_MEMCTRL 0x000C
|
||||
#define MEMREFRESH_MASK 0xC0000000U
|
||||
#define MEMREFRESH_SHIFT 30
|
||||
#define MEMREFRESH_SIGNED 0
|
||||
|
||||
/*
|
||||
Register PVR_TCF_RGBPDP_STRCTRL
|
||||
*/
|
||||
#define TCF_RGBPDP_PVR_TCF_RGBPDP_STRCTRL 0x0010
|
||||
#define BURSTLEN_GFX_MASK 0x000000FFU
|
||||
#define BURSTLEN_GFX_SHIFT 0
|
||||
#define BURSTLEN_GFX_SIGNED 0
|
||||
|
||||
#define THRESHOLD_GFX_MASK 0x0000FF00U
|
||||
#define THRESHOLD_GFX_SHIFT 8
|
||||
#define THRESHOLD_GFX_SIGNED 0
|
||||
|
||||
/*
|
||||
Register PVR_TCF_RGBPDP_SYNCCTRL
|
||||
*/
|
||||
#define TCF_RGBPDP_PVR_TCF_RGBPDP_SYNCCTRL 0x0014
|
||||
#define HSDIS_MASK 0x00000001U
|
||||
#define HSDIS_SHIFT 0
|
||||
#define HSDIS_SIGNED 0
|
||||
|
||||
#define HSPOL_MASK 0x00000002U
|
||||
#define HSPOL_SHIFT 1
|
||||
#define HSPOL_SIGNED 0
|
||||
|
||||
#define VSDIS_MASK 0x00000004U
|
||||
#define VSDIS_SHIFT 2
|
||||
#define VSDIS_SIGNED 0
|
||||
|
||||
#define VSPOL_MASK 0x00000008U
|
||||
#define VSPOL_SHIFT 3
|
||||
#define VSPOL_SIGNED 0
|
||||
|
||||
#define BLNKDIS_MASK 0x00000010U
|
||||
#define BLNKDIS_SHIFT 4
|
||||
#define BLNKDIS_SIGNED 0
|
||||
|
||||
#define BLNKPOL_MASK 0x00000020U
|
||||
#define BLNKPOL_SHIFT 5
|
||||
#define BLNKPOL_SIGNED 0
|
||||
|
||||
#define HS_SLAVE_MASK 0x00000040U
|
||||
#define HS_SLAVE_SHIFT 6
|
||||
#define HS_SLAVE_SIGNED 0
|
||||
|
||||
#define VS_SLAVE_MASK 0x00000080U
|
||||
#define VS_SLAVE_SHIFT 7
|
||||
#define VS_SLAVE_SIGNED 0
|
||||
|
||||
#define INTERLACE_MASK 0x00000100U
|
||||
#define INTERLACE_SHIFT 8
|
||||
#define INTERLACE_SIGNED 0
|
||||
|
||||
#define FIELDPOL_MASK 0x00000200U
|
||||
#define FIELDPOL_SHIFT 9
|
||||
#define FIELDPOL_SIGNED 0
|
||||
|
||||
#define CLKPOL_MASK 0x00000800U
|
||||
#define CLKPOL_SHIFT 11
|
||||
#define CLKPOL_SIGNED 0
|
||||
|
||||
#define CSYNC_EN_MASK 0x00001000U
|
||||
#define CSYNC_EN_SHIFT 12
|
||||
#define CSYNC_EN_SIGNED 0
|
||||
|
||||
#define FIELD_EN_MASK 0x00002000U
|
||||
#define FIELD_EN_SHIFT 13
|
||||
#define FIELD_EN_SIGNED 0
|
||||
|
||||
#define UPDWAIT_MASK 0x000F0000U
|
||||
#define UPDWAIT_SHIFT 16
|
||||
#define UPDWAIT_SIGNED 0
|
||||
|
||||
#define UPDCTRL_MASK 0x01000000U
|
||||
#define UPDCTRL_SHIFT 24
|
||||
#define UPDCTRL_SIGNED 0
|
||||
|
||||
#define UPDINTCTRL_MASK 0x02000000U
|
||||
#define UPDINTCTRL_SHIFT 25
|
||||
#define UPDINTCTRL_SIGNED 0
|
||||
|
||||
#define UPDSYNCTRL_MASK 0x04000000U
|
||||
#define UPDSYNCTRL_SHIFT 26
|
||||
#define UPDSYNCTRL_SIGNED 0
|
||||
|
||||
#define POWERDN_MASK 0x10000000U
|
||||
#define POWERDN_SHIFT 28
|
||||
#define POWERDN_SIGNED 0
|
||||
|
||||
#define DISP_RST_MASK 0x20000000U
|
||||
#define DISP_RST_SHIFT 29
|
||||
#define DISP_RST_SIGNED 0
|
||||
|
||||
#define SYNCACTIVE_MASK 0x80000000U
|
||||
#define SYNCACTIVE_SHIFT 31
|
||||
#define SYNCACTIVE_SIGNED 0
|
||||
|
||||
/*
|
||||
Register PVR_TCF_RGBPDP_BORDCOL
|
||||
*/
|
||||
#define TCF_RGBPDP_PVR_TCF_RGBPDP_BORDCOL 0x0018
|
||||
#define BORDCOL_MASK 0x00FFFFFFU
|
||||
#define BORDCOL_SHIFT 0
|
||||
#define BORDCOL_SIGNED 0
|
||||
|
||||
/*
|
||||
Register PVR_TCF_RGBPDP_UPDCTRL
|
||||
*/
|
||||
#define TCF_RGBPDP_PVR_TCF_RGBPDP_UPDCTRL 0x001C
|
||||
#define UPDFIELD_MASK 0x00000001U
|
||||
#define UPDFIELD_SHIFT 0
|
||||
#define UPDFIELD_SIGNED 0
|
||||
|
||||
/*
|
||||
Register PVR_TCF_RGBPDP_HSYNC1
|
||||
*/
|
||||
#define TCF_RGBPDP_PVR_TCF_RGBPDP_HSYNC1 0x0020
|
||||
#define HT_MASK 0x00000FFFU
|
||||
#define HT_SHIFT 0
|
||||
#define HT_SIGNED 0
|
||||
|
||||
#define HBPS_MASK 0x0FFF0000U
|
||||
#define HBPS_SHIFT 16
|
||||
#define HBPS_SIGNED 0
|
||||
|
||||
/*
|
||||
Register PVR_TCF_RGBPDP_HSYNC2
|
||||
*/
|
||||
#define TCF_RGBPDP_PVR_TCF_RGBPDP_HSYNC2 0x0024
|
||||
#define HLBS_MASK 0x00000FFFU
|
||||
#define HLBS_SHIFT 0
|
||||
#define HLBS_SIGNED 0
|
||||
|
||||
#define HAS_MASK 0x0FFF0000U
|
||||
#define HAS_SHIFT 16
|
||||
#define HAS_SIGNED 0
|
||||
|
||||
/*
|
||||
Register PVR_TCF_RGBPDP_HSYNC3
|
||||
*/
|
||||
#define TCF_RGBPDP_PVR_TCF_RGBPDP_HSYNC3 0x0028
|
||||
#define HRBS_MASK 0x00000FFFU
|
||||
#define HRBS_SHIFT 0
|
||||
#define HRBS_SIGNED 0
|
||||
|
||||
#define HFPS_MASK 0x0FFF0000U
|
||||
#define HFPS_SHIFT 16
|
||||
#define HFPS_SIGNED 0
|
||||
|
||||
/*
|
||||
Register PVR_TCF_RGBPDP_VSYNC1
|
||||
*/
|
||||
#define TCF_RGBPDP_PVR_TCF_RGBPDP_VSYNC1 0x002C
|
||||
#define VT_MASK 0x00000FFFU
|
||||
#define VT_SHIFT 0
|
||||
#define VT_SIGNED 0
|
||||
|
||||
#define VBPS_MASK 0x0FFF0000U
|
||||
#define VBPS_SHIFT 16
|
||||
#define VBPS_SIGNED 0
|
||||
|
||||
/*
|
||||
Register PVR_TCF_RGBPDP_VSYNC2
|
||||
*/
|
||||
#define TCF_RGBPDP_PVR_TCF_RGBPDP_VSYNC2 0x0030
|
||||
#define VTBS_MASK 0x00000FFFU
|
||||
#define VTBS_SHIFT 0
|
||||
#define VTBS_SIGNED 0
|
||||
|
||||
#define VAS_MASK 0x0FFF0000U
|
||||
#define VAS_SHIFT 16
|
||||
#define VAS_SIGNED 0
|
||||
|
||||
/*
|
||||
Register PVR_TCF_RGBPDP_VSYNC3
|
||||
*/
|
||||
#define TCF_RGBPDP_PVR_TCF_RGBPDP_VSYNC3 0x0034
|
||||
#define VBBS_MASK 0x00000FFFU
|
||||
#define VBBS_SHIFT 0
|
||||
#define VBBS_SIGNED 0
|
||||
|
||||
#define VFPS_MASK 0x0FFF0000U
|
||||
#define VFPS_SHIFT 16
|
||||
#define VFPS_SIGNED 0
|
||||
|
||||
/*
|
||||
Register PVR_TCF_RGBPDP_HDECTRL
|
||||
*/
|
||||
#define TCF_RGBPDP_PVR_TCF_RGBPDP_HDECTRL 0x0038
|
||||
#define HDEF_MASK 0x00000FFFU
|
||||
#define HDEF_SHIFT 0
|
||||
#define HDEF_SIGNED 0
|
||||
|
||||
#define HDES_MASK 0x0FFF0000U
|
||||
#define HDES_SHIFT 16
|
||||
#define HDES_SIGNED 0
|
||||
|
||||
/*
|
||||
Register PVR_TCF_RGBPDP_VDECTRL
|
||||
*/
|
||||
#define TCF_RGBPDP_PVR_TCF_RGBPDP_VDECTRL 0x003C
|
||||
#define VDEF_MASK 0x00000FFFU
|
||||
#define VDEF_SHIFT 0
|
||||
#define VDEF_SIGNED 0
|
||||
|
||||
#define VDES_MASK 0x0FFF0000U
|
||||
#define VDES_SHIFT 16
|
||||
#define VDES_SIGNED 0
|
||||
|
||||
/*
|
||||
Register PVR_TCF_RGBPDP_VEVENT
|
||||
*/
|
||||
#define TCF_RGBPDP_PVR_TCF_RGBPDP_VEVENT 0x0040
|
||||
#define VFETCH_MASK 0x00000FFFU
|
||||
#define VFETCH_SHIFT 0
|
||||
#define VFETCH_SIGNED 0
|
||||
|
||||
#define VEVENT_MASK 0x0FFF0000U
|
||||
#define VEVENT_SHIFT 16
|
||||
#define VEVENT_SIGNED 0
|
||||
|
||||
/*
|
||||
Register PVR_TCF_RGBPDP_OPMASK
|
||||
*/
|
||||
#define TCF_RGBPDP_PVR_TCF_RGBPDP_OPMASK 0x0044
|
||||
#define MASKR_MASK 0x000000FFU
|
||||
#define MASKR_SHIFT 0
|
||||
#define MASKR_SIGNED 0
|
||||
|
||||
#define MASKG_MASK 0x0000FF00U
|
||||
#define MASKG_SHIFT 8
|
||||
#define MASKG_SIGNED 0
|
||||
|
||||
#define MASKB_MASK 0x00FF0000U
|
||||
#define MASKB_SHIFT 16
|
||||
#define MASKB_SIGNED 0
|
||||
|
||||
#define BLANKLEVEL_MASK 0x40000000U
|
||||
#define BLANKLEVEL_SHIFT 30
|
||||
#define BLANKLEVEL_SIGNED 0
|
||||
|
||||
#define MASKLEVEL_MASK 0x80000000U
|
||||
#define MASKLEVEL_SHIFT 31
|
||||
#define MASKLEVEL_SIGNED 0
|
||||
|
||||
/*
|
||||
Register PVR_TCF_RGBPDP_INTSTAT
|
||||
*/
|
||||
#define TCF_RGBPDP_PVR_TCF_RGBPDP_INTSTAT 0x0048
|
||||
#define INTS_HBLNK0_MASK 0x00000001U
|
||||
#define INTS_HBLNK0_SHIFT 0
|
||||
#define INTS_HBLNK0_SIGNED 0
|
||||
|
||||
#define INTS_HBLNK1_MASK 0x00000002U
|
||||
#define INTS_HBLNK1_SHIFT 1
|
||||
#define INTS_HBLNK1_SIGNED 0
|
||||
|
||||
#define INTS_VBLNK0_MASK 0x00000004U
|
||||
#define INTS_VBLNK0_SHIFT 2
|
||||
#define INTS_VBLNK0_SIGNED 0
|
||||
|
||||
#define INTS_VBLNK1_MASK 0x00000008U
|
||||
#define INTS_VBLNK1_SHIFT 3
|
||||
#define INTS_VBLNK1_SIGNED 0
|
||||
|
||||
#define INTS_STR1URUN_MASK 0x00000010U
|
||||
#define INTS_STR1URUN_SHIFT 4
|
||||
#define INTS_STR1URUN_SIGNED 0
|
||||
|
||||
#define INTS_STR1ORUN_MASK 0x00000020U
|
||||
#define INTS_STR1ORUN_SHIFT 5
|
||||
#define INTS_STR1ORUN_SIGNED 0
|
||||
|
||||
#define INTS_DISPURUN_MASK 0x00000040U
|
||||
#define INTS_DISPURUN_SHIFT 6
|
||||
#define INTS_DISPURUN_SIGNED 0
|
||||
|
||||
/*
|
||||
Register PVR_TCF_RGBPDP_INTENAB
|
||||
*/
|
||||
#define TCF_RGBPDP_PVR_TCF_RGBPDP_INTENAB 0x004C
|
||||
#define INTEN_HBLNK0_MASK 0x00000001U
|
||||
#define INTEN_HBLNK0_SHIFT 0
|
||||
#define INTEN_HBLNK0_SIGNED 0
|
||||
|
||||
#define INTEN_HBLNK1_MASK 0x00000002U
|
||||
#define INTEN_HBLNK1_SHIFT 1
|
||||
#define INTEN_HBLNK1_SIGNED 0
|
||||
|
||||
#define INTEN_VBLNK0_MASK 0x00000004U
|
||||
#define INTEN_VBLNK0_SHIFT 2
|
||||
#define INTEN_VBLNK0_SIGNED 0
|
||||
|
||||
#define INTEN_VBLNK1_MASK 0x00000008U
|
||||
#define INTEN_VBLNK1_SHIFT 3
|
||||
#define INTEN_VBLNK1_SIGNED 0
|
||||
|
||||
#define INTEN_STR1URUN_MASK 0x00000010U
|
||||
#define INTEN_STR1URUN_SHIFT 4
|
||||
#define INTEN_STR1URUN_SIGNED 0
|
||||
|
||||
#define INTEN_STR1ORUN_MASK 0x00000020U
|
||||
#define INTEN_STR1ORUN_SHIFT 5
|
||||
#define INTEN_STR1ORUN_SIGNED 0
|
||||
|
||||
#define INTEN_DISPURUN_MASK 0x00000040U
|
||||
#define INTEN_DISPURUN_SHIFT 6
|
||||
#define INTEN_DISPURUN_SIGNED 0
|
||||
|
||||
/*
|
||||
Register PVR_TCF_RGBPDP_INTCLEAR
|
||||
*/
|
||||
#define TCF_RGBPDP_PVR_TCF_RGBPDP_INTCLEAR 0x0050
|
||||
#define INTCLR_HBLNK0_MASK 0x00000001U
|
||||
#define INTCLR_HBLNK0_SHIFT 0
|
||||
#define INTCLR_HBLNK0_SIGNED 0
|
||||
|
||||
#define INTCLR_HBLNK1_MASK 0x00000002U
|
||||
#define INTCLR_HBLNK1_SHIFT 1
|
||||
#define INTCLR_HBLNK1_SIGNED 0
|
||||
|
||||
#define INTCLR_VBLNK0_MASK 0x00000004U
|
||||
#define INTCLR_VBLNK0_SHIFT 2
|
||||
#define INTCLR_VBLNK0_SIGNED 0
|
||||
|
||||
#define INTCLR_VBLNK1_MASK 0x00000008U
|
||||
#define INTCLR_VBLNK1_SHIFT 3
|
||||
#define INTCLR_VBLNK1_SIGNED 0
|
||||
|
||||
#define INTCLR_STR1URUN_MASK 0x00000010U
|
||||
#define INTCLR_STR1URUN_SHIFT 4
|
||||
#define INTCLR_STR1URUN_SIGNED 0
|
||||
|
||||
#define INTCLR_STR1ORUN_MASK 0x00000020U
|
||||
#define INTCLR_STR1ORUN_SHIFT 5
|
||||
#define INTCLR_STR1ORUN_SIGNED 0
|
||||
|
||||
#define INTCLR_DISPURUN_MASK 0x00000040U
|
||||
#define INTCLR_DISPURUN_SHIFT 6
|
||||
#define INTCLR_DISPURUN_SIGNED 0
|
||||
|
||||
/*
|
||||
Register PVR_TCF_RGBPDP_INTCTRL
|
||||
*/
|
||||
#define TCF_RGBPDP_PVR_TCF_RGBPDP_INTCTRL 0x0054
|
||||
#define HBLNK_LINENO_MASK 0x00000FFFU
|
||||
#define HBLNK_LINENO_SHIFT 0
|
||||
#define HBLNK_LINENO_SIGNED 0
|
||||
|
||||
#define HBLNK_LINE_MASK 0x00010000U
|
||||
#define HBLNK_LINE_SHIFT 16
|
||||
#define HBLNK_LINE_SIGNED 0
|
||||
|
||||
/*
|
||||
Register PVR_TCF_RGBPDP_SIGNAT
|
||||
*/
|
||||
#define TCF_RGBPDP_PVR_TCF_RGBPDP_SIGNAT 0x0058
|
||||
#define SIGNATURE_MASK 0xFFFFFFFFU
|
||||
#define SIGNATURE_SHIFT 0
|
||||
#define SIGNATURE_SIGNED 0
|
||||
|
||||
/*
|
||||
Register PVR_TCF_RGBPDP_LINESTAT
|
||||
*/
|
||||
#define TCF_RGBPDP_PVR_TCF_RGBPDP_LINESTAT 0x005C
|
||||
#define LINENO_MASK 0x00000FFFU
|
||||
#define LINENO_SHIFT 0
|
||||
#define LINENO_SIGNED 0
|
||||
|
||||
/*
|
||||
Register PVR_TCF_RGBPDP_DBGCTRL
|
||||
*/
|
||||
#define TCF_RGBPDP_PVR_TCF_RGBPDP_DBGCTRL 0x0060
|
||||
#define DBG_ENAB_MASK 0x00000001U
|
||||
#define DBG_ENAB_SHIFT 0
|
||||
#define DBG_ENAB_SIGNED 0
|
||||
|
||||
#define DBG_READ_MASK 0x00000002U
|
||||
#define DBG_READ_SHIFT 1
|
||||
#define DBG_READ_SIGNED 0
|
||||
|
||||
/*
|
||||
Register PVR_TCF_RGBPDP_DBGDATA
|
||||
*/
|
||||
#define TCF_RGBPDP_PVR_TCF_RGBPDP_DBGDATA 0x0064
|
||||
#define DBG_DATA_MASK 0x00FFFFFFU
|
||||
#define DBG_DATA_SHIFT 0
|
||||
#define DBG_DATA_SIGNED 0
|
||||
|
||||
/*
|
||||
Register PVR_TCF_RGBPDP_DBGSIDE
|
||||
*/
|
||||
#define TCF_RGBPDP_PVR_TCF_RGBPDP_DBGSIDE 0x0068
|
||||
#define DBG_SIDE_MASK 0x00000007U
|
||||
#define DBG_SIDE_SHIFT 0
|
||||
#define DBG_SIDE_SIGNED 0
|
||||
|
||||
#define DBG_VAL_MASK 0x00000008U
|
||||
#define DBG_VAL_SHIFT 3
|
||||
#define DBG_VAL_SIGNED 0
|
||||
|
||||
/*
|
||||
Register PVR_TCF_RGBPDP_REGLD_STAT
|
||||
*/
|
||||
#define TCF_RGBPDP_PVR_TCF_RGBPDP_REGLD_STAT 0x0070
|
||||
#define REGLD_ADDROUT_MASK 0x00FFFFFFU
|
||||
#define REGLD_ADDROUT_SHIFT 0
|
||||
#define REGLD_ADDROUT_SIGNED 0
|
||||
|
||||
#define REGLD_ADDREN_MASK 0x80000000U
|
||||
#define REGLD_ADDREN_SHIFT 31
|
||||
#define REGLD_ADDREN_SIGNED 0
|
||||
|
||||
/*
|
||||
Register PVR_TCF_RGBPDP_REGLD_CTRL
|
||||
*/
|
||||
#define TCF_RGBPDP_PVR_TCF_RGBPDP_REGLD_CTRL 0x0074
|
||||
#define REGLD_ADDRIN_MASK 0x00FFFFFFU
|
||||
#define REGLD_ADDRIN_SHIFT 0
|
||||
#define REGLD_ADDRIN_SIGNED 0
|
||||
|
||||
#define REGLD_VAL_MASK 0x01000000U
|
||||
#define REGLD_VAL_SHIFT 24
|
||||
#define REGLD_VAL_SIGNED 0
|
||||
|
||||
#define REGLD_ADDRLEN_MASK 0xFE000000U
|
||||
#define REGLD_ADDRLEN_SHIFT 25
|
||||
#define REGLD_ADDRLEN_SIGNED 0
|
||||
|
||||
/*
|
||||
Register PVR_TCF_RGBPDP_CORE_ID
|
||||
*/
|
||||
#define TCF_RGBPDP_PVR_TCF_RGBPDP_CORE_ID 0x0078
|
||||
#define CONFIG_ID_MASK 0x0000FFFFU
|
||||
#define CONFIG_ID_SHIFT 0
|
||||
#define CONFIG_ID_SIGNED 0
|
||||
|
||||
#define CORE_ID_MASK 0x00FF0000U
|
||||
#define CORE_ID_SHIFT 16
|
||||
#define CORE_ID_SIGNED 0
|
||||
|
||||
#define GROUP_ID_MASK 0xFF000000U
|
||||
#define GROUP_ID_SHIFT 24
|
||||
#define GROUP_ID_SIGNED 0
|
||||
|
||||
/*
|
||||
Register PVR_TCF_RGBPDP_CORE_REV
|
||||
*/
|
||||
#define TCF_RGBPDP_PVR_TCF_RGBPDP_CORE_REV 0x007C
|
||||
#define MAINT_REV_MASK 0x000000FFU
|
||||
#define MAINT_REV_SHIFT 0
|
||||
#define MAINT_REV_SIGNED 0
|
||||
|
||||
#define MINOR_REV_MASK 0x0000FF00U
|
||||
#define MINOR_REV_SHIFT 8
|
||||
#define MINOR_REV_SIGNED 0
|
||||
|
||||
#define MAJOR_REV_MASK 0x00FF0000U
|
||||
#define MAJOR_REV_SHIFT 16
|
||||
#define MAJOR_REV_SIGNED 0
|
||||
|
||||
#endif /* !defined(_TCF_RGBPDP_REGS_H_) */
|
||||
|
||||
/*****************************************************************************
|
||||
End of file (tcf_rgbpdp_regs.h)
|
||||
*****************************************************************************/
|
||||
Reference in New Issue
Block a user