diff --git a/arch/riscv/Kconfig b/arch/riscv/Kconfig index 8f404fd86..6bccae460 100644 --- a/arch/riscv/Kconfig +++ b/arch/riscv/Kconfig @@ -26,6 +26,7 @@ config RISCV select ARCH_HAS_SET_DIRECT_MAP select ARCH_HAS_SET_MEMORY select ARCH_HAS_STRICT_KERNEL_RWX if MMU + select ARCH_HAS_STRICT_MODULE_RWX if MMU select ARCH_HAS_DMA_PREP_COHERENT select ARCH_HAS_SYNC_DMA_FOR_CPU select ARCH_HAS_SYNC_DMA_FOR_DEVICE @@ -359,8 +360,6 @@ config RISCV_ISA_C config NO_SFENCE_VMA bool "Replace sfence.vma with CSR_SMCIR operation" - depends on !SMP - default y config RISCV_SWIOTLB bool "Enable SWIOTLB" @@ -416,6 +415,11 @@ config VECTOR_0_7 endchoice +config VLEN_256 + bool "VECTOR VLEN 256" + depends on VECTOR + default n + config VECTOR_EMU bool "VECTOR e64 emulate for c906 v1" depends on VECTOR diff --git a/arch/riscv/boot/dts/thead/Makefile b/arch/riscv/boot/dts/thead/Makefile index 035048f2d..7d56875bd 100644 --- a/arch/riscv/boot/dts/thead/Makefile +++ b/arch/riscv/boot/dts/thead/Makefile @@ -24,23 +24,12 @@ dtb-$(CONFIG_SOC_THEAD) += light-b-product.dtb dtb-$(CONFIG_SOC_THEAD) += light-b-product-ddr1G.dtb dtb-$(CONFIG_SOC_THEAD) += light-b-product-miniapp-hdmi.dtb dtb-$(CONFIG_SOC_THEAD) += light-a-val-full.dtb -dtb-$(CONFIG_SOC_THEAD) += light-ant-evt.dtb +dtb-$(CONFIG_SOC_THEAD) += light-ant-ref.dtb dtb-$(CONFIG_SOC_THEAD) += light-ant-discrete.dtb +dtb-$(CONFIG_SOC_THEAD) += light-beagle.dtb +dtb-$(CONFIG_SOC_THEAD) += light-a-ref.dtb light-a-ref-dsi0.dtb light-a-ref-dsi0-hdmi.dtb +dtb-$(CONFIG_SOC_THEAD) += light-b-ref.dtb +dtb-$(CONFIG_SOC_THEAD) += light-a-val-crash.dtb light-b-product-crash.dtb light-ant-ref-crash.dtb light-ant-discrete-crash.dtb +dtb-$(CONFIG_SOC_THEAD) += light-b-power.dtb -# // temporary dtb for power gate -dtb-$(CONFIG_SOC_THEAD) += light-a-val-powergate.dtb light-a-val-sv-powergate.dtb -dtb-$(CONFIG_SOC_THEAD) += light-a-val-ddr2G-powergate.dtb light-a-val-ddr1G-powergate.dtb -dtb-$(CONFIG_SOC_THEAD) += light-a-val-npu-fce-powergate.dtb -dtb-$(CONFIG_SOC_THEAD) += light-a-val-iso7816-powergate.dtb -dtb-$(CONFIG_SOC_THEAD) += light-a-val-nand-powergate.dtb -dtb-$(CONFIG_SOC_THEAD) += light-a-val-audio-powergate.dtb -dtb-$(CONFIG_SOC_THEAD) += light-a-val-dsi0-powergate.dtb light-a-val-dsi1-powergate.dtb light-a-val-hdmi-powergate.dtb light-a-val-dsi0-dsi1-powergate.dtb light-a-val-dsi0-hdmi-powergate.dtb light-a-val-dpi0-powergate.dtb light-a-val-dpi0-dpi1-powergate.dtb -dtb-$(CONFIG_SOC_THEAD) += light-a-val-wcn-powergate.dtb -dtb-$(CONFIG_SOC_THEAD) += light-a-val-khv-powergate.dtb -dtb-$(CONFIG_SOC_THEAD) += light-a-val-sec-powergate.dtb -dtb-$(CONFIG_SOC_THEAD) += light-a-val-miniapp-hdmi-powergate.dtb -dtb-$(CONFIG_SOC_THEAD) += light-a-product-powergate.dtb -dtb-$(CONFIG_SOC_THEAD) += light-b-product-powergate.dtb -dtb-$(CONFIG_SOC_THEAD) += light-b-product-ddr1G-powergate.dtb -dtb-$(CONFIG_SOC_THEAD) += light-a-val-full-powergate.dtb dtb-$(CONFIG_SOC_THEAD) += light-a-val-android.dtb diff --git a/arch/riscv/boot/dts/thead/light-a-product.dts b/arch/riscv/boot/dts/thead/light-a-product.dts index c2312516e..dbeb964bc 100644 --- a/arch/riscv/boot/dts/thead/light-a-product.dts +++ b/arch/riscv/boot/dts/thead/light-a-product.dts @@ -13,8 +13,6 @@ chosen { bootargs = "console=ttyS0,115200 crashkernel=256M-:128M earlycon clk_ignore_unused sram=0xffe0000000,0x180000"; - linux,initrd-start = <0x0 0x2000000>; - linux,initrd-end = <0x0 0x14600000>; stdout-path = "serial0:115200n8"; }; @@ -465,6 +463,10 @@ }; }; +&cmamem { + alloc-ranges = <0 0xe4000000 0 0x14000000>; // [0xE400_0000 ~ 0xF800_0000] +}; + &resmem { #address-cells = <2>; #size-cells = <2>; @@ -488,14 +490,16 @@ 0x0 0x20688000 0x0 0x00178000>; /* DSP shared memory */ no-map; }; - facelib_mem: memory@d0000000 { - reg = <0x0 0xd0000000 0 0x10000000>; + vi_mem: framebuffer@0f800000 { + reg = <0x0 0x0F800000 0x0 0x05400000 /* vi_mem_pool_region[0] 84 MB (default) */ + 0x0 0x14C00000 0x0 0x01D00000 /* vi_mem_pool_region[1] 29 MB */ + 0x0 0x16900000 0x0 0x03200000>; /* vi_mem_pool_region[2] 50 MB */ no-map; }; - vi_mem: framebuffer@70000000 { - reg = <0x0 0x70000000 0 0xbc00000>; + facelib_mem: memory@22000000 { + reg = <0x0 0x22000000 0x0 0x10000000>; no-map; - }; + }; }; &adc { @@ -504,7 +508,7 @@ }; &i2c0 { - clock-frequency = <100000>; + clock-frequency = <400000>; status = "okay"; eeprom@50 { @@ -537,7 +541,7 @@ }; &i2c1 { - clock-frequency = <100000>; + clock-frequency = <400000>; status = "okay"; touch1@5d { #gpio-cells = <2>; @@ -683,6 +687,7 @@ no-mmc; non-removable; io_fixed_1v8; + post-power-on-delay-ms = <50>; wprtn_ignore; cap-sd-highspeed; keep-power-in-suspend; @@ -815,6 +820,7 @@ }; &i2c2 { + clock-frequency = <400000>; status = "okay"; eeprom@50 { @@ -825,6 +831,7 @@ }; &i2c3 { + clock-frequency = <400000>; status = "okay"; eeprom@50 { @@ -835,6 +842,7 @@ }; &i2c4 { + clock-frequency = <400000>; status = "okay"; eeprom@50 { diff --git a/arch/riscv/boot/dts/thead/light-a-ref-dsi0-hdmi.dts b/arch/riscv/boot/dts/thead/light-a-ref-dsi0-hdmi.dts new file mode 100644 index 000000000..c134431d4 --- /dev/null +++ b/arch/riscv/boot/dts/thead/light-a-ref-dsi0-hdmi.dts @@ -0,0 +1,29 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Copyright (C) 2021 Alibaba Group Holding Limited. + */ + +/dts-v1/; + +#include "light-a-ref-dsi0.dts" + +&dpu_enc1 { + ports { + /delete-node/ port@0; + }; +}; + +&disp1_out { + remote-endpoint = <&hdmi_tx_in>; +}; + +&hdmi_tx { + status = "okay"; + + port@0 { + /* input */ + hdmi_tx_in: endpoint { + remote-endpoint = <&disp1_out>; + }; + }; +}; diff --git a/arch/riscv/boot/dts/thead/light-a-ref-dsi0.dts b/arch/riscv/boot/dts/thead/light-a-ref-dsi0.dts new file mode 100644 index 000000000..57bd3ae2b --- /dev/null +++ b/arch/riscv/boot/dts/thead/light-a-ref-dsi0.dts @@ -0,0 +1,75 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Copyright (C) 2021 Alibaba Group Holding Limited. + */ + +/dts-v1/; + +#include "light-a-ref.dts" + +/ { + display-subsystem { + status = "okay"; + }; +}; + +&dpu_enc0 { + status = "okay"; + + ports { + /* output */ + port@1 { + reg = <1>; + + enc0_out: endpoint { + remote-endpoint = <&dsi0_in>; + }; + }; + }; +}; + +&dpu { + status = "okay"; +}; + +&dsi0 { + status = "okay"; +}; + +&dhost_0 { + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + dsi0_in: endpoint { + remote-endpoint = <&enc0_out>; + }; + }; + + port@1 { + reg = <1>; + + dsi0_out: endpoint { + remote-endpoint = <&panel0_in>; + }; + }; + }; + + panel0@0 { + compatible = "txd,dy800qwxpab"; + reg = <0>; + backlight = <&lcd0_backlight>; + reset-gpio = <&gpio1_porta 5 1>; /* active low */ + vdd1v8-supply = <&lcd0_1v8>; + vspn5v7-supply = <&lcd0_5v7>; + + port { + panel0_in: endpoint { + remote-endpoint = <&dsi0_out>; + }; + }; + }; +}; diff --git a/arch/riscv/boot/dts/thead/light-a-ref.dts b/arch/riscv/boot/dts/thead/light-a-ref.dts new file mode 100644 index 000000000..4287c4a11 --- /dev/null +++ b/arch/riscv/boot/dts/thead/light-a-ref.dts @@ -0,0 +1,5 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Copyright (C) 2021 Alibaba Group Holding Limited. + */ +#include "light-a-val.dts" diff --git a/arch/riscv/boot/dts/thead/light-a-val-crash.dts b/arch/riscv/boot/dts/thead/light-a-val-crash.dts new file mode 100644 index 000000000..78a51f006 --- /dev/null +++ b/arch/riscv/boot/dts/thead/light-a-val-crash.dts @@ -0,0 +1,98 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Copyright (C) 2021 Alibaba Group Holding Limited. + */ + +#include "light-crash.dts" + +&aon { + aon_reg_dialog: light-dialog-reg { + compatible = "thead,light-dialog-pmic"; + status = "okay"; + + dvdd_cpu_reg: appcpu_dvdd { + regulator-name = "appcpu_dvdd"; + regulator-min-microvolt = <600000>; + regulator-max-microvolt = <1500000>; + regulator-boot-on; + regulator-always-on; + }; + + dvddm_cpu_reg: appcpu_dvddm { + regulator-name = "appcpu_dvddm"; + regulator-min-microvolt = <600000>; + regulator-max-microvolt = <1500000>; + regulator-boot-on; + regulator-always-on; + }; + }; +}; + +&cpus { + c910_0: cpu@0 { + operating-points = < + /* kHz uV */ + 300000 600000 + 800000 700000 + 1500000 800000 + 1848000 1000000 + >; + light,dvddm-operating-points = < + /* kHz uV */ + 300000 800000 + 800000 800000 + 1500000 800000 + 1848000 1000000 + >; + }; + c910_1: cpu@1 { + operating-points = < + /* kHz uV */ + 300000 600000 + 800000 700000 + 1500000 800000 + 1848000 1000000 + >; + light,dvddm-operating-points = < + /* kHz uV */ + 300000 800000 + 800000 800000 + 1500000 800000 + 1848000 1000000 + >; + }; + c910_2: cpu@2 { + + operating-points = < + /* kHz uV */ + 300000 600000 + 800000 700000 + 1500000 800000 + 1848000 1000000 + >; + light,dvddm-operating-points = < + /* kHz uV */ + 300000 800000 + 800000 800000 + 1500000 800000 + 1848000 1000000 + >; + }; + c910_3: cpu@3 { + + operating-points = < + /* kHz uV */ + 300000 600000 + 800000 700000 + 1500000 800000 + 1848000 1000000 + >; + light,dvddm-operating-points = < + /* kHz uV */ + 300000 800000 + 800000 800000 + 1500000 800000 + 1848000 1000000 + >; + }; +}; diff --git a/arch/riscv/boot/dts/thead/light-a-val-ddr1G.dts b/arch/riscv/boot/dts/thead/light-a-val-ddr1G.dts index 82f492244..4361d13c8 100644 --- a/arch/riscv/boot/dts/thead/light-a-val-ddr1G.dts +++ b/arch/riscv/boot/dts/thead/light-a-val-ddr1G.dts @@ -16,6 +16,6 @@ }; &cmamem { - size = <0 0x8c00000>; - alloc-ranges = <0 0x35000000 0 0x3dc00000>; + size = <0 0x8c00000>; // 140MB by default + alloc-ranges = <0 0x02000000 0 0x0cc00000>; // [0x0600_0000 ~ 0x0EC0_0000] }; diff --git a/arch/riscv/boot/dts/thead/light-a-val-ddr2G.dts b/arch/riscv/boot/dts/thead/light-a-val-ddr2G.dts index d934f1e2b..31c515fe9 100644 --- a/arch/riscv/boot/dts/thead/light-a-val-ddr2G.dts +++ b/arch/riscv/boot/dts/thead/light-a-val-ddr2G.dts @@ -15,7 +15,11 @@ }; }; +&cmamem { + alloc-ranges = <0 0x64000000 0 0x14000000>; // [0x6400_0000 ~ 0x7800_0000] +}; + &facelib_mem { - reg = <0x0 0x33000000 0 0x02000000>; + reg = <0x0 0x22000000 0 0x02000000>; no-map; }; diff --git a/arch/riscv/boot/dts/thead/light-a-val.dts b/arch/riscv/boot/dts/thead/light-a-val.dts index 6b4a72539..90da285ee 100644 --- a/arch/riscv/boot/dts/thead/light-a-val.dts +++ b/arch/riscv/boot/dts/thead/light-a-val.dts @@ -16,8 +16,6 @@ chosen { bootargs = "console=ttyS0,115200 crashkernel=256M-:128M earlycon clk_ignore_unused sram=0xffe0000000,0x180000"; - linux,initrd-start = <0x0 0x2000000>; - linux,initrd-end = <0x0 0x14600000>; stdout-path = "serial0:115200n8"; }; @@ -405,6 +403,8 @@ }; soc_dovdd18_scan_reg: soc_dovdd18_scan { regulator-name = "soc_dovdd18_scan"; + regulator-min-microvolt = <900000>; + regulator-max-microvolt = <3600000>; }; soc_vext_2v8_reg: soc_vext_2v8 { regulator-name = "soc_vext_2v8"; @@ -413,37 +413,51 @@ }; soc_dvdd12_scan_reg: soc_dvdd12_scan { regulator-name = "soc_dvdd12_scan"; + regulator-min-microvolt = <900000>; + regulator-max-microvolt = <3600000>; }; soc_avdd28_scan_en_reg: soc_avdd28_scan_en { regulator-name = "soc_avdd28_scan_en"; }; soc_avdd28_rgb_reg: soc_avdd28_rgb { regulator-name = "soc_avdd28_rgb"; + regulator-min-microvolt = <2200000>; + regulator-max-microvolt = <3475000>; regulator-boot-on; regulator-always-on; }; soc_dovdd18_rgb_reg: soc_dovdd18_rgb { regulator-name = "soc_dovdd18_rgb"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <3600000>; regulator-boot-on; regulator-always-on; }; soc_dvdd12_rgb_reg: soc_dvdd12_rgb { regulator-name = "soc_dvdd12_rgb"; + regulator-min-microvolt = <400000>; + regulator-max-microvolt = <1675000>; regulator-boot-on; regulator-always-on; }; soc_avdd25_ir_reg: soc_avdd25_ir { regulator-name = "soc_avdd25_ir"; + regulator-min-microvolt = <2200000>; + regulator-max-microvolt = <3475000>; regulator-boot-on; regulator-always-on; }; soc_dovdd18_ir_reg: soc_dovdd18_ir { regulator-name = "soc_dovdd18_ir"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <3600000>; regulator-boot-on; regulator-always-on; }; soc_dvdd12_ir_reg: soc_dvdd12_ir { regulator-name = "soc_dvdd12_ir"; + regulator-min-microvolt = <400000>; + regulator-max-microvolt = <1675000>; regulator-boot-on; regulator-always-on; }; @@ -461,6 +475,10 @@ }; }; +&cmamem { + alloc-ranges = <0 0xe4000000 0 0x14000000>; // [0xE400_0000 ~ 0xF800_0000] +}; + &resmem { #address-cells = <2>; #size-cells = <2>; @@ -484,17 +502,17 @@ 0x0 0x20688000 0x0 0x00178000>; /* DSP shared memory */ no-map; }; - facelib_mem: memory@d0000000 { - reg = <0x0 0xd0000000 0x0 0x10000000>; + vi_mem: framebuffer@0f800000 { + reg = <0x0 0x0F800000 0x0 0x05400000 /* vi_mem_pool_region[0] 84 MB (default) */ + 0x0 0x14C00000 0x0 0x01D00000 /* vi_mem_pool_region[1] 29 MB */ + 0x0 0x16900000 0x0 0x03200000>; /* vi_mem_pool_region[2] 50 MB */ + no-map; + }; + facelib_mem: memory@22000000 { + reg = <0x0 0x22000000 0x0 0x10000000>; no-map; }; - vi_mem: framebuffer@70000000 { - reg = <0x0 0x70000000 0x0 0x05400000 /* vi_mem_pool_region[0] 84 MB (default) */ - 0x0 0x75400000 0x0 0x01D00000 /* vi_mem_pool_region[1] 29 MB */ - 0x0 0x77100000 0x0 0x03200000>; /* vi_mem_pool_region[2] 50 MB */ - no-map; - }; }; &adc { @@ -503,7 +521,7 @@ }; &i2c0 { - clock-frequency = <100000>; + clock-frequency = <400000>; status = "okay"; eeprom@50 { @@ -553,7 +571,7 @@ }; &i2c1 { - clock-frequency = <100000>; + clock-frequency = <400000>; status = "okay"; touch1@5d { #gpio-cells = <2>; @@ -699,6 +717,7 @@ no-mmc; non-removable; io_fixed_1v8; + post-power-on-delay-ms = <50>; wprtn_ignore; cap-sd-highspeed; keep-power-in-suspend; @@ -837,8 +856,8 @@ }; &i2c2 { + clock-frequency = <400000>; status = "okay"; - eeprom@50 { compatible = "atmel,24c32"; reg = <0x50>; @@ -847,8 +866,8 @@ }; &i2c3 { + clock-frequency = <400000>; status = "okay"; - eeprom@50 { compatible = "atmel,24c32"; reg = <0x50>; @@ -857,8 +876,8 @@ }; &i2c4 { + clock-frequency = <400000>; status = "okay"; - eeprom@50 { compatible = "atmel,24c32"; reg = <0x50>; @@ -950,7 +969,7 @@ sensor_regulators = "DOVDD18_RGB", "DVDD12_RGB", "AVDD28_RGB"; sensor_regulator_timing_us = <70 50 20>; sensor_rst = <&gpio1_porta 16 0>; - sensor_pdn_delay_us = <1000>; //powerdown pin / shutdown pin actived till I2C ready + sensor_pdn_delay_us = <4000>; //powerdown pin / shutdown pin actived till I2C ready DOVDD18_RGB-supply = <&soc_dovdd18_rgb_reg>; DVDD12_RGB-supply = <&soc_dvdd12_rgb_reg>; AVDD28_RGB-supply = <&soc_avdd28_rgb_reg>; @@ -990,8 +1009,9 @@ sensor_name = "SC2310"; sensor_regulators = "DOVDD18_SCAN", "DVDD12_SCAN", "AVDD28_SCAN"; sensor_regulator_timing_us = <70 50 20>; - //sensor_pdn = <&gpio1_porta 30 0>; //powerdown pin / shutdown pin - //sensor_rst = <&gpio1_porta 29 0>; + sensor_pdn = <&gpio1_porta 30 0>; //powerdown pin / shutdown pin + sensor_rst = <&gpio1_porta 29 0>; + sensor_pdn_delay_us = <4000>; //powerdown pin / shutdown pin actived till I2C ready DOVDD18_SCAN-supply = <&soc_dovdd18_scan_reg>; DVDD12_SCAN-supply = <&soc_dvdd12_scan_reg>; AVDD28_SCAN-supply = <&soc_avdd28_scan_en_reg>; @@ -1002,10 +1022,10 @@ &vvcam_sensor4 { sensor_name = "SC132GS"; sensor_regulators = "DOVDD18_IR", "DVDD12_IR", "AVDD25_IR"; - sensor_regulator_timing_us = <70 50 20>; + sensor_regulator_timing_us = <70 1000 2000>; i2c_addr = /bits/ 8 <0x31>; sensor_rst = <&gpio1_porta 24 0>; - sensor_pdn_delay_us = <1000>; //powerdown pin / shutdown pin actived till I2C ready + sensor_pdn_delay_us = <2000>; //powerdown pin / shutdown pin actived till I2C ready DOVDD18_IR-supply = <&soc_dovdd18_ir_reg>; DVDD12_IR-supply = <&soc_dvdd12_ir_reg>; AVDD25_IR-supply = <&soc_avdd25_ir_reg>; @@ -1019,7 +1039,7 @@ sensor_name = "OV12870"; sensor_regulators = "DOVDD18_RGB", "DVDD12_RGB", "AVDD28_RGB"; sensor_regulator_timing_us = <100 50 0>; - //sensor_rst = <&gpio1_porta 16 0>; + sensor_rst = <&gpio1_porta 16 0>; sensor_pdn_delay_us = <60>; //powerdown pin / shutdown pin actived till I2C ready DOVDD18_RGB-supply = <&soc_dovdd18_rgb_reg>; DVDD12_RGB-supply = <&soc_dvdd12_rgb_reg>; @@ -1031,6 +1051,22 @@ status = "okay"; }; +&vvcam_sensor6 { + sensor_name = "GC02M1B"; + sensor_regulators = "DOVDD18_RGB", "DVDD12_RGB", "AVDD28_RGB"; + sensor_regulator_timing_us = <70 50 20>; + sensor_rst = <&gpio1_porta 16 0>; + sensor_pdn_delay_us = <1000>; //powerdown pin / shutdown pin actived till I2C ready + DOVDD18_RGB-supply = <&soc_dovdd18_rgb_reg>; + DVDD12_RGB-supply = <&soc_dvdd12_rgb_reg>; + AVDD28_RGB-supply = <&soc_avdd28_rgb_reg>; + i2c_reg_width = /bits/ 8 <1>; + i2c_data_width = /bits/ 8 <1>; + i2c_addr = /bits/ 8 <0x37>; + i2c_bus = /bits/ 8 <3>; + status = "okay"; +}; + &video0{ vi_mem_pool_region = <2>; // vi_mem: framebuffer, region[2] pipline0 { @@ -1038,13 +1074,15 @@ subdev_name = "vivcam"; idx = <2>; //<2>=vivcam2 : gc5035 csi_idx = <1>; //<1>=CSI2X2_B - path_type = "SENSOR_1080P_RAW10_LINER"; //SENSOR_VGA_RAW10_LINER// + mode_idx = <3>; + path_type = "SENSOR_1296x972_RAW10_LINER"; //SENSOR_VGA_RAW10_LINER// }; sensor1 { subdev_name = "vivcam"; idx = <3>; //<3>=vivcam3 : sc2310 csi_idx = <1>; //<1>=CSI2X2_B - path_type = "SENSOR_1080P_RAW12_LINER"; + mode_idx = <1>; + path_type = "SENSOR_1920X1088_26FPS_RAW12_LINER"; }; isp { subdev_name = "isp"; @@ -1063,13 +1101,15 @@ subdev_name = "vivcam"; idx = <2>; //<2>=vivcam2 : gc5035 csi_idx = <1>; //<1>=CSI2X2_B - path_type = "SENSOR_1080P_RAW10_LINER"; //SENSOR_VGA_RAW10_LINER// + mode_idx = <3>; + path_type = "SENSOR_1296x972_RAW10_LINER"; //SENSOR_VGA_RAW10_LINER// }; sensor1 { subdev_name = "vivcam"; idx = <3>; //<3>=vivcam3 : sc2310 csi_idx = <1>; //<1>=CSI2X2_B - path_type = "SENSOR_1080P_RAW12_LINER"; + mode_idx = <1>; + path_type = "SENSOR_1920X1088_26FPS_RAW12_LINER"; }; isp { subdev_name = "isp"; @@ -1088,13 +1128,15 @@ subdev_name = "vivcam"; idx = <2>; //<2>=vivcam2 : gc5035 csi_idx = <1>; //<1>=CSI2X2_B - path_type = "SENSOR_1080P_RAW10_LINER"; //SENSOR_VGA_RAW10_LINER// + mode_idx = <3>; + path_type = "SENSOR_1296x972_RAW10_LINER"; //SENSOR_VGA_RAW10_LINER// }; sensor1 { subdev_name = "vivcam"; idx = <3>; //<3>=vivcam3 : sc2310 csi_idx = <1>; //<1>=CSI2X2_B - path_type = "SENSOR_1080P_RAW12_LINER"; + mode_idx = <1>; + path_type = "SENSOR_1920X1088_26FPS_RAW12_LINER"; }; isp { subdev_name = "isp"; @@ -1118,13 +1160,15 @@ subdev_name = "vivcam"; idx = <2>; //<2>=vivcam2 : gc5035 csi_idx = <1>; //<1>=CSI2X2_B - path_type = "SENSOR_1080P_RAW10_LINER"; + mode_idx = <3>; + path_type = "SENSOR_1296x972_RAW10_LINER"; }; sensor1 { subdev_name = "vivcam"; idx = <3>; //<3>=vivcam3 : sc2310 csi_idx = <1>; //<1>=CSI2X2_B - path_type = "SENSOR_1080P_RAW12_LINER"; + mode_idx = <1>; + path_type = "SENSOR_1920X1088_26FPS_RAW12_LINER"; }; isp { subdev_name = "isp"; @@ -1149,13 +1193,15 @@ subdev_name = "vivcam"; idx = <2>; //<2>=vivcam2 : gc5035 csi_idx = <1>; //<1>=CSI2X2_B - path_type = "SENSOR_1080P_RAW10_LINER"; + mode_idx = <3>; + path_type = "SENSOR_1296x972_RAW10_LINER"; }; sensor1 { subdev_name = "vivcam"; idx = <3>; //<3>=vivcam3 : sc2310 csi_idx = <1>; //<1>=CSI2X2_B - path_type = "SENSOR_1080P_RAW12_LINER"; + mode_idx = <1>; + path_type = "SENSOR_1920X1088_26FPS_RAW12_LINER"; }; isp { subdev_name = "isp"; @@ -1180,13 +1226,15 @@ subdev_name = "vivcam"; idx = <2>; //<2>=vivcam2 : gc5035 csi_idx = <1>; //<1>=CSI2X2_B - path_type = "SENSOR_1080P_RAW10_LINER"; + mode_idx = <3>; + path_type = "SENSOR_1296x972_RAW10_LINER"; }; sensor1 { subdev_name = "vivcam"; idx = <3>; //<3>=vivcam3 : sc2310 csi_idx = <1>; //<1>=CSI2X2_B - path_type = "SENSOR_1080P_RAW12_LINER"; + mode_idx = <1>; + path_type = "SENSOR_1920X1088_26FPS_RAW12_LINER"; }; isp { subdev_name = "isp"; @@ -1215,7 +1263,15 @@ subdev_name = "vivcam"; idx = <0>; //sc2310 csi_idx = <0>; //<0>=CSI2 - path_type = "SENSOR_1080P_RAW12_LINER"; + mode_idx = <1>; + path_type = "SENSOR_1920X1088_26FPS_RAW12_LINER"; + }; + sensor1 { + subdev_name = "vivcam"; + idx = <6>; //gc02m1b + csi_idx = <0>; //<0>=CSI2 + mode_idx = <0>; + path_type = "SENSOR_1600x1200_RAW10_LINER"; }; isp { subdev_name = "isp"; @@ -1224,7 +1280,7 @@ output { max_width = <1920>; max_height = <1088>; - bit_per_pixel = <12>; + bit_per_pixel = <16>; frame_count = <3>; }; }; @@ -1234,7 +1290,15 @@ subdev_name = "vivcam"; idx = <0>; //sc2310 csi_idx = <0>; //<0>=CSI2 - path_type = "SENSOR_1080P_RAW12_LINER"; + mode_idx = <1>; + path_type = "SENSOR_1920X1088_26FPS_RAW12_LINER"; + }; + sensor1 { + subdev_name = "vivcam"; + idx = <6>; //gc02m1b + csi_idx = <0>; //<0>=CSI2 + mode_idx = <0>; + path_type = "SENSOR_1600x1200_RAW10_LINER"; }; isp { subdev_name = "isp"; @@ -1243,7 +1307,7 @@ output { max_width = <1920>; max_height = <1088>; - bit_per_pixel = <12>; + bit_per_pixel = <16>; frame_count = <3>; }; }; @@ -1253,7 +1317,15 @@ subdev_name = "vivcam"; idx = <0>; //sc2310 csi_idx = <0>; //<0>=CSI2 - path_type = "SENSOR_1080P_RAW12_LINER"; + mode_idx = <1>; + path_type = "SENSOR_1920X1088_26FPS_RAW12_LINER"; + }; + sensor1 { + subdev_name = "vivcam"; + idx = <6>; //gc02m1b + csi_idx = <0>; //<0>=CSI2 + mode_idx = <0>; + path_type = "SENSOR_1600x1200_RAW10_LINER"; }; isp { subdev_name = "isp"; @@ -1262,7 +1334,7 @@ output { max_width = <1920>; max_height = <1088>; - bit_per_pixel = <12>; + bit_per_pixel = <16>; frame_count = <3>; }; }; @@ -1276,7 +1348,15 @@ subdev_name = "vivcam"; idx = <0>; //sc2310 csi_idx = <0>; //<0>=CSI2 - path_type = "SENSOR_1080P_RAW12_LINER"; + mode_idx = <1>; + path_type = "SENSOR_1920X1088_26FPS_RAW12_LINER"; + }; + sensor1 { + subdev_name = "vivcam"; + idx = <6>; //gc02m1b + csi_idx = <0>; //<0>=CSI2 + mode_idx = <0>; + path_type = "SENSOR_1600x1200_RAW10_LINER"; }; isp { subdev_name = "isp"; @@ -1301,7 +1381,15 @@ subdev_name = "vivcam"; idx = <0>; //sc2310 csi_idx = <0>; //<0>=CSI2 - path_type = "SENSOR_1080P_RAW12_LINER"; + mode_idx = <1>; + path_type = "SENSOR_1920X1088_26FPS_RAW12_LINER"; + }; + sensor1 { + subdev_name = "vivcam"; + idx = <6>; //gc02m1b + csi_idx = <0>; //<0>=CSI2 + mode_idx = <0>; + path_type = "SENSOR_1600x1200_RAW10_LINER"; }; isp { subdev_name = "isp"; @@ -1326,7 +1414,15 @@ subdev_name = "vivcam"; idx = <0>; //sc2310 csi_idx = <0>; //<0>=CSI2 - path_type = "SENSOR_1080P_RAW12_LINER"; + mode_idx = <1>; + path_type = "SENSOR_1920X1088_26FPS_RAW12_LINER"; + }; + sensor1 { + subdev_name = "vivcam"; + idx = <6>; //gc02m1b + csi_idx = <0>; //<0>=CSI2 + mode_idx = <0>; + path_type = "SENSOR_1600x1200_RAW10_LINER"; }; isp { subdev_name = "isp"; @@ -1355,7 +1451,15 @@ subdev_name = "vivcam"; idx = <0>; //sc2310 csi_idx = <0>; //<0>=CSI2 - path_type = "SENSOR_1080P_RAW12_LINER"; + mode_idx = <1>; + path_type = "SENSOR_1920X1088_26FPS_RAW12_LINER"; + }; + sensor1 { + subdev_name = "vivcam"; + idx = <6>; //gc02m1b + csi_idx = <0>; //<0>=CSI2 + mode_idx = <0>; + path_type = "SENSOR_1600x1200_RAW10_LINER"; }; isp { subdev_name = "isp"; @@ -1396,7 +1500,15 @@ subdev_name = "vivcam"; idx = <0>; //sc2310 csi_idx = <0>; //<0>=CSI2 - path_type = "SENSOR_1080P_RAW12_LINER"; + mode_idx = <1>; + path_type = "SENSOR_1920X1088_26FPS_RAW12_LINER"; + }; + sensor1 { + subdev_name = "vivcam"; + idx = <6>; //gc02m1b + csi_idx = <0>; //<0>=CSI2 + mode_idx = <0>; + path_type = "SENSOR_1600x1200_RAW10_LINER"; }; isp { subdev_name = "isp"; @@ -1437,7 +1549,15 @@ subdev_name = "vivcam"; idx = <0>; //sc2310 csi_idx = <0>; //<0>=CSI2 - path_type = "SENSOR_1080P_RAW12_LINER"; + mode_idx = <1>; + path_type = "SENSOR_1920X1088_26FPS_RAW12_LINER"; + }; + sensor1 { + subdev_name = "vivcam"; + idx = <6>; //gc02m1b + csi_idx = <0>; //<0>=CSI2 + mode_idx = <0>; + path_type = "SENSOR_1600x1200_RAW10_LINER"; }; isp { subdev_name = "isp"; @@ -1482,7 +1602,15 @@ subdev_name = "vivcam"; idx = <0>; //sc2310 csi_idx = <0>; //<0>=CSI2 - path_type = "SENSOR_1080P_RAW12_LINER"; + mode_idx = <1>; + path_type = "SENSOR_1920X1088_26FPS_RAW12_LINER"; + }; + sensor1 { + subdev_name = "vivcam"; + idx = <6>; //gc02m1b + csi_idx = <0>; //<0>=CSI2 + mode_idx = <0>; + path_type = "SENSOR_1600x1200_RAW10_LINER"; }; isp { subdev_name = "isp"; @@ -1529,7 +1657,15 @@ subdev_name = "vivcam"; idx = <0>; //sc2310 csi_idx = <0>; //<0>=CSI2 - path_type = "SENSOR_1080P_RAW12_LINER"; + mode_idx = <1>; + path_type = "SENSOR_1920X1088_26FPS_RAW12_LINER"; + }; + sensor1 { + subdev_name = "vivcam"; + idx = <6>; //gc02m1b + csi_idx = <0>; //<0>=CSI2 + mode_idx = <0>; + path_type = "SENSOR_1600x1200_RAW10_LINER"; }; isp { subdev_name = "isp"; @@ -1576,7 +1712,15 @@ subdev_name = "vivcam"; idx = <0>; //sc2310 csi_idx = <0>; //<0>=CSI2 - path_type = "SENSOR_1080P_RAW12_LINER"; + mode_idx = <1>; + path_type = "SENSOR_1920X1088_26FPS_RAW12_LINER"; + }; + sensor1 { + subdev_name = "vivcam"; + idx = <6>; //gc02m1b + csi_idx = <0>; //<0>=CSI2 + mode_idx = <0>; + path_type = "SENSOR_1600x1200_RAW10_LINER"; }; isp { subdev_name = "isp"; @@ -1628,7 +1772,8 @@ idx = <4>; //sc132gs csi_idx = <2>; //<2>=CSI2X2_A flash_led_idx = <0>; - path_type = "SENSOR_1080P_RAW10_LINER"; + mode_idx = <0>; + path_type = "SENSOR_1080X1280_30FPS_RAW10_LINER"; }; dsp{ output { @@ -1645,7 +1790,8 @@ idx = <4>; //sc132gs csi_idx = <2>; //<2>=CSI2X2_A flash_led_idx = <0>; - path_type = "SENSOR_1080P_RAW10_LINER"; + mode_idx = <0>; + path_type = "SENSOR_1080X1280_30FPS_RAW10_LINER"; }; dsp{ output { @@ -1664,13 +1810,15 @@ subdev_name = "vivcam"; idx = <2>; //<2>=vivcam2 : gc5035 csi_idx = <1>; //<1>=CSI2X2_B - path_type = "SENSOR_1080P_RAW10_LINER"; //SENSOR_VGA_RAW10_LINER// + mode_idx = <3>; + path_type = "SENSOR_1296x972_RAW10_LINER"; //SENSOR_VGA_RAW10_LINER// }; sensor1 { subdev_name = "vivcam"; idx = <3>; //<3>=vivcam3 : sc2310 csi_idx = <1>; //<1>=CSI2X2_B - path_type = "SENSOR_1080P_RAW12_LINER"; + mode_idx = <1>; + path_type = "SENSOR_1920X1088_26FPS_RAW12_LINER"; }; isp { subdev_name = "isp"; @@ -1717,13 +1865,15 @@ subdev_name = "vivcam"; idx = <2>; //<2>=vivcam2 : gc5035 csi_idx = <1>; //<1>=CSI2X2_B - path_type = "SENSOR_1080P_RAW10_LINER"; //SENSOR_VGA_RAW10_LINER// + mode_idx = <3>; + path_type = "SENSOR_1296x972_RAW10_LINER"; //SENSOR_VGA_RAW10_LINER// }; sensor1 { subdev_name = "vivcam"; idx = <3>; //<3>=vivcam3 : sc2310 csi_idx = <1>; //<1>=CSI2X2_B - path_type = "SENSOR_1080P_RAW12_LINER"; + mode_idx = <1>; + path_type = "SENSOR_1920X1088_26FPS_RAW12_LINER"; }; isp { subdev_name = "isp"; @@ -1770,13 +1920,15 @@ subdev_name = "vivcam"; idx = <2>; //<2>=vivcam2 : gc5035 csi_idx = <1>; //<1>=CSI2X2_B - path_type = "SENSOR_1080P_RAW10_LINER"; //SENSOR_VGA_RAW10_LINER// + mode_idx = <3>; + path_type = "SENSOR_1296x972_RAW10_LINER"; //SENSOR_VGA_RAW10_LINER// }; sensor1 { subdev_name = "vivcam"; idx = <3>; //<3>=vivcam3 : sc2310 csi_idx = <1>; //<1>=CSI2X2_B - path_type = "SENSOR_1080P_RAW12_LINER"; + mode_idx = <1>; + path_type = "SENSOR_1920X1088_26FPS_RAW12_LINER"; }; isp { subdev_name = "isp"; @@ -1828,13 +1980,15 @@ subdev_name = "vivcam"; idx = <2>; //<2>=vivcam2 : gc5035 csi_idx = <1>; //<1>=CSI2X2_B - path_type = "SENSOR_1080P_RAW10_LINER"; //SENSOR_VGA_RAW10_LINER// + mode_idx = <3>; + path_type = "SENSOR_1296x972_RAW10_LINER"; //SENSOR_VGA_RAW10_LINER// }; sensor1 { subdev_name = "vivcam"; idx = <3>; //<3>=vivcam3 : sc2310 csi_idx = <1>; //<1>=CSI2X2_B - path_type = "SENSOR_1080P_RAW12_LINER"; + mode_idx = <1>; + path_type = "SENSOR_1920X1088_26FPS_RAW12_LINER"; }; dsp { subdev_name = "dsp"; @@ -1856,7 +2010,8 @@ subdev_name = "vivcam"; idx = <4>; //sc132gs csi_idx = <2>; //<2>=CSI2X2_A - path_type = "SENSOR_1080P_RAW10_LINER"; + mode_idx = <0>; + path_type = "SENSOR_1080X1280_30FPS_RAW10_LINER"; }; dsp{ output { @@ -1876,13 +2031,17 @@ subdev_name = "vivcam"; idx = <2>; //<2>=vivcam2 : gc5035 csi_idx = <1>; //<1>=CSI2X2_B + mode_idx = <1>; path_type = "SENSOR_1080P_RAW10_LINER"; //SENSOR_VGA_RAW10_LINER// + skip_init = <1>; }; sensor1 { subdev_name = "vivcam"; idx = <3>; //<3>=vivcam3 : sc2310 csi_idx = <1>; //<1>=CSI2X2_B - path_type = "SENSOR_1080P_RAW12_LINER"; + mode_idx = <1>; + path_type = "SENSOR_1920X1088_26FPS_RAW12_LINER"; + skip_init = <1>; }; }; }; @@ -1896,7 +2055,8 @@ idx = <4>; //sc132gs csi_idx = <2>; //<2>=CSI2X2_A flash_led_idx = <0>; - path_type = "SENSOR_1080P_RAW10_LINER"; + mode_idx = <0>; + path_type = "SENSOR_1080X1280_30FPS_RAW10_LINER"; }; isp { subdev_name = "isp"; @@ -1912,13 +2072,22 @@ }; }; -&video12{ +&video12{ // TUNINGTOOL pipline0 { // CSI2 sensor0 { subdev_name = "vivcam"; idx = <0>; //sc2310 csi_idx = <0>; //<0>=CSI2 - path_type = "SENSOR_1080P_RAW12_LINER"; + mode_idx = <1>; + path_type = "SENSOR_1920X1088_26FPS_RAW12_LINER"; + skip_init = <1>; + }; + sensor1 { + subdev_name = "vivcam"; + idx = <6>; //gc02m1b + csi_idx = <0>; //<0>=CSI2 + mode_idx = <0>; + path_type = "SENSOR_1600x1200_RAW10_LINER"; skip_init = <1>; }; }; @@ -1963,3 +2132,71 @@ status = "okay"; }; +&cpus { + c910_0: cpu@0 { + operating-points = < + /* kHz uV */ + 300000 650000 + 800000 700000 + 1500000 800000 + 1848000 1000000 + >; + light,dvddm-operating-points = < + /* kHz uV */ + 300000 800000 + 800000 800000 + 1500000 800000 + 1848000 1000000 + >; + }; + c910_1: cpu@1 { + operating-points = < + /* kHz uV */ + 300000 650000 + 800000 700000 + 1500000 800000 + 1848000 1000000 + >; + light,dvddm-operating-points = < + /* kHz uV */ + 300000 800000 + 800000 800000 + 1500000 800000 + 1848000 1000000 + >; + }; + c910_2: cpu@2 { + + operating-points = < + /* kHz uV */ + 300000 650000 + 800000 700000 + 1500000 800000 + 1848000 1000000 + >; + light,dvddm-operating-points = < + /* kHz uV */ + 300000 800000 + 800000 800000 + 1500000 800000 + 1848000 1000000 + >; + }; + c910_3: cpu@3 { + + operating-points = < + /* kHz uV */ + 300000 650000 + 800000 700000 + 1500000 800000 + 1848000 1000000 + >; + light,dvddm-operating-points = < + /* kHz uV */ + 300000 800000 + 800000 800000 + 1500000 800000 + 1848000 1000000 + >; + }; +}; diff --git a/arch/riscv/boot/dts/thead/light-ant-discrete-crash.dts b/arch/riscv/boot/dts/thead/light-ant-discrete-crash.dts new file mode 100644 index 000000000..1bf6121a7 --- /dev/null +++ b/arch/riscv/boot/dts/thead/light-ant-discrete-crash.dts @@ -0,0 +1,88 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Copyright (C) 2022 Alibaba Group Holding Limited. + */ + +#include "light-crash.dts" + +&aon { + aon_reg_dialog: light-dialog-reg { + compatible = "thead,light-dialog-pmic-ant"; + status = "okay"; + + dvdd_cpu_reg: appcpu_dvdd { + regulator-name = "appcpu_dvdd"; + regulator-min-microvolt = <300000>; + regulator-max-microvolt = <1570000>; + regulator-boot-on; + regulator-always-on; + }; + + dvddm_cpu_reg: appcpu_dvddm { + regulator-name = "appcpu_dvddm"; + regulator-min-microvolt = <300000>; + regulator-max-microvolt = <1570000>; + regulator-boot-on; + regulator-always-on; + }; + }; +}; + +&cpus { + c910_0: cpu@0 { + operating-points = < + /* kHz uV */ + 300000 720000 + 800000 720000 + 1500000 820000 + >; + light,dvddm-operating-points = < + /* kHz uV */ + 300000 770000 + 800000 820000 + 1500000 820000 + >; + }; + c910_1: cpu@1 { + operating-points = < + /* kHz uV */ + 300000 720000 + 800000 720000 + 1500000 820000 + >; + light,dvddm-operating-points = < + /* kHz uV */ + 300000 770000 + 800000 820000 + 1500000 820000 + >; + }; + c910_2: cpu@2 { + operating-points = < + /* kHz uV */ + 300000 720000 + 800000 720000 + 1500000 820000 + >; + light,dvddm-operating-points = < + /* kHz uV */ + 300000 770000 + 800000 820000 + 1500000 820000 + >; + }; + c910_3: cpu@3 { + operating-points = < + /* kHz uV */ + 300000 720000 + 800000 720000 + 1500000 820000 + >; + light,dvddm-operating-points = < + /* kHz uV */ + 300000 770000 + 800000 820000 + 1500000 820000 + >; + }; +}; diff --git a/arch/riscv/boot/dts/thead/light-ant-discrete.dts b/arch/riscv/boot/dts/thead/light-ant-discrete.dts index d5e11cb9c..db7ae5bb6 100644 --- a/arch/riscv/boot/dts/thead/light-ant-discrete.dts +++ b/arch/riscv/boot/dts/thead/light-ant-discrete.dts @@ -8,7 +8,7 @@ #include "light.dtsi" #include #include - +#include "light-vi-devices.dtsi" / { model = "T-HEAD Light val board"; compatible = "thead,light-val", "thead,light"; @@ -20,8 +20,6 @@ chosen { bootargs = "console=ttyS0,115200 crashkernel=256M-:128M earlycon clk_ignore_unused sram=0xffe0000000,0x180000"; - linux,initrd-start = <0x0 0x2000000>; - linux,initrd-end = <0x0 0x14600000>; stdout-path = "serial0:115200n8"; }; @@ -304,7 +302,6 @@ regulator-max-microvolt = <5700000>; gpio = <&gpio1_porta 10 1>; enable-active-high; - regulator-always-on; }; soc_vdd18_lcd0_en_reg: soc_lcd0_en { @@ -314,7 +311,6 @@ regulator-max-microvolt = <1800000>; gpio = <&gpio1_porta 9 1>; enable-active-high; - regulator-always-on; }; soc_vdd5v_se_en_reg: soc_vdd5v_se_en { @@ -355,7 +351,6 @@ regulator-max-microvolt = <2800000>; gpio = <&gpio1_porta 15 1>; enable-active-high; - regulator-always-on; }; soc_dovdd18_rgb_reg: soc_dovdd18_rgb { @@ -365,7 +360,6 @@ regulator-max-microvolt = <2800000>; gpio = <&gpio1_porta 13 1>; enable-active-high; - regulator-always-on; }; soc_dvdd12_rgb_reg: soc_dvdd12_rgb { @@ -375,7 +369,6 @@ regulator-max-microvolt = <2800000>; gpio = <&gpio1_porta 14 1>; enable-active-high; - regulator-always-on; }; soc_avdd25_ir_reg: soc_avdd25_ir { @@ -385,7 +378,6 @@ regulator-max-microvolt = <2500000>; gpio = <&gpio0_porta 28 1>; enable-active-high; - regulator-always-on; }; soc_dovdd18_ir_reg: soc_dovdd18_ir { @@ -395,7 +387,6 @@ regulator-max-microvolt = <1800000>; gpio = <&gpio1_porta 13 1>; enable-active-high; - regulator-always-on; }; soc_dvdd12_ir_reg: soc_dvdd12_ir { @@ -405,7 +396,6 @@ regulator-max-microvolt = <1200000>; gpio = <&gpio0_porta 29 1>; enable-active-high; - regulator-always-on; }; aon_reg_dialog: light-dialog-reg { @@ -531,27 +521,33 @@ #size-cells = <2>; ranges; - tee_mem: memory@1a000000 { - reg = <0x0 0x1a000000 0 0x4000000>; + tee_mem: memory@1c000000 { + reg = <0x0 0x1c000000 0 0x2000000>; no-map; }; - dsp0_mem: memory@20000000 { /**0x20000000~0x21fffffff**/ - reg = <0x0 0x20000000 0x0 0x01000000 /* DSP FW code&data section */ - 0x0 0x21000000 0x0 0x00001000 /* DSP communication area */ - 0x0 0x21001000 0x0 0x00002000 /* Panic/log page*/ - 0x0 0x21003000 0x0 0x00ffd000>; /* DSP shared memory */ + dsp0_mem: memory@20000000 { /**0x2000_0000~0x2040_0000 4M**/ + reg = <0x0 0x20000000 0x0 0x00280000 /* DSP FW code&data section 2.5M*/ + 0x0 0x20280000 0x0 0x00001000 /* DSP communication area 4K*/ + 0x0 0x20281000 0x0 0x00007000 /* Panic/log page 28K */ + 0x0 0x20288000 0x0 0x00178000>; /* DSP shared memory 1.5M-32K*/ no-map; }; - dsp1_mem: memory@24000000 { /**0x24000000~0x25ffffff**/ - reg = <0x0 0x24000000 0x0 0x01000000 /* DSP FW code&data section */ - 0x0 0x25000000 0x0 0x00001000 /* DSP communication area */ - 0x0 0x25001000 0x0 0x00002000 /* Panic/log page*/ - 0x0 0x25003000 0x0 0x00ffd000>; /* DSP shared memory */ + dsp1_mem: memory@20400000 { /**0x2040_0000~0x2080_0000 4M**/ + reg = <0x0 0x20400000 0x0 0x00280000 /* DSP FW code&data section */ + 0x0 0x20680000 0x0 0x00001000 /* DSP communication area */ + 0x0 0x20681000 0x0 0x00007000 /* Panic/log page*/ + 0x0 0x20688000 0x0 0x00178000>; /* DSP shared memory */ no-map; }; - facelib_mem: memory@33000000 { - reg = <0x0 0x33000000 0 0x02000000>; + vi_mem: framebuffer@10000000 { + reg = <0x0 0x10000000 0x0 0x02C00000 /* vi_mem_pool_region[0] 44 MB (default) */ + 0x0 0x12C00000 0x0 0x01D00000 /* vi_mem_pool_region[1] 29 MB */ + 0x0 0x14900000 0x0 0x01E00000>; /* vi_mem_pool_region[2] 30 MB */ + no-map; + }; + facelib_mem: memory@17000000 { + reg = <0x0 0x17000000 0 0x02000000>; no-map; }; }; @@ -596,11 +592,13 @@ compatible = "MicArray_0"; reg = <0x40>; }; - audio_aw87519_pa@58 { - compatible = "awinic,aw87519_pa"; - reg = <0x58>; - status = "okay"; - }; + + audio_aw87519_pa@58 { + compatible = "awinic,aw87519_pa"; + reg = <0x58>; + reset-gpio = <&ao_gpio4_porta 9 0x1>; + status = "okay"; + }; }; &i2c1 { @@ -733,6 +731,7 @@ no-mmc; non-removable; io_fixed_1v8; + post-power-on-delay-ms = <50>; wprtn_ignore; cap-sd-highspeed; keep-power-in-suspend; @@ -867,22 +866,27 @@ }; &i2c0 { + clock-frequency = <400000>; status = "okay"; }; &i2c1 { + clock-frequency = <400000>; status = "okay"; }; &i2c2 { + clock-frequency = <400000>; status = "okay"; }; &i2c3 { + clock-frequency = <400000>; status = "okay"; }; &i2c4 { + clock-frequency = <400000>; status = "okay"; }; @@ -966,7 +970,7 @@ sensor_regulator_timing_us = <70 50 20>; sensor_pdn = <&gpio1_porta 21 0>; //powerdown pin / shutdown pin sensor_rst = <&gpio1_porta 16 0>; - sensor_pdn_delay_us = <1000>; //powerdown pin / shutdown pin actived till I2C ready + sensor_pdn_delay_us = <4000>; //powerdown pin / shutdown pin actived till I2C ready DOVDD18_RGB-supply = <&soc_dovdd18_rgb_reg>; DVDD12_RGB-supply = <&soc_dvdd12_rgb_reg>; AVDD28_RGB-supply = <&soc_avdd28_rgb_reg>; @@ -980,11 +984,11 @@ &vvcam_sensor1 { sensor_name = "SC132GS"; sensor_regulators = "DOVDD18_IR", "DVDD12_IR", "AVDD25_IR"; - sensor_regulator_timing_us = <70 50 20>; + sensor_regulator_timing_us = <70 1000 2000>; i2c_addr = /bits/ 8 <0x31>; sensor_pdn = <&gpio1_porta 28 0>; //powerdown pin / shutdown pin sensor_rst = <&gpio1_porta 24 0>; - sensor_pdn_delay_us = <1000>; //powerdown pin / shutdown pin actived till I2C ready + sensor_pdn_delay_us = <2000>; //powerdown pin / shutdown pin actived till I2C ready DOVDD18_IR-supply = <&soc_dovdd18_ir_reg>; DVDD12_IR-supply = <&soc_dvdd12_ir_reg>; AVDD25_IR-supply = <&soc_avdd25_ir_reg>; @@ -1011,906 +1015,959 @@ status = "okay"; }; -&video0{ +&vvcam_sensor3 { + sensor_name = "GC02M1B"; + sensor_regulators = "DOVDD18_SCAN", "DVDD12_SCAN", "AVDD28_SCAN"; + sensor_regulator_timing_us = <100 50 0>; + sensor_pdn = <&gpio1_porta 30 0>; //powerdown pin / shutdown pin + sensor_rst = <&gpio1_porta 29 0>; + sensor_pdn_delay_us = <1000>; //powerdown pin / shutdown pin actived till I2C ready + DOVDD18_SCAN-supply = <&soc_dovdd18_scan_reg>; + DVDD12_SCAN-supply = <&soc_dvdd12_scan_reg>; + AVDD28_SCAN-supply = <&soc_avdd28_scan_en_reg>; + i2c_addr = /bits/ 8 <0x37>; + i2c_bus = /bits/ 8 <4>; + i2c_reg_width = /bits/ 8 <1>; + i2c_data_width = /bits/ 8 <1>; status = "okay"; - piplane0 { - pipline_id = <0>; - status = "okay"; +}; + +&video0{ + vi_mem_pool_region = <2>; // vi_mem: framebuffer, region[2] + pipline0 { sensor0 { subdev_name = "vivcam"; idx = <2>; //<2>=vivcam2 : gc5035 csi_idx = <1>; //<1>=CSI2X2_B - path_type = "SENSOR_VGA_RAW10_LINER"; //SENSOR_VGA_RAW10_LINER//SENSOR_1080P_RAW10_LINER + mode_idx = <3>; + path_type = "SENSOR_1296x972_RAW10_LINER"; //SENSOR_VGA_RAW10_LINER// }; - dma { - subdev_name = "vipre"; - idx = <0>; - path_type = "VIPRE_CSI1_ISP0"; + sensor1 { + subdev_name = "vivcam"; + idx = <3>; //<3>=vivcam3 : gc02m1b + csi_idx = <1>; //<1>=CSI2X2_B + mode_idx = <0>; + path_type = "SENSOR_1600x1200_RAW10_LINER"; }; isp { subdev_name = "isp"; idx = <0>; path_type = "ISP_MI_PATH_MP"; - }; - dw { - subdev_name = "dw"; - idx = <0>; - path_type = "DW_DWE_VSE0"; + output { + max_width = <1920>; + max_height = <1088>; + bit_per_pixel = <12>; + frame_count = <3>; + }; }; }; - piplane1 { - pipline_id = <0>; - status = "okay"; + pipline1 { sensor0 { subdev_name = "vivcam"; idx = <2>; //<2>=vivcam2 : gc5035 csi_idx = <1>; //<1>=CSI2X2_B - path_type = "SENSOR_VGA_RAW10_LINER"; //SENSOR_1080P_RAW10_LINER + mode_idx = <3>; + path_type = "SENSOR_1296x972_RAW10_LINER"; //SENSOR_VGA_RAW10_LINER// }; - dma { - subdev_name = "vipre"; - idx = <0>; - path_type = "VIPRE_CSI1_ISP0"; + sensor1 { + subdev_name = "vivcam"; + idx = <3>; //<3>=vivcam3 : gc02m1b + csi_idx = <1>; //<1>=CSI2X2_B + mode_idx = <0>; + path_type = "SENSOR_1600x1200_RAW10_LINER"; }; isp { subdev_name = "isp"; idx = <0>; - path_type = "ISP_MI_PATH_MP"; - }; - dw { - subdev_name = "dw"; - idx = <0>; - path_type = "DW_DWE_VSE1"; + path_type = "ISP_MI_PATH_SP"; + output { + max_width = <1920>; + max_height = <1088>; + bit_per_pixel = <12>; + frame_count = <3>; + }; }; }; - piplane2 { - pipline_id = <0>; - status = "okay"; + pipline2 { sensor0 { subdev_name = "vivcam"; idx = <2>; //<2>=vivcam2 : gc5035 csi_idx = <1>; //<1>=CSI2X2_B - path_type = "SENSOR_VGA_RAW10_LINER"; //SENSOR_1080P_RAW10_LINER + mode_idx = <3>; + path_type = "SENSOR_1296x972_RAW10_LINER"; //SENSOR_VGA_RAW10_LINER// }; - dma { - subdev_name = "vipre"; - idx = <0>; - path_type = "VIPRE_CSI1_ISP0"; + sensor1 { + subdev_name = "vivcam"; + idx = <3>; //<3>=vivcam3 : gc02m1b + csi_idx = <1>; //<1>=CSI2X2_B + mode_idx = <0>; + path_type = "SENSOR_1600x1200_RAW10_LINER"; }; isp { subdev_name = "isp"; idx = <0>; path_type = "ISP_MI_PATH_SP2_BP"; - }; - }; - piplane3 { // full size pipeline - pipline_id = <0>; - status = "okay"; - sensor0 { - subdev_name = "vivcam"; - idx = <2>; //<2>=vivcam2 : gc5035 - csi_idx = <1>; //<1>=CSI2X2_B - path_type = "SENSOR_2592x1944_RAW10_LINER"; - }; - dma { - subdev_name = "vipre"; - idx = <0>; - path_type = "VIPRE_CSI1_ISP0"; - }; - isp { - subdev_name = "isp"; - idx = <0>; - path_type = "ISP_MI_PATH_MP"; - }; - dw { - subdev_name = "dw"; - idx = <0>; - path_type = "DW_DWE_VSE0"; + output { + max_width = <1920>; + max_height = <1088>; + bit_per_pixel = <12>; + frame_count = <3>; + }; }; }; }; + &video1{ - status = "okay"; - piplane0 { - pipline_id = <0>; - status = "okay"; + vi_mem_pool_region = <2>; // vi_mem: framebuffer, region[2] + pipline0 { sensor0 { subdev_name = "vivcam"; idx = <2>; //<2>=vivcam2 : gc5035 csi_idx = <1>; //<1>=CSI2X2_B - path_type = "SENSOR_VGA_RAW10_LINER"; //SENSOR_1080P_RAW10_LINER + mode_idx = <3>; + path_type = "SENSOR_1296x972_RAW10_LINER"; }; - dma { - subdev_name = "vipre"; - idx = <0>; - path_type = "VIPRE_CSI1_ISP0"; + sensor1 { + subdev_name = "vivcam"; + idx = <3>; //<3>=vivcam3 : gc02m1b + csi_idx = <1>; //<1>=CSI2X2_B + mode_idx = <0>; + path_type = "SENSOR_1600x1200_RAW10_LINER"; }; isp { subdev_name = "isp"; idx = <0>; - path_type = "ISP_MI_PATH_PP"; - }; - dsp { - subdev_name = "dsp"; - idx = <0>; - path_type = "DSP_PATH_ISP_RY"; - }; - ry { - subdev_name = "ry"; - idx = <0>; - path_type = "ISP_RY_MI_PATH_MP"; + path_type = "ISP_MI_PATH_MP"; + output { + max_width = <1920>; + max_height = <1088>; + bit_per_pixel = <12>; + frame_count = <3>; + }; }; dw { subdev_name = "dw"; idx = <0>; path_type = "DW_DWE_VSE0"; + dw_dst_depth = <2>; }; - }; -}; - - -&video2{ - status = "okay"; - piplane0 { - pipline_id = <0>; - status = "okay"; + pipline1 { sensor0 { subdev_name = "vivcam"; idx = <2>; //<2>=vivcam2 : gc5035 csi_idx = <1>; //<1>=CSI2X2_B - path_type = "SENSOR_VGA_RAW10_LINER"; //SENSOR_1080P_RAW10_LINER + mode_idx = <3>; + path_type = "SENSOR_1296x972_RAW10_LINER"; }; - dma { - subdev_name = "vipre"; - idx = <0>; - path_type = "VIPRE_CSI1_DDR"; - }; - dsp { - subdev_name = "dsp"; - idx = <1>; - path_type = "DSP_PATH_VIPRE_DDR"; - }; - }; -}; - -&video3{ - status = "okay"; - piplane0 { - pipline_id = <0>; - status = "okay"; - sensor0 { + sensor1 { subdev_name = "vivcam"; - idx = <2>; //<2>=vivcam2 : gc5035 + idx = <3>; //<3>=vivcam3 : gc02m1b csi_idx = <1>; //<1>=CSI2X2_B - path_type = "SENSOR_VGA_RAW10_LINER"; //SENSOR_1080P_RAW10_LINER - }; - dma { - subdev_name = "vipre"; - idx = <0>; - path_type = "VIPRE_CSI1_ISP0"; - }; - isp { - subdev_name = "isp"; - idx = <0>; - path_type = "ISP_MI_PATH_MP"; - }; - }; - piplane1 { - pipline_id = <1>; - status = "okay"; - sensor0 { - subdev_name = "vivcam"; - idx = <2>; //<2>=vivcam2 : gc5035 - csi_idx = <1>; //<1>=CSI2X2_B - path_type = "SENSOR_VGA_RAW10_LINER"; //SENSOR_1080P_RAW10_LINER - }; - dma { - subdev_name = "vipre"; - idx = <0>; - path_type = "VIPRE_CSI1_ISP0"; - }; - isp { - subdev_name = "isp"; - idx = <0>; - path_type = "ISP_MI_PATH_SP"; - }; - }; - piplane2 { - pipline_id = <2>; - status = "okay"; - sensor0 { - subdev_name = "vivcam"; - idx = <2>; //<2>=vivcam2 : gc5035 - csi_idx = <1>; //<1>=CSI2X2_B - path_type = "SENSOR_VGA_RAW10_LINER"; //SENSOR_1080P_RAW10_LINER - }; - dma { - subdev_name = "vipre"; - idx = <0>; - path_type = "VIPRE_CSI1_ISP0"; - }; - isp { - subdev_name = "isp"; - idx = <0>; - path_type = "ISP_MI_PATH_SP2_BP"; - }; - }; - piplane3 { - pipline_id = <3>; - status = "okay"; - sensor0 { - subdev_name = "vivcam"; - idx = <2>; //<2>=vivcam2 : gc5035 - csi_idx = <1>; //<1>=CSI2X2_B - path_type = "SENSOR_1080P_RAW10_LINER"; //SENSOR_1080P_RAW10_LINER - }; - dma { - subdev_name = "vipre"; - idx = <0>; - path_type = "VIPRE_CSI1_ISP0"; - }; - isp { - subdev_name = "isp"; - idx = <0>; - path_type = "ISP_MI_PATH_MP"; - }; - }; - piplane4 { - pipline_id = <2>; - status = "okay"; - sensor0 { - subdev_name = "vivcam"; - idx = <2>; //<2>=vivcam2 : gc5035 - csi_idx = <1>; //<1>=CSI2X2_B - path_type = "SENSOR_2592x1944_RAW10_LINER"; //SENSOR_1080P_RAW10_LINER - }; - dma { - subdev_name = "vipre"; - idx = <0>; - path_type = "VIPRE_CSI1_ISP0"; - }; - isp { - subdev_name = "isp"; - idx = <0>; - path_type = "ISP_MI_PATH_MP"; - }; - }; - piplane5 { - pipline_id = <5>; - status = "okay"; - sensor0 { - subdev_name = "vivcam"; - idx = <2>; //<2>=vivcam2 : gc5035 - csi_idx = <1>; //<1>=CSI2X2_B - path_type = "SENSOR_1280x720_RAW10_LINER"; //SENSOR_1080P_RAW10_LINER - }; - dma { - subdev_name = "vipre"; - idx = <0>; - path_type = "VIPRE_CSI1_ISP0"; - }; - isp { - subdev_name = "isp"; - idx = <0>; - path_type = "ISP_MI_PATH_MP"; - }; - }; -}; - -&video4{ - status = "okay"; - piplane0 { - pipline_id = <0>; - status = "okay"; - sensor0 { - subdev_name = "vivcam"; - idx = <2>; //<2>=vivcam2 : gc5035 - csi_idx = <1>; //<1>=CSI2X2_B - path_type = "SENSOR_VGA_RAW10_LINER"; //SENSOR_1080P_RAW10_LINER - }; - dma { - subdev_name = "vipre"; - idx = <0>; - path_type = "VIPRE_CSI1_ISP1"; - }; - isp { - subdev_name = "isp"; - idx = <1>; - path_type = "ISP_MI_PATH_MP"; - }; - }; - piplane1 { - pipline_id = <1>; - status = "okay"; - sensor0 { - subdev_name = "vivcam"; - idx = <2>; //<2>=vivcam2 : gc5035 - csi_idx = <1>; //<1>=CSI2X2_B - path_type = "SENSOR_VGA_RAW10_LINER"; //SENSOR_1080P_RAW10_LINER - }; - dma { - subdev_name = "vipre"; - idx = <0>; - path_type = "VIPRE_CSI1_ISP1"; - }; - isp { - subdev_name = "isp"; - idx = <1>; - path_type = "ISP_MI_PATH_SP"; - }; - }; - piplane2 { - pipline_id = <2>; - status = "okay"; - sensor0 { - subdev_name = "vivcam"; - idx = <2>; //<2>=vivcam2 : gc5035 - csi_idx = <1>; //<1>=CSI2X2_B - path_type = "SENSOR_VGA_RAW10_LINER"; //SENSOR_1080P_RAW10_LINER - }; - dma { - subdev_name = "vipre"; - idx = <0>; - path_type = "VIPRE_CSI1_ISP1"; - }; - isp { - subdev_name = "isp"; - idx = <1>; - path_type = "ISP_MI_PATH_SP2_BP"; - }; - }; - piplane3 { - pipline_id = <3>; - status = "okay"; - sensor0 { - subdev_name = "vivcam"; - idx = <2>; //<2>=vivcam2 : gc5035 - csi_idx = <1>; //<1>=CSI2X2_B - path_type = "SENSOR_VGA_RAW10_LINER"; //SENSOR_1080P_RAW10_LINER - }; - dma { - subdev_name = "vipre"; - idx = <0>; - path_type = "VIPRE_CSI1_ISP1"; - }; - isp { - subdev_name = "isp"; - idx = <1>; - path_type = "ISP_MI_PATH_MP"; - }; - }; -}; - -&video5 { - status = "okay"; - piplane0 { - pipline_id = <0>; - status = "okay"; - sensor0 { - subdev_name = "vivcam"; - idx = <1>; //sc132gs - csi_idx = <2>; //<2>=CSI2X2_A - path_type = "SENSOR_1080P_RAW10_LINER"; - }; - dma { - subdev_name = "vipre"; - idx = <0>; - path_type = "VIPRE_CSI2_ISP0"; - }; - isp { - subdev_name = "isp"; - idx = <0>; - path_type = "ISP_MI_PATH_MP"; - }; - }; - piplane1 { - pipline_id = <1>; - status = "okay"; - sensor0 { - subdev_name = "vivcam"; - idx = <0>; //sc2310 - csi_idx = <0>; //<0>=CSI2 - path_type = "SENSOR_1080P_RAW12_LINER"; - }; - dma { - subdev_name = "vipre"; - idx = <0>; - path_type = "VIPRE_CSI0_ISP0"; - }; - isp { - subdev_name = "isp"; - idx = <0>; - path_type = "ISP_MI_PATH_MP"; - }; - }; -}; - -&video6{ // TUNING TOOL - status = "okay"; - piplane0 { // CSI2X2_B - status = "okay"; - sensor0 { - subdev_name = "vivcam"; - idx = <2>; //<2>=vivcam2 : gc5035 - csi_idx = <1>; //<1>=CSI2X2_B - path_type = "SENSOR_VGA_RAW10_LINER"; // SENSOR_VGA_RAW10_LINER SENSOR_1080P_RAW10_LINER SENSOR_2592x1944_RAW10_LINER - skip_init = <1>; - }; - dma { - subdev_name = "vipre"; - idx = <0>; - path_type = "VIPRE_CSI1_ISP0"; - }; - }; -}; - -&video7{ // DW200 - status = "okay"; - piplane0 { // VSE0 - pipline_id = <0>; - status = "okay"; - sensor0 { - subdev_name = "vivcam"; - idx = <2>; //<2>=vivcam2 : gc5035 - csi_idx = <1>; //<1>=CSI2X2_B - path_type = "SENSOR_VGA_RAW10_LINER"; //SENSOR_VGA_RAW10_LINER//SENSOR_1080P_RAW10_LINER - }; - dma { - subdev_name = "vipre"; - idx = <0>; - path_type = "VIPRE_CSI1_ISP0"; - }; - isp { - subdev_name = "isp"; - idx = <0>; - path_type = "ISP_MI_PATH_MP"; - }; - dw { - subdev_name = "dw"; - idx = <0>; - path_type = "DW_DWE_VSE0"; - }; - }; - piplane1 { // VSE1 - pipline_id = <0>; - status = "okay"; - sensor0 { - subdev_name = "vivcam"; - idx = <2>; //<2>=vivcam2 : gc5035 - csi_idx = <1>; //<1>=CSI2X2_B - path_type = "SENSOR_VGA_RAW10_LINER"; //SENSOR_1080P_RAW10_LINER - }; - dma { - subdev_name = "vipre"; - idx = <0>; - path_type = "VIPRE_CSI1_ISP0"; + mode_idx = <0>; + path_type = "SENSOR_1600x1200_RAW10_LINER"; }; isp { subdev_name = "isp"; idx = <0>; path_type = "ISP_MI_PATH_MP"; + output { + max_width = <1920>; + max_height = <1088>; + bit_per_pixel = <12>; + frame_count = <3>; + }; }; dw { subdev_name = "dw"; idx = <0>; path_type = "DW_DWE_VSE1"; + dw_dst_depth = <2>; }; }; - piplane2 { // VSE2 - pipline_id = <0>; - status = "okay"; + pipline2 { sensor0 { subdev_name = "vivcam"; idx = <2>; //<2>=vivcam2 : gc5035 csi_idx = <1>; //<1>=CSI2X2_B - path_type = "SENSOR_VGA_RAW10_LINER"; //SENSOR_1080P_RAW10_LINER + mode_idx = <3>; + path_type = "SENSOR_1296x972_RAW10_LINER"; }; - dma { - subdev_name = "vipre"; - idx = <0>; - path_type = "VIPRE_CSI1_ISP0"; + sensor1 { + subdev_name = "vivcam"; + idx = <3>; //<3>=vivcam3 : gc02m1b + csi_idx = <1>; //<1>=CSI2X2_B + mode_idx = <0>; + path_type = "SENSOR_1600x1200_RAW10_LINER"; }; isp { subdev_name = "isp"; idx = <0>; path_type = "ISP_MI_PATH_MP"; + output { + max_width = <1920>; + max_height = <1088>; + bit_per_pixel = <12>; + frame_count = <3>; + }; }; dw { subdev_name = "dw"; idx = <0>; path_type = "DW_DWE_VSE2"; - }; - }; - piplane3 { // multi instance - pipline_id = <0>; - status = "okay"; - sensor0 { - subdev_name = "vivcam"; - idx = <2>; //<2>=vivcam2 : gc5035 - csi_idx = <1>; //<1>=CSI2X2_B - path_type = "SENSOR_1080P_RAW10_LINER"; //SENSOR_VGA_RAW10_LINER//SENSOR_1080P_RAW10_LINER - }; - dma { - subdev_name = "vipre"; - idx = <0>; - path_type = "VIPRE_CSI1_ISP1"; - }; - isp { - subdev_name = "isp"; - idx = <1>; - path_type = "ISP_MI_PATH_MP"; - }; - dw { - subdev_name = "dw"; - idx = <0>; - path_type = "DW_DWE_VSE0"; + dw_dst_depth = <2>; }; }; }; -&video8 { - status = "okay"; - piplane0 { - pipline_id = <0>; - status = "okay"; +&video2{ + vi_mem_pool_region = <0>; // vi_mem: framebuffer, region[0] + pipline0 { sensor0 { subdev_name = "vivcam"; - idx = <1>; //sc132gs - csi_idx = <2>; //<2>=CSI2X2_A - path_type = "SENSOR_1080P_RAW10_LINER"; - }; - dma { - subdev_name = "vipre"; - idx = <0>; - path_type = "VIPRE_CSI2_ISP0"; + idx = <0>; //vivcam0 sc2310 + csi_idx = <0>; //<0>=CSI2 + mode_idx = <1>; + path_type = "SENSOR_1920X1088_26FPS_RAW12_LINER"; }; isp { subdev_name = "isp"; - idx = <0>; + idx = <1>; path_type = "ISP_MI_PATH_MP"; + output { + max_width = <1920>; + max_height = <1088>; + bit_per_pixel = <12>; + frame_count = <3>; + }; }; }; - piplane1 { - pipline_id = <1>; - status = "okay"; + pipline1 { sensor0 { subdev_name = "vivcam"; - idx = <1>; //sc132gs - csi_idx = <2>; //<2>=CSI2X2_A - path_type = "SENSOR_1080P_RAW10_LINER"; - }; - dma { - subdev_name = "vipre"; - idx = <0>; - path_type = "VIPRE_CSI2_ISP0"; + idx = <0>; //vivcam0 sc2310 + csi_idx = <0>; //<0>=CSI2 + mode_idx = <1>; + path_type = "SENSOR_1920X1088_26FPS_RAW12_LINER"; }; isp { subdev_name = "isp"; - idx = <0>; - path_type = "ISP_MI_PATH_MP"; + idx = <1>; + path_type = "ISP_MI_PATH_SP"; + output { + max_width = <1920>; + max_height = <1088>; + bit_per_pixel = <12>; + frame_count = <3>; + }; }; - dw { - subdev_name = "dw"; - idx = <0>; - path_type = "DW_DWE_VSE0"; + }; + pipline2 { + sensor0 { + subdev_name = "vivcam"; + idx = <0>; //vivcam0 sc2310 + csi_idx = <0>; //<0>=CSI2 + mode_idx = <1>; + path_type = "SENSOR_1920X1088_26FPS_RAW12_LINER"; + }; + isp { + subdev_name = "isp"; + idx = <1>; + path_type = "ISP_MI_PATH_SP2_BP"; + output { + max_width = <1920>; + max_height = <1088>; + bit_per_pixel = <12>; + frame_count = <3>; + }; }; }; }; -&video9 { - status = "okay"; - piplane0 { - pipline_id = <0>; - status = "okay"; +&video3{ + vi_mem_pool_region = <0>; // vi_mem: framebuffer, region[0] + pipline0 { sensor0 { subdev_name = "vivcam"; - idx = <0>; //dual camera sc2310 + idx = <0>; //vivcam0 sc2310 csi_idx = <0>; //<0>=CSI2 - path_type = "SENSOR_1080P_RAW12_LINER"; + mode_idx = <1>; + path_type = "SENSOR_1920X1088_26FPS_RAW12_LINER"; }; - dma { - subdev_name = "vipre"; - idx = <0>; - path_type = "VIPRE_CSI0_ISP1"; - }; - isp { - subdev_name = "isp"; - idx = <1>; - path_type = "ISP_MI_PATH_MP"; - }; - }; - piplane1 { - pipline_id = <1>; - status = "okay"; - sensor0 { - subdev_name = "vivcam"; - idx = <0>; //dual sc2310 - csi_idx = <0>; //<0>=CSI2 - path_type = "SENSOR_1080P_RAW12_LINER"; - }; - dma { - subdev_name = "vipre"; - idx = <0>; - path_type = "VIPRE_CSI0_ISP1"; - }; - isp { + isp { subdev_name = "isp"; idx = <1>; path_type = "ISP_MI_PATH_MP"; + output { + max_width = <1920>; + max_height = <1088>; + bit_per_pixel = <12>; + frame_count = <3>; + }; }; dw { subdev_name = "dw"; idx = <0>; path_type = "DW_DWE_VSE0"; + dw_dst_depth = <2>; }; }; - piplane2 { - pipline_id = <2>; - status = "okay"; + pipline1 { sensor0 { subdev_name = "vivcam"; - idx = <0>; //dual sc2310 + idx = <0>; //vivcam0 sc2310 csi_idx = <0>; //<0>=CSI2 - path_type = "SENSOR_1080P_RAW12_LINER"; + mode_idx = <1>; + path_type = "SENSOR_1920X1088_26FPS_RAW12_LINER"; }; - dma { - subdev_name = "vipre"; + isp { + subdev_name = "isp"; + idx = <1>; + path_type = "ISP_MI_PATH_MP"; + output { + max_width = <1920>; + max_height = <1088>; + bit_per_pixel = <12>; + frame_count = <3>; + }; + }; + dw { + subdev_name = "dw"; idx = <0>; - path_type = "VIPRE_CSI0_ISP1"; + path_type = "DW_DWE_VSE1"; + dw_dst_depth = <2>; }; - isp { + }; + pipline2 { + sensor0 { + subdev_name = "vivcam"; + idx = <0>; //vivcam0 sc2310 + csi_idx = <0>; //<0>=CSI2 + mode_idx = <1>; + path_type = "SENSOR_1920X1088_26FPS_RAW12_LINER"; + }; + isp { + subdev_name = "isp"; + idx = <1>; + path_type = "ISP_MI_PATH_MP"; + output { + max_width = <1920>; + max_height = <1088>; + bit_per_pixel = <12>; + frame_count = <3>; + }; + }; + dw { + subdev_name = "dw"; + idx = <0>; + path_type = "DW_DWE_VSE2"; + dw_dst_depth = <2>; + }; + }; +}; + +&video4{ + vi_mem_pool_region = <0>; // vi_mem: framebuffer, region[0] + pipline0 { + sensor0 { + subdev_name = "vivcam"; + idx = <0>; //vivcam0 sc2310 + csi_idx = <0>; //<0>=CSI2 + mode_idx = <1>; + path_type = "SENSOR_1920X1088_26FPS_RAW12_LINER"; + }; + isp { subdev_name = "isp"; idx = <1>; path_type = "ISP_MI_PATH_PP"; + output { + max_width = <1920>; + max_height = <1088>; + bit_per_pixel = <12>; + frame_count = <3>; + }; }; dsp { subdev_name = "dsp"; idx = <0>; path_type = "DSP_PATH_ISP_RY"; + output { + max_width = <1920>; + max_height = <1088>; + bit_per_pixel = <12>; + frame_count = <3>; + }; }; ry { subdev_name = "ry"; idx = <0>; path_type = "ISP_RY_MI_PATH_MP"; + output { + max_width = <1920>; + max_height = <1088>; + bit_per_pixel = <12>; + frame_count = <3>; + }; + }; + }; + pipline1 { + sensor0 { + subdev_name = "vivcam"; + idx = <0>; //vivcam0 sc2310 + csi_idx = <0>; //<0>=CSI2 + mode_idx = <1>; + path_type = "SENSOR_1920X1088_26FPS_RAW12_LINER"; + }; + isp { + subdev_name = "isp"; + idx = <1>; + path_type = "ISP_MI_PATH_PP"; + output { + max_width = <1920>; + max_height = <1088>; + bit_per_pixel = <12>; + frame_count = <3>; + }; + }; + dsp { + subdev_name = "dsp"; + idx = <0>; + path_type = "DSP_PATH_ISP_RY"; + output { + max_width = <1920>; + max_height = <1088>; + bit_per_pixel = <12>; + frame_count = <3>; + }; + }; + ry { + subdev_name = "ry"; + idx = <0>; + path_type = "ISP_RY_MI_PATH_SP"; + output { + max_width = <1920>; + max_height = <1088>; + bit_per_pixel = <12>; + frame_count = <3>; + }; + }; + }; + pipline2 { + sensor0 { + subdev_name = "vivcam"; + idx = <0>; //vivcam0 sc2310 + csi_idx = <0>; //<0>=CSI2 + mode_idx = <1>; + path_type = "SENSOR_1920X1088_26FPS_RAW12_LINER"; + }; + isp { + subdev_name = "isp"; + idx = <1>; + path_type = "ISP_MI_PATH_PP"; + output { + max_width = <1920>; + max_height = <1088>; + bit_per_pixel = <12>; + frame_count = <3>; + }; + }; + dsp { + subdev_name = "dsp"; + idx = <0>; + path_type = "DSP_PATH_ISP_RY"; + output { + max_width = <1920>; + max_height = <1088>; + bit_per_pixel = <12>; + frame_count = <3>; + }; + }; + ry { + subdev_name = "ry"; + idx = <0>; + path_type = "ISP_RY_MI_PATH_SP2_BP"; + output { + max_width = <1920>; + max_height = <1088>; + bit_per_pixel = <12>; + frame_count = <3>; + }; + }; + }; +}; + +&video5{ + vi_mem_pool_region = <0>; // vi_mem: framebuffer, region[0] + pipline0 { + sensor0 { + subdev_name = "vivcam"; + idx = <0>; //vivcam0 sc2310 + csi_idx = <0>; //<0>=CSI2 + mode_idx = <1>; + path_type = "SENSOR_1920X1088_26FPS_RAW12_LINER"; + }; + isp { + subdev_name = "isp"; + idx = <1>; + path_type = "ISP_MI_PATH_PP"; + output { + max_width = <1920>; + max_height = <1088>; + bit_per_pixel = <12>; + frame_count = <3>; + }; + }; + dsp { + subdev_name = "dsp"; + idx = <0>; + path_type = "DSP_PATH_ISP_RY"; + output { + max_width = <1920>; + max_height = <1088>; + bit_per_pixel = <12>; + frame_count = <3>; + }; + }; + ry { + subdev_name = "ry"; + idx = <0>; + path_type = "ISP_RY_MI_PATH_MP"; + output { + max_width = <1920>; + max_height = <1088>; + bit_per_pixel = <12>; + frame_count = <3>; + }; }; dw { subdev_name = "dw"; idx = <0>; path_type = "DW_DWE_VSE0"; + dw_dst_depth = <2>; + }; + }; + pipline1 { + sensor0 { + subdev_name = "vivcam"; + idx = <0>; //vivcam0 sc2310 + csi_idx = <0>; //<0>=CSI2 + mode_idx = <1>; + path_type = "SENSOR_1920X1088_26FPS_RAW12_LINER"; + }; + isp { + subdev_name = "isp"; + idx = <1>; + path_type = "ISP_MI_PATH_PP"; + output { + max_width = <1920>; + max_height = <1088>; + bit_per_pixel = <12>; + frame_count = <3>; + }; + }; + dsp { + subdev_name = "dsp"; + idx = <0>; + path_type = "DSP_PATH_ISP_RY"; + output { + max_width = <1920>; + max_height = <1088>; + bit_per_pixel = <12>; + frame_count = <3>; + }; + }; + ry { + subdev_name = "ry"; + idx = <0>; + path_type = "ISP_RY_MI_PATH_MP"; + output { + max_width = <1920>; + max_height = <1088>; + bit_per_pixel = <12>; + frame_count = <3>; + }; + }; + dw { + subdev_name = "dw"; + idx = <0>; + path_type = "DW_DWE_VSE1"; + dw_dst_depth = <2>; + }; + }; + pipline2 { + sensor0 { + subdev_name = "vivcam"; + idx = <0>; //vivcam0 sc2310 + csi_idx = <0>; //<0>=CSI2 + mode_idx = <1>; + path_type = "SENSOR_1920X1088_26FPS_RAW12_LINER"; + }; + isp { + subdev_name = "isp"; + idx = <1>; + path_type = "ISP_MI_PATH_PP"; + output { + max_width = <1920>; + max_height = <1088>; + bit_per_pixel = <12>; + frame_count = <3>; + }; + }; + dsp { + subdev_name = "dsp"; + idx = <0>; + path_type = "DSP_PATH_ISP_RY"; + output { + max_width = <1920>; + max_height = <1088>; + bit_per_pixel = <12>; + frame_count = <3>; + }; + }; + ry { + subdev_name = "ry"; + idx = <0>; + path_type = "ISP_RY_MI_PATH_MP"; + output { + max_width = <1920>; + max_height = <1088>; + bit_per_pixel = <12>; + frame_count = <3>; + }; + }; + dw { + subdev_name = "dw"; + idx = <0>; + path_type = "DW_DWE_VSE2"; + dw_dst_depth = <2>; }; }; }; -&video10 { - status = "okay"; - piplane0 { - pipline_id = <0>; - status = "okay"; +&video6{ + vi_mem_pool_region = <1>; // vi_mem: framebuffer, region[1] + pipline0 { sensor0 { subdev_name = "vivcam"; - idx = <1>; //sc132gs + idx = <1>; // vivcam1 sc132gs csi_idx = <2>; //<2>=CSI2X2_A - path_type = "SENSOR_1080P_RAW10_LINER"; + flash_led_idx = <0>; + mode_idx= <0>; + path_type = "SENSOR_1080X1280_RAW10_LINER"; }; - dma { - subdev_name = "vipre"; + dsp{ + output { + max_width = <1080>; + max_height = <1280>; + bit_per_pixel = <16>; + frame_count = <3>; + }; + }; + }; + pipline1 { + sensor0 { + subdev_name = "vivcam"; + idx = <1>; //vivcam1 sc132gs + csi_idx = <2>; //<2>=CSI2X2_A + flash_led_idx = <0>; + mode_idx= <0>; + path_type = "SENSOR_1080X1280_RAW10_LINER"; + }; + dsp{ + output { + max_width = <1080>; + max_height = <1280>; + bit_per_pixel = <16>; + frame_count = <3>; + }; + }; + }; + +}; + +&video7{ + pipline0 { + sensor0 { + subdev_name = "vivcam"; + idx = <2>; //<2>=vivcam2 : gc5035 + csi_idx = <1>; //<1>=CSI2X2_B + mode_idx = <3>; + path_type = "SENSOR_1296x972_RAW10_LINER"; //SENSOR_VGA_RAW10_LINER// + }; + sensor1 { + subdev_name = "vivcam"; + idx = <3>; //<3>=vivcam3 : gc02m1b + csi_idx = <1>; //<1>=CSI2X2_B + mode_idx = <0>; + path_type = "SENSOR_1600x1200_RAW10_LINER"; + }; + isp { + subdev_name = "isp"; idx = <0>; - path_type = "VIPRE_CSI2_DDR"; + path_type = "ISP_MI_PATH_PP"; + output { + max_width = <1920>; + max_height = <1088>; + bit_per_pixel = <12>; + frame_count = <3>; + }; }; dsp { subdev_name = "dsp"; idx = <1>; - path_type = "DSP_PATH_VIPRE_DDR"; + path_type = "DSP_PATH_ISP_RY"; + output { + max_width = <1920>; + max_height = <1088>; + bit_per_pixel = <12>; + frame_count = <3>; + }; }; - }; -}; - -&video11 { - status = "okay"; - piplane0 { - pipline_id = <0>; - status = "okay"; - sensor0 { - subdev_name = "vivcam"; - idx = <0>; //sc2310 - csi_idx = <0>; //<0>=CSI2 - path_type = "SENSOR_1080P_RAW12_LINER"; - }; - dma { - subdev_name = "vipre"; + ry { + subdev_name = "ry"; idx = <0>; - path_type = "VIPRE_CSI0_ISP1"; - }; - isp { - subdev_name = "isp"; - idx = <1>; - path_type = "ISP_MI_PATH_MP"; - }; - }; - piplane1 { - pipline_id = <1>; - status = "okay"; - sensor0 { - subdev_name = "vivcam"; - idx = <0>; //sc2310 - csi_idx = <0>; //<0>=CSI2 - path_type = "SENSOR_1080P_RAW12_LINER"; - }; - dma { - subdev_name = "vipre"; - idx = <0>; - path_type = "VIPRE_CSI0_ISP1"; - }; - isp { - subdev_name = "isp"; - idx = <1>; - path_type = "ISP_MI_PATH_SP"; - }; - }; - - piplane2 { - pipline_id = <2>; - status = "okay"; - sensor0 { - subdev_name = "vivcam"; - idx = <0>; //sc2310 - csi_idx = <0>; //<0>=CSI2 - path_type = "SENSOR_1080P_RAW12_LINER"; - }; - dma { - subdev_name = "vipre"; - idx = <0>; - path_type = "VIPRE_CSI0_ISP1"; - }; - isp { - subdev_name = "isp"; - idx = <1>; - path_type = "ISP_MI_PATH_SP2_BP"; - }; - }; -}; - -&video12{ - status = "okay"; - piplane0 { - pipline_id = <0>; - status = "okay"; - sensor0 { - subdev_name = "vivcam"; - idx = <1>; //sc132gs - csi_idx = <2>; //<2>=CSI2X2_A - flash_led_idx = <0>; - path_type = "SENSOR_1080P_RAW10_LINER"; - }; - dma { - subdev_name = "vipre"; - idx = <0>; - path_type = "VIPRE_CSI2_DDR"; - }; - dsp { - subdev_name = "dsp"; - idx = <1>; - path_type = "DSP_PATH_VIPRE_ODD"; - }; - }; - piplane1 { - pipline_id = <1>; - status = "okay"; - sensor0 { - subdev_name = "vivcam"; - idx = <1>; //sc132gs - csi_idx = <2>; //<2>=CSI2X2_A - flash_led_idx = <0>; - path_type = "SENSOR_1080P_RAW10_LINER"; - }; - dma { - subdev_name = "vipre"; - idx = <0>; - path_type = "VIPRE_CSI2_DDR"; - }; - dsp { - subdev_name = "dsp"; - idx = <1>; - path_type = "DSP_PATH_VIPRE_EVEN"; - }; - }; -}; - -&video13{ - status = "okay"; - piplane0 { - pipline_id = <0>; - status = "okay"; - sensor0 { - subdev_name = "vivcam"; - idx = <1>; //sc132gs - csi_idx = <2>; //<2>=CSI2X2_A - flash_led_idx = <0>; - path_type = "SENSOR_1080P_RAW10_LINER"; - }; - dma { - subdev_name = "vipre"; - idx = <0>; - path_type = "VIPRE_CSI2_DDR"; - }; - dsp { - subdev_name = "dsp"; - idx = <0>; - path_type = "DSP_PATH_VIPRE_DDR"; - }; - }; -}; - -&video14 { - status = "okay"; - piplane0 { - pipline_id = <0>; - status = "okay"; - sensor0 { - subdev_name = "vivcam"; - idx = <2>; //<2>=vivcam2 : gc5035 - csi_idx = <1>; //<1>=CSI2X2_B - path_type = "SENSOR_1080P_RAW10_LINER"; //SENSOR_1080P_RAW10_LINER - }; - dma { - subdev_name = "vipre"; - idx = <0>; - path_type = "VIPRE_CSI1_ISP0"; - }; - isp { - subdev_name = "isp"; - idx = <0>; - path_type = "ISP_MI_PATH_MP"; - }; - }; - piplane1 { - pipline_id = <1>; - status = "okay"; - sensor0 { - subdev_name = "vivcam"; - idx = <2>; //<2>=vivcam2 : gc5035 - csi_idx = <1>; //<1>=CSI2X2_B - path_type = "SENSOR_1080P_RAW10_LINER"; //SENSOR_1080P_RAW10_LINER - }; - dma { - subdev_name = "vipre"; - idx = <0>; - path_type = "VIPRE_CSI1_ISP0"; - }; - isp { - subdev_name = "isp"; - idx = <0>; - path_type = "ISP_MI_PATH_MP"; + path_type = "ISP_RY_MI_PATH_MP"; + output { + max_width = <1920>; + max_height = <1088>; + bit_per_pixel = <12>; + frame_count = <3>; + }; }; dw { subdev_name = "dw"; idx = <0>; path_type = "DW_DWE_VSE0"; + dw_dst_depth = <2>; + }; + }; + pipline1 { + sensor0 { + subdev_name = "vivcam"; + idx = <2>; //<2>=vivcam2 : gc5035 + csi_idx = <1>; //<1>=CSI2X2_B + mode_idx = <3>; + path_type = "SENSOR_1296x972_RAW10_LINER"; //SENSOR_VGA_RAW10_LINER// + }; + sensor1 { + subdev_name = "vivcam"; + idx = <3>; //<3>=vivcam3 : gc02m1b + csi_idx = <1>; //<1>=CSI2X2_B + mode_idx = <0>; + path_type = "SENSOR_1600x1200_RAW10_LINER"; + }; + isp { + subdev_name = "isp"; + idx = <0>; + path_type = "ISP_MI_PATH_PP"; + output { + max_width = <1920>; + max_height = <1088>; + bit_per_pixel = <12>; + frame_count = <3>; + }; + }; + dsp { + subdev_name = "dsp"; + idx = <1>; + path_type = "DSP_PATH_ISP_RY"; + output { + max_width = <1920>; + max_height = <1088>; + bit_per_pixel = <12>; + frame_count = <3>; + }; + }; + ry { + subdev_name = "ry"; + idx = <0>; + path_type = "ISP_RY_MI_PATH_MP"; + output { + max_width = <1920>; + max_height = <1088>; + bit_per_pixel = <12>; + frame_count = <3>; + }; + }; + dw { + subdev_name = "dw"; + idx = <0>; + path_type = "DW_DWE_VSE1"; + dw_dst_depth = <2>; + }; + }; + pipline2 { + sensor0 { + subdev_name = "vivcam"; + idx = <2>; //<2>=vivcam2 : gc5035 + csi_idx = <1>; //<1>=CSI2X2_B + mode_idx = <3>; + path_type = "SENSOR_1296x972_RAW10_LINER"; //SENSOR_VGA_RAW10_LINER// + }; + sensor1 { + subdev_name = "vivcam"; + idx = <3>; //<3>=vivcam3 : gc02m1b + csi_idx = <1>; //<1>=CSI2X2_B + mode_idx = <0>; + path_type = "SENSOR_1600x1200_RAW10_LINER"; + }; + isp { + subdev_name = "isp"; + idx = <0>; + path_type = "ISP_MI_PATH_PP"; + output { + max_width = <1920>; + max_height = <1088>; + bit_per_pixel = <12>; + frame_count = <3>; + }; + }; + dsp { + subdev_name = "dsp"; + idx = <1>; + path_type = "DSP_PATH_ISP_RY"; + output { + max_width = <1920>; + max_height = <1088>; + bit_per_pixel = <12>; + frame_count = <3>; + }; + }; + ry { + subdev_name = "ry"; + idx = <0>; + path_type = "ISP_RY_MI_PATH_MP"; + output { + max_width = <1920>; + max_height = <1088>; + bit_per_pixel = <12>; + frame_count = <3>; + }; + }; + dw { + subdev_name = "dw"; + idx = <0>; + path_type = "DW_DWE_VSE2"; + dw_dst_depth = <2>; }; }; }; -&video15 { // TUNING TOOL - status = "okay"; - piplane0 { // CSI2 - status = "okay"; + +&video8{ + vi_mem_pool_region = <1>; // vi_mem: framebuffer, region[1] + pipline0 { sensor0 { - subdev_name = "vivcam"; - idx = <0>; //sc2310 - csi_idx = <0>; //<0>=CSI2 - path_type = "SENSOR_1080P_RAW12_LINER"; - skip_init = <1>; + subdev_name = "vivcam"; + idx = <2>; //<2>=vivcam2 : gc5035 + csi_idx = <1>; //<1>=CSI2X2_B + mode_idx = <3>; + path_type = "SENSOR_1296x972_RAW10_LINER"; //SENSOR_VGA_RAW10_LINER// }; - dma { - subdev_name = "vipre"; + sensor1 { + subdev_name = "vivcam"; + idx = <3>; //<3>=vivcam3 : gc02m1b + csi_idx = <1>; //<1>=CSI2X2_B + mode_idx = <0>; + path_type = "SENSOR_1600x1200_RAW10_LINER"; + }; + dsp { + subdev_name = "dsp"; idx = <0>; - path_type = "VIPRE_CSI0_ISP0"; + path_type = "DSP_PATH_VIPRE_DDR"; + output { + max_width = <1920>; + max_height = <1088>; + bit_per_pixel = <12>; + frame_count = <3>; + }; }; }; }; +&video9{ + pipline0 { + sensor0 { + subdev_name = "vivcam"; + idx = <1>; //vivcam1 sc132gs + csi_idx = <2>; //<2>=CSI2X2_A + mode_idx= <0>; + path_type = "SENSOR_1080X1280_RAW10_LINER"; + }; + dsp{ + output { + max_width = <1080>; + max_height = <1280>; + bit_per_pixel = <16>; + frame_count = <3>; + }; + }; + }; +}; + + +&video10{ // TUNINGTOOL + pipline0 { + sensor0 { + subdev_name = "vivcam"; + idx = <2>; //<2>=vivcam2 : gc5035 + csi_idx = <1>; //<1>=CSI2X2_B + mode_idx= <1>; + path_type = "SENSOR_1920X1080_RAW10_LINER"; //SENSOR_VGA_RAW10_LINER// + skip_init = <1>; + }; + sensor1 { + subdev_name = "vivcam"; + idx = <3>; //<3>=vivcam3 : gc02m1b + csi_idx = <1>; //<1>=CSI2X2_B + mode_idx = <0>; + path_type = "SENSOR_1600x1200_RAW10_LINER"; + skip_init = <1>; + }; + }; +}; + +&video11{ + pipline0 { + pipline_id = <0>; + status = "okay"; + sensor0 { + subdev_name = "vivcam"; + idx = <1>; //sc132gs + csi_idx = <2>; //<2>=CSI2X2_A + flash_led_idx = <0>; + mode_idx= <0>; + path_type = "SENSOR_1080X1280_RAW10_LINER"; + }; + isp { + subdev_name = "isp"; + idx = <0>; + path_type = "ISP_MI_PATH_MP"; + output { + max_width = <1920>; + max_height = <1088>; + bit_per_pixel = <12>; + frame_count = <3>; + }; + }; + }; +}; + +&video12{ // TUNINGTOOL + pipline0 { // CSI2 + sensor0 { + subdev_name = "vivcam"; + idx = <0>; //sc2310 + csi_idx = <0>; //<0>=CSI2 + mode_idx = <1>; + path_type = "SENSOR_1920X1088_26FPS_RAW12_LINER"; + skip_init = <1>; + }; + }; +}; + + &trng { status = "disabled"; }; @@ -1933,6 +1990,7 @@ &vidmem { status = "okay"; + memory-region = <&vi_mem>; }; &gpu { @@ -2005,6 +2063,7 @@ reg = <0>; backlight = <&lcd0_backlight>; reset-gpio = <&gpio1_porta 5 1>; /* active low */ + vdd1v8-supply = <&soc_vdd18_lcd0_en_reg>; vspn5v7-supply = <&soc_lcd0_bias_en_reg>; port { diff --git a/arch/riscv/boot/dts/thead/light-ant-ref-crash.dts b/arch/riscv/boot/dts/thead/light-ant-ref-crash.dts new file mode 100644 index 000000000..8987da77b --- /dev/null +++ b/arch/riscv/boot/dts/thead/light-ant-ref-crash.dts @@ -0,0 +1,90 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Copyright (C) 2022 Alibaba Group Holding Limited. + */ + +#include "light-crash.dts" + +&aon { + aon_reg_dialog: light-dialog-reg { + compatible = "thead,light-dialog-pmic-ant"; + status = "okay"; + + dvdd_cpu_reg: appcpu_dvdd { + regulator-name = "appcpu_dvdd"; + regulator-min-microvolt = <300000>; + regulator-max-microvolt = <1570000>; + regulator-boot-on; + regulator-always-on; + }; + + dvddm_cpu_reg: appcpu_dvddm { + regulator-name = "appcpu_dvddm"; + regulator-min-microvolt = <300000>; + regulator-max-microvolt = <1570000>; + regulator-boot-on; + regulator-always-on; + }; + }; +}; + +&cpus { + c910_0: cpu@0 { + operating-points = < + /* kHz uV */ + 300000 650000 + 800000 700000 + 1500000 800000 + >; + light,dvddm-operating-points = < + /* kHz uV */ + 300000 800000 + 800000 800000 + 1500000 800000 + >; + }; + c910_1: cpu@1 { + operating-points = < + /* kHz uV */ + 300000 650000 + 800000 700000 + 1500000 800000 + >; + light,dvddm-operating-points = < + /* kHz uV */ + 300000 800000 + 800000 800000 + 1500000 800000 + >; + }; + c910_2: cpu@2 { + + operating-points = < + /* kHz uV */ + 300000 650000 + 800000 700000 + 1500000 800000 + >; + light,dvddm-operating-points = < + /* kHz uV */ + 300000 800000 + 800000 800000 + 1500000 800000 + >; + }; + c910_3: cpu@3 { + + operating-points = < + /* kHz uV */ + 300000 650000 + 800000 700000 + 1500000 800000 + >; + light,dvddm-operating-points = < + /* kHz uV */ + 300000 800000 + 800000 800000 + 1500000 800000 + >; + }; +}; diff --git a/arch/riscv/boot/dts/thead/light-ant-evt-sec.dts b/arch/riscv/boot/dts/thead/light-ant-ref-sec.dts similarity index 87% rename from arch/riscv/boot/dts/thead/light-ant-evt-sec.dts rename to arch/riscv/boot/dts/thead/light-ant-ref-sec.dts index b479a1d6f..0cbed3d72 100644 --- a/arch/riscv/boot/dts/thead/light-ant-evt-sec.dts +++ b/arch/riscv/boot/dts/thead/light-ant-ref-sec.dts @@ -5,7 +5,7 @@ /dts-v1/; -#include "light-ant-evt.dts" +#include "light-ant-ref.dts" diff --git a/arch/riscv/boot/dts/thead/light-ant-evt.dts b/arch/riscv/boot/dts/thead/light-ant-ref.dts similarity index 79% rename from arch/riscv/boot/dts/thead/light-ant-evt.dts rename to arch/riscv/boot/dts/thead/light-ant-ref.dts index aca23fa94..c62b3f97b 100644 --- a/arch/riscv/boot/dts/thead/light-ant-evt.dts +++ b/arch/riscv/boot/dts/thead/light-ant-ref.dts @@ -20,8 +20,6 @@ chosen { bootargs = "console=ttyS0,115200 crashkernel=256M-:128M earlycon clk_ignore_unused sram=0xffe0000000,0x180000"; - linux,initrd-start = <0x0 0x2000000>; - linux,initrd-end = <0x0 0x14600000>; stdout-path = "serial0:115200n8"; }; @@ -256,7 +254,7 @@ }; }; - aon { + aon: aon { compatible = "thead,light-aon"; mbox-names = "aon"; mboxes = <&mbox_910t 1 0>; @@ -494,14 +492,20 @@ soc_dovdd18_scan_reg: soc_dovdd18_scan { regulator-name = "soc_dovdd18_scan"; + regulator-min-microvolt = <900000>; + regulator-max-microvolt = <3600000>; }; soc_dvdd12_scan_reg: soc_dvdd12_scan { regulator-name = "soc_dvdd12_scan"; + regulator-min-microvolt = <900000>; + regulator-max-microvolt = <3600000>; }; soc_avdd28_scan_en_reg: soc_avdd28_scan_en { regulator-name = "soc_avdd28_scan_en"; + regulator-min-microvolt = <900000>; + regulator-max-microvolt = <3600000>; }; }; @@ -542,16 +546,17 @@ 0x0 0x20688000 0x0 0x00178000>; /* DSP shared memory */ no-map; }; - facelib_mem: memory@33000000 { - reg = <0x0 0x33000000 0 0x02000000>; + vi_mem: framebuffer@10000000 { + reg = <0x0 0x10000000 0x0 0x02C00000 /* vi_mem_pool_region[0] 44 MB (default) */ + 0x0 0x12C00000 0x0 0x01D00000 /* vi_mem_pool_region[1] 29 MB */ + 0x0 0x14900000 0x0 0x01E00000>; /* vi_mem_pool_region[2] 30 MB */ no-map; }; - vi_mem: framebuffer@70000000 { - reg = <0x0 0x70000000 0x0 0x02C00000 /* vi_mem_pool_region[0] 44 MB (default) */ - 0x0 0x72C00000 0x0 0x01D00000 /* vi_mem_pool_region[1] 29 MB */ - 0x0 0x74900000 0x0 0x01E00000>; /* vi_mem_pool_region[2] 30 MB */ + facelib_mem: memory@17000000 { + reg = <0x0 0x17000000 0 0x02000000>; no-map; }; + }; &adc { @@ -733,6 +738,7 @@ no-mmc; non-removable; io_fixed_1v8; + post-power-on-delay-ms = <50>; wprtn_ignore; cap-sd-highspeed; keep-power-in-suspend; @@ -867,22 +873,27 @@ }; &i2c0 { + clock-frequency = <400000>; status = "okay"; }; &i2c1 { + clock-frequency = <400000>; status = "okay"; }; &i2c2 { + clock-frequency = <400000>; status = "okay"; }; &i2c3 { + clock-frequency = <400000>; status = "okay"; }; &i2c4 { + clock-frequency = <400000>; status = "okay"; }; @@ -951,7 +962,7 @@ &vvcam_flash_led0{ flash_led_name = "aw36413_aw36515"; - floodlight_i2c_bus = /bits/ 8 <0>; + floodlight_i2c_bus = /bits/ 8 <2>; floodlight_en_pin = <&gpio1_porta 26 0>; projection_i2c_bus = /bits/ 8 <1>; flash_led_touch_pin = <&gpio1_porta 27 0>; //flash led touch pin @@ -966,7 +977,7 @@ sensor_regulator_timing_us = <70 50 20>; sensor_pdn = <&gpio1_porta 21 0>; //powerdown pin / shutdown pin sensor_rst = <&gpio1_porta 16 0>; - sensor_pdn_delay_us = <1000>; //powerdown pin / shutdown pin actived till I2C ready + sensor_pdn_delay_us = <4000>; //powerdown pin / shutdown pin actived till I2C ready DOVDD18_RGB-supply = <&soc_dovdd18_rgb_reg>; DVDD12_RGB-supply = <&soc_dvdd12_rgb_reg>; AVDD28_RGB-supply = <&soc_avdd28_rgb_reg>; @@ -980,11 +991,11 @@ &vvcam_sensor1 { sensor_name = "SC132GS"; sensor_regulators = "DOVDD18_IR", "DVDD12_IR", "AVDD25_IR"; - sensor_regulator_timing_us = <70 50 20>; + sensor_regulator_timing_us = <70 1000 2000>; i2c_addr = /bits/ 8 <0x31>; sensor_pdn = <&gpio1_porta 28 0>; //powerdown pin / shutdown pin sensor_rst = <&gpio1_porta 24 0>; - sensor_pdn_delay_us = <1000>; //powerdown pin / shutdown pin actived till I2C ready + sensor_pdn_delay_us = <2000>; //powerdown pin / shutdown pin actived till I2C ready DOVDD18_IR-supply = <&soc_dovdd18_ir_reg>; DVDD12_IR-supply = <&soc_dvdd12_ir_reg>; AVDD25_IR-supply = <&soc_avdd25_ir_reg>; @@ -1011,14 +1022,42 @@ status = "okay"; }; +&vvcam_sensor3 { + sensor_name = "GC02M1B"; + sensor_regulators = "DOVDD18_SCAN", "DVDD12_SCAN", "AVDD28_SCAN"; + sensor_regulator_timing_us = <100 50 0>; + sensor_pdn = <&gpio1_porta 30 0>; //powerdown pin / shutdown pin + sensor_rst = <&gpio1_porta 29 0>; + sensor_pdn_delay_us = <1000>; //powerdown pin / shutdown pin actived till I2C ready + DOVDD18_SCAN-supply = <&soc_dovdd18_scan_reg>; + DVDD12_SCAN-supply = <&soc_dvdd12_scan_reg>; + AVDD28_SCAN-supply = <&soc_avdd28_scan_en_reg>; + i2c_addr = /bits/ 8 <0x37>; + i2c_bus = /bits/ 8 <4>; + i2c_reg_width = /bits/ 8 <1>; + i2c_data_width = /bits/ 8 <1>; + status = "okay"; +}; + &video0{ - vi_mem_pool_region = <2>; // vi_mem: framebuffer, region[2] + vi_mem_pool_region = <2>; // vi_mem: framebuffer, region[2] pipline0 { sensor0 { subdev_name = "vivcam"; idx = <2>; //<2>=vivcam2 : gc5035 - csi_idx = <1>; //<1>=CSI2X2_B - path_type = "SENSOR_1080P_RAW10_LINER"; //SENSOR_VGA_RAW10_LINER// + csi_idx = <0>; //<0>=CSI2 + mode_idx = <3>; + path_type = "SENSOR_1296x972_RAW10_LINER"; //SENSOR_VGA_RAW10_LINER// + }; + sensor1 { + subdev_name = "vivcam"; + idx = <3>; //<3>=vivcam3 : gc02m1b + csi_idx = <0>; //<0>=CSI2 + mode_idx = <0>; + path_type = "SENSOR_1600x1200_RAW10_LINER"; + }; + dma { + path_type = "VIPRE_CSI0_ISP0"; }; isp { subdev_name = "isp"; @@ -1036,8 +1075,19 @@ sensor0 { subdev_name = "vivcam"; idx = <2>; //<2>=vivcam2 : gc5035 - csi_idx = <1>; //<1>=CSI2X2_B - path_type = "SENSOR_1080P_RAW10_LINER"; //SENSOR_VGA_RAW10_LINER// + csi_idx = <0>; //<0>=CSI2 + mode_idx = <3>; + path_type = "SENSOR_1296x972_RAW10_LINER"; //SENSOR_VGA_RAW10_LINER// + }; + sensor1 { + subdev_name = "vivcam"; + idx = <3>; //<3>=vivcam3 : gc02m1b + csi_idx = <0>; //<0>=CSI2 + mode_idx = <0>; + path_type = "SENSOR_1600x1200_RAW10_LINER"; + }; + dma { + path_type = "VIPRE_CSI0_ISP0"; }; isp { subdev_name = "isp"; @@ -1055,8 +1105,19 @@ sensor0 { subdev_name = "vivcam"; idx = <2>; //<2>=vivcam2 : gc5035 - csi_idx = <1>; //<1>=CSI2X2_B - path_type = "SENSOR_1080P_RAW10_LINER"; //SENSOR_VGA_RAW10_LINER// + csi_idx = <0>; //<0>=CSI2 + mode_idx = <3>; + path_type = "SENSOR_1296x972_RAW10_LINER"; //SENSOR_VGA_RAW10_LINER// + }; + sensor1 { + subdev_name = "vivcam"; + idx = <3>; //<3>=vivcam3 : gc02m1b + csi_idx = <0>; //<0>=CSI2 + mode_idx = <0>; + path_type = "SENSOR_1600x1200_RAW10_LINER"; + }; + dma { + path_type = "VIPRE_CSI0_ISP0"; }; isp { subdev_name = "isp"; @@ -1079,9 +1140,21 @@ sensor0 { subdev_name = "vivcam"; idx = <2>; //<2>=vivcam2 : gc5035 - csi_idx = <1>; //<1>=CSI2X2_B - path_type = "SENSOR_1080P_RAW10_LINER"; + csi_idx = <0>; //<0>=CSI2 + mode_idx = <3>; + path_type = "SENSOR_1296x972_RAW10_LINER"; }; + sensor1 { + subdev_name = "vivcam"; + idx = <3>; //<3>=vivcam3 : gc02m1b + csi_idx = <0>; //<0>=CSI2 + mode_idx = <0>; + path_type = "SENSOR_1600x1200_RAW10_LINER"; + }; + dma { + path_type = "VIPRE_CSI0_ISP0"; + }; + isp { subdev_name = "isp"; idx = <0>; @@ -1104,9 +1177,21 @@ sensor0 { subdev_name = "vivcam"; idx = <2>; //<2>=vivcam2 : gc5035 - csi_idx = <1>; //<1>=CSI2X2_B - path_type = "SENSOR_1080P_RAW10_LINER"; + csi_idx = <0>; //<0>=CSI2 + mode_idx = <3>; + path_type = "SENSOR_1296x972_RAW10_LINER"; }; + sensor1 { + subdev_name = "vivcam"; + idx = <3>; //<3>=vivcam3 : gc02m1b + csi_idx = <0>; //<0>=CSI2 + mode_idx = <0>; + path_type = "SENSOR_1600x1200_RAW10_LINER"; + }; + dma { + path_type = "VIPRE_CSI0_ISP0"; + }; + isp { subdev_name = "isp"; idx = <0>; @@ -1129,9 +1214,21 @@ sensor0 { subdev_name = "vivcam"; idx = <2>; //<2>=vivcam2 : gc5035 - csi_idx = <1>; //<1>=CSI2X2_B - path_type = "SENSOR_1080P_RAW10_LINER"; + csi_idx = <0>; //<0>=CSI2 + mode_idx = <3>; + path_type = "SENSOR_1296x972_RAW10_LINER"; }; + sensor1 { + subdev_name = "vivcam"; + idx = <3>; //<3>=vivcam3 : gc02m1b + csi_idx = <0>; //<0>=CSI2 + mode_idx = <0>; + path_type = "SENSOR_1600x1200_RAW10_LINER"; + }; + dma { + path_type = "VIPRE_CSI0_ISP0"; + }; + isp { subdev_name = "isp"; idx = <0>; @@ -1158,8 +1255,12 @@ sensor0 { subdev_name = "vivcam"; idx = <0>; //vivcam0 sc2310 - csi_idx = <0>; //<0>=CSI2 - path_type = "SENSOR_1080P_RAW12_LINER"; + csi_idx = <1>; //<1>=CSI2_B + mode_idx = <1>; + path_type = "SENSOR_1920X1088_30FPS_RAW12_LINER"; + }; + dma { + path_type = "VIPRE_CSI1_ISP1"; }; isp { subdev_name = "isp"; @@ -1177,8 +1278,12 @@ sensor0 { subdev_name = "vivcam"; idx = <0>; //vivcam0 sc2310 - csi_idx = <0>; //<0>=CSI2 - path_type = "SENSOR_1080P_RAW12_LINER"; + csi_idx = <1>; //<1>=CSI2_B + mode_idx = <1>; + path_type = "SENSOR_1920X1088_30FPS_RAW12_LINER"; + }; + dma { + path_type = "VIPRE_CSI1_ISP1"; }; isp { subdev_name = "isp"; @@ -1196,8 +1301,12 @@ sensor0 { subdev_name = "vivcam"; idx = <0>; //vivcam0 sc2310 - csi_idx = <0>; //<0>=CSI2 - path_type = "SENSOR_1080P_RAW12_LINER"; + csi_idx = <1>; //<1>=CSI2_B + mode_idx = <1>; + path_type = "SENSOR_1920X1088_30FPS_RAW12_LINER"; + }; + dma { + path_type = "VIPRE_CSI1_ISP1"; }; isp { subdev_name = "isp"; @@ -1219,8 +1328,12 @@ sensor0 { subdev_name = "vivcam"; idx = <0>; //vivcam0 sc2310 - csi_idx = <0>; //<0>=CSI2 - path_type = "SENSOR_1080P_RAW12_LINER"; + csi_idx = <1>; //<1>=CSI2B + mode_idx = <1>; + path_type = "SENSOR_1920X1088_30FPS_RAW12_LINER"; + }; + dma { + path_type = "VIPRE_CSI1_ISP1"; }; isp { subdev_name = "isp"; @@ -1244,8 +1357,12 @@ sensor0 { subdev_name = "vivcam"; idx = <0>; //vivcam0 sc2310 - csi_idx = <0>; //<0>=CSI2 - path_type = "SENSOR_1080P_RAW12_LINER"; + csi_idx = <1>; //<1>=CSI2B + mode_idx = <1>; + path_type = "SENSOR_1920X1088_30FPS_RAW12_LINER"; + }; + dma { + path_type = "VIPRE_CSI1_ISP1"; }; isp { subdev_name = "isp"; @@ -1269,8 +1386,12 @@ sensor0 { subdev_name = "vivcam"; idx = <0>; //vivcam0 sc2310 - csi_idx = <0>; //<0>=CSI2 - path_type = "SENSOR_1080P_RAW12_LINER"; + csi_idx = <1>; //<1>=CSI2_B + mode_idx = <1>; + path_type = "SENSOR_1920X1088_30FPS_RAW12_LINER"; + }; + dma { + path_type = "VIPRE_CSI1_ISP1"; }; isp { subdev_name = "isp"; @@ -1298,8 +1419,12 @@ sensor0 { subdev_name = "vivcam"; idx = <0>; //vivcam0 sc2310 - csi_idx = <0>; //<0>=CSI2 - path_type = "SENSOR_1080P_RAW12_LINER"; + csi_idx = <1>; //<1>=CSI2_B + mode_idx = <1>; + path_type = "SENSOR_1920X1088_30FPS_RAW12_LINER"; + }; + dma { + path_type = "VIPRE_CSI1_ISP1"; }; isp { subdev_name = "isp"; @@ -1339,8 +1464,12 @@ sensor0 { subdev_name = "vivcam"; idx = <0>; //vivcam0 sc2310 - csi_idx = <0>; //<0>=CSI2 - path_type = "SENSOR_1080P_RAW12_LINER"; + csi_idx = <1>; //<1>=CSI2_B + mode_idx = <1>; + path_type = "SENSOR_1920X1088_30FPS_RAW12_LINER"; + }; + dma { + path_type = "VIPRE_CSI1_ISP1"; }; isp { subdev_name = "isp"; @@ -1380,8 +1509,12 @@ sensor0 { subdev_name = "vivcam"; idx = <0>; //vivcam0 sc2310 - csi_idx = <0>; //<0>=CSI2 - path_type = "SENSOR_1080P_RAW12_LINER"; + csi_idx = <1>; //<1>=CSI2_B + mode_idx = <1>; + path_type = "SENSOR_1920X1088_30FPS_RAW12_LINER"; + }; + dma { + path_type = "VIPRE_CSI1_ISP1"; }; isp { subdev_name = "isp"; @@ -1425,8 +1558,12 @@ sensor0 { subdev_name = "vivcam"; idx = <0>; //vivcam0 sc2310 - csi_idx = <0>; //<0>=CSI2 - path_type = "SENSOR_1080P_RAW12_LINER"; + csi_idx = <1>; //<1>=CSI2_B + mode_idx = <1>; + path_type = "SENSOR_1920X1088_30FPS_RAW12_LINER"; + }; + dma { + path_type = "VIPRE_CSI1_ISP1"; }; isp { subdev_name = "isp"; @@ -1472,8 +1609,12 @@ sensor0 { subdev_name = "vivcam"; idx = <0>; //vivcam0 sc2310 - csi_idx = <0>; //<0>=CSI2 - path_type = "SENSOR_1080P_RAW12_LINER"; + csi_idx = <1>; //<1>=CSI2_B + mode_idx = <1>; + path_type = "SENSOR_1920X1088_30FPS_RAW12_LINER"; + }; + dma { + path_type = "VIPRE_CSI1_ISP1"; }; isp { subdev_name = "isp"; @@ -1519,8 +1660,12 @@ sensor0 { subdev_name = "vivcam"; idx = <0>; //vivcam0 sc2310 - csi_idx = <0>; //<0>=CSI2 - path_type = "SENSOR_1080P_RAW12_LINER"; + csi_idx = <1>; //<1>=CSI2_B + mode_idx = <1>; + path_type = "SENSOR_1920X1088_30FPS_RAW12_LINER"; + }; + dma { + path_type = "VIPRE_CSI1_ISP1"; }; isp { subdev_name = "isp"; @@ -1572,7 +1717,8 @@ idx = <1>; // vivcam1 sc132gs csi_idx = <2>; //<2>=CSI2X2_A flash_led_idx = <0>; - path_type = "SENSOR_1080P_RAW10_LINER"; + mode_idx = <0>; + path_type = "SENSOR_1080X1280_30FPS_RAW10_LINER"; }; dsp{ output { @@ -1589,7 +1735,8 @@ idx = <1>; //vivcam1 sc132gs csi_idx = <2>; //<2>=CSI2X2_A flash_led_idx = <0>; - path_type = "SENSOR_1080P_RAW10_LINER"; + mode_idx = <0>; + path_type = "SENSOR_1080X1280_30FPS_RAW10_LINER"; }; dsp{ output { @@ -1608,9 +1755,21 @@ sensor0 { subdev_name = "vivcam"; idx = <2>; //<2>=vivcam2 : gc5035 - csi_idx = <1>; //<1>=CSI2X2_B - path_type = "SENSOR_1080P_RAW10_LINER"; //SENSOR_VGA_RAW10_LINER// + csi_idx = <0>; //<0>=CSI2 + mode_idx = <3>; + path_type = "SENSOR_1296x972_RAW10_LINER"; //SENSOR_VGA_RAW10_LINER// }; + sensor1 { + subdev_name = "vivcam"; + idx = <3>; //<3>=vivcam3 : gc02m1b + csi_idx = <0>; //<0>=CSI2 + mode_idx = <0>; + path_type = "SENSOR_1600x1200_RAW10_LINER"; + }; + dma { + path_type = "VIPRE_CSI0_ISP0"; + }; + isp { subdev_name = "isp"; idx = <0>; @@ -1655,9 +1814,21 @@ sensor0 { subdev_name = "vivcam"; idx = <2>; //<2>=vivcam2 : gc5035 - csi_idx = <1>; //<1>=CSI2X2_B - path_type = "SENSOR_1080P_RAW10_LINER"; //SENSOR_VGA_RAW10_LINER// + csi_idx = <0>; //<0>=CSI2 + mode_idx = <3>; + path_type = "SENSOR_1296x972_RAW10_LINER"; //SENSOR_VGA_RAW10_LINER// }; + sensor1 { + subdev_name = "vivcam"; + idx = <3>; //<3>=vivcam3 : gc02m1b + csi_idx = <0>; //<0>=CSI2 + mode_idx = <0>; + path_type = "SENSOR_1600x1200_RAW10_LINER"; + }; + dma { + path_type = "VIPRE_CSI0_ISP0"; + }; + isp { subdev_name = "isp"; idx = <0>; @@ -1702,9 +1873,21 @@ sensor0 { subdev_name = "vivcam"; idx = <2>; //<2>=vivcam2 : gc5035 - csi_idx = <1>; //<1>=CSI2X2_B - path_type = "SENSOR_1080P_RAW10_LINER"; //SENSOR_VGA_RAW10_LINER// + csi_idx = <0>; //<0>=CSI2 + mode_idx = <3>; + path_type = "SENSOR_1296x972_RAW10_LINER"; //SENSOR_VGA_RAW10_LINER// }; + sensor1 { + subdev_name = "vivcam"; + idx = <3>; //<3>=vivcam3 : gc02m1b + csi_idx = <0>; //<0>=CSI2 + mode_idx = <0>; + path_type = "SENSOR_1600x1200_RAW10_LINER"; + }; + dma { + path_type = "VIPRE_CSI0_ISP0"; + }; + isp { subdev_name = "isp"; idx = <0>; @@ -1754,8 +1937,19 @@ sensor0 { subdev_name = "vivcam"; idx = <2>; //<2>=vivcam2 : gc5035 - csi_idx = <1>; //<1>=CSI2X2_B - path_type = "SENSOR_1080P_RAW10_LINER"; //SENSOR_VGA_RAW10_LINER// + csi_idx = <0>; //<0>=CSI2 + mode_idx = <3>; + path_type = "SENSOR_1296x972_RAW10_LINER"; //SENSOR_VGA_RAW10_LINER// + }; + sensor1 { + subdev_name = "vivcam"; + idx = <3>; //<3>=vivcam3 : gc02m1b + csi_idx = <0>; //<0>=CSI2 + mode_idx = <0>; + path_type = "SENSOR_1600x1200_RAW10_LINER"; + }; + dma { + path_type = "VIPRE_CSI0_DSP"; }; dsp { subdev_name = "dsp"; @@ -1777,7 +1971,8 @@ subdev_name = "vivcam"; idx = <1>; //vivcam1 sc132gs csi_idx = <2>; //<2>=CSI2X2_A - path_type = "SENSOR_1080P_RAW10_LINER"; + mode_idx = <0>; + path_type = "SENSOR_1080X1280_30FPS_RAW10_LINER"; }; dsp{ output { @@ -1791,13 +1986,26 @@ }; -&video10{ +&video10{ // TUNINGTOOL pipline0 { sensor0 { subdev_name = "vivcam"; idx = <2>; //<2>=vivcam2 : gc5035 - csi_idx = <1>; //<1>=CSI2X2_B + csi_idx = <0>; //<0>=CSI2 + mode_idx = <1>; path_type = "SENSOR_1080P_RAW10_LINER"; //SENSOR_VGA_RAW10_LINER// + skip_init = <1>; + }; + sensor1 { + subdev_name = "vivcam"; + idx = <3>; //<3>=vivcam3 : gc02m1b + csi_idx = <0>; //<0>=CSI2 + mode_idx = <0>; + path_type = "SENSOR_1600x1200_RAW10_LINER"; + skip_init = <1>; + }; + dma { + path_type = "VIPRE_CSI0_ISP0"; }; }; }; @@ -1808,10 +2016,11 @@ status = "okay"; sensor0 { subdev_name = "vivcam"; - idx = <4>; //sc132gs + idx = <1>; //sc132gs csi_idx = <2>; //<2>=CSI2X2_A flash_led_idx = <0>; - path_type = "SENSOR_1080P_RAW10_LINER"; + mode_idx = <0>; + path_type = "SENSOR_1080X1280_30FPS_RAW10_LINER"; }; isp { subdev_name = "isp"; @@ -1827,18 +2036,116 @@ }; }; -&video12{ +&video12{ // TUNINGTOOL pipline0 { // CSI2 sensor0 { subdev_name = "vivcam"; idx = <0>; //sc2310 - csi_idx = <0>; //<0>=CSI2 - path_type = "SENSOR_1080P_RAW12_LINER"; + csi_idx = <1>; //<1>=CSI2_B + mode_idx = <1>; + path_type = "SENSOR_1920X1088_30FPS_RAW12_LINER"; + skip_init = <1>; + }; + sensor1 { + subdev_name = "vivcam"; + idx = <6>; //gc02m1b + csi_idx = <1>; //<1>=CSI2_B + mode_idx = <0>; + path_type = "SENSOR_1600x1200_RAW10_LINER"; skip_init = <1>; }; }; + dma { + path_type = "VIPRE_CSI1_ISP0"; + }; }; +&video13{ + status = "okay"; + //vi_mem_pool_region = <0>; + pipline0 { + pipline_id = <0>; + status = "okay"; + sensor0 { + subdev_name = "vivcam"; + idx = <0>; //sc2310 + csi_idx = <1>; //<1>=CSI2_B + mode_idx = <1>; + path_type = "SENSOR_1920X1088_26FPS_RAW12_LINER"; + }; + dma { + subdev_name = "vipre"; + idx = <0>; + path_type = "VIPRE_CSI0_ISP0"; + }; + isp { + subdev_name = "isp"; + idx = <0>; + path_type = "ISP_MI_MCM_WR0"; + output { + max_width = <1920>; + max_height = <1088>; + bit_per_pixel = <16>; + frame_count = <3>; + }; + }; + }; +}; + +&video14{ + vi_mem_pool_region = <2>; // vi_mem: framebuffer, region[0] + status = "okay"; + pipline0 { + pipline_id = <0>; + status = "okay"; + sensor0 { + subdev_name = "vivcam"; + idx = <1>; //sc132gs + csi_idx = <2>; //<2>=CSI2X2_A + flash_led_idx = <0>; + mode_idx = <0>; + path_type = "SENSOR_1080X1280_30FPS_RAW10_LINER"; + }; + dma { + subdev_name = "vipre"; + idx = <0>; + path_type = "VIPRE_CSI2_ISP1"; + }; + isp { + subdev_name = "isp"; + idx = <1>; + path_type = "ISP_MI_MCM_WR0"; + output { + max_width = <1080>; + max_height = <1280>; + bit_per_pixel = <16>; + frame_count = <3>; + }; + }; + }; +}; + +&video15{ + status = "okay"; + //vi_mem_pool_region = <0>; + pipline0 { + pipline_id = <0>; + status = "okay"; + sensor0 { + subdev_name = "vivcam"; + idx = <0>; //<0>=vivcam0 :2310 + csi_idx = <1>; //<1>=CSI2_B + flash_led_idx = <0>; + mode_idx = <1>; + path_type = "SENSOR_1920X1088_26FPS_RAW12_LINER"; + }; + dma { + subdev_name = "vipre"; + idx = <0>; + path_type = "VIPRE_CSI0_DDR"; + }; + }; +}; &trng { status = "disabled"; diff --git a/arch/riscv/boot/dts/thead/light-b-power.dts b/arch/riscv/boot/dts/thead/light-b-power.dts new file mode 100644 index 000000000..eeaea596b --- /dev/null +++ b/arch/riscv/boot/dts/thead/light-b-power.dts @@ -0,0 +1,134 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Copyright (C) 2021 Alibaba Group Holding Limited. + */ + +/dts-v1/; + +#include "light-b-product.dts" + +&aon { + /delete-node/light-ricoh-reg; + + soc_vdd18_lcd0_bk_en_reg: soc_vdd18_lcd0_bk_en { + compatible = "regulator-fixed"; + regulator-name = "soc_vdd18_lcd0_bk_en"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + gpio = <&gpio1_porta 9 1>; + enable-active-high; + }; + + aon_reg_dialog: light-dialog-reg { + compatible = "thead,light-dialog-pmic-ant"; + status = "okay"; + + dvdd_cpu_reg: appcpu_dvdd { + regulator-name = "appcpu_dvdd"; + regulator-min-microvolt = <300000>; + regulator-max-microvolt = <1570000>; + regulator-boot-on; + regulator-always-on; + }; + + dvddm_cpu_reg: appcpu_dvddm { + regulator-name = "appcpu_dvddm"; + regulator-min-microvolt = <300000>; + regulator-max-microvolt = <1570000>; + regulator-boot-on; + regulator-always-on; + }; + + soc_dvdd18_aon_reg: soc_dvdd18_aon { + regulator-name = "soc_dvdd18_aon"; + regulator-boot-on; + regulator-always-on; + }; + + soc_avdd33_usb3_reg: soc_avdd33_usb3 { + regulator-name = "soc_avdd33_usb3"; + regulator-boot-on; + regulator-always-on; + }; + + soc_dvdd08_aon_reg: soc_dvdd08_aon { + regulator-name = "soc_dvdd08_aon"; + regulator-boot-on; + regulator-always-on; + }; + + soc_dvdd08_ddr_reg: soc_dvdd08_ddr { + regulator-name = "soc_dvdd08_ddr"; + regulator-boot-on; + regulator-always-on; + }; + + soc_vdd_ddr_1v8_reg: soc_vdd_ddr_1v8 { + regulator-name = "soc_vdd_ddr_1v8"; + regulator-boot-on; + regulator-always-on; + }; + + soc_vdd_ddr_1v1_reg: soc_vdd_ddr_1v1 { + regulator-name = "soc_vdd_ddr_1v1"; + regulator-boot-on; + regulator-always-on; + }; + + soc_vdd_ddr_0v6_reg: soc_vdd_ddr_0v6 { + regulator-name = "soc_vdd_ddr_0v6"; + regulator-boot-on; + regulator-always-on; + }; + + soc_dvdd18_ap_reg: soc_dvdd18_ap { + regulator-name = "soc_dvdd18_ap"; + regulator-boot-on; + regulator-always-on; + }; + + soc_avdd08_mipi_hdmi_reg: soc_avdd08_mipi_hdmi { + regulator-name = "soc_avdd08_mipi_hdmi"; + regulator-boot-on; + regulator-always-on; + }; + + soc_avdd18_mipi_hdmi_reg: soc_avdd18_mipi_hdmi { + regulator-name = "soc_avdd18_mipi_hdmi"; + regulator-boot-on; + regulator-always-on; + }; + + soc_vdd33_emmc_reg: soc_vdd33_emmc { + regulator-name = "soc_vdd33_emmc"; + regulator-boot-on; + regulator-always-on; + }; + + soc_vdd18_emmc_reg: soc_vdd18_emmc { + regulator-name = "soc_vdd18_emmc"; + regulator-boot-on; + regulator-always-on; + }; +#if 0 + soc_dovdd18_scan_reg: soc_dovdd18_scan { + regulator-name = "soc_dovdd18_scan"; + }; + + soc_dvdd12_scan_reg: soc_dvdd12_scan { + regulator-name = "soc_dvdd12_scan"; + }; + + soc_avdd28_scan_en_reg: soc_avdd28_scan_en { + regulator-name = "soc_avdd28_scan_en"; + }; +#endif + + }; +}; + + +&panel0 { + + vdd1v8-supply = <&soc_vdd18_lcd0_bk_en_reg>; +}; diff --git a/arch/riscv/boot/dts/thead/light-b-product-crash.dts b/arch/riscv/boot/dts/thead/light-b-product-crash.dts new file mode 100644 index 000000000..401a76a7b --- /dev/null +++ b/arch/riscv/boot/dts/thead/light-b-product-crash.dts @@ -0,0 +1,90 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Copyright (C) 2021 Alibaba Group Holding Limited. + */ + +#include "light-crash.dts" + +&aon { + aon_reg_ricoh: light-ricoh-reg { + compatible = "thead,light-ricoh-pmic"; + status = "okay"; + + dvdd_cpu_reg: appcpu_dvdd { + regulator-name = "appcpu_dvdd"; + regulator-min-microvolt = <600000>; + regulator-max-microvolt = <1500000>; + regulator-boot-on; + regulator-always-on; + }; + + dvddm_cpu_reg: appcpu_dvddm { + regulator-name = "appcpu_dvddm"; + regulator-min-microvolt = <600000>; + regulator-max-microvolt = <1500000>; + regulator-boot-on; + regulator-always-on; + }; + }; +}; + +&cpus { + c910_0: cpu@0 { + operating-points = < + /* kHz uV */ + 300000 600000 + 800000 700000 + 1500000 800000 + >; + light,dvddm-operating-points = < + /* kHz uV */ + 300000 800000 + 800000 800000 + 1500000 800000 + >; + }; + c910_1: cpu@1 { + operating-points = < + /* kHz uV */ + 300000 600000 + 800000 700000 + 1500000 800000 + >; + light,dvddm-operating-points = < + /* kHz uV */ + 300000 800000 + 800000 800000 + 1500000 800000 + >; + }; + c910_2: cpu@2 { + + operating-points = < + /* kHz uV */ + 300000 600000 + 800000 700000 + 1500000 800000 + >; + light,dvddm-operating-points = < + /* kHz uV */ + 300000 800000 + 800000 800000 + 1500000 800000 + >; + }; + c910_3: cpu@3 { + + operating-points = < + /* kHz uV */ + 300000 600000 + 800000 700000 + 1500000 800000 + >; + light,dvddm-operating-points = < + /* kHz uV */ + 300000 800000 + 800000 800000 + 1500000 800000 + >; + }; +}; diff --git a/arch/riscv/boot/dts/thead/light-b-product-ddr1G.dts b/arch/riscv/boot/dts/thead/light-b-product-ddr1G.dts index 25d439387..a4e81ff2e 100644 --- a/arch/riscv/boot/dts/thead/light-b-product-ddr1G.dts +++ b/arch/riscv/boot/dts/thead/light-b-product-ddr1G.dts @@ -16,6 +16,6 @@ }; &cmamem { - size = <0 0x8c00000>; - alloc-ranges = <0 0x35000000 0 0x3dc00000>; + size = <0 0x8c00000>; // 140MB by default + alloc-ranges = <0 0x02000000 0 0x0cc000000>; // [0x0600_0000 ~ 0x0EC0_0000] }; diff --git a/arch/riscv/boot/dts/thead/light-b-product.dts b/arch/riscv/boot/dts/thead/light-b-product.dts index 9926593df..8e79fe7b1 100644 --- a/arch/riscv/boot/dts/thead/light-b-product.dts +++ b/arch/riscv/boot/dts/thead/light-b-product.dts @@ -20,8 +20,6 @@ chosen { bootargs = "console=ttyS0,115200 crashkernel=256M-:128M earlycon clk_ignore_unused sram=0xffe0000000,0x180000"; - linux,initrd-start = <0x0 0x2000000>; - linux,initrd-end = <0x0 0x14600000>; stdout-path = "serial0:115200n8"; }; @@ -227,14 +225,14 @@ pinctrl-names = "default"; wifi_chip_type = "rtl8723ds"; WIFI,poweren_gpio = <&gpio2_porta 29 0>; - WIFI,reset_n = <&gpio2_porta 22 0>; + WIFI,reset_n = <&gpio2_porta 24 0>; status = "okay"; }; wcn_bt: wireless-bluetooth { compatible = "bluetooth-platdata"; pinctrl-names = "default", "rts_gpio"; - BT,power_gpio = <&gpio2_porta 29 0>; + BT,power_gpio = <&gpio2_porta 25 0>; status = "okay"; }; @@ -256,7 +254,7 @@ }; }; - aon { + aon: aon@0 { compatible = "thead,light-aon"; mbox-names = "aon"; mboxes = <&mbox_910t 1 0>; @@ -560,16 +558,19 @@ 0x0 0x20688000 0x0 0x00178000>; /* DSP shared memory */ no-map; }; - facelib_mem: memory@33000000 { - reg = <0x0 0x33000000 0 0x02000000>; + vi_mem: framebuffer@10000000 { + reg = <0x0 0x10000000 0x0 0x02C00000 /* vi_mem_pool_region[0] 44 MB (default) */ + 0x0 0x12C00000 0x0 0x01D00000 /* vi_mem_pool_region[1] 29 MB */ + 0x0 0x14900000 0x0 0x01E00000>; /* vi_mem_pool_region[2] 30 MB */ no-map; }; - vi_mem: framebuffer@70000000 { - reg = <0x0 0x70000000 0x0 0x02C00000 /* vi_mem_pool_region[0] 44 MB (default) */ - 0x0 0x72C00000 0x0 0x01D00000 /* vi_mem_pool_region[1] 29 MB */ - 0x0 0x74900000 0x0 0x01E00000>; /* vi_mem_pool_region[2] 30 MB */ + + facelib_mem: memory@17000000 { + reg = <0x0 0x17000000 0 0x02000000>; no-map; }; + + }; &adc { @@ -749,6 +750,7 @@ no-mmc; non-removable; io_fixed_1v8; + post-power-on-delay-ms = <50>; wprtn_ignore; cap-sd-highspeed; keep-power-in-suspend; @@ -886,22 +888,27 @@ }; &i2c0 { + clock-frequency = <400000>; status = "okay"; }; &i2c1 { + clock-frequency = <400000>; status = "okay"; }; &i2c2 { + clock-frequency = <400000>; status = "okay"; }; &i2c3 { + clock-frequency = <400000>; status = "okay"; }; &i2c4 { + clock-frequency = <400000>; status = "okay"; }; @@ -950,7 +957,7 @@ }; &vi_pre { - //vi_pre_irq_en = <1>; + vi_pre_irq_en = <1>; status = "okay"; }; @@ -977,13 +984,12 @@ status = "okay"; }; - &vvcam_sensor0 { sensor_name = "SC2310"; sensor_regulators = "DOVDD18_RGB", "DVDD12_RGB", "AVDD28_RGB"; sensor_regulator_timing_us = <70 50 20>; sensor_rst = <&gpio1_porta 16 0>; - sensor_pdn_delay_us = <1000>; //powerdown pin / shutdown pin actived till I2C ready + sensor_pdn_delay_us = <4000>; //powerdown pin / shutdown pin actived till I2C ready DOVDD18_RGB-supply = <&soc_dovdd18_rgb_reg>; DVDD12_RGB-supply = <&soc_dvdd12_rgb_reg>; AVDD28_RGB-supply = <&soc_avdd28_rgb_reg>; @@ -1012,7 +1018,6 @@ }; */ - &vvcam_sensor1 { sensor_name = "OV5693"; i2c_bus = /bits/ 8 <3>; @@ -1042,8 +1047,9 @@ sensor_name = "SC2310"; sensor_regulators = "DOVDD18_SCAN", "DVDD12_SCAN", "AVDD28_SCAN"; sensor_regulator_timing_us = <70 50 20>; - //sensor_pdn = <&gpio1_porta 30 0>; //powerdown pin / shutdown pin - //sensor_rst = <&gpio1_porta 29 0>; + sensor_pdn = <&gpio1_porta 30 0>; //powerdown pin / shutdown pin + sensor_rst = <&gpio1_porta 29 0>; + sensor_pdn_delay_us = <4000>; //powerdown pin / shutdown pin actived till I2C ready DOVDD18_SCAN-supply = <&soc_dovdd18_scan_reg>; DVDD12_SCAN-supply = <&soc_dvdd12_scan_reg>; AVDD28_SCAN-supply = <&soc_avdd28_scan_en_reg>; @@ -1054,10 +1060,10 @@ &vvcam_sensor4 { sensor_name = "SC132GS"; sensor_regulators = "DOVDD18_IR", "DVDD12_IR", "AVDD25_IR"; - sensor_regulator_timing_us = <70 50 20>; + sensor_regulator_timing_us = <70 1000 2000>; i2c_addr = /bits/ 8 <0x31>; sensor_rst = <&gpio1_porta 24 0>; - sensor_pdn_delay_us = <1000>; //powerdown pin / shutdown pin actived till I2C ready + sensor_pdn_delay_us = <2000>; //powerdown pin / shutdown pin actived till I2C ready DOVDD18_IR-supply = <&soc_dovdd18_ir_reg>; DVDD12_IR-supply = <&soc_dvdd12_ir_reg>; AVDD25_IR-supply = <&soc_avdd25_ir_reg>; @@ -1071,7 +1077,7 @@ sensor_name = "OV12870"; sensor_regulators = "DOVDD18_RGB", "DVDD12_RGB", "AVDD28_RGB"; sensor_regulator_timing_us = <100 50 0>; - //sensor_rst = <&gpio1_porta 16 0>; + sensor_rst = <&gpio1_porta 16 0>; sensor_pdn_delay_us = <60>; //powerdown pin / shutdown pin actived till I2C ready DOVDD18_RGB-supply = <&soc_dovdd18_rgb_reg>; DVDD12_RGB-supply = <&soc_dvdd12_rgb_reg>; @@ -1083,6 +1089,22 @@ status = "okay"; }; +&vvcam_sensor6 { + sensor_name = "GC02M1B"; + sensor_regulators = "DOVDD18_RGB", "DVDD12_RGB", "AVDD28_RGB"; + sensor_regulator_timing_us = <70 50 20>; + sensor_rst = <&gpio1_porta 16 0>; + sensor_pdn_delay_us = <1000>; //powerdown pin / shutdown pin actived till I2C ready + DOVDD18_RGB-supply = <&soc_dovdd18_rgb_reg>; + DVDD12_RGB-supply = <&soc_dvdd12_rgb_reg>; + AVDD28_RGB-supply = <&soc_avdd28_rgb_reg>; + i2c_reg_width = /bits/ 8 <1>; + i2c_data_width = /bits/ 8 <1>; + i2c_addr = /bits/ 8 <0x37>; + i2c_bus = /bits/ 8 <3>; + status = "okay"; +}; + &video0{ vi_mem_pool_region = <2>; // vi_mem: framebuffer, region[2] pipline0 { @@ -1090,13 +1112,15 @@ subdev_name = "vivcam"; idx = <2>; //<2>=vivcam2 : gc5035 csi_idx = <1>; //<1>=CSI2X2_B - path_type = "SENSOR_1080P_RAW10_LINER"; //SENSOR_VGA_RAW10_LINER// + mode_idx = <3>; + path_type = "SENSOR_1296x972_RAW10_LINER"; //SENSOR_VGA_RAW10_LINER// }; sensor1 { subdev_name = "vivcam"; idx = <3>; //<3>=vivcam3 : sc2310 csi_idx = <1>; //<1>=CSI2X2_B - path_type = "SENSOR_1080P_RAW12_LINER"; + mode_idx = <1>; + path_type = "SENSOR_1920X1088_26FPS_RAW12_LINER"; }; isp { subdev_name = "isp"; @@ -1115,13 +1139,15 @@ subdev_name = "vivcam"; idx = <2>; //<2>=vivcam2 : gc5035 csi_idx = <1>; //<1>=CSI2X2_B - path_type = "SENSOR_1080P_RAW10_LINER"; //SENSOR_VGA_RAW10_LINER// + mode_idx = <3>; + path_type = "SENSOR_1296x972_RAW10_LINER"; //SENSOR_VGA_RAW10_LINER// }; sensor1 { subdev_name = "vivcam"; idx = <3>; //<3>=vivcam3 : sc2310 csi_idx = <1>; //<1>=CSI2X2_B - path_type = "SENSOR_1080P_RAW12_LINER"; + mode_idx = <1>; + path_type = "SENSOR_1920X1088_26FPS_RAW12_LINER"; }; isp { subdev_name = "isp"; @@ -1140,13 +1166,15 @@ subdev_name = "vivcam"; idx = <2>; //<2>=vivcam2 : gc5035 csi_idx = <1>; //<1>=CSI2X2_B - path_type = "SENSOR_1080P_RAW10_LINER"; //SENSOR_VGA_RAW10_LINER// + mode_idx = <3>; + path_type = "SENSOR_1296x972_RAW10_LINER"; //SENSOR_VGA_RAW10_LINER// }; sensor1 { subdev_name = "vivcam"; idx = <3>; //<3>=vivcam3 : sc2310 csi_idx = <1>; //<1>=CSI2X2_B - path_type = "SENSOR_1080P_RAW12_LINER"; + mode_idx = <1>; + path_type = "SENSOR_1920X1088_26FPS_RAW12_LINER"; }; isp { subdev_name = "isp"; @@ -1170,13 +1198,15 @@ subdev_name = "vivcam"; idx = <2>; //<2>=vivcam2 : gc5035 csi_idx = <1>; //<1>=CSI2X2_B - path_type = "SENSOR_1080P_RAW10_LINER"; + mode_idx = <3>; + path_type = "SENSOR_1296x972_RAW10_LINER"; }; sensor1 { subdev_name = "vivcam"; idx = <3>; //<3>=vivcam3 : sc2310 csi_idx = <1>; //<1>=CSI2X2_B - path_type = "SENSOR_1080P_RAW12_LINER"; + mode_idx = <1>; + path_type = "SENSOR_1920X1088_26FPS_RAW12_LINER"; }; isp { subdev_name = "isp"; @@ -1201,13 +1231,15 @@ subdev_name = "vivcam"; idx = <2>; //<2>=vivcam2 : gc5035 csi_idx = <1>; //<1>=CSI2X2_B - path_type = "SENSOR_1080P_RAW10_LINER"; + mode_idx = <3>; + path_type = "SENSOR_1296x972_RAW10_LINER"; }; sensor1 { subdev_name = "vivcam"; idx = <3>; //<3>=vivcam3 : sc2310 csi_idx = <1>; //<1>=CSI2X2_B - path_type = "SENSOR_1080P_RAW12_LINER"; + mode_idx = <1>; + path_type = "SENSOR_1920X1088_26FPS_RAW12_LINER"; }; isp { subdev_name = "isp"; @@ -1232,13 +1264,15 @@ subdev_name = "vivcam"; idx = <2>; //<2>=vivcam2 : gc5035 csi_idx = <1>; //<1>=CSI2X2_B - path_type = "SENSOR_1080P_RAW10_LINER"; + mode_idx = <3>; + path_type = "SENSOR_1296x972_RAW10_LINER"; }; sensor1 { subdev_name = "vivcam"; idx = <3>; //<3>=vivcam3 : sc2310 csi_idx = <1>; //<1>=CSI2X2_B - path_type = "SENSOR_1080P_RAW12_LINER"; + mode_idx = <1>; + path_type = "SENSOR_1920X1088_26FPS_RAW12_LINER"; }; isp { subdev_name = "isp"; @@ -1267,7 +1301,15 @@ subdev_name = "vivcam"; idx = <0>; //sc2310 csi_idx = <0>; //<0>=CSI2 - path_type = "SENSOR_1080P_RAW12_LINER"; + mode_idx = <1>; + path_type = "SENSOR_1920X1088_26FPS_RAW12_LINER"; + }; + sensor1 { + subdev_name = "vivcam"; + idx = <6>; //gc02m1b + csi_idx = <0>; //<0>=CSI2 + mode_idx = <0>; + path_type = "SENSOR_1600x1200_RAW10_LINER"; }; isp { subdev_name = "isp"; @@ -1276,7 +1318,7 @@ output { max_width = <1920>; max_height = <1088>; - bit_per_pixel = <12>; + bit_per_pixel = <16>; frame_count = <3>; }; }; @@ -1286,7 +1328,15 @@ subdev_name = "vivcam"; idx = <0>; //sc2310 csi_idx = <0>; //<0>=CSI2 - path_type = "SENSOR_1080P_RAW12_LINER"; + mode_idx = <1>; + path_type = "SENSOR_1920X1088_26FPS_RAW12_LINER"; + }; + sensor1 { + subdev_name = "vivcam"; + idx = <6>; //gc02m1b + csi_idx = <0>; //<0>=CSI2 + mode_idx = <0>; + path_type = "SENSOR_1600x1200_RAW10_LINER"; }; isp { subdev_name = "isp"; @@ -1295,7 +1345,7 @@ output { max_width = <1920>; max_height = <1088>; - bit_per_pixel = <12>; + bit_per_pixel = <16>; frame_count = <3>; }; }; @@ -1305,7 +1355,15 @@ subdev_name = "vivcam"; idx = <0>; //sc2310 csi_idx = <0>; //<0>=CSI2 - path_type = "SENSOR_1080P_RAW12_LINER"; + mode_idx = <1>; + path_type = "SENSOR_1920X1088_26FPS_RAW12_LINER"; + }; + sensor1 { + subdev_name = "vivcam"; + idx = <6>; //gc02m1b + csi_idx = <0>; //<0>=CSI2 + mode_idx = <0>; + path_type = "SENSOR_1600x1200_RAW10_LINER"; }; isp { subdev_name = "isp"; @@ -1314,7 +1372,7 @@ output { max_width = <1920>; max_height = <1088>; - bit_per_pixel = <12>; + bit_per_pixel = <16>; frame_count = <3>; }; }; @@ -1328,7 +1386,15 @@ subdev_name = "vivcam"; idx = <0>; //sc2310 csi_idx = <0>; //<0>=CSI2 - path_type = "SENSOR_1080P_RAW12_LINER"; + mode_idx = <1>; + path_type = "SENSOR_1920X1088_26FPS_RAW12_LINER"; + }; + sensor1 { + subdev_name = "vivcam"; + idx = <6>; //gc02m1b + csi_idx = <0>; //<0>=CSI2 + mode_idx = <0>; + path_type = "SENSOR_1600x1200_RAW10_LINER"; }; isp { subdev_name = "isp"; @@ -1353,7 +1419,15 @@ subdev_name = "vivcam"; idx = <0>; //sc2310 csi_idx = <0>; //<0>=CSI2 - path_type = "SENSOR_1080P_RAW12_LINER"; + mode_idx = <1>; + path_type = "SENSOR_1920X1088_26FPS_RAW12_LINER"; + }; + sensor1 { + subdev_name = "vivcam"; + idx = <6>; //gc02m1b + csi_idx = <0>; //<0>=CSI2 + mode_idx = <0>; + path_type = "SENSOR_1600x1200_RAW10_LINER"; }; isp { subdev_name = "isp"; @@ -1378,7 +1452,15 @@ subdev_name = "vivcam"; idx = <0>; //sc2310 csi_idx = <0>; //<0>=CSI2 - path_type = "SENSOR_1080P_RAW12_LINER"; + mode_idx = <1>; + path_type = "SENSOR_1920X1088_26FPS_RAW12_LINER"; + }; + sensor1 { + subdev_name = "vivcam"; + idx = <6>; //gc02m1b + csi_idx = <0>; //<0>=CSI2 + mode_idx = <0>; + path_type = "SENSOR_1600x1200_RAW10_LINER"; }; isp { subdev_name = "isp"; @@ -1407,7 +1489,15 @@ subdev_name = "vivcam"; idx = <0>; //sc2310 csi_idx = <0>; //<0>=CSI2 - path_type = "SENSOR_1080P_RAW12_LINER"; + mode_idx = <1>; + path_type = "SENSOR_1920X1088_26FPS_RAW12_LINER"; + }; + sensor1 { + subdev_name = "vivcam"; + idx = <6>; //gc02m1b + csi_idx = <0>; //<0>=CSI2 + mode_idx = <0>; + path_type = "SENSOR_1600x1200_RAW10_LINER"; }; isp { subdev_name = "isp"; @@ -1448,7 +1538,15 @@ subdev_name = "vivcam"; idx = <0>; //sc2310 csi_idx = <0>; //<0>=CSI2 - path_type = "SENSOR_1080P_RAW12_LINER"; + mode_idx = <1>; + path_type = "SENSOR_1920X1088_26FPS_RAW12_LINER"; + }; + sensor1 { + subdev_name = "vivcam"; + idx = <6>; //gc02m1b + csi_idx = <0>; //<0>=CSI2 + mode_idx = <0>; + path_type = "SENSOR_1600x1200_RAW10_LINER"; }; isp { subdev_name = "isp"; @@ -1489,7 +1587,15 @@ subdev_name = "vivcam"; idx = <0>; //sc2310 csi_idx = <0>; //<0>=CSI2 - path_type = "SENSOR_1080P_RAW12_LINER"; + mode_idx = <1>; + path_type = "SENSOR_1920X1088_26FPS_RAW12_LINER"; + }; + sensor1 { + subdev_name = "vivcam"; + idx = <6>; //gc02m1b + csi_idx = <0>; //<0>=CSI2 + mode_idx = <0>; + path_type = "SENSOR_1600x1200_RAW10_LINER"; }; isp { subdev_name = "isp"; @@ -1534,7 +1640,15 @@ subdev_name = "vivcam"; idx = <0>; //sc2310 csi_idx = <0>; //<0>=CSI2 - path_type = "SENSOR_1080P_RAW12_LINER"; + mode_idx = <1>; + path_type = "SENSOR_1920X1088_26FPS_RAW12_LINER"; + }; + sensor1 { + subdev_name = "vivcam"; + idx = <6>; //gc02m1b + csi_idx = <0>; //<0>=CSI2 + mode_idx = <0>; + path_type = "SENSOR_1600x1200_RAW10_LINER"; }; isp { subdev_name = "isp"; @@ -1581,7 +1695,15 @@ subdev_name = "vivcam"; idx = <0>; //sc2310 csi_idx = <0>; //<0>=CSI2 - path_type = "SENSOR_1080P_RAW12_LINER"; + mode_idx = <1>; + path_type = "SENSOR_1920X1088_26FPS_RAW12_LINER"; + }; + sensor1 { + subdev_name = "vivcam"; + idx = <6>; //gc02m1b + csi_idx = <0>; //<0>=CSI2 + mode_idx = <0>; + path_type = "SENSOR_1600x1200_RAW10_LINER"; }; isp { subdev_name = "isp"; @@ -1628,7 +1750,15 @@ subdev_name = "vivcam"; idx = <0>; //sc2310 csi_idx = <0>; //<0>=CSI2 - path_type = "SENSOR_1080P_RAW12_LINER"; + mode_idx = <1>; + path_type = "SENSOR_1920X1088_26FPS_RAW12_LINER"; + }; + sensor1 { + subdev_name = "vivcam"; + idx = <6>; //gc02m1b + csi_idx = <0>; //<0>=CSI2 + mode_idx = <0>; + path_type = "SENSOR_1600x1200_RAW10_LINER"; }; isp { subdev_name = "isp"; @@ -1680,7 +1810,8 @@ idx = <4>; //sc132gs csi_idx = <2>; //<2>=CSI2X2_A flash_led_idx = <0>; - path_type = "SENSOR_1080P_RAW10_LINER"; + mode_idx = <0>; + path_type = "SENSOR_1080X1280_30FPS_RAW10_LINER"; }; dsp{ output { @@ -1697,7 +1828,8 @@ idx = <4>; //sc132gs csi_idx = <2>; //<2>=CSI2X2_A flash_led_idx = <0>; - path_type = "SENSOR_1080P_RAW10_LINER"; + mode_idx = <0>; + path_type = "SENSOR_1080X1280_30FPS_RAW10_LINER"; }; dsp{ output { @@ -1717,13 +1849,15 @@ subdev_name = "vivcam"; idx = <2>; //<2>=vivcam2 : gc5035 csi_idx = <1>; //<1>=CSI2X2_B - path_type = "SENSOR_1080P_RAW10_LINER"; //SENSOR_VGA_RAW10_LINER// + mode_idx = <1>; + path_type = "SENSOR_1080P_RAW10_LINER"; }; sensor1 { subdev_name = "vivcam"; idx = <3>; //<3>=vivcam3 : sc2310 csi_idx = <1>; //<1>=CSI2X2_B - path_type = "SENSOR_1080P_RAW12_LINER"; + mode_idx = <1>; + path_type = "SENSOR_1920X1088_26FPS_RAW12_LINER"; }; isp { subdev_name = "isp"; @@ -1770,13 +1904,15 @@ subdev_name = "vivcam"; idx = <2>; //<2>=vivcam2 : gc5035 csi_idx = <1>; //<1>=CSI2X2_B - path_type = "SENSOR_1080P_RAW10_LINER"; //SENSOR_VGA_RAW10_LINER// + mode_idx = <3>; + path_type = "SENSOR_1296x972_RAW10_LINER"; //SENSOR_VGA_RAW10_LINER// }; sensor1 { subdev_name = "vivcam"; idx = <3>; //<3>=vivcam3 : sc2310 csi_idx = <1>; //<1>=CSI2X2_B - path_type = "SENSOR_1080P_RAW12_LINER"; + mode_idx = <1>; + path_type = "SENSOR_1920X1088_26FPS_RAW12_LINER"; }; isp { subdev_name = "isp"; @@ -1823,13 +1959,15 @@ subdev_name = "vivcam"; idx = <2>; //<2>=vivcam2 : gc5035 csi_idx = <1>; //<1>=CSI2X2_B - path_type = "SENSOR_1080P_RAW10_LINER"; //SENSOR_VGA_RAW10_LINER// + mode_idx = <3>; + path_type = "SENSOR_1296x972_RAW10_LINER"; //SENSOR_VGA_RAW10_LINER// }; sensor1 { subdev_name = "vivcam"; idx = <3>; //<3>=vivcam3 : sc2310 csi_idx = <1>; //<1>=CSI2X2_B - path_type = "SENSOR_1080P_RAW12_LINER"; + mode_idx = <1>; + path_type = "SENSOR_1920X1088_26FPS_RAW12_LINER"; }; isp { subdev_name = "isp"; @@ -1881,13 +2019,15 @@ subdev_name = "vivcam"; idx = <2>; //<2>=vivcam2 : gc5035 csi_idx = <1>; //<1>=CSI2X2_B - path_type = "SENSOR_1080P_RAW10_LINER"; //SENSOR_VGA_RAW10_LINER// + mode_idx = <3>; + path_type = "SENSOR_1296x972_RAW10_LINER"; //SENSOR_VGA_RAW10_LINER// }; sensor1 { subdev_name = "vivcam"; idx = <3>; //<3>=vivcam3 : sc2310 csi_idx = <1>; //<1>=CSI2X2_B - path_type = "SENSOR_1080P_RAW12_LINER"; + mode_idx = <1>; + path_type = "SENSOR_1920X1088_26FPS_RAW12_LINER"; }; dsp { subdev_name = "dsp"; @@ -1909,7 +2049,8 @@ subdev_name = "vivcam"; idx = <4>; //sc132gs csi_idx = <2>; //<2>=CSI2X2_A - path_type = "SENSOR_1080P_RAW10_LINER"; + mode_idx = <0>; + path_type = "SENSOR_1080X1280_30FPS_RAW10_LINER"; }; dsp{ output { @@ -1923,19 +2064,23 @@ }; -&video10{ +&video10{ // TUNINGTOOL pipline0 { sensor0 { subdev_name = "vivcam"; idx = <2>; //<2>=vivcam2 : gc5035 csi_idx = <1>; //<1>=CSI2X2_B + mode_idx = <1>; path_type = "SENSOR_1080P_RAW10_LINER"; //SENSOR_VGA_RAW10_LINER// + skip_init = <1>; }; sensor1 { subdev_name = "vivcam"; idx = <3>; //<3>=vivcam3 : sc2310 csi_idx = <1>; //<1>=CSI2X2_B - path_type = "SENSOR_1080P_RAW12_LINER"; + mode_idx = <1>; + path_type = "SENSOR_1920X1088_26FPS_RAW12_LINER"; + skip_init = <1>; }; }; }; @@ -1949,7 +2094,8 @@ idx = <4>; //sc132gs csi_idx = <2>; //<2>=CSI2X2_A flash_led_idx = <0>; - path_type = "SENSOR_1080P_RAW10_LINER"; + mode_idx = <0>; + path_type = "SENSOR_1080X1280_30FPS_RAW10_LINER"; }; isp { subdev_name = "isp"; @@ -1965,15 +2111,79 @@ }; }; -&video12{ +&video12{ // TUNINGTOOL pipline0 { // CSI2 sensor0 { subdev_name = "vivcam"; idx = <0>; //sc2310 csi_idx = <0>; //<0>=CSI2 - path_type = "SENSOR_1080P_RAW12_LINER"; + mode_idx = <1>; + path_type = "SENSOR_1920X1088_26FPS_RAW12_LINER"; skip_init = <1>; }; + sensor1 { + subdev_name = "vivcam"; + idx = <6>; //gc02m1b + csi_idx = <0>; //<0>=CSI2 + mode_idx = <0>; + path_type = "SENSOR_1600x1200_RAW10_LINER"; + skip_init = <1>; + }; + }; +}; + +&video14{ + vi_mem_pool_region = <2>; // vi_mem: framebuffer, region[0] + status = "okay"; + pipline0 { + pipline_id = <0>; + status = "okay"; + sensor0 { + subdev_name = "vivcam"; + idx = <4>; //sc132gs + csi_idx = <2>; //<2>=CSI2X2_A + flash_led_idx = <0>; + mode_idx = <0>; + path_type = "SENSOR_1080X1280_30FPS_RAW10_LINER"; + }; + dma { + subdev_name = "vipre"; + idx = <0>; + path_type = "VIPRE_CSI2_ISP1"; + }; + isp { + subdev_name = "isp"; + idx = <1>; + path_type = "ISP_MI_MCM_WR0"; + output { + max_width = <1080>; + max_height = <1280>; + bit_per_pixel = <16>; + frame_count = <3>; + }; + }; + }; +}; + +&video15{ + status = "okay"; + //vi_mem_pool_region = <0>; + pipline0 { + pipline_id = <0>; + status = "okay"; + sensor0 { + subdev_name = "vivcam"; + idx = <0>; //<0>=vivcam0 :2310 + csi_idx = <0>; //<0>=CSI2 + flash_led_idx = <0>; + mode_idx = <1>; + path_type = "SENSOR_1920X1088_26FPS_RAW12_LINER"; + }; + dma { + subdev_name = "vipre"; + idx = <0>; + path_type = "VIPRE_CSI0_DDR"; + }; }; }; @@ -2067,7 +2277,7 @@ }; }; - panel0@0 { + panel0: panel0@0 { compatible = "txd,dy800qwxpab"; reg = <0>; backlight = <&lcd0_backlight>; diff --git a/arch/riscv/boot/dts/thead/light-b-ref.dts b/arch/riscv/boot/dts/thead/light-b-ref.dts new file mode 100644 index 000000000..eeaea596b --- /dev/null +++ b/arch/riscv/boot/dts/thead/light-b-ref.dts @@ -0,0 +1,134 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Copyright (C) 2021 Alibaba Group Holding Limited. + */ + +/dts-v1/; + +#include "light-b-product.dts" + +&aon { + /delete-node/light-ricoh-reg; + + soc_vdd18_lcd0_bk_en_reg: soc_vdd18_lcd0_bk_en { + compatible = "regulator-fixed"; + regulator-name = "soc_vdd18_lcd0_bk_en"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + gpio = <&gpio1_porta 9 1>; + enable-active-high; + }; + + aon_reg_dialog: light-dialog-reg { + compatible = "thead,light-dialog-pmic-ant"; + status = "okay"; + + dvdd_cpu_reg: appcpu_dvdd { + regulator-name = "appcpu_dvdd"; + regulator-min-microvolt = <300000>; + regulator-max-microvolt = <1570000>; + regulator-boot-on; + regulator-always-on; + }; + + dvddm_cpu_reg: appcpu_dvddm { + regulator-name = "appcpu_dvddm"; + regulator-min-microvolt = <300000>; + regulator-max-microvolt = <1570000>; + regulator-boot-on; + regulator-always-on; + }; + + soc_dvdd18_aon_reg: soc_dvdd18_aon { + regulator-name = "soc_dvdd18_aon"; + regulator-boot-on; + regulator-always-on; + }; + + soc_avdd33_usb3_reg: soc_avdd33_usb3 { + regulator-name = "soc_avdd33_usb3"; + regulator-boot-on; + regulator-always-on; + }; + + soc_dvdd08_aon_reg: soc_dvdd08_aon { + regulator-name = "soc_dvdd08_aon"; + regulator-boot-on; + regulator-always-on; + }; + + soc_dvdd08_ddr_reg: soc_dvdd08_ddr { + regulator-name = "soc_dvdd08_ddr"; + regulator-boot-on; + regulator-always-on; + }; + + soc_vdd_ddr_1v8_reg: soc_vdd_ddr_1v8 { + regulator-name = "soc_vdd_ddr_1v8"; + regulator-boot-on; + regulator-always-on; + }; + + soc_vdd_ddr_1v1_reg: soc_vdd_ddr_1v1 { + regulator-name = "soc_vdd_ddr_1v1"; + regulator-boot-on; + regulator-always-on; + }; + + soc_vdd_ddr_0v6_reg: soc_vdd_ddr_0v6 { + regulator-name = "soc_vdd_ddr_0v6"; + regulator-boot-on; + regulator-always-on; + }; + + soc_dvdd18_ap_reg: soc_dvdd18_ap { + regulator-name = "soc_dvdd18_ap"; + regulator-boot-on; + regulator-always-on; + }; + + soc_avdd08_mipi_hdmi_reg: soc_avdd08_mipi_hdmi { + regulator-name = "soc_avdd08_mipi_hdmi"; + regulator-boot-on; + regulator-always-on; + }; + + soc_avdd18_mipi_hdmi_reg: soc_avdd18_mipi_hdmi { + regulator-name = "soc_avdd18_mipi_hdmi"; + regulator-boot-on; + regulator-always-on; + }; + + soc_vdd33_emmc_reg: soc_vdd33_emmc { + regulator-name = "soc_vdd33_emmc"; + regulator-boot-on; + regulator-always-on; + }; + + soc_vdd18_emmc_reg: soc_vdd18_emmc { + regulator-name = "soc_vdd18_emmc"; + regulator-boot-on; + regulator-always-on; + }; +#if 0 + soc_dovdd18_scan_reg: soc_dovdd18_scan { + regulator-name = "soc_dovdd18_scan"; + }; + + soc_dvdd12_scan_reg: soc_dvdd12_scan { + regulator-name = "soc_dvdd12_scan"; + }; + + soc_avdd28_scan_en_reg: soc_avdd28_scan_en { + regulator-name = "soc_avdd28_scan_en"; + }; +#endif + + }; +}; + + +&panel0 { + + vdd1v8-supply = <&soc_vdd18_lcd0_bk_en_reg>; +}; diff --git a/arch/riscv/boot/dts/thead/light-beagle.dts b/arch/riscv/boot/dts/thead/light-beagle.dts new file mode 100644 index 000000000..2c442dea5 --- /dev/null +++ b/arch/riscv/boot/dts/thead/light-beagle.dts @@ -0,0 +1,608 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Copyright (C) 2021 Alibaba Group Holding Limited. + */ + +/dts-v1/; + +#include "light-ant-ref.dts" + +&vvcam_sensor4 { // beagle board J5 CSI0 connector + sensor_name = "IMX219"; + sensor_pdn = <&gpio2_porta 23 0>; //powerdown pin / shutdown pin + sensor_pdn_delay_us = <2000>; //powerdown pin / shutdown pin actived till I2C ready + i2c_addr = /bits/ 8 <0x10>; + i2c_bus = /bits/ 8 <1>; + i2c_reg_width = /bits/ 8 <2>; + i2c_data_width = /bits/ 8 <1>; + status = "okay"; +}; + +&vvcam_sensor5 { // beagle board J4 CSI1 connector + sensor_name = "IMX219"; + sensor_pdn = <&gpio2_porta 24 0>; //powerdown pin / shutdown pin + sensor_pdn_delay_us = <2000>; //powerdown pin / shutdown pin actived till I2C ready + i2c_addr = /bits/ 8 <0x10>; + i2c_bus = /bits/ 8 <3>; + i2c_reg_width = /bits/ 8 <2>; + i2c_data_width = /bits/ 8 <1>; + status = "okay"; +}; + +/* +sensor imx219 mounted on beagle board J4 +video0: sensor-vipre-isp0 +video1: sensor-vipre-isp0-dw +video7: sensor-vipre-isp0-dsp1-ry-dw +video10: tuningtool + +sensor imx219 mounted on beagle board J5 +video2: sensor-vipre-isp1 +video3: sensor-vipre-isp1-dw +video4: sensor-vipre-isp1-dsp0-ry +video5: sensor-vipre-isp1-dsp0-ry-dw +video12: tuningtool +*/ + +&video2 { + vi_mem_pool_region = <0>; // vi_mem: framebuffer, region[0] + status = "okay"; + pipline0 { + pipline_id = <0>; + status = "okay"; + sensor0 { + subdev_name = "vivcam"; + idx = <4>; // imx219 + csi_idx = <0>; //<0>=CSI2 + mode_idx = <0>; + path_type = "SENSOR_1080P_RAW10_LINER"; + }; + sensor1 { + subdev_name = "vivcam"; + idx = <0xff>; // invalid + csi_idx = <0xff>; + path_type = "SENSOR_VGA_RAW10_LINER"; + }; + dma { + subdev_name = "vipre"; + idx = <0>; + path_type = "VIPRE_CSI0_ISP1"; + }; + isp { + subdev_name = "isp"; + idx = <1>; + path_type = "ISP_MI_PATH_MP"; + output { + max_width = <1920>; + max_height = <1088>; + bit_per_pixel = <16>; + frame_count = <3>; + }; + }; + }; + pipline1 { + pipline_id = <1>; + status = "okay"; + sensor0 { + subdev_name = "vivcam"; + idx = <4>; // imx219 + csi_idx = <0>; //<0>=CSI2 + mode_idx = <0>; + path_type = "SENSOR_1080P_RAW10_LINER"; + }; + sensor1 { + subdev_name = "vivcam"; + idx = <0xff>; // invalid + csi_idx = <0xff>; + path_type = "SENSOR_VGA_RAW10_LINER"; + }; + dma { + subdev_name = "vipre"; + idx = <0>; + path_type = "VIPRE_CSI0_ISP1"; + }; + isp { + subdev_name = "isp"; + idx = <1>; + path_type = "ISP_MI_PATH_SP"; + output { + max_width = <1920>; + max_height = <1088>; + bit_per_pixel = <16>; + frame_count = <3>; + }; + }; + }; + pipline2 { + pipline_id = <2>; + status = "okay"; + sensor0 { + subdev_name = "vivcam"; + idx = <4>; // imx219 + csi_idx = <0>; //<0>=CSI2 + mode_idx = <0>; + path_type = "SENSOR_1080P_RAW10_LINER"; + }; + sensor1 { + subdev_name = "vivcam"; + idx = <0xff>; // invalid + csi_idx = <0xff>; + path_type = "SENSOR_VGA_RAW10_LINER"; + }; + dma { + subdev_name = "vipre"; + idx = <0>; + path_type = "VIPRE_CSI0_ISP1"; + }; + isp { + subdev_name = "isp"; + idx = <1>; + path_type = "ISP_MI_PATH_SP2_BP"; + output { + max_width = <1920>; + max_height = <1088>; + bit_per_pixel = <16>; + frame_count = <3>; + }; + }; + }; +}; + +&video3{ + vi_mem_pool_region = <0>; // vi_mem: framebuffer, region[0] + pipline0 { + sensor0 { + subdev_name = "vivcam"; + idx = <4>; // imx219 + csi_idx = <0>; //<0>=CSI2 + mode_idx = <0>; + path_type = "SENSOR_1080P_RAW10_LINER"; + }; + sensor1 { + subdev_name = "vivcam"; + idx = <0xff>; // invalid + csi_idx = <0xff>; + path_type = "SENSOR_VGA_RAW10_LINER"; + }; + dma { + subdev_name = "vipre"; + idx = <0>; + path_type = "VIPRE_CSI0_ISP1"; + }; + isp { + subdev_name = "isp"; + idx = <1>; + path_type = "ISP_MI_PATH_MP"; + output { + max_width = <1920>; + max_height = <1088>; + bit_per_pixel = <12>; + frame_count = <3>; + }; + }; + dw { + subdev_name = "dw"; + idx = <0>; + path_type = "DW_DWE_VSE0"; + dw_dst_depth = <2>; + }; + }; + pipline1 { + sensor0 { + subdev_name = "vivcam"; + idx = <4>; // imx219 + csi_idx = <0>; //<0>=CSI2 + mode_idx = <0>; + path_type = "SENSOR_1080P_RAW10_LINER"; + }; + sensor1 { + subdev_name = "vivcam"; + idx = <0xff>; // invalid + csi_idx = <0xff>; + path_type = "SENSOR_VGA_RAW10_LINER"; + }; + dma { + subdev_name = "vipre"; + idx = <0>; + path_type = "VIPRE_CSI0_ISP1"; + }; + isp { + subdev_name = "isp"; + idx = <1>; + path_type = "ISP_MI_PATH_MP"; + output { + max_width = <1920>; + max_height = <1088>; + bit_per_pixel = <12>; + frame_count = <3>; + }; + }; + dw { + subdev_name = "dw"; + idx = <0>; + path_type = "DW_DWE_VSE1"; + dw_dst_depth = <2>; + }; + }; + pipline2 { + sensor0 { + subdev_name = "vivcam"; + idx = <4>; // imx219 + csi_idx = <0>; //<0>=CSI2 + mode_idx = <0>; + path_type = "SENSOR_1080P_RAW10_LINER"; + }; + sensor1 { + subdev_name = "vivcam"; + idx = <0xff>; // invalid + csi_idx = <0xff>; + path_type = "SENSOR_VGA_RAW10_LINER"; + }; + dma { + subdev_name = "vipre"; + idx = <0>; + path_type = "VIPRE_CSI0_ISP1"; + }; + isp { + subdev_name = "isp"; + idx = <1>; + path_type = "ISP_MI_PATH_MP"; + output { + max_width = <1920>; + max_height = <1088>; + bit_per_pixel = <12>; + frame_count = <3>; + }; + }; + dw { + subdev_name = "dw"; + idx = <0>; + path_type = "DW_DWE_VSE2"; + dw_dst_depth = <2>; + }; + }; +}; + +&video4{ + vi_mem_pool_region = <0>; // vi_mem: framebuffer, region[0] + pipline0 { + sensor0 { + subdev_name = "vivcam"; + idx = <4>; // imx219 + csi_idx = <0>; //<0>=CSI2 + mode_idx = <0>; + path_type = "SENSOR_1080P_RAW10_LINER"; + }; + sensor1 { + subdev_name = "vivcam"; + idx = <0xff>; // invalid + csi_idx = <0xff>; + path_type = "SENSOR_VGA_RAW10_LINER"; + }; + dma { + subdev_name = "vipre"; + idx = <0>; + path_type = "VIPRE_CSI0_ISP1"; + }; + isp { + subdev_name = "isp"; + idx = <1>; + path_type = "ISP_MI_PATH_PP"; + output { + max_width = <1920>; + max_height = <1088>; + bit_per_pixel = <12>; + frame_count = <3>; + }; + }; + dsp { + subdev_name = "dsp"; + idx = <0>; + path_type = "DSP_PATH_ISP_RY"; + output { + max_width = <1920>; + max_height = <1088>; + bit_per_pixel = <12>; + frame_count = <3>; + }; + }; + ry { + subdev_name = "ry"; + idx = <0>; + path_type = "ISP_RY_MI_PATH_MP"; + output { + max_width = <1920>; + max_height = <1088>; + bit_per_pixel = <12>; + frame_count = <3>; + }; + }; + }; + pipline1 { + sensor0 { + subdev_name = "vivcam"; + idx = <4>; // imx219 + csi_idx = <0>; //<0>=CSI2 + mode_idx = <0>; + path_type = "SENSOR_1080P_RAW10_LINER"; + }; + sensor1 { + subdev_name = "vivcam"; + idx = <0xff>; // invalid + csi_idx = <0xff>; + path_type = "SENSOR_VGA_RAW10_LINER"; + }; + dma { + subdev_name = "vipre"; + idx = <0>; + path_type = "VIPRE_CSI0_ISP1"; + }; + isp { + subdev_name = "isp"; + idx = <1>; + path_type = "ISP_MI_PATH_PP"; + output { + max_width = <1920>; + max_height = <1088>; + bit_per_pixel = <12>; + frame_count = <3>; + }; + }; + dsp { + subdev_name = "dsp"; + idx = <0>; + path_type = "DSP_PATH_ISP_RY"; + output { + max_width = <1920>; + max_height = <1088>; + bit_per_pixel = <12>; + frame_count = <3>; + }; + }; + ry { + subdev_name = "ry"; + idx = <0>; + path_type = "ISP_RY_MI_PATH_SP"; + output { + max_width = <1920>; + max_height = <1088>; + bit_per_pixel = <12>; + frame_count = <3>; + }; + }; + }; + pipline2 { + sensor0 { + subdev_name = "vivcam"; + idx = <4>; // imx219 + csi_idx = <0>; //<0>=CSI2 + mode_idx = <0>; + path_type = "SENSOR_1080P_RAW10_LINER"; + }; + sensor1 { + subdev_name = "vivcam"; + idx = <0xff>; // invalid + csi_idx = <0xff>; + path_type = "SENSOR_VGA_RAW10_LINER"; + }; + dma { + subdev_name = "vipre"; + idx = <0>; + path_type = "VIPRE_CSI0_ISP1"; + }; + isp { + subdev_name = "isp"; + idx = <1>; + path_type = "ISP_MI_PATH_PP"; + output { + max_width = <1920>; + max_height = <1088>; + bit_per_pixel = <12>; + frame_count = <3>; + }; + }; + dsp { + subdev_name = "dsp"; + idx = <0>; + path_type = "DSP_PATH_ISP_RY"; + output { + max_width = <1920>; + max_height = <1088>; + bit_per_pixel = <12>; + frame_count = <3>; + }; + }; + ry { + subdev_name = "ry"; + idx = <0>; + path_type = "ISP_RY_MI_PATH_SP2_BP"; + output { + max_width = <1920>; + max_height = <1088>; + bit_per_pixel = <12>; + frame_count = <3>; + }; + }; + }; +}; + +&video5{ + vi_mem_pool_region = <0>; // vi_mem: framebuffer, region[0] + pipline0 { + sensor0 { + subdev_name = "vivcam"; + idx = <4>; // imx219 + csi_idx = <0>; //<0>=CSI2 + mode_idx = <0>; + path_type = "SENSOR_1080P_RAW10_LINER"; + }; + sensor1 { + subdev_name = "vivcam"; + idx = <0xff>; // invalid + csi_idx = <0xff>; + path_type = "SENSOR_VGA_RAW10_LINER"; + }; + dma { + subdev_name = "vipre"; + idx = <0>; + path_type = "VIPRE_CSI0_ISP1"; + }; + isp { + subdev_name = "isp"; + idx = <1>; + path_type = "ISP_MI_PATH_PP"; + output { + max_width = <1920>; + max_height = <1088>; + bit_per_pixel = <12>; + frame_count = <3>; + }; + }; + dsp { + subdev_name = "dsp"; + idx = <0>; + path_type = "DSP_PATH_ISP_RY"; + output { + max_width = <1920>; + max_height = <1088>; + bit_per_pixel = <12>; + frame_count = <3>; + }; + }; + ry { + subdev_name = "ry"; + idx = <0>; + path_type = "ISP_RY_MI_PATH_MP"; + output { + max_width = <1920>; + max_height = <1088>; + bit_per_pixel = <12>; + frame_count = <3>; + }; + }; + dw { + subdev_name = "dw"; + idx = <0>; + path_type = "DW_DWE_VSE0"; + dw_dst_depth = <2>; + }; + }; + pipline1 { + sensor0 { + subdev_name = "vivcam"; + idx = <4>; // imx219 + csi_idx = <0>; //<0>=CSI2 + mode_idx = <0>; + path_type = "SENSOR_1080P_RAW10_LINER"; + }; + sensor1 { + subdev_name = "vivcam"; + idx = <0xff>; // invalid + csi_idx = <0xff>; + path_type = "SENSOR_VGA_RAW10_LINER"; + }; + dma { + subdev_name = "vipre"; + idx = <0>; + path_type = "VIPRE_CSI0_ISP1"; + }; + isp { + subdev_name = "isp"; + idx = <1>; + path_type = "ISP_MI_PATH_PP"; + output { + max_width = <1920>; + max_height = <1088>; + bit_per_pixel = <12>; + frame_count = <3>; + }; + }; + dsp { + subdev_name = "dsp"; + idx = <0>; + path_type = "DSP_PATH_ISP_RY"; + output { + max_width = <1920>; + max_height = <1088>; + bit_per_pixel = <12>; + frame_count = <3>; + }; + }; + ry { + subdev_name = "ry"; + idx = <0>; + path_type = "ISP_RY_MI_PATH_MP"; + output { + max_width = <1920>; + max_height = <1088>; + bit_per_pixel = <12>; + frame_count = <3>; + }; + }; + dw { + subdev_name = "dw"; + idx = <0>; + path_type = "DW_DWE_VSE1"; + dw_dst_depth = <2>; + }; + }; + pipline2 { + sensor0 { + subdev_name = "vivcam"; + idx = <4>; // imx219 + csi_idx = <0>; //<0>=CSI2 + mode_idx = <0>; + path_type = "SENSOR_1080P_RAW10_LINER"; + }; + sensor1 { + subdev_name = "vivcam"; + idx = <0xff>; // invalid + csi_idx = <0xff>; + path_type = "SENSOR_VGA_RAW10_LINER"; + }; + dma { + subdev_name = "vipre"; + idx = <0>; + path_type = "VIPRE_CSI0_ISP1"; + }; + isp { + subdev_name = "isp"; + idx = <1>; + path_type = "ISP_MI_PATH_PP"; + output { + max_width = <1920>; + max_height = <1088>; + bit_per_pixel = <12>; + frame_count = <3>; + }; + }; + dsp { + subdev_name = "dsp"; + idx = <0>; + path_type = "DSP_PATH_ISP_RY"; + output { + max_width = <1920>; + max_height = <1088>; + bit_per_pixel = <12>; + frame_count = <3>; + }; + }; + ry { + subdev_name = "ry"; + idx = <0>; + path_type = "ISP_RY_MI_PATH_MP"; + output { + max_width = <1920>; + max_height = <1088>; + bit_per_pixel = <12>; + frame_count = <3>; + }; + }; + dw { + subdev_name = "dw"; + idx = <0>; + path_type = "DW_DWE_VSE2"; + dw_dst_depth = <2>; + }; + }; +}; \ No newline at end of file diff --git a/arch/riscv/boot/dts/thead/light-crash.dts b/arch/riscv/boot/dts/thead/light-crash.dts new file mode 100644 index 000000000..d8c3f144d --- /dev/null +++ b/arch/riscv/boot/dts/thead/light-crash.dts @@ -0,0 +1,883 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Copyright (C) 2021 Alibaba Group Holding Limited. + */ + +/dts-v1/; + +#include "light.dtsi" +#include +#include +#include "light-vi-devices.dtsi" +/ { + model = "T-HEAD Light val board"; + compatible = "thead,light-val", "thead,light"; + + chosen { + bootargs = "console=ttyS0,115200 earlycon"; + stdout-path = "serial0:115200n8"; + }; + + leds { + compatible = "gpio-leds"; + status = "disabled"; + led0 { + label = "SYS_STATUS"; + gpios = <&gpio1_porta 15 0>; /* GPIO_ACTIVE_HIGH: 0 */ + default-state = "off"; + }; + }; + + display-subsystem { + status = "okay"; + }; + + lcd0_backlight: pwm-backlight@0 { + status = "disabled"; + compatible = "pwm-backlight"; + pwms = <&pwm 0 5000000>; + brightness-levels = <0 4 8 16 32 64 128 255>; + default-brightness-level = <7>; + }; + + light_iopmp: iopmp { + status = "disabled"; + compatible = "thead,light-iopmp"; + + /* config#1: multiple valid regions */ + iopmp_emmc: IOPMP_EMMC { + regions = <0x000000 0x100000>, + <0x100000 0x200000>; + attr = <0xFFFFFFFF>; + dummy_slave= <0x800000>; + }; + + /* config#2: iopmp bypass */ + iopmp_sdio0: IOPMP_SDIO0 { + bypass_en; + }; + + /* config#3: iopmp default region set */ + iopmp_sdio1: IOPMP_SDIO1 { + attr = <0xFFFFFFFF>; + is_default_region; + }; + + iopmp_usb0: IOPMP_USB0 { + attr = <0xFFFFFFFF>; + is_default_region; + }; + + iopmp_ao: IOPMP_AO { + is_default_region; + }; + + iopmp_aud: IOPMP_AUD { + is_default_region; + }; + + iopmp_chip_dbg: IOPMP_CHIP_DBG { + is_default_region; + }; + + iopmp_eip120i: IOPMP_EIP120I { + is_default_region; + }; + + iopmp_eip120ii: IOPMP_EIP120II { + is_default_region; + }; + + iopmp_eip120iii: IOPMP_EIP120III { + is_default_region; + }; + + iopmp_isp0: IOPMP_ISP0 { + is_default_region; + }; + + iopmp_isp1: IOPMP_ISP1 { + is_default_region; + }; + + iopmp_dw200: IOPMP_DW200 { + is_default_region; + }; + + iopmp_vipre: IOPMP_VIPRE { + is_default_region; + }; + + iopmp_venc: IOPMP_VENC { + is_default_region; + }; + + iopmp_vdec: IOPMP_VDEC { + is_default_region; + }; + + iopmp_g2d: IOPMP_G2D { + is_default_region; + }; + + iopmp_fce: IOPMP_FCE { + is_default_region; + }; + + iopmp_npu: IOPMP_NPU { + is_default_region; + }; + + iopmp0_dpu: IOPMP0_DPU { + bypass_en; + }; + + iopmp1_dpu: IOPMP1_DPU { + bypass_en; + }; + + iopmp_gpu: IOPMP_GPU { + is_default_region; + }; + + iopmp_gmac1: IOPMP_GMAC1 { + is_default_region; + }; + + iopmp_gmac2: IOPMP_GMAC2 { + is_default_region; + }; + + iopmp_dmac: IOPMP_DMAC { + is_default_region; + }; + + iopmp_tee_dmac: IOPMP_TEE_DMAC { + is_default_region; + }; + + iopmp_dsp0: IOPMP_DSP0 { + is_default_region; + }; + + iopmp_dsp1: IOPMP_DSP1 { + is_default_region; + }; + }; + + mbox_910t_client1: mbox_910t_client1 { + compatible = "thead,light-mbox-client"; + mbox-names = "902"; + mboxes = <&mbox_910t 1 0>; + status = "disabled"; + }; + + + mbox_910t_client2: mbox_910t_client2 { + compatible = "thead,light-mbox-client"; + mbox-names = "906"; + mboxes = <&mbox_910t 2 0>; + status = "disabled"; + }; + + lightsound: lightsound@1 { + compatible = "simple-audio-card"; + simple-audio-card,name = "Light-Sound-Card"; + + #address-cells = <1>; + #size-cells = <0>; + + status = "disabled"; + }; + + dummy_codec: dummy_codec { + #sound-dai-cells = <1>; + compatible = "linux,bt-sco"; + status = "okay"; + }; + + reg_vref_1v8: regulator-adc-verf { + compatible = "regulator-fixed"; + regulator-name = "vref-1v8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + status = "okay"; + }; + + reg_tp_pwr_en: regulator-pwr-en { + compatible = "regulator-fixed"; + regulator-name = "PWR_EN"; + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <2800000>; + gpio = <&gpio1_porta 12 1>; + enable-active-high; + regulator-always-on; + }; + + wcn_wifi: wireless-wlan { + compatible = "wlan-platdata"; + clock-names = "clk_wifi"; + ref-clock-frequency = <24000000>; + keep_wifi_power_on; + pinctrl-names = "default"; + wifi_chip_type = "rtl8723ds"; + WIFI,poweren_gpio = <&gpio2_porta 29 0>; + WIFI,reset_n = <&gpio2_porta 24 0>; + status = "okay"; + }; + + wcn_bt: wireless-bluetooth { + compatible = "bluetooth-platdata"; + pinctrl-names = "default", "rts_gpio"; + BT,power_gpio = <&gpio2_porta 25 0>; + status = "okay"; + }; + + gpio-keys { + compatible = "gpio-keys"; + pinctrl-0 = <&pinctrl_volume>; + pinctrl-names = "default"; + key-volumedown { + label = "Volume Down Key"; + linux,code = ; + debounce-interval = <1>; + gpios = <&ao_gpio_porta 11 0x1>; + }; + key-volumeup { + label = "Volume Up Key"; + linux,code = ; + debounce-interval = <1>; + gpios = <&ao_gpio_porta 10 0x1>; + }; + }; + + aon: light-aon { + compatible = "thead,light-aon"; + mbox-names = "aon"; + mboxes = <&mbox_910t 1 0>; + status = "okay"; + + pd: light-aon-pd { + compatible = "thead,light-aon-pd"; + #power-domain-cells = <1>; + }; + + c910_cpufreq { + compatible = "thead,light-mpw-cpufreq"; + status = "okay"; + }; + + test: light-aon-test { + compatible = "thead,light-aon-test"; + }; + }; +}; + +&resmem { + #address-cells = <2>; + #size-cells = <2>; + ranges; + + tee_mem: memory@1a000000 { + reg = <0x0 0x1a000000 0 0x4000000>; + no-map; + }; + + dsp0_mem: memory@20000000 { /**0x2000_0000~0x2040_0000 4M**/ + reg = <0x0 0x20000000 0x0 0x00280000 /* DSP FW code&data section 2.5M*/ + 0x0 0x20280000 0x0 0x00001000 /* DSP communication area 4K*/ + 0x0 0x20281000 0x0 0x00007000 /* Panic/log page 28K */ + 0x0 0x20288000 0x0 0x00178000>; /* DSP shared memory 1.5M-32K*/ + no-map; + }; + dsp1_mem: memory@20400000 { /**0x2040_0000~0x2080_0000 4M**/ + reg = <0x0 0x20400000 0x0 0x00280000 /* DSP FW code&data section */ + 0x0 0x20680000 0x0 0x00001000 /* DSP communication area */ + 0x0 0x20681000 0x0 0x00007000 /* Panic/log page*/ + 0x0 0x20688000 0x0 0x00178000>; /* DSP shared memory */ + no-map; + }; + vi_mem: framebuffer@10000000 { + reg = <0x0 0x10000000 0x0 0x02C00000 /* vi_mem_pool_region[0] 44 MB (default) */ + 0x0 0x12C00000 0x0 0x01D00000 /* vi_mem_pool_region[1] 29 MB */ + 0x0 0x14900000 0x0 0x01E00000>; /* vi_mem_pool_region[2] 30 MB */ + no-map; + }; + facelib_mem: memory@17000000 { + reg = <0x0 0x17000000 0 0x02000000>; + no-map; + }; +}; + +&adc { + vref-supply = <®_vref_1v8>; + status = "okay"; +}; + +&i2c0 { + clock-frequency = <100000>; + status = "okay"; + + touch@5d { + #gpio-cells = <2>; + compatible = "goodix,gt911"; + reg = <0x5d>; + interrupt-parent = <&gpio1_porta>; + interrupts = <8 0>; + irq-gpios = <&gpio1_porta 8 0>; + reset-gpios = <&gpio1_porta 7 0>; + AVDD28-supply = <®_tp_pwr_en>; + touchscreen-size-x = <720>; + touchscreen-size-y = <1280>; + }; + +}; + +&audio_i2c0 { + clock-frequency = <100000>; + status = "okay"; + + es8156_audio_codec: es8156@8 { + #sound-dai-cells = <0>; + compatible = "everest,es8156"; + reg = <0x08>; + }; + + es7210_audio_codec: es7210@40 { + #sound-dai-cells = <0>; + compatible = "MicArray_0"; + reg = <0x40>; + }; + + audio_aw87519_pa@58 { + compatible = "awinic,aw87519_pa"; + reg = <0x58>; + reset-gpio = <&ao_gpio4_porta 9 0x1>; + status = "okay"; + }; +}; + +&i2c1 { + clock-frequency = <100000>; + status = "okay"; +}; + +&spi0 { + num-cs = <1>; + cs-gpios = <&gpio2_porta 15 0>; // GPIO_ACTIVE_HIGH: 0 + rx-sample-delay-ns = <10>; + status = "disabled"; + + spi_norflash@0 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "winbond,w25q64jwm", "jedec,spi-nor"; + reg = <0>; + spi-max-frequency = <50000000>; + w25q,fast-read; + }; + + spidev@1 { + compatible = "spidev"; + #address-cells = <0x1>; + #size-cells = <0x1>; + reg = <0x1>; + spi-max-frequency = <50000000>; + }; +}; + +&uart0 { + clocks = <&dummy_clock_uart_sclk>; + clock-names = "baudclk"; + clock-frequency = <100000000>; +}; + +&qspi0 { + num-cs = <1>; + cs-gpios = <&gpio2_porta 3 0>; + rx-sample-dly = <4>; + status = "disabled"; + + spi-flash@0 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "spi-nand"; + spi-max-frequency = <100000000>; + spi-tx-bus-width = <4>; + spi-rx-bus-width = <4>; + reg = <0>; + + partition@0 { + label = "ubi1"; + reg = <0x00000000 0x08000000>; + }; + }; +}; + +&qspi1 { + compatible = "snps,dw-apb-ssi"; + num-cs = <1>; + cs-gpios = <&gpio0_porta 1 0>; + status = "disabled"; + + spidev@0 { + compatible = "spidev"; + #address-cells = <0x1>; + #size-cells = <0x1>; + reg = <0x0>; + spi-max-frequency = <50000000>; + }; +}; + +&gmac0 { + phy-mode = "rgmii-id"; + rx-clk-delay = <0x00>; /* for RGMII */ + tx-clk-delay = <0x00>; /* for RGMII */ + phy-handle = <&phy_88E1111_0>; + status = "okay"; + + mdio0 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "snps,dwmac-mdio"; + + phy_88E1111_0: ethernet-phy@0 { + reg = <0x1>; + }; + + phy_88E1111_1: ethernet-phy@1 { + reg = <0x2>; + }; + }; +}; + +&gmac1 { + phy-mode = "rgmii-id"; + rx-clk-delay = <0x00>; /* for RGMII */ + tx-clk-delay = <0x00>; /* for RGMII */ + phy-handle = <&phy_88E1111_1>; + status = "disabled"; +}; + +&emmc { + max-frequency = <198000000>; + non-removable; + mmc-hs400-1_8v; + io_fixed_1v8; + is_emmc; + no-sdio; + no-sd; + pull_up; + bus-width = <8>; + status = "okay"; +}; + +&sdhci0 { + max-frequency = <198000000>; + bus-width = <4>; + pull_up; + wprtn_ignore; + status = "okay"; +}; + +&sdhci1 { + max-frequency = <100000000>; + bus-width = <4>; + pull_up; + no-sd; + no-mmc; + non-removable; + io_fixed_1v8; + post-power-on-delay-ms = <50>; + wprtn_ignore; + cap-sd-highspeed; + keep-power-in-suspend; + wakeup-source; + status = "okay"; +}; + +&padctrl0_apsys { /* right-pinctrl */ + light-evb-padctrl0 { + /* + * Pin Configuration Node: + * Format: + */ + pinctrl_uart0: uart0grp { + thead,pins = < + FM_UART0_TXD 0x0 0x72 + FM_UART0_RXD 0x0 0x72 + >; + }; + + pinctrl_spi0: spi0grp { + thead,pins = < + FM_SPI_CSN 0x3 0x20a + FM_SPI_SCLK 0x0 0x20a + FM_SPI_MISO 0x0 0x23a + FM_SPI_MOSI 0x0 0x23a + >; + }; + + pinctrl_qspi0: qspi0grp { + thead,pins = < + FM_QSPI0_SCLK 0x0 0x20f + FM_QSPI0_CSN0 0x3 0x20f + FM_QSPI0_CSN1 0x0 0x20f + FM_QSPI0_D0_MOSI 0x0 0x23f + FM_QSPI0_D1_MISO 0x0 0x23f + FM_QSPI0_D2_WP 0x0 0x23f + FM_QSPI0_D3_HOLD 0x0 0x23f + >; + }; + + pinctrl_audio_i2s0: i2s0grp { + thead,pins = < + FM_QSPI0_SCLK 0x2 0x208 + FM_QSPI0_CSN0 0x2 0x238 + FM_QSPI0_CSN1 0x2 0x208 + FM_QSPI0_D0_MOSI 0x2 0x238 + FM_QSPI0_D1_MISO 0x2 0x238 + FM_QSPI0_D2_WP 0x2 0x238 + FM_QSPI0_D3_HOLD 0x2 0x238 + >; + }; + + pinctrl_pwm: pwmgrp { + thead,pins = < + FM_GPIO3_2 0x1 0x208 /* pwm0 */ + >; + }; + }; +}; + +&padctrl1_apsys { /* left-pinctrl */ + light-evb-padctrl1 { + /* + * Pin Configuration Node: + * Format: + */ + pinctrl_uart3: uart3grp { + thead,pins = < + FM_UART3_TXD 0x0 0x72 + FM_UART3_RXD 0x0 0x72 + >; + }; + + pinctrl_uart4: uart4grp { + thead,pins = < + FM_UART4_TXD 0x0 0x72 + FM_UART4_RXD 0x0 0x72 + FM_UART4_CTSN 0x0 0x72 + FM_UART4_RTSN 0x0 0x72 + >; + }; + + pinctrl_qspi1: qspi1grp { + thead,pins = < + FM_QSPI1_SCLK 0x0 0x20a + FM_QSPI1_CSN0 0x3 0x20a + FM_QSPI1_D0_MOSI 0x0 0x23a + FM_QSPI1_D1_MISO 0x0 0x23a + FM_QSPI1_D2_WP 0x0 0x23a + FM_QSPI1_D3_HOLD 0x0 0x23a + >; + }; + + + pinctrl_iso7816: iso7816grp { + thead,pins = < + FM_QSPI1_SCLK 0x1 0x208 + FM_QSPI1_D0_MOSI 0x1 0x238 + FM_QSPI1_D1_MISO 0x1 0x238 + FM_QSPI1_D2_WP 0x1 0x238 + FM_QSPI1_D3_HOLD 0x1 0x238 + >; + }; + + }; +}; + +&padctrl_aosys { + light-aon-padctrl { + /* + * Pin Configuration Node: + * Format: + */ + + pinctrl_audiopa1: audiopa1_grp { + thead,pins = < + FM_AUDIO_PA1 0x3 0x72 + >; + }; + + pinctrl_audiopa2: audiopa2_grp { + thead,pins = < + FM_AUDIO_PA2 0x0 0x72 + >; + }; + + pinctrl_volume: volume_grp { + thead,pins = < + FM_AOGPIO_11 0x0 0x208 + FM_AOGPIO_10 0x3 0x208 + >; + }; + }; +}; + +&i2c0 { + clock-frequency = <400000>; + status = "okay"; +}; + +&i2c1 { + clock-frequency = <400000>; + status = "okay"; +}; + +&i2c2 { + clock-frequency = <400000>; + status = "okay"; +}; + +&i2c3 { + clock-frequency = <400000>; + status = "okay"; +}; + +&i2c4 { + clock-frequency = <400000>; + status = "okay"; +}; + +&isp0 { + status = "disabled"; +}; + +&isp1 { + status = "disabled"; +}; + +&isp_ry0 { + status = "disabled"; +}; + +&dewarp { + status = "disabled"; +}; + +&dec400_isp0 { + status = "disabled"; +}; + +&dec400_isp1 { + status = "disabled"; +}; + +&dec400_isp2 { + status = "disabled"; +}; + +&bm_visys { + status = "disabled"; +}; + +&bm_csi0 { + status = "disabled"; +}; + +&bm_csi1 { + status = "disabled"; +}; + +&bm_csi2 { + status = "disabled"; +}; + +&vi_pre { + status = "disabled"; +}; + +&xtensa_dsp { + status = "disabled"; +}; + +&xtensa_dsp0 { + status = "disabled"; +}; + +&xtensa_dsp1 { + status = "disabled"; +}; + +&vvcam_flash_led0{ + status = "disabled"; +}; + + +&vvcam_sensor0 { + status = "disabled"; +}; + +&vvcam_sensor1 { + status = "disabled"; +}; + +&vvcam_sensor2 { + status = "disabled"; +}; + +&vvcam_sensor3 { + status = "disabled"; +}; + +&vvcam_sensor4 { + status = "disabled"; +}; + +&vvcam_sensor5 { + status = "disabled"; +}; + +&video0{ + status = "disabled"; +}; + + +&video1{ + status = "disabled"; +}; + +&video2{ + status = "disabled"; +}; + +&video3{ + status = "disabled"; +}; + +&video4{ + status = "disabled"; +}; + +&video5{ + status = "disabled"; +}; + +&video6{ + status = "disabled"; +}; + +&video7{ + status = "disabled"; +}; + + +&video8{ + status = "disabled"; +}; + +&video9{ + status = "disabled"; +}; + + +&video10{ + status = "disabled"; +}; + +&video11{ + status = "disabled"; +}; + +&video12{ + status = "disabled"; +}; + +&trng { + status = "disabled"; +}; + +&eip_28 { + status = "disabled"; +}; + +&vdec { + status = "disabled"; +}; + +&venc { + status = "disabled"; +}; + +&isp_venc_shake { + status = "disabled"; +}; + +&vidmem { + status = "disabled"; +}; + +&gpu { + status = "disabled"; +}; + +&npu { + status = "disabled"; +}; + +&fce { + status = "disabled"; +}; + +&dpu_enc0 { + status = "disabled"; +}; + +&dpu_enc1 { + status = "disabled"; +}; + +&dpu { + status = "disabled"; +}; + +&dsi0 { + status = "disabled"; +}; + +&dhost_0 { + status = "disabled"; +}; + +&disp1_out { + status = "disabled"; +}; + +&hdmi_tx { + status = "disabled"; +}; + +&lightsound { + status = "disabled"; +}; + +&light_i2s { + status = "okay"; +}; + +&i2s0 { + status = "okay"; +}; + +&i2s1 { + status = "okay"; +}; + +&i2s3 { + status = "okay"; +}; + +&khvhost { + status = "disabled"; +}; diff --git a/arch/riscv/boot/dts/thead/light-evb.dtsi b/arch/riscv/boot/dts/thead/light-evb.dtsi index b6f73b0d3..1d2d3323f 100644 --- a/arch/riscv/boot/dts/thead/light-evb.dtsi +++ b/arch/riscv/boot/dts/thead/light-evb.dtsi @@ -42,6 +42,7 @@ vivcam3= &vvcam_sensor3; vivcam4= &vvcam_sensor4; vivcam5= &vvcam_sensor5; + vivcam6= &vvcam_sensor6; }; memory@0 { @@ -1574,6 +1575,11 @@ compatible = "thead,light-vvcam-sensor"; status = "disabled"; }; + + vvcam_sensor6: vvcam_sensor@6 { + compatible = "thead,light-vvcam-sensor"; + status = "disabled"; + }; xtensa_dsp: dsp@01{ compatible = "thead,dsp-hw-common"; diff --git a/arch/riscv/boot/dts/thead/light-vi-devices.dtsi b/arch/riscv/boot/dts/thead/light-vi-devices.dtsi index fb6008627..15827de16 100644 --- a/arch/riscv/boot/dts/thead/light-vi-devices.dtsi +++ b/arch/riscv/boot/dts/thead/light-vi-devices.dtsi @@ -625,7 +625,7 @@ dma { subdev_name = "vipre"; idx = <0>; - path_type = "VIPRE_CSI2_DDR"; + path_type = "VIPRE_CSI2_DSP"; }; dsp { subdev_name = "dsp"; @@ -651,7 +651,7 @@ dma { subdev_name = "vipre"; idx = <0>; - path_type = "VIPRE_CSI2_DDR"; + path_type = "VIPRE_CSI2_DSP"; }; dsp { subdev_name = "dsp"; @@ -811,7 +811,7 @@ dma { subdev_name = "vipre"; idx = <0>; - path_type = "VIPRE_CSI1_DDR"; + path_type = "VIPRE_CSI1_DSP"; }; dsp { subdev_name = "dsp"; @@ -844,7 +844,7 @@ dma { subdev_name = "vipre"; idx = <0>; - path_type = "VIPRE_CSI2_DDR"; + path_type = "VIPRE_CSI2_DSP"; }; dsp { subdev_name = "dsp"; diff --git a/arch/riscv/boot/dts/thead/light.dtsi b/arch/riscv/boot/dts/thead/light.dtsi index 19d85846a..f8f1240bf 100644 --- a/arch/riscv/boot/dts/thead/light.dtsi +++ b/arch/riscv/boot/dts/thead/light.dtsi @@ -14,6 +14,7 @@ #include #include #include +#include / { compatible = "thead,light"; @@ -74,7 +75,7 @@ memory@0 { device_type = "memory"; - reg = <0x0 0x00000000 0x1 0x00000000>; + reg = <0x0 0x200000 0x0 0xffe00000>; }; resmem: reserved-memory { @@ -86,8 +87,8 @@ cmamem: linux,cma { compatible = "shared-dma-pool"; reusable; - size = <0 0x14000000>; - alloc-ranges = <0 0x20000000 0 0x40000000>; + size = <0 0x14000000>; // 320MB by default + alloc-ranges = <0 0x64000000 0 0x14000000>; // [0x6400_0000 ~ 0x7800_0000] linux,cma-default; }; }; @@ -975,9 +976,9 @@ status = "disabled"; }; - adc: adc@ffec020000 { + adc: adc@0xfffff51000 { compatible = "thead,light-adc"; - reg = <0xff 0xfff51000 0x0 0x2000>; + reg = <0xff 0xfff51000 0x0 0x1000>; interrupt-parent = <&intc>; interrupts = <61>; clocks = <&dummy_clock_aonsys_clk>; @@ -1171,8 +1172,9 @@ reg = <0xff 0xefc30000 0x0 0x1000>; interrupt-parent = <&intc>; interrupts = <24>; - clocks = <&dummy_clock_apb>; - clock-names = "baudclk"; + clocks = <&clk CLKGEN_WDT0_PCLK>; + clock-names = "tclk"; + resets = <&rst LIGHT_RESET_WDT0>; status = "okay"; }; @@ -1181,8 +1183,9 @@ reg = <0xff 0xefc31000 0x0 0x1000>; interrupt-parent = <&intc>; interrupts = <25>; - clocks = <&dummy_clock_apb>; - clock-names = "baudclk"; + clocks = <&clk CLKGEN_WDT1_PCLK>; + clock-names = "tclk"; + resets = <&rst LIGHT_RESET_WDT1>; status = "okay"; }; @@ -1237,6 +1240,13 @@ status = "okay"; }; + rst: reset-controller@ffef014000 { + compatible = "thead,light-reset-src","syscon"; + reg = <0xff 0xef014000 0x0 0x1000>; + #reset-cells = <1>; + status = "okay"; + }; + sys_reg: sys_reg@ffef010100 { compatible = "thead,light_sys_reg"; reg = <0xff 0xef010100 0x0 0x100>; @@ -1386,6 +1396,7 @@ interrupt-parent = <&intc>; interrupts = <113>; interrupt-names = "npuirq"; + power-domains = <&pd LIGHT_AON_NPU_PD>; clocks = <&clk CLKGEN_TOP_APB_SX_PCLK>, <&clk CLKGEN_TOP_AXI4S_ACLK>; clock-names = "pclk", "aclk"; @@ -1401,6 +1412,8 @@ interrupt-parent = <&intc>; interrupts = <102>; interrupt-names = "gpuirq"; + vosys-regmap = <&vosys_reg>; + power-domains = <&pd LIGHT_AON_GPU_PD>; clocks = <&vosys_clk_gate LIGHT_CLKGEN_GPU_CORE_CLK>, <&vosys_clk_gate LIGHT_CLKGEN_GPU_CFG_ACLK>; clock-names = "cclk", "aclk"; @@ -1427,6 +1440,7 @@ reg = <0xff 0xecc00000 0x0 0x8000>; interrupt-parent = <&intc>; interrupts = <131>; + power-domains = <&pd LIGHT_AON_VDEC_PD>; clocks = <&vpsys_clk_gate LIGHT_VPSYS_VDEC_ACLK>, <&vpsys_clk_gate LIGHT_VPSYS_VDEC_CCLK>, <&vpsys_clk_gate LIGHT_VPSYS_VDEC_PCLK>; @@ -1439,6 +1453,7 @@ reg = <0xff 0xecc10000 0x0 0x8000>; interrupt-parent = <&intc>; interrupts = <133>; + power-domains = <&pd LIGHT_AON_VENC_PD>; clocks = <&vpsys_clk_gate LIGHT_VPSYS_VENC_ACLK>, <&vpsys_clk_gate LIGHT_VPSYS_VENC_CCLK>, <&vpsys_clk_gate LIGHT_VPSYS_VENC_PCLK>; @@ -1562,8 +1577,8 @@ fs_lcnt = /bits/ 16 <0x42>; fp_hcnt = /bits/ 16 <0x14>; fp_lcnt = /bits/ 16 <0x1a>; - hs_hcnt = /bits/ 16 <0x5>; - hs_lcnt = /bits/ 16 <0x15>; + hs_hcnt = /bits/ 16 <0x9>; + hs_lcnt = /bits/ 16 <0x11>; #address-cells = <1>; #size-cells = <0>; }; @@ -1581,8 +1596,8 @@ fs_lcnt = /bits/ 16 <0x42>; fp_hcnt = /bits/ 16 <0x14>; fp_lcnt = /bits/ 16 <0x1a>; - hs_hcnt = /bits/ 16 <0x5>; - hs_lcnt = /bits/ 16 <0x15>; + hs_hcnt = /bits/ 16 <0x9>; + hs_lcnt = /bits/ 16 <0x11>; #address-cells = <1>; #size-cells = <0>; }; @@ -1600,8 +1615,8 @@ fs_lcnt = /bits/ 16 <0x42>; fp_hcnt = /bits/ 16 <0x14>; fp_lcnt = /bits/ 16 <0x1a>; - hs_hcnt = /bits/ 16 <0x5>; - hs_lcnt = /bits/ 16 <0x15>; + hs_hcnt = /bits/ 16 <0x9>; + hs_lcnt = /bits/ 16 <0x11>; status = "disabled"; #address-cells = <1>; @@ -1621,8 +1636,8 @@ fs_lcnt = /bits/ 16 <0x42>; fp_hcnt = /bits/ 16 <0x14>; fp_lcnt = /bits/ 16 <0x1a>; - hs_hcnt = /bits/ 16 <0x5>; - hs_lcnt = /bits/ 16 <0x15>; + hs_hcnt = /bits/ 16 <0x9>; + hs_lcnt = /bits/ 16 <0x11>; status = "disabled"; #address-cells = <1>; @@ -1642,8 +1657,8 @@ fs_lcnt = /bits/ 16 <0x42>; fp_hcnt = /bits/ 16 <0x14>; fp_lcnt = /bits/ 16 <0x1a>; - hs_hcnt = /bits/ 16 <0x5>; - hs_lcnt = /bits/ 16 <0x15>; + hs_hcnt = /bits/ 16 <0x9>; + hs_lcnt = /bits/ 16 <0x11>; status = "disabled"; #address-cells = <1>; @@ -1674,10 +1689,10 @@ reg = <0xff 0xe4100000 0x0 0x10000>; interrupt-parent = <&intc>; interrupts = <117>,<118>; - clocks = <&dummy_clock_visys>, - <&dummy_clock_visys>, - <&dummy_clock_visys>, - <&dummy_clock_visys>; + clocks = <&visys_clk_gate LIGHT_CLKGEN_ISP0_ACLK>, + <&visys_clk_gate LIGHT_CLKGEN_ISP0_HCLK>, + <&visys_clk_gate LIGHT_CLKGEN_ISP0_PIXELCLK>, + <&visys_clk_gate LIGHT_CLKGEN_ISP0_CLK>; clock-names = "aclk", "hclk", "isp0_pclk", "cclk"; status = "disabled"; }; @@ -1687,11 +1702,11 @@ reg = <0xff 0xe4110000 0x0 0x10000>; interrupt-parent = <&intc>; interrupts = <120>,<121>; - clocks = <&dummy_clock_visys>, - <&dummy_clock_visys>, - <&dummy_clock_visys>, - <&dummy_clock_visys>, - <&dummy_clock_visys>; + clocks = <&visys_clk_gate LIGHT_CLKGEN_ISP0_ACLK>, + <&visys_clk_gate LIGHT_CLKGEN_ISP0_HCLK>, + <&visys_clk_gate LIGHT_CLKGEN_ISP0_PIXELCLK>, + <&visys_clk_gate LIGHT_CLKGEN_ISP1_CLK>, + <&visys_clk_gate LIGHT_CLKGEN_ISP1_PIXELCLK>; clock-names = "aclk", "hclk", "isp0_pclk", "cclk", "isp1_pclk"; status = "disabled"; }; @@ -1701,9 +1716,9 @@ reg = <0xff 0xe4120000 0x0 0x10000>; interrupt-parent = <&intc>; interrupts = <123>,<124>; - clocks = <&dummy_clock_visys>, - <&dummy_clock_visys>, - <&dummy_clock_visys>; + clocks = <&visys_clk_gate LIGHT_CLKGEN_ISP_RY_ACLK>, + <&visys_clk_gate LIGHT_CLKGEN_ISP_RY_HCLK>, + <&visys_clk_gate LIGHT_CLKGEN_ISP_RY_CCLK>; clock-names = "aclk", "hclk", "cclk"; status = "disabled"; }; @@ -1713,10 +1728,10 @@ reg = <0xff 0xe4130000 0x0 0x10000>; interrupt-parent = <&intc>; interrupts = <98>,<99>; - clocks = <&dummy_clock_visys>, - <&dummy_clock_visys>, - <&dummy_clock_visys>, - <&dummy_clock_visys>; + clocks = <&visys_clk_gate LIGHT_CLKGEN_DW200_ACLK>, + <&visys_clk_gate LIGHT_CLKGEN_DW200_HCLK>, + <&visys_clk_gate LIGHT_CLKGEN_DW200_CLK_VSE>, + <&visys_clk_gate LIGHT_CLKGEN_DW200_CLK_DWE>; clock-names = "aclk", "hclk", "vseclk", "dweclk"; status = "disabled"; }; @@ -1752,14 +1767,22 @@ interrupts = <128>; dphyglueiftester = <0x180>; sysreg_mipi_csi_ctrl = <0x140>; - clocks = <&dummy_clock_visys>, - <&dummy_clock_visys>, - <&dummy_clock_visys>; - clock-names = "pclk", "pixclk", "cfg_clk"; - + clocks = <&visys_clk_gate LIGHT_CLKGEN_MIPI_CSI0_PCLK>, + <&visys_clk_gate LIGHT_CLKGEN_MIPI_CSI0_PIXCLK>, + <&visys_clk_gate LIGHT_CLKGEN_MIPI_CSI0_CFG_CLK>, + <&visys_clk_gate LIGHT_CLKGEN_MIPI_CSI1_CFG_CLK>, + <&visys_clk_gate LIGHT_CLKGEN_MIPI_CSI2_CFG_CLK>; + clock-names = "pclk", "pixclk", "cfg_clk0", "cfg_clk1", "cfg_clk2"; + phy_name = "CSI_4LANE"; status = "disabled"; }; + csia_reg: visys-reg@ffe4020000 { + compatible = "thead,light-visys-reg", "syscon"; + reg = < 0xff 0xe4020000 0x0 0x10000>; + status = "okay"; + }; + bm_csi1: csi@ffe4010000{ //CSI2X2_B compatible = "thead,light-bm-csi"; reg = < 0xff 0xe4010000 0x0 0x10000>; @@ -1767,11 +1790,15 @@ interrupts = <126>; // 110 + 16 int_mipi_csi2x2_int0 dphyglueiftester = <0x182>; // for FPGA PHY only. ASIC not needed. sysreg_mipi_csi_ctrl = <0x148>; - clocks = <&dummy_clock_visys>, - <&dummy_clock_visys>, - <&dummy_clock_visys>; - clock-names = "pclk", "pixclk", "cfg_clk"; - + visys-regmap = <&visys_reg>; + csia-regmap = <&csia_reg>; + clocks = <&visys_clk_gate LIGHT_CLKGEN_MIPI_CSI1_PCLK>, + <&visys_clk_gate LIGHT_CLKGEN_MIPI_CSI1_PIXCLK>, + <&visys_clk_gate LIGHT_CLKGEN_MIPI_CSI0_CFG_CLK>, + <&visys_clk_gate LIGHT_CLKGEN_MIPI_CSI1_CFG_CLK>, + <&visys_clk_gate LIGHT_CLKGEN_MIPI_CSI2_CFG_CLK>; + clock-names = "pclk", "pixclk", "cfg_clk0", "cfg_clk1", "cfg_clk2"; + phy_name = "CSI_B"; status = "disabled"; }; @@ -1782,11 +1809,13 @@ interrupts = <127>; dphyglueiftester = <0x184>; sysreg_mipi_csi_ctrl = <0x144>; - clocks = <&dummy_clock_visys>, - <&dummy_clock_visys>, - <&dummy_clock_visys>; - clock-names = "pclk", "pixclk", "cfg_clk"; - + clocks = <&visys_clk_gate LIGHT_CLKGEN_MIPI_CSI2_PCLK>, + <&visys_clk_gate LIGHT_CLKGEN_MIPI_CSI2_PIXCLK>, + <&visys_clk_gate LIGHT_CLKGEN_MIPI_CSI0_CFG_CLK>, + <&visys_clk_gate LIGHT_CLKGEN_MIPI_CSI1_CFG_CLK>, + <&visys_clk_gate LIGHT_CLKGEN_MIPI_CSI2_CFG_CLK>; + clock-names = "pclk", "pixclk", "cfg_clk0", "cfg_clk1", "cfg_clk2"; + phy_name = "CSI_A"; status = "disabled"; }; @@ -1815,6 +1844,10 @@ reg = <0xff 0xe4030000 0x0 0x1000>; interrupt-parent = <&intc>; interrupts = <134>; + clocks = <&visys_clk_gate LIGHT_CLKGEN_VIPRE_ACLK>, + <&visys_clk_gate LIGHT_CLKGEN_VIPRE_PCLK>, + <&visys_clk_gate LIGHT_CLKGEN_VIPRE_PIXELCLK>; + clock-names ="aclk", "pclk", "pixclk"; status = "disabled"; }; @@ -1960,8 +1993,8 @@ interrupt-parent = <&intc>; interrupts = <156>; firmware-name = "xrp0.elf"; - clocks = <&dummy_clock_visys>, - <&dummy_clock_visys>; + clocks = <&dummy_clock_visys>, + <&dummy_clock_visys>; clock-names = "pclk", "cclk"; status = "disabled"; @@ -1998,8 +2031,8 @@ interrupt-parent = <&intc>; interrupts = <157>; firmware-name = "xrp1.elf"; - clocks = <&dummy_clock_visys>, - <&dummy_clock_visys>; + clocks = <&dummy_clock_visys>, + <&dummy_clock_visys>; clock-names = "pclk", "cclk"; status = "disabled"; diff --git a/arch/riscv/configs/light-android_defconfig b/arch/riscv/configs/light-android_defconfig index 384d9526f..1be3bd643 100644 --- a/arch/riscv/configs/light-android_defconfig +++ b/arch/riscv/configs/light-android_defconfig @@ -1,34 +1,273 @@ -CONFIG_COMPILE_TEST=y -CONFIG_SYSVIPC=y -CONFIG_POSIX_MQUEUE=y +# see kernel/configs/android-5.10/android-base.config +# KEEP ALPHABETICALLY SORTED +# CONFIG_ANDROID_LOW_MEMORY_KILLER is not set +# CONFIG_ANDROID_PARANOID_NETWORK is not set +# CONFIG_BPFILTER is not set +# CONFIG_CRYPTO_MD4 is not set +# CONFIG_DEVMEM is not set +# CONFIG_FHANDLE is not set +# CONFIG_FW_CACHE is not set +# CONFIG_IP6_NF_NAT is not set +# CONFIG_MODULE_FORCE_UNLOAD is not set +# CONFIG_NFSD is not set +# CONFIG_NFS_FS is not set +# CONFIG_PM_AUTOSLEEP is not set +# CONFIG_RT_GROUP_SCHED is not set +# CONFIG_SYSVIPC is not set +# CONFIG_USELIB is not set +CONFIG_ADVISE_SYSCALLS=y +CONFIG_AIO=y +CONFIG_ANDROID=y +CONFIG_ANDROID_BINDER_DEVICES="binder,hwbinder,vndbinder" +CONFIG_ANDROID_BINDER_IPC=y +CONFIG_ANDROID_BINDERFS=y +CONFIG_ASHMEM=y CONFIG_AUDIT=y -CONFIG_NO_HZ=y +CONFIG_BINFMT_ELF=y +CONFIG_BINFMT_SCRIPT=y +CONFIG_BLK_DEV_INITRD=y +CONFIG_BLK_DEV_LOOP=y +CONFIG_BLOCK=y +CONFIG_BPF_JIT=y +CONFIG_BPF_SYSCALL=y +CONFIG_CGROUPS=y +CONFIG_CGROUP_BPF=y +CONFIG_CGROUP_CPUACCT=y +CONFIG_CGROUP_FREEZER=y +CONFIG_CGROUP_SCHED=y +CONFIG_CROSS_MEMORY_ATTACH=y +CONFIG_CRYPTO_AES=y +CONFIG_CRYPTO_CBC=y +CONFIG_CRYPTO_CHACHA20POLY1305=y +CONFIG_CRYPTO_CMAC=y +CONFIG_CRYPTO_CTR=y +CONFIG_CRYPTO_ECB=y +CONFIG_CRYPTO_GCM=y +CONFIG_CRYPTO_HMAC=y +CONFIG_CRYPTO_MD5=y +CONFIG_CRYPTO_NULL=y +CONFIG_CRYPTO_SHA1=y +CONFIG_CRYPTO_SHA256=y +CONFIG_CRYPTO_SHA512=y +CONFIG_CRYPTO_XCBC=y +CONFIG_DEBUG_LIST=y +CONFIG_DEFAULT_SECURITY_SELINUX=y +CONFIG_DM_SNAPSHOT=y +CONFIG_DM_VERITY=y +CONFIG_DUMMY=y +CONFIG_EMBEDDED=y +CONFIG_EPOLL=y +CONFIG_EVENTFD=y +CONFIG_FILE_LOCKING=y +CONFIG_FS_ENCRYPTION=y +CONFIG_FS_VERITY=y +CONFIG_FS_VERITY_BUILTIN_SIGNATURES=y +CONFIG_FUSE_FS=y +CONFIG_FUTEX=y +CONFIG_HARDENED_USERCOPY=y +CONFIG_HID_GENERIC=y +CONFIG_HID_PLAYSTATION=y +CONFIG_PLAYSTATION_FF=y +CONFIG_HID_SONY=y +CONFIG_SONY_FF=y CONFIG_HIGH_RES_TIMERS=y -CONFIG_PREEMPT=y -CONFIG_TASKSTATS=y -CONFIG_TASK_DELAY_ACCT=y -CONFIG_TASK_XACCT=y -CONFIG_TASK_IO_ACCOUNTING=y -CONFIG_PSI=y CONFIG_IKCONFIG=y CONFIG_IKCONFIG_PROC=y -CONFIG_UCLAMP_TASK=y -CONFIG_CGROUPS=y -CONFIG_CGROUP_SCHED=y -CONFIG_UCLAMP_TASK_GROUP=y -CONFIG_CGROUP_FREEZER=y -CONFIG_CGROUP_CPUACCT=y -CONFIG_CGROUP_BPF=y +CONFIG_INET6_ESP=y +CONFIG_INET6_IPCOMP=y +CONFIG_INET=y +CONFIG_INET_DIAG_DESTROY=y +CONFIG_INET_ESP=y +CONFIG_INET_UDP_DIAG=y +CONFIG_INOTIFY_USER=y +CONFIG_INPUT=y +CONFIG_INPUT_EVDEV=y +CONFIG_INPUT_JOYSTICK=y +CONFIG_IP6_NF_FILTER=y +CONFIG_IP6_NF_IPTABLES=y +CONFIG_IP6_NF_MANGLE=y +CONFIG_IP6_NF_MATCH_RPFILTER=y +CONFIG_IP6_NF_RAW=y +CONFIG_IP6_NF_TARGET_REJECT=y +CONFIG_IPV6=y +CONFIG_IPV6_MIP6=y +CONFIG_IPV6_MULTIPLE_TABLES=y +CONFIG_IPV6_OPTIMISTIC_DAD=y +CONFIG_IPV6_ROUTER_PREF=y +CONFIG_IPV6_ROUTE_INFO=y +CONFIG_IPV6_VTI=y +CONFIG_IP_ADVANCED_ROUTER=y +CONFIG_IP_MULTICAST=y +CONFIG_IP_MULTIPLE_TABLES=y +CONFIG_IP_NF_ARPFILTER=y +CONFIG_IP_NF_ARPTABLES=y +CONFIG_IP_NF_ARP_MANGLE=y +CONFIG_IP_NF_FILTER=y +CONFIG_IP_NF_IPTABLES=y +CONFIG_IP_NF_MANGLE=y +CONFIG_IP_NF_MATCH_ECN=y +CONFIG_IP_NF_MATCH_TTL=y +CONFIG_IP_NF_NAT=y +CONFIG_IP_NF_RAW=y +CONFIG_IP_NF_SECURITY=y +CONFIG_IP_NF_TARGET_MASQUERADE=y +CONFIG_IP_NF_TARGET_NETMAP=y +CONFIG_IP_NF_TARGET_REDIRECT=y +CONFIG_IP_NF_TARGET_REJECT=y +CONFIG_JOYSTICK_XPAD=y +CONFIG_L2TP=y +CONFIG_MAGIC_SYSRQ=y +CONFIG_MD=y +CONFIG_MEMBARRIER=y +CONFIG_MMU=y +CONFIG_MODULES=y +CONFIG_MODULE_UNLOAD=y +CONFIG_MODVERSIONS=y +CONFIG_MULTIUSER=y CONFIG_NAMESPACES=y +CONFIG_NET=y +CONFIG_NETDEVICES=y +CONFIG_NETFILTER=y +CONFIG_NETFILTER_XT_MATCH_BPF=y +CONFIG_NETFILTER_XT_MATCH_COMMENT=y +CONFIG_NETFILTER_XT_MATCH_CONNLIMIT=y +CONFIG_NETFILTER_XT_MATCH_CONNMARK=y +CONFIG_NETFILTER_XT_MATCH_CONNTRACK=y +CONFIG_NETFILTER_XT_MATCH_HASHLIMIT=y +CONFIG_NETFILTER_XT_MATCH_HELPER=y +CONFIG_NETFILTER_XT_MATCH_IPRANGE=y +CONFIG_NETFILTER_XT_MATCH_LENGTH=y +CONFIG_NETFILTER_XT_MATCH_LIMIT=y +CONFIG_NETFILTER_XT_MATCH_MAC=y +CONFIG_NETFILTER_XT_MATCH_MARK=y +CONFIG_NETFILTER_XT_MATCH_OWNER=y +CONFIG_NETFILTER_XT_MATCH_PKTTYPE=y +CONFIG_NETFILTER_XT_MATCH_POLICY=y +CONFIG_NETFILTER_XT_MATCH_QUOTA2=y +CONFIG_NETFILTER_XT_MATCH_QUOTA2_LOG=y +CONFIG_NETFILTER_XT_MATCH_QUOTA=y +CONFIG_NETFILTER_XT_MATCH_SOCKET=y +CONFIG_NETFILTER_XT_MATCH_STATE=y +CONFIG_NETFILTER_XT_MATCH_STATISTIC=y +CONFIG_NETFILTER_XT_MATCH_STRING=y +CONFIG_NETFILTER_XT_MATCH_TIME=y +CONFIG_NETFILTER_XT_MATCH_U32=y +CONFIG_NETFILTER_XT_TARGET_CLASSIFY=y +CONFIG_NETFILTER_XT_TARGET_CONNMARK=y +CONFIG_NETFILTER_XT_TARGET_CONNSECMARK=y +CONFIG_NETFILTER_XT_TARGET_CT=y +CONFIG_NETFILTER_XT_TARGET_IDLETIMER=y +CONFIG_NETFILTER_XT_TARGET_MARK=y +CONFIG_NETFILTER_XT_TARGET_NFLOG=y +CONFIG_NETFILTER_XT_TARGET_NFQUEUE=y +CONFIG_NETFILTER_XT_TARGET_SECMARK=y +CONFIG_NETFILTER_XT_TARGET_TCPMSS=y +CONFIG_NETFILTER_XT_TARGET_TPROXY=y +CONFIG_NETFILTER_XT_TARGET_TRACE=y +CONFIG_NET_CLS_ACT=y +CONFIG_NET_CLS_BPF=y +CONFIG_NET_CLS_U32=y +CONFIG_NET_EMATCH=y +CONFIG_NET_EMATCH_U32=y +CONFIG_NET_IPGRE_DEMUX=y +CONFIG_NET_IPVTI=y +CONFIG_NET_KEY=y +CONFIG_NET_NS=y +CONFIG_NET_SCHED=y +CONFIG_NET_SCH_HTB=y +CONFIG_NET_SCH_INGRESS=y +CONFIG_NF_CONNTRACK=y +CONFIG_NF_CONNTRACK_AMANDA=y +CONFIG_NF_CONNTRACK_EVENTS=y +CONFIG_NF_CONNTRACK_FTP=y +CONFIG_NF_CONNTRACK_H323=y +CONFIG_NF_CONNTRACK_IRC=y +CONFIG_NF_CONNTRACK_NETBIOS_NS=y +CONFIG_NF_CONNTRACK_PPTP=y +CONFIG_NF_CONNTRACK_SANE=y +CONFIG_NF_CONNTRACK_SECMARK=y +CONFIG_NF_CONNTRACK_TFTP=y +CONFIG_NF_CT_NETLINK=y +CONFIG_NF_CT_PROTO_DCCP=y +CONFIG_NF_CT_PROTO_SCTP=y +CONFIG_NF_CT_PROTO_UDPLITE=y +CONFIG_NF_NAT=y +CONFIG_NF_SOCKET_IPV4=y +CONFIG_NF_SOCKET_IPV6=y +CONFIG_NO_HZ=y +CONFIG_PACKET=y +CONFIG_PM_WAKELOCKS=y +CONFIG_POSIX_TIMERS=y +CONFIG_PPP=y +CONFIG_PPPOL2TP=y +CONFIG_PPP_BSDCOMP=y +CONFIG_PPP_DEFLATE=y +CONFIG_PPP_MPPE=y +CONFIG_PPTP=y +CONFIG_PREEMPT=y +CONFIG_PROC_FS=y +CONFIG_PROFILING=y +CONFIG_PSI=y +CONFIG_QFMT_V2=y +CONFIG_QUOTA=y +CONFIG_QUOTACTL=y +CONFIG_RD_LZ4=y +CONFIG_RTC_CLASS=y +CONFIG_SCHED_DEBUG=y +CONFIG_SECCOMP=y +CONFIG_SECCOMP_FILTER=y +CONFIG_SECURITY=y +CONFIG_SECURITY_NETWORK=y +CONFIG_SECURITY_SELINUX=y +CONFIG_SHMEM=y +CONFIG_SIGNALFD=y +CONFIG_SND=y +CONFIG_SOUND=y +CONFIG_STACKPROTECTOR=y +CONFIG_STACKPROTECTOR_STRONG=y +CONFIG_STAGING=y +CONFIG_STATIC_USERMODEHELPER=y +CONFIG_STRICT_KERNEL_RWX=y +CONFIG_STRICT_MODULE_RWX=y +CONFIG_SUSPEND=y +CONFIG_SYNC_FILE=y +CONFIG_SYSFS=y +CONFIG_TASKSTATS=y +CONFIG_TASK_IO_ACCOUNTING=y +CONFIG_TASK_XACCT=y +CONFIG_TIMERFD=y +CONFIG_TRACE_GPU_MEM=y +CONFIG_TTY=y +CONFIG_TUN=y +CONFIG_UHID=y +CONFIG_UID_SYS_STATS=y +CONFIG_UNIX=y +CONFIG_USB=y +CONFIG_USB_CONFIGFS=y +CONFIG_USB_CONFIGFS_F_ACC=y +CONFIG_USB_CONFIGFS_F_AUDIO_SRC=y +CONFIG_USB_CONFIGFS_F_FS=y +CONFIG_USB_CONFIGFS_F_MIDI=y +CONFIG_USB_CONFIGFS_UEVENT=y +CONFIG_USB_GADGET=y +CONFIG_USB_SUPPORT=y +CONFIG_UTS_NS=y +CONFIG_VETH=y +CONFIG_XFRM_INTERFACE=y +CONFIG_XFRM_MIGRATE=y +CONFIG_XFRM_STATISTICS=y +CONFIG_XFRM_USER=y +# kernel/configs/android-5.10/android-base.config + +CONFIG_COMPILE_TEST=y +CONFIG_POSIX_MQUEUE=y +CONFIG_TASK_DELAY_ACCT=y +CONFIG_UCLAMP_TASK=y +CONFIG_UCLAMP_TASK_GROUP=y CONFIG_USER_NS=y CONFIG_CHECKPOINT_RESTORE=y -CONFIG_BLK_DEV_INITRD=y -# CONFIG_FHANDLE is not set # CONFIG_BUG is not set CONFIG_KALLSYMS_ALL=y -CONFIG_BPF_SYSCALL=y -CONFIG_EMBEDDED=y -CONFIG_PROFILING=y CONFIG_SOC_SIFIVE=y CONFIG_SOC_THEAD=y CONFIG_SMP=y @@ -45,133 +284,26 @@ CONFIG_CPU_FREQ_GOV_CONSERVATIVE=y CONFIG_CPU_FREQ_GOV_SCHEDUTIL=y CONFIG_CPUFREQ_DT=y CONFIG_RISV_THEAD_LIGHT_CPUFREQ=y -CONFIG_PM_WAKELOCKS=y +CONFIG_PM_WAKELOCKS_LIMIT=0 +# CONFIG_PM_WAKELOCKS_GC is not set CONFIG_ENERGY_MODEL=y CONFIG_VIRTUALIZATION=y CONFIG_KVM=y -CONFIG_MODULES=y -CONFIG_MODULE_UNLOAD=y -CONFIG_MODVERSIONS=y CONFIG_BLK_INLINE_ENCRYPTION=y # CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS is not set CONFIG_CMA=y CONFIG_CMA_DEBUGFS=y CONFIG_CMA_AREAS=16 -CONFIG_NET=y -CONFIG_PACKET=y -CONFIG_UNIX=y -CONFIG_XFRM_USER=y -CONFIG_XFRM_INTERFACE=y -CONFIG_XFRM_MIGRATE=y -CONFIG_XFRM_STATISTICS=y -CONFIG_NET_KEY=y -CONFIG_INET=y -CONFIG_IP_MULTICAST=y -CONFIG_IP_ADVANCED_ROUTER=y -CONFIG_IP_MULTIPLE_TABLES=y CONFIG_IP_PNP=y CONFIG_IP_PNP_DHCP=y CONFIG_IP_PNP_BOOTP=y CONFIG_IP_PNP_RARP=y -CONFIG_NET_IPGRE_DEMUX=y -CONFIG_NET_IPVTI=y -CONFIG_INET_ESP=y -CONFIG_INET_UDP_DIAG=y -CONFIG_INET_DIAG_DESTROY=y -CONFIG_IPV6_ROUTER_PREF=y -CONFIG_IPV6_ROUTE_INFO=y -CONFIG_IPV6_OPTIMISTIC_DAD=y -CONFIG_INET6_ESP=y -CONFIG_INET6_IPCOMP=y -CONFIG_IPV6_MIP6=y -CONFIG_IPV6_VTI=y -CONFIG_IPV6_MULTIPLE_TABLES=y -CONFIG_NETFILTER=y -CONFIG_NF_CONNTRACK=y -CONFIG_NF_CONNTRACK_SECMARK=y -CONFIG_NF_CONNTRACK_EVENTS=y -CONFIG_NF_CONNTRACK_AMANDA=y -CONFIG_NF_CONNTRACK_FTP=y -CONFIG_NF_CONNTRACK_H323=y -CONFIG_NF_CONNTRACK_IRC=y -CONFIG_NF_CONNTRACK_NETBIOS_NS=y -CONFIG_NF_CONNTRACK_PPTP=y -CONFIG_NF_CONNTRACK_SANE=y -CONFIG_NF_CONNTRACK_TFTP=y -CONFIG_NF_CT_NETLINK=y -CONFIG_NETFILTER_XT_TARGET_CLASSIFY=y -CONFIG_NETFILTER_XT_TARGET_CONNMARK=y -CONFIG_NETFILTER_XT_TARGET_CONNSECMARK=y -CONFIG_NETFILTER_XT_TARGET_CT=y -CONFIG_NETFILTER_XT_TARGET_IDLETIMER=y -CONFIG_NETFILTER_XT_TARGET_MARK=y -CONFIG_NETFILTER_XT_TARGET_NFLOG=y -CONFIG_NETFILTER_XT_TARGET_NFQUEUE=y -CONFIG_NETFILTER_XT_TARGET_TPROXY=y -CONFIG_NETFILTER_XT_TARGET_TRACE=y -CONFIG_NETFILTER_XT_TARGET_SECMARK=y -CONFIG_NETFILTER_XT_TARGET_TCPMSS=y -CONFIG_NETFILTER_XT_MATCH_BPF=y -CONFIG_NETFILTER_XT_MATCH_COMMENT=y -CONFIG_NETFILTER_XT_MATCH_CONNLIMIT=y -CONFIG_NETFILTER_XT_MATCH_CONNMARK=y -CONFIG_NETFILTER_XT_MATCH_CONNTRACK=y -CONFIG_NETFILTER_XT_MATCH_HASHLIMIT=y -CONFIG_NETFILTER_XT_MATCH_HELPER=y -CONFIG_NETFILTER_XT_MATCH_IPRANGE=y -CONFIG_NETFILTER_XT_MATCH_LENGTH=y -CONFIG_NETFILTER_XT_MATCH_LIMIT=y -CONFIG_NETFILTER_XT_MATCH_MAC=y -CONFIG_NETFILTER_XT_MATCH_MARK=y -CONFIG_NETFILTER_XT_MATCH_OWNER=y -CONFIG_NETFILTER_XT_MATCH_POLICY=y -CONFIG_NETFILTER_XT_MATCH_PKTTYPE=y -CONFIG_NETFILTER_XT_MATCH_QUOTA=y -CONFIG_NETFILTER_XT_MATCH_QUOTA2=y -CONFIG_NETFILTER_XT_MATCH_QUOTA2_LOG=y -CONFIG_NETFILTER_XT_MATCH_SOCKET=y -CONFIG_NETFILTER_XT_MATCH_STATE=y -CONFIG_NETFILTER_XT_MATCH_STATISTIC=y -CONFIG_NETFILTER_XT_MATCH_STRING=y -CONFIG_NETFILTER_XT_MATCH_TIME=y -CONFIG_NETFILTER_XT_MATCH_U32=y -CONFIG_IP_NF_IPTABLES=y -CONFIG_IP_NF_MATCH_ECN=y -CONFIG_IP_NF_MATCH_TTL=y -CONFIG_IP_NF_FILTER=y -CONFIG_IP_NF_TARGET_REJECT=y -CONFIG_IP_NF_NAT=y -CONFIG_IP_NF_TARGET_MASQUERADE=y -CONFIG_IP_NF_TARGET_NETMAP=y -CONFIG_IP_NF_TARGET_REDIRECT=y -CONFIG_IP_NF_MANGLE=y -CONFIG_IP_NF_RAW=y -CONFIG_IP_NF_SECURITY=y -CONFIG_IP_NF_ARPTABLES=y -CONFIG_IP_NF_ARPFILTER=y -CONFIG_IP_NF_ARP_MANGLE=y -CONFIG_IP6_NF_IPTABLES=y -CONFIG_IP6_NF_MATCH_RPFILTER=y -CONFIG_IP6_NF_FILTER=y -CONFIG_IP6_NF_TARGET_REJECT=y -CONFIG_IP6_NF_MANGLE=y -CONFIG_IP6_NF_RAW=y -CONFIG_L2TP=y CONFIG_BRIDGE=y -CONFIG_NET_SCHED=y -CONFIG_NET_SCH_HTB=y CONFIG_NET_SCH_NETEM=y -CONFIG_NET_SCH_INGRESS=y -CONFIG_NET_CLS_U32=y -CONFIG_NET_CLS_BPF=y -CONFIG_NET_EMATCH=y -CONFIG_NET_EMATCH_U32=y -CONFIG_NET_CLS_ACT=y CONFIG_VSOCKETS=y # CONFIG_VSOCKETS_LOOPBACK is not set CONFIG_VIRTIO_VSOCKETS=y CONFIG_NETLINK_DIAG=y -CONFIG_BPF_JIT=y CONFIG_BT=y CONFIG_BT_RFCOMM=y CONFIG_BT_RFCOMM_TTY=y @@ -194,48 +326,30 @@ CONFIG_MTD_PHRAM=m CONFIG_MTD_SPI_NAND=y CONFIG_MTD_SPI_NOR=y CONFIG_MTD_UBI=y -CONFIG_BLK_DEV_LOOP=y CONFIG_BLK_DEV_RAM=y CONFIG_BLK_DEV_RAM_SIZE=8192 CONFIG_VIRTIO_BLK=y -CONFIG_UID_SYS_STATS=y CONFIG_LIGHT_DSMART_CARD=y CONFIG_EEPROM_AT24=y CONFIG_SCSI=y CONFIG_BLK_DEV_SD=y -CONFIG_MD=y CONFIG_BLK_DEV_DM=y CONFIG_DM_CRYPT=y CONFIG_DM_DEFAULT_KEY=y -CONFIG_DM_SNAPSHOT=y CONFIG_DM_UEVENT=y -CONFIG_DM_VERITY=y CONFIG_DM_VERITY_FEC=y CONFIG_DM_BOW=y -CONFIG_NETDEVICES=y -CONFIG_DUMMY=y -CONFIG_TUN=y -CONFIG_VETH=y CONFIG_VIRTIO_NET=y CONFIG_MACB=y CONFIG_STMMAC_ETH=y CONFIG_DWMAC_LIGHT=y CONFIG_MICROSEMI_PHY=y CONFIG_REALTEK_PHY=y -CONFIG_PPP=y -CONFIG_PPP_BSDCOMP=y -CONFIG_PPP_DEFLATE=y -CONFIG_PPP_MPPE=y -CONFIG_PPTP=y -CONFIG_PPPOL2TP=y CONFIG_USB_RTL8152=y CONFIG_USB_USBNET=m CONFIG_RTL8723DS=y CONFIG_INPUT_MOUSEDEV=m -CONFIG_INPUT_EVDEV=y CONFIG_KEYBOARD_GPIO=y -CONFIG_INPUT_JOYSTICK=y -CONFIG_JOYSTICK_XPAD=y CONFIG_JOYSTICK_XPAD_FF=y CONFIG_JOYSTICK_XPAD_LEDS=y CONFIG_INPUT_TABLET=y @@ -291,8 +405,6 @@ CONFIG_DRM_VERISILICON=y CONFIG_BACKLIGHT_CLASS_DEVICE=y CONFIG_BACKLIGHT_PWM=y CONFIG_LOGO=y -CONFIG_SOUND=y -CONFIG_SND=y CONFIG_SND_USB_AUDIO=m CONFIG_SND_SOC=y CONFIG_SND_SOC_THEAD_LIGHT=y @@ -301,7 +413,6 @@ CONFIG_SND_SOC_WM8960=y CONFIG_SND_SIMPLE_CARD=y CONFIG_SND_AUDIO_GRAPH_CARD=y CONFIG_HIDRAW=y -CONFIG_UHID=y CONFIG_HID_A4TECH=y CONFIG_HID_ACRUX=y CONFIG_HID_ACRUX_FF=y @@ -340,14 +451,10 @@ CONFIG_HID_PANTHERLORD=y CONFIG_PANTHERLORD_FF=y CONFIG_HID_PETALYNX=y CONFIG_HID_PICOLCD=y -CONFIG_HID_PLAYSTATION=y -CONFIG_PLAYSTATION_FF=y CONFIG_HID_PRIMAX=y CONFIG_HID_ROCCAT=y CONFIG_HID_SAITEK=y CONFIG_HID_SAMSUNG=y -CONFIG_HID_SONY=y -CONFIG_SONY_FF=y CONFIG_HID_SPEEDLINK=y CONFIG_HID_STEAM=y CONFIG_HID_SUNPLUS=y @@ -374,13 +481,6 @@ CONFIG_USB_STORAGE_SDDR09=y CONFIG_USB_STORAGE_SDDR55=y CONFIG_USB_DWC3=m # CONFIG_USB_DWC3_OF_SIMPLE is not set -CONFIG_USB_GADGET=y -CONFIG_USB_CONFIGFS=y -CONFIG_USB_CONFIGFS_UEVENT=y -CONFIG_USB_CONFIGFS_F_FS=y -CONFIG_USB_CONFIGFS_F_ACC=y -CONFIG_USB_CONFIGFS_F_AUDIO_SRC=y -CONFIG_USB_CONFIGFS_F_MIDI=y CONFIG_USB_ZERO=m CONFIG_USB_ETH=m CONFIG_USB_ETH_EEM=y @@ -394,7 +494,6 @@ CONFIG_MMC_SDHCI=y CONFIG_MMC_SDHCI_PLTFM=y CONFIG_MMC_SDHCI_OF_DWCMSHC=y CONFIG_LEDS_GPIO=y -CONFIG_RTC_CLASS=y CONFIG_RTC_DRV_XGENE=y CONFIG_DMADEVICES=y CONFIG_DW_AXI_DMAC=y @@ -410,8 +509,6 @@ CONFIG_DMABUF_HEAPS_SYSTEM=y # CONFIG_VIRTIO_MENU is not set CONFIG_VHOST_NET=y CONFIG_VHOST_VSOCK=y -CONFIG_STAGING=y -CONFIG_ASHMEM=y CONFIG_ION=y CONFIG_ION_SYSTEM_HEAP=y CONFIG_ION_CMA_HEAP=y @@ -424,8 +521,6 @@ CONFIG_IIO=y CONFIG_IIO_SW_DEVICE=y CONFIG_PWM=y CONFIG_PWM_LIGHT=y -CONFIG_ANDROID=y -CONFIG_ANDROID_BINDER_IPC=y CONFIG_NVMEM_THEAD_LIGHT_EFUSE=y CONFIG_LIGHT_GPU_VIV=m # CONFIG_LIGHT_NET is not set @@ -434,14 +529,8 @@ CONFIG_EXT4_FS_POSIX_ACL=y CONFIG_EXT4_FS_SECURITY=y CONFIG_F2FS_FS=y CONFIG_F2FS_FS_SECURITY=y -CONFIG_FS_ENCRYPTION=y CONFIG_FS_ENCRYPTION_INLINE_CRYPT=y -CONFIG_FS_VERITY=y -CONFIG_FS_VERITY_BUILTIN_SIGNATURES=y -CONFIG_QUOTA=y -CONFIG_QFMT_V2=y CONFIG_AUTOFS4_FS=y -CONFIG_FUSE_FS=y CONFIG_OVERLAY_FS=y CONFIG_MSDOS_FS=y CONFIG_VFAT_FS=y @@ -457,17 +546,9 @@ CONFIG_PSTORE_RAM=y CONFIG_9P_FS=y CONFIG_NLS_CODEPAGE_437=y CONFIG_NLS_ISO8859_1=y -CONFIG_SECURITY=y -CONFIG_SECURITY_NETWORK=y -CONFIG_HARDENED_USERCOPY=y -CONFIG_STATIC_USERMODEHELPER=y -CONFIG_SECURITY_SELINUX=y CONFIG_CRYPTO_DH=y CONFIG_CRYPTO_CURVE25519=y -CONFIG_CRYPTO_CHACHA20POLY1305=y CONFIG_CRYPTO_OFB=y -CONFIG_CRYPTO_XCBC=y -CONFIG_CRYPTO_MD5=y CONFIG_CRYPTO_SHA3=y CONFIG_CRYPTO_SM3=y CONFIG_CRYPTO_DES=y @@ -477,14 +558,13 @@ CONFIG_DMA_PERNUMA_CMA=y CONFIG_CMA_SIZE_MBYTES=32 CONFIG_PRINTK_TIME=y CONFIG_DYNAMIC_DEBUG=y -CONFIG_MAGIC_SYSRQ=y CONFIG_DEBUG_FS=y CONFIG_PANIC_TIMEOUT=5 CONFIG_DETECT_HUNG_TASK=y CONFIG_DEFAULT_HUNG_TASK_TIMEOUT=60 CONFIG_SCHEDSTATS=y CONFIG_DEBUG_ATOMIC_SLEEP=y -CONFIG_DEBUG_LIST=y # CONFIG_GCC_PLUGINS is not set # CONFIG_RCU_TRACE is not set CONFIG_ENABLE_DEFAULT_TRACERS=y +CONFIG_GKI_HACKS_TO_FIX=y diff --git a/arch/riscv/configs/light_defconfig b/arch/riscv/configs/light_defconfig index 9e0c37b37..f419fb4d7 100644 --- a/arch/riscv/configs/light_defconfig +++ b/arch/riscv/configs/light_defconfig @@ -143,7 +143,8 @@ CONFIG_LIGHT_PMIC_WATCHDOG=y CONFIG_WATCHDOG_PRETIMEOUT_GOV=y CONFIG_WATCHDOG_PRETIMEOUT_GOV_SEL=m CONFIG_WATCHDOG_PRETIMEOUT_GOV_PANIC=y -CONFIG_WATCHDOG_PRETIMEOUT_DEFAULT_GOV_PANIC=y +#CONFIG_WATCHDOG_PRETIMEOUT_DEFAULT_GOV_PANIC=y +CONFIG_WATCHDOG_PRETIMEOUT_DEFAULT_GOV_NOOP=y CONFIG_WATCHDOG_OPEN_TIMEOUT=32 CONFIG_ABX500_CORE=y CONFIG_REGULATOR=y @@ -315,3 +316,9 @@ CONFIG_DEFAULT_HUNG_TASK_TIMEOUT=60 CONFIG_DEBUG_ATOMIC_SLEEP=y # CONFIG_RCU_TRACE is not set CONFIG_OVERLAY_FS=y +CONFIG_LOCKUP_DETECTOR=y +CONFIG_SOFTLOCKUP_DETECTOR=y +CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC_VALUE=0 +CONFIG_PM=y +# CONFIG_SUSPEND is not set +# CONFIG_PM_SLEEP is not set diff --git a/arch/riscv/include/asm/atomic.h b/arch/riscv/include/asm/atomic.h index ac4f305d1..400a8c8b6 100644 --- a/arch/riscv/include/asm/atomic.h +++ b/arch/riscv/include/asm/atomic.h @@ -55,13 +55,11 @@ static __always_inline void atomic64_set(atomic64_t *v, s64 i) static __always_inline \ void atomic##prefix##_##op(c_type i, atomic##prefix##_t *v) \ { \ - smp_mb(); \ __asm__ __volatile__ ( \ " amo" #asm_op "." #asm_type " zero, %1, %0" \ : "+A" (v->counter) \ : "r" (I) \ : "memory"); \ - smp_mb(); \ } \ #ifdef CONFIG_GENERIC_ATOMIC64 @@ -93,26 +91,22 @@ c_type atomic##prefix##_fetch_##op##_relaxed(c_type i, \ atomic##prefix##_t *v) \ { \ register c_type ret; \ - smp_mb(); \ __asm__ __volatile__ ( \ " amo" #asm_op "." #asm_type " %1, %2, %0" \ : "+A" (v->counter), "=r" (ret) \ : "r" (I) \ : "memory"); \ - smp_mb(); \ return ret; \ } \ static __always_inline \ c_type atomic##prefix##_fetch_##op(c_type i, atomic##prefix##_t *v) \ { \ register c_type ret; \ - smp_mb(); \ __asm__ __volatile__ ( \ " amo" #asm_op "." #asm_type ".aqrl %1, %2, %0" \ : "+A" (v->counter), "=r" (ret) \ : "r" (I) \ : "memory"); \ - smp_mb(); \ return ret; \ } @@ -207,7 +201,6 @@ static __always_inline int atomic_fetch_add_unless(atomic_t *v, int a, int u) { int prev, rc; - smp_mb(); __asm__ __volatile__ ( "0: lr.w %[p], %[c]\n" " beq %[p], %[u], 1f\n" @@ -219,7 +212,6 @@ static __always_inline int atomic_fetch_add_unless(atomic_t *v, int a, int u) : [p]"=&r" (prev), [rc]"=&r" (rc), [c]"+A" (v->counter) : [a]"r" (a), [u]"r" (u) : "memory"); - smp_mb(); return prev; } #define atomic_fetch_add_unless atomic_fetch_add_unless @@ -230,7 +222,6 @@ static __always_inline s64 atomic64_fetch_add_unless(atomic64_t *v, s64 a, s64 u s64 prev; long rc; - smp_mb(); __asm__ __volatile__ ( "0: lr.d %[p], %[c]\n" " beq %[p], %[u], 1f\n" @@ -242,7 +233,6 @@ static __always_inline s64 atomic64_fetch_add_unless(atomic64_t *v, s64 a, s64 u : [p]"=&r" (prev), [rc]"=&r" (rc), [c]"+A" (v->counter) : [a]"r" (a), [u]"r" (u) : "memory"); - smp_mb(); return prev; } #define atomic64_fetch_add_unless atomic64_fetch_add_unless @@ -324,7 +314,6 @@ static __always_inline int atomic_sub_if_positive(atomic_t *v, int offset) { int prev, rc; - smp_mb(); __asm__ __volatile__ ( "0: lr.w %[p], %[c]\n" " sub %[rc], %[p], %[o]\n" @@ -336,7 +325,6 @@ static __always_inline int atomic_sub_if_positive(atomic_t *v, int offset) : [p]"=&r" (prev), [rc]"=&r" (rc), [c]"+A" (v->counter) : [o]"r" (offset) : "memory"); - smp_mb(); return prev - offset; } @@ -348,7 +336,6 @@ static __always_inline s64 atomic64_sub_if_positive(atomic64_t *v, s64 offset) s64 prev; long rc; - smp_mb(); __asm__ __volatile__ ( "0: lr.d %[p], %[c]\n" " sub %[rc], %[p], %[o]\n" @@ -360,7 +347,6 @@ static __always_inline s64 atomic64_sub_if_positive(atomic64_t *v, s64 offset) : [p]"=&r" (prev), [rc]"=&r" (rc), [c]"+A" (v->counter) : [o]"r" (offset) : "memory"); - smp_mb(); return prev - offset; } diff --git a/arch/riscv/include/asm/cmpxchg.h b/arch/riscv/include/asm/cmpxchg.h index 7f2b16cd1..262e5bbb2 100644 --- a/arch/riscv/include/asm/cmpxchg.h +++ b/arch/riscv/include/asm/cmpxchg.h @@ -16,7 +16,6 @@ __typeof__(ptr) __ptr = (ptr); \ __typeof__(new) __new = (new); \ __typeof__(*(ptr)) __ret; \ - smp_mb(); \ switch (size) { \ case 4: \ __asm__ __volatile__ ( \ @@ -35,7 +34,6 @@ default: \ BUILD_BUG(); \ } \ - smp_mb(); \ __ret; \ }) @@ -51,7 +49,6 @@ __typeof__(ptr) __ptr = (ptr); \ __typeof__(new) __new = (new); \ __typeof__(*(ptr)) __ret; \ - smp_mb(); \ switch (size) { \ case 4: \ __asm__ __volatile__ ( \ @@ -72,7 +69,6 @@ default: \ BUILD_BUG(); \ } \ - smp_mb(); \ __ret; \ }) @@ -88,7 +84,6 @@ __typeof__(ptr) __ptr = (ptr); \ __typeof__(new) __new = (new); \ __typeof__(*(ptr)) __ret; \ - smp_mb(); \ switch (size) { \ case 4: \ __asm__ __volatile__ ( \ @@ -109,7 +104,6 @@ default: \ BUILD_BUG(); \ } \ - smp_mb(); \ __ret; \ }) @@ -125,7 +119,6 @@ __typeof__(ptr) __ptr = (ptr); \ __typeof__(new) __new = (new); \ __typeof__(*(ptr)) __ret; \ - smp_mb(); \ switch (size) { \ case 4: \ __asm__ __volatile__ ( \ @@ -144,7 +137,6 @@ default: \ BUILD_BUG(); \ } \ - smp_mb(); \ __ret; \ }) @@ -178,7 +170,6 @@ __typeof__(*(ptr)) __new = (new); \ __typeof__(*(ptr)) __ret; \ register unsigned int __rc; \ - smp_mb(); \ switch (size) { \ case 4: \ __asm__ __volatile__ ( \ @@ -205,7 +196,6 @@ default: \ BUILD_BUG(); \ } \ - smp_mb(); \ __ret; \ }) @@ -224,7 +214,6 @@ __typeof__(*(ptr)) __new = (new); \ __typeof__(*(ptr)) __ret; \ register unsigned int __rc; \ - smp_mb(); \ switch (size) { \ case 4: \ __asm__ __volatile__ ( \ @@ -253,7 +242,6 @@ default: \ BUILD_BUG(); \ } \ - smp_mb(); \ __ret; \ }) @@ -272,7 +260,6 @@ __typeof__(*(ptr)) __new = (new); \ __typeof__(*(ptr)) __ret; \ register unsigned int __rc; \ - smp_mb(); \ switch (size) { \ case 4: \ __asm__ __volatile__ ( \ @@ -301,7 +288,6 @@ default: \ BUILD_BUG(); \ } \ - smp_mb(); \ __ret; \ }) @@ -320,7 +306,6 @@ __typeof__(*(ptr)) __new = (new); \ __typeof__(*(ptr)) __ret; \ register unsigned int __rc; \ - smp_mb(); \ switch (size) { \ case 4: \ __asm__ __volatile__ ( \ @@ -349,7 +334,6 @@ default: \ BUILD_BUG(); \ } \ - smp_mb(); \ __ret; \ }) diff --git a/arch/riscv/include/asm/smp.h b/arch/riscv/include/asm/smp.h index df1f7c4cd..74abc2bfe 100644 --- a/arch/riscv/include/asm/smp.h +++ b/arch/riscv/include/asm/smp.h @@ -51,6 +51,9 @@ void riscv_set_ipi_ops(struct riscv_ipi_ops *ops); /* Clear IPI for current CPU */ void riscv_clear_ipi(void); +void crash_smp_send_stop(void); +bool smp_crash_stop_failed(void); + /* Secondary hart entry */ asmlinkage void smp_callin(void); diff --git a/arch/riscv/include/asm/tlbflush.h b/arch/riscv/include/asm/tlbflush.h index d76ef8cd4..ed4ae9bec 100644 --- a/arch/riscv/include/asm/tlbflush.h +++ b/arch/riscv/include/asm/tlbflush.h @@ -65,6 +65,11 @@ static inline void flush_tlb_kernel_range(unsigned long start, end += PAGE_SIZE - 1; end &= PAGE_MASK; + if ((end - start) > SZ_1M) { + flush_tlb_all(); + return; + } + while (start < end) { __asm__ __volatile__ ("sfence.vma %0" : : "r" (start) : "memory"); start += PAGE_SIZE; diff --git a/arch/riscv/include/uapi/asm/ptrace.h b/arch/riscv/include/uapi/asm/ptrace.h index 857a93910..0390a8ba3 100644 --- a/arch/riscv/include/uapi/asm/ptrace.h +++ b/arch/riscv/include/uapi/asm/ptrace.h @@ -77,8 +77,18 @@ union __riscv_fp_state { struct __riscv_q_ext_state q; }; +#ifdef CONFIG_VLEN_256 +struct __riscv_vblen { + __uint128_t v[2]; +}; +#endif + struct __riscv_v_state { +#ifdef CONFIG_VLEN_256 + struct __riscv_vblen v[32]; +#else __uint128_t v[32]; +#endif unsigned long vstart; unsigned long vxsat; unsigned long vxrm; diff --git a/arch/riscv/kernel/asm-offsets.c b/arch/riscv/kernel/asm-offsets.c index 6069af41c..431afa56c 100644 --- a/arch/riscv/kernel/asm-offsets.c +++ b/arch/riscv/kernel/asm-offsets.c @@ -104,7 +104,11 @@ void asm_offsets(void) OFFSET(TASK_THREAD_VXRM, task_struct, thread.vstate.vxrm); OFFSET(TASK_THREAD_VL, task_struct, thread.vstate.vl); OFFSET(TASK_THREAD_VTYPE, task_struct, thread.vstate.vtype); +#ifdef CONFIG_VLEN_256 + DEFINE(RISCV_VECTOR_VLENB, sizeof(struct __riscv_vblen)); +#else DEFINE(RISCV_VECTOR_VLENB, sizeof(__uint128_t)); +#endif DEFINE(PT_SIZE, sizeof(struct pt_regs)); OFFSET(PT_EPC, pt_regs, epc); diff --git a/arch/riscv/kernel/machine_kexec.c b/arch/riscv/kernel/machine_kexec.c index b5dfd99a7..3d3725ded 100644 --- a/arch/riscv/kernel/machine_kexec.c +++ b/arch/riscv/kernel/machine_kexec.c @@ -14,6 +14,8 @@ #include /* For set_memory_x() */ #include /* For unreachable() */ #include /* For cpu_down() */ +#include +#include /** * kexec_image_info - Print received image details @@ -135,19 +137,54 @@ void machine_shutdown(void) #endif } -/** +static void machine_kexec_mask_interrupts(void) +{ + unsigned int i; + struct irq_desc *desc; + + for_each_irq_desc(i, desc) { + struct irq_chip *chip; + int ret; + + chip = irq_desc_get_chip(desc); + if (!chip) + continue; + + /* + * First try to remove the active state. If this + * fails, try to EOI the interrupt. + */ + ret = irq_set_irqchip_state(i, IRQCHIP_STATE_ACTIVE, false); + + if (ret && irqd_irq_inprogress(&desc->irq_data) && + chip->irq_eoi) + chip->irq_eoi(&desc->irq_data); + + if (chip->irq_mask) + chip->irq_mask(&desc->irq_data); + + if (chip->irq_disable && !irqd_irq_disabled(&desc->irq_data)) + chip->irq_disable(&desc->irq_data); + } +} + +/* * machine_crash_shutdown - Prepare to kexec after a kernel crash * * This function is called by crash_kexec just before machine_kexec - * below and its goal is similar to machine_shutdown, but in case of - * a kernel crash. Since we don't handle such cases yet, this function - * is empty. + * and its goal is to shutdown non-crashing cpus and save registers. */ void machine_crash_shutdown(struct pt_regs *regs) { + local_irq_disable(); + + /* shutdown non-crashing cpus */ + crash_smp_send_stop(); + crash_save_cpu(regs, smp_processor_id()); - machine_shutdown(); + machine_kexec_mask_interrupts(); + pr_info("Starting crashdump kernel...\n"); } @@ -168,12 +205,15 @@ machine_kexec(struct kimage *image) struct kimage_arch *internal = &image->arch; unsigned long jump_addr = (unsigned long) image->start; unsigned long first_ind_entry = (unsigned long) &image->head; - unsigned long this_cpu_id = smp_processor_id(); + unsigned long this_cpu_id = __smp_processor_id(); unsigned long this_hart_id = cpuid_to_hartid_map(this_cpu_id); unsigned long fdt_addr = internal->fdt_addr; void *control_code_buffer = page_address(image->control_code_page); riscv_kexec_method kexec_method = NULL; + WARN(smp_crash_stop_failed(), + "Some CPUs may be stale, kdump will be unreliable.\n"); + if (image->type != KEXEC_TYPE_CRASH) kexec_method = control_code_buffer; else diff --git a/arch/riscv/kernel/smp.c b/arch/riscv/kernel/smp.c index d44567490..b1255f5cb 100644 --- a/arch/riscv/kernel/smp.c +++ b/arch/riscv/kernel/smp.c @@ -11,6 +11,7 @@ #include #include #include +#include #include #include #include @@ -26,6 +27,7 @@ enum ipi_message_type { IPI_RESCHEDULE, IPI_CALL_FUNC, IPI_CPU_STOP, + IPI_CPU_CRASH_STOP, IPI_IRQ_WORK, IPI_MAX }; @@ -85,6 +87,22 @@ static void ipi_stop(void) wait_for_interrupt(); } +#ifdef CONFIG_KEXEC_CORE +static atomic_t waiting_for_crash_ipi = ATOMIC_INIT(0); + +static void ipi_cpu_crash_stop(unsigned int cpu, struct pt_regs *regs) +{ + crash_save_cpu(regs, cpu); + + atomic_dec(&waiting_for_crash_ipi); + + local_irq_disable(); + + while(1) + wait_for_interrupt(); +} +#endif + static struct riscv_ipi_ops *ipi_ops; void riscv_set_ipi_ops(struct riscv_ipi_ops *ops) @@ -138,6 +156,7 @@ void arch_irq_work_raise(void) void handle_IPI(struct pt_regs *regs) { + unsigned int cpu = smp_processor_id(); struct pt_regs *old_regs = set_irq_regs(regs); unsigned long *pending_ipis = &ipi_data[smp_processor_id()].bits; unsigned long *stats = ipi_data[smp_processor_id()].stats; @@ -171,6 +190,13 @@ void handle_IPI(struct pt_regs *regs) ipi_stop(); } + if (ops & (1 << IPI_CPU_CRASH_STOP)) { +#ifdef CONFIG_KEXEC_CORE + ipi_cpu_crash_stop(cpu, get_irq_regs()); +#endif + unreachable(); + } + if (ops & (1 << IPI_IRQ_WORK)) { stats[IPI_IRQ_WORK]++; irq_work_run(); @@ -191,6 +217,7 @@ static const char * const ipi_names[] = { [IPI_RESCHEDULE] = "Rescheduling interrupts", [IPI_CALL_FUNC] = "Function call interrupts", [IPI_CPU_STOP] = "CPU stop interrupts", + [IPI_CPU_CRASH_STOP] = "CPU stop (for crash dump) interrupts", [IPI_IRQ_WORK] = "IRQ work interrupts", }; @@ -242,6 +269,64 @@ void smp_send_stop(void) cpumask_pr_args(cpu_online_mask)); } +#ifdef CONFIG_KEXEC_CORE +/* + * The number of CPUs online, not counting this CPU (which may not be + * fully online and so not counted in num_online_cpus()). + */ +static inline unsigned int num_other_online_cpus(void) +{ + unsigned int this_cpu_online = cpu_online(smp_processor_id()); + + return num_online_cpus() - this_cpu_online; +} + +void crash_smp_send_stop(void) +{ + static int cpus_stopped; + cpumask_t mask; + unsigned long timeout; + + /* + * This function can be called twice in panic path, but obviously + * we execute this only once. + */ + if (cpus_stopped) + return; + + cpus_stopped = 1; + + /* + * If this cpu is the only one alive at this point in time, online or + * not, there are no stop messages to be sent around, so just back out. + */ + if (num_other_online_cpus() == 0) + return; + + cpumask_copy(&mask, cpu_online_mask); + cpumask_clear_cpu(smp_processor_id(), &mask); + + atomic_set(&waiting_for_crash_ipi, num_other_online_cpus()); + + pr_crit("SMP: stopping secondary CPUs\n"); + send_ipi_mask(&mask, IPI_CPU_CRASH_STOP); + + /* Wait up to ten seconds for other CPUs to stop */ + timeout = USEC_PER_SEC * 10; + while ((atomic_read(&waiting_for_crash_ipi) > 0) && timeout--) + udelay(1); + + if (atomic_read(&waiting_for_crash_ipi) > 0) + pr_warn("SMP: failed to stop secondary CPUs %*pbl\n", + cpumask_pr_args(&mask)); +} + +bool smp_crash_stop_failed(void) +{ + return (atomic_read(&waiting_for_crash_ipi) > 0); +} +#endif + void smp_send_reschedule(int cpu) { send_ipi_single(cpu, IPI_RESCHEDULE); diff --git a/arch/riscv/kernel/vector.S b/arch/riscv/kernel/vector.S index ccb0deb4a..88221a1a4 100644 --- a/arch/riscv/kernel/vector.S +++ b/arch/riscv/kernel/vector.S @@ -46,6 +46,72 @@ ENTRY(__vstate_save) csrr t0, CSR_VTYPE sd t0, TASK_THREAD_VTYPE_V0(a0) +#ifdef CONFIG_VLEN_256 + vsetvli t0, x0, e8,m1 + V_ST v0, (a0) + addi a0, a0, RISCV_VECTOR_VLENB + V_ST v1, (a0) + addi a0, a0, RISCV_VECTOR_VLENB + V_ST v2, (a0) + addi a0, a0, RISCV_VECTOR_VLENB + V_ST v3, (a0) + addi a0, a0, RISCV_VECTOR_VLENB + V_ST v4, (a0) + addi a0, a0, RISCV_VECTOR_VLENB + V_ST v5, (a0) + addi a0, a0, RISCV_VECTOR_VLENB + V_ST v6, (a0) + addi a0, a0, RISCV_VECTOR_VLENB + V_ST v7, (a0) + addi a0, a0, RISCV_VECTOR_VLENB + V_ST v8, (a0) + addi a0, a0, RISCV_VECTOR_VLENB + V_ST v9, (a0) + addi a0, a0, RISCV_VECTOR_VLENB + V_ST v10, (a0) + addi a0, a0, RISCV_VECTOR_VLENB + V_ST v11, (a0) + addi a0, a0, RISCV_VECTOR_VLENB + V_ST v12, (a0) + addi a0, a0, RISCV_VECTOR_VLENB + V_ST v13, (a0) + addi a0, a0, RISCV_VECTOR_VLENB + V_ST v14, (a0) + addi a0, a0, RISCV_VECTOR_VLENB + V_ST v15, (a0) + addi a0, a0, RISCV_VECTOR_VLENB + V_ST v16, (a0) + addi a0, a0, RISCV_VECTOR_VLENB + V_ST v17, (a0) + addi a0, a0, RISCV_VECTOR_VLENB + V_ST v18, (a0) + addi a0, a0, RISCV_VECTOR_VLENB + V_ST v19, (a0) + addi a0, a0, RISCV_VECTOR_VLENB + V_ST v20, (a0) + addi a0, a0, RISCV_VECTOR_VLENB + V_ST v21, (a0) + addi a0, a0, RISCV_VECTOR_VLENB + V_ST v22, (a0) + addi a0, a0, RISCV_VECTOR_VLENB + V_ST v23, (a0) + addi a0, a0, RISCV_VECTOR_VLENB + V_ST v24, (a0) + addi a0, a0, RISCV_VECTOR_VLENB + V_ST v25, (a0) + addi a0, a0, RISCV_VECTOR_VLENB + V_ST v26, (a0) + addi a0, a0, RISCV_VECTOR_VLENB + V_ST v27, (a0) + addi a0, a0, RISCV_VECTOR_VLENB + V_ST v28, (a0) + addi a0, a0, RISCV_VECTOR_VLENB + V_ST v29, (a0) + addi a0, a0, RISCV_VECTOR_VLENB + V_ST v30, (a0) + addi a0, a0, RISCV_VECTOR_VLENB + V_ST v31, (a0) +#else vsetvli t0, x0, e8,m8 V_ST v0, (a0) addi a0, a0, RISCV_VECTOR_VLENB*8 @@ -54,6 +120,7 @@ ENTRY(__vstate_save) V_ST v16, (a0) addi a0, a0, RISCV_VECTOR_VLENB*8 V_ST v24, (a0) +#endif csrc sstatus, t1 ret @@ -67,6 +134,72 @@ ENTRY(__vstate_restore) li t1, (SR_VS | SR_FS) csrs sstatus, t1 +#ifdef CONFIG_VLEN_256 + vsetvli t0, x0, e8,m1 + V_LD v0, (a0) + addi a0, a0, RISCV_VECTOR_VLENB + V_LD v1, (a0) + addi a0, a0, RISCV_VECTOR_VLENB + V_LD v2, (a0) + addi a0, a0, RISCV_VECTOR_VLENB + V_LD v3, (a0) + addi a0, a0, RISCV_VECTOR_VLENB + V_LD v4, (a0) + addi a0, a0, RISCV_VECTOR_VLENB + V_LD v5, (a0) + addi a0, a0, RISCV_VECTOR_VLENB + V_LD v6, (a0) + addi a0, a0, RISCV_VECTOR_VLENB + V_LD v7, (a0) + addi a0, a0, RISCV_VECTOR_VLENB + V_LD v8, (a0) + addi a0, a0, RISCV_VECTOR_VLENB + V_LD v9, (a0) + addi a0, a0, RISCV_VECTOR_VLENB + V_LD v10, (a0) + addi a0, a0, RISCV_VECTOR_VLENB + V_LD v11, (a0) + addi a0, a0, RISCV_VECTOR_VLENB + V_LD v12, (a0) + addi a0, a0, RISCV_VECTOR_VLENB + V_LD v13, (a0) + addi a0, a0, RISCV_VECTOR_VLENB + V_LD v14, (a0) + addi a0, a0, RISCV_VECTOR_VLENB + V_LD v15, (a0) + addi a0, a0, RISCV_VECTOR_VLENB + V_LD v16, (a0) + addi a0, a0, RISCV_VECTOR_VLENB + V_LD v17, (a0) + addi a0, a0, RISCV_VECTOR_VLENB + V_LD v18, (a0) + addi a0, a0, RISCV_VECTOR_VLENB + V_LD v19, (a0) + addi a0, a0, RISCV_VECTOR_VLENB + V_LD v20, (a0) + addi a0, a0, RISCV_VECTOR_VLENB + V_LD v21, (a0) + addi a0, a0, RISCV_VECTOR_VLENB + V_LD v22, (a0) + addi a0, a0, RISCV_VECTOR_VLENB + V_LD v23, (a0) + addi a0, a0, RISCV_VECTOR_VLENB + V_LD v24, (a0) + addi a0, a0, RISCV_VECTOR_VLENB + V_LD v25, (a0) + addi a0, a0, RISCV_VECTOR_VLENB + V_LD v26, (a0) + addi a0, a0, RISCV_VECTOR_VLENB + V_LD v27, (a0) + addi a0, a0, RISCV_VECTOR_VLENB + V_LD v28, (a0) + addi a0, a0, RISCV_VECTOR_VLENB + V_LD v29, (a0) + addi a0, a0, RISCV_VECTOR_VLENB + V_LD v30, (a0) + addi a0, a0, RISCV_VECTOR_VLENB + V_LD v31, (a0) +#else vsetvli t0, x0, e8,m8 V_LD v0, (a0) addi a0, a0, RISCV_VECTOR_VLENB*8 @@ -75,6 +208,7 @@ ENTRY(__vstate_restore) V_LD v16, (a0) addi a0, a0, RISCV_VECTOR_VLENB*8 V_LD v24, (a0) +#endif mv a0, t2 ld t0, TASK_THREAD_VSTART_V0(a0) diff --git a/arch/riscv/mm/cacheflush.c b/arch/riscv/mm/cacheflush.c index 2045468b6..508aa5cb3 100644 --- a/arch/riscv/mm/cacheflush.c +++ b/arch/riscv/mm/cacheflush.c @@ -91,7 +91,7 @@ void flush_icache_pte(pte_t pte) static bool thead_dma_init_flag = false; -#define sync_is() asm volatile (".long 0x01b0000b") +#define sync_is() asm volatile (".long 0x01a0000b") void dma_wbinv_range(unsigned long start, unsigned long end) { register unsigned long i asm("a0") = start & ~(L1_CACHE_BYTES - 1); diff --git a/drivers/clk/thead/clk-light-fm.c b/drivers/clk/thead/clk-light-fm.c index b75a17839..2d38fc1e4 100644 --- a/drivers/clk/thead/clk-light-fm.c +++ b/drivers/clk/thead/clk-light-fm.c @@ -5,6 +5,7 @@ #include #include +#include #include #include #include @@ -607,6 +608,8 @@ static int light_clocks_probe(struct platform_device *pdev) #ifndef FPGA_EMU /* HW defalut */ + clk_prepare_enable(clks[CPU_PLL1_FOUTPOSTDIV]); + udelay(1); clk_set_parent(clks[C910_CCLK], clks[CPU_PLL1_FOUTPOSTDIV]); #else clk_set_parent(clks[C910_CCLK_I0], clks[OSC_24M]); @@ -640,6 +643,6 @@ static struct platform_driver light_clk_driver = { }; module_platform_driver(light_clk_driver); -MODULE_AUTHOR("wei.liu "); +MODULE_AUTHOR("wei.liu "); MODULE_DESCRIPTION("Thead Light Fullmask clock driver"); MODULE_LICENSE("GPL v2"); diff --git a/drivers/clk/thead/clk-light-mpw.c b/drivers/clk/thead/clk-light-mpw.c index 0c3ed447a..f7356ddf4 100644 --- a/drivers/clk/thead/clk-light-mpw.c +++ b/drivers/clk/thead/clk-light-mpw.c @@ -487,6 +487,6 @@ static struct platform_driver light_clk_driver = { }; module_platform_driver(light_clk_driver); -MODULE_AUTHOR("fugang.duan "); +MODULE_AUTHOR("fugang.duan "); MODULE_DESCRIPTION("Thead Light MPW clock driver"); MODULE_LICENSE("GPL v2"); diff --git a/drivers/clk/thead/gate/dspsys-gate.c b/drivers/clk/thead/gate/dspsys-gate.c index 0be962fc8..e68a5d4e6 100644 --- a/drivers/clk/thead/gate/dspsys-gate.c +++ b/drivers/clk/thead/gate/dspsys-gate.c @@ -104,6 +104,6 @@ static struct platform_driver light_dspsys_clk_driver = { }; module_platform_driver(light_dspsys_clk_driver); -MODULE_AUTHOR("wei.liu "); +MODULE_AUTHOR("wei.liu "); MODULE_DESCRIPTION("Thead Light Fullmask dspsys clock gate provider"); MODULE_LICENSE("GPL v2"); diff --git a/drivers/clk/thead/gate/visys-gate.c b/drivers/clk/thead/gate/visys-gate.c index 3d68fb316..96a177561 100644 --- a/drivers/clk/thead/gate/visys-gate.c +++ b/drivers/clk/thead/gate/visys-gate.c @@ -139,6 +139,6 @@ static struct platform_driver light_visys_clk_driver = { }; module_platform_driver(light_visys_clk_driver); -MODULE_AUTHOR("wei.liu "); +MODULE_AUTHOR("wei.liu "); MODULE_DESCRIPTION("Thead Light Fullmask visys clock gate provider"); MODULE_LICENSE("GPL v2"); diff --git a/drivers/clk/thead/gate/vosys-gate.c b/drivers/clk/thead/gate/vosys-gate.c index 0ac1bb334..e53ba1a3e 100644 --- a/drivers/clk/thead/gate/vosys-gate.c +++ b/drivers/clk/thead/gate/vosys-gate.c @@ -106,6 +106,6 @@ static struct platform_driver light_vosys_clk_driver = { }; module_platform_driver(light_vosys_clk_driver); -MODULE_AUTHOR("wei.liu "); +MODULE_AUTHOR("wei.liu "); MODULE_DESCRIPTION("Thead Light Fullmask vosys clock gate provider"); MODULE_LICENSE("GPL v2"); diff --git a/drivers/clk/thead/gate/vpsys-gate.c b/drivers/clk/thead/gate/vpsys-gate.c index bf5cca5af..78613188d 100644 --- a/drivers/clk/thead/gate/vpsys-gate.c +++ b/drivers/clk/thead/gate/vpsys-gate.c @@ -89,6 +89,6 @@ static struct platform_driver light_vpsys_clk_driver = { }; module_platform_driver(light_vpsys_clk_driver); -MODULE_AUTHOR("wei.liu "); +MODULE_AUTHOR("wei.liu "); MODULE_DESCRIPTION("Thead Light Fullmask vpsys clock gate provider"); MODULE_LICENSE("GPL v2"); diff --git a/drivers/cpufreq/light-mpw-cpufreq.c b/drivers/cpufreq/light-mpw-cpufreq.c index b6da5ba7b..e6a6ad5e2 100644 --- a/drivers/cpufreq/light-mpw-cpufreq.c +++ b/drivers/cpufreq/light-mpw-cpufreq.c @@ -13,9 +13,15 @@ #include #include #include +#include #include #include #include +#include + +static DEFINE_MUTEX(cpufreq_lock); + +bool cpufreq_denied = false; struct regulator *dvdd_cpu_reg; struct regulator *dvddm_cpu_reg; @@ -62,6 +68,13 @@ static int light_set_target(struct cpufreq_policy *policy, unsigned int index) u32 val; u32 re_modify_bus_freq = 0; + mutex_lock(&cpufreq_lock); + + if (cpufreq_denied) { + dev_emerg(cpu_dev, "Denied to set cpu frequency temporarily on reboot\n"); + mutex_unlock(&cpufreq_lock); + return 0; + } new_freq = freq_table[index].frequency; freq_hz = new_freq * 1000; old_freq = policy->cur; @@ -69,6 +82,7 @@ static int light_set_target(struct cpufreq_policy *policy, unsigned int index) opp = dev_pm_opp_find_freq_ceil(cpu_dev, &freq_hz); if (IS_ERR(opp)) { dev_err(cpu_dev, "failed to find OPP for %ld\n", freq_hz); + mutex_unlock(&cpufreq_lock); return PTR_ERR(opp); } @@ -78,6 +92,7 @@ static int light_set_target(struct cpufreq_policy *policy, unsigned int index) volt_old = regulator_get_voltage(dvdd_cpu_reg); if (volt_old < 0) { dev_err(cpu_dev, "failed to get cpu voltage\n"); + mutex_unlock(&cpufreq_lock); return volt_old; } @@ -113,12 +128,14 @@ static int light_set_target(struct cpufreq_policy *policy, unsigned int index) ret = regulator_set_voltage_tol(dvddm_cpu_reg, light_dvddm_volt[index], 0); if (ret) { dev_err(cpu_dev, "failed to scale vddsoc up: %d\n", ret); + mutex_unlock(&cpufreq_lock); return ret; } ret = regulator_set_voltage_tol(dvdd_cpu_reg, volt, 0); if (ret) { dev_err(cpu_dev, "failed to scale vddarm up: %d\n", ret); + mutex_unlock(&cpufreq_lock); return ret; } } @@ -150,6 +167,7 @@ static int light_set_target(struct cpufreq_policy *policy, unsigned int index) ret1 = regulator_set_voltage_tol(dvdd_cpu_reg, volt_old, 0); if (ret1) dev_err(cpu_dev, "failed to restore dvdd_cpu voltage: %d\n", ret1); + mutex_unlock(&cpufreq_lock); return ret; } @@ -177,6 +195,8 @@ static int light_set_target(struct cpufreq_policy *policy, unsigned int index) udelay(1); } + mutex_unlock(&cpufreq_lock); + return 0; } @@ -191,6 +211,20 @@ static int light_cpufreq_init(struct cpufreq_policy *policy) return 0; } +static int light_cpufreq_reboot_notifier(struct notifier_block *this, + unsigned long event, void *ptr) +{ + mutex_lock(&cpufreq_lock); + cpufreq_denied = true; + mutex_unlock(&cpufreq_lock); + + return NOTIFY_DONE; +} + +static struct notifier_block cpufreq_reboot_notifier = { + .notifier_call = light_cpufreq_reboot_notifier, +}; + static struct cpufreq_driver light_cpufreq_driver = { .flags = CPUFREQ_NEED_INITIAL_FREQ_CHECK | CPUFREQ_IS_COOLING_DEV, @@ -224,6 +258,53 @@ static struct notifier_block light_cpufreq_pm_notifier = { .notifier_call = light_cpufreq_pm_notify, }; +/* + * Set CPU PLL1's frequency as minimum on panic + */ +static int panic_cpufreq_notifier_call(struct notifier_block *nb, + unsigned long action, void *data) +{ + int cpu = smp_processor_id(); + struct cpufreq_policy *policy = cpufreq_cpu_get(cpu); + u32 val = readl(ap_sys_reg); + + pr_debug("[%s,%d]Enter panic_cpufreq_notifier_call\n", __func__, __LINE__); + + /* + * set CPU PLL1's frequency as minimum to compatible voltage + * becarefull if the PLL1 is serving the cpu core, swith to PLL0 first + */ + if (strcmp(__clk_get_name(clk_get_parent(clks[LIGHT_C910_CCLK].clk)), + __clk_get_name(clks[LIGHT_C910_CCLK_I0].clk))) { + pr_debug("[%s,%d]\n", __func__, __LINE__); + + clk_set_rate(clks[LIGHT_CPU_PLL0_FOUTPOSTDIV].clk, policy->min * 1000); + udelay(1); + clk_set_parent(clks[LIGHT_C910_CCLK].clk, clks[LIGHT_C910_CCLK_I0].clk); + + pr_debug("[%s,%d]\n", __func__, __LINE__); + } + + pr_debug("[%s,%d]\n", __func__, __LINE__); + /* + * since the clk driver will use PLL1 as the default clock source, + * in order to compatible voltage which is unpredictable we should + * set the CPU PLL1's frequency as minimum in advance, otherwise the + * system may crash in crash kernel stage. + */ + clk_prepare_enable(clks[LIGHT_CPU_PLL1_FOUTPOSTDIV].clk); + clk_set_rate(clks[LIGHT_CPU_PLL1_FOUTPOSTDIV].clk, policy->min * 1000); + udelay(1); + + pr_debug("finish to execute cpufreq notifier callback on panic\n"); + + return 0; +} + +static struct notifier_block panic_cpufreq_notifier = { + .notifier_call = panic_cpufreq_notifier_call, +}; + static int light_cpufreq_probe(struct platform_device *pdev) { struct device_node *np; @@ -341,6 +422,15 @@ soc_opp_out: of_node_put(np); + ret = atomic_notifier_chain_register(&panic_notifier_list, + &panic_cpufreq_notifier); + if (ret) { + pr_err("unable to register notifier(%d)\n", ret); + goto free_freq_table; + } + + register_reboot_notifier(&cpufreq_reboot_notifier); + dev_info(cpu_dev, "finish to register cpufreq driver\n"); return 0; @@ -391,6 +481,6 @@ static struct platform_driver light_cpufreq_platdrv = { module_platform_driver(light_cpufreq_platdrv); MODULE_ALIAS("platform:light-cpufreq"); -MODULE_AUTHOR("fugang.duan "); +MODULE_AUTHOR("fugang.duan "); MODULE_DESCRIPTION("Thead Light cpufreq driver"); MODULE_LICENSE("GPL v2"); diff --git a/drivers/dma/dw-axi-dmac/dw-axi-dmac-platform.c b/drivers/dma/dw-axi-dmac/dw-axi-dmac-platform.c index 0cc8b2301..d83ab5017 100644 --- a/drivers/dma/dw-axi-dmac/dw-axi-dmac-platform.c +++ b/drivers/dma/dw-axi-dmac/dw-axi-dmac-platform.c @@ -82,37 +82,49 @@ axi_chan_iowrite64(struct axi_dma_chan *chan, u32 reg, u64 val) static inline void axi_dma_disable(struct axi_dma_chip *chip) { u32 val; + unsigned long flags; + spin_lock_irqsave(&chip->lock, flags); val = axi_dma_ioread32(chip, DMAC_CFG); val &= ~DMAC_EN_MASK; axi_dma_iowrite32(chip, DMAC_CFG, val); + spin_unlock_irqrestore(&chip->lock, flags); } static inline void axi_dma_enable(struct axi_dma_chip *chip) { u32 val; + unsigned long flags; + spin_lock_irqsave(&chip->lock, flags); val = axi_dma_ioread32(chip, DMAC_CFG); val |= DMAC_EN_MASK; axi_dma_iowrite32(chip, DMAC_CFG, val); + spin_unlock_irqrestore(&chip->lock, flags); } static inline void axi_dma_irq_disable(struct axi_dma_chip *chip) { u32 val; + unsigned long flags; + spin_lock_irqsave(&chip->lock, flags); val = axi_dma_ioread32(chip, DMAC_CFG); val &= ~INT_EN_MASK; axi_dma_iowrite32(chip, DMAC_CFG, val); + spin_unlock_irqrestore(&chip->lock, flags); } static inline void axi_dma_irq_enable(struct axi_dma_chip *chip) { u32 val; + unsigned long flags; + spin_lock_irqsave(&chip->lock, flags); val = axi_dma_ioread32(chip, DMAC_CFG); val |= INT_EN_MASK; axi_dma_iowrite32(chip, DMAC_CFG, val); + spin_unlock_irqrestore(&chip->lock, flags); } static inline void axi_chan_irq_disable(struct axi_dma_chan *chan, u32 irq_mask) @@ -1348,6 +1360,7 @@ static int dw_probe(struct platform_device *pdev) chip->dev = &pdev->dev; chip->dw->hdata = hdata; + spin_lock_init(&chip->lock); chip->irq = platform_get_irq(pdev, 0); if (chip->irq < 0) return chip->irq; diff --git a/drivers/dma/dw-axi-dmac/dw-axi-dmac.h b/drivers/dma/dw-axi-dmac/dw-axi-dmac.h index bb388153c..803e98258 100644 --- a/drivers/dma/dw-axi-dmac/dw-axi-dmac.h +++ b/drivers/dma/dw-axi-dmac/dw-axi-dmac.h @@ -70,6 +70,7 @@ struct axi_dma_chip { struct clk *core_clk; struct clk *cfgr_clk; struct dw_axi_dma *dw; + spinlock_t lock; }; /* LLI == Linked List Item */ diff --git a/drivers/firmware/thead/light_aon.c b/drivers/firmware/thead/light_aon.c index d88ebfe11..8fbd808d7 100644 --- a/drivers/firmware/thead/light_aon.c +++ b/drivers/firmware/thead/light_aon.c @@ -239,6 +239,6 @@ static struct platform_driver light_aon_driver = { }; builtin_platform_driver(light_aon_driver); -MODULE_AUTHOR("fugang.duan "); +MODULE_AUTHOR("fugang.duan "); MODULE_DESCRIPTION("Thead Light firmware protocol driver"); MODULE_LICENSE("GPL v2"); diff --git a/drivers/firmware/thead/light_aon_pd.c b/drivers/firmware/thead/light_aon_pd.c index 4fcad4256..3bef67df5 100644 --- a/drivers/firmware/thead/light_aon_pd.c +++ b/drivers/firmware/thead/light_aon_pd.c @@ -412,6 +412,6 @@ static struct platform_driver light_aon_pd_driver = { }; builtin_platform_driver(light_aon_pd_driver); -MODULE_AUTHOR("fugang.duan "); +MODULE_AUTHOR("fugang.duan "); MODULE_DESCRIPTION("Thead Light firmware protocol driver"); MODULE_LICENSE("GPL v2"); diff --git a/drivers/firmware/thead/light_aon_test.c b/drivers/firmware/thead/light_aon_test.c index 38e3f1095..172025430 100644 --- a/drivers/firmware/thead/light_aon_test.c +++ b/drivers/firmware/thead/light_aon_test.c @@ -158,6 +158,6 @@ static struct platform_driver light_aon_driver = { }; module_platform_driver(light_aon_driver); -MODULE_AUTHOR("fugang.duan "); +MODULE_AUTHOR("fugang.duan "); MODULE_DESCRIPTION("Thead Light firmware protocol test driver"); MODULE_LICENSE("GPL v2"); diff --git a/drivers/gpu/drm/bridge/synopsys/dw-hdmi.c b/drivers/gpu/drm/bridge/synopsys/dw-hdmi.c index 05cac7848..8af46a6b9 100644 --- a/drivers/gpu/drm/bridge/synopsys/dw-hdmi.c +++ b/drivers/gpu/drm/bridge/synopsys/dw-hdmi.c @@ -49,6 +49,10 @@ #define HDMI14_MAX_TMDSCLK 340000000 +#define HDMI_DDC_CHECK_MAX_RETRIES 100 +#define HDMI_DDC_CHECK_NORMAL 2 +#define HDMI_SCRAMBLING_RETRIES 20 + enum hdmi_datamap { RGB444_8B = 0x01, RGB444_10B = 0x03, @@ -1865,6 +1869,45 @@ static void hdmi_config_drm_infoframe(struct dw_hdmi *hdmi, HDMI_FC_PACKET_TX_EN_DRM_MASK, HDMI_FC_PACKET_TX_EN); } +static bool dw_hdmi_ddc_debounce(struct dw_hdmi *hdmi) +{ + u8 config, val, orig; + int ret, count = 0, check = 0; + + drm_scdc_readb(hdmi->ddc, SCDC_TMDS_CONFIG, &orig); + + do { + drm_scdc_readb(hdmi->ddc, SCDC_TMDS_CONFIG, &config); + if (count & 0x1) + config |= SCDC_SCRAMBLING_ENABLE; + else + config &= ~SCDC_SCRAMBLING_ENABLE; + drm_scdc_writeb(hdmi->ddc, SCDC_TMDS_CONFIG, config); + drm_scdc_readb(hdmi->ddc, SCDC_TMDS_CONFIG, &val); + + if (val != config) + check = 0; + else + check++; + if (check >= HDMI_DDC_CHECK_NORMAL) { + ret = true; + goto out; + } + + if (count++ >= HDMI_DDC_CHECK_MAX_RETRIES) { + dev_err(hdmi->dev, "exceed max retries:%d\n", HDMI_DDC_CHECK_MAX_RETRIES); + ret = false; + goto out; + } + + usleep_range(10000, 15000); + } while (1); + +out: + drm_scdc_writeb(hdmi->ddc, SCDC_TMDS_CONFIG, orig); + return ret; +} + static void hdmi_av_composer(struct dw_hdmi *hdmi, const struct drm_display_info *display, const struct drm_display_mode *mode) @@ -1983,7 +2026,8 @@ static void hdmi_av_composer(struct dw_hdmi *hdmi, * Source Devices compliant shall set the * Source Version = 1. */ - mdelay(60); + dw_hdmi_ddc_debounce(hdmi); + drm_scdc_readb(hdmi->ddc, SCDC_SINK_VERSION, &bytes); drm_scdc_writeb(hdmi->ddc, SCDC_SOURCE_VERSION, @@ -2137,6 +2181,28 @@ static void hdmi_disable_overflow_interrupts(struct dw_hdmi *hdmi) HDMI_IH_MUTE_FC_STAT2); } +static void hdmi_check_scrambling_status(struct dw_hdmi *hdmi, + const struct drm_display_info *display) +{ + int count = 0; + + if (!dw_hdmi_support_scdc(hdmi, display)) + return; + + do { + if (drm_scdc_get_scrambling_status(hdmi->ddc)) + break; + + /* polling scrambling_status up to a maximum of 200ms */ + if (count++ >= HDMI_SCRAMBLING_RETRIES) { + dev_err(hdmi->dev, + "TMDS link of scrambling_status is not ready\n"); + break; + } + usleep_range(10000, 11000); + } while (1); +} + static int dw_hdmi_setup(struct dw_hdmi *hdmi, const struct drm_connector *connector, const struct drm_display_mode *mode) @@ -2223,6 +2289,7 @@ static int dw_hdmi_setup(struct dw_hdmi *hdmi, hdmi_video_csc(hdmi); hdmi_video_sample(hdmi); hdmi_tx_hdcp_config(hdmi); + hdmi_check_scrambling_status(hdmi, &connector->display_info); dw_hdmi_clear_overflow(hdmi); @@ -2960,6 +3027,8 @@ static irqreturn_t dw_hdmi_hardirq(int irq, void *dev_id) intr_stat = hdmi_readb(hdmi, HDMI_IH_PHY_STAT0); if (intr_stat) { + hdmi_writeb(hdmi, intr_stat, HDMI_IH_PHY_STAT0); + hdmi_writeb(hdmi, 0xff, HDMI_PHY_MASK0); hdmi_writeb(hdmi, ~0, HDMI_IH_MUTE_PHY_STAT0); return IRQ_WAKE_THREAD; } @@ -3000,6 +3069,7 @@ static irqreturn_t dw_hdmi_irq(int irq, void *dev_id) struct dw_hdmi *hdmi = dev_id; u8 intr_stat, phy_int_pol, phy_pol_mask, phy_stat; + msleep(50); intr_stat = hdmi_readb(hdmi, HDMI_IH_PHY_STAT0); phy_int_pol = hdmi_readb(hdmi, HDMI_PHY_POL0); phy_stat = hdmi_readb(hdmi, HDMI_PHY_STAT0); @@ -3057,6 +3127,7 @@ static irqreturn_t dw_hdmi_irq(int irq, void *dev_id) hdmi_writeb(hdmi, intr_stat, HDMI_IH_PHY_STAT0); hdmi_writeb(hdmi, ~(HDMI_IH_PHY_STAT0_HPD | HDMI_IH_PHY_STAT0_RX_SENSE), HDMI_IH_MUTE_PHY_STAT0); + hdmi_writeb(hdmi, (u8)~(HDMI_PHY_HPD | HDMI_PHY_RX_SENSE), HDMI_PHY_MASK0); return IRQ_HANDLED; } diff --git a/drivers/gpu/drm/panel/panel-ilitek-ili9881c.c b/drivers/gpu/drm/panel/panel-ilitek-ili9881c.c index c0db958ac..30742fb23 100644 --- a/drivers/gpu/drm/panel/panel-ilitek-ili9881c.c +++ b/drivers/gpu/drm/panel/panel-ilitek-ili9881c.c @@ -690,11 +690,6 @@ static const struct ili9881c_instr txd_dy800qwxpab_init[] = { }; static const struct ili9881c_instr gx_kd080d74_d028_init[] = { - ILI9881C_SWITCH_PAGE_INSTR(0), - ILI9881C_COMMAND_INSTR(0x35, 0x0), - ILI9881C_COMMAND_INSTR(0x11, 0x0), - ILI9881C_COMMAND_INSTR(0x29, 0x0), - ILI9881C_SWITCH_PAGE_INSTR(0x3), ILI9881C_COMMAND_INSTR(0x01, 0x00), ILI9881C_COMMAND_INSTR(0x02, 0x00), diff --git a/drivers/gpu/drm/verisilicon/dw_hdmi-light.c b/drivers/gpu/drm/verisilicon/dw_hdmi-light.c index 2569b45b5..745fa7e8f 100644 --- a/drivers/gpu/drm/verisilicon/dw_hdmi-light.c +++ b/drivers/gpu/drm/verisilicon/dw_hdmi-light.c @@ -163,7 +163,7 @@ struct platform_driver dw_hdmi_light_platform_driver = { }, }; -MODULE_AUTHOR("You Xiao "); +MODULE_AUTHOR("You Xiao "); MODULE_DESCRIPTION("Light Platforms Specific DW-HDMI Driver Extention"); MODULE_LICENSE("GPL v2"); MODULE_ALIAS("platform:dwhdmi-light"); diff --git a/drivers/gpu/drm/verisilicon/vs_dc_hw.c b/drivers/gpu/drm/verisilicon/vs_dc_hw.c index a9944437f..d73dc9051 100644 --- a/drivers/gpu/drm/verisilicon/vs_dc_hw.c +++ b/drivers/gpu/drm/verisilicon/vs_dc_hw.c @@ -1390,6 +1390,9 @@ int dc_hw_init(struct dc_hw *hw) dc_write(hw, DC_OVERLAY_WATER_MARK + 0xc, 0x3000); dc_write(hw, DC_QOS_CONFIG, 0xc0); + dc_write(hw, DC_CLK_GATTING, 0x0); + dc_write(hw, DC_CLK_GATTING + 0x4, 0x0); + return 0; } diff --git a/drivers/gpu/drm/verisilicon/vs_gem.c b/drivers/gpu/drm/verisilicon/vs_gem.c index 0608abe2f..310bd31bc 100644 --- a/drivers/gpu/drm/verisilicon/vs_gem.c +++ b/drivers/gpu/drm/verisilicon/vs_gem.c @@ -227,10 +227,13 @@ static void vs_gem_free_object(struct drm_gem_object *obj) { struct vs_gem_object *vs_obj = to_vs_gem_object(obj); - if (obj->import_attach) + if (obj->import_attach) { drm_prime_gem_destroy(obj, vs_obj->sgt); - else + kvfree(vs_obj->pages); + } + else { vs_gem_free_buf(vs_obj); + } drm_gem_object_release(obj); diff --git a/drivers/iio/adc/light_adc.c b/drivers/iio/adc/light_adc.c index ce78e5600..57800aadf 100644 --- a/drivers/iio/adc/light_adc.c +++ b/drivers/iio/adc/light_adc.c @@ -722,6 +722,6 @@ static struct platform_driver light_adc_driver = { module_platform_driver(light_adc_driver); -MODULE_AUTHOR("fugang.duan "); +MODULE_AUTHOR("fugang.duan "); MODULE_DESCRIPTION("Thead Light ADC driver"); MODULE_LICENSE("GPL v2"); diff --git a/drivers/irqchip/irq-riscv-intc.c b/drivers/irqchip/irq-riscv-intc.c index 8017f6d32..e376c32a9 100644 --- a/drivers/irqchip/irq-riscv-intc.c +++ b/drivers/irqchip/irq-riscv-intc.c @@ -22,7 +22,31 @@ static struct irq_domain *intc_domain; static asmlinkage void riscv_intc_irq(struct pt_regs *regs) { unsigned long cause = regs->cause & ~CAUSE_IRQ_FLAG; + unsigned long epc = instruction_pointer(regs); + u32 insn; +#define MATCH_LR_W 0x1000202f +#define MASK_LR_W 0xf9f0707f +#define MATCH_DCACHE_CVAL1 0x0240000b +#define MASK_DCACHE_CVAL1 0xfff07fff + + if ((epc & 0x7f) != 4) + goto out; + + if (__get_user(insn, (u32 *)epc)) + goto out; + + if ((insn & MASK_LR_W) != MATCH_LR_W) + goto out; + + if (__get_user(insn, (u32 *)(epc - 4))) + goto out; + + if ((insn & MASK_DCACHE_CVAL1) != MATCH_DCACHE_CVAL1) + goto out; + + instruction_pointer_set(regs, epc - 4); +out: if (unlikely(cause >= BITS_PER_LONG)) panic("unexpected interrupt cause"); diff --git a/drivers/mailbox/light-mailbox.c b/drivers/mailbox/light-mailbox.c index f3c67ae68..f3d34d947 100644 --- a/drivers/mailbox/light-mailbox.c +++ b/drivers/mailbox/light-mailbox.c @@ -254,10 +254,8 @@ static irqreturn_t light_mbox_isr(int irq, void *p) mbox_chan_txdone(chan, 0); } - if (!info0_data && !info7_data) { - dev_warn_ratelimited(priv->dev, "not expected chan[%d] interrupt\n", cp->idx); + if (!info0_data && !info7_data) return IRQ_NONE; - } return IRQ_HANDLED; } @@ -504,6 +502,6 @@ static struct platform_driver light_mbox_driver = { }; module_platform_driver(light_mbox_driver); -MODULE_AUTHOR("fugang.duan "); +MODULE_AUTHOR("fugang.duan "); MODULE_DESCRIPTION("Thead Light mailbox IPC driver"); MODULE_LICENSE("GPL v2"); diff --git a/drivers/misc/dsmart_card.c b/drivers/misc/dsmart_card.c index 52c792bbc..c6c6e1083 100644 --- a/drivers/misc/dsmart_card.c +++ b/drivers/misc/dsmart_card.c @@ -1246,6 +1246,6 @@ static struct platform_driver dsmart_card_driver = { }; module_platform_driver(dsmart_card_driver); -MODULE_AUTHOR("wei.liu "); +MODULE_AUTHOR("wei.liu "); MODULE_DESCRIPTION("iso7816 smart card platform driver"); MODULE_LICENSE("GPL v2"); diff --git a/drivers/mmc/host/sdhci-of-dwcmshc.c b/drivers/mmc/host/sdhci-of-dwcmshc.c index bc58d8ee3..011e14080 100644 --- a/drivers/mmc/host/sdhci-of-dwcmshc.c +++ b/drivers/mmc/host/sdhci-of-dwcmshc.c @@ -33,6 +33,7 @@ struct dwcmshc_priv { bool pull_up_en; bool io_fixed_1v8; bool wprtn_ignore; + long reset_cnt; }; #define HS400_DELAY_LINE 24 @@ -255,12 +256,35 @@ static int snps_execute_tuning(struct sdhci_host *host, u32 opcode) return 0; } -static void snps_sdhci_reset(struct sdhci_host *host, u8 mask) +static void snps_sdhci_set_phy(struct sdhci_host *host) { struct sdhci_pltfm_host *pltfm_host; struct dwcmshc_priv *priv; u8 emmc_ctl; - //u32 soc_reg; + + pltfm_host = sdhci_priv(host); + priv = sdhci_pltfm_priv(pltfm_host); + + /*Before power on,set PHY configs*/ + emmc_ctl = sdhci_readw(host, EMMC_CTRL_R); + if (priv->is_emmc_card) { + snps_phy_1_8v_init(host); + emmc_ctl |= (1 << CARD_IS_EMMC); + } else { + snps_phy_3_3v_init(host); + emmc_ctl &=~(1 << CARD_IS_EMMC); + } + sdhci_writeb(host, emmc_ctl, EMMC_CTRL_R); + sdhci_writeb(host, 0x25, PHY_DLL_CNFG1_R); +} + +static void snps_sdhci_reset(struct sdhci_host *host, u8 mask) +{ + struct sdhci_pltfm_host *pltfm_host; + struct dwcmshc_priv *priv; + + u16 ctrl_2; + pltfm_host = sdhci_priv(host); priv = sdhci_pltfm_priv(pltfm_host); @@ -274,19 +298,21 @@ static void snps_sdhci_reset(struct sdhci_host *host, u8 mask) /*host reset*/ sdhci_reset(host, mask); - /*fix host reset error*/ - mdelay(100); + + /* Before phy reset,set io voltage to fixed to 1v8. + * For mask is SDHCI_RESET_ALL,regs will reset to default val. + */ + if(priv->io_fixed_1v8){ + ctrl_2 = sdhci_readw(host, SDHCI_HOST_CONTROL2); + if(! (ctrl_2 & SDHCI_CTRL_VDD_180)){ + ctrl_2 |= SDHCI_CTRL_VDD_180; + sdhci_writew(host, ctrl_2, SDHCI_HOST_CONTROL2); + } + } + + ++(priv->reset_cnt); + pr_debug("%s: sdhci reset cnt %ld\n",host->hw_name,priv->reset_cnt); - emmc_ctl = sdhci_readw(host, EMMC_CTRL_R); - if (priv->is_emmc_card) { - snps_phy_1_8v_init(host); - emmc_ctl |= (1 << CARD_IS_EMMC); - } else { - snps_phy_3_3v_init(host); - emmc_ctl &=~(1 << CARD_IS_EMMC); - } - sdhci_writeb(host, emmc_ctl, EMMC_CTRL_R); - sdhci_writeb(host, 0x25, PHY_DLL_CNFG1_R); } /* * If DMA addr spans 128MB boundary, we split the DMA transfer into two @@ -362,7 +388,7 @@ static void dwcmshc_set_uhs_signaling(struct sdhci_host *host, if (priv->io_fixed_1v8) ctrl_2 |= SDHCI_CTRL_VDD_180; - + sdhci_writew(host, ctrl_2, SDHCI_HOST_CONTROL2); if (timing == MMC_TIMING_MMC_HS400) { @@ -381,6 +407,7 @@ static void dwcmshc_set_uhs_signaling(struct sdhci_host *host, sdhci_writel(host, reg, AT_CTRL_R); delay_line = HS400_DELAY_LINE; + snps_sdhci_set_phy(host); /* update tx delay*/ } else { sdhci_writeb(host, 0, PHY_DLLDL_CNFG_R); } @@ -400,8 +427,141 @@ static unsigned int dwcmshc_pltfm_get_ro(struct sdhci_host *host) return is_readonly; } +/* Complete selection of HS400 ,software reset DAT & cmd line +* resolve for first time data access error(time out) when +* first swith to hs400 mode. +* +* From : SDHCI_QUIRK_RESET_CMD_DATA_ON_IOS +* Some (ENE) controllers go apeshit on some ios operation, +* signalling timeout and CRC errors even on CMD0. Resetting +* it on each ios seems to solve the problem. +* +*/ +static void dwcmshc_hs400_complete(struct mmc_host *mmc) +{ + struct sdhci_host *host = mmc_priv(mmc); + u8 mask = SDHCI_RESET_CMD | SDHCI_RESET_DATA; + + if (host->quirks & SDHCI_QUIRK_NO_CARD_NO_RESET) { + + if (!mmc->ops->get_cd(mmc)) + return; + } + snps_sdhci_reset(host,mask); + //host->ops->reset(host, mask); +} + +static void sdhci_set_power_reg(struct sdhci_host *host, unsigned char mode, + unsigned short vdd) +{ + struct mmc_host *mmc = host->mmc; + + mmc_regulator_set_ocr(mmc, mmc->supply.vmmc, vdd); + + if (mode != MMC_POWER_OFF) + sdhci_writeb(host, SDHCI_POWER_ON, SDHCI_POWER_CONTROL); + else + sdhci_writeb(host, 0, SDHCI_POWER_CONTROL); +} + +/* Add snps_sdhci_set_phy before POWER ON for this controller. + * Similar to public sdhci.c sdhci_set_power_noreg(). + */ +static void dwcmshc_set_power_noreg(struct sdhci_host *host, unsigned char mode, + unsigned short vdd) +{ + u8 pwr = 0; + + if (mode != MMC_POWER_OFF) { + switch (1 << vdd) { + case MMC_VDD_165_195: + /* + * Without a regulator, SDHCI does not support 2.0v + * so we only get here if the driver deliberately + * added the 2.0v range to ocr_avail. Map it to 1.8v + * for the purpose of turning on the power. + */ + case MMC_VDD_20_21: + pwr = SDHCI_POWER_180; + break; + case MMC_VDD_29_30: + case MMC_VDD_30_31: + pwr = SDHCI_POWER_300; + break; + case MMC_VDD_32_33: + case MMC_VDD_33_34: + /* + * 3.4 ~ 3.6V are valid only for those platforms where it's + * known that the voltage range is supported by hardware. + */ + case MMC_VDD_34_35: + case MMC_VDD_35_36: + pwr = SDHCI_POWER_330; + break; + default: + WARN(1, "%s: Invalid vdd %#x\n", + mmc_hostname(host->mmc), vdd); + break; + } + } + + if (host->pwr == pwr) + return; + + host->pwr = pwr; + snps_sdhci_set_phy(host); + + if (pwr == 0) { + sdhci_writeb(host, 0, SDHCI_POWER_CONTROL); + /* + if (host->quirks2 & SDHCI_QUIRK2_CARD_ON_NEEDS_BUS_ON) + sdhci_runtime_pm_bus_off(host); + */ + } else { + /* + * Spec says that we should clear the power reg before setting + * a new value. Some controllers don't seem to like this though. + */ + if (!(host->quirks & SDHCI_QUIRK_SINGLE_POWER_WRITE)) + sdhci_writeb(host, 0, SDHCI_POWER_CONTROL); + + /* + * At least the Marvell CaFe chip gets confused if we set the + * voltage and set turn on power at the same time, so set the + * voltage first. + */ + if (host->quirks & SDHCI_QUIRK_NO_SIMULT_VDD_AND_POWER) + sdhci_writeb(host, pwr, SDHCI_POWER_CONTROL); + + pwr |= SDHCI_POWER_ON; + + sdhci_writeb(host, pwr, SDHCI_POWER_CONTROL); + /* + if (host->quirks2 & SDHCI_QUIRK2_CARD_ON_NEEDS_BUS_ON) + sdhci_runtime_pm_bus_on(host); + */ + /* + * Some controllers need an extra 10ms delay of 10ms before + * they can apply clock after applying power + */ + if (host->quirks & SDHCI_QUIRK_DELAY_AFTER_POWER) + mdelay(10); + } +} + +static void dwcmshc_set_power(struct sdhci_host *host, unsigned char mode, + unsigned short vdd) +{ + if (IS_ERR(host->mmc->supply.vmmc)) + dwcmshc_set_power_noreg(host, mode, vdd); + else + sdhci_set_power_reg(host, mode, vdd); +} + + static const struct sdhci_ops sdhci_dwcmshc_ops = { .set_clock = sdhci_set_clock, + .set_power = dwcmshc_set_power, .set_bus_width = sdhci_set_bus_width, .set_uhs_signaling = dwcmshc_set_uhs_signaling, .get_max_clock = sdhci_pltfm_clk_get_max_clock, @@ -415,7 +575,7 @@ static const struct sdhci_ops sdhci_dwcmshc_ops = { static const struct sdhci_pltfm_data sdhci_dwcmshc_pdata = { .ops = &sdhci_dwcmshc_ops, - .quirks = SDHCI_QUIRK_CAP_CLOCK_BASE_BROKEN, + .quirks = SDHCI_QUIRK_CAP_CLOCK_BASE_BROKEN | SDHCI_QUIRK_SINGLE_POWER_WRITE, .quirks2 = SDHCI_QUIRK2_PRESET_VALUE_BROKEN, }; @@ -463,6 +623,15 @@ static int dwcmshc_probe(struct platform_device *pdev) priv->io_fixed_1v8 = true; else priv->io_fixed_1v8 = false; + + /* start_signal_voltage_switch will try 3V3 first, when io fixed 1V8, + * use SDHCI_SIGNALING_180 ranther than SDHCI_SIGNALING_330 to avoid set to 3V3 + * in sdhci_start_signal_voltage_switch. + */ + if(priv->io_fixed_1v8){ + host->flags &=~SDHCI_SIGNALING_330; + host->flags |= SDHCI_SIGNALING_180; + } if (device_property_present(&pdev->dev, "wprtn_ignore")) priv->wprtn_ignore = true; @@ -490,6 +659,7 @@ static int dwcmshc_probe(struct platform_device *pdev) sdhci_get_of_property(pdev); host->mmc_host_ops.request = dwcmshc_request; + host->mmc_host_ops.hs400_complete = dwcmshc_hs400_complete; err = sdhci_add_host(host); if (err) diff --git a/drivers/nvmem/light-efuse.c b/drivers/nvmem/light-efuse.c index ce1f4f3de..e09810498 100644 --- a/drivers/nvmem/light-efuse.c +++ b/drivers/nvmem/light-efuse.c @@ -965,6 +965,6 @@ static struct platform_driver light_efuse_driver = { }; module_platform_driver(light_efuse_driver); -MODULE_AUTHOR("wei.liu "); +MODULE_AUTHOR("wei.liu "); MODULE_DESCRIPTION("Thead light nvmem driver"); MODULE_LICENSE("GPL v2"); diff --git a/drivers/phy/synopsys/phy-dw-mipi-dphy.c b/drivers/phy/synopsys/phy-dw-mipi-dphy.c index 06f3a9949..a6db5d574 100644 --- a/drivers/phy/synopsys/phy-dw-mipi-dphy.c +++ b/drivers/phy/synopsys/phy-dw-mipi-dphy.c @@ -767,6 +767,6 @@ static struct platform_driver dw_dphy_driver = { }; module_platform_driver(dw_dphy_driver); -MODULE_AUTHOR("You Xiao "); +MODULE_AUTHOR("You Xiao "); MODULE_DESCRIPTION("Synopsys DesignWare MIPI DPHY driver"); MODULE_LICENSE("GPL"); diff --git a/drivers/pinctrl/thead/pinctrl-light.c b/drivers/pinctrl/thead/pinctrl-light.c index be2648eb5..544727e10 100644 --- a/drivers/pinctrl/thead/pinctrl-light.c +++ b/drivers/pinctrl/thead/pinctrl-light.c @@ -913,6 +913,6 @@ static struct platform_driver light_pinctrl_driver = { module_platform_driver(light_pinctrl_driver); -MODULE_AUTHOR("fugang.duan "); +MODULE_AUTHOR("fugang.duan "); MODULE_DESCRIPTION("Thead light pinctrl driver"); MODULE_LICENSE("GPL v2"); diff --git a/drivers/pwm/pwm-light.c b/drivers/pwm/pwm-light.c index 49a40f3c0..3dd826b5c 100644 --- a/drivers/pwm/pwm-light.c +++ b/drivers/pwm/pwm-light.c @@ -313,6 +313,6 @@ static struct platform_driver pwm_light_driver = { }; module_platform_driver(pwm_light_driver); -MODULE_AUTHOR("wei.liu "); +MODULE_AUTHOR("wei.liu "); MODULE_DESCRIPTION("Thead light pwm driver"); MODULE_LICENSE("GPL v2"); diff --git a/drivers/regulator/light-regulator-aon.c b/drivers/regulator/light-regulator-aon.c index c4216bd05..d30cb9561 100644 --- a/drivers/regulator/light-regulator-aon.c +++ b/drivers/regulator/light-regulator-aon.c @@ -251,6 +251,42 @@ static int aon_regu_is_enabled(struct regulator_dev *reg) return (int) msg.rpc.regu_pwr_get.status; } +static int aon_regu_set_voltage(struct regulator_dev *reg, + int minuV, int uV, unsigned *selector) +{ + u16 regu_id =(u16) rdev_get_id(reg); + u32 voltage = minuV; /* uV */ + int err; + + pr_debug("[%s,%d]minuV = %d, uV = %d\n", __func__, __LINE__, minuV, uV); + + err = aon_set_regulator(light_aon_pmic_info.ipc_handle, regu_id, + voltage, 0, 0); + if (err) { + pr_err("failed to set Voltages to %d!\n", minuV); + return -EINVAL; + } + + return 0; +} + +static int aon_regu_get_voltage(struct regulator_dev *reg) +{ + u16 regu_id = (u16) rdev_get_id(reg); + int voltage, ret; + + ret = aon_get_regulator(light_aon_pmic_info.ipc_handle, regu_id, + &voltage, NULL, 0); + if (ret) { + pr_err("failed to get voltage\n"); + return -EINVAL; + } + + pr_debug("[%s,%d]voltage = %d\n", __func__, __LINE__, voltage); + + return voltage; +} + static const struct apcpu_vol_set *apcpu_get_matched_signed_off_voltage(u32 vdd, u32 vddm) { int vol_count = ARRAY_SIZE(apcpu_volts); @@ -362,6 +398,9 @@ static const struct regulator_ops regu_common_ops = { .enable = aon_regu_enable, .disable = aon_regu_disable, .is_enabled = aon_regu_is_enabled, + .list_voltage = regulator_list_voltage_linear, + .set_voltage = aon_regu_set_voltage, + .get_voltage = aon_regu_get_voltage, }; static const struct regulator_ops apcpu_dvdd_ops = { .enable = aon_regu_dummy_enable, @@ -843,7 +882,7 @@ static struct platform_driver light_aon_regulator_driver = { module_platform_driver(light_aon_regulator_driver); -MODULE_AUTHOR("fugang.duan "); -MODULE_AUTHOR("linghui.zlh "); +MODULE_AUTHOR("fugang.duan "); +MODULE_AUTHOR("linghui.zlh "); MODULE_DESCRIPTION("Thead Light Aon regulator virtual driver"); MODULE_LICENSE("GPL v2"); diff --git a/drivers/reset/Makefile b/drivers/reset/Makefile index 16947610c..1beda5490 100644 --- a/drivers/reset/Makefile +++ b/drivers/reset/Makefile @@ -11,6 +11,7 @@ obj-$(CONFIG_RESET_BRCMSTB) += reset-brcmstb.o obj-$(CONFIG_RESET_BRCMSTB_RESCAL) += reset-brcmstb-rescal.o obj-$(CONFIG_RESET_HSDK) += reset-hsdk.o obj-$(CONFIG_RESET_IMX7) += reset-imx7.o +obj-$(CONFIG_RESET_LIGHT) += reset-light.o obj-$(CONFIG_RESET_INTEL_GW) += reset-intel-gw.o obj-$(CONFIG_RESET_LANTIQ) += reset-lantiq.o obj-$(CONFIG_RESET_LPC18XX) += reset-lpc18xx.o diff --git a/drivers/reset/reset-light.c b/drivers/reset/reset-light.c new file mode 100644 index 000000000..8deafacb8 --- /dev/null +++ b/drivers/reset/reset-light.c @@ -0,0 +1,140 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (c) 2017, Impinj, Inc. + * + * i.MX7 System Reset Controller (SRC) driver + * + * Author: Andrey Smirnov + */ + +#include +#include +#include +#include +#include +#include +#include + +struct light_src_signal { + unsigned int offset, bit; +}; + +struct light_src_variant { + const struct light_src_signal *signals; + unsigned int signals_num; + struct reset_control_ops ops; +}; + +struct light_src { + struct reset_controller_dev rcdev; + struct regmap *regmap; + const struct light_src_signal *signals; +}; + +enum light_src_registers { + SRC_WDT0 = 0x0034, + SRC_WDT1 = 0x0038, +}; + +static int light_reset_update(struct light_src *lightsrc, + unsigned long id, unsigned int value) +{ + const struct light_src_signal *signal = &lightsrc->signals[id]; + + return regmap_update_bits(lightsrc->regmap, + signal->offset, signal->bit, value); +} + +static const struct light_src_signal light_src_signals[] = { + [LIGHT_RESET_WDT0] = { SRC_WDT0, BIT(0) }, + [LIGHT_RESET_WDT1] = { SRC_WDT1, BIT(0) }, +}; + +static struct light_src *to_light_src(struct reset_controller_dev *rcdev) +{ + return container_of(rcdev, struct light_src, rcdev); +} + +static int light_reset_set(struct reset_controller_dev *rcdev, + unsigned long id, bool assert) +{ + struct light_src *lightsrc = to_light_src(rcdev); + const unsigned int bit = lightsrc->signals[id].bit; + unsigned int value = assert ? bit : 0; + + switch (id) { + /*add special dispatch*/ + default: + break; + } + + return light_reset_update(lightsrc, id, value); +} + +static int light_reset_assert(struct reset_controller_dev *rcdev, + unsigned long id) +{ + pr_info("%s id:%u\n",__func__,id); + return light_reset_set(rcdev, id, false); +} + +static int light_reset_deassert(struct reset_controller_dev *rcdev, + unsigned long id) +{ + pr_info("%s id:%u\n",__func__,id); + return light_reset_set(rcdev, id, true); +} + +static const struct light_src_variant variant_light = { + .signals = light_src_signals, + .signals_num = ARRAY_SIZE(light_src_signals), + .ops = { + .assert = light_reset_assert, + .deassert = light_reset_deassert, + }, +}; + +static int light_reset_probe(struct platform_device *pdev) +{ + struct light_src *lightsrc; + struct device *dev = &pdev->dev; + struct regmap_config config = { .name = "src" }; + const struct light_src_variant *variant = of_device_get_match_data(dev); + + lightsrc = devm_kzalloc(dev, sizeof(*lightsrc), GFP_KERNEL); + if (!lightsrc) + return -ENOMEM; + + lightsrc->signals = variant->signals; + lightsrc->regmap = syscon_node_to_regmap(dev->of_node); + if (IS_ERR(lightsrc->regmap)) { + dev_err(dev, "Unable to get light-src regmap"); + return PTR_ERR(lightsrc->regmap); + } + regmap_attach_dev(dev, lightsrc->regmap, &config); + + lightsrc->rcdev.owner = THIS_MODULE; + lightsrc->rcdev.nr_resets = variant->signals_num; + lightsrc->rcdev.ops = &variant->ops; + lightsrc->rcdev.of_node = dev->of_node; + + return devm_reset_controller_register(dev, &lightsrc->rcdev); +} + +static const struct of_device_id light_reset_dt_ids[] = { + { .compatible = "thead,light-reset-src", .data = &variant_light }, +}; +MODULE_DEVICE_TABLE(of, light_reset_dt_ids); + +static struct platform_driver light_reset_driver = { + .probe = light_reset_probe, + .driver = { + .name = KBUILD_MODNAME, + .of_match_table = light_reset_dt_ids, + }, +}; +module_platform_driver(light_reset_driver); + +MODULE_AUTHOR("zenglinghui.zlh "); +MODULE_DESCRIPTION("Thead light reset driver"); +MODULE_LICENSE("GPL v2"); diff --git a/drivers/soc/thead/light-iopmp.c b/drivers/soc/thead/light-iopmp.c index b0144eba3..1286a2ed3 100644 --- a/drivers/soc/thead/light-iopmp.c +++ b/drivers/soc/thead/light-iopmp.c @@ -672,6 +672,6 @@ static int __init light_iopmp_init(void) arch_initcall(light_iopmp_init); MODULE_ALIAS("platform:light-iopmp"); -MODULE_AUTHOR("fugang.duan "); +MODULE_AUTHOR("fugang.duan "); MODULE_DESCRIPTION("Thead Light iopmp driver"); MODULE_LICENSE("GPL v2"); diff --git a/drivers/spi/spi-dw-mmio-quad.c b/drivers/spi/spi-dw-mmio-quad.c index 0a7ca5f35..ed14c3d08 100644 --- a/drivers/spi/spi-dw-mmio-quad.c +++ b/drivers/spi/spi-dw-mmio-quad.c @@ -145,6 +145,6 @@ static struct platform_driver dw_qspi_mmio_driver = { }; module_platform_driver(dw_qspi_mmio_driver); -MODULE_AUTHOR("linghui zeng "); +MODULE_AUTHOR("linghui zeng "); MODULE_DESCRIPTION("Memory-mapped I/O interface driver for DW ehance-spi Core"); MODULE_LICENSE("GPL v2"); diff --git a/drivers/spi/spi-dw-quad.c b/drivers/spi/spi-dw-quad.c index 846718df2..803a5ea72 100644 --- a/drivers/spi/spi-dw-quad.c +++ b/drivers/spi/spi-dw-quad.c @@ -791,6 +791,6 @@ int dw_qspi_resume_host(struct dw_spi *dws) } EXPORT_SYMBOL_GPL(dw_qspi_resume_host); -MODULE_AUTHOR("linghui zeng"); +MODULE_AUTHOR("linghui zeng"); MODULE_DESCRIPTION("Driver for DesignWare ehance-spi controller core"); MODULE_LICENSE("GPL v2"); diff --git a/drivers/watchdog/dw_wdt.c b/drivers/watchdog/dw_wdt.c index 978f0a8ee..76dfce326 100644 --- a/drivers/watchdog/dw_wdt.c +++ b/drivers/watchdog/dw_wdt.c @@ -372,11 +372,16 @@ static irqreturn_t dw_wdt_irq(int irq, void *devid) * following ping operations. */ val = readl(dw_wdt->regs + WDOG_INTERRUPT_STATUS_REG_OFFSET); - if (!val) + if (!val ) { + pr_warn("watchdog irq enter. however status is 0\n"); return IRQ_NONE; + } + WARN(1, "watchdog app was stuck! watchdog pretimeout event\n"); watchdog_notify_pretimeout(&dw_wdt->wdd); + dw_wdt_ping(&dw_wdt->wdd); + return IRQ_HANDLED; } diff --git a/drivers/watchdog/light_wdt.c b/drivers/watchdog/light_wdt.c index 6c18581e7..41922940e 100644 --- a/drivers/watchdog/light_wdt.c +++ b/drivers/watchdog/light_wdt.c @@ -14,6 +14,7 @@ #include #include #include +#include #include #include @@ -44,6 +45,7 @@ struct light_wdt_device { struct device *dev; struct light_aon_ipc *ipc_handle; struct light_aon_msg_wdg_ctrl msg; + unsigned int is_aon_wdt_ena; }; struct light_wdt_device *light_power_off_wdt; @@ -210,6 +212,40 @@ static const struct watchdog_ops light_watchdog_ops = { .restart = light_wdt_restart, }; +static ssize_t aon_sys_wdt_show(struct device *dev, + struct device_attribute *attr, char *buf) +{ + struct platform_device *pdev = to_platform_device(dev); + struct light_wdt_device *wdt_dev = platform_get_drvdata(pdev); + return sprintf(buf,"%u\n",wdt_dev->is_aon_wdt_ena); +} + +static ssize_t aon_sys_wdt_store(struct device *dev, + struct device_attribute *attr, + const char *buf, size_t size) +{ + struct platform_device *pdev = to_platform_device(dev); + struct light_wdt_device *wdt_dev = platform_get_drvdata(pdev); + struct light_aon_ipc *ipc; + int ret; + char *start = (char *)buf; + unsigned long val; + + ipc = wdt_dev->ipc_handle; + val = simple_strtoul(start, &start, 0); + wdt_dev->is_aon_wdt_ena = val; + if (val) + light_wdt_msg_hdr_fill(&wdt_dev->msg.hdr, LIGHT_AON_MISC_FUNC_AON_WDT_ON); + else + light_wdt_msg_hdr_fill(&wdt_dev->msg.hdr, LIGHT_AON_MISC_FUNC_AON_WDT_OFF); + ret = light_aon_call_rpc(ipc, &wdt_dev->msg, true); + if (ret){ + pr_err("%s: err:%d \n",__func__,ret); + return -EINVAL; + } + return size; +} + void light_pm_power_off(void) { struct light_wdt_device *wdt_dev = light_power_off_wdt; @@ -226,6 +262,17 @@ void light_pm_power_off(void) pr_err("failed to power off the system\n"); } + +static DEVICE_ATTR(aon_sys_wdt, 0644, aon_sys_wdt_show, aon_sys_wdt_store); + +static struct attribute *aon_sys_wdt_sysfs_entries[] = { + &dev_attr_aon_sys_wdt.attr, + NULL +}; +static const struct attribute_group dev_attr_aon_sys_wdt_group = { + .attrs = aon_sys_wdt_sysfs_entries, +}; + static int light_wdt_probe(struct platform_device *pdev) { struct device *dev = &pdev->dev; @@ -236,6 +283,7 @@ static int light_wdt_probe(struct platform_device *pdev) wdt_dev = devm_kzalloc(dev, sizeof(*wdt_dev), GFP_KERNEL); if (!wdt_dev) return -ENOMEM; + wdt_dev->is_aon_wdt_ena = 0; ret = light_aon_get_handle(&(wdt_dev->ipc_handle)); if (ret == -EPROBE_DEFER) @@ -260,6 +308,7 @@ static int light_wdt_probe(struct platform_device *pdev) watchdog_init_timeout(wdd, 0, dev); light_wdt_set_timeout(wdd, wdd->timeout); + platform_set_drvdata(pdev, wdt_dev); ret = light_wdt_is_running(wdt_dev); if (ret < 0) { pr_err("failed to get pmic wdt running state\n"); @@ -281,6 +330,12 @@ static int light_wdt_probe(struct platform_device *pdev) light_power_off_wdt = wdt_dev; + ret = sysfs_create_group(&pdev->dev.kobj, &dev_attr_aon_sys_wdt_group); + if (ret) { + dev_err(&pdev->dev, "Failed to create aon_sys_wdt sysfs.\n"); + return ret; + } + pr_info("succeed to register light pmic watchdog\n"); return 0; @@ -314,6 +369,6 @@ static int __init light_wdt_init(void) } device_initcall(light_wdt_init); -MODULE_AUTHOR("Wei.Liu "); +MODULE_AUTHOR("Wei.Liu "); MODULE_DESCRIPTION("PMIC Watchdog Driver for Light"); MODULE_LICENSE("GPL"); diff --git a/include/asm-generic/rwonce.h b/include/asm-generic/rwonce.h index a84d376f4..8d0a6280e 100644 --- a/include/asm-generic/rwonce.h +++ b/include/asm-generic/rwonce.h @@ -36,13 +36,12 @@ compiletime_assert(__native_word(t) || sizeof(t) == sizeof(long long), \ "Unsupported access size for {READ,WRITE}_ONCE().") -#define smp_mb() __asm__ __volatile__ ("fence rw, rw" : : : "memory") /* * Use __READ_ONCE() instead of READ_ONCE() if you do not require any * atomicity. Note that this may result in tears! */ #ifndef __READ_ONCE -#define __READ_ONCE(x) ({smp_mb();(*(const volatile __unqual_scalar_typeof(x) *)&(x));}) +#define __READ_ONCE(x) (*(const volatile __unqual_scalar_typeof(x) *)&(x)) #endif #define READ_ONCE(x) \ @@ -53,9 +52,7 @@ #define __WRITE_ONCE(x, val) \ do { \ - smp_mb(); \ *(volatile typeof(x) *)&(x) = (val); \ - smp_mb(); \ } while (0) #define WRITE_ONCE(x, val) \ @@ -86,7 +83,6 @@ static __no_kasan_or_inline unsigned long read_word_at_a_time(const void *addr) { kasan_check_read(addr, 1); - smp_mb(); return *(unsigned long *)addr; } diff --git a/include/dt-bindings/reset/light-reset.h b/include/dt-bindings/reset/light-reset.h new file mode 100644 index 000000000..e99470368 --- /dev/null +++ b/include/dt-bindings/reset/light-reset.h @@ -0,0 +1,14 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * Copyright (C) 2021 Alibaba, Inc. + * + * Author: zenglinghui + */ + +#ifndef DT_BINDING_RESET_LIGHT_H +#define DT_BINDING_RESET_LIGHT_H + +#define LIGHT_RESET_WDT0 0 +#define LIGHT_RESET_WDT1 1 +#endif + diff --git a/include/linux/firmware/thead/ipc.h b/include/linux/firmware/thead/ipc.h index 9410def91..7e67dfdad 100644 --- a/include/linux/firmware/thead/ipc.h +++ b/include/linux/firmware/thead/ipc.h @@ -34,6 +34,8 @@ enum light_aon_misc_func { LIGHT_AON_MISC_FUNC_WDG_RESTART = 7, LIGHT_AON_MISC_FUNC_WDG_GET_STATE = 8, LIGHT_AON_MISC_FUNC_WDG_POWER_OFF = 9, + LIGHT_AON_MISC_FUNC_AON_WDT_ON = 10, + LIGHT_AON_MISC_FUNC_AON_WDT_OFF = 11, }; enum light_aon_pm_func { diff --git a/scripts/headers_install.sh b/scripts/headers_install.sh index dd554bd43..9feac28ba 100755 --- a/scripts/headers_install.sh +++ b/scripts/headers_install.sh @@ -81,6 +81,7 @@ arch/ia64/include/uapi/asm/cmpxchg.h:CONFIG_IA64_DEBUG_CMPXCHG arch/m68k/include/uapi/asm/ptrace.h:CONFIG_COLDFIRE arch/nios2/include/uapi/asm/swab.h:CONFIG_NIOS2_CI_SWAB_NO arch/nios2/include/uapi/asm/swab.h:CONFIG_NIOS2_CI_SWAB_SUPPORT +arch/riscv/include/uapi/asm/ptrace.h:CONFIG_VLEN_256 arch/x86/include/uapi/asm/auxvec.h:CONFIG_IA32_EMULATION arch/x86/include/uapi/asm/auxvec.h:CONFIG_X86_64 arch/x86/include/uapi/asm/mman.h:CONFIG_X86_INTEL_MEMORY_PROTECTION_KEYS diff --git a/sound/soc/thead/aw87519_audio.c b/sound/soc/thead/aw87519_audio.c index 1e9d85cf9..a50d54f4d 100644 --- a/sound/soc/thead/aw87519_audio.c +++ b/sound/soc/thead/aw87519_audio.c @@ -552,9 +552,11 @@ int aw87519_hw_reset(struct aw87519 *aw87519) int aw87519_read_chipid(struct aw87519 *aw87519) { unsigned int cnt = 0; + unsigned int retry_count = 1; int ret = -1; unsigned char reg_val = 0; +retry: while (cnt < AW_READ_CHIPID_RETRIES) { aw87519_i2c_write(aw87519, 0x64, 0x2C); ret = aw87519_i2c_read(aw87519, REG_CHIPID, ®_val); @@ -565,6 +567,13 @@ int aw87519_read_chipid(struct aw87519 *aw87519) usleep_range(2500, 3000); } + if (retry_count > 0) { + aw87519_hw_reset(aw87519); + cnt = 0; + retry_count--; + goto retry; + } + return -EINVAL; } diff --git a/sound/soc/thead/light-i2s.c b/sound/soc/thead/light-i2s.c index 824bd425d..f0f3f56e4 100644 --- a/sound/soc/thead/light-i2s.c +++ b/sound/soc/thead/light-i2s.c @@ -755,6 +755,6 @@ static struct platform_driver light_i2s_driver = { module_platform_driver(light_i2s_driver); -MODULE_AUTHOR("shuofeng.ren "); +MODULE_AUTHOR("shuofeng.ren "); MODULE_DESCRIPTION("Thead Light audio driver"); MODULE_LICENSE("GPL v2");