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Linux_SDK_V1.3.3

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Signed-off-by: thead_admin <occ_thead@service.alibaba.com>
This commit is contained in:
thead_admin
2023-11-14 01:42:19 +00:00
committed by Han Gao/Revy/Rabenda
parent 2bd2eac4a7
commit e17ac7bab2
127 changed files with 6216 additions and 1379 deletions
Download Patch File Download Diff File Expand all files Collapse all files

8
arch/riscv/Kconfig
View File

@@ -44,7 +44,7 @@ config RISCV
select CLONE_BACKWARDS
select CLINT_TIMER if !MMU
select COMMON_CLK
select CPU_PM if (SUSPEND || CPU_IDLE)
select CPU_PM if CPU_IDLE
select COMPAT_BINFMT_ELF if BINFMT_ELF && COMPAT
select EDAC_SUPPORT
select DMA_DIRECT_REMAP
@@ -551,5 +551,11 @@ config ARCH_SUSPEND_POSSIBLE
endmenu
menu "CPU Power Management"
source "drivers/cpuidle/Kconfig"
endmenu
source "arch/riscv/kvm/Kconfig"
source "drivers/firmware/Kconfig"

3
arch/riscv/Kconfig.socs
View File

@@ -19,6 +19,9 @@ config SOC_VIRT
select GOLDFISH
select RTC_DRV_GOLDFISH if RTC_CLASS
select SIFIVE_PLIC
select PM_GENERIC_DOMAINS if PM
select PM_GENERIC_DOMAINS_OF if PM && OF
select RISCV_SBI_CPUIDLE if CPU_IDLE
help
This enables support for QEMU Virt Machine.

2
arch/riscv/boot/dts/thead/Makefile
View File

@@ -38,7 +38,7 @@ dtb-$(CONFIG_SOC_THEAD) += light-lpi4a.dtb light-lpi4a-ddr2G.dtb light-lpi4a-16g
dtb-$(CONFIG_SOC_THEAD) += light-lpi4a-cluster.dtb light-lpi4a-cluster-16gb.dtb
dtb-$(CONFIG_SOC_THEAD) += light-a-ref.dtb light-a-ref-dsi0.dtb light-a-ref-dsi0-hdmi.dtb
dtb-$(CONFIG_SOC_THEAD) += light-b-ref.dtb
dtb-$(CONFIG_SOC_THEAD) += light-a-val-crash.dtb light-b-product-crash.dtb light-ant-ref-crash.dtb light-ant-discrete-crash.dtb
dtb-$(CONFIG_SOC_THEAD) += light-a-val-crash.dtb light-b-product-crash.dtb light-ant-ref-crash.dtb light-ant-discrete-crash.dtb light-lpi4a-crash.dtb light-lpi4a-camera-tuning.dtb light-lpi4a-hdmi.dtb
dtb-$(CONFIG_SOC_THEAD) += light-b-power.dtb
dtb-$(CONFIG_SOC_THEAD) += light-a-val-android.dtb

9
arch/riscv/boot/dts/thead/fire-crash.dts
View File

@@ -306,15 +306,6 @@
pagesize = <32>;
};
codec: wm8960@1a {
#sound-dai-cells = <0>;
compatible = "wlf,wm8960";
reg = <0x1a>;
wlf,shared-lrclk;
wlf,hp-cfg = <3 2 3>;
wlf,gpio-cfg = <1 3>;
};
touch@5d {
#gpio-cells = <2>;
compatible = "goodix,gt911";

9
arch/riscv/boot/dts/thead/fire-emu.dts
View File

@@ -311,15 +311,6 @@
pagesize = <32>;
};
codec: wm8960@1a {
#sound-dai-cells = <0>;
compatible = "wlf,wm8960";
reg = <0x1a>;
wlf,shared-lrclk;
wlf,hp-cfg = <3 2 3>;
wlf,gpio-cfg = <1 3>;
};
touch@5d {
#gpio-cells = <2>;
compatible = "goodix,gt911";

17
arch/riscv/boot/dts/thead/light-a-product.dts
View File

@@ -162,6 +162,14 @@
iopmp_dsp1: IOPMP_DSP1 {
is_default_region;
};
iopmp_audio0: IOPMP_AUDIO0 {
is_default_region;
};
iopmp_audio1: IOPMP_AUDIO1 {
is_default_region;
};
};
mbox_910t_client1: mbox_910t_client1 {
@@ -517,15 +525,6 @@
pagesize = <32>;
};
codec: wm8960@1a {
#sound-dai-cells = <0>;
compatible = "wlf,wm8960";
reg = <0x1a>;
wlf,shared-lrclk;
wlf,hp-cfg = <3 2 3>;
wlf,gpio-cfg = <1 3>;
};
touch@5d {
#gpio-cells = <2>;
compatible = "goodix,gt911";

67
arch/riscv/boot/dts/thead/light-a-val-android.dts
View File

@@ -30,45 +30,54 @@
&lightsound {
status = "okay";
simple-audio-card,widgets =
"Microphone", "Mic Jack",
"Speaker", "Speaker",
"Headphone", "Headphone Jack";
simple-audio-card,routing =
"Headphone Jack", "HP_L",
"Headphone Jack", "HP_R",
"Speaker", "SPK_LP",
"Speaker", "SPK_LN",
"Speaker", "SPK_RP",
"Speaker", "SPK_RN",
"Mic Jack","MICB",
"LINPUT1", "Mic Jack",
"LINPUT3", "Mic Jack";
simple-audio-card,dai-link@0 { /* I2S - CODEC */
reg = <0>;
format = "i2s";
cpu {
sound-dai = <&light_i2s 0>;
};
codec {
sound-dai = <&codec>;
};
};
simple-audio-card,dai-link@1 { /* I2S - HDMI */
simple-audio-card,dai-link@0 { /* I2S - AUDIO SYS CODEC 8156*/
reg = <0>;
format = "i2s";
cpu {
sound-dai = <&i2s0 0>;
};
codec {
sound-dai = <&es8156_audio_codec>;
};
};
simple-audio-card,dai-link@1 { /* I2S - AUDIO SYS CODEC 7210*/
reg = <1>;
format = "i2s";
cpu {
sound-dai = <&light_i2s 1>;
sound-dai = <&i2s_8ch_sd2 2>;
};
codec {
sound-dai = <&dummy_codec>;
sound-dai = <&es7210_audio_codec_adc0>;
};
};
};
simple-audio-card,dai-link@2 { /* I2S - HDMI */
reg = <2>;
format = "i2s";
cpu {
sound-dai = <&light_i2s 1>;
};
codec {
sound-dai = <&dummy_codec>;
};
};
};
&light_i2s {
status = "okay";
};
&i2s0 {
status = "okay";
};
&i2s_8ch_sd2 {
status = "okay";
};
&es7210_audio_codec_adc0 {
status = "okay";
};

3
arch/riscv/boot/dts/thead/light-a-val-sec.dts
View File

@@ -15,3 +15,6 @@
status = "disabled";
};
&eip_28 {
status = "disabled";
};

264
arch/riscv/boot/dts/thead/light-a-val.dts
View File

@@ -16,7 +16,7 @@
chosen {
bootargs = "console=ttyS0,115200 crashkernel=256M-:128M earlycon clk_ignore_unused sram=0xffe0000000,0x180000";
stdout-path = "serial0:115200n8";
stdout-path = "serial0";
};
leds {
@@ -165,6 +165,14 @@
iopmp_dsp1: IOPMP_DSP1 {
is_default_region;
};
iopmp_audio0: IOPMP_AUDIO0 {
is_default_region;
};
iopmp_audio1: IOPMP_AUDIO1 {
is_default_region;
};
};
mbox_910t_client1: mbox_910t_client1 {
@@ -322,12 +330,14 @@
status = "disabled";
key-volumedown {
label = "Volume Down Key";
wakeup-source;
linux,code = <KEY_1>;
debounce-interval = <2>;
gpios = <&ao_gpio_porta 4 GPIO_ACTIVE_LOW>;
};
key-volumeup {
label = "Volume Up Key";
wakeup-source;
linux,code = <KEY_2>;
debounce-interval = <2>;
gpios = <&ao_gpio_porta 5 GPIO_ACTIVE_LOW>;
@@ -564,22 +574,14 @@
&i2c0 {
clock-frequency = <400000>;
status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_i2c0>;
eeprom@50 {
compatible = "atmel,24c32";
reg = <0x50>;
pagesize = <32>;
};
codec: wm8960@1a {
#sound-dai-cells = <0>;
compatible = "wlf,wm8960";
reg = <0x1a>;
wlf,shared-lrclk;
wlf,hp-cfg = <3 2 3>;
wlf,gpio-cfg = <1 3>;
};
touch@5d {
#gpio-cells = <2>;
compatible = "goodix,gt911";
@@ -671,6 +673,8 @@
&i2c1 {
clock-frequency = <400000>;
status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_i2c1>;
touch1@5d {
#gpio-cells = <2>;
compatible = "goodix,gt911";
@@ -689,9 +693,9 @@
num-cs = <1>;
cs-gpios = <&gpio2_porta 15 0>; // GPIO_ACTIVE_HIGH: 0
rx-sample-delay-ns = <10>;
status = "okay";
spi_norflash@0 {
status = "okay";
#address-cells = <1>;
#size-cells = <1>;
compatible = "winbond,w25q64jwm", "jedec,spi-nor";
@@ -701,6 +705,7 @@
};
spidev@1 {
status = "disable";
compatible = "spidev";
#address-cells = <0x1>;
#size-cells = <0x1>;
@@ -711,13 +716,30 @@
&uart0 {
clock-frequency = <100000000>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart0>;
};
&uart1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart1>;
};
&uart3 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart3>;
};
&uart4 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart4>;
};
&qspi0 {
num-cs = <1>;
cs-gpios = <&gpio2_porta 3 0>;
rx-sample-dly = <4>;
status = "disabled";
rx-sample-dly = <5>;
status = "okay";
spi-flash@0 {
#address-cells = <1>;
@@ -738,7 +760,8 @@
&qspi1 {
num-cs = <1>;
cs-gpios = <&gpio0_porta 1 0>;
status = "disabled";
rx-sample-dly = <5>;
status = "okay";
spi-flash@0 {
#address-cells = <1>;
@@ -761,6 +784,8 @@
rx-clk-delay = <0x00>; /* for RGMII */
tx-clk-delay = <0x00>; /* for RGMII */
phy-handle = <&phy_88E1111_0>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_gmac0>;
status = "okay";
mdio0 {
@@ -783,6 +808,8 @@
rx-clk-delay = <0x00>; /* for RGMII */
tx-clk-delay = <0x00>; /* for RGMII */
phy-handle = <&phy_88E1111_1>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_gmac1>;
status = "okay";
};
@@ -804,6 +831,8 @@
bus-width = <4>;
pull_up;
wprtn_ignore;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_sdio0>;
status = "okay";
};
@@ -832,17 +861,8 @@
*/
pinctrl_uart0: uart0grp {
thead,pins = <
FM_UART0_TXD 0x0 0x72
FM_UART0_RXD 0x0 0x72
>;
};
pinctrl_spi0: spi0grp {
thead,pins = <
FM_SPI_CSN 0x3 0x20a
FM_SPI_SCLK 0x0 0x20a
FM_SPI_MISO 0x0 0x23a
FM_SPI_MOSI 0x0 0x23a
FM_UART0_TXD 0x0 0x234
FM_UART0_RXD 0x0 0x234
>;
};
@@ -870,12 +890,87 @@
>;
};
pinctrl_i2c2: i2c2grp {
thead,pins = <
FM_I2C2_SCL 0x0 0x204
FM_I2C2_SDA 0x0 0x204
>;
};
pinctrl_i2c3: i2c3grp {
thead,pins = <
FM_I2C3_SCL 0x0 0x204
FM_I2C3_SDA 0x0 0x204
>;
};
pinctrl_spi0: spi0grp {
thead,pins = <
FM_SPI_CSN 0x3 0x20a
FM_SPI_SCLK 0x0 0x20a
FM_SPI_MISO 0x0 0x23a
FM_SPI_MOSI 0x0 0x23a
>;
};
pinctrl_gmac1: gmac1grp {
thead,pins = <
FM_GPIO2_18 0x1 0x20f /* GMAC1_TX_CLK */
FM_GPIO2_19 0x1 0x20f /* GMAC1_RX_CLK */
FM_GPIO2_20 0x1 0x20f /* GMAC1_TXEN */
FM_GPIO2_21 0x1 0x20f /* GMAC1_TXD0 */
FM_GPIO2_22 0x1 0x20f /* GMAC1_TXD1 */
FM_GPIO2_23 0x1 0x20f /* GMAC1_TXD2 */
FM_GPIO2_24 0x1 0x20f /* GMAC1_TXD3 */
FM_GPIO2_25 0x1 0x20f /* GMAC1_RXDV */
FM_GPIO2_30 0x1 0x20f /* GMAC1_RXD0 */
FM_GPIO2_31 0x1 0x20f /* GMAC1_RXD1 */
FM_GPIO3_0 0x1 0x20f /* GMAC1_RXD2 */
FM_GPIO3_1 0x1 0x20f /* GMAC1_RXD3 */
>;
};
pinctrl_sdio0: sdio0grp {
thead,pins = <
FM_SDIO0_DETN 0x0 0x208
>;
};
pinctrl_pwm: pwmgrp {
thead,pins = <
FM_GPIO3_2 0x1 0x208 /* pwm0 */
FM_GPIO3_3 0x1 0x208 /* pwm1 */
>;
};
pinctrl_hdmi: hdmigrp {
thead,pins = <
FM_HDMI_SCL 0x0 0x208
FM_HDMI_SDA 0x0 0x208
FM_HDMI_CEC 0x0 0x208
>;
};
pinctrl_gmac0: gmac0grp {
thead,pins = <
FM_GMAC0_TX_CLK 0x0 0x20f /* GMAC0_TX_CLK */
FM_GMAC0_RX_CLK 0x0 0x20f /* GMAC0_RX_CLK */
FM_GMAC0_TXEN 0x0 0x20f /* GMAC0_TXEN */
FM_GMAC0_TXD0 0x0 0x20f /* GMAC0_TXD0 */
FM_GMAC0_TXD1 0x0 0x20f /* GMAC0_TXD1 */
FM_GMAC0_TXD2 0x0 0x20f /* GMAC0_TXD2 */
FM_GMAC0_TXD3 0x0 0x20f /* GMAC0_TXD3 */
FM_GMAC0_RXDV 0x0 0x20f /* GMAC0_RXDV */
FM_GMAC0_RXD0 0x0 0x20f /* GMAC0_RXD0 */
FM_GMAC0_RXD1 0x0 0x20f /* GMAC0_RXD1 */
FM_GMAC0_RXD2 0x0 0x20f /* GMAC0_RXD2 */
FM_GMAC0_RXD3 0x0 0x20f /* GMAC0_RXD3 */
FM_GMAC0_MDC 0x0 0x208 /* GMAC0_MDC */
FM_GMAC0_MDIO 0x0 0x208 /* GMAC0_MDIO */
FM_GMAC0_COL 0x3 0x232 /* PHY0_nRST */
FM_GMAC0_CRS 0x3 0x232 /* PHY0_nINT */
>;
};
};
};
@@ -885,22 +980,6 @@
* Pin Configuration Node:
* Format: <pin_id mux_node config>
*/
pinctrl_uart3: uart3grp {
thead,pins = <
FM_UART3_TXD 0x0 0x72
FM_UART3_RXD 0x0 0x72
>;
};
pinctrl_uart4: uart4grp {
thead,pins = <
FM_UART4_TXD 0x0 0x72
FM_UART4_RXD 0x0 0x72
FM_UART4_CTSN 0x0 0x72
FM_UART4_RTSN 0x0 0x72
>;
};
pinctrl_qspi1: qspi1grp {
thead,pins = <
FM_QSPI1_SCLK 0x0 0x20a
@@ -912,7 +991,6 @@
>;
};
pinctrl_iso7816: iso7816grp {
thead,pins = <
FM_QSPI1_SCLK 0x1 0x208
@@ -923,6 +1001,51 @@
>;
};
pinctrl_i2c0: i2c0grp {
thead,pins = <
FM_I2C0_SCL 0x0 0x204
FM_I2C0_SDA 0x0 0x204
>;
};
pinctrl_i2c1: i2c1grp {
thead,pins = <
FM_I2C1_SCL 0x0 0x204
FM_I2C1_SDA 0x0 0x204
>;
};
pinctrl_uart1: uart1grp {
thead,pins = <
FM_UART1_TXD 0x0 0x234
FM_UART1_RXD 0x0 0x234
>;
};
pinctrl_uart4: uart4grp {
thead,pins = <
FM_UART4_TXD 0x0 0x208
FM_UART4_RXD 0x0 0x208
FM_UART4_CTSN 0x0 0x208
FM_UART4_RTSN 0x0 0x208
>;
};
pinctrl_uart3: uart3grp {
thead,pins = <
FM_UART3_TXD 0x1 0x202
FM_UART3_RXD 0x1 0x202
FM_GPIO0_20 0x2 0x202 /* UART3_IR_OUT */
FM_GPIO0_21 0x2 0x202 /* UART3_IR_IN */
>;
};
pinctrl_i2c4: i2c4grp {
thead,pins = <
FM_GPIO0_18 0x1 0x204 /* I2C4_SCL */
FM_GPIO0_19 0x1 0x204 /* I2C4_SDA */
>;
};
};
};
@@ -1086,6 +1209,8 @@
&i2c2 {
clock-frequency = <400000>;
status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_i2c2>;
eeprom@50 {
compatible = "atmel,24c32";
reg = <0x50>;
@@ -1096,6 +1221,8 @@
&i2c3 {
clock-frequency = <400000>;
status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_i2c3>;
eeprom@50 {
compatible = "atmel,24c32";
reg = <0x50>;
@@ -1106,6 +1233,8 @@
&i2c4 {
clock-frequency = <400000>;
status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_i2c4>;
eeprom@50 {
compatible = "atmel,24c32";
reg = <0x50>;
@@ -1328,7 +1457,7 @@
DOVDD18_RGB-supply = <&soc_dovdd18_rgb_reg>;
DVDD12_RGB-supply = <&soc_dvdd12_rgb_reg>;
AVDD28_RGB-supply = <&soc_avdd28_rgb_reg>;
i2c_reg_width = /bits/ 8 <2>;
i2c_reg_width = /bits/ 8 <2>;
i2c_data_width = /bits/ 8 <1>;
i2c_addr = /bits/ 8 <0x1a>;
i2c_bus = /bits/ 8 <3>;
@@ -1336,6 +1465,7 @@
};
&video0{
status = "okay";
vi_mem_pool_region = <2>; // vi_mem: framebuffer, region[2]
channel0 {
sensor0 {
@@ -1422,6 +1552,7 @@
&video1{
status = "okay";
vi_mem_pool_region = <2>; // vi_mem: framebuffer, region[2]
channel0 {
sensor0 {
@@ -1525,6 +1656,7 @@
};
&video2{
status = "okay";
vi_mem_pool_region = <0>; // vi_mem: framebuffer, region[0]
channel0 {
sensor0 {
@@ -1617,6 +1749,7 @@
};
&video3{
status = "okay";
vi_mem_pool_region = <0>; // vi_mem: framebuffer, region[0]
channel0 {
sensor0 {
@@ -1720,6 +1853,7 @@
};
&video4{
status = "okay";
vi_mem_pool_region = <0>; // vi_mem: framebuffer, region[0]
channel0 {
sensor0 {
@@ -1871,6 +2005,7 @@
};
&video5{
status = "okay";
vi_mem_pool_region = <0>; // vi_mem: framebuffer, region[0]
channel0 {
sensor0 {
@@ -2040,6 +2175,7 @@
};
&video6{
status = "okay";
vi_mem_pool_region = <1>; // vi_mem: framebuffer, region[1]
channel0 {
sensor0 {
@@ -2080,6 +2216,7 @@
};
&video7{
status = "okay";
channel0 {
sensor0 {
subdev_name = "vivcam";
@@ -2249,6 +2386,7 @@
&video8{
status = "okay";
vi_mem_pool_region = <1>; // vi_mem: framebuffer, region[1]
channel0 {
sensor0 {
@@ -2280,6 +2418,7 @@
};
&video9{
status = "okay";
channel0 {
sensor0 {
subdev_name = "vivcam";
@@ -2301,6 +2440,7 @@
&video10{
status = "okay";
channel0 {
sensor0 {
subdev_name = "vivcam";
@@ -2322,6 +2462,7 @@
};
&video11{
status = "okay";
channel0 {
channel_id = <0>;
status = "okay";
@@ -2348,6 +2489,7 @@
};
&video12{ // TUNINGTOOL
status = "okay";
channel0 { // CSI2
sensor0 {
subdev_name = "vivcam";
@@ -2368,6 +2510,35 @@
};
};
&video15{
status = "okay";
vi_mem_pool_region = <0>;
channel0 {
channel_id = <0>;
status = "okay";
sensor0 {
subdev_name = "vivcam";
idx = <0>; //<0>=vivcam0 :2310
csi_idx = <0>; //<0>=CSI2
flash_led_idx = <0>;
mode_idx = <1>;
path_type = "SENSOR_1920X1088_26FPS_RAW12_LINER";
};
sensor1 {
subdev_name = "vivcam";
idx = <7>; //imx334
csi_idx = <0>; //<0>=CSI2
mode_idx = <0>;
path_type = "SENSOR_3840x2180_RAW12_LINER";
};
dma {
subdev_name = "vipre";
idx = <0>;
path_type = "VIPRE_CSI0_DDR";
};
};
};
&trng {
status = "disabled";
};
@@ -2513,3 +2684,8 @@
>;
};
};
&hdmi_tx {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_hdmi>;
};

11
arch/riscv/boot/dts/thead/light-ant-ref.dts
View File

@@ -166,6 +166,14 @@
iopmp_dsp1: IOPMP_DSP1 {
is_default_region;
};
iopmp_audio0: IOPMP_AUDIO0 {
is_default_region;
};
iopmp_audio1: IOPMP_AUDIO1 {
is_default_region;
};
};
mbox_910t_client1: mbox_910t_client1 {
@@ -2271,6 +2279,9 @@
&hdmi_tx {
status = "okay";
max_width = /bits/ 16 <1280>;
max_height = /bits/ 16 <720>;
port@0 {
/* input */
hdmi_tx_in: endpoint {

10
arch/riscv/boot/dts/thead/light-b-audio-hdmi.dts
View File

@@ -166,6 +166,14 @@
iopmp_dsp1: IOPMP_DSP1 {
is_default_region;
};
iopmp_audio0: IOPMP_AUDIO0 {
is_default_region;
};
iopmp_audio1: IOPMP_AUDIO1 {
is_default_region;
};
};
mbox_910t_client1: mbox_910t_client1 {
@@ -258,12 +266,14 @@
pinctrl-names = "default";
key-volumedown {
label = "Volume Down Key";
wakeup-source;
linux,code = <KEY_VOLUMEDOWN>;
debounce-interval = <1>;
gpios = <&ao_gpio_porta 11 0x1>;
};
key-volumeup {
label = "Volume Up Key";
wakeup-source;
linux,code = <KEY_VOLUMEUP>;
debounce-interval = <1>;
gpios = <&ao_gpio_porta 10 0x1>;

219
arch/riscv/boot/dts/thead/light-b-product.dts
View File

@@ -166,6 +166,14 @@
iopmp_dsp1: IOPMP_DSP1 {
is_default_region;
};
iopmp_audio0: IOPMP_AUDIO0 {
is_default_region;
};
iopmp_audio1: IOPMP_AUDIO1 {
is_default_region;
};
};
mbox_910t_client1: mbox_910t_client1 {
@@ -239,6 +247,7 @@
ref-clock-frequency = <24000000>;
keep_wifi_power_on;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_wifi>;
wifi_chip_type = "rtl8723ds";
WIFI,poweren_gpio = <&gpio2_porta 29 0>;
WIFI,reset_n = <&gpio2_porta 24 0>;
@@ -247,7 +256,8 @@
wcn_bt: wireless-bluetooth {
compatible = "bluetooth-platdata";
pinctrl-names = "default", "rts_gpio";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_bt>;
BT,power_gpio = <&gpio2_porta 25 0>;
status = "okay";
};
@@ -258,12 +268,14 @@
pinctrl-names = "default";
key-volumedown {
label = "Volume Down Key";
wakeup-source;
linux,code = <KEY_VOLUMEDOWN>;
debounce-interval = <1>;
gpios = <&ao_gpio_porta 11 0x1>;
};
key-volumeup {
label = "Volume Up Key";
wakeup-source;
linux,code = <KEY_VOLUMEUP>;
debounce-interval = <1>;
gpios = <&ao_gpio_porta 10 0x1>;
@@ -699,6 +711,23 @@
&uart0 {
clock-frequency = <100000000>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart0>;
};
&uart1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart1>;
};
&uart3 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart3>;
};
&uart4 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart4>;
};
&qspi0 {
@@ -744,6 +773,8 @@
tx-clk-delay = <0x00>; /* for RGMII */
phy-handle = <&phy_88E1111_0>;
status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_gmac0>;
mdio0 {
#address-cells = <1>;
@@ -787,6 +818,8 @@
pull_up;
wprtn_ignore;
status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_sdio0>;
};
&sdhci1 {
@@ -814,17 +847,8 @@
*/
pinctrl_uart0: uart0grp {
thead,pins = <
FM_UART0_TXD 0x0 0x72
FM_UART0_RXD 0x0 0x72
>;
};
pinctrl_spi0: spi0grp {
thead,pins = <
FM_SPI_CSN 0x3 0x20a
FM_SPI_SCLK 0x0 0x20a
FM_SPI_MISO 0x0 0x23a
FM_SPI_MOSI 0x0 0x23a
FM_UART0_TXD 0x0 0x234
FM_UART0_RXD 0x0 0x234
>;
};
@@ -852,9 +876,81 @@
>;
};
pinctrl_i2c2: i2c2grp {
thead,pins = <
FM_I2C2_SCL 0x0 0x204
FM_I2C2_SDA 0x0 0x204
>;
};
pinctrl_i2c3: i2c3grp {
thead,pins = <
FM_I2C3_SCL 0x0 0x204
FM_I2C3_SDA 0x0 0x204
>;
};
pinctrl_spi0: spi0grp {
thead,pins = <
FM_SPI_CSN 0x3 0x20a
FM_SPI_SCLK 0x0 0x20a
FM_SPI_MISO 0x0 0x23a
FM_SPI_MOSI 0x0 0x23a
>;
};
pinctrl_wifi: wifi_grp {
thead,pins = <
FM_GPIO2_22 0x0 0x202
FM_GPIO2_24 0x0 0x202
>;
};
pinctrl_bt: bt_grp {
thead,pins = <
FM_GPIO2_23 0x0 0x202
FM_GPIO2_25 0x0 0x202
>;
};
pinctrl_sdio0: sdio0grp {
thead,pins = <
FM_SDIO0_DETN 0x0 0x208
>;
};
pinctrl_pwm: pwmgrp {
thead,pins = <
FM_GPIO3_2 0x1 0x208 /* pwm0 */
FM_GPIO3_2 0x1 0x20f /* pwm0 */
>;
};
pinctrl_hdmi: hdmigrp {
thead,pins = <
FM_HDMI_SCL 0x0 0x208
FM_HDMI_SDA 0x0 0x208
FM_HDMI_CEC 0x0 0x208
>;
};
pinctrl_gmac0: gmac0grp {
thead,pins = <
FM_GMAC0_TX_CLK 0x0 0x20f /* GMAC0_TX_CLK */
FM_GMAC0_RX_CLK 0x0 0x20f /* GMAC0_RX_CLK */
FM_GMAC0_TXEN 0x0 0x20f /* GMAC0_TXEN */
FM_GMAC0_TXD0 0x0 0x20f /* GMAC0_TXD0 */
FM_GMAC0_TXD1 0x0 0x20f /* GMAC0_TXD1 */
FM_GMAC0_TXD2 0x0 0x20f /* GMAC0_TXD2 */
FM_GMAC0_TXD3 0x0 0x20f /* GMAC0_TXD3 */
FM_GMAC0_RXDV 0x0 0x20f /* GMAC0_RXDV */
FM_GMAC0_RXD0 0x0 0x20f /* GMAC0_RXD0 */
FM_GMAC0_RXD1 0x0 0x20f /* GMAC0_RXD1 */
FM_GMAC0_RXD2 0x0 0x20f /* GMAC0_RXD2 */
FM_GMAC0_RXD3 0x0 0x20f /* GMAC0_RXD3 */
FM_GMAC0_MDC 0x0 0x208 /* GMAC0_MDC */
FM_GMAC0_MDIO 0x0 0x208 /* GMAC0_MDIO */
FM_GMAC0_COL 0x3 0x232 /* PHY0_nRST */
FM_GMAC0_CRS 0x3 0x232 /* PHY0_nINT */
>;
};
};
@@ -866,22 +962,6 @@
* Pin Configuration Node:
* Format: <pin_id mux_node config>
*/
pinctrl_uart3: uart3grp {
thead,pins = <
FM_UART3_TXD 0x0 0x72
FM_UART3_RXD 0x0 0x72
>;
};
pinctrl_uart4: uart4grp {
thead,pins = <
FM_UART4_TXD 0x0 0x72
FM_UART4_RXD 0x0 0x72
FM_UART4_CTSN 0x0 0x72
FM_UART4_RTSN 0x0 0x72
>;
};
pinctrl_qspi1: qspi1grp {
thead,pins = <
FM_QSPI1_SCLK 0x0 0x20a
@@ -893,7 +973,6 @@
>;
};
pinctrl_iso7816: iso7816grp {
thead,pins = <
FM_QSPI1_SCLK 0x1 0x208
@@ -904,6 +983,49 @@
>;
};
pinctrl_i2c0: i2c0grp {
thead,pins = <
FM_I2C0_SCL 0x0 0x204
FM_I2C0_SDA 0x0 0x204
>;
};
pinctrl_i2c1: i2c1grp {
thead,pins = <
FM_I2C1_SCL 0x0 0x204
FM_I2C1_SDA 0x0 0x204
>;
};
pinctrl_uart1: uart1grp {
thead,pins = <
FM_UART1_TXD 0x0 0x234
FM_UART1_RXD 0x0 0x234
>;
};
pinctrl_uart4: uart4grp {
thead,pins = <
FM_UART4_TXD 0x0 0x208
FM_UART4_RXD 0x0 0x208
FM_UART4_CTSN 0x0 0x208
FM_UART4_RTSN 0x0 0x208
>;
};
pinctrl_uart3: uart3grp {
thead,pins = <
FM_UART3_TXD 0x1 0x202
FM_UART3_RXD 0x1 0x202
>;
};
pinctrl_i2c4: i2c4grp {
thead,pins = <
FM_GPIO0_18 0x1 0x204 /* I2C4_SCL */
FM_GPIO0_19 0x1 0x204 /* I2C4_SDA */
>;
};
};
};
@@ -1014,26 +1136,36 @@
&i2c0 {
clock-frequency = <400000>;
status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_i2c0>;
};
&i2c1 {
clock-frequency = <400000>;
status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_i2c1>;
};
&i2c2 {
clock-frequency = <400000>;
status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_i2c2>;
};
&i2c3 {
clock-frequency = <400000>;
status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_i2c3>;
};
&i2c4 {
clock-frequency = <400000>;
status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_i2c4>;
};
&isp0 {
@@ -1240,6 +1372,7 @@
};
&video0{
status = "okay";
vi_mem_pool_region = <2>; // vi_mem: framebuffer, region[2]
channel0 {
sensor0 {
@@ -1326,6 +1459,7 @@
&video1{
status = "okay";
vi_mem_pool_region = <2>; // vi_mem: framebuffer, region[2]
channel0 {
sensor0 {
@@ -1429,6 +1563,7 @@
};
&video2{
status = "okay";
vi_mem_pool_region = <0>; // vi_mem: framebuffer, region[0]
channel0 {
sensor0 {
@@ -1445,20 +1580,13 @@
mode_idx = <0>;
path_type = "SENSOR_1600x1200_RAW10_LINER";
};
sensor2 {
subdev_name = "vivcam";
idx = <7>; //imx334
csi_idx = <0>; //<0>=CSI2
mode_idx = <0>;
path_type = "SENSOR_3840x2180_RAW12_LINER";
};
isp {
subdev_name = "isp";
idx = <1>;
path_type = "ISP_MI_PATH_MP";
output {
max_width = <3840>;
max_height = <2180>;
max_width = <1920>;
max_height = <1088>;
bit_per_pixel = <16>;
frame_count = <3>;
};
@@ -1521,6 +1649,7 @@
};
&video3{
status = "okay";
vi_mem_pool_region = <0>; // vi_mem: framebuffer, region[0]
channel0 {
sensor0 {
@@ -1624,6 +1753,7 @@
};
&video4{
status = "okay";
vi_mem_pool_region = <0>; // vi_mem: framebuffer, region[0]
channel0 {
sensor0 {
@@ -1775,6 +1905,7 @@
};
&video5{
status = "okay";
vi_mem_pool_region = <0>; // vi_mem: framebuffer, region[0]
channel0 {
sensor0 {
@@ -1944,6 +2075,7 @@
};
&video6{
status = "okay";
vi_mem_pool_region = <1>; // vi_mem: framebuffer, region[1]
channel0 {
sensor0 {
@@ -1985,6 +2117,7 @@
};
&video7{
status = "okay";
channel0 {
sensor0 {
subdev_name = "vivcam";
@@ -2154,6 +2287,7 @@
&video8{
status = "okay";
vi_mem_pool_region = <1>; // vi_mem: framebuffer, region[1]
channel0 {
sensor0 {
@@ -2185,6 +2319,7 @@
};
&video9{
status = "okay";
channel0 {
sensor0 {
subdev_name = "vivcam";
@@ -2206,6 +2341,7 @@
&video10{ // TUNINGTOOL
status = "okay";
channel0 {
sensor0 {
subdev_name = "vivcam";
@@ -2227,6 +2363,7 @@
};
&video11{
status = "okay";
channel0 {
channel_id = <0>;
status = "okay";
@@ -2253,6 +2390,7 @@
};
&video12{ // TUNINGTOOL
status = "okay";
channel0 { // CSI2
sensor0 {
subdev_name = "vivcam";
@@ -2274,6 +2412,7 @@
};
&video14{
status = "okay";
vi_mem_pool_region = <2>; // vi_mem: framebuffer, region[0]
status = "okay";
channel0 {
@@ -2440,6 +2579,8 @@
&hdmi_tx {
status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_hdmi>;
port@0 {
/* input */

8
arch/riscv/boot/dts/thead/light-beagle-ref.dts
View File

@@ -194,6 +194,14 @@
iopmp_dsp1: IOPMP_DSP1 {
is_default_region;
};
iopmp_audio0: IOPMP_AUDIO0 {
is_default_region;
};
iopmp_audio1: IOPMP_AUDIO1 {
is_default_region;
};
};
mbox_910t_client1: mbox_910t_client1 {

8
arch/riscv/boot/dts/thead/light-crash.dts
View File

@@ -163,6 +163,14 @@
iopmp_dsp1: IOPMP_DSP1 {
is_default_region;
};
iopmp_audio0: IOPMP_AUDIO0 {
is_default_region;
};
iopmp_audio1: IOPMP_AUDIO1 {
is_default_region;
};
};
mbox_910t_client1: mbox_910t_client1 {

53
arch/riscv/boot/dts/thead/light-lpi4a-camera-tuning.dts Normal file
View File

@@ -0,0 +1,53 @@
/* SPDX-License-Identifier: GPL-2.0 */
/*
* Copyright (C) 2021 Alibaba Group Holding Limited.
*/
/dts-v1/;
#include "light-lpi4a.dts"
&video10{ // TUNINGTOOL
status = "okay";
channel0 {
sensor1 {
subdev_name = "vivcam";
idx = <3>;
csi_idx = <0>;
mode_idx = <1>; // 0=640 480 1=2592x1944
path_type = "SENSOR_2592x1944_LINER";
};
dma {
path_type = "VIPRE_CSI0_ISP0";
};
};
};
&video15{
status = "okay";
vi_mem_pool_region = <0>; // vi_mem: framebuffer, region[0]
channel0 {
status = "okay";
sensor0 {
subdev_name = "vivcam";
idx = <0>;
csi_idx = <0>;
mode_idx = <0>;
path_type = "SENSOR_VGA_RAW12_LINER";
};
sensor1 {
subdev_name = "vivcam";
idx = <3>;
csi_idx = <0>;
mode_idx = <1>;
path_type = "SENSOR_2592x1944_LINER";
};
dma {
subdev_name = "vipre";
idx = <0>;
path_type = "VIPRE_CSI0_DDR";
};
};
};

98
arch/riscv/boot/dts/thead/light-lpi4a-crash.dts Normal file
View File

@@ -0,0 +1,98 @@
/* SPDX-License-Identifier: GPL-2.0 */
/*
* Copyright (C) 2023 Alibaba Group Holding Limited.
*/
#include "light-crash.dts"
&aon {
aon_reg_dialog: light-dialog-reg {
compatible = "thead,light-dialog-pmic-ant";
status = "okay";
dvdd_cpu_reg: appcpu_dvdd {
regulator-name = "appcpu_dvdd";
regulator-min-microvolt = <300000>;
regulator-max-microvolt = <1570000>;
regulator-boot-on;
regulator-always-on;
};
dvddm_cpu_reg: appcpu_dvddm {
regulator-name = "appcpu_dvddm";
regulator-min-microvolt = <300000>;
regulator-max-microvolt = <1570000>;
regulator-boot-on;
regulator-always-on;
};
};
};
&cpus {
c910_0: cpu@0 {
operating-points = <
/* kHz uV */
300000 600000
800000 700000
1500000 800000
1848000 1000000
>;
light,dvddm-operating-points = <
/* kHz uV */
300000 800000
800000 800000
1500000 800000
1848000 1000000
>;
};
c910_1: cpu@1 {
operating-points = <
/* kHz uV */
300000 600000
800000 700000
1500000 800000
1848000 1000000
>;
light,dvddm-operating-points = <
/* kHz uV */
300000 800000
800000 800000
1500000 800000
1848000 1000000
>;
};
c910_2: cpu@2 {
operating-points = <
/* kHz uV */
300000 600000
800000 700000
1500000 800000
1848000 1000000
>;
light,dvddm-operating-points = <
/* kHz uV */
300000 800000
800000 800000
1500000 800000
1848000 1000000
>;
};
c910_3: cpu@3 {
operating-points = <
/* kHz uV */
300000 600000
800000 700000
1500000 800000
1848000 1000000
>;
light,dvddm-operating-points = <
/* kHz uV */
300000 800000
800000 800000
1500000 800000
1848000 1000000
>;
};
};

50
arch/riscv/boot/dts/thead/light-lpi4a-hdmi.dts Normal file
View File

@@ -0,0 +1,50 @@
/* SPDX-License-Identifier: GPL-2.0 */
/*
* Copyright (C) 2021 Alibaba Group Holding Limited.
*/
/dts-v1/;
#include "light-lpi4a.dts"
&lightsound {
status = "okay";
simple-audio-card,dai-link@0 { /* I2S - HDMI*/
reg = <0>;
format = "i2s";
cpu {
sound-dai = <&light_i2s 1>;
};
codec {
sound-dai = <&dummy_codec>;
};
};
simple-audio-card,dai-link@1 { /* I2S - AUDIO SYS CODEC 7210*/
reg = <1>;
format = "i2s";
cpu {
sound-dai = <&i2s1 0>;
};
codec {
sound-dai = <&es7210_audio_codec>;
};
};
simple-audio-card,dai-link@2 { /* I2S - AUDIO SYS CODEC 8156*/
reg = <2>;
format = "i2s";
cpu {
sound-dai = <&i2s1 0>;
};
codec {
sound-dai = <&es8156_audio_codec>;
};
};
};
&dpu_enc0 {
status = "disabled";
};
&dsi0 {
status = "disabled";
};

60
arch/riscv/boot/dts/thead/light-lpi4a-hx8279.dts Normal file
View File

@@ -0,0 +1,60 @@
/* SPDX-License-Identifier: GPL-2.0 */
/*
* Copyright (C) 2022-2023 Alibaba Group Holding Limited.
*/
#include "light-lpi4a-ref.dts"
/ {
model = "T-HEAD Light Lichee Pi 4A configuration for 8GB DDR board";
compatible = "thead,light-val", "thead,light-lpi4a", "thead,light";
memory@0 {
device_type = "memory";
reg = <0x0 0x200000 0x1 0xffe00000>;
};
};
&cmamem {
size = <0 0x20000000>; // 512MB on lpi4a (SOM)
alloc-ranges = <0 0xd8000000 0 0x20000000>; // [0x0D800_0000 ~ 0x0F800_0000]
};
&i2c3 {
touch@14 {
#gpio-cells = <2>;
compatible = "goodix,gt9271";
reg = <0x14>;
interrupt-parent = <&ao_gpio_porta>;
interrupts = <3 0>;
irq-gpios = <&ao_gpio_porta 3 0>;
reset-gpios = <&pcal6408ahk_d 0 0>;
AVDD28-supply = <&reg_tp_pwr_en>;
touchscreen-size-x = <1200>;
touchscreen-size-y = <1920>;
tp-size = <9271>;
status = "okay";
};
};
&dsi0 {
status = "okay";
};
&dhost_0 {
panel0@0 {
compatible = "himax,hx8279";
reg = <0>;
backlight = <&lcd0_backlight>;
reset-gpio = <&pcal6408ahk_d 7 0>; /* active low */
hsvcc-supply = <&soc_vdd18_lcd0_en_reg>;
vspn3v3-supply = <&soc_vdd33_lcd0_en_reg>;
port {
panel0_in: endpoint {
remote-endpoint = <&dsi0_out>;
};
};
};
};

374
arch/riscv/boot/dts/thead/light-lpi4a-ref.dts
View File

@@ -158,6 +158,14 @@
iopmp_dsp1: IOPMP_DSP1 {
is_default_region;
};
iopmp_audio0: IOPMP_AUDIO0 {
is_default_region;
};
iopmp_audio1: IOPMP_AUDIO1 {
is_default_region;
};
};
mbox_910t_client1: mbox_910t_client1 {
@@ -258,15 +266,17 @@
ref-clock-frequency = <24000000>;
keep_wifi_power_on;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_wifi_wake>;
wifi_chip_type = "rtl8723ds";
WIFI,poweren_gpio = <&pcal6408ahk_c 5 0>;
WIFI,poweren_gpio = <&pcal6408ahk_c 4 0>;
status = "okay";
};
wcn_bt: wireless-bluetooth {
compatible = "bluetooth-platdata";
pinctrl-names = "default", "rts_gpio";
BT,power_gpio = <&pcal6408ahk_c 6 0>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_bt_wake>;
BT,power_gpio = <&pcal6408ahk_c 5 0>;
status = "okay";
};
@@ -651,9 +661,9 @@
no-map;
};
vi_mem: framebuffer@10000000 {
reg = <0x0 0x10000000 0x0 0x02C00000 /* vi_mem_pool_region[0] 44 MB (default) */
0x0 0x12C00000 0x0 0x01D00000 /* vi_mem_pool_region[1] 29 MB */
0x0 0x14900000 0x0 0x01E00000>; /* vi_mem_pool_region[2] 30 MB */
reg = <0x0 0x10000000 0x0 0x6700000>; /* vi_mem_pool_region[0] 44 MB (default) */
//0x0 0x12C00000 0x0 0x01D00000 /* vi_mem_pool_region[1] 29 MB */
//0x0 0x14900000 0x0 0x01E00000>; /* vi_mem_pool_region[2] 30 MB */
no-map;
};
facelib_mem: memory@17000000 {
@@ -759,9 +769,9 @@
num-cs = <1>;
cs-gpios = <&gpio2_porta 15 0>; // GPIO_ACTIVE_HIGH: 0
rx-sample-delay-ns = <10>;
status = "okay";
spi_norflash@0 {
status = "okay";
#address-cells = <1>;
#size-cells = <1>;
compatible = "winbond,w25q64jwm", "jedec,spi-nor";
@@ -771,6 +781,7 @@
};
spidev@1 {
status = "disable";
compatible = "spidev";
#address-cells = <0x1>;
#size-cells = <0x1>;
@@ -781,6 +792,23 @@
&uart0 {
clock-frequency = <100000000>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart0>;
};
&uart1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart1>;
};
&uart3 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart3>;
};
&uart4 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart4>;
};
&qspi0 {
@@ -827,6 +855,8 @@
tx-clk-delay = <0x00>; /* for RGMII */
phy-handle = <&phy_88E1111_0>;
status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_gmac0>;
mdio0 {
#address-cells = <1>;
@@ -849,6 +879,8 @@
tx-clk-delay = <0x00>; /* for RGMII */
phy-handle = <&phy_88E1111_1>;
status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_gmac1>;
};
&emmc {
@@ -870,6 +902,8 @@
pull_up;
wprtn_ignore;
status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_sdio0>;
};
&sdhci1 {
@@ -896,8 +930,22 @@
*/
pinctrl_uart0: uart0grp {
thead,pins = <
FM_UART0_TXD 0x0 0x72
FM_UART0_RXD 0x0 0x72
FM_UART0_TXD 0x0 0x202
FM_UART0_RXD 0x0 0x202
>;
};
pinctrl_i2c2: i2c2grp {
thead,pins = <
FM_I2C2_SCL 0x0 0x204
FM_I2C2_SDA 0x0 0x204
>;
};
pinctrl_i2c3: i2c3grp {
thead,pins = <
FM_I2C3_SCL 0x0 0x204
FM_I2C3_SDA 0x0 0x204
>;
};
@@ -934,9 +982,62 @@
>;
};
pinctrl_gmac1: gmac1grp {
thead,pins = <
FM_GPIO2_18 0x1 0x20f /* GMAC1_TX_CLK */
FM_GPIO2_19 0x1 0x20f /* GMAC1_RX_CLK */
FM_GPIO2_20 0x1 0x20f /* GMAC1_TXEN */
FM_GPIO2_21 0x1 0x20f /* GMAC1_TXD0 */
FM_GPIO2_22 0x1 0x20f /* GMAC1_TXD1 */
FM_GPIO2_23 0x1 0x20f /* GMAC1_TXD2 */
FM_GPIO2_24 0x1 0x20f /* GMAC1_TXD3 */
FM_GPIO2_25 0x1 0x20f /* GMAC1_RXDV */
FM_GPIO2_30 0x1 0x20f /* GMAC1_RXD0 */
FM_GPIO2_31 0x1 0x20f /* GMAC1_RXD1 */
FM_GPIO3_0 0x1 0x20f /* GMAC1_RXD2 */
FM_GPIO3_1 0x1 0x20f /* GMAC1_RXD3 */
>;
};
pinctrl_sdio0: sdio0grp {
thead,pins = <
FM_SDIO0_DETN 0x0 0x202
>;
};
pinctrl_pwm: pwmgrp {
thead,pins = <
FM_GPIO3_2 0x1 0x208 /* pwm0 */
FM_GPIO3_2 0x1 0x20f /* pwm0 */
FM_GPIO3_3 0x1 0x20f /* pwm1 */
>;
};
pinctrl_hdmi: hdmigrp {
thead,pins = <
FM_HDMI_SCL 0x0 0x202
FM_HDMI_SDA 0x0 0x202
FM_HDMI_CEC 0x0 0x202
>;
};
pinctrl_gmac0: gmac0grp {
thead,pins = <
FM_GMAC0_TX_CLK 0x0 0x20f /* GMAC0_TX_CLK */
FM_GMAC0_RX_CLK 0x0 0x20f /* GMAC0_RX_CLK */
FM_GMAC0_TXEN 0x0 0x20f /* GMAC0_TXEN */
FM_GMAC0_TXD0 0x0 0x20f /* GMAC0_TXD0 */
FM_GMAC0_TXD1 0x0 0x20f /* GMAC0_TXD1 */
FM_GMAC0_TXD2 0x0 0x20f /* GMAC0_TXD2 */
FM_GMAC0_TXD3 0x0 0x20f /* GMAC0_TXD3 */
FM_GMAC0_RXDV 0x0 0x20f /* GMAC0_RXDV */
FM_GMAC0_RXD0 0x0 0x20f /* GMAC0_RXD0 */
FM_GMAC0_RXD1 0x0 0x20f /* GMAC0_RXD1 */
FM_GMAC0_RXD2 0x0 0x20f /* GMAC0_RXD2 */
FM_GMAC0_RXD3 0x0 0x20f /* GMAC0_RXD3 */
FM_GMAC0_MDC 0x0 0x208 /* GMAC0_MDC */
FM_GMAC0_MDIO 0x0 0x208 /* GMAC0_MDIO */
FM_GMAC0_COL 0x3 0x232 /* PHY0_nRST */
FM_GMAC0_CRS 0x3 0x232 /* PHY0_nINT */
>;
};
};
@@ -948,22 +1049,6 @@
* Pin Configuration Node:
* Format: <pin_id mux_node config>
*/
pinctrl_uart3: uart3grp {
thead,pins = <
FM_UART3_TXD 0x0 0x72
FM_UART3_RXD 0x0 0x72
>;
};
pinctrl_uart4: uart4grp {
thead,pins = <
FM_UART4_TXD 0x0 0x72
FM_UART4_RXD 0x0 0x72
FM_UART4_CTSN 0x0 0x72
FM_UART4_RTSN 0x0 0x72
>;
};
pinctrl_qspi1: qspi1grp {
thead,pins = <
FM_QSPI1_SCLK 0x0 0x20a
@@ -973,6 +1058,54 @@
>;
};
pinctrl_i2c0: i2c0grp {
thead,pins = <
FM_I2C0_SCL 0x0 0x204
FM_I2C0_SDA 0x0 0x204
>;
};
pinctrl_i2c1: i2c1grp {
thead,pins = <
FM_I2C1_SCL 0x0 0x204
FM_I2C1_SDA 0x0 0x204
>;
};
pinctrl_uart1: uart1grp {
thead,pins = <
FM_UART1_TXD 0x0 0x202
FM_UART1_RXD 0x0 0x202
>;
};
pinctrl_uart4: uart4grp {
thead,pins = <
FM_UART4_TXD 0x0 0x202
FM_UART4_RXD 0x0 0x202
FM_UART4_CTSN 0x0 0x202
FM_UART4_RTSN 0x0 0x202
>;
};
pinctrl_uart3: uart3grp {
thead,pins = <
FM_UART3_TXD 0x1 0x202
FM_UART3_RXD 0x1 0x202
>;
};
pinctrl_wifi_wake: wifi_grp {
thead,pins = <
FM_GPIO0_27 0x0 0x202
>;
};
pinctrl_bt_wake: bt_grp {
thead,pins = <
FM_GPIO0_28 0x0 0x202
>;
};
pinctrl_iso7816: iso7816grp {
thead,pins = <
@@ -1094,6 +1227,8 @@
&i2c0 {
clock-frequency = <400000>;
status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_i2c0>;
pcal6408ahk_b: gpio@20 {
compatible = "nxp,pca9557";
@@ -1106,6 +1241,8 @@
&i2c1 {
clock-frequency = <400000>;
status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_i2c1>;
pcal6408ahk_c: gpio@20 {
compatible = "nxp,pca9557";
@@ -1118,11 +1255,15 @@
&i2c2 {
clock-frequency = <400000>;
status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_i2c2>;
};
&i2c3 {
clock-frequency = <400000>;
status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_i2c3>;
pcal6408ahk_d: gpio@20 {
compatible = "nxp,pca9557";
@@ -1275,13 +1416,6 @@
channel0 {
channel_id = <0>;
status = "okay";
sensor0 {
subdev_name = "vivcam";
idx = <0>;
csi_idx = <0>;
mode_idx = <0>;
path_type = "SENSOR_VGA_RAW12_LINER";
};
sensor1 {
subdev_name = "vivcam";
idx = <3>;
@@ -1306,21 +1440,52 @@
};
};
};
channel1 {
sensor1 {
subdev_name = "vivcam";
idx = <3>;
csi_idx = <0>;
mode_idx = <1>;
path_type = "SENSOR_2592x1944_LINER";
};
isp {
subdev_name = "isp";
idx = <1>;
path_type = "ISP_MI_PATH_SP";
output {
max_width = <2600>;
max_height = <2000>;
bit_per_pixel = <12>;
frame_count = <3>;
};
};
};
channel2 {
sensor1 {
subdev_name = "vivcam";
idx = <3>;
csi_idx = <0>;
mode_idx = <1>;
path_type = "SENSOR_2592x1944_LINER";
};
isp {
subdev_name = "isp";
idx = <1>;
path_type = "ISP_MI_PATH_SP2_BP";
output {
max_width = <2600>;
max_height = <2000>;
bit_per_pixel = <12>;
frame_count = <3>;
};
};
};
};
&video3{
vi_mem_pool_region = <0>; // vi_mem: framebuffer, region[0]
status = "okay";
channel0 {
sensor0 {
subdev_name = "vivcam";
idx = <0>;
csi_idx = <0>;
mode_idx = <0>;
path_type = "SENSOR_VGA_RAW12_LINER";
};
sensor1 {
subdev_name = "vivcam";
idx = <3>;
@@ -1339,8 +1504,8 @@
idx = <1>;
path_type = "ISP_MI_PATH_MP";
output {
max_width = <1920>;
max_height = <1088>;
max_width = <2600>;
max_height = <2000>;
bit_per_pixel = <12>;
frame_count = <3>;
};
@@ -1353,13 +1518,12 @@
};
};
channel1 {
sensor0 {
subdev_name = "vivcam";
idx = <0>;
sensor1 {
subdev_name = "vivcam";
idx = <3>;
csi_idx = <0>;
mode_idx = <0>;
path_type = "SENSOR_VGA_RAW12_LINER";
mode_idx = <1>;
path_type = "SENSOR_2592x1944_LINER";
};
dma {
subdev_name = "vipre";
@@ -1372,8 +1536,8 @@
idx = <1>;
path_type = "ISP_MI_PATH_MP";
output {
max_width = <1920>;
max_height = <1088>;
max_width = <2600>;
max_height = <2000>;
bit_per_pixel = <12>;
frame_count = <3>;
};
@@ -1386,13 +1550,12 @@
};
};
channel2 {
sensor0 {
subdev_name = "vivcam";
idx = <0>;
sensor1 {
subdev_name = "vivcam";
idx = <3>;
csi_idx = <0>;
mode_idx = <0>;
path_type = "SENSOR_VGA_RAW12_LINER";
mode_idx = <1>;
path_type = "SENSOR_2592x1944_LINER";
};
dma {
subdev_name = "vipre";
@@ -1405,8 +1568,8 @@
idx = <1>;
path_type = "ISP_MI_PATH_MP";
output {
max_width = <1920>;
max_height = <1088>;
max_width = <2600>;
max_height = <2000>;
bit_per_pixel = <12>;
frame_count = <3>;
};
@@ -1420,70 +1583,6 @@
};
};
&video9{
status = "okay";
channel0 {
sensor0 {
subdev_name = "vivcam";
idx = <1>; //vivcam1 sc132gs
csi_idx = <2>; //<2>=CSI2X2_A
mode_idx = <0>;
path_type = "SENSOR_1080X1280_30FPS_RAW10_LINER";
};
dsp{
output {
max_width = <1080>;
max_height = <1280>;
bit_per_pixel = <16>;
frame_count = <3>;
};
};
};
};
&video10{ // TUNINGTOOL
status = "okay";
channel0 {
sensor0 {
subdev_name = "vivcam";
idx = <0>; //<0>=vivcam0 : ov12870
csi_idx = <0>; //<0>=CSI2
mode_idx = <1>;
path_type = "SENSOR_1080P_RAW10_LINER"; //SENSOR_VGA_RAW10_LINER//
skip_init = <1>;
};
dma {
path_type = "VIPRE_CSI0_ISP0";
};
};
};
&video15{
status = "okay";
channel0 {
status = "okay";
sensor0 {
subdev_name = "vivcam";
idx = <0>;
csi_idx = <0>;
mode_idx = <0>;
path_type = "SENSOR_VGA_RAW12_LINER";
};
sensor1 {
subdev_name = "vivcam";
idx = <3>;
csi_idx = <0>;
mode_idx = <1>;
path_type = "SENSOR_2592x1944_LINER";
};
dma {
subdev_name = "vipre";
idx = <0>;
path_type = "VIPRE_CSI0_DDR";
};
};
};
&trng {
status = "disabled";
@@ -1534,12 +1633,37 @@
status = "okay";
};
&dhost_0 {
ports {
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
dsi0_in: endpoint {
remote-endpoint = <&enc0_out>;
};
};
port@1 {
reg = <1>;
dsi0_out: endpoint {
remote-endpoint = <&panel0_in>;
};
};
};
};
&disp1_out {
remote-endpoint = <&hdmi_tx_in>;
};
&hdmi_tx {
status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_hdmi>;
port@0 {
/* input */
@@ -1593,13 +1717,13 @@
&i2s1 {
status = "okay";
dmas = <&dmac2 11>, <&dmac2 10>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_audiopa14>,
<&pinctrl_audiopa15>,
<&pinctrl_audiopa16>,
<&pinctrl_audiopa17>,
<&pinctrl_audio_i2s1>;
light,mclk_keepon = <1>;
};
&i2s2 {

2
arch/riscv/boot/dts/thead/light-lpi4a-sec.dts
View File

@@ -5,7 +5,7 @@
/dts-v1/;
#include "light-lpi4a.dts"
#include "light-lpi4a-hdmi.dts"
&light_iopmp {

43
arch/riscv/boot/dts/thead/light-lpi4a.dts
View File

@@ -1,6 +1,6 @@
/* SPDX-License-Identifier: GPL-2.0 */
/*
* Copyright (C) 2022 Alibaba Group Holding Limited.
* Copyright (C) 2022-2023 Alibaba Group Holding Limited.
*/
#include "light-lpi4a-ref.dts"
@@ -16,5 +16,44 @@
};
&cmamem {
alloc-ranges = <0 0xe4000000 0 0x14000000>; // [0x0E400_0000 ~ 0x0F800_0000]
size = <0 0x20000000>; // 512MB on lpi4a (SOM)
alloc-ranges = <0 0xd8000000 0 0x20000000>; // [0x0D800_0000 ~ 0x0F800_0000]
};
&i2c3 {
touch@14 {
#gpio-cells = <2>;
compatible = "goodix,gt9271";
reg = <0x14>;
interrupt-parent = <&ao_gpio_porta>;
interrupts = <3 0>;
irq-gpios = <&ao_gpio_porta 3 0>;
reset-gpios = <&pcal6408ahk_d 0 0>;
AVDD28-supply = <&reg_tp_pwr_en>;
touchscreen-size-x = <800>;
touchscreen-size-y = <1200>;
tp-size = <9271>;
status = "okay";
};
};
&dsi0 {
status = "okay";
};
&dhost_0 {
panel0@0 {
compatible = "chongzhou,cz101b4001", "jadard,jd9365da-h3";
reg = <0>;
backlight = <&lcd0_backlight>;
reset-gpio = <&pcal6408ahk_d 7 0>; /* active low */
hsvcc-supply = <&soc_vdd18_lcd0_en_reg>;
vspn3v3-supply = <&soc_vdd33_lcd0_en_reg>;
port {
panel0_in: endpoint {
remote-endpoint = <&dsi0_out>;
};
};
};
};

26
arch/riscv/boot/dts/thead/light-vi-devices.dtsi
View File

@@ -4,7 +4,7 @@
*/
&video0{
status = "okay";
status = "disabled";
channel0 {
channel_id = <0>;
status = "okay";
@@ -86,7 +86,7 @@
};
&video1{
status = "okay";
status = "disabled";
channel0 { // VSE0
channel_id = <0>;
status = "okay";
@@ -183,7 +183,7 @@
};
&video2 {
status = "okay";
status = "disabled";
channel0 {
channel_id = <0>;
status = "okay";
@@ -272,7 +272,7 @@
};
&video3 {
status = "okay";
status = "disabled";
channel0 {
channel_id = <0>;
status = "okay";
@@ -370,7 +370,7 @@
};
&video4 {
status = "okay";
status = "disabled";
channel0 {
channel_id = <0>;
status = "okay";
@@ -483,7 +483,7 @@
};
&video5 {
status = "okay";
status = "disabled";
channel0 {
channel_id = <0>;
status = "okay";
@@ -612,7 +612,7 @@
&video6 {
status = "okay";
status = "disabled";
channel0 {
channel_id = <0>;
status = "okay";
@@ -669,7 +669,7 @@
&video7{
status = "okay";
status = "disabled";
channel0 {
channel_id = <0>;
status = "okay";
@@ -798,7 +798,7 @@
&video8{
status = "okay";
status = "disabled";
channel0 {
channel_id = <0>;
status = "okay";
@@ -829,7 +829,7 @@
&video9 { //IR debug
status = "okay";
status = "disabled";
channel0 {
channel_id = <0>;
status = "okay";
@@ -862,7 +862,7 @@
&video10{ // TUNING TOOL
status = "okay";
status = "disabled";
channel0 { // CSI2X2_B
status = "okay";
sensor0 {
@@ -889,7 +889,7 @@
&video11{
status = "okay";
status = "disabled";
channel0 {
channel_id = <0>;
status = "okay";
@@ -920,7 +920,7 @@
&video12{ // TUNING TOOL
status = "okay";
status = "disabled";
channel0 { // CSI2
status = "okay";
sensor0 {

206
arch/riscv/boot/dts/thead/light.dtsi
View File

@@ -16,6 +16,7 @@
#include <dt-bindings/clock/light-dspsys.h>
#include <dt-bindings/clock/light-audiosys.h>
#include <dt-bindings/firmware/thead/rsrc.h>
#include <dt-bindings/clock/light-miscsys.h>
#include <dt-bindings/soc/thead,light-iopmp.h>
#include <dt-bindings/thermal/thermal.h>
#include <dt-bindings/reset/light-reset.h>
@@ -186,6 +187,7 @@
interrupt-controller;
};
};
c910_1: cpu@1 {
device_type = "cpu";
reg = <1>;
@@ -324,6 +326,44 @@
interrupt-controller;
};
};
idle_states: idle-states {
CPU_RET_0_0: cpu-retentive-0-0 {
compatible = "riscv,idle-state";
riscv,sbi-suspend-param = <0x10000000>;
entry-latency-us = <20>;
exit-latency-us = <40>;
min-residency-us = <80>;
};
CPU_NONRET_0_0: cpu-nonretentive-0-0 {
compatible = "riscv,idle-state";
riscv,sbi-suspend-param = <0x90000000>;
entry-latency-us = <250>;
exit-latency-us = <500>;
min-residency-us = <950>;
};
CLUSTER_RET_0: cluster-retentive-0 {
compatible = "riscv,idle-state";
riscv,sbi-suspend-param = <0x11000000>;
local-timer-stop;
entry-latency-us = <50>;
exit-latency-us = <100>;
min-residency-us = <250>;
wakeup-latency-us = <130>;
};
CLUSTER_NONRET_0: cluster-nonretentive-0 {
compatible = "riscv,idle-state";
riscv,sbi-suspend-param = <0x91000000>;
local-timer-stop;
entry-latency-us = <600>;
exit-latency-us = <1100>;
min-residency-us = <2700>;
wakeup-latency-us = <1500>;
};
};
};
display-subsystem {
@@ -632,6 +672,18 @@
status = "okay";
};
miscsys_reg: miscsys-reg@ffec02c000 {
compatible = "thead,light-miscsys-reg", "syscon";
reg = <0xff 0xec02c000 0x0 0x1000>;
status = "okay";
};
tee_miscsys_reg: tee_miscsys-reg@fffc02d000 {
compatible = "thead,light-miscsys-reg", "syscon";
reg = <0xff 0xfc02d000 0x0 0x1000>;
status = "okay";
};
audio_ioctrl: audio_ioctrl@ffcb01d000 {
compatible = "thead,light-audio-ioctrl-reg", "syscon";
reg = <0xff 0xcb01d000 0x0 0x1000>;
@@ -656,6 +708,8 @@
thead,teesys = <&teesys_syscon>;
#address-cells = <1>;
#size-cells = <1>;
clocks = <&miscsys_clk_gate CLKGEN_MISCSYS_EFUSE_PCLK>;
clock-names = "pclk";
gmac0_mac_address: mac-address@176 {
reg = <0xb0 6>;
@@ -683,7 +737,9 @@
reg = <0xff 0xec005000 0x0 0x1000>;
#address-cells = <1>;
#size-cells = <0>;
clocks = <&clk CLKGEN_GPIO0_PCLK>,
<&clk CLKGEN_GPIO0_DBCLK>;
clock-names = "bus", "db";
gpio0_porta: gpio0-controller@0 {
compatible = "snps,dw-apb-gpio-port";
gpio-controller;
@@ -703,7 +759,9 @@
reg = <0xff 0xec006000 0x0 0x1000>;
#address-cells = <1>;
#size-cells = <0>;
clocks = <&clk CLKGEN_GPIO1_PCLK>,
<&clk CLKGEN_GPIO1_DBCLK>;
clock-names = "bus", "db";
gpio1_porta: gpio1-controller@0 {
compatible = "snps,dw-apb-gpio-port";
gpio-controller;
@@ -723,7 +781,9 @@
reg = <0xff 0xe7f34000 0x0 0x1000>;
#address-cells = <1>;
#size-cells = <0>;
clocks = <&clk CLKGEN_GPIO2_PCLK>,
<&clk CLKGEN_GPIO2_DBCLK>;
clock-names = "bus", "db";
gpio2_porta: gpio2-controller@0 {
compatible = "snps,dw-apb-gpio-port";
gpio-controller;
@@ -743,7 +803,9 @@
reg = <0xff 0xe7f38000 0x0 0x1000>;
#address-cells = <1>;
#size-cells = <0>;
clocks = <&clk CLKGEN_GPIO3_PCLK>,
<&clk CLKGEN_GPIO3_DBCLK>;
clock-names = "bus", "db";
gpio3_porta: gpio3-controller@0 {
compatible = "snps,dw-apb-gpio-port";
gpio-controller;
@@ -798,15 +860,19 @@
};
};
padctrl1_apsys: pinctrl1-apsys@ffe7f3c000 {
padctrl1_apsys: padctrl1-apsys@ffe7f3c000 {
compatible = "thead,light-fm-left-pinctrl";
reg = <0xff 0xe7f3c000 0x0 0x1000>;
clocks = <&clk CLKGEN_PADCTRL1_APSYS_PCLK>;
clock-names = "pclk";
status = "okay";
};
padctrl0_apsys: padctrl0-apsys@ffec007000 {
compatible = "thead,light-fm-right-pinctrl";
reg = <0xff 0xec007000 0x0 0x1000>;
clocks = <&clk CLKGEN_PADCTRL0_APSYS_PCLK>;
clock-names = "pclk";
status = "okay";
};
@@ -922,7 +988,7 @@
};
uart0: serial@ffe7014000 { /* Normal serial, for C910 log */
compatible = "snps,dw-apb-uart";
compatible = "snps,dw-apb-uart", "light,uart0";
reg = <0xff 0xe7014000 0x0 0x4000>;
interrupt-parent = <&intc>;
interrupts = <36>;
@@ -1017,7 +1083,9 @@
pinctrl-0 = <&pinctrl_spi0>;
interrupt-parent = <&intc>;
interrupts = <54>;
clocks = <&dummy_clock_spi>;
clocks = <&clk CLKGEN_SPI_SSI_CLK>,
<&clk CLKGEN_SPI_PCLK>;
clock-names = "sclk", "pclk";
num-cs = <2>;
#address-cells = <1>;
#size-cells = <0>;
@@ -1030,7 +1098,9 @@
pinctrl-0 = <&pinctrl_qspi0>;
interrupt-parent = <&intc>;
interrupts = <52>;
clocks = <&dummy_clock_qspi>;
clocks = <&clk CLKGEN_QSPI0_SSI_CLK>,
<&clk CLKGEN_QSPI0_PCLK>;
clock-names = "sclk", "pclk";
#address-cells = <1>;
#size-cells = <0>;
};
@@ -1042,7 +1112,9 @@
pinctrl-0 = <&pinctrl_qspi1>;
interrupt-parent = <&intc>;
interrupts = <53>;
clocks = <&dummy_clock_spi>;
clocks = <&clk CLKGEN_QSPI1_SSI_CLK>,
<&clk CLKGEN_QSPI1_PCLK>;
clock-names = "sclk", "pclk";
#address-cells = <1>;
#size-cells = <0>;
};
@@ -1153,9 +1225,8 @@
clocks = <&vosys_clk_gate LIGHT_CLKGEN_HDMI_PCLK>,
<&vosys_clk_gate LIGHT_CLKGEN_HDMI_SFR_CLK>,
<&vosys_clk_gate LIGHT_CLKGEN_HDMI_CEC_CLK>,
<&vosys_clk_gate LIGHT_CLKGEN_HDMI_PIXCLK>,
<&vosys_clk_gate LIGHT_CLKGEN_HDMI_I2S_CLK>;
clock-names = "iahb", "isfr", "cec", "pixclk", "i2s";
<&vosys_clk_gate LIGHT_CLKGEN_HDMI_PIXCLK>;
clock-names = "iahb", "isfr", "cec", "pixclk";
reg-io-width = <4>;
phy_version = <301>;
/* TODO: add phy property */
@@ -1171,6 +1242,7 @@
<0xff 0xef630010 0x0 0x60>;
interrupt-parent = <&intc>;
interrupts = <93>;
vosys-regmap = <&vosys_reg>;
clocks = <&vosys_clk_gate LIGHT_CLKGEN_DPU_CCLK>,
<&vosys_clk_gate LIGHT_CLKGEN_DPU_PIXCLK0>,
<&vosys_clk_gate LIGHT_CLKGEN_DPU_PIXCLK1>,
@@ -1232,6 +1304,7 @@
interrupts = <74>;
clocks = <&dummy_clock_rtc>;
clock-names = "rtc";
wakeup-source;
status = "okay";
};
@@ -1239,6 +1312,11 @@
compatible = "thead,dwc3";
usb3-misc-regmap = <&misc_sysreg>;
usb3-drd-regmap = <&usb3_drd>;
clocks = <&miscsys_clk_gate CLKGEN_MISCSYS_USB3_DRD_CLK>,
<&miscsys_clk_gate CLKGEN_MISCSYS_USB3_DRD_CTRL_REF_CLK>,
<&miscsys_clk_gate CLKGEN_MISCSYS_USB3_DRD_PHY_REF_CLK>,
<&miscsys_clk_gate CLKGEN_MISCSYS_USB3_DRD_SUSPEND_CLK>;
clock-names = "drd", "ctrl", "phy", "suspend";
#address-cells = <2>;
#size-cells = <2>;
ranges;
@@ -1248,8 +1326,6 @@
reg = <0xff 0xe7040000 0x0 0x10000>;
interrupt-parent = <&intc>;
interrupts = <68>;
clocks = <&dummy_clock_ref>, <&dummy_clock_apb>, <&dummy_clock_suspend>;
clock-names = "ref", "bus_early", "suspend";
reg-shift = <2>;
reg-io-width = <4>;
maximum-speed = "super-speed";
@@ -1301,7 +1377,7 @@
reg = <0xff 0xefc00000 0x0 0x1000>;
interrupt-parent = <&intc>;
interrupts = <27>;
clocks = <&dummy_clock_apb>, <&dummy_clock_apb>;
clocks = <&clk CLKGEN_DMAC_CPUSYS_ACLK>, <&clk CLKGEN_DMAC_CPUSYS_HCLK>;
clock-names = "core-clk", "cfgr-clk";
#dma-cells = <1>;
dma-channels = <4>;
@@ -1318,7 +1394,7 @@
reg = <0xff 0xff340000 0x0 0x1000>;
interrupt-parent = <&intc>;
interrupts = <150>;
clocks = <&dummy_clock_apb>, <&dummy_clock_apb>;
clocks = <&clk CLKGEN_DMAC_CPUSYS_ACLK>, <&clk CLKGEN_DMAC_CPUSYS_HCLK>;
clock-names = "core-clk", "cfgr-clk";
#dma-cells = <1>;
dma-channels = <4>;
@@ -1335,7 +1411,7 @@
reg = <0xff 0xc8000000 0x0 0x2000>;
interrupt-parent = <&intc>;
interrupts = <167>;
clocks = <&dummy_clock_apb>, <&dummy_clock_apb>;
clocks = <&clk CLKGEN_DMAC_CPUSYS_ACLK>, <&clk CLKGEN_DMAC_CPUSYS_HCLK>;
clock-names = "core-clk", "cfgr-clk";
#dma-cells = <1>;
dma-channels = <16>;
@@ -1366,8 +1442,11 @@
interrupt-parent = <&intc>;
interrupts = <66>;
interrupt-names = "macirq";
clocks = <&clk CLKGEN_GMAC0_CCLK>;
clock-names = "gmac_pll_clk";
clocks = <&clk CLKGEN_GMAC0_CCLK>,
<&clk CLKGEN_GMAC0_PCLK>,
<&clk CLKGEN_GMAC_AXI_ACLK>,
<&clk CLKGEN_GMAC_AXI_PCLK>;
clock-names = "gmac_pll_clk","pclk","axi_aclk","axi_pclk";
snps,pbl = <32>;
snps,fixed-burst;
snps,axi-config = <&stmmac_axi_setup>;
@@ -1385,8 +1464,11 @@
interrupt-parent = <&intc>;
interrupts = <67>;
interrupt-names = "macirq";
clocks = <&clk CLKGEN_GMAC1_CCLK>;
clock-names = "gmac_pll_clk";
clocks = <&clk CLKGEN_GMAC1_CCLK>,
<&clk CLKGEN_GMAC1_PCLK>,
<&clk CLKGEN_GMAC_AXI_ACLK>,
<&clk CLKGEN_GMAC_AXI_PCLK>;
clock-names = "gmac_pll_clk","pclk","axi_aclk","axi_pclk";
snps,pbl = <32>;
snps,fixed-burst;
snps,axi-config = <&stmmac_axi_setup>;
@@ -1400,8 +1482,9 @@
interrupt-parent = <&intc>;
interrupts = <62>;
interrupt-names = "sdhciirq";
clocks = <&dummy_clock_sdhci>;
clock-names = "core";
clocks = <&clk CLKGEN_EMMC_SDIO_REF_CLK>,
<&miscsys_clk_gate CLKGEN_MISCSYS_EMMC_CLK>;
clock-names = "core", "bus";
};
sdhci0: sd@ffe7090000 {
@@ -1410,18 +1493,20 @@
interrupt-parent = <&intc>;
interrupts = <64>;
interrupt-names = "sdhci0irq";
clocks = <&dummy_clock_sdhci>;
clock-names = "core";
clocks = <&clk CLKGEN_EMMC_SDIO_REF_CLK>,
<&miscsys_clk_gate CLKGEN_MISCSYS_EMMC_CLK>;
clock-names = "core", "bus";
};
sdhci1: sd@ffe70a0000 {
compatible = "snps,dwcmshc-sdhci";
reg = <0xff 0xe70a0000 0x0 0x10000>;
interrupt-parent = <&intc>;
interrupts = <71>;
interrupt-names = "sdhci1irq";
clocks = <&dummy_clock_sdhci>;
clock-names = "core";
compatible = "snps,dwcmshc-sdhci";
reg = <0xff 0xe70a0000 0x0 0x10000>;
interrupt-parent = <&intc>;
interrupts = <71>;
interrupt-names = "sdhci1irq";
clocks = <&clk CLKGEN_EMMC_SDIO_REF_CLK>,
<&miscsys_clk_gate CLKGEN_MISCSYS_EMMC_CLK>;
clock-names = "core", "bus";
};
hwspinlock: hwspinlock@ffefc10000 {
@@ -1521,8 +1606,6 @@
#sound-dai-cells = <1>;
compatible = "light,light-i2s";
reg = <0xff 0xe7034000 0x0 0x4000>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_light_i2s0>;
light,mode = "i2s-master";
light,sel = "ap_i2s";
interrupt-parent = <&intc>;
@@ -1531,7 +1614,7 @@
dma-names = "tx", "rx";
light,dma_maxburst = <4>;
#dma-cells = <1>;
clocks = <&dummy_clock_apb>;
clocks = <&vosys_clk_gate LIGHT_CLKGEN_HDMI_I2S_CLK>;
clock-names = "pclk";
status = "disabled";
};
@@ -1551,7 +1634,7 @@
dma-names = "tx", "rx";
light,dma_maxburst = <4>;
#dma-cells = <1>;
clocks = <&dummy_clock_apb>;
clocks = <&audiosys_clk_gate LIGHT_CLKGEN_AUDIO_I2S0>;
clock-names = "pclk";
status = "disabled";
};
@@ -1567,11 +1650,11 @@
light,sel = "i2s1";
interrupt-parent = <&intc>;
interrupts = <175>;
dmas = <&dmac2 11>, <&dmac2 17>;
dmas = <&dmac2 11>, <&dmac2 10>;
dma-names = "tx", "rx";
light,dma_maxburst = <4>;
#dma-cells = <1>;
clocks = <&dummy_clock_apb>;
clocks = <&audiosys_clk_gate LIGHT_CLKGEN_AUDIO_I2S1>;
clock-names = "pclk";
status = "disabled";
};
@@ -1591,7 +1674,7 @@
dma-names = "tx", "rx";
light,dma_maxburst = <4>;
#dma-cells = <1>;
clocks = <&dummy_clock_apb>;
clocks = <&audiosys_clk_gate LIGHT_CLKGEN_AUDIO_I2S2>;
clock-names = "pclk";
status = "disabled";
};
@@ -1610,7 +1693,7 @@
dma-names = "tx", "rx";
light,dma_maxburst = <4>;
#dma-cells = <1>;
clocks = <&dummy_clock_apb>;
clocks = <&audiosys_clk_gate LIGHT_CLKGEN_AUDIO_I2S8CH>;
clock-names = "pclk";
status = "disabled";
};
@@ -1629,7 +1712,7 @@
dma-names = "tx", "rx";
light,dma_maxburst = <4>;
#dma-cells = <1>;
clocks = <&dummy_clock_apb>;
clocks = <&audiosys_clk_gate LIGHT_CLKGEN_AUDIO_I2S8CH>;
clock-names = "pclk";
status = "disabled";
};
@@ -1648,7 +1731,7 @@
dma-names = "tx", "rx";
light,dma_maxburst = <4>;
#dma-cells = <1>;
clocks = <&dummy_clock_apb>;
clocks = <&audiosys_clk_gate LIGHT_CLKGEN_AUDIO_I2S8CH>;
clock-names = "pclk";
status = "disabled";
};
@@ -1667,7 +1750,7 @@
dma-names = "tx", "rx";
light,dma_maxburst = <4>;
#dma-cells = <1>;
clocks = <&dummy_clock_apb>;
clocks = <&audiosys_clk_gate LIGHT_CLKGEN_AUDIO_I2S8CH>;
clock-names = "pclk";
status = "disabled";
};
@@ -1855,6 +1938,7 @@
#dma-cells = <1>;
clocks = <&audiosys_clk_gate LIGHT_CLKGEN_AUDIO_SPDIF0>;
clock-names = "pclk";
id = <0>;
status = "disabled";
};
@@ -1873,6 +1957,7 @@
#dma-cells = <1>;
clocks = <&audiosys_clk_gate LIGHT_CLKGEN_AUDIO_SPDIF1>;
clock-names = "pclk";
id = <1>;
status = "disabled";
};
@@ -1893,7 +1978,8 @@
reg = <0xff 0xe7f20000 0x0 0x4000>;
interrupt-parent = <&intc>;
interrupts = <44>;
clocks = <&dummy_clock_apb>;
clocks = <&clk CLKGEN_I2C0_PCLK>;
clock-names = "pclk";
clock-frequency = <100000>;
i2c_mode = "dma";
dmas = <&dmac0 12>, <&dmac0 13>;
@@ -1916,7 +2002,8 @@
reg = <0xff 0xe7f24000 0x0 0x4000>;
interrupt-parent = <&intc>;
interrupts = <45>;
clocks = <&dummy_clock_apb>;
clocks = <&clk CLKGEN_I2C1_PCLK>;
clock-names = "pclk";
clock-frequency = <100000>;
i2c_mode = "dma";
dmas = <&dmac0 14>, <&dmac0 15>;
@@ -1939,7 +2026,8 @@
reg = <0xff 0xec00c000 0x0 0x4000>;
interrupt-parent = <&intc>;
interrupts = <46>;
clocks = <&dummy_clock_apb>;
clocks = <&clk CLKGEN_I2C2_PCLK>;
clock-names = "pclk";
clock-frequency = <100000>;
i2c_mode = "dma";
dmas = <&dmac0 16>, <&dmac0 17>;
@@ -1964,7 +2052,8 @@
reg = <0xff 0xec014000 0x0 0x4000>;
interrupt-parent = <&intc>;
interrupts = <47>;
clocks = <&dummy_clock_apb>;
clocks = <&clk CLKGEN_I2C3_PCLK>;
clock-names = "pclk";
clock-frequency = <100000>;
i2c_mode = "dma";
dmas = <&dmac0 18>, <&dmac0 19>;
@@ -1989,7 +2078,8 @@
reg = <0xff 0xe7f28000 0x0 0x4000>;
interrupt-parent = <&intc>;
interrupts = <48>;
clocks = <&dummy_clock_apb>;
clocks = <&clk CLKGEN_I2C4_PCLK>;
clock-names = "pclk";
clock-frequency = <100000>;
i2c_mode = "dma";
dmas = <&dmac0 20>, <&dmac0 21>;
@@ -2480,7 +2570,11 @@
reg = <0xff 0xff300000 0x0 0x40000>;
interrupt-parent = <&intc>;
interrupts = <144>,<145>,<146>,<147>;
clocks = <&dummy_clock_eip>;
clocks = <&miscsys_clk_gate CLKGEN_MISCSYS_EIP120SI_CLK>,
<&miscsys_clk_gate CLKGEN_MISCSYS_EIP120SII_CLK>,
<&miscsys_clk_gate CLKGEN_MISCSYS_EIP120SIII_CLK>,
<&miscsys_clk_gate CLKGEN_MISCSYS_EIP150B_HCLK>;
clock-names = "120si_clk","120sii_clk","120siii_clk","hclk";
status = "disabled";
};
@@ -2496,6 +2590,11 @@
status = "okay";
};
aon_suspend_ctrl: aon_suspend_ctrl {
compatible = "thead,light-aon-suspend-ctrl";
status = "okay";
};
visys_clk_gate: visys-clk-gate { /* VI_SYSREG_R */
compatible = "thead,visys-gate-controller";
visys-regmap = <&visys_reg>;
@@ -2530,6 +2629,15 @@
#clock-cells = <1>;
status = "okay";
};
miscsys_clk_gate: miscsys-clk-gate {
compatible = "thead,miscsys-gate-controller";
miscsys-regmap = <&miscsys_reg>;
tee-miscsys-regmap = <&tee_miscsys_reg>;
#clock-cells = <1>;
status = "okay";
};
};
};

6
arch/riscv/configs/defconfig
View File

@@ -17,6 +17,12 @@ CONFIG_PERF_EVENTS=y
CONFIG_SOC_THEAD=y
CONFIG_SMP=y
CONFIG_VECTOR=y
CONFIG_HOTPLUG_CPU=y
CONFIG_PM=y
CONFIG_CPU_IDLE=y
CONFIG_VIRTUALIZATION=y
CONFIG_KVM=m
CONFIG_JUMP_LABEL=y
CONFIG_MODULES=y
CONFIG_MODULE_UNLOAD=y
CONFIG_PARTITION_ADVANCED=y

11
arch/riscv/configs/light_defconfig
View File

@@ -106,6 +106,7 @@ CONFIG_KEYBOARD_GPIO=y
# CONFIG_INPUT_MOUSE is not set
CONFIG_INPUT_TOUCHSCREEN=y
CONFIG_TOUCHSCREEN_GOODIX=y
CONFIG_TOUCHSCREEN_GT9XX=y
CONFIG_INPUT_MISC=y
CONFIG_INPUT_UINPUT=y
CONFIG_SERIAL_8250=y
@@ -200,6 +201,8 @@ CONFIG_DRM_PANEL_SIMPLE=y
CONFIG_DRM_PANEL_ILITEK_ILI9881C=y
CONFIG_DRM_PANEL_ILI9881D=y
CONFIG_DRM_PANEL_HX8394=y
CONFIG_DRM_PANEL_JADARD_JD9365DA_H3=y
CONFIG_DRM_PANEL_HX8279=y
CONFIG_DRM_VERISILICON=y
CONFIG_BACKLIGHT_CLASS_DEVICE=y
CONFIG_BACKLIGHT_PWM=y
@@ -337,3 +340,11 @@ CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC_VALUE=0
CONFIG_PM=y
# CONFIG_SUSPEND is not set
# CONFIG_PM_SLEEP is not set
CONFIG_PM_DEVFREQ=y
CONFIG_DEVFREQ_GOV_SIMPLE_ONDEMAND=y
CONFIG_DEVFREQ_GOV_PERFORMANCE=y
CONFIG_DEVFREQ_GOV_POWERSAVE=y
CONFIG_DEVFREQ_GOV_USERSPACE=y
CONFIG_DEVFREQ_GOV_PASSIVE=y
CONFIG_PM_DEVFREQ_EVENT=y

5
arch/riscv/configs/rv32_defconfig
View File

@@ -18,6 +18,11 @@ CONFIG_SOC_SIFIVE=y
CONFIG_SOC_VIRT=y
CONFIG_ARCH_RV32I=y
CONFIG_SMP=y
CONFIG_HOTPLUG_CPU=y
CONFIG_PM=y
CONFIG_CPU_IDLE=y
CONFIG_VIRTUALIZATION=y
CONFIG_KVM=m
CONFIG_JUMP_LABEL=y
CONFIG_MODULES=y
CONFIG_MODULE_UNLOAD=y

27
arch/riscv/include/asm/asm.h
View File

@@ -66,4 +66,31 @@
#error "Unexpected __SIZEOF_SHORT__"
#endif
#ifdef __ASSEMBLY__
/* Common assembly source macros */
#ifdef CONFIG_XIP_KERNEL
.macro XIP_FIXUP_OFFSET reg
REG_L t0, _xip_fixup
add \reg, \reg, t0
.endm
.macro XIP_FIXUP_FLASH_OFFSET reg
la t1, __data_loc
li t0, XIP_OFFSET_MASK
and t1, t1, t0
li t1, XIP_OFFSET
sub t0, t0, t1
sub \reg, \reg, t0
.endm
_xip_fixup: .dword CONFIG_PHYS_RAM_BASE - CONFIG_XIP_PHYS_ADDR - XIP_OFFSET
#else
.macro XIP_FIXUP_OFFSET reg
.endm
.macro XIP_FIXUP_FLASH_OFFSET reg
.endm
#endif /* CONFIG_XIP_KERNEL */
#endif /* __ASSEMBLY__ */
#endif /* _ASM_RISCV_ASM_H */

25
arch/riscv/include/asm/cpu_ops_sbi.h Normal file
View File

@@ -0,0 +1,25 @@
/* SPDX-License-Identifier: GPL-2.0-only */
/*
* Copyright (c) 2021 by Rivos Inc.
*/
#ifndef __ASM_CPU_OPS_SBI_H
#define __ASM_CPU_OPS_SBI_H
#ifndef __ASSEMBLY__
#include <linux/init.h>
#include <linux/sched.h>
#include <linux/threads.h>
/**
* struct sbi_hart_boot_data - Hart specific boot used during booting and
* cpu hotplug.
* @task_ptr: A pointer to the hart specific tp
* @stack_ptr: A pointer to the hart specific sp
*/
struct sbi_hart_boot_data {
void *task_ptr;
void *stack_ptr;
};
#endif
#endif /* ifndef __ASM_CPU_OPS_SBI_H */

2
arch/riscv/include/asm/pgtable.h
View File

@@ -446,7 +446,7 @@ static inline pgprot_t pgprot_writecombine(pgprot_t _prot)
return __pgprot(prot);
}
#define pgprot_dmacoherent pgprot_writecombine
/*
* Encode and decode a swap entry
*

42
arch/riscv/include/asm/sbi.h
View File

@@ -61,13 +61,45 @@ enum sbi_ext_hsm_fid {
SBI_EXT_HSM_HART_START = 0,
SBI_EXT_HSM_HART_STOP,
SBI_EXT_HSM_HART_STATUS,
SBI_EXT_HSM_HART_SUSPEND,
};
enum sbi_hsm_hart_status {
SBI_HSM_HART_STATUS_STARTED = 0,
SBI_HSM_HART_STATUS_STOPPED,
SBI_HSM_HART_STATUS_START_PENDING,
SBI_HSM_HART_STATUS_STOP_PENDING,
enum sbi_hsm_hart_state {
SBI_HSM_STATE_STARTED = 0,
SBI_HSM_STATE_STOPPED,
SBI_HSM_STATE_START_PENDING,
SBI_HSM_STATE_STOP_PENDING,
SBI_HSM_STATE_SUSPENDED,
SBI_HSM_STATE_SUSPEND_PENDING,
SBI_HSM_STATE_RESUME_PENDING,
};
#define SBI_HSM_SUSP_BASE_MASK 0x7fffffff
#define SBI_HSM_SUSP_NON_RET_BIT 0x80000000
#define SBI_HSM_SUSP_PLAT_BASE 0x10000000
#define SBI_HSM_SUSPEND_RET_DEFAULT 0x00000000
#define SBI_HSM_SUSPEND_RET_PLATFORM SBI_HSM_SUSP_PLAT_BASE
#define SBI_HSM_SUSPEND_RET_LAST SBI_HSM_SUSP_BASE_MASK
#define SBI_HSM_SUSPEND_NON_RET_DEFAULT SBI_HSM_SUSP_NON_RET_BIT
#define SBI_HSM_SUSPEND_NON_RET_PLATFORM (SBI_HSM_SUSP_NON_RET_BIT | \
SBI_HSM_SUSP_PLAT_BASE)
#define SBI_HSM_SUSPEND_NON_RET_LAST (SBI_HSM_SUSP_NON_RET_BIT | \
SBI_HSM_SUSP_BASE_MASK)
enum sbi_ext_srst_fid {
SBI_EXT_SRST_RESET = 0,
};
enum sbi_srst_reset_type {
SBI_SRST_RESET_TYPE_SHUTDOWN = 0,
SBI_SRST_RESET_TYPE_COLD_REBOOT,
SBI_SRST_RESET_TYPE_WARM_REBOOT,
};
enum sbi_srst_reset_reason {
SBI_SRST_RESET_REASON_NONE = 0,
SBI_SRST_RESET_REASON_SYS_FAILURE,
};
#define SBI_SPEC_VERSION_DEFAULT 0x1

36
arch/riscv/include/asm/suspend.h Normal file
View File

@@ -0,0 +1,36 @@
/* SPDX-License-Identifier: GPL-2.0-only */
/*
* Copyright (c) 2021 Western Digital Corporation or its affiliates.
* Copyright (c) 2022 Ventana Micro Systems Inc.
*/
#ifndef _ASM_RISCV_SUSPEND_H
#define _ASM_RISCV_SUSPEND_H
#include <asm/ptrace.h>
struct suspend_context {
/* Saved and restored by low-level functions */
struct pt_regs regs;
/* Saved and restored by high-level functions */
unsigned long scratch;
unsigned long tvec;
unsigned long ie;
#ifdef CONFIG_MMU
unsigned long satp;
#endif
};
/* Low-level CPU suspend entry function */
int __cpu_suspend_enter(struct suspend_context *context);
/* High-level CPU suspend which will save context and call finish() */
int cpu_suspend(unsigned long arg,
int (*finish)(unsigned long arg,
unsigned long entry,
unsigned long context));
/* Low-level CPU resume entry function */
int __cpu_resume_enter(unsigned long hartid, unsigned long context);
#endif

2
arch/riscv/kernel/Makefile
View File

@@ -48,6 +48,8 @@ obj-$(CONFIG_SMP) += cpu_ops_spinwait.o
obj-$(CONFIG_MODULES) += module.o
obj-$(CONFIG_MODULE_SECTIONS) += module-sections.o
obj-$(CONFIG_CPU_PM) += suspend_entry.o suspend.o
obj-$(CONFIG_FUNCTION_TRACER) += mcount.o ftrace.o
obj-$(CONFIG_DYNAMIC_FTRACE) += mcount-dyn.o

165
arch/riscv/kernel/asm-offsets.c
View File

@@ -10,6 +10,10 @@
#include <linux/sched.h>
#include <asm/thread_info.h>
#include <asm/ptrace.h>
#include <asm/cpu_ops_sbi.h>
#include <asm/suspend.h>
void asm_offsets(void);
void asm_offsets(void)
{
@@ -149,6 +153,162 @@ void asm_offsets(void)
OFFSET(PT_BADADDR, pt_regs, badaddr);
OFFSET(PT_CAUSE, pt_regs, cause);
OFFSET(SUSPEND_CONTEXT_REGS, suspend_context, regs);
#if 0
OFFSET(KVM_ARCH_GUEST_ZERO, kvm_vcpu_arch, guest_context.zero);
OFFSET(KVM_ARCH_GUEST_RA, kvm_vcpu_arch, guest_context.ra);
OFFSET(KVM_ARCH_GUEST_SP, kvm_vcpu_arch, guest_context.sp);
OFFSET(KVM_ARCH_GUEST_GP, kvm_vcpu_arch, guest_context.gp);
OFFSET(KVM_ARCH_GUEST_TP, kvm_vcpu_arch, guest_context.tp);
OFFSET(KVM_ARCH_GUEST_T0, kvm_vcpu_arch, guest_context.t0);
OFFSET(KVM_ARCH_GUEST_T1, kvm_vcpu_arch, guest_context.t1);
OFFSET(KVM_ARCH_GUEST_T2, kvm_vcpu_arch, guest_context.t2);
OFFSET(KVM_ARCH_GUEST_S0, kvm_vcpu_arch, guest_context.s0);
OFFSET(KVM_ARCH_GUEST_S1, kvm_vcpu_arch, guest_context.s1);
OFFSET(KVM_ARCH_GUEST_A0, kvm_vcpu_arch, guest_context.a0);
OFFSET(KVM_ARCH_GUEST_A1, kvm_vcpu_arch, guest_context.a1);
OFFSET(KVM_ARCH_GUEST_A2, kvm_vcpu_arch, guest_context.a2);
OFFSET(KVM_ARCH_GUEST_A3, kvm_vcpu_arch, guest_context.a3);
OFFSET(KVM_ARCH_GUEST_A4, kvm_vcpu_arch, guest_context.a4);
OFFSET(KVM_ARCH_GUEST_A5, kvm_vcpu_arch, guest_context.a5);
OFFSET(KVM_ARCH_GUEST_A6, kvm_vcpu_arch, guest_context.a6);
OFFSET(KVM_ARCH_GUEST_A7, kvm_vcpu_arch, guest_context.a7);
OFFSET(KVM_ARCH_GUEST_S2, kvm_vcpu_arch, guest_context.s2);
OFFSET(KVM_ARCH_GUEST_S3, kvm_vcpu_arch, guest_context.s3);
OFFSET(KVM_ARCH_GUEST_S4, kvm_vcpu_arch, guest_context.s4);
OFFSET(KVM_ARCH_GUEST_S5, kvm_vcpu_arch, guest_context.s5);
OFFSET(KVM_ARCH_GUEST_S6, kvm_vcpu_arch, guest_context.s6);
OFFSET(KVM_ARCH_GUEST_S7, kvm_vcpu_arch, guest_context.s7);
OFFSET(KVM_ARCH_GUEST_S8, kvm_vcpu_arch, guest_context.s8);
OFFSET(KVM_ARCH_GUEST_S9, kvm_vcpu_arch, guest_context.s9);
OFFSET(KVM_ARCH_GUEST_S10, kvm_vcpu_arch, guest_context.s10);
OFFSET(KVM_ARCH_GUEST_S11, kvm_vcpu_arch, guest_context.s11);
OFFSET(KVM_ARCH_GUEST_T3, kvm_vcpu_arch, guest_context.t3);
OFFSET(KVM_ARCH_GUEST_T4, kvm_vcpu_arch, guest_context.t4);
OFFSET(KVM_ARCH_GUEST_T5, kvm_vcpu_arch, guest_context.t5);
OFFSET(KVM_ARCH_GUEST_T6, kvm_vcpu_arch, guest_context.t6);
OFFSET(KVM_ARCH_GUEST_SEPC, kvm_vcpu_arch, guest_context.sepc);
OFFSET(KVM_ARCH_GUEST_SSTATUS, kvm_vcpu_arch, guest_context.sstatus);
OFFSET(KVM_ARCH_GUEST_HSTATUS, kvm_vcpu_arch, guest_context.hstatus);
OFFSET(KVM_ARCH_GUEST_SCOUNTEREN, kvm_vcpu_arch, guest_csr.scounteren);
OFFSET(KVM_ARCH_HOST_ZERO, kvm_vcpu_arch, host_context.zero);
OFFSET(KVM_ARCH_HOST_RA, kvm_vcpu_arch, host_context.ra);
OFFSET(KVM_ARCH_HOST_SP, kvm_vcpu_arch, host_context.sp);
OFFSET(KVM_ARCH_HOST_GP, kvm_vcpu_arch, host_context.gp);
OFFSET(KVM_ARCH_HOST_TP, kvm_vcpu_arch, host_context.tp);
OFFSET(KVM_ARCH_HOST_T0, kvm_vcpu_arch, host_context.t0);
OFFSET(KVM_ARCH_HOST_T1, kvm_vcpu_arch, host_context.t1);
OFFSET(KVM_ARCH_HOST_T2, kvm_vcpu_arch, host_context.t2);
OFFSET(KVM_ARCH_HOST_S0, kvm_vcpu_arch, host_context.s0);
OFFSET(KVM_ARCH_HOST_S1, kvm_vcpu_arch, host_context.s1);
OFFSET(KVM_ARCH_HOST_A0, kvm_vcpu_arch, host_context.a0);
OFFSET(KVM_ARCH_HOST_A1, kvm_vcpu_arch, host_context.a1);
OFFSET(KVM_ARCH_HOST_A2, kvm_vcpu_arch, host_context.a2);
OFFSET(KVM_ARCH_HOST_A3, kvm_vcpu_arch, host_context.a3);
OFFSET(KVM_ARCH_HOST_A4, kvm_vcpu_arch, host_context.a4);
OFFSET(KVM_ARCH_HOST_A5, kvm_vcpu_arch, host_context.a5);
OFFSET(KVM_ARCH_HOST_A6, kvm_vcpu_arch, host_context.a6);
OFFSET(KVM_ARCH_HOST_A7, kvm_vcpu_arch, host_context.a7);
OFFSET(KVM_ARCH_HOST_S2, kvm_vcpu_arch, host_context.s2);
OFFSET(KVM_ARCH_HOST_S3, kvm_vcpu_arch, host_context.s3);
OFFSET(KVM_ARCH_HOST_S4, kvm_vcpu_arch, host_context.s4);
OFFSET(KVM_ARCH_HOST_S5, kvm_vcpu_arch, host_context.s5);
OFFSET(KVM_ARCH_HOST_S6, kvm_vcpu_arch, host_context.s6);
OFFSET(KVM_ARCH_HOST_S7, kvm_vcpu_arch, host_context.s7);
OFFSET(KVM_ARCH_HOST_S8, kvm_vcpu_arch, host_context.s8);
OFFSET(KVM_ARCH_HOST_S9, kvm_vcpu_arch, host_context.s9);
OFFSET(KVM_ARCH_HOST_S10, kvm_vcpu_arch, host_context.s10);
OFFSET(KVM_ARCH_HOST_S11, kvm_vcpu_arch, host_context.s11);
OFFSET(KVM_ARCH_HOST_T3, kvm_vcpu_arch, host_context.t3);
OFFSET(KVM_ARCH_HOST_T4, kvm_vcpu_arch, host_context.t4);
OFFSET(KVM_ARCH_HOST_T5, kvm_vcpu_arch, host_context.t5);
OFFSET(KVM_ARCH_HOST_T6, kvm_vcpu_arch, host_context.t6);
OFFSET(KVM_ARCH_HOST_SEPC, kvm_vcpu_arch, host_context.sepc);
OFFSET(KVM_ARCH_HOST_SSTATUS, kvm_vcpu_arch, host_context.sstatus);
OFFSET(KVM_ARCH_HOST_HSTATUS, kvm_vcpu_arch, host_context.hstatus);
OFFSET(KVM_ARCH_HOST_SSCRATCH, kvm_vcpu_arch, host_sscratch);
OFFSET(KVM_ARCH_HOST_STVEC, kvm_vcpu_arch, host_stvec);
OFFSET(KVM_ARCH_HOST_SCOUNTEREN, kvm_vcpu_arch, host_scounteren);
OFFSET(KVM_ARCH_TRAP_SEPC, kvm_cpu_trap, sepc);
OFFSET(KVM_ARCH_TRAP_SCAUSE, kvm_cpu_trap, scause);
OFFSET(KVM_ARCH_TRAP_STVAL, kvm_cpu_trap, stval);
OFFSET(KVM_ARCH_TRAP_HTVAL, kvm_cpu_trap, htval);
OFFSET(KVM_ARCH_TRAP_HTINST, kvm_cpu_trap, htinst);
/* F extension */
OFFSET(KVM_ARCH_FP_F_F0, kvm_cpu_context, fp.f.f[0]);
OFFSET(KVM_ARCH_FP_F_F1, kvm_cpu_context, fp.f.f[1]);
OFFSET(KVM_ARCH_FP_F_F2, kvm_cpu_context, fp.f.f[2]);
OFFSET(KVM_ARCH_FP_F_F3, kvm_cpu_context, fp.f.f[3]);
OFFSET(KVM_ARCH_FP_F_F4, kvm_cpu_context, fp.f.f[4]);
OFFSET(KVM_ARCH_FP_F_F5, kvm_cpu_context, fp.f.f[5]);
OFFSET(KVM_ARCH_FP_F_F6, kvm_cpu_context, fp.f.f[6]);
OFFSET(KVM_ARCH_FP_F_F7, kvm_cpu_context, fp.f.f[7]);
OFFSET(KVM_ARCH_FP_F_F8, kvm_cpu_context, fp.f.f[8]);
OFFSET(KVM_ARCH_FP_F_F9, kvm_cpu_context, fp.f.f[9]);
OFFSET(KVM_ARCH_FP_F_F10, kvm_cpu_context, fp.f.f[10]);
OFFSET(KVM_ARCH_FP_F_F11, kvm_cpu_context, fp.f.f[11]);
OFFSET(KVM_ARCH_FP_F_F12, kvm_cpu_context, fp.f.f[12]);
OFFSET(KVM_ARCH_FP_F_F13, kvm_cpu_context, fp.f.f[13]);
OFFSET(KVM_ARCH_FP_F_F14, kvm_cpu_context, fp.f.f[14]);
OFFSET(KVM_ARCH_FP_F_F15, kvm_cpu_context, fp.f.f[15]);
OFFSET(KVM_ARCH_FP_F_F16, kvm_cpu_context, fp.f.f[16]);
OFFSET(KVM_ARCH_FP_F_F17, kvm_cpu_context, fp.f.f[17]);
OFFSET(KVM_ARCH_FP_F_F18, kvm_cpu_context, fp.f.f[18]);
OFFSET(KVM_ARCH_FP_F_F19, kvm_cpu_context, fp.f.f[19]);
OFFSET(KVM_ARCH_FP_F_F20, kvm_cpu_context, fp.f.f[20]);
OFFSET(KVM_ARCH_FP_F_F21, kvm_cpu_context, fp.f.f[21]);
OFFSET(KVM_ARCH_FP_F_F22, kvm_cpu_context, fp.f.f[22]);
OFFSET(KVM_ARCH_FP_F_F23, kvm_cpu_context, fp.f.f[23]);
OFFSET(KVM_ARCH_FP_F_F24, kvm_cpu_context, fp.f.f[24]);
OFFSET(KVM_ARCH_FP_F_F25, kvm_cpu_context, fp.f.f[25]);
OFFSET(KVM_ARCH_FP_F_F26, kvm_cpu_context, fp.f.f[26]);
OFFSET(KVM_ARCH_FP_F_F27, kvm_cpu_context, fp.f.f[27]);
OFFSET(KVM_ARCH_FP_F_F28, kvm_cpu_context, fp.f.f[28]);
OFFSET(KVM_ARCH_FP_F_F29, kvm_cpu_context, fp.f.f[29]);
OFFSET(KVM_ARCH_FP_F_F30, kvm_cpu_context, fp.f.f[30]);
OFFSET(KVM_ARCH_FP_F_F31, kvm_cpu_context, fp.f.f[31]);
OFFSET(KVM_ARCH_FP_F_FCSR, kvm_cpu_context, fp.f.fcsr);
/* D extension */
OFFSET(KVM_ARCH_FP_D_F0, kvm_cpu_context, fp.d.f[0]);
OFFSET(KVM_ARCH_FP_D_F1, kvm_cpu_context, fp.d.f[1]);
OFFSET(KVM_ARCH_FP_D_F2, kvm_cpu_context, fp.d.f[2]);
OFFSET(KVM_ARCH_FP_D_F3, kvm_cpu_context, fp.d.f[3]);
OFFSET(KVM_ARCH_FP_D_F4, kvm_cpu_context, fp.d.f[4]);
OFFSET(KVM_ARCH_FP_D_F5, kvm_cpu_context, fp.d.f[5]);
OFFSET(KVM_ARCH_FP_D_F6, kvm_cpu_context, fp.d.f[6]);
OFFSET(KVM_ARCH_FP_D_F7, kvm_cpu_context, fp.d.f[7]);
OFFSET(KVM_ARCH_FP_D_F8, kvm_cpu_context, fp.d.f[8]);
OFFSET(KVM_ARCH_FP_D_F9, kvm_cpu_context, fp.d.f[9]);
OFFSET(KVM_ARCH_FP_D_F10, kvm_cpu_context, fp.d.f[10]);
OFFSET(KVM_ARCH_FP_D_F11, kvm_cpu_context, fp.d.f[11]);
OFFSET(KVM_ARCH_FP_D_F12, kvm_cpu_context, fp.d.f[12]);
OFFSET(KVM_ARCH_FP_D_F13, kvm_cpu_context, fp.d.f[13]);
OFFSET(KVM_ARCH_FP_D_F14, kvm_cpu_context, fp.d.f[14]);
OFFSET(KVM_ARCH_FP_D_F15, kvm_cpu_context, fp.d.f[15]);
OFFSET(KVM_ARCH_FP_D_F16, kvm_cpu_context, fp.d.f[16]);
OFFSET(KVM_ARCH_FP_D_F17, kvm_cpu_context, fp.d.f[17]);
OFFSET(KVM_ARCH_FP_D_F18, kvm_cpu_context, fp.d.f[18]);
OFFSET(KVM_ARCH_FP_D_F19, kvm_cpu_context, fp.d.f[19]);
OFFSET(KVM_ARCH_FP_D_F20, kvm_cpu_context, fp.d.f[20]);
OFFSET(KVM_ARCH_FP_D_F21, kvm_cpu_context, fp.d.f[21]);
OFFSET(KVM_ARCH_FP_D_F22, kvm_cpu_context, fp.d.f[22]);
OFFSET(KVM_ARCH_FP_D_F23, kvm_cpu_context, fp.d.f[23]);
OFFSET(KVM_ARCH_FP_D_F24, kvm_cpu_context, fp.d.f[24]);
OFFSET(KVM_ARCH_FP_D_F25, kvm_cpu_context, fp.d.f[25]);
OFFSET(KVM_ARCH_FP_D_F26, kvm_cpu_context, fp.d.f[26]);
OFFSET(KVM_ARCH_FP_D_F27, kvm_cpu_context, fp.d.f[27]);
OFFSET(KVM_ARCH_FP_D_F28, kvm_cpu_context, fp.d.f[28]);
OFFSET(KVM_ARCH_FP_D_F29, kvm_cpu_context, fp.d.f[29]);
OFFSET(KVM_ARCH_FP_D_F30, kvm_cpu_context, fp.d.f[30]);
OFFSET(KVM_ARCH_FP_D_F31, kvm_cpu_context, fp.d.f[31]);
OFFSET(KVM_ARCH_FP_D_FCSR, kvm_cpu_context, fp.d.fcsr);
#endif
/*
* THREAD_{F,X}* might be larger than a S-type offset can handle, but
* these are used in performance-sensitive assembly so we can't resort
@@ -500,4 +660,9 @@ void asm_offsets(void)
* ensures the alignment is sane.
*/
DEFINE(PT_SIZE_ON_STACK, ALIGN(sizeof(struct pt_regs), STACK_ALIGN));
#if 0
OFFSET(KERNEL_MAP_VIRT_ADDR, kernel_mapping, virt_addr);
#endif
OFFSET(SBI_HART_BOOT_TASK_PTR_OFFSET, sbi_hart_boot_data, task_ptr);
OFFSET(SBI_HART_BOOT_STACK_PTR_OFFSET, sbi_hart_boot_data, stack_ptr);
}

26
arch/riscv/kernel/cpu_ops_sbi.c
View File

@@ -7,13 +7,22 @@
#include <linux/init.h>
#include <linux/mm.h>
#include <linux/sched/task_stack.h>
#include <asm/cpu_ops.h>
#include <asm/cpu_ops_sbi.h>
#include <asm/sbi.h>
#include <asm/smp.h>
extern char secondary_start_sbi[];
const struct cpu_operations cpu_ops_sbi;
/*
* Ordered booting via HSM brings one cpu at a time. However, cpu hotplug can
* be invoked from multiple threads in parallel. Define a per cpu data
* to handle that.
*/
DEFINE_PER_CPU(struct sbi_hart_boot_data, boot_data);
static int sbi_hsm_hart_start(unsigned long hartid, unsigned long saddr,
unsigned long priv)
{
@@ -55,14 +64,19 @@ static int sbi_hsm_hart_get_status(unsigned long hartid)
static int sbi_cpu_start(unsigned int cpuid, struct task_struct *tidle)
{
int rc;
unsigned long boot_addr = __pa_symbol(secondary_start_sbi);
int hartid = cpuid_to_hartid_map(cpuid);
unsigned long hsm_data;
struct sbi_hart_boot_data *bdata = &per_cpu(boot_data, cpuid);
cpu_update_secondary_bootdata(cpuid, tidle);
rc = sbi_hsm_hart_start(hartid, boot_addr, 0);
return rc;
/* Make sure tidle is updated */
smp_mb();
bdata->task_ptr = tidle;
bdata->stack_ptr = task_stack_page(tidle) + THREAD_SIZE;
/* Make sure boot data is updated */
smp_mb();
hsm_data = __pa(bdata);
return sbi_hsm_hart_start(hartid, boot_addr, hsm_data);
}
static int sbi_cpu_prepare(unsigned int cpuid)
@@ -97,7 +111,7 @@ static int sbi_cpu_is_stopped(unsigned int cpuid)
rc = sbi_hsm_hart_get_status(hartid);
if (rc == SBI_HSM_HART_STATUS_STOPPED)
if (rc == SBI_HSM_STATE_STOPPED)
return 0;
return rc;
}

26
arch/riscv/kernel/head.S
View File

@@ -10,6 +10,7 @@
#include <asm/thread_info.h>
#include <asm/page.h>
#include <asm/csr.h>
#include <asm/cpu_ops_sbi.h>
#include <asm/hwcap.h>
#include <asm/image.h>
#include "efi-header.S"
@@ -67,7 +68,8 @@ pe_head_start:
.align 2
#ifdef CONFIG_MMU
relocate:
.global relocate_enable_mmu
relocate_enable_mmu:
/* Relocate return address */
li a1, PAGE_OFFSET
la a2, _start
@@ -142,13 +144,15 @@ secondary_start_sbi:
la a3, .Lsecondary_park
csrw CSR_TVEC, a3
slli a3, a0, LGREG
la a4, __cpu_up_stack_pointer
la a5, __cpu_up_task_pointer
add a4, a3, a4
add a5, a3, a5
REG_L sp, (a4)
REG_L tp, (a5)
/* a0 contains the hartid & a1 contains boot data */
li a2, SBI_HART_BOOT_TASK_PTR_OFFSET
XIP_FIXUP_OFFSET a2
add a2, a2, a1
REG_L tp, (a2)
li a3, SBI_HART_BOOT_STACK_PTR_OFFSET
XIP_FIXUP_OFFSET a3
add a3, a3, a1
REG_L sp, (a3)
.global secondary_start_common
secondary_start_common:
@@ -156,7 +160,8 @@ secondary_start_common:
#ifdef CONFIG_MMU
/* Enable virtual memory and relocate to virtual address */
la a0, swapper_pg_dir
call relocate
XIP_FIXUP_OFFSET a0
call relocate_enable_mmu
#endif
call setup_trap_vector
tail smp_callin
@@ -266,7 +271,8 @@ clear_bss_done:
call setup_vm
#ifdef CONFIG_MMU
la a0, early_pg_dir
call relocate
XIP_FIXUP_OFFSET a0
call relocate_enable_mmu
#endif /* CONFIG_MMU */
call setup_trap_vector

2
arch/riscv/kernel/perf_callchain.c
View File

@@ -77,7 +77,7 @@ void perf_callchain_user(struct perf_callchain_entry_ctx *entry,
bool fill_callchain(unsigned long pc, unsigned long regs, void *entry)
{
return perf_callchain_store(entry, pc) == 0;
return perf_callchain_store(entry, pc);
}
void notrace walk_stackframe(struct task_struct *task,

3
arch/riscv/kernel/process.c
View File

@@ -23,6 +23,7 @@
#include <asm/string.h>
#include <asm/switch_to.h>
#include <asm/thread_info.h>
#include <asm/cpuidle.h>
register unsigned long gp_in_global __asm__("gp");
@@ -37,7 +38,7 @@ extern asmlinkage void ret_from_kernel_thread(void);
void arch_cpu_idle(void)
{
wait_for_interrupt();
cpu_do_idle();
raw_local_irq_enable();
}

1
arch/riscv/kernel/ptrace.c
View File

@@ -97,6 +97,7 @@ static int riscv_vr_get(struct task_struct *target,
struct __riscv_v_state *vstate = &target->thread.vstate;
membuf_write(&to, vstate, offsetof(struct __riscv_v_state, vtype));
membuf_store(&to, vstate->vtype);
return membuf_zero(&to, 4); // explicitly pad
}

87
arch/riscv/kernel/suspend.c Normal file
View File

@@ -0,0 +1,87 @@
// SPDX-License-Identifier: GPL-2.0-only
/*
* Copyright (c) 2021 Western Digital Corporation or its affiliates.
* Copyright (c) 2022 Ventana Micro Systems Inc.
*/
#include <linux/ftrace.h>
#include <asm/csr.h>
#include <asm/suspend.h>
static void suspend_save_csrs(struct suspend_context *context)
{
context->scratch = csr_read(CSR_SCRATCH);
context->tvec = csr_read(CSR_TVEC);
context->ie = csr_read(CSR_IE);
/*
* No need to save/restore IP CSR (i.e. MIP or SIP) because:
*
* 1. For no-MMU (M-mode) kernel, the bits in MIP are set by
* external devices (such as interrupt controller, timer, etc).
* 2. For MMU (S-mode) kernel, the bits in SIP are set by
* M-mode firmware and external devices (such as interrupt
* controller, etc).
*/
#ifdef CONFIG_MMU
context->satp = csr_read(CSR_SATP);
#endif
}
static void suspend_restore_csrs(struct suspend_context *context)
{
csr_write(CSR_SCRATCH, context->scratch);
csr_write(CSR_TVEC, context->tvec);
csr_write(CSR_IE, context->ie);
#ifdef CONFIG_MMU
csr_write(CSR_SATP, context->satp);
#endif
}
int cpu_suspend(unsigned long arg,
int (*finish)(unsigned long arg,
unsigned long entry,
unsigned long context))
{
int rc = 0;
struct suspend_context context = { 0 };
/* Finisher should be non-NULL */
if (!finish)
return -EINVAL;
/* Save additional CSRs*/
suspend_save_csrs(&context);
/*
* Function graph tracer state gets incosistent when the kernel
* calls functions that never return (aka finishers) hence disable
* graph tracing during their execution.
*/
pause_graph_tracing();
/* Save context on stack */
if (__cpu_suspend_enter(&context)) {
/* Call the finisher */
rc = finish(arg, __pa_symbol(__cpu_resume_enter),
(ulong)&context);
/*
* Should never reach here, unless the suspend finisher
* fails. Successful cpu_suspend() should return from
* __cpu_resume_entry()
*/
if (!rc)
rc = -EOPNOTSUPP;
}
/* Enable function graph tracer */
unpause_graph_tracing();
/* Restore additional CSRs */
suspend_restore_csrs(&context);
return rc;
}

124
arch/riscv/kernel/suspend_entry.S Normal file
View File

@@ -0,0 +1,124 @@
/* SPDX-License-Identifier: GPL-2.0-only */
/*
* Copyright (c) 2021 Western Digital Corporation or its affiliates.
* Copyright (c) 2022 Ventana Micro Systems Inc.
*/
#include <linux/linkage.h>
#include <asm/asm.h>
#include <asm/asm-offsets.h>
#include <asm/csr.h>
.text
.altmacro
.option norelax
ENTRY(__cpu_suspend_enter)
/* Save registers (except A0 and T0-T6) */
REG_S ra, (SUSPEND_CONTEXT_REGS + PT_RA)(a0)
REG_S sp, (SUSPEND_CONTEXT_REGS + PT_SP)(a0)
REG_S gp, (SUSPEND_CONTEXT_REGS + PT_GP)(a0)
REG_S tp, (SUSPEND_CONTEXT_REGS + PT_TP)(a0)
REG_S s0, (SUSPEND_CONTEXT_REGS + PT_S0)(a0)
REG_S s1, (SUSPEND_CONTEXT_REGS + PT_S1)(a0)
REG_S a1, (SUSPEND_CONTEXT_REGS + PT_A1)(a0)
REG_S a2, (SUSPEND_CONTEXT_REGS + PT_A2)(a0)
REG_S a3, (SUSPEND_CONTEXT_REGS + PT_A3)(a0)
REG_S a4, (SUSPEND_CONTEXT_REGS + PT_A4)(a0)
REG_S a5, (SUSPEND_CONTEXT_REGS + PT_A5)(a0)
REG_S a6, (SUSPEND_CONTEXT_REGS + PT_A6)(a0)
REG_S a7, (SUSPEND_CONTEXT_REGS + PT_A7)(a0)
REG_S s2, (SUSPEND_CONTEXT_REGS + PT_S2)(a0)
REG_S s3, (SUSPEND_CONTEXT_REGS + PT_S3)(a0)
REG_S s4, (SUSPEND_CONTEXT_REGS + PT_S4)(a0)
REG_S s5, (SUSPEND_CONTEXT_REGS + PT_S5)(a0)
REG_S s6, (SUSPEND_CONTEXT_REGS + PT_S6)(a0)
REG_S s7, (SUSPEND_CONTEXT_REGS + PT_S7)(a0)
REG_S s8, (SUSPEND_CONTEXT_REGS + PT_S8)(a0)
REG_S s9, (SUSPEND_CONTEXT_REGS + PT_S9)(a0)
REG_S s10, (SUSPEND_CONTEXT_REGS + PT_S10)(a0)
REG_S s11, (SUSPEND_CONTEXT_REGS + PT_S11)(a0)
/* Save CSRs */
csrr t0, CSR_EPC
REG_S t0, (SUSPEND_CONTEXT_REGS + PT_EPC)(a0)
csrr t0, CSR_STATUS
REG_S t0, (SUSPEND_CONTEXT_REGS + PT_STATUS)(a0)
csrr t0, CSR_TVAL
REG_S t0, (SUSPEND_CONTEXT_REGS + PT_BADADDR)(a0)
csrr t0, CSR_CAUSE
REG_S t0, (SUSPEND_CONTEXT_REGS + PT_CAUSE)(a0)
/* Return non-zero value */
li a0, 1
/* Return to C code */
ret
END(__cpu_suspend_enter)
ENTRY(__cpu_resume_enter)
/* Load the global pointer */
.option push
.option norelax
la gp, __global_pointer$
.option pop
#ifdef CONFIG_MMU
/* Save A0 and A1 */
add t0, a0, zero
add t1, a1, zero
/* Enable MMU */
la a0, swapper_pg_dir
XIP_FIXUP_OFFSET a0
call relocate_enable_mmu
/* Restore A0 and A1 */
add a0, t0, zero
add a1, t1, zero
#endif
/* Make A0 point to suspend context */
add a0, a1, zero
/* Restore CSRs */
REG_L t0, (SUSPEND_CONTEXT_REGS + PT_EPC)(a0)
csrw CSR_EPC, t0
REG_L t0, (SUSPEND_CONTEXT_REGS + PT_STATUS)(a0)
csrw CSR_STATUS, t0
REG_L t0, (SUSPEND_CONTEXT_REGS + PT_BADADDR)(a0)
csrw CSR_TVAL, t0
REG_L t0, (SUSPEND_CONTEXT_REGS + PT_CAUSE)(a0)
csrw CSR_CAUSE, t0
/* Restore registers (except A0 and T0-T6) */
REG_L ra, (SUSPEND_CONTEXT_REGS + PT_RA)(a0)
REG_L sp, (SUSPEND_CONTEXT_REGS + PT_SP)(a0)
REG_L gp, (SUSPEND_CONTEXT_REGS + PT_GP)(a0)
REG_L tp, (SUSPEND_CONTEXT_REGS + PT_TP)(a0)
REG_L s0, (SUSPEND_CONTEXT_REGS + PT_S0)(a0)
REG_L s1, (SUSPEND_CONTEXT_REGS + PT_S1)(a0)
REG_L a1, (SUSPEND_CONTEXT_REGS + PT_A1)(a0)
REG_L a2, (SUSPEND_CONTEXT_REGS + PT_A2)(a0)
REG_L a3, (SUSPEND_CONTEXT_REGS + PT_A3)(a0)
REG_L a4, (SUSPEND_CONTEXT_REGS + PT_A4)(a0)
REG_L a5, (SUSPEND_CONTEXT_REGS + PT_A5)(a0)
REG_L a6, (SUSPEND_CONTEXT_REGS + PT_A6)(a0)
REG_L a7, (SUSPEND_CONTEXT_REGS + PT_A7)(a0)
REG_L s2, (SUSPEND_CONTEXT_REGS + PT_S2)(a0)
REG_L s3, (SUSPEND_CONTEXT_REGS + PT_S3)(a0)
REG_L s4, (SUSPEND_CONTEXT_REGS + PT_S4)(a0)
REG_L s5, (SUSPEND_CONTEXT_REGS + PT_S5)(a0)
REG_L s6, (SUSPEND_CONTEXT_REGS + PT_S6)(a0)
REG_L s7, (SUSPEND_CONTEXT_REGS + PT_S7)(a0)
REG_L s8, (SUSPEND_CONTEXT_REGS + PT_S8)(a0)
REG_L s9, (SUSPEND_CONTEXT_REGS + PT_S9)(a0)
REG_L s10, (SUSPEND_CONTEXT_REGS + PT_S10)(a0)
REG_L s11, (SUSPEND_CONTEXT_REGS + PT_S11)(a0)
/* Return zero value */
add a0, zero, zero
/* Return to C code */
ret
END(__cpu_resume_enter)

105
arch/riscv/kvm/vcpu_sbi_hsm.c Normal file
View File

@@ -0,0 +1,105 @@
// SPDX-License-Identifier: GPL-2.0
/*
* Copyright (c) 2021 Western Digital Corporation or its affiliates.
*
* Authors:
* Atish Patra <atish.patra@wdc.com>
*/
#include <linux/errno.h>
#include <linux/err.h>
#include <linux/kvm_host.h>
#include <asm/csr.h>
#include <asm/sbi.h>
#include <asm/kvm_vcpu_sbi.h>
static int kvm_sbi_hsm_vcpu_start(struct kvm_vcpu *vcpu)
{
struct kvm_cpu_context *reset_cntx;
struct kvm_cpu_context *cp = &vcpu->arch.guest_context;
struct kvm_vcpu *target_vcpu;
unsigned long target_vcpuid = cp->a0;
target_vcpu = kvm_get_vcpu_by_id(vcpu->kvm, target_vcpuid);
if (!target_vcpu)
return -EINVAL;
if (!target_vcpu->arch.power_off)
return -EALREADY;
reset_cntx = &target_vcpu->arch.guest_reset_context;
/* start address */
reset_cntx->sepc = cp->a1;
/* target vcpu id to start */
reset_cntx->a0 = target_vcpuid;
/* private data passed from kernel */
reset_cntx->a1 = cp->a2;
kvm_make_request(KVM_REQ_VCPU_RESET, target_vcpu);
kvm_riscv_vcpu_power_on(target_vcpu);
return 0;
}
static int kvm_sbi_hsm_vcpu_stop(struct kvm_vcpu *vcpu)
{
if (vcpu->arch.power_off)
return -EINVAL;
kvm_riscv_vcpu_power_off(vcpu);
return 0;
}
static int kvm_sbi_hsm_vcpu_get_status(struct kvm_vcpu *vcpu)
{
struct kvm_cpu_context *cp = &vcpu->arch.guest_context;
unsigned long target_vcpuid = cp->a0;
struct kvm_vcpu *target_vcpu;
target_vcpu = kvm_get_vcpu_by_id(vcpu->kvm, target_vcpuid);
if (!target_vcpu)
return -EINVAL;
if (!target_vcpu->arch.power_off)
return SBI_HSM_STATE_STARTED;
else
return SBI_HSM_STATE_STOPPED;
}
static int kvm_sbi_ext_hsm_handler(struct kvm_vcpu *vcpu, struct kvm_run *run,
unsigned long *out_val,
struct kvm_cpu_trap *utrap,
bool *exit)
{
int ret = 0;
struct kvm_cpu_context *cp = &vcpu->arch.guest_context;
struct kvm *kvm = vcpu->kvm;
unsigned long funcid = cp->a6;
switch (funcid) {
case SBI_EXT_HSM_HART_START:
mutex_lock(&kvm->lock);
ret = kvm_sbi_hsm_vcpu_start(vcpu);
mutex_unlock(&kvm->lock);
break;
case SBI_EXT_HSM_HART_STOP:
ret = kvm_sbi_hsm_vcpu_stop(vcpu);
break;
case SBI_EXT_HSM_HART_STATUS:
ret = kvm_sbi_hsm_vcpu_get_status(vcpu);
if (ret >= 0) {
*out_val = ret;
ret = 0;
}
break;
default:
ret = -EOPNOTSUPP;
}
return ret;
}
const struct kvm_vcpu_sbi_extension vcpu_sbi_ext_hsm = {
.extid_start = SBI_EXT_HSM,
.extid_end = SBI_EXT_HSM,
.handler = kvm_sbi_ext_hsm_handler,
};