mirror of
https://github.com/revyos/thead-kernel.git
synced 2026-09-16 12:22:33 +02:00
Linux_SDK_V1.3.3
Signed-off-by: thead_admin <occ_thead@service.alibaba.com>
This commit is contained in:
committed by
Han Gao/Revy/Rabenda
parent
2bd2eac4a7
commit
e17ac7bab2
@@ -66,4 +66,31 @@
|
||||
#error "Unexpected __SIZEOF_SHORT__"
|
||||
#endif
|
||||
|
||||
#ifdef __ASSEMBLY__
|
||||
|
||||
/* Common assembly source macros */
|
||||
|
||||
#ifdef CONFIG_XIP_KERNEL
|
||||
.macro XIP_FIXUP_OFFSET reg
|
||||
REG_L t0, _xip_fixup
|
||||
add \reg, \reg, t0
|
||||
.endm
|
||||
.macro XIP_FIXUP_FLASH_OFFSET reg
|
||||
la t1, __data_loc
|
||||
li t0, XIP_OFFSET_MASK
|
||||
and t1, t1, t0
|
||||
li t1, XIP_OFFSET
|
||||
sub t0, t0, t1
|
||||
sub \reg, \reg, t0
|
||||
.endm
|
||||
_xip_fixup: .dword CONFIG_PHYS_RAM_BASE - CONFIG_XIP_PHYS_ADDR - XIP_OFFSET
|
||||
#else
|
||||
.macro XIP_FIXUP_OFFSET reg
|
||||
.endm
|
||||
.macro XIP_FIXUP_FLASH_OFFSET reg
|
||||
.endm
|
||||
#endif /* CONFIG_XIP_KERNEL */
|
||||
|
||||
#endif /* __ASSEMBLY__ */
|
||||
|
||||
#endif /* _ASM_RISCV_ASM_H */
|
||||
|
||||
25
arch/riscv/include/asm/cpu_ops_sbi.h
Normal file
25
arch/riscv/include/asm/cpu_ops_sbi.h
Normal file
@@ -0,0 +1,25 @@
|
||||
/* SPDX-License-Identifier: GPL-2.0-only */
|
||||
/*
|
||||
* Copyright (c) 2021 by Rivos Inc.
|
||||
*/
|
||||
#ifndef __ASM_CPU_OPS_SBI_H
|
||||
#define __ASM_CPU_OPS_SBI_H
|
||||
|
||||
#ifndef __ASSEMBLY__
|
||||
#include <linux/init.h>
|
||||
#include <linux/sched.h>
|
||||
#include <linux/threads.h>
|
||||
|
||||
/**
|
||||
* struct sbi_hart_boot_data - Hart specific boot used during booting and
|
||||
* cpu hotplug.
|
||||
* @task_ptr: A pointer to the hart specific tp
|
||||
* @stack_ptr: A pointer to the hart specific sp
|
||||
*/
|
||||
struct sbi_hart_boot_data {
|
||||
void *task_ptr;
|
||||
void *stack_ptr;
|
||||
};
|
||||
#endif
|
||||
|
||||
#endif /* ifndef __ASM_CPU_OPS_SBI_H */
|
||||
@@ -446,7 +446,7 @@ static inline pgprot_t pgprot_writecombine(pgprot_t _prot)
|
||||
|
||||
return __pgprot(prot);
|
||||
}
|
||||
|
||||
#define pgprot_dmacoherent pgprot_writecombine
|
||||
/*
|
||||
* Encode and decode a swap entry
|
||||
*
|
||||
|
||||
@@ -61,13 +61,45 @@ enum sbi_ext_hsm_fid {
|
||||
SBI_EXT_HSM_HART_START = 0,
|
||||
SBI_EXT_HSM_HART_STOP,
|
||||
SBI_EXT_HSM_HART_STATUS,
|
||||
SBI_EXT_HSM_HART_SUSPEND,
|
||||
};
|
||||
|
||||
enum sbi_hsm_hart_status {
|
||||
SBI_HSM_HART_STATUS_STARTED = 0,
|
||||
SBI_HSM_HART_STATUS_STOPPED,
|
||||
SBI_HSM_HART_STATUS_START_PENDING,
|
||||
SBI_HSM_HART_STATUS_STOP_PENDING,
|
||||
enum sbi_hsm_hart_state {
|
||||
SBI_HSM_STATE_STARTED = 0,
|
||||
SBI_HSM_STATE_STOPPED,
|
||||
SBI_HSM_STATE_START_PENDING,
|
||||
SBI_HSM_STATE_STOP_PENDING,
|
||||
SBI_HSM_STATE_SUSPENDED,
|
||||
SBI_HSM_STATE_SUSPEND_PENDING,
|
||||
SBI_HSM_STATE_RESUME_PENDING,
|
||||
};
|
||||
|
||||
#define SBI_HSM_SUSP_BASE_MASK 0x7fffffff
|
||||
#define SBI_HSM_SUSP_NON_RET_BIT 0x80000000
|
||||
#define SBI_HSM_SUSP_PLAT_BASE 0x10000000
|
||||
|
||||
#define SBI_HSM_SUSPEND_RET_DEFAULT 0x00000000
|
||||
#define SBI_HSM_SUSPEND_RET_PLATFORM SBI_HSM_SUSP_PLAT_BASE
|
||||
#define SBI_HSM_SUSPEND_RET_LAST SBI_HSM_SUSP_BASE_MASK
|
||||
#define SBI_HSM_SUSPEND_NON_RET_DEFAULT SBI_HSM_SUSP_NON_RET_BIT
|
||||
#define SBI_HSM_SUSPEND_NON_RET_PLATFORM (SBI_HSM_SUSP_NON_RET_BIT | \
|
||||
SBI_HSM_SUSP_PLAT_BASE)
|
||||
#define SBI_HSM_SUSPEND_NON_RET_LAST (SBI_HSM_SUSP_NON_RET_BIT | \
|
||||
SBI_HSM_SUSP_BASE_MASK)
|
||||
|
||||
enum sbi_ext_srst_fid {
|
||||
SBI_EXT_SRST_RESET = 0,
|
||||
};
|
||||
|
||||
enum sbi_srst_reset_type {
|
||||
SBI_SRST_RESET_TYPE_SHUTDOWN = 0,
|
||||
SBI_SRST_RESET_TYPE_COLD_REBOOT,
|
||||
SBI_SRST_RESET_TYPE_WARM_REBOOT,
|
||||
};
|
||||
|
||||
enum sbi_srst_reset_reason {
|
||||
SBI_SRST_RESET_REASON_NONE = 0,
|
||||
SBI_SRST_RESET_REASON_SYS_FAILURE,
|
||||
};
|
||||
|
||||
#define SBI_SPEC_VERSION_DEFAULT 0x1
|
||||
|
||||
36
arch/riscv/include/asm/suspend.h
Normal file
36
arch/riscv/include/asm/suspend.h
Normal file
@@ -0,0 +1,36 @@
|
||||
/* SPDX-License-Identifier: GPL-2.0-only */
|
||||
/*
|
||||
* Copyright (c) 2021 Western Digital Corporation or its affiliates.
|
||||
* Copyright (c) 2022 Ventana Micro Systems Inc.
|
||||
*/
|
||||
|
||||
#ifndef _ASM_RISCV_SUSPEND_H
|
||||
#define _ASM_RISCV_SUSPEND_H
|
||||
|
||||
#include <asm/ptrace.h>
|
||||
|
||||
struct suspend_context {
|
||||
/* Saved and restored by low-level functions */
|
||||
struct pt_regs regs;
|
||||
/* Saved and restored by high-level functions */
|
||||
unsigned long scratch;
|
||||
unsigned long tvec;
|
||||
unsigned long ie;
|
||||
#ifdef CONFIG_MMU
|
||||
unsigned long satp;
|
||||
#endif
|
||||
};
|
||||
|
||||
/* Low-level CPU suspend entry function */
|
||||
int __cpu_suspend_enter(struct suspend_context *context);
|
||||
|
||||
/* High-level CPU suspend which will save context and call finish() */
|
||||
int cpu_suspend(unsigned long arg,
|
||||
int (*finish)(unsigned long arg,
|
||||
unsigned long entry,
|
||||
unsigned long context));
|
||||
|
||||
/* Low-level CPU resume entry function */
|
||||
int __cpu_resume_enter(unsigned long hartid, unsigned long context);
|
||||
|
||||
#endif
|
||||
Reference in New Issue
Block a user