mirror of
https://github.com/revyos/thead-kernel.git
synced 2026-09-18 13:22:15 +02:00
Linux_SDK_V1.2.1
Signed-off-by: thead_admin <occ_thead@service.alibaba.com>
This commit is contained in:
thead_admin
@@ -3,7 +3,8 @@ generic-y += early_ioremap.h
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generic-y += extable.h
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generic-y += flat.h
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generic-y += kvm_para.h
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generic-y += mcs_spinlock.h
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generic-y += qspinlock.h
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generic-y += qrwlock.h
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generic-y += qrwlock_types.h
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generic-y += user.h
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generic-y += vmlinux.lds.h
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@@ -11,12 +11,36 @@
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#include <asm/barrier.h>
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#include <asm/fence.h>
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static inline ulong __xchg16_relaxed(ulong new, void *ptr)
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{
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ulong ret, tmp;
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ulong shif = ((ulong)ptr & 2) ? 16 : 0;
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ulong mask = 0xffff << shif;
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ulong *__ptr = (ulong *)((ulong)ptr & ~2);
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__asm__ __volatile__ (
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"0: lr.w %0, %2\n"
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" and %1, %0, %z3\n"
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" or %1, %1, %z4\n"
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" sc.w %1, %1, %2\n"
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" bnez %1, 0b\n"
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: "=&r" (ret), "=&r" (tmp), "+A" (*__ptr)
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: "rJ" (~mask), "rJ" (new << shif)
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: "memory");
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return (ulong)((ret & mask) >> shif);
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}
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#define __xchg_relaxed(ptr, new, size) \
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({ \
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__typeof__(ptr) __ptr = (ptr); \
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__typeof__(new) __new = (new); \
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__typeof__(*(ptr)) __ret; \
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switch (size) { \
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case 2: { \
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__ret = (__typeof__(*(ptr))) \
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__xchg16_relaxed((ulong)__new, __ptr); \
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break;} \
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case 4: \
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__asm__ __volatile__ ( \
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" amoswap.w %0, %2, %1\n" \
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@@ -13,7 +13,6 @@
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#include <linux/types.h>
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#include <linux/pgtable.h>
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#include <asm/mmiowb.h>
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#include <asm/early_ioremap.h>
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/*
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@@ -133,7 +133,7 @@ static inline u64 __raw_readq(const volatile void __iomem *addr)
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#define __io_br() do {} while (0)
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#define __io_ar(v) __asm__ __volatile__ ("fence i,r" : : : "memory")
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#define __io_bw() __asm__ __volatile__ ("fence w,o" : : : "memory")
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#define __io_aw() mmiowb_set_pending()
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#define __io_aw() __asm__ __volatile__ ("fence o,w" : : : "memory")
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#define readb(c) ({ u8 __v; __io_br(); __v = readb_cpu(c); __io_ar(__v); __v; })
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#define readw(c) ({ u16 __v; __io_br(); __v = readw_cpu(c); __io_ar(__v); __v; })
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@@ -1,15 +0,0 @@
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/* SPDX-License-Identifier: GPL-2.0 */
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#ifndef _ASM_RISCV_MMIOWB_H
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#define _ASM_RISCV_MMIOWB_H
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/*
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* "o,w" is sufficient to ensure that all writes to the device have completed
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* before the write to the spinlock is allowed to commit.
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*/
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#define mmiowb() __asm__ __volatile__ ("fence o,w" : : : "memory");
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#include <linux/smp.h>
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#include <asm-generic/mmiowb.h>
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#endif /* _ASM_RISCV_MMIOWB_H */
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@@ -1,92 +1,9 @@
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/* SPDX-License-Identifier: GPL-2.0 */
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/*
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* 'Generic' ticket-lock implementation.
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*
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* It relies on atomic_fetch_add() having well defined forward progress
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* guarantees under contention. If your architecture cannot provide this, stick
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* to a test-and-set lock.
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*
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* It also relies on atomic_fetch_add() being safe vs smp_store_release() on a
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* sub-word of the value. This is generally true for anything LL/SC although
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* you'd be hard pressed to find anything useful in architecture specifications
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* about this. If your architecture cannot do this you might be better off with
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* a test-and-set.
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*
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* It further assumes atomic_*_release() + atomic_*_acquire() is RCpc and hence
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* uses atomic_fetch_add() which is RCsc to create an RCsc hot path, along with
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* a full fence after the spin to upgrade the otherwise-RCpc
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* atomic_cond_read_acquire().
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*
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* The implementation uses smp_cond_load_acquire() to spin, so if the
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* architecture has WFE like instructions to sleep instead of poll for word
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* modifications be sure to implement that (see ARM64 for example).
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*
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*/
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#ifndef __ASM_GENERIC_SPINLOCK_H
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#define __ASM_GENERIC_SPINLOCK_H
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#include <linux/atomic.h>
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#include <asm/spinlock_types.h>
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static __always_inline void arch_spin_lock(arch_spinlock_t *lock)
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{
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u32 val = atomic_fetch_add(1<<16, lock);
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u16 ticket = val >> 16;
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if (ticket == (u16)val)
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return;
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/*
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* atomic_cond_read_acquire() is RCpc, but rather than defining a
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* custom cond_read_rcsc() here we just emit a full fence. We only
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* need the prior reads before subsequent writes ordering from
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* smb_mb(), but as atomic_cond_read_acquire() just emits reads and we
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* have no outstanding writes due to the atomic_fetch_add() the extra
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* orderings are free.
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*/
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atomic_cond_read_acquire(lock, ticket == (u16)VAL);
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smp_mb();
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}
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static __always_inline bool arch_spin_trylock(arch_spinlock_t *lock)
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{
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u32 old = atomic_read(lock);
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if ((old >> 16) != (old & 0xffff))
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return false;
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return atomic_try_cmpxchg(lock, &old, old + (1<<16)); /* SC, for RCsc */
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}
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static __always_inline void arch_spin_unlock(arch_spinlock_t *lock)
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{
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u16 *ptr = (u16 *)lock + IS_ENABLED(CONFIG_CPU_BIG_ENDIAN);
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u32 val = atomic_read(lock);
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smp_store_release(ptr, (u16)val + 1);
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}
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static __always_inline int arch_spin_is_locked(arch_spinlock_t *lock)
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{
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u32 val = atomic_read(lock);
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return ((val >> 16) != (val & 0xffff));
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}
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static __always_inline int arch_spin_is_contended(arch_spinlock_t *lock)
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{
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u32 val = atomic_read(lock);
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return (s16)((val >> 16) - (val & 0xffff)) > 1;
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}
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static __always_inline int arch_spin_value_unlocked(arch_spinlock_t lock)
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{
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return !arch_spin_is_locked(&lock);
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}
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#include <asm-generic/qspinlock.h>
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#include <asm/qrwlock.h>
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#endif /* __ASM_GENERIC_SPINLOCK_H */
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@@ -3,15 +3,7 @@
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#ifndef __ASM_GENERIC_SPINLOCK_TYPES_H
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#define __ASM_GENERIC_SPINLOCK_TYPES_H
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#include <linux/types.h>
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typedef atomic_t arch_spinlock_t;
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/*
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* qrwlock_types depends on arch_spinlock_t, so we must typedef that before the
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* include.
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*/
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#include <asm/qrwlock_types.h>
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#define __ARCH_SPIN_LOCK_UNLOCKED ATOMIC_INIT(0)
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#include <asm-generic/qspinlock_types.h>
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#include <asm-generic/qrwlock_types.h>
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#endif /* __ASM_GENERIC_SPINLOCK_TYPES_H */
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