From f722795a380c2733ac949ad3e2c254bad6b886fa Mon Sep 17 00:00:00 2001
From: Han Gao <gaohan@iscas.ac.cn>
Date: Wed, 29 Nov 2023 10:56:18 +0800
Subject: [PATCH] toolchains: fix mainline toolchain build

Signed-off-by: Han Gao <gaohan@iscas.ac.cn>
---
 arch/riscv/Makefile | 11 ++++++++---
 1 file changed, 8 insertions(+), 3 deletions(-)

diff --git a/arch/riscv/Makefile b/arch/riscv/Makefile
index 549aa0f4d..67c2117e8 100644
--- a/arch/riscv/Makefile
+++ b/arch/riscv/Makefile
@@ -50,10 +50,15 @@ endif
 # ISA string setting
 riscv-march-$(CONFIG_ARCH_RV32I)	:= rv32ima
 riscv-march-$(CONFIG_ARCH_RV64I)	:= rv64ima
-riscv-march-$(CONFIG_FPU)			:= $(riscv-march-y)fd
+riscv-march-$(CONFIG_FPU)		:= $(riscv-march-y)fd
 riscv-march-$(CONFIG_RISCV_ISA_C)	:= $(riscv-march-y)c
-riscv-march-$(CONFIG_VECTOR)		:= $(riscv-march-y)v0p7
-riscv-march-$(CONFIG_THEAD_ISA)		:= $(riscv-march-y)_xtheadc
+
+# Fix mainline build
+toolchain-have-v0p7 := $(call cc-option-yn, -march=$(riscv-march-y)v0p7)
+riscv-march-$(toolchain-have-v0p7) := $(riscv-march-y)v0p7
+
+toolchain-have-xtheadc := $(call cc-option-yn, -march=$(riscv-march-y)_xtheadc)
+riscv-march-$(toolchain-have-xtheadc) := $(riscv-march-y)_xtheadc
 
 # Newer binutils versions default to ISA spec version 20191213 which moves some
 # instructions from the I extension to the Zicsr and Zifencei extensions.