From f72e7cd0775ba52da4380f034d1b51a44eb124e6 Mon Sep 17 00:00:00 2001 From: Mingzheng Xing Date: Wed, 30 Aug 2023 21:19:50 +0800 Subject: [PATCH] feat: update gpu to Linux_SDK_V1.2.1 This version update involves a lot of content, so the previous version has been deleted and the new version has been re-merged into the kernel. The configuration file for the GPU driver originates from a previous version. Signed-off-by: Mingzheng Xing --- drivers/gpu/drm/img-rogue/allocmem.c | 21 +- drivers/gpu/drm/img-rogue/allocmem.h | 103 +- drivers/gpu/drm/img-rogue/cache_km.c | 1310 +++-------------- drivers/gpu/drm/img-rogue/cache_km.h | 21 +- .../gpu/drm/img-rogue/client_cache_bridge.h | 9 +- .../img-rogue/client_cache_direct_bridge.c | 18 +- drivers/gpu/drm/img-rogue/client_mm_bridge.h | 11 + .../drm/img-rogue/client_mm_direct_bridge.c | 29 + .../gpu/drm/img-rogue/common_cache_bridge.h | 7 +- .../gpu/drm/img-rogue/common_dmabuf_bridge.h | 50 +- drivers/gpu/drm/img-rogue/common_mm_bridge.h | 41 +- .../gpu/drm/img-rogue/common_rgxcmp_bridge.h | 1 - .../drm/img-rogue/common_rgxkicksync_bridge.h | 1 - .../gpu/drm/img-rogue/common_rgxta3d_bridge.h | 28 +- .../gpu/drm/img-rogue/common_rgxtq2_bridge.h | 4 +- .../gpu/drm/img-rogue/common_rgxtq_bridge.h | 2 +- drivers/gpu/drm/img-rogue/config_kernel.h | 21 +- drivers/gpu/drm/img-rogue/config_kernel.mk | 4 +- .../img-rogue/configs/rgxconfig_km_1.V.4.5.h | 2 + .../configs/rgxconfig_km_36.V.104.182.h | 4 + drivers/gpu/drm/img-rogue/connection_server.c | 221 ++- drivers/gpu/drm/img-rogue/connection_server.h | 9 + .../drm/img-rogue/cores/rgxcore_km_1.82.4.5.h | 2 +- .../cores/rgxcore_km_36.52.104.182.h | 2 +- drivers/gpu/drm/img-rogue/debug_common.c | 276 +++- drivers/gpu/drm/img-rogue/device.h | 78 +- drivers/gpu/drm/img-rogue/devicemem.c | 107 +- drivers/gpu/drm/img-rogue/devicemem.h | 2 +- drivers/gpu/drm/img-rogue/devicemem_server.c | 172 ++- drivers/gpu/drm/img-rogue/devicemem_server.h | 49 - .../drm/img-rogue/devicemem_server_utils.h | 16 - .../gpu/drm/img-rogue/devicemem_typedefs.h | 2 +- drivers/gpu/drm/img-rogue/devicemem_utils.c | 107 +- drivers/gpu/drm/img-rogue/devicemem_utils.h | 85 +- drivers/gpu/drm/img-rogue/di_common.h | 4 +- drivers/gpu/drm/img-rogue/di_impl_brg.c | 7 + drivers/gpu/drm/img-rogue/di_server.c | 13 +- drivers/gpu/drm/img-rogue/di_server.h | 25 +- drivers/gpu/drm/img-rogue/drm_nulldisp_drv.c | 47 +- drivers/gpu/drm/img-rogue/drm_nulldisp_gem.c | 4 +- drivers/gpu/drm/img-rogue/handle.c | 668 ++++++--- drivers/gpu/drm/img-rogue/handle.h | 15 +- drivers/gpu/drm/img-rogue/handle_types.h | 3 + drivers/gpu/drm/img-rogue/htbuffer.c | 13 +- drivers/gpu/drm/img-rogue/img_defs.h | 20 +- drivers/gpu/drm/img-rogue/img_types.h | 12 +- .../img-rogue/include/devicemem_typedefs.h | 2 +- .../gpu/drm/img-rogue/include/drm/pvr_drm.h | 18 + drivers/gpu/drm/img-rogue/include/img_defs.h | 20 +- .../include/img_drm_fourcc_internal.h | 4 +- drivers/gpu/drm/img-rogue/include/img_types.h | 12 +- .../gpu/drm/img-rogue/include/lock_types.h | 14 +- drivers/gpu/drm/img-rogue/include/log2.h | 8 +- .../gpu/drm/img-rogue/include/osfunc_common.h | 48 +- .../include/public/powervr/img_drm_fourcc.h | 3 + drivers/gpu/drm/img-rogue/include/pvr_debug.h | 141 +- .../gpu/drm/img-rogue/include/pvrsrv_errors.h | 2 + .../include/pvrsrv_memalloc_physheap.h | 128 +- .../img-rogue/include/pvrsrv_memallocflags.h | 70 +- .../drm/img-rogue/include/pvrsrv_tlcommon.h | 2 +- .../gpu/drm/img-rogue/include/pvrversion.h | 16 +- .../gpu/drm/img-rogue/include/rgx_common.h | 66 +- .../img-rogue/include/rgx_common_asserts.h | 73 + .../drm/img-rogue/include/rgx_compat_bvnc.h | 2 +- .../include/rgx_fwif_resetframework.h | 18 +- .../gpu/drm/img-rogue/include/rgx_fwif_sf.h | 54 +- .../drm/img-rogue/include/rgx_heap_firmware.h | 32 +- .../drm/img-rogue/include/rgx_hwperf_common.h | 482 ++++++ drivers/gpu/drm/img-rogue/include/rgx_meta.h | 12 +- drivers/gpu/drm/img-rogue/include/rgx_mips.h | 36 +- drivers/gpu/drm/img-rogue/include/rgx_riscv.h | 2 +- .../img-rogue/include/rogue/rgx_fwif_hwperf.h | 34 +- .../drm/img-rogue/include/rogue/rgx_fwif_km.h | 340 +++-- .../img-rogue/include/rogue/rgx_fwif_shared.h | 44 +- .../drm/img-rogue/include/rogue/rgx_heaps.h | 1 + .../drm/img-rogue/include/rogue/rgx_hwperf.h | 524 ++----- .../img-rogue/include/rogue/rgxheapconfig.h | 9 +- .../gpu/drm/img-rogue/include/servicesext.h | 24 +- .../include/sync_checkpoint_external.h | 6 +- .../img-rogue/include/virt_validation_defs.h | 63 + .../img-rogue/include/volcanic/rgx_fwif_km.h | 268 ++-- .../include/volcanic/rgx_fwif_shared.h | 32 +- .../img-rogue/include/volcanic/rgx_hwperf.h | 485 +----- .../gpu/drm/img-rogue/kernel_compatibility.h | 11 + .../gpu/drm/img-rogue/km/rgx_bvnc_defs_km.h | 76 +- .../gpu/drm/img-rogue/km/rgx_bvnc_table_km.h | 179 ++- drivers/gpu/drm/img-rogue/km/rgx_cr_defs_km.h | 46 + drivers/gpu/drm/img-rogue/km/rgxdefs_km.h | 24 +- drivers/gpu/drm/img-rogue/km/rgxmhdefs_km.h | 8 +- drivers/gpu/drm/img-rogue/km_apphint.c | 8 +- drivers/gpu/drm/img-rogue/km_apphint_defs.h | 3 +- .../drm/img-rogue/km_apphint_defs_common.h | 3 +- drivers/gpu/drm/img-rogue/lists.h | 14 +- drivers/gpu/drm/img-rogue/lock.h | 22 +- drivers/gpu/drm/img-rogue/lock_types.h | 14 +- drivers/gpu/drm/img-rogue/log2.h | 8 +- drivers/gpu/drm/img-rogue/mmu_common.c | 201 ++- drivers/gpu/drm/img-rogue/mmu_common.h | 16 + drivers/gpu/drm/img-rogue/module_common.c | 242 ++- drivers/gpu/drm/img-rogue/module_common.h | 40 +- .../gpu/drm/img-rogue/osconnection_server.h | 2 + drivers/gpu/drm/img-rogue/osdi_impl.h | 13 + drivers/gpu/drm/img-rogue/osfunc.c | 54 +- drivers/gpu/drm/img-rogue/osfunc.h | 68 +- drivers/gpu/drm/img-rogue/osfunc_arm64.c | 6 +- drivers/gpu/drm/img-rogue/osfunc_common.h | 48 +- drivers/gpu/drm/img-rogue/oskm_apphint.h | 2 +- drivers/gpu/drm/img-rogue/osmmap.h | 1 - drivers/gpu/drm/img-rogue/pdump_km.h | 77 +- drivers/gpu/drm/img-rogue/physheap.c | 543 ++++++- drivers/gpu/drm/img-rogue/physheap.h | 159 +- drivers/gpu/drm/img-rogue/physheap_config.h | 23 - drivers/gpu/drm/img-rogue/physmem.c | 101 +- drivers/gpu/drm/img-rogue/physmem.h | 29 + drivers/gpu/drm/img-rogue/physmem_dmabuf.c | 14 +- drivers/gpu/drm/img-rogue/physmem_lma.c | 309 +++- drivers/gpu/drm/img-rogue/physmem_lma.h | 4 - .../gpu/drm/img-rogue/physmem_osmem_linux.c | 24 +- drivers/gpu/drm/img-rogue/physmem_test.c | 2 - drivers/gpu/drm/img-rogue/plato_drv.h | 2 + drivers/gpu/drm/img-rogue/pmr.c | 44 +- drivers/gpu/drm/img-rogue/pmr.h | 2 +- drivers/gpu/drm/img-rogue/power.c | 11 +- drivers/gpu/drm/img-rogue/power.h | 4 +- .../drm/img-rogue/powervr/img_drm_fourcc.h | 3 + drivers/gpu/drm/img-rogue/private_data.h | 9 +- drivers/gpu/drm/img-rogue/process_stats.c | 179 +-- drivers/gpu/drm/img-rogue/process_stats.h | 33 +- drivers/gpu/drm/img-rogue/pvr_bridge_k.c | 22 +- drivers/gpu/drm/img-rogue/pvr_buffer_sync.c | 9 +- drivers/gpu/drm/img-rogue/pvr_debug.h | 141 +- drivers/gpu/drm/img-rogue/pvr_debugfs.c | 20 +- drivers/gpu/drm/img-rogue/pvr_dma_resv.h | 10 + drivers/gpu/drm/img-rogue/pvr_drm.c | 14 +- drivers/gpu/drm/img-rogue/pvr_drm.h | 18 + drivers/gpu/drm/img-rogue/pvr_fence.c | 12 +- drivers/gpu/drm/img-rogue/pvr_fence.h | 14 +- drivers/gpu/drm/img-rogue/pvr_gputrace.c | 84 +- drivers/gpu/drm/img-rogue/pvr_notifier.c | 7 +- drivers/gpu/drm/img-rogue/pvr_sync_file.c | 11 +- .../gpu/drm/img-rogue/pvr_sync_ioctl_drm.c | 10 +- .../gpu/drm/img-rogue/pvr_sync_ioctl_drm.h | 2 +- drivers/gpu/drm/img-rogue/pvrsrv.c | 732 +++------ drivers/gpu/drm/img-rogue/pvrsrv.h | 46 +- .../gpu/drm/img-rogue/pvrsrv_bridge_init.c | 160 +- .../gpu/drm/img-rogue/pvrsrv_bridge_init.h | 2 +- drivers/gpu/drm/img-rogue/pvrsrv_cleanup.h | 18 + drivers/gpu/drm/img-rogue/pvrsrv_device.h | 24 + drivers/gpu/drm/img-rogue/pvrsrv_errors.h | 2 + .../drm/img-rogue/pvrsrv_memalloc_physheap.h | 128 +- .../gpu/drm/img-rogue/pvrsrv_memallocflags.h | 70 +- drivers/gpu/drm/img-rogue/pvrsrv_tlcommon.h | 2 +- drivers/gpu/drm/img-rogue/pvrversion.h | 16 +- drivers/gpu/drm/img-rogue/ra.c | 796 ++++++---- drivers/gpu/drm/img-rogue/ra.h | 27 +- drivers/gpu/drm/img-rogue/rgx_bridge.h | 10 + drivers/gpu/drm/img-rogue/rgx_bridge_init.c | 27 +- drivers/gpu/drm/img-rogue/rgx_bridge_init.h | 3 +- drivers/gpu/drm/img-rogue/rgx_common.h | 66 +- .../gpu/drm/img-rogue/rgx_common_asserts.h | 73 + drivers/gpu/drm/img-rogue/rgx_compat_bvnc.h | 2 +- drivers/gpu/drm/img-rogue/rgx_fwif_hwperf.h | 34 +- drivers/gpu/drm/img-rogue/rgx_fwif_km.h | 340 +++-- .../drm/img-rogue/rgx_fwif_resetframework.h | 18 +- drivers/gpu/drm/img-rogue/rgx_fwif_sf.h | 54 +- drivers/gpu/drm/img-rogue/rgx_fwif_shared.h | 44 +- drivers/gpu/drm/img-rogue/rgx_heap_firmware.h | 32 +- drivers/gpu/drm/img-rogue/rgx_heaps.h | 1 + drivers/gpu/drm/img-rogue/rgx_hwperf.h | 524 ++----- drivers/gpu/drm/img-rogue/rgx_hwperf_common.h | 482 ++++++ drivers/gpu/drm/img-rogue/rgx_hwperf_table.c | 3 - drivers/gpu/drm/img-rogue/rgx_meta.h | 12 +- drivers/gpu/drm/img-rogue/rgx_mips.h | 36 +- drivers/gpu/drm/img-rogue/rgx_riscv.h | 2 +- drivers/gpu/drm/img-rogue/rgxbreakpoint.c | 5 - drivers/gpu/drm/img-rogue/rgxbvnc.c | 59 +- drivers/gpu/drm/img-rogue/rgxccb.c | 54 +- drivers/gpu/drm/img-rogue/rgxccb.h | 6 +- drivers/gpu/drm/img-rogue/rgxcompute.c | 14 +- drivers/gpu/drm/img-rogue/rgxcompute.h | 1 - drivers/gpu/drm/img-rogue/rgxdebug.c | 436 +++--- drivers/gpu/drm/img-rogue/rgxdebug.h | 43 +- drivers/gpu/drm/img-rogue/rgxdevice.h | 11 + drivers/gpu/drm/img-rogue/rgxfwdbg.c | 4 +- drivers/gpu/drm/img-rogue/rgxfwimageutils.c | 16 + drivers/gpu/drm/img-rogue/rgxfwutils.c | 703 ++++++--- drivers/gpu/drm/img-rogue/rgxfwutils.h | 140 +- drivers/gpu/drm/img-rogue/rgxheapconfig.h | 9 +- drivers/gpu/drm/img-rogue/rgxhwperf.c | 166 ++- drivers/gpu/drm/img-rogue/rgxhwperf_common.c | 151 +- drivers/gpu/drm/img-rogue/rgxhwperf_common.h | 24 + drivers/gpu/drm/img-rogue/rgxinit.c | 586 ++++---- drivers/gpu/drm/img-rogue/rgxkicksync.c | 12 +- drivers/gpu/drm/img-rogue/rgxkicksync.h | 1 - drivers/gpu/drm/img-rogue/rgxlayer_impl.c | 44 +- drivers/gpu/drm/img-rogue/rgxmem.c | 16 +- drivers/gpu/drm/img-rogue/rgxmipsmmuinit.c | 37 + drivers/gpu/drm/img-rogue/rgxmipsmmuinit.h | 3 + drivers/gpu/drm/img-rogue/rgxpower.c | 110 +- drivers/gpu/drm/img-rogue/rgxregconfig.c | 4 - drivers/gpu/drm/img-rogue/rgxshader.c | 19 +- drivers/gpu/drm/img-rogue/rgxshader.h | 4 +- drivers/gpu/drm/img-rogue/rgxsrvinit.c | 202 ++- drivers/gpu/drm/img-rogue/rgxstartstop.c | 187 ++- drivers/gpu/drm/img-rogue/rgxta3d.c | 69 +- drivers/gpu/drm/img-rogue/rgxta3d.h | 11 +- drivers/gpu/drm/img-rogue/rgxtdmtransfer.c | 26 +- drivers/gpu/drm/img-rogue/rgxtdmtransfer.h | 2 +- drivers/gpu/drm/img-rogue/rgxtimecorr.c | 2 +- drivers/gpu/drm/img-rogue/rgxtimerquery.c | 2 +- drivers/gpu/drm/img-rogue/rgxtransfer.c | 135 +- drivers/gpu/drm/img-rogue/rgxtransfer.h | 2 +- drivers/gpu/drm/img-rogue/rgxutils.c | 12 +- drivers/gpu/drm/img-rogue/ri_server.c | 11 +- .../gpu/drm/img-rogue/server_cache_bridge.c | 17 +- drivers/gpu/drm/img-rogue/server_cmm_bridge.c | 17 +- .../server_devicememhistory_bridge.c | 7 +- drivers/gpu/drm/img-rogue/server_di_bridge.c | 12 +- .../gpu/drm/img-rogue/server_dmabuf_bridge.c | 345 +++-- .../drm/img-rogue/server_htbuffer_bridge.c | 10 +- drivers/gpu/drm/img-rogue/server_mm_bridge.c | 368 ++++- .../gpu/drm/img-rogue/server_pvrtl_bridge.c | 14 +- .../img-rogue/server_rgxbreakpoint_bridge.c | 8 +- .../gpu/drm/img-rogue/server_rgxcmp_bridge.c | 15 +- .../drm/img-rogue/server_rgxfwdbg_bridge.c | 5 +- .../drm/img-rogue/server_rgxhwperf_bridge.c | 5 +- .../drm/img-rogue/server_rgxkicksync_bridge.c | 15 +- .../img-rogue/server_rgxregconfig_bridge.c | 8 +- .../gpu/drm/img-rogue/server_rgxta3d_bridge.c | 177 ++- .../img-rogue/server_rgxtimerquery_bridge.c | 5 +- .../gpu/drm/img-rogue/server_rgxtq2_bridge.c | 41 +- .../gpu/drm/img-rogue/server_rgxtq_bridge.c | 21 +- drivers/gpu/drm/img-rogue/server_ri_bridge.c | 12 +- .../gpu/drm/img-rogue/server_srvcore_bridge.c | 28 +- .../gpu/drm/img-rogue/server_sync_bridge.c | 14 +- .../img-rogue/server_synctracking_bridge.c | 12 +- .../drm/img-rogue/services_kernel_client.h | 6 +- drivers/gpu/drm/img-rogue/servicesext.h | 24 +- drivers/gpu/drm/img-rogue/srvcore.c | 18 +- drivers/gpu/drm/img-rogue/srvcore.h | 13 + drivers/gpu/drm/img-rogue/sync.c | 22 +- drivers/gpu/drm/img-rogue/sync_checkpoint.c | 127 +- drivers/gpu/drm/img-rogue/sync_checkpoint.h | 7 +- .../drm/img-rogue/sync_checkpoint_external.h | 6 +- .../drm/img-rogue/sync_checkpoint_internal.h | 8 +- .../gpu/drm/img-rogue/sync_fallback_server.h | 3 +- drivers/gpu/drm/img-rogue/tlclient.c | 12 +- drivers/gpu/drm/img-rogue/tlstream.c | 5 +- drivers/gpu/drm/img-rogue/vmm_impl.h | 2 +- drivers/gpu/drm/img-rogue/vmm_pvz_client.c | 2 +- 250 files changed, 10635 insertions(+), 7697 deletions(-) create mode 100644 drivers/gpu/drm/img-rogue/include/rgx_common_asserts.h create mode 100644 drivers/gpu/drm/img-rogue/include/rgx_hwperf_common.h create mode 100644 drivers/gpu/drm/img-rogue/include/virt_validation_defs.h create mode 100644 drivers/gpu/drm/img-rogue/rgx_common_asserts.h create mode 100644 drivers/gpu/drm/img-rogue/rgx_hwperf_common.h diff --git a/drivers/gpu/drm/img-rogue/allocmem.c b/drivers/gpu/drm/img-rogue/allocmem.c index 3b81559a5..5d7c85da1 100644 --- a/drivers/gpu/drm/img-rogue/allocmem.c +++ b/drivers/gpu/drm/img-rogue/allocmem.c @@ -54,19 +54,6 @@ CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. #endif #include "osfunc.h" -/* - * DEBUG_MEMSTATS_ALLOC_RECORD_VALUES needs to be different from - * DEBUG_MEMSTATS_VALUES defined in process_stats.h. - * The reason for this is that the file and line where the allocation happens - * are tracked from the OSAllocMem params. If DEBUG_MEMSTATS_VALUES were to be - * used, all OSAllocMem allocation statistics would point to allocmem.c, which - * is not expected behaviour. - */ -#if defined(PVRSRV_DEBUG_LINUX_MEMORY_STATS_ON) -#define DEBUG_MEMSTATS_ALLOC_RECORD_VALUES ,pvAllocFromFile, ui32AllocFromLine -#else -#define DEBUG_MEMSTATS_ALLOC_RECORD_VALUES -#endif /* * When memory statistics are disabled, memory records are used instead. @@ -167,7 +154,7 @@ static inline void _pvr_alloc_stats_add(void *pvAddr, IMG_UINT32 ui32Size DEBUG_ ksize(pvAddr), NULL, OSGetCurrentClientProcessIDKM() - DEBUG_MEMSTATS_ALLOC_RECORD_VALUES); + DEBUG_MEMSTATS_ARGS); #else { /* Store the PID in the final additional 4 bytes allocated */ @@ -189,7 +176,7 @@ static inline void _pvr_alloc_stats_add(void *pvAddr, IMG_UINT32 ui32Size DEBUG_ ((ui32Size + PAGE_SIZE-1) & ~(PAGE_SIZE-1)), NULL, OSGetCurrentClientProcessIDKM() - DEBUG_MEMSTATS_ALLOC_RECORD_VALUES); + DEBUG_MEMSTATS_ARGS); #else PVRSRVStatsIncrMemAllocStatAndTrack(PVRSRV_MEM_ALLOC_TYPE_VMALLOC, ((ui32Size + PAGE_SIZE-1) & ~(PAGE_SIZE-1)), @@ -256,7 +243,7 @@ void *(OSAllocMem)(IMG_UINT32 ui32Size DEBUG_MEMSTATS_PARAMS) if (pvRet != NULL) { - _pvr_alloc_stats_add(pvRet, ui32Size DEBUG_MEMSTATS_ALLOC_RECORD_VALUES); + _pvr_alloc_stats_add(pvRet, ui32Size DEBUG_MEMSTATS_ARGS); } return pvRet; @@ -286,7 +273,7 @@ void *(OSAllocZMem)(IMG_UINT32 ui32Size DEBUG_MEMSTATS_PARAMS) if (pvRet != NULL) { - _pvr_alloc_stats_add(pvRet, ui32Size DEBUG_MEMSTATS_ALLOC_RECORD_VALUES); + _pvr_alloc_stats_add(pvRet, ui32Size DEBUG_MEMSTATS_ARGS); } return pvRet; diff --git a/drivers/gpu/drm/img-rogue/allocmem.h b/drivers/gpu/drm/img-rogue/allocmem.h index d0ce7a7ff..3de9e6781 100644 --- a/drivers/gpu/drm/img-rogue/allocmem.h +++ b/drivers/gpu/drm/img-rogue/allocmem.h @@ -51,7 +51,47 @@ CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. extern "C" { #endif -#if !defined(PVRSRV_DEBUG_LINUX_MEMORY_STATS) || !defined(DEBUG) || !defined(PVRSRV_ENABLE_PROCESS_STATS) || !defined(PVRSRV_ENABLE_MEMORY_STATS) || defined(DOXYGEN) +/* + * PVRSRV_ENABLE_PROCESS_STATS enables process statistics regarding events, + * resources and memory across all processes + * PVRSRV_ENABLE_MEMORY_STATS enables recording of Linux kernel memory + * allocations, provided that PVRSRV_ENABLE_PROCESS_STATS is enabled + * - Output can be found in: + * /(sys/kernel/debug|proc)/pvr/proc_stats/[live|retired]_pids_stats/mem_area + * PVRSRV_DEBUG_LINUX_MEMORY_STATS provides more details about memory + * statistics in conjunction with PVRSRV_ENABLE_MEMORY_STATS + * PVRSRV_DEBUG_LINUX_MEMORY_STATS_ON is defined to encompass both memory + * allocation statistics functionalities described above in a single macro + */ +#if defined(PVRSRV_ENABLE_PROCESS_STATS) && defined(PVRSRV_ENABLE_MEMORY_STATS) && defined(PVRSRV_DEBUG_LINUX_MEMORY_STATS) && defined(DEBUG) +#define PVRSRV_DEBUG_LINUX_MEMORY_STATS_ON +#endif + +/* + * When using detailed memory allocation statistics, the line number and + * file name where the allocation happened are also provided. + * When this feature is not used, these parameters are not needed. + */ +#if defined(PVRSRV_DEBUG_LINUX_MEMORY_STATS_ON) +#define DEBUG_MEMSTATS_PARAMS ,void *pvAllocFromFile, IMG_UINT32 ui32AllocFromLine +#define DEBUG_MEMSTATS_ARGS ,pvAllocFromFile, ui32AllocFromLine +#define DEBUG_MEMSTATS_UNREF (void)pvAllocFromFile; (void)ui32AllocFromLine; +#define DEBUG_MEMSTATS_VALUES ,__FILE__, __LINE__ +#else +#define DEBUG_MEMSTATS_PARAMS /*!< + * Used for PVRSRV_DEBUG_LINUX_MEMORY_STATS_ON + * build option. */ +#define DEBUG_MEMSTATS_ARGS /*!< + * Used for PVRSRV_DEBUG_LINUX_MEMORY_STATS_ON + * build option. */ +#define DEBUG_MEMSTATS_UNREF /*!< + * Used for PVRSRV_DEBUG_LINUX_MEMORY_STATS_ON + * build option. */ +#define DEBUG_MEMSTATS_VALUES /*!< + * Used for PVRSRV_DEBUG_LINUX_MEMORY_STATS_ON + * build option. */ +#endif + /**************************************************************************/ /*! @Function OSAllocMem @@ -62,8 +102,13 @@ extern "C" { @Return Pointer to allocated memory on success. Otherwise NULL. */ /**************************************************************************/ +#if defined(DOXYGEN) void *OSAllocMem(IMG_UINT32 ui32Size); -#define OSAllocMem(_size) (OSAllocMem)((_size)) +#else +void *OSAllocMem(IMG_UINT32 ui32Size DEBUG_MEMSTATS_PARAMS); +#define OSAllocMem(_size) (OSAllocMem)((_size) DEBUG_MEMSTATS_VALUES) +#endif + /**************************************************************************/ /*! @Function OSAllocZMem @Description Allocates CPU memory and initializes the contents to zero. @@ -73,27 +118,25 @@ void *OSAllocMem(IMG_UINT32 ui32Size); @Return Pointer to allocated memory on success. Otherwise NULL. */ /**************************************************************************/ +#if defined(DOXYGEN) void *OSAllocZMem(IMG_UINT32 ui32Size); -#define OSAllocZMem(_size) (OSAllocZMem)((_size)) - #else -void *OSAllocMem(IMG_UINT32 ui32Size, void *pvAllocFromFile, IMG_UINT32 ui32AllocFromLine); -void *OSAllocZMem(IMG_UINT32 ui32Size, void *pvAllocFromFile, IMG_UINT32 ui32AllocFromLine); -#define OSAllocMem(_size) (OSAllocMem)((_size), (__FILE__), (__LINE__)) -#define OSAllocZMem(_size) (OSAllocZMem)((_size), (__FILE__), (__LINE__)) +void *OSAllocZMem(IMG_UINT32 ui32Size DEBUG_MEMSTATS_PARAMS); +#define OSAllocZMem(_size) (OSAllocZMem)((_size) DEBUG_MEMSTATS_VALUES) #endif + /**************************************************************************/ /*! @Function OSAllocMemNoStats @Description Allocates CPU memory. Contents are uninitialized. - If passed a size of zero, function should not assert, - but just return a NULL pointer. - The allocated memory is not accounted for by process stats. - Process stats are an optional feature (enabled only when - PVRSRV_ENABLE_PROCESS_STATS is defined) which track the amount - of memory allocated to help in debugging. Where this is not - required, OSAllocMem() and OSAllocMemNoStats() equate to - the same operation. + If passed a size of zero, function should not assert, + but just return a NULL pointer. + The allocated memory is not accounted for by process stats. + Process stats are an optional feature (enabled only when + PVRSRV_ENABLE_PROCESS_STATS is defined) which track the amount + of memory allocated to help in debugging. Where this is not + required, OSAllocMem() and OSAllocMemNoStats() equate to + the same operation. @Input ui32Size Size of required allocation (in bytes) @Return Pointer to allocated memory on success. Otherwise NULL. @@ -103,14 +146,14 @@ void *OSAllocMemNoStats(IMG_UINT32 ui32Size); /**************************************************************************/ /*! @Function OSAllocZMemNoStats @Description Allocates CPU memory and initializes the contents to zero. - If passed a size of zero, function should not assert, - but just return a NULL pointer. - The allocated memory is not accounted for by process stats. - Process stats are an optional feature (enabled only when - PVRSRV_ENABLE_PROCESS_STATS is defined) which track the amount - of memory allocated to help in debugging. Where this is not - required, OSAllocZMem() and OSAllocZMemNoStats() equate to - the same operation. + If passed a size of zero, function should not assert, + but just return a NULL pointer. + The allocated memory is not accounted for by process stats. + Process stats are an optional feature (enabled only when + PVRSRV_ENABLE_PROCESS_STATS is defined) which track the amount + of memory allocated to help in debugging. Where this is not + required, OSAllocZMem() and OSAllocZMemNoStats() equate to + the same operation. @Input ui32Size Size of required allocation (in bytes) @Return Pointer to allocated memory on success. Otherwise NULL. @@ -128,12 +171,12 @@ void OSFreeMem(void *pvCpuVAddr); /**************************************************************************/ /*! @Function OSFreeMemNoStats @Description Frees previously allocated CPU memory. - The freed memory does not update the figures in process stats. - Process stats are an optional feature (enabled only when - PVRSRV_ENABLE_PROCESS_STATS is defined) which track the amount - of memory allocated to help in debugging. Where this is not - required, OSFreeMem() and OSFreeMemNoStats() equate to the - same operation. + The freed memory does not update the figures in process stats. + Process stats are an optional feature (enabled only when + PVRSRV_ENABLE_PROCESS_STATS is defined) which track the amount + of memory allocated to help in debugging. Where this is not + required, OSFreeMem() and OSFreeMemNoStats() equate to the + same operation. @Input pvCpuVAddr Pointer to the memory to be freed. @Return None. */ /**************************************************************************/ diff --git a/drivers/gpu/drm/img-rogue/cache_km.c b/drivers/gpu/drm/img-rogue/cache_km.c index dc85fc4b9..71ed28342 100644 --- a/drivers/gpu/drm/img-rogue/cache_km.c +++ b/drivers/gpu/drm/img-rogue/cache_km.c @@ -86,32 +86,22 @@ CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. #define DECR_WRAP(x) ((x-1) < 0 ? (CACHEOP_STATS_ITEMS_MAX-1) : (x-1)) #if defined(PVRSRV_ENABLE_GPU_MEMORY_INFO) && defined(DEBUG) /* Refer to CacheOpStatsExecLogHeader() for header item names */ -#define CACHEOP_RI_PRINTF_HEADER "%-8s %-8s %-10s %-10s %-5s %-16s %-16s %-10s %-10s %-18s %-18s %-12s" -#define CACHEOP_RI_PRINTF "%-8d %-8d %-10s %-10s %-5s 0x%-14llx 0x%-14llx 0x%-8llx 0x%-8llx %-18llu %-18llu 0x%-10x\n" +#define CACHEOP_RI_PRINTF_HEADER "%-8s %-8s %-10s %-10s %-5s %-16s %-16s %-10s %-10s %-18s" +#define CACHEOP_RI_PRINTF "%-8d %-8d %-10s %-10s %-5s 0x%-14llx 0x%-14llx 0x%-8llx 0x%-8llx %-18llu\n" #else -#define CACHEOP_PRINTF_HEADER "%-8s %-8s %-10s %-10s %-5s %-10s %-10s %-18s %-18s %-12s" -#define CACHEOP_PRINTF "%-8d %-8d %-10s %-10s %-5s 0x%-8llx 0x%-8llx %-18llu %-18llu 0x%-10x\n" +#define CACHEOP_PRINTF_HEADER "%-8s %-8s %-10s %-10s %-5s %-10s %-10s %-18s" +#define CACHEOP_PRINTF "%-8d %-8d %-10s %-10s %-5s 0x%-8llx 0x%-8llx %-18llu\n" #endif #endif //#define CACHEOP_NO_CACHE_LINE_ALIGNED_ROUNDING /* Force OS page (not cache line) flush granularity */ #define CACHEOP_PVR_ASSERT(x) /* Define as PVR_ASSERT(x), enable for swdev & testing */ -#if defined(PVRSRV_SERVER_THREADS_INDEFINITE_SLEEP) -#define CACHEOP_THREAD_WAIT_TIMEOUT 0ULL /* Wait indefinitely */ -#else -#define CACHEOP_THREAD_WAIT_TIMEOUT 500000ULL /* Wait 500ms between wait unless woken-up on demand */ -#endif -#define CACHEOP_FENCE_WAIT_TIMEOUT 1000ULL /* Wait 1ms between wait events unless woken-up */ -#define CACHEOP_FENCE_RETRY_ABORT 1000ULL /* Fence retries that aborts fence operation */ -#define CACHEOP_SEQ_MIDPOINT (IMG_UINT32) 0x7FFFFFFF /* Where seqNum(s) are rebase, compared at */ -#define CACHEOP_ABORT_FENCE_ERROR_STRING "detected stalled client, retrying cacheop fence" #define CACHEOP_DEVMEM_OOR_ERROR_STRING "cacheop device memory request is out of range" #define CACHEOP_MAX_DEBUG_MESSAGE_LEN 160 typedef struct _CACHEOP_WORK_ITEM_ { PMR *psPMR; - IMG_UINT32 ui32OpSeqNum; IMG_DEVMEM_SIZE_T uiSize; PVRSRV_CACHE_OP uiCacheOp; IMG_DEVMEM_OFFSET_T uiOffset; @@ -119,16 +109,10 @@ typedef struct _CACHEOP_WORK_ITEM_ SYNC_TIMELINE_OBJ sSWTimelineObj; PVRSRV_DEVICE_NODE *psDevNode; #if defined(CACHEOP_DEBUG) - IMG_UINT64 ui64EnqueuedTime; - IMG_UINT64 ui64DequeuedTime; - IMG_UINT64 ui64ExecuteTime; - IMG_BOOL bDeferred; + IMG_UINT64 ui64StartTime; + IMG_UINT64 ui64EndTime; IMG_BOOL bKMReq; - IMG_BOOL bUMF; IMG_PID pid; -#if defined(PVRSRV_ENABLE_GPU_MEMORY_INFO) && defined(DEBUG) - RGXFWIF_DM eFenceOpType; -#endif #endif } CACHEOP_WORK_ITEM; @@ -136,21 +120,15 @@ typedef struct _CACHEOP_STATS_EXEC_ITEM_ { IMG_UINT32 ui32DeviceID; IMG_PID pid; - IMG_UINT32 ui32OpSeqNum; PVRSRV_CACHE_OP uiCacheOp; IMG_DEVMEM_SIZE_T uiOffset; IMG_DEVMEM_SIZE_T uiSize; - IMG_UINT64 ui64EnqueuedTime; - IMG_UINT64 ui64DequeuedTime; - IMG_UINT64 ui64ExecuteTime; - IMG_BOOL bIsFence; + IMG_UINT64 ui64StartTime; + IMG_UINT64 ui64EndTime; IMG_BOOL bKMReq; - IMG_BOOL bUMF; - IMG_BOOL bDeferred; #if defined(PVRSRV_ENABLE_GPU_MEMORY_INFO) && defined(DEBUG) IMG_DEV_VIRTADDR sDevVAddr; IMG_DEV_PHYADDR sDevPAddr; - RGXFWIF_DM eFenceOpType; #endif } CACHEOP_STATS_EXEC_ITEM; @@ -182,112 +160,31 @@ typedef struct _CACHEOP_WORK_QUEUE_ IMG_UINT32 uiLineShift; IMG_UINT32 uiPageShift; OS_CACHE_OP_ADDR_TYPE uiCacheOpAddrType; -/* - CacheOp deferred queueing protocol - + Implementation geared for performance, atomic counter based - - Value Space is 0 -> 1 -> 2 -> 3 -> 4 -> 5 -> 6 -> 7 -> 8 -> n. - - Index Space is 0 -> 1 -> 2 -> 3 -> 0 -> 1 -> 2 -> 3 -> 0 -> m. - - Index = Value modulo CACHEOP_INDICES_LOG2_SIZE. - + Write counter never collides with read counter in index space - - Unless at start of day when both are initialised to zero. - - This means we sacrifice one entry when the queue is full. - - Incremented by producer - - Value space tracks total number of CacheOps queued. - - Index space identifies CacheOp CCB queue index. - + Read counter increments towards write counter in value space - - Empty queue occurs when read equals write counter. - - Wrap-round logic handled by consumer as/when needed. - - Incremented by consumer - - Value space tracks total # of CacheOps executed. - - Index space identifies CacheOp CCB queue index. - + Total queued size adjusted up/down during write/read activity - - Counter might overflow but does not compromise framework. - */ - ATOMIC_T hReadCounter; - ATOMIC_T hWriteCounter; -/* - CacheOp sequence numbers - + hCommonSeqNum: - - Common sequence, numbers every CacheOp operation in both UM/KM. - - In KM - - Every deferred CacheOp (on behalf of UM) gets a unique seqNum. - - Last executed deferred CacheOp updates gsCwq.hCompletedSeqNum. - - Under debug, all CacheOp gets a unique seqNum for tracking. - - This includes all UM/KM synchronous non-deferred CacheOp(s) - - In UM - - CacheOp(s) discarding happens in both UM and KM space. - + hCompletedSeqNum: - - Tracks last executed KM/deferred RBF/Global CacheOp(s) - */ - ATOMIC_T hCommonSeqNum; - ATOMIC_T hCompletedSeqNum; -/* - CacheOp information page - + psInfoPagePMR: - - Single system-wide OS page that is multi-mapped in UM/KM. - - Mapped into clients using read-only memory protection. - - Mapped into server using read/write memory protection. - - Contains information pertaining to cache framework. - + pui32InfoPage: - - Server linear address pointer to said information page. - - Each info-page entry currently of sizeof(IMG_UINT32). - */ PMR *psInfoPagePMR; IMG_UINT32 *pui32InfoPage; -/* - CacheOp deferred work-item queue - + CACHEOP_INDICES_LOG2_SIZE - */ -#define CACHEOP_INDICES_LOG2_SIZE (4) -#define CACHEOP_INDICES_MAX (1 << CACHEOP_INDICES_LOG2_SIZE) -#define CACHEOP_INDICES_MASK (CACHEOP_INDICES_MAX-1) - CACHEOP_WORK_ITEM asWorkItems[CACHEOP_INDICES_MAX]; + #if defined(CACHEOP_DEBUG) /* CacheOp statistics */ DI_ENTRY *psDIEntry; IMG_HANDLE hStatsExecLock; - IMG_UINT32 ui32ServerASync; - IMG_UINT32 ui32ServerSyncVA; - IMG_UINT32 ui32ServerSync; - IMG_UINT32 ui32ServerRBF; - IMG_UINT32 ui32ServerDTL; - IMG_UINT32 ui32ClientSync; - IMG_UINT32 ui32ClientRBF; - IMG_UINT32 ui32TotalFenceOps; - IMG_UINT32 ui32TotalExecOps; + + IMG_UINT32 ui32ServerOps; + IMG_UINT32 ui32ClientOps; + IMG_UINT32 ui32TotalOps; + IMG_UINT32 ui32ServerOpUsedUMVA; IMG_UINT32 ui32AvgExecTime; IMG_UINT32 ui32AvgExecTimeRemainder; - IMG_UINT32 ui32AvgFenceTime; - IMG_UINT32 ui32AvgFenceTimeRemainder; + IMG_INT32 i32StatsExecWriteIdx; CACHEOP_STATS_EXEC_ITEM asStatsExecuted[CACHEOP_STATS_ITEMS_MAX]; #endif -/* - CacheOp (re)configuration - */ + DI_ENTRY *psConfigTune; IMG_HANDLE hConfigLock; -/* - CacheOp deferred worker thread - + eConfig - - Runtime configuration - + hWorkerThread - - CacheOp thread handler - + hThreadWakeUpEvtObj - - Event object to drive CacheOp worker thread sleep/wake-ups. - + hClientWakeUpEvtObj - - Event object to unblock stalled clients waiting on queue. - */ CACHEOP_CONFIG eConfig; IMG_UINT32 ui32Config; - IMG_HANDLE hWorkerThread; - IMG_HANDLE hDeferredLock; - IMG_HANDLE hThreadWakeUpEvtObj; - IMG_HANDLE hClientWakeUpEvtObj; - IMG_UINT32 ui32FenceWaitTimeUs; - IMG_UINT32 ui32FenceRetryAbort; IMG_BOOL bSupportsUMFlush; } CACHEOP_WORK_QUEUE; @@ -296,48 +193,6 @@ static CACHEOP_WORK_QUEUE gsCwq; #define CacheOpConfigSupports(e) ((gsCwq.eConfig & (e)) ? IMG_TRUE : IMG_FALSE) -static INLINE IMG_UINT32 CacheOpIdxRead(ATOMIC_T *phCounter) -{ - IMG_UINT32 ui32Idx = OSAtomicRead(phCounter); - return ui32Idx & CACHEOP_INDICES_MASK; -} - -static INLINE IMG_UINT32 CacheOpIdxIncrement(ATOMIC_T *phCounter) -{ - IMG_UINT32 ui32Idx = OSAtomicIncrement(phCounter); - return ui32Idx & CACHEOP_INDICES_MASK; -} - -static INLINE IMG_UINT32 CacheOpIdxNext(ATOMIC_T *phCounter) -{ - IMG_UINT32 ui32Idx = OSAtomicRead(phCounter); - return ++ui32Idx & CACHEOP_INDICES_MASK; -} - -static INLINE IMG_UINT32 CacheOpIdxSpan(ATOMIC_T *phLhs, ATOMIC_T *phRhs) -{ - return OSAtomicRead(phLhs) - OSAtomicRead(phRhs); -} - -/* Callback to dump info of cacheop thread in debug_dump */ -static void CacheOpThreadDumpInfo(DUMPDEBUG_PRINTF_FUNC* pfnDumpDebugPrintf, - void *pvDumpDebugFile) -{ - PVR_DUMPDEBUG_LOG(" Configuration: QSZ: %d, UKT: %d, KDFT: %d, " - "LINESIZE: %d, PGSIZE: %d, KDF: %s, " - "URBF: %s", - CACHEOP_INDICES_MAX, - gsCwq.pui32InfoPage[CACHEOP_INFO_UMKMTHRESHLD], - gsCwq.pui32InfoPage[CACHEOP_INFO_KMDFTHRESHLD], - gsCwq.pui32InfoPage[CACHEOP_INFO_LINESIZE], - gsCwq.pui32InfoPage[CACHEOP_INFO_PGSIZE], - gsCwq.eConfig & CACHEOP_CONFIG_KDF ? "Yes" : "No", - gsCwq.eConfig & CACHEOP_CONFIG_URBF ? "Yes" : "No" - ); - PVR_DUMPDEBUG_LOG(" Pending deferred CacheOp entries : %u", - CacheOpIdxSpan(&gsCwq.hWriteCounter, &gsCwq.hReadCounter)); -} - #if defined(CACHEOP_DEBUG) static INLINE void CacheOpStatsExecLogHeader(IMG_CHAR szBuffer[CACHEOP_MAX_DEBUG_MESSAGE_LEN]) { @@ -350,29 +205,24 @@ static INLINE void CacheOpStatsExecLogHeader(IMG_CHAR szBuffer[CACHEOP_MAX_DEBUG "DevID", "Pid", "CacheOp", - " Type", - "Mode", + "Type", + "Origin", #if defined(PVRSRV_ENABLE_GPU_MEMORY_INFO) && defined(DEBUG) "DevVAddr", "DevPAddr", #endif "Offset", "Size", - "xTime (us)", - "qTime (us)", - "SeqNum"); + "xTime (us)"); } static void CacheOpStatsExecLogWrite(CACHEOP_WORK_ITEM *psCacheOpWorkItem) { - IMG_UINT64 ui64ExecuteTime; - IMG_UINT64 ui64EnqueuedTime; IMG_INT32 i32WriteOffset; - - if (!psCacheOpWorkItem->ui32OpSeqNum && !psCacheOpWorkItem->uiCacheOp) + IMG_UINT32 ui32ExecTime; + printk("log write\n"); + if (!psCacheOpWorkItem->uiCacheOp) { - /* This breaks the logic of read-out, so we do not queue items - with zero sequence number and no CacheOp */ return; } else if (psCacheOpWorkItem->bKMReq && !CacheOpConfigSupports(CACHEOP_CONFIG_KLOG)) @@ -384,21 +234,16 @@ static void CacheOpStatsExecLogWrite(CACHEOP_WORK_ITEM *psCacheOpWorkItem) OSLockAcquire(gsCwq.hStatsExecLock); i32WriteOffset = gsCwq.i32StatsExecWriteIdx; + gsCwq.i32StatsExecWriteIdx = INCR_WRAP(gsCwq.i32StatsExecWriteIdx); gsCwq.asStatsExecuted[i32WriteOffset].ui32DeviceID = psCacheOpWorkItem->psDevNode ? psCacheOpWorkItem->psDevNode->sDevId.ui32InternalID : -1; gsCwq.asStatsExecuted[i32WriteOffset].pid = psCacheOpWorkItem->pid; - gsCwq.i32StatsExecWriteIdx = INCR_WRAP(gsCwq.i32StatsExecWriteIdx); - gsCwq.asStatsExecuted[i32WriteOffset].bUMF = psCacheOpWorkItem->bUMF; gsCwq.asStatsExecuted[i32WriteOffset].uiSize = psCacheOpWorkItem->uiSize; gsCwq.asStatsExecuted[i32WriteOffset].bKMReq = psCacheOpWorkItem->bKMReq; gsCwq.asStatsExecuted[i32WriteOffset].uiOffset = psCacheOpWorkItem->uiOffset; gsCwq.asStatsExecuted[i32WriteOffset].uiCacheOp = psCacheOpWorkItem->uiCacheOp; - gsCwq.asStatsExecuted[i32WriteOffset].bDeferred = psCacheOpWorkItem->bDeferred; - gsCwq.asStatsExecuted[i32WriteOffset].ui32OpSeqNum = psCacheOpWorkItem->ui32OpSeqNum; - gsCwq.asStatsExecuted[i32WriteOffset].ui64ExecuteTime = psCacheOpWorkItem->ui64ExecuteTime; - gsCwq.asStatsExecuted[i32WriteOffset].ui64EnqueuedTime = psCacheOpWorkItem->ui64EnqueuedTime; - gsCwq.asStatsExecuted[i32WriteOffset].ui64DequeuedTime = psCacheOpWorkItem->ui64DequeuedTime; - /* During early system initialisation, only non-fence & non-PMR CacheOps are processed */ - gsCwq.asStatsExecuted[i32WriteOffset].bIsFence = gsCwq.bInit && !psCacheOpWorkItem->psPMR; + gsCwq.asStatsExecuted[i32WriteOffset].ui64StartTime = psCacheOpWorkItem->ui64StartTime; + gsCwq.asStatsExecuted[i32WriteOffset].ui64EndTime = psCacheOpWorkItem->ui64EndTime; + CACHEOP_PVR_ASSERT(gsCwq.asStatsExecuted[i32WriteOffset].pid); #if defined(PVRSRV_ENABLE_GPU_MEMORY_INFO) && defined(DEBUG) if (gsCwq.bInit && psCacheOpWorkItem->psPMR) @@ -435,74 +280,60 @@ static void CacheOpStatsExecLogWrite(CACHEOP_WORK_ITEM *psCacheOpWorkItem) gsCwq.asStatsExecuted[i32WriteOffset].sDevPAddr.uiAddr = sDevPAddr.uiAddr; } - - if (gsCwq.asStatsExecuted[i32WriteOffset].bIsFence) - { - gsCwq.asStatsExecuted[i32WriteOffset].eFenceOpType = psCacheOpWorkItem->eFenceOpType; - } #endif + /* Calculate the approximate cumulative moving average execution time. + * This calculation is based on standard equation: + * + * CMAnext = (new + count * CMAprev) / (count + 1) + * + * but in simplified form: + * + * CMAnext = CMAprev + (new - CMAprev) / (count + 1) + * + * this gets rid of multiplication and prevents overflow. + * + * Also to increase accuracy that we lose with integer division, + * we hold the moving remainder of the division and add it. + * + * CMAnext = CMAprev + (new - CMAprev + CMRprev) / (count + 1) + * + * Multiple tests proved it to be the best solution for approximating + * CMA using integers. + * + */ + + ui32ExecTime = + gsCwq.asStatsExecuted[i32WriteOffset].ui64EndTime - + gsCwq.asStatsExecuted[i32WriteOffset].ui64StartTime; + { - /* Convert timing from nanoseconds to microseconds */ - IMG_UINT64 ui64ExecuteTimeNs = gsCwq.asStatsExecuted[i32WriteOffset].ui64ExecuteTime; - IMG_UINT64 ui64EnqueuedTimeNs = gsCwq.asStatsExecuted[i32WriteOffset].ui64EnqueuedTime; - do_div(ui64ExecuteTimeNs, 1000); - do_div(ui64EnqueuedTimeNs, 1000); + IMG_INT32 i32Div = + (IMG_INT32) ui32ExecTime - + (IMG_INT32) gsCwq.ui32AvgExecTime + + (IMG_INT32) gsCwq.ui32AvgExecTimeRemainder; - ui64ExecuteTime = ui64ExecuteTimeNs; - ui64EnqueuedTime = ui64EnqueuedTimeNs; - } + gsCwq.ui32AvgExecTime += i32Div / (IMG_INT32)(gsCwq.ui32TotalOps + 1); + gsCwq.ui32AvgExecTimeRemainder = i32Div % (IMG_INT32)(gsCwq.ui32TotalOps + 1); - /* Coalesced deferred CacheOps do not contribute to statistics, - as both enqueue/execute time is identical for these CacheOps */ - if (!gsCwq.asStatsExecuted[i32WriteOffset].bIsFence) - { - /* Calculate the approximate cumulative moving average execution time. - * This calculation is based on standard equation: - * - * CMAnext = (new + count * CMAprev) / (count + 1) - * - * but in simplified form: - * - * CMAnext = CMAprev + (new - CMAprev) / (count + 1) - * - * this gets rid of multiplication and prevents overflow. - * - * Also to increase accuracy that we lose with integer division, - * we hold the moving remainder of the division and add it. - * - * CMAnext = CMAprev + (new - CMAprev + CMRprev) / (count + 1) - * - * Multiple tests proved it to be the best solution for approximating - * CMA using integers. - * - */ + gsCwq.ui32TotalOps++; - IMG_UINT32 ui32Time = ui64ExecuteTime - ui64EnqueuedTime; - IMG_INT32 i32Div = (IMG_INT32)ui32Time - (IMG_INT32)gsCwq.ui32AvgExecTime + (IMG_INT32)gsCwq.ui32AvgExecTimeRemainder; - - gsCwq.ui32AvgExecTime += i32Div / (IMG_INT32)(gsCwq.ui32TotalExecOps + 1); - gsCwq.ui32AvgExecTimeRemainder = i32Div % (IMG_INT32)(gsCwq.ui32TotalExecOps + 1); - - gsCwq.ui32TotalExecOps++; } if (!gsCwq.asStatsExecuted[i32WriteOffset].bKMReq) { /* This operation queues only UM CacheOp in per-PID process statistics database */ - PVRSRVStatsUpdateCacheOpStats(gsCwq.asStatsExecuted[i32WriteOffset].uiCacheOp, - gsCwq.asStatsExecuted[i32WriteOffset].ui32OpSeqNum, + PVRSRVStatsUpdateCacheOpStats( + gsCwq.asStatsExecuted[i32WriteOffset].uiCacheOp, #if defined(PVRSRV_ENABLE_GPU_MEMORY_INFO) && defined(DEBUG) gsCwq.asStatsExecuted[i32WriteOffset].sDevVAddr, gsCwq.asStatsExecuted[i32WriteOffset].sDevPAddr, - gsCwq.asStatsExecuted[i32WriteOffset].eFenceOpType, #endif gsCwq.asStatsExecuted[i32WriteOffset].uiOffset, gsCwq.asStatsExecuted[i32WriteOffset].uiSize, - ui64ExecuteTime-ui64EnqueuedTime, - gsCwq.asStatsExecuted[i32WriteOffset].bUMF, - gsCwq.asStatsExecuted[i32WriteOffset].bIsFence, + ui32ExecTime, + !gsCwq.asStatsExecuted[i32WriteOffset].bKMReq, psCacheOpWorkItem->pid); } @@ -514,14 +345,12 @@ e0: static int CacheOpStatsExecLogRead(OSDI_IMPL_ENTRY *psEntry, void *pvData) { - IMG_CHAR *pszFlushype; + IMG_CHAR *pszFlushType; IMG_CHAR *pszCacheOpType; IMG_CHAR *pszFlushSource; IMG_INT32 i32ReadOffset; IMG_INT32 i32WriteOffset; - IMG_UINT64 ui64EnqueuedTime; - IMG_UINT64 ui64DequeuedTime; - IMG_UINT64 ui64ExecuteTime; + IMG_CHAR szBuffer[CACHEOP_MAX_DEBUG_MESSAGE_LEN] = {0}; PVR_UNREFERENCED_PARAMETER(pvData); @@ -530,24 +359,17 @@ static int CacheOpStatsExecLogRead(OSDI_IMPL_ENTRY *psEntry, void *pvData) DIPrintf(psEntry, "Primary CPU d-cache architecture: LSZ: 0x%x, URBF: %s\n", gsCwq.uiLineSize, - gsCwq.bSupportsUMFlush ? "Yes" : "No" - ); + gsCwq.bSupportsUMFlush ? "Yes" : "No"); DIPrintf(psEntry, - "Configuration: QSZ: %d, UKT: %d, KDFT: %d, KDF: %s, URBF: %s\n", - CACHEOP_INDICES_MAX, + "Configuration: UKT: %d, URBF: %s\n", gsCwq.pui32InfoPage[CACHEOP_INFO_UMKMTHRESHLD], - gsCwq.pui32InfoPage[CACHEOP_INFO_KMDFTHRESHLD], - gsCwq.eConfig & CACHEOP_CONFIG_KDF ? "Yes" : "No", - gsCwq.eConfig & CACHEOP_CONFIG_URBF ? "Yes" : "No" - ); + gsCwq.eConfig & CACHEOP_CONFIG_URBF ? "Yes" : "No"); DIPrintf(psEntry, - "Summary: OP[F][TL] (tot.avg): %d.%d/%d.%d/%d, [KM][UM][A]SYNC: %d.%d/%d/%d, RBF (um/km): %d/%d\n", - gsCwq.ui32TotalExecOps, gsCwq.ui32AvgExecTime, gsCwq.ui32TotalFenceOps, gsCwq.ui32AvgFenceTime, gsCwq.ui32ServerDTL, - gsCwq.ui32ServerSync, gsCwq.ui32ServerSyncVA, gsCwq.ui32ClientSync, gsCwq.ui32ServerASync, - gsCwq.ui32ClientRBF, gsCwq.ui32ServerRBF - ); + "Summary: Total Ops [%d] - Server(using UMVA)/Client [%d(%d)/%d]. Avg execution time [%d]\n", + gsCwq.ui32TotalOps, gsCwq.ui32ServerOps, gsCwq.ui32ServerOpUsedUMVA, gsCwq.ui32ClientOps, gsCwq.ui32AvgExecTime); + CacheOpStatsExecLogHeader(szBuffer); DIPrintf(psEntry, "%s\n", szBuffer); @@ -557,160 +379,71 @@ static int CacheOpStatsExecLogRead(OSDI_IMPL_ENTRY *psEntry, void *pvData) i32ReadOffset != i32WriteOffset; i32ReadOffset = DECR_WRAP(i32ReadOffset)) { - if (!gsCwq.asStatsExecuted[i32ReadOffset].ui32OpSeqNum && - !gsCwq.asStatsExecuted[i32ReadOffset].uiCacheOp) + IMG_UINT64 ui64ExecTime = + gsCwq.asStatsExecuted[i32ReadOffset].ui64EndTime - + gsCwq.asStatsExecuted[i32ReadOffset].ui64StartTime; + + IMG_DEVMEM_SIZE_T ui64NumOfPages = + gsCwq.asStatsExecuted[i32ReadOffset].uiSize >> gsCwq.uiPageShift; + + + if (!gsCwq.asStatsExecuted[i32ReadOffset].uiCacheOp) { break; } - + if (ui64NumOfPages <= PMR_MAX_TRANSLATION_STACK_ALLOC) { - /* Convert from nano-seconds to micro-seconds */ - IMG_UINT64 ui64ExecuteTimeNs = gsCwq.asStatsExecuted[i32ReadOffset].ui64ExecuteTime; - IMG_UINT64 ui64EnqueuedTimeNs = gsCwq.asStatsExecuted[i32ReadOffset].ui64EnqueuedTime; - IMG_UINT64 ui64DequeuedTimeNs = gsCwq.asStatsExecuted[i32ReadOffset].ui64DequeuedTime; - - do_div(ui64ExecuteTimeNs, 1000); - do_div(ui64EnqueuedTimeNs, 1000); - do_div(ui64DequeuedTimeNs, 1000); - - ui64ExecuteTime = ui64ExecuteTimeNs; - ui64EnqueuedTime = ui64EnqueuedTimeNs; - ui64DequeuedTime = ui64DequeuedTimeNs; - } - - if (gsCwq.asStatsExecuted[i32ReadOffset].bIsFence) - { - IMG_CHAR *pszMode = ""; - IMG_CHAR *pszFenceType = ""; - pszCacheOpType = "Fence"; - -#if defined(PVRSRV_ENABLE_GPU_MEMORY_INFO) && defined(DEBUG) - switch (gsCwq.asStatsExecuted[i32ReadOffset].eFenceOpType) - { - case RGXFWIF_DM_GP: - pszFenceType = " GP "; - break; - - case RGXFWIF_DM_TDM: - pszFenceType = " TDM "; - break; - - case RGXFWIF_DM_GEOM: - pszFenceType = " GEOM"; - break; - - case RGXFWIF_DM_3D: - pszFenceType = " 3D "; - break; - - case RGXFWIF_DM_CDM: - pszFenceType = " CDM "; - break; - - default: - pszFenceType = " DM? "; - CACHEOP_PVR_ASSERT(0); - break; - } -#endif - - DIPrintf(psEntry, -#if defined(PVRSRV_ENABLE_GPU_MEMORY_INFO) && defined(DEBUG) - CACHEOP_RI_PRINTF, -#else - CACHEOP_PRINTF, -#endif - gsCwq.asStatsExecuted[i32ReadOffset].ui32DeviceID, - gsCwq.asStatsExecuted[i32ReadOffset].pid, - pszCacheOpType, - pszFenceType, - pszMode, -#if defined(PVRSRV_ENABLE_GPU_MEMORY_INFO) && defined(DEBUG) - 0ull, - 0ull, -#endif - gsCwq.asStatsExecuted[i32ReadOffset].uiOffset, - gsCwq.asStatsExecuted[i32ReadOffset].uiSize, - ui64ExecuteTime - ui64EnqueuedTime, - ui64DequeuedTime ? ui64DequeuedTime - ui64EnqueuedTime : 0, /* CacheOp might not have a valid DequeuedTime */ - gsCwq.asStatsExecuted[i32ReadOffset].ui32OpSeqNum); + pszFlushType = "RBF.Fast"; } else { - IMG_DEVMEM_SIZE_T ui64NumOfPages; - - ui64NumOfPages = gsCwq.asStatsExecuted[i32ReadOffset].uiSize >> gsCwq.uiPageShift; - if (ui64NumOfPages <= PMR_MAX_TRANSLATION_STACK_ALLOC) - { - pszFlushype = "RBF.Fast"; - } - else - { - pszFlushype = "RBF.Slow"; - } - - if (gsCwq.asStatsExecuted[i32ReadOffset].bUMF) - { - pszFlushSource = " UM"; - } - else - { - /* - - Request originates directly from a KM thread or in KM (KM<), or - - Request originates from a UM thread and is KM deferred (KM+), or - */ - pszFlushSource = - gsCwq.asStatsExecuted[i32ReadOffset].bKMReq ? " KM<" : - gsCwq.asStatsExecuted[i32ReadOffset].bDeferred && gsCwq.asStatsExecuted[i32ReadOffset].ui64ExecuteTime ? " KM+" : - !gsCwq.asStatsExecuted[i32ReadOffset].ui64ExecuteTime ? " KM-" : " KM"; - } - - switch (gsCwq.asStatsExecuted[i32ReadOffset].uiCacheOp) - { - case PVRSRV_CACHE_OP_NONE: - pszCacheOpType = "None"; - break; - case PVRSRV_CACHE_OP_CLEAN: - pszCacheOpType = "Clean"; - break; - case PVRSRV_CACHE_OP_INVALIDATE: - pszCacheOpType = "Invalidate"; - break; - case PVRSRV_CACHE_OP_FLUSH: - pszCacheOpType = "Flush"; - break; - case PVRSRV_CACHE_OP_TIMELINE: - pszCacheOpType = "Timeline"; - pszFlushype = " "; - break; - default: - pszCacheOpType = "Unknown"; - gsCwq.asStatsExecuted[i32ReadOffset].ui32OpSeqNum = - (IMG_UINT32) gsCwq.asStatsExecuted[i32ReadOffset].uiCacheOp; - break; - } - - DIPrintf(psEntry, -#if defined(PVRSRV_ENABLE_GPU_MEMORY_INFO) && defined(DEBUG) - CACHEOP_RI_PRINTF, -#else - CACHEOP_PRINTF, -#endif - gsCwq.asStatsExecuted[i32ReadOffset].ui32DeviceID, - gsCwq.asStatsExecuted[i32ReadOffset].pid, - pszCacheOpType, - pszFlushype, - pszFlushSource, -#if defined(PVRSRV_ENABLE_GPU_MEMORY_INFO) && defined(DEBUG) - gsCwq.asStatsExecuted[i32ReadOffset].sDevVAddr.uiAddr, - gsCwq.asStatsExecuted[i32ReadOffset].sDevPAddr.uiAddr, -#endif - gsCwq.asStatsExecuted[i32ReadOffset].uiOffset, - gsCwq.asStatsExecuted[i32ReadOffset].uiSize, - ui64ExecuteTime - ui64EnqueuedTime, - ui64DequeuedTime ? ui64DequeuedTime - ui64EnqueuedTime : 0, /* CacheOp might not have a valid DequeuedTime */ - gsCwq.asStatsExecuted[i32ReadOffset].ui32OpSeqNum); + pszFlushType = "RBF.Slow"; } + + pszFlushSource = gsCwq.asStatsExecuted[i32ReadOffset].bKMReq ? " KM" : " UM"; + + switch (gsCwq.asStatsExecuted[i32ReadOffset].uiCacheOp) + { + case PVRSRV_CACHE_OP_NONE: + pszCacheOpType = "None"; + break; + case PVRSRV_CACHE_OP_CLEAN: + pszCacheOpType = "Clean"; + break; + case PVRSRV_CACHE_OP_INVALIDATE: + pszCacheOpType = "Invalidate"; + break; + case PVRSRV_CACHE_OP_FLUSH: + pszCacheOpType = "Flush"; + break; + case PVRSRV_CACHE_OP_TIMELINE: + pszCacheOpType = "Timeline"; + pszFlushType = " "; + break; + default: + pszCacheOpType = "Unknown"; + break; + } + + DIPrintf(psEntry, +#if defined(PVRSRV_ENABLE_GPU_MEMORY_INFO) && defined(DEBUG) + CACHEOP_RI_PRINTF, +#else + CACHEOP_PRINTF, +#endif + gsCwq.asStatsExecuted[i32ReadOffset].ui32DeviceID, + gsCwq.asStatsExecuted[i32ReadOffset].pid, + pszCacheOpType, + pszFlushType, + pszFlushSource, +#if defined(PVRSRV_ENABLE_GPU_MEMORY_INFO) && defined(DEBUG) + gsCwq.asStatsExecuted[i32ReadOffset].sDevVAddr.uiAddr, + gsCwq.asStatsExecuted[i32ReadOffset].sDevPAddr.uiAddr, +#endif + gsCwq.asStatsExecuted[i32ReadOffset].uiOffset, + gsCwq.asStatsExecuted[i32ReadOffset].uiSize, + ui64ExecTime); + } OSLockRelease(gsCwq.hStatsExecLock); @@ -722,20 +455,15 @@ static int CacheOpStatsExecLogRead(OSDI_IMPL_ENTRY *psEntry, void *pvData) static INLINE void CacheOpStatsReset(void) { #if defined(CACHEOP_DEBUG) - gsCwq.ui32TotalExecOps = 0; - gsCwq.ui32TotalFenceOps = 0; - gsCwq.ui32AvgExecTime = 0; - gsCwq.ui32AvgExecTimeRemainder = 0; - gsCwq.ui32AvgFenceTime = 0; - gsCwq.ui32AvgFenceTimeRemainder = 0; - gsCwq.ui32ClientRBF = 0; - gsCwq.ui32ClientSync = 0; - gsCwq.ui32ServerRBF = 0; - gsCwq.ui32ServerASync = 0; - gsCwq.ui32ServerSyncVA = 0; - gsCwq.ui32ServerSync = 0; - gsCwq.ui32ServerDTL = 0; - gsCwq.i32StatsExecWriteIdx = 0; + gsCwq.ui32ServerOps = 0; + gsCwq.ui32ClientOps = 0; + gsCwq.ui32TotalOps = 0; + gsCwq.ui32ServerOpUsedUMVA = 0; + gsCwq.ui32AvgExecTime = 0; + gsCwq.ui32AvgExecTimeRemainder = 0; + + gsCwq.i32StatsExecWriteIdx = 0; + OSCachedMemSet(gsCwq.asStatsExecuted, 0, sizeof(gsCwq.asStatsExecuted)); #endif } @@ -830,11 +558,10 @@ static void CacheOpConfigUpdate(IMG_UINT32 ui32Config) static int CacheOpConfigRead(OSDI_IMPL_ENTRY *psEntry, void *pvData) { PVR_UNREFERENCED_PARAMETER(pvData); - DIPrintf(psEntry, - "KDF: %s, URBF: %s\n", - gsCwq.eConfig & CACHEOP_CONFIG_KDF ? "Yes" : "No", - gsCwq.eConfig & CACHEOP_CONFIG_URBF ? "Yes" : "No" - ); + + DIPrintf(psEntry, "URBF: %s\n", + gsCwq.eConfig & CACHEOP_CONFIG_URBF ? "Yes" : "No"); + return 0; } @@ -906,68 +633,6 @@ static INLINE PVRSRV_ERROR CacheOpConfigSet(const PVRSRV_DEVICE_NODE *psDevNode, return PVRSRV_OK; } -static INLINE IMG_UINT32 CacheOpGetNextCommonSeqNum(void) -{ - IMG_UINT32 ui32SeqNum = OSAtomicIncrement(&gsCwq.hCommonSeqNum); - if (! ui32SeqNum) - { - ui32SeqNum = OSAtomicIncrement(&gsCwq.hCommonSeqNum); - } - return ui32SeqNum; -} - -static INLINE IMG_BOOL CacheOpFenceCheck(IMG_UINT32 ui32CompletedSeqNum, - IMG_UINT32 ui32FenceSeqNum) -{ - IMG_UINT32 ui32RebasedCompletedNum; - IMG_UINT32 ui32RebasedFenceNum; - IMG_UINT32 ui32Rebase; - - if (ui32FenceSeqNum == 0) - { - return IMG_TRUE; - } - - /* - The problem statement is how to compare two values on - a numerical sequentially incrementing timeline in the - presence of wrap around arithmetic semantics using a - single ui32 counter & atomic (increment) operations. - - The rationale for the solution here is to rebase the - incoming values to the sequence midpoint and perform - comparisons there; this allows us to handle overflow - or underflow wrap-round using only a single integer. - - NOTE: Here we assume that the absolute value of the - difference between the two incoming values in _not_ - greater than CACHEOP_SEQ_MIDPOINT. This assumption - holds as it implies that it is very _unlikely_ that 2 - billion CacheOp requests could have been made between - a single client's CacheOp request & the corresponding - fence check. This code sequence is hopefully a _more_ - hand optimised (branchless) version of this: - - x = ui32CompletedOpSeqNum - y = ui32FenceOpSeqNum - - if (|x - y| < CACHEOP_SEQ_MIDPOINT) - return (x - y) >= 0 ? true : false - else - return (y - x) >= 0 ? true : false - */ - ui32Rebase = CACHEOP_SEQ_MIDPOINT - ui32CompletedSeqNum; - - /* ui32Rebase could be either positive/negative, in - any case we still perform operation using unsigned - semantics as 2's complement notation always means - we end up with the correct result */ - ui32RebasedCompletedNum = ui32Rebase + ui32CompletedSeqNum; - ui32RebasedFenceNum = ui32Rebase + ui32FenceSeqNum; - - return (ui32RebasedCompletedNum >= ui32RebasedFenceNum); -} - static INLINE PVRSRV_ERROR CacheOpTimelineBind(PVRSRV_DEVICE_NODE *psDevNode, CACHEOP_WORK_ITEM *psCacheOpWorkItem, PVRSRV_TIMELINE iTimeline) @@ -1099,10 +764,6 @@ static INLINE void CacheOpExecRangeBased(PVRSRV_DEVICE_NODE *psDevNode, break; } -#if defined(CACHEOP_DEBUG) - /* Tracks the number of kernel-mode cacheline maintenance instructions */ - gsCwq.ui32ServerRBF += (uiRelFlushSize & ((IMG_DEVMEM_SIZE_T)~(gsCwq.uiLineSize - 1))) >> gsCwq.uiLineShift; -#endif } static INLINE void CacheOpExecRangeBasedVA(PVRSRV_DEVICE_NODE *psDevNode, @@ -1138,10 +799,6 @@ static INLINE void CacheOpExecRangeBasedVA(PVRSRV_DEVICE_NODE *psDevNode, break; } -#if defined(CACHEOP_DEBUG) - /* Tracks the number of kernel-mode cacheline maintenance instructions */ - gsCwq.ui32ServerRBF += (uiSize & ((IMG_DEVMEM_SIZE_T)~(gsCwq.uiLineSize - 1))) >> gsCwq.uiLineShift; -#endif } static INLINE PVRSRV_ERROR CacheOpValidateUMVA(PMR *psPMR, @@ -1274,7 +931,7 @@ static PVRSRV_ERROR CacheOpPMRExec (PMR *psPMR, PVR_LOG_IF_ERROR(eError, "PMRUnlockSysPhysAddresses"); } #if defined(CACHEOP_DEBUG) - gsCwq.ui32ServerSyncVA += 1; + gsCwq.ui32ServerOpUsedUMVA += 1; #endif return PVRSRV_OK; } @@ -1283,7 +940,7 @@ static PVRSRV_ERROR CacheOpPMRExec (PMR *psPMR, /* Round down the incoming VA (if any) down to the nearest page aligned VA */ pvAddress = (void*)((uintptr_t)pvAddress & ~((uintptr_t)gsCwq.uiPageSize-1)); #if defined(CACHEOP_DEBUG) - gsCwq.ui32ServerSyncVA += 1; + gsCwq.ui32ServerOpUsedUMVA += 1; #endif } } @@ -1578,213 +1235,18 @@ e0: return eError; } -static PVRSRV_ERROR CacheOpQListExecRangeBased(void) -{ - IMG_UINT32 ui32NumOfEntries; - PVRSRV_ERROR eError = PVRSRV_OK; - CACHEOP_WORK_ITEM *psCacheOpWorkItem = NULL; - - /* Take a snapshot of the current count of deferred entries at this junction */ - ui32NumOfEntries = CacheOpIdxSpan(&gsCwq.hWriteCounter, &gsCwq.hReadCounter); - if (! ui32NumOfEntries) - { - return PVRSRV_OK; - } -#if defined(CACHEOP_DEBUG) - CACHEOP_PVR_ASSERT(ui32NumOfEntries < CACHEOP_INDICES_MAX); -#endif - - while (ui32NumOfEntries) - { - if (! OSAtomicRead(&gsCwq.hReadCounter)) - { - /* Normally, the read-counter will trail the write counter until the write - counter wraps-round to zero. Under this condition we (re)calculate as the - read-counter too is wrapping around at this point */ - ui32NumOfEntries = CacheOpIdxSpan(&gsCwq.hWriteCounter, &gsCwq.hReadCounter); - } -#if defined(CACHEOP_DEBUG) - /* Something's gone horribly wrong if these 2 counters are identical at this point */ - CACHEOP_PVR_ASSERT(OSAtomicRead(&gsCwq.hWriteCounter) != OSAtomicRead(&gsCwq.hReadCounter)); -#endif - - /* Select the next pending deferred work-item for RBF cache maintenance */ - psCacheOpWorkItem = &gsCwq.asWorkItems[CacheOpIdxNext(&gsCwq.hReadCounter)]; - -#if defined(CACHEOP_DEBUG) - /* The time waiting in the queue to be serviced */ - psCacheOpWorkItem->ui64DequeuedTime = OSClockns64(); -#endif - - eError = CacheOpPMRExec(psCacheOpWorkItem->psPMR, - NULL, /* No UM virtual address */ - psCacheOpWorkItem->uiOffset, - psCacheOpWorkItem->uiSize, - psCacheOpWorkItem->uiCacheOp, - IMG_TRUE /* PMR is pre-validated */ - ); - if (eError != PVRSRV_OK) - { -#if defined(CACHEOP_DEBUG) -#define PID_FMTSPEC " PID:%u" -#define CACHE_OP_WORK_PID psCacheOpWorkItem->pid -#else -#define PID_FMTSPEC "%s" -#define CACHE_OP_WORK_PID "" -#endif - - PVR_LOG(("Deferred CacheOpPMRExec failed:" - PID_FMTSPEC - " PMR:%p" - " Offset:%" IMG_UINT64_FMTSPECX - " Size:%" IMG_UINT64_FMTSPECX - " CacheOp:%d," - " error: %d", - CACHE_OP_WORK_PID, - psCacheOpWorkItem->psPMR, - psCacheOpWorkItem->uiOffset, - psCacheOpWorkItem->uiSize, - psCacheOpWorkItem->uiCacheOp, - eError)); - -#undef PID_FMTSPEC -#undef CACHE_OP_WORK_PID - } - -#if defined(CACHEOP_DEBUG) - psCacheOpWorkItem->ui64ExecuteTime = OSClockns64(); - CacheOpStatsExecLogWrite(psCacheOpWorkItem); -#endif - - /* The currently executed CacheOp item updates gsCwq.hCompletedSeqNum. - NOTE: This CacheOp item might be a discard item, if so its seqNum - still updates the gsCwq.hCompletedSeqNum */ - OSAtomicWrite(&gsCwq.hCompletedSeqNum, psCacheOpWorkItem->ui32OpSeqNum); - - /* If CacheOp is timeline(d), notify timeline waiters */ - eError = CacheOpTimelineExec(psCacheOpWorkItem); - PVR_LOG_IF_ERROR(eError, "CacheOpTimelineExec"); - - eError = PMRUnlockSysPhysAddresses(psCacheOpWorkItem->psPMR); - PVR_LOG_IF_ERROR(eError, "PMRUnlockSysPhysAddresses"); - - (void) CacheOpIdxIncrement(&gsCwq.hReadCounter); - ui32NumOfEntries = ui32NumOfEntries - 1; - } - - return eError; -} - -static INLINE PVRSRV_ERROR CacheOpQListExec(void) -{ - PVRSRV_ERROR eError; - - eError = CacheOpQListExecRangeBased(); - PVR_LOG_IF_ERROR(eError, "CacheOpQListExecRangeBased"); - - /* Signal any waiting threads blocked on CacheOp fence checks update - completed sequence number to last queue work item */ - eError = OSEventObjectSignal(gsCwq.hClientWakeUpEvtObj); - PVR_LOG_IF_ERROR(eError, "OSEventObjectSignal"); - - return eError; -} - -static void CacheOpThread(void *pvData) -{ - PVRSRV_DATA *psPVRSRVData = pvData; - IMG_HANDLE hOSEvent; - PVRSRV_ERROR eError; - - /* Open CacheOp thread event object, abort driver if event object open fails */ - eError = OSEventObjectOpen(gsCwq.hThreadWakeUpEvtObj, &hOSEvent); - PVR_LOG_IF_ERROR(eError, "OSEventObjectOpen"); - - /* While driver is in good state & loaded, perform pending cache maintenance */ - while ((psPVRSRVData->eServicesState == PVRSRV_SERVICES_STATE_OK) && gsCwq.bInit) - { - /* Sleep-wait here until when signalled for new queued CacheOp work items; - when woken-up, drain deferred queue completely before next event-wait */ - (void) OSEventObjectWaitKernel(hOSEvent, CACHEOP_THREAD_WAIT_TIMEOUT); - while (CacheOpIdxSpan(&gsCwq.hWriteCounter, &gsCwq.hReadCounter)) - { - eError = CacheOpQListExec(); - PVR_LOG_IF_ERROR(eError, "CacheOpQListExec"); - } - } - - eError = CacheOpQListExec(); - PVR_LOG_IF_ERROR(eError, "CacheOpQListExec"); - - eError = OSEventObjectClose(hOSEvent); - PVR_LOG_IF_ERROR(eError, "OSEventObjectClose"); -} - static PVRSRV_ERROR CacheOpBatchExecTimeline(PVRSRV_DEVICE_NODE *psDevNode, - PVRSRV_TIMELINE iTimeline, - IMG_UINT32 ui32CurrentFenceSeqNum, - IMG_UINT32 *pui32NextFenceSeqNum) + PVRSRV_TIMELINE iTimeline) { PVRSRV_ERROR eError; - IMG_UINT32 ui32NextIdx; CACHEOP_WORK_ITEM sCacheOpWorkItem = {NULL}; - CACHEOP_WORK_ITEM *psCacheOpWorkItem = NULL; eError = CacheOpTimelineBind(psDevNode, &sCacheOpWorkItem, iTimeline); PVR_LOG_RETURN_IF_ERROR(eError, "CacheOpTimelineBind"); - OSLockAcquire(gsCwq.hDeferredLock); + eError = CacheOpTimelineExec(&sCacheOpWorkItem); + PVR_LOG_IF_ERROR(eError, "CacheOpTimelineExec"); - /* - Check if there is any deferred queueing space available and that nothing is - currently queued. This second check is required as Android where timelines - are used sets a timeline signalling deadline of 1000ms to signal timelines - else complains. So seeing we cannot be sure how long the CacheOp presently - in the queue would take we should not send this timeline down the queue as - well. - */ - ui32NextIdx = CacheOpIdxNext(&gsCwq.hWriteCounter); - if (!CacheOpIdxSpan(&gsCwq.hWriteCounter, &gsCwq.hReadCounter) && - CacheOpIdxRead(&gsCwq.hReadCounter) != ui32NextIdx) - { - psCacheOpWorkItem = &gsCwq.asWorkItems[ui32NextIdx]; - - psCacheOpWorkItem->sSWTimelineObj = sCacheOpWorkItem.sSWTimelineObj; - psCacheOpWorkItem->iTimeline = sCacheOpWorkItem.iTimeline; - psCacheOpWorkItem->psDevNode = sCacheOpWorkItem.psDevNode; - psCacheOpWorkItem->ui32OpSeqNum = CacheOpGetNextCommonSeqNum(); - psCacheOpWorkItem->uiCacheOp = PVRSRV_CACHE_OP_TIMELINE; - psCacheOpWorkItem->uiOffset = (IMG_DEVMEM_OFFSET_T)0; - psCacheOpWorkItem->uiSize = (IMG_DEVMEM_SIZE_T)0; - /* Defer timeline using information page PMR */ - psCacheOpWorkItem->psPMR = gsCwq.psInfoPagePMR; - - eError = PMRLockSysPhysAddresses(psCacheOpWorkItem->psPMR); - PVR_LOG_GOTO_IF_ERROR(eError, "PMRLockSysPhysAddresses", e0); - -#if defined(CACHEOP_DEBUG) - psCacheOpWorkItem->pid = OSGetCurrentClientProcessIDKM(); - psCacheOpWorkItem->ui64EnqueuedTime = OSClockns64(); - gsCwq.ui32ServerASync += 1; - gsCwq.ui32ServerDTL += 1; -#endif - - /* Mark index ready for cache maintenance */ - (void) CacheOpIdxIncrement(&gsCwq.hWriteCounter); - - eError = OSEventObjectSignal(gsCwq.hThreadWakeUpEvtObj); - PVR_LOG_IF_ERROR(eError, "OSEventObjectSignal"); - } - else - { - /* signal timeline. - * All ops with timelines and partial batches were executed synchronously. */ - eError = CacheOpTimelineExec(&sCacheOpWorkItem); - PVR_LOG_IF_ERROR(eError, "CacheOpTimelineExec"); - } - -e0: - OSLockRelease(gsCwq.hDeferredLock); return eError; } @@ -1795,21 +1257,14 @@ static PVRSRV_ERROR CacheOpBatchExecRangeBased(PVRSRV_DEVICE_NODE *psDevNode, IMG_DEVMEM_SIZE_T *puiSize, PVRSRV_CACHE_OP *puiCacheOp, IMG_UINT32 ui32NumCacheOps, - PVRSRV_TIMELINE uiTimeline, - IMG_UINT32 uiCurrentFenceSeqNum, - IMG_UINT32 *pui32NextFenceSeqNum) + PVRSRV_TIMELINE uiTimeline) { IMG_UINT32 ui32Idx; - IMG_UINT32 ui32NextIdx; IMG_BOOL bBatchHasTimeline; - IMG_BOOL bCacheOpConfigKDF; - IMG_DEVMEM_SIZE_T uiLogicalSize; - IMG_BOOL bBatchForceSynchronous = IMG_FALSE; PVRSRV_ERROR eError = PVRSRV_OK; - CACHEOP_WORK_ITEM *psCacheOpWorkItem = NULL; + #if defined(CACHEOP_DEBUG) CACHEOP_WORK_ITEM sCacheOpWorkItem = {0}; - IMG_UINT32 ui32OpSeqNum = CacheOpGetNextCommonSeqNum(); sCacheOpWorkItem.pid = OSGetCurrentClientProcessIDKM(); #endif @@ -1817,170 +1272,41 @@ static PVRSRV_ERROR CacheOpBatchExecRangeBased(PVRSRV_DEVICE_NODE *psDevNode, bBatchHasTimeline = puiCacheOp[ui32NumCacheOps-1] & PVRSRV_CACHE_OP_TIMELINE; puiCacheOp[ui32NumCacheOps-1] &= ~(PVRSRV_CACHE_OP_TIMELINE); - /* Check if batch is forcing synchronous execution */ - bBatchForceSynchronous = puiCacheOp[ui32NumCacheOps-1] & PVRSRV_CACHE_OP_FORCE_SYNCHRONOUS; - puiCacheOp[ui32NumCacheOps-1] &= ~(PVRSRV_CACHE_OP_FORCE_SYNCHRONOUS); - - /* Check if config. supports kernel deferring of cacheops */ - bCacheOpConfigKDF = CacheOpConfigSupports(CACHEOP_CONFIG_KDF); - - /* - Client expects the next fence seqNum to be zero unless the server has deferred - at least one CacheOp in the submitted queue in which case the server informs - the client of the last CacheOp seqNum deferred in this batch. - */ - for (*pui32NextFenceSeqNum = 0, ui32Idx = 0; ui32Idx < ui32NumCacheOps; ui32Idx++) + for (ui32Idx = 0; ui32Idx < ui32NumCacheOps; ui32Idx++) { /* Fail UM request, don't silently ignore */ PVR_GOTO_IF_INVALID_PARAM(puiSize[ui32Idx], eError, e0); - if (bCacheOpConfigKDF) - { - /* Check if there is deferred queueing space available */ - ui32NextIdx = CacheOpIdxNext(&gsCwq.hWriteCounter); - if (ui32NextIdx != CacheOpIdxRead(&gsCwq.hReadCounter)) - { - psCacheOpWorkItem = &gsCwq.asWorkItems[ui32NextIdx]; - } - } - - /* - Normally, we would like to defer client CacheOp(s) but we may not always be in a - position or is necessary to do so based on the following reasons: - 0 - There is currently no queueing space left to enqueue this CacheOp, this might - imply the system is queueing more requests than can be consumed by the CacheOp - thread in time. - 1 - Batch has timeline, action this now due to Android timeline signaling deadlines. - 2 - Batch is forced synchronous. Necessary on Android for batches scheduled in the - middle of add operation. Those cannot have timelines that client plans to add - during actual batch execution and thus make synchronization on Android tricky. - 3 - Configuration does not support deferring of cache maintenance operations so we - execute the batch synchronously/immediately. - 4 - CacheOp has an INVALIDATE, as this is used to transfer device memory buffer - ownership back to the processor, we cannot defer it so action it immediately. - 5 - CacheOp size too small (single OS page size) to warrant overhead of deferment, - 6 - CacheOp size OK for deferment, but a client virtual address is supplied so we - might has well just take advantage of said VA & flush immediately in UM context. - 7 - Prevent DoS attack if a malicious client queues something very large, say 1GiB. - Here we upper bound this threshold to PVR_DIRTY_BYTES_FLUSH_THRESHOLD. - */ - if (!psCacheOpWorkItem || - bBatchHasTimeline || - bBatchForceSynchronous || - !bCacheOpConfigKDF || - puiCacheOp[ui32Idx] & PVRSRV_CACHE_OP_INVALIDATE || - (puiSize[ui32Idx] <= (IMG_DEVMEM_SIZE_T)gsCwq.uiPageSize) || - (pvAddress[ui32Idx] && puiSize[ui32Idx] < (IMG_DEVMEM_SIZE_T)gsCwq.pui32InfoPage[CACHEOP_INFO_KMDFTHRESHLD]) || - (puiSize[ui32Idx] >= (IMG_DEVMEM_SIZE_T)(gsCwq.pui32InfoPage[CACHEOP_INFO_KMDFTHRESHLD] << 2))) - { - /* When the CacheOp thread not keeping up, trash d-cache */ #if defined(CACHEOP_DEBUG) - sCacheOpWorkItem.ui64EnqueuedTime = OSClockns64(); - gsCwq.ui32ServerSync += 1; -#endif - psCacheOpWorkItem = NULL; - - eError = CacheOpPMRExec(ppsPMR[ui32Idx], - pvAddress[ui32Idx], - puiOffset[ui32Idx], - puiSize[ui32Idx], - puiCacheOp[ui32Idx], - IMG_FALSE); - PVR_LOG_GOTO_IF_ERROR(eError, "CacheOpExecPMR", e0); - -#if defined(CACHEOP_DEBUG) - sCacheOpWorkItem.psDevNode = psDevNode; - sCacheOpWorkItem.ui64ExecuteTime = OSClockns64(); - sCacheOpWorkItem.ui32OpSeqNum = ui32OpSeqNum; - sCacheOpWorkItem.psPMR = ppsPMR[ui32Idx]; - sCacheOpWorkItem.uiSize = puiSize[ui32Idx]; - sCacheOpWorkItem.uiOffset = puiOffset[ui32Idx]; - sCacheOpWorkItem.uiCacheOp = puiCacheOp[ui32Idx]; - CacheOpStatsExecLogWrite(&sCacheOpWorkItem); + sCacheOpWorkItem.ui64StartTime = OSClockus64(); #endif - continue; - } - - /* Need to validate request parameters here before enqueing */ - eError = PMR_LogicalSize(ppsPMR[ui32Idx], &uiLogicalSize); - PVR_LOG_GOTO_IF_ERROR(eError, "PMR_LogicalSize", e0); - eError = PVRSRV_ERROR_DEVICEMEM_OUT_OF_RANGE; - PVR_LOG_GOTO_IF_FALSE(((puiOffset[ui32Idx]+puiSize[ui32Idx]) <= uiLogicalSize), CACHEOP_DEVMEM_OOR_ERROR_STRING, e0); - eError = PVRSRV_OK; - - /* For safety, take reference here in user context */ - eError = PMRLockSysPhysAddresses(ppsPMR[ui32Idx]); - PVR_LOG_GOTO_IF_ERROR(eError, "PMRLockSysPhysAddresses", e0); - - OSLockAcquire(gsCwq.hDeferredLock); - /* Select next item off the queue to defer with */ - ui32NextIdx = CacheOpIdxNext(&gsCwq.hWriteCounter); - if (ui32NextIdx != CacheOpIdxRead(&gsCwq.hReadCounter)) - { - psCacheOpWorkItem = &gsCwq.asWorkItems[ui32NextIdx]; - } - else - { - /* Retry, disable KDF for this batch */ - OSLockRelease(gsCwq.hDeferredLock); - bCacheOpConfigKDF = IMG_FALSE; - psCacheOpWorkItem = NULL; - eError = PMRUnlockSysPhysAddresses(ppsPMR[ui32Idx]); - PVR_LOG_GOTO_IF_ERROR(eError, "PMRUnlockSysPhysAddresses", e0); - ui32Idx = ui32Idx - 1; - continue; - } - - psCacheOpWorkItem->psPMR = ppsPMR[ui32Idx]; - psCacheOpWorkItem->uiCacheOp = puiCacheOp[ui32Idx]; - psCacheOpWorkItem->uiOffset = puiOffset[ui32Idx]; - psCacheOpWorkItem->uiSize = puiSize[ui32Idx]; - - /* Timeline need to be looked-up (i.e. bind) in the user context - before deferring into the CacheOp thread kernel context */ - eError = CacheOpTimelineBind(psDevNode, psCacheOpWorkItem, PVRSRV_NO_TIMELINE); - PVR_LOG_GOTO_IF_ERROR(eError, "CacheOpTimelineBind", e1); - - /* Prepare & enqueue next deferred work item for CacheOp thread */ - psCacheOpWorkItem->ui32OpSeqNum = CacheOpGetNextCommonSeqNum(); - *pui32NextFenceSeqNum = psCacheOpWorkItem->ui32OpSeqNum; + eError = CacheOpPMRExec(ppsPMR[ui32Idx], + pvAddress[ui32Idx], + puiOffset[ui32Idx], + puiSize[ui32Idx], + puiCacheOp[ui32Idx], + IMG_FALSE); + PVR_LOG_GOTO_IF_ERROR(eError, "CacheOpExecPMR", e0); #if defined(CACHEOP_DEBUG) - psCacheOpWorkItem->ui64EnqueuedTime = OSClockns64(); - psCacheOpWorkItem->pid = sCacheOpWorkItem.pid; - psCacheOpWorkItem->bDeferred = IMG_TRUE; - psCacheOpWorkItem->bKMReq = IMG_FALSE; - psCacheOpWorkItem->bUMF = IMG_FALSE; - gsCwq.ui32ServerASync += 1; + sCacheOpWorkItem.ui64EndTime = OSClockus64(); + + sCacheOpWorkItem.psDevNode = psDevNode; + sCacheOpWorkItem.psPMR = ppsPMR[ui32Idx]; + sCacheOpWorkItem.uiSize = puiSize[ui32Idx]; + sCacheOpWorkItem.uiOffset = puiOffset[ui32Idx]; + sCacheOpWorkItem.uiCacheOp = puiCacheOp[ui32Idx]; + CacheOpStatsExecLogWrite(&sCacheOpWorkItem); + + gsCwq.ui32ServerOps += 1; #endif - - /* Increment deferred size & mark index ready for cache maintenance */ - (void) CacheOpIdxIncrement(&gsCwq.hWriteCounter); - - OSLockRelease(gsCwq.hDeferredLock); - psCacheOpWorkItem = NULL; } - /* Signal the CacheOp thread to ensure these items get processed */ - eError = OSEventObjectSignal(gsCwq.hThreadWakeUpEvtObj); - PVR_LOG_IF_ERROR(eError, "OSEventObjectSignal"); - -e1: - if (psCacheOpWorkItem) - { - eError = PMRUnlockSysPhysAddresses(psCacheOpWorkItem->psPMR); - PVR_LOG_IF_ERROR(eError, "PMRUnlockSysPhysAddresses"); - } - OSLockRelease(gsCwq.hDeferredLock); - e0: if (bBatchHasTimeline) { - PVRSRV_ERROR eError2; - eError2 = CacheOpBatchExecTimeline(psDevNode, uiTimeline, - uiCurrentFenceSeqNum, pui32NextFenceSeqNum); - eError = (eError2 == PVRSRV_ERROR_RETRY) ? eError2 : eError; + eError = CacheOpBatchExecTimeline(psDevNode, uiTimeline); } return eError; @@ -1995,7 +1321,7 @@ PVRSRV_ERROR CacheOpExec (PPVRSRV_DEVICE_NODE psDevNode, PVRSRV_CACHE_OP uiCacheOp) { #if defined(CACHEOP_DEBUG) - IMG_UINT64 ui64EnqueueTime = OSClockns64(); + IMG_UINT64 ui64StartTime = OSClockus64(); #endif switch (uiCacheOp) @@ -2020,9 +1346,7 @@ PVRSRV_ERROR CacheOpExec (PPVRSRV_DEVICE_NODE psDevNode, { CACHEOP_WORK_ITEM sCacheOpWorkItem = {0}; - gsCwq.ui32ServerSync += 1; - gsCwq.ui32ServerRBF += - ((sCPUPhysEnd.uiAddr - sCPUPhysStart.uiAddr) & ((IMG_DEVMEM_SIZE_T)~(gsCwq.uiLineSize - 1))) >> gsCwq.uiLineShift; + gsCwq.ui32ServerOps += 1; sCacheOpWorkItem.uiOffset = 0; sCacheOpWorkItem.bKMReq = IMG_TRUE; @@ -2030,10 +1354,9 @@ PVRSRV_ERROR CacheOpExec (PPVRSRV_DEVICE_NODE psDevNode, /* Use information page PMR for logging KM request */ sCacheOpWorkItem.psPMR = gsCwq.psInfoPagePMR; sCacheOpWorkItem.psDevNode = psDevNode; - sCacheOpWorkItem.ui64EnqueuedTime = ui64EnqueueTime; - sCacheOpWorkItem.ui64ExecuteTime = OSClockns64(); + sCacheOpWorkItem.ui64StartTime = ui64StartTime; + sCacheOpWorkItem.ui64EndTime = OSClockus64(); sCacheOpWorkItem.pid = OSGetCurrentClientProcessIDKM(); - sCacheOpWorkItem.ui32OpSeqNum = CacheOpGetNextCommonSeqNum(); sCacheOpWorkItem.uiSize = (sCPUPhysEnd.uiAddr - sCPUPhysStart.uiAddr); CacheOpStatsExecLogWrite(&sCacheOpWorkItem); @@ -2053,15 +1376,8 @@ PVRSRV_ERROR CacheOpValExec(PMR *psPMR, IMG_CPU_VIRTADDR pvAddress = (IMG_CPU_VIRTADDR)(uintptr_t)uiAddress; #if defined(CACHEOP_DEBUG) CACHEOP_WORK_ITEM sCacheOpWorkItem = {0}; - gsCwq.ui32ServerSync += 1; - sCacheOpWorkItem.psDevNode = PMR_DeviceNode(psPMR); - sCacheOpWorkItem.psPMR = psPMR; - sCacheOpWorkItem.uiSize = uiSize; - sCacheOpWorkItem.uiOffset = uiOffset; - sCacheOpWorkItem.uiCacheOp = uiCacheOp; - sCacheOpWorkItem.pid = OSGetCurrentClientProcessIDKM(); - sCacheOpWorkItem.ui32OpSeqNum = CacheOpGetNextCommonSeqNum(); - sCacheOpWorkItem.ui64EnqueuedTime = OSClockns64(); + + sCacheOpWorkItem.ui64StartTime = OSClockus64(); #endif eError = CacheOpPMRExec(psPMR, @@ -2073,8 +1389,17 @@ PVRSRV_ERROR CacheOpValExec(PMR *psPMR, PVR_LOG_GOTO_IF_ERROR(eError, "CacheOpPMRExec", e0); #if defined(CACHEOP_DEBUG) - sCacheOpWorkItem.ui64ExecuteTime = OSClockns64(); + sCacheOpWorkItem.ui64EndTime = OSClockus64(); + + sCacheOpWorkItem.psDevNode = PMR_DeviceNode(psPMR); + sCacheOpWorkItem.psPMR = psPMR; + sCacheOpWorkItem.uiSize = uiSize; + sCacheOpWorkItem.uiOffset = uiOffset; + sCacheOpWorkItem.uiCacheOp = uiCacheOp; + sCacheOpWorkItem.pid = OSGetCurrentClientProcessIDKM(); CacheOpStatsExecLogWrite(&sCacheOpWorkItem); + + gsCwq.ui32ServerOps += 1; #endif e0: @@ -2089,9 +1414,7 @@ PVRSRV_ERROR CacheOpQueue (CONNECTION_DATA *psConnection, IMG_DEVMEM_OFFSET_T *puiOffset, IMG_DEVMEM_SIZE_T *puiSize, PVRSRV_CACHE_OP *puiCacheOp, - IMG_UINT32 ui32OpTimeline, - IMG_UINT32 uiCurrentFenceSeqNum, - IMG_UINT32 *pui32NextFenceSeqNum) + IMG_UINT32 ui32OpTimeline) { PVRSRV_ERROR eError; PVRSRV_TIMELINE uiTimeline = (PVRSRV_TIMELINE)ui32OpTimeline; @@ -2111,7 +1434,7 @@ PVRSRV_ERROR CacheOpQueue (CONNECTION_DATA *psConnection, /* Ensure any single timeline CacheOp request is processed immediately */ else if (ui32NumCacheOps == 1 && puiCacheOp[0] == PVRSRV_CACHE_OP_TIMELINE) { - eError = CacheOpBatchExecTimeline(psDevNode, uiTimeline, uiCurrentFenceSeqNum, pui32NextFenceSeqNum); + eError = CacheOpBatchExecTimeline(psDevNode, uiTimeline); } /* This is the default entry for all client requests */ else @@ -2130,147 +1453,18 @@ PVRSRV_ERROR CacheOpQueue (CONNECTION_DATA *psConnection, puiSize, puiCacheOp, ui32NumCacheOps, - uiTimeline, - uiCurrentFenceSeqNum, - pui32NextFenceSeqNum); + uiTimeline); } return eError; } -PVRSRV_ERROR CacheOpFence (PPVRSRV_DEVICE_NODE psDevNode, - RGXFWIF_DM eFenceOpType, - IMG_UINT32 ui32FenceOpSeqNum) -{ - IMG_HANDLE hOSEvent; - PVRSRV_ERROR eError2; - IMG_UINT32 ui32RetryAbort; - IMG_UINT32 ui32CompletedOpSeqNum; - PVRSRV_ERROR eError = PVRSRV_OK; -#if defined(CACHEOP_DEBUG) - IMG_UINT64 uiTimeNow; - CACHEOP_WORK_ITEM sCacheOpWorkItem = {0}; - sCacheOpWorkItem.psDevNode = psDevNode; - sCacheOpWorkItem.pid = OSGetCurrentClientProcessIDKM(); - sCacheOpWorkItem.ui32OpSeqNum = ui32FenceOpSeqNum; - sCacheOpWorkItem.ui64EnqueuedTime = OSClockns64(); - uiTimeNow = sCacheOpWorkItem.ui64EnqueuedTime; -#if defined(PVRSRV_ENABLE_GPU_MEMORY_INFO) && defined(DEBUG) - sCacheOpWorkItem.eFenceOpType = eFenceOpType; -#endif - sCacheOpWorkItem.uiSize = (uintptr_t) OSAtomicRead(&gsCwq.hCompletedSeqNum); - sCacheOpWorkItem.uiOffset = 0; -#endif - PVR_UNREFERENCED_PARAMETER(eFenceOpType); - - /* If initial fence check fails, then wait-and-retry in loop */ - ui32CompletedOpSeqNum = OSAtomicRead(&gsCwq.hCompletedSeqNum); - if (CacheOpFenceCheck(ui32CompletedOpSeqNum, ui32FenceOpSeqNum)) - { -#if defined(CACHEOP_DEBUG) - sCacheOpWorkItem.uiSize = (uintptr_t) ui32CompletedOpSeqNum; -#endif - goto e0; - } - - /* Open CacheOp update event object, if event open fails return error */ - eError2 = OSEventObjectOpen(gsCwq.hClientWakeUpEvtObj, &hOSEvent); - PVR_LOG_GOTO_IF_ERROR(eError2, "OSEventObjectOpen", e0); - - /* Linear (i.e. use exponential?) back-off, upper bounds user wait */ - for (ui32RetryAbort = gsCwq.ui32FenceRetryAbort; ;--ui32RetryAbort) - { - /* (Re)read completed CacheOp sequence number before waiting */ - ui32CompletedOpSeqNum = OSAtomicRead(&gsCwq.hCompletedSeqNum); - if (CacheOpFenceCheck(ui32CompletedOpSeqNum, ui32FenceOpSeqNum)) - { -#if defined(CACHEOP_DEBUG) - sCacheOpWorkItem.uiSize = (uintptr_t) ui32CompletedOpSeqNum; -#endif - break; - } - - (void) OSEventObjectWaitTimeout(hOSEvent, gsCwq.ui32FenceWaitTimeUs); - - if (! ui32RetryAbort) - { -#if defined(CACHEOP_DEBUG) - sCacheOpWorkItem.uiSize = (uintptr_t) OSAtomicRead(&gsCwq.hCompletedSeqNum); - sCacheOpWorkItem.uiOffset = 0; - uiTimeNow = OSClockns64(); -#endif - PVR_LOG(("CacheOpFence() event: "CACHEOP_ABORT_FENCE_ERROR_STRING)); - eError = PVRSRV_ERROR_RETRY; - break; - } - else - { -#if defined(CACHEOP_DEBUG) - uiTimeNow = OSClockns64(); -#endif - } - } - - eError2 = OSEventObjectClose(hOSEvent); - PVR_LOG_IF_ERROR(eError2, "OSEventObjectOpen"); - -e0: -#if defined(CACHEOP_DEBUG) - sCacheOpWorkItem.ui64ExecuteTime = uiTimeNow; - if (ui32FenceOpSeqNum) - { - IMG_UINT64 ui64TimeTakenNs = sCacheOpWorkItem.ui64EnqueuedTime - sCacheOpWorkItem.ui64ExecuteTime; - IMG_UINT32 ui32Time; - IMG_INT32 i32Div; - - do_div(ui64TimeTakenNs, 1000); - ui32Time = ui64TimeTakenNs; - - /* Only fences pending on CacheOps contribute towards statistics, - * Calculate the approximate cumulative moving average fence time. - * This calculation is based on standard equation: - * - * CMAnext = (new + count * CMAprev) / (count + 1) - * - * but in simplified form: - * - * CMAnext = CMAprev + (new - CMAprev) / (count + 1) - * - * this gets rid of multiplication and prevents overflow. - * - * Also to increase accuracy that we lose with integer division, - * we hold the moving remainder of the division and add it. - * - * CMAnext = CMAprev + (new - CMAprev + CMRprev) / (count + 1) - * - * Multiple tests proved it to be the best solution for approximating - * CMA using integers. - * - */ - - i32Div = (IMG_INT32)ui32Time - (IMG_INT32)gsCwq.ui32AvgFenceTime + (IMG_INT32)gsCwq.ui32AvgFenceTimeRemainder; - - - gsCwq.ui32AvgFenceTime += i32Div / (IMG_INT32)(gsCwq.ui32TotalFenceOps + 1); - gsCwq.ui32AvgFenceTimeRemainder = i32Div % (IMG_INT32)(gsCwq.ui32TotalFenceOps + 1); - - - gsCwq.ui32TotalFenceOps++; - - } - CacheOpStatsExecLogWrite(&sCacheOpWorkItem); -#endif - - return eError; -} - PVRSRV_ERROR CacheOpLog (PMR *psPMR, IMG_UINT64 puiAddress, IMG_DEVMEM_OFFSET_T uiOffset, IMG_DEVMEM_SIZE_T uiSize, - IMG_UINT64 ui64EnqueuedTimeUs, - IMG_UINT64 ui64ExecuteTimeUs, - IMG_UINT32 ui32NumRBF, + IMG_UINT64 ui64StartTime, + IMG_UINT64 ui64EndTime, PVRSRV_CACHE_OP uiCacheOp) { #if defined(CACHEOP_DEBUG) @@ -2283,13 +1477,11 @@ PVRSRV_ERROR CacheOpLog (PMR *psPMR, sCacheOpWorkItem.uiOffset = uiOffset; sCacheOpWorkItem.uiCacheOp = uiCacheOp; sCacheOpWorkItem.pid = OSGetCurrentClientProcessIDKM(); - sCacheOpWorkItem.ui32OpSeqNum = CacheOpGetNextCommonSeqNum(); - sCacheOpWorkItem.ui64EnqueuedTime = ui64EnqueuedTimeUs; - sCacheOpWorkItem.ui64ExecuteTime = ui64ExecuteTimeUs; - sCacheOpWorkItem.bUMF = IMG_TRUE; - gsCwq.ui32ClientRBF += ui32NumRBF; - gsCwq.ui32ClientSync += 1; + sCacheOpWorkItem.ui64StartTime = ui64StartTime; + sCacheOpWorkItem.ui64EndTime = ui64EndTime; + + gsCwq.ui32ClientOps += 1; CacheOpStatsExecLogWrite(&sCacheOpWorkItem); #else @@ -2297,41 +1489,22 @@ PVRSRV_ERROR CacheOpLog (PMR *psPMR, PVR_UNREFERENCED_PARAMETER(uiSize); PVR_UNREFERENCED_PARAMETER(uiOffset); PVR_UNREFERENCED_PARAMETER(uiCacheOp); - PVR_UNREFERENCED_PARAMETER(ui32NumRBF); PVR_UNREFERENCED_PARAMETER(puiAddress); - PVR_UNREFERENCED_PARAMETER(ui64ExecuteTimeUs); - PVR_UNREFERENCED_PARAMETER(ui64EnqueuedTimeUs); + PVR_UNREFERENCED_PARAMETER(ui64StartTime); + PVR_UNREFERENCED_PARAMETER(ui64EndTime); #endif return PVRSRV_OK; } PVRSRV_ERROR CacheOpInit2 (void) { - void *pvAppHintState = NULL; - IMG_UINT32 ui32AppHintDefault = PVRSRV_APPHINT_CACHEOPTHREADPRIORITY; - IMG_UINT32 ui32AppHintCacheOpThreadPriority; - PVRSRV_ERROR eError; PVRSRV_DATA *psPVRSRVData = PVRSRVGetPVRSRVData(); - /* Create an event object for pending CacheOp work items */ - eError = OSEventObjectCreate("PVRSRV_CACHEOP_EVENTOBJECT", &gsCwq.hThreadWakeUpEvtObj); - PVR_LOG_GOTO_IF_ERROR(eError, "OSEventObjectCreate", e0); - - /* Create an event object for updating pending fence checks on CacheOp */ - eError = OSEventObjectCreate("PVRSRV_CACHEOP_EVENTOBJECT", &gsCwq.hClientWakeUpEvtObj); - PVR_LOG_GOTO_IF_ERROR(eError, "OSEventObjectCreate", e0); - - /* Appending work-items is not concurrent, lock protects against this */ - eError = OSLockCreate((POS_LOCK*)&gsCwq.hDeferredLock); - PVR_LOG_GOTO_IF_ERROR(eError, "OSLockCreate", e0); - /* Apphint read/write is not concurrent, so lock protects against this */ eError = OSLockCreate((POS_LOCK*)&gsCwq.hConfigLock); PVR_LOG_GOTO_IF_ERROR(eError, "OSLockCreate", e0); - gsCwq.ui32FenceWaitTimeUs = CACHEOP_FENCE_WAIT_TIMEOUT; - gsCwq.ui32FenceRetryAbort = CACHEOP_FENCE_RETRY_ABORT; #if defined(CACHEFLUSH_ISA_SUPPORTS_UM_FLUSH) gsCwq.bSupportsUMFlush = IMG_TRUE; @@ -2360,24 +1533,6 @@ PVRSRV_ERROR CacheOpInit2 (void) /* Set before spawning thread */ gsCwq.bInit = IMG_TRUE; - OSCreateKMAppHintState(&pvAppHintState); - OSGetKMAppHintUINT32(APPHINT_NO_DEVICE, pvAppHintState, CacheOpThreadPriority, - &ui32AppHintDefault, &ui32AppHintCacheOpThreadPriority); - OSFreeKMAppHintState(pvAppHintState); - - /* Create a thread which is used to execute the deferred CacheOp(s), - these are CacheOp(s) executed by the server on behalf of clients - asynchronously. All clients synchronise with the server before - submitting any HW operation (i.e. device kicks) to ensure that - client device work-load memory is coherent */ - eError = OSThreadCreatePriority(&gsCwq.hWorkerThread, - "pvr_cacheop", - CacheOpThread, - CacheOpThreadDumpInfo, - IMG_TRUE, - psPVRSRVData, - ui32AppHintCacheOpThreadPriority); - PVR_LOG_GOTO_IF_ERROR(eError, "OSThreadCreatePriority", e0); { DI_ITERATOR_CB sIterator = {.pfnShow = CacheOpConfigRead}; /* Writing the unsigned integer binary encoding of CACHEOP_CONFIG @@ -2408,66 +1563,14 @@ e0: void CacheOpDeInit2 (void) { - PVRSRV_ERROR eError = PVRSRV_OK; - gsCwq.bInit = IMG_FALSE; - if (gsCwq.hThreadWakeUpEvtObj) - { - eError = OSEventObjectSignal(gsCwq.hThreadWakeUpEvtObj); - PVR_LOG_IF_ERROR(eError, "OSEventObjectSignal"); - } - - if (gsCwq.hClientWakeUpEvtObj) - { - eError = OSEventObjectSignal(gsCwq.hClientWakeUpEvtObj); - PVR_LOG_IF_ERROR(eError, "OSEventObjectSignal"); - } - - if (gsCwq.hWorkerThread) - { - LOOP_UNTIL_TIMEOUT(OS_THREAD_DESTROY_TIMEOUT_US) - { - eError = OSThreadDestroy(gsCwq.hWorkerThread); - if (PVRSRV_OK == eError) - { - gsCwq.hWorkerThread = NULL; - break; - } - OSWaitus(OS_THREAD_DESTROY_TIMEOUT_US/OS_THREAD_DESTROY_RETRY_COUNT); - } END_LOOP_UNTIL_TIMEOUT(); - PVR_LOG_IF_ERROR(eError, "OSThreadDestroy"); - gsCwq.hWorkerThread = NULL; - } - - if (gsCwq.hClientWakeUpEvtObj) - { - eError = OSEventObjectDestroy(gsCwq.hClientWakeUpEvtObj); - PVR_LOG_IF_ERROR(eError, "OSEventObjectDestroy"); - gsCwq.hClientWakeUpEvtObj = NULL; - } - - if (gsCwq.hThreadWakeUpEvtObj) - { - eError = OSEventObjectDestroy(gsCwq.hThreadWakeUpEvtObj); - PVR_LOG_IF_ERROR(eError, "OSEventObjectDestroy"); - gsCwq.hThreadWakeUpEvtObj = NULL; - } - if (gsCwq.hConfigLock) { - eError = OSLockDestroy(gsCwq.hConfigLock); - PVR_LOG_IF_ERROR(eError, "OSLockDestroy"); + OSLockDestroy(gsCwq.hConfigLock); gsCwq.hConfigLock = NULL; } - if (gsCwq.hDeferredLock) - { - eError = OSLockDestroy(gsCwq.hDeferredLock); - PVR_LOG_IF_ERROR(eError, "OSLockDestroy"); - gsCwq.hDeferredLock = NULL; - } - if (gsCwq.psConfigTune) { DIDestroyEntry(gsCwq.psConfigTune); @@ -2480,14 +1583,8 @@ void CacheOpDeInit2 (void) PVRSRV_ERROR CacheOpInit (void) { - IMG_UINT32 idx; PVRSRV_ERROR eError = PVRSRV_OK; - /* DDK initialisation is anticipated to be performed on the boot - processor (little core in big/little systems) though this may - not always be the case. If so, the value cached here is the - system wide safe (i.e. smallest) L1 d-cache line size value - on any/such platforms with mismatched d-cache line sizes */ gsCwq.uiPageSize = OSGetPageSize(); gsCwq.uiPageShift = OSGetPageShift(); gsCwq.uiLineSize = OSCPUCacheAttributeSize(OS_CPU_CACHE_ATTRIBUTE_LINE_SIZE); @@ -2495,21 +1592,6 @@ PVRSRV_ERROR CacheOpInit (void) PVR_LOG_RETURN_IF_FALSE((gsCwq.uiLineSize && gsCwq.uiPageSize && gsCwq.uiPageShift), "", PVRSRV_ERROR_INIT_FAILURE); gsCwq.uiCacheOpAddrType = OSCPUCacheOpAddressType(); - /* More information regarding these atomic counters can be found - in the CACHEOP_WORK_QUEUE type definition at top of file */ - OSAtomicWrite(&gsCwq.hCompletedSeqNum, 0); - OSAtomicWrite(&gsCwq.hCommonSeqNum, 0); - OSAtomicWrite(&gsCwq.hWriteCounter, 0); - OSAtomicWrite(&gsCwq.hReadCounter, 0); - - for (idx = 0; idx < CACHEOP_INDICES_MAX; idx++) - { - gsCwq.asWorkItems[idx].iTimeline = PVRSRV_NO_TIMELINE; - gsCwq.asWorkItems[idx].psPMR = (void *)(uintptr_t)~0; - gsCwq.asWorkItems[idx].ui32OpSeqNum = (IMG_UINT32)~0; - } - - #if defined(CACHEOP_DEBUG) /* debugfs file read-out is not concurrent, so lock protects against this */ eError = OSLockCreate((POS_LOCK*)&gsCwq.hStatsExecLock); @@ -2535,7 +1617,7 @@ void CacheOpDeInit (void) #if defined(CACHEOP_DEBUG) if (gsCwq.hStatsExecLock) { - (void) OSLockDestroy(gsCwq.hStatsExecLock); + OSLockDestroy(gsCwq.hStatsExecLock); gsCwq.hStatsExecLock = NULL; } diff --git a/drivers/gpu/drm/img-rogue/cache_km.h b/drivers/gpu/drm/img-rogue/cache_km.h index df4041f7b..282ff5bc5 100644 --- a/drivers/gpu/drm/img-rogue/cache_km.h +++ b/drivers/gpu/drm/img-rogue/cache_km.h @@ -132,21 +132,7 @@ PVRSRV_ERROR CacheOpQueue(CONNECTION_DATA *psConnection, IMG_DEVMEM_OFFSET_T *puiOffset, IMG_DEVMEM_SIZE_T *puiSize, PVRSRV_CACHE_OP *puiCacheOp, - IMG_UINT32 ui32OpTimeline, - IMG_UINT32 uiCurrentFenceSeqNum, - IMG_UINT32 *puiNextFenceSeqNum); - -/* - * CacheOpFence() - * - * This is used for fencing for any client in-flight cache maintenance - * operations that might have been deferred by the use of CacheOpQueue(). - * This should be called before any subsequent HW device kicks to ensure - * device memory is coherent with the HW before the kick. - */ -PVRSRV_ERROR CacheOpFence(PPVRSRV_DEVICE_NODE psDevNode, - RGXFWIF_DM eOpType, - IMG_UINT32 ui32OpSeqNum); + IMG_UINT32 ui32OpTimeline); /* * CacheOpLog() @@ -158,9 +144,8 @@ PVRSRV_ERROR CacheOpLog(PMR *psPMR, IMG_UINT64 uiAddress, IMG_DEVMEM_OFFSET_T uiOffset, IMG_DEVMEM_SIZE_T uiSize, - IMG_UINT64 ui64QueuedTimeMs, - IMG_UINT64 ui64ExecuteTimeMs, - IMG_UINT32 ui32NumRBF, + IMG_UINT64 ui64StartTime, + IMG_UINT64 ui64EndTime, PVRSRV_CACHE_OP uiCacheOp); #endif /* CACHE_KM_H */ diff --git a/drivers/gpu/drm/img-rogue/client_cache_bridge.h b/drivers/gpu/drm/img-rogue/client_cache_bridge.h index 5952ae758..1dec13fcc 100644 --- a/drivers/gpu/drm/img-rogue/client_cache_bridge.h +++ b/drivers/gpu/drm/img-rogue/client_cache_bridge.h @@ -61,9 +61,7 @@ IMG_INTERNAL PVRSRV_ERROR BridgeCacheOpQueue(IMG_HANDLE hBridge, IMG_DEVMEM_OFFSET_T * puiOffset, IMG_DEVMEM_SIZE_T * puiSize, PVRSRV_CACHE_OP * piuCacheOp, - IMG_UINT32 ui32OpTimeline, - IMG_UINT32 ui32CurrentFenceSeqNum, - IMG_UINT32 * pui32NextFenceSeqNum); + IMG_UINT32 ui32OpTimeline); IMG_INTERNAL PVRSRV_ERROR BridgeCacheOpExec(IMG_HANDLE hBridge, IMG_HANDLE hPMR, @@ -76,8 +74,7 @@ IMG_INTERNAL PVRSRV_ERROR BridgeCacheOpLog(IMG_HANDLE hBridge, IMG_UINT64 ui64Address, IMG_DEVMEM_OFFSET_T uiOffset, IMG_DEVMEM_SIZE_T uiSize, - IMG_INT64 i64QueuedTimeUs, - IMG_INT64 i64ExecuteTimeUs, - IMG_INT32 i32NumRBF, PVRSRV_CACHE_OP iuCacheOp); + IMG_INT64 i64StartTime, + IMG_INT64 i64EndTime, PVRSRV_CACHE_OP iuCacheOp); #endif /* CLIENT_CACHE_BRIDGE_H */ diff --git a/drivers/gpu/drm/img-rogue/client_cache_direct_bridge.c b/drivers/gpu/drm/img-rogue/client_cache_direct_bridge.c index 9f7634cc2..9691bae93 100644 --- a/drivers/gpu/drm/img-rogue/client_cache_direct_bridge.c +++ b/drivers/gpu/drm/img-rogue/client_cache_direct_bridge.c @@ -58,9 +58,7 @@ IMG_INTERNAL PVRSRV_ERROR BridgeCacheOpQueue(IMG_HANDLE hBridge, IMG_DEVMEM_OFFSET_T * puiOffset, IMG_DEVMEM_SIZE_T * puiSize, PVRSRV_CACHE_OP * piuCacheOp, - IMG_UINT32 ui32OpTimeline, - IMG_UINT32 ui32CurrentFenceSeqNum, - IMG_UINT32 * pui32NextFenceSeqNum) + IMG_UINT32 ui32OpTimeline) { PVRSRV_ERROR eError; PMR **psPMRInt; @@ -70,11 +68,7 @@ IMG_INTERNAL PVRSRV_ERROR BridgeCacheOpQueue(IMG_HANDLE hBridge, eError = CacheOpQueue(NULL, (PVRSRV_DEVICE_NODE *) ((void *)hBridge), ui32NumCacheOps, - psPMRInt, - pui64Address, - puiOffset, - puiSize, - piuCacheOp, ui32OpTimeline, ui32CurrentFenceSeqNum, pui32NextFenceSeqNum); + psPMRInt, pui64Address, puiOffset, puiSize, piuCacheOp, ui32OpTimeline); return eError; } @@ -101,9 +95,8 @@ IMG_INTERNAL PVRSRV_ERROR BridgeCacheOpLog(IMG_HANDLE hBridge, IMG_UINT64 ui64Address, IMG_DEVMEM_OFFSET_T uiOffset, IMG_DEVMEM_SIZE_T uiSize, - IMG_INT64 i64QueuedTimeUs, - IMG_INT64 i64ExecuteTimeUs, - IMG_INT32 i32NumRBF, PVRSRV_CACHE_OP iuCacheOp) + IMG_INT64 i64StartTime, + IMG_INT64 i64EndTime, PVRSRV_CACHE_OP iuCacheOp) { PVRSRV_ERROR eError; PMR *psPMRInt; @@ -113,8 +106,7 @@ IMG_INTERNAL PVRSRV_ERROR BridgeCacheOpLog(IMG_HANDLE hBridge, eError = CacheOpLog(psPMRInt, - ui64Address, - uiOffset, uiSize, i64QueuedTimeUs, i64ExecuteTimeUs, i32NumRBF, iuCacheOp); + ui64Address, uiOffset, uiSize, i64StartTime, i64EndTime, iuCacheOp); return eError; } diff --git a/drivers/gpu/drm/img-rogue/client_mm_bridge.h b/drivers/gpu/drm/img-rogue/client_mm_bridge.h index 9be507ced..ce172eaf2 100644 --- a/drivers/gpu/drm/img-rogue/client_mm_bridge.h +++ b/drivers/gpu/drm/img-rogue/client_mm_bridge.h @@ -251,4 +251,15 @@ IMG_INTERNAL PVRSRV_ERROR BridgeDevmemGetFaultAddress(IMG_HANDLE hBridge, IMG_INTERNAL PVRSRV_ERROR BridgePVRSRVUpdateOOMStats(IMG_HANDLE hBridge, IMG_UINT32 ui32ui32StatType, IMG_PID ui32pid); +IMG_INTERNAL PVRSRV_ERROR BridgePhysHeapGetMemInfoPkd(IMG_HANDLE hBridge, + IMG_UINT32 ui32PhysHeapCount, + PVRSRV_PHYS_HEAP * peaPhysHeapID, + PHYS_HEAP_MEM_STATS_PKD * + psapPhysHeapMemStats); + +IMG_INTERNAL PVRSRV_ERROR BridgeGetHeapPhysMemUsagePkd(IMG_HANDLE hBridge, + IMG_UINT32 ui32PhysHeapCount, + PHYS_HEAP_MEM_STATS_PKD * + psapPhysHeapMemStats); + #endif /* CLIENT_MM_BRIDGE_H */ diff --git a/drivers/gpu/drm/img-rogue/client_mm_direct_bridge.c b/drivers/gpu/drm/img-rogue/client_mm_direct_bridge.c index df0a6f661..958706b63 100644 --- a/drivers/gpu/drm/img-rogue/client_mm_direct_bridge.c +++ b/drivers/gpu/drm/img-rogue/client_mm_direct_bridge.c @@ -773,3 +773,32 @@ IMG_INTERNAL PVRSRV_ERROR BridgePVRSRVUpdateOOMStats(IMG_HANDLE hBridge, return PVRSRV_ERROR_NOT_IMPLEMENTED; #endif } + +IMG_INTERNAL PVRSRV_ERROR BridgePhysHeapGetMemInfoPkd(IMG_HANDLE hBridge, + IMG_UINT32 ui32PhysHeapCount, + PVRSRV_PHYS_HEAP * peaPhysHeapID, + PHYS_HEAP_MEM_STATS_PKD * + psapPhysHeapMemStats) +{ + PVRSRV_ERROR eError; + + eError = + PVRSRVPhysHeapGetMemInfoPkdKM(NULL, (PVRSRV_DEVICE_NODE *) ((void *)hBridge), + ui32PhysHeapCount, peaPhysHeapID, psapPhysHeapMemStats); + + return eError; +} + +IMG_INTERNAL PVRSRV_ERROR BridgeGetHeapPhysMemUsagePkd(IMG_HANDLE hBridge, + IMG_UINT32 ui32PhysHeapCount, + PHYS_HEAP_MEM_STATS_PKD * + psapPhysHeapMemStats) +{ + PVRSRV_ERROR eError; + + eError = + PVRSRVGetHeapPhysMemUsagePkdKM(NULL, (PVRSRV_DEVICE_NODE *) ((void *)hBridge), + ui32PhysHeapCount, psapPhysHeapMemStats); + + return eError; +} diff --git a/drivers/gpu/drm/img-rogue/common_cache_bridge.h b/drivers/gpu/drm/img-rogue/common_cache_bridge.h index e8532f635..cc848753f 100644 --- a/drivers/gpu/drm/img-rogue/common_cache_bridge.h +++ b/drivers/gpu/drm/img-rogue/common_cache_bridge.h @@ -71,7 +71,6 @@ typedef struct PVRSRV_BRIDGE_IN_CACHEOPQUEUE_TAG IMG_DEVMEM_OFFSET_T *puiOffset; IMG_DEVMEM_SIZE_T *puiSize; IMG_HANDLE *phPMR; - IMG_UINT32 ui32CurrentFenceSeqNum; IMG_UINT32 ui32NumCacheOps; IMG_UINT32 ui32OpTimeline; } __packed PVRSRV_BRIDGE_IN_CACHEOPQUEUE; @@ -80,7 +79,6 @@ typedef struct PVRSRV_BRIDGE_IN_CACHEOPQUEUE_TAG typedef struct PVRSRV_BRIDGE_OUT_CACHEOPQUEUE_TAG { PVRSRV_ERROR eError; - IMG_UINT32 ui32NextFenceSeqNum; } __packed PVRSRV_BRIDGE_OUT_CACHEOPQUEUE; /******************************************* @@ -110,13 +108,12 @@ typedef struct PVRSRV_BRIDGE_OUT_CACHEOPEXEC_TAG /* Bridge in structure for CacheOpLog */ typedef struct PVRSRV_BRIDGE_IN_CACHEOPLOG_TAG { - IMG_INT64 i64ExecuteTimeUs; - IMG_INT64 i64QueuedTimeUs; + IMG_INT64 i64EndTime; + IMG_INT64 i64StartTime; IMG_UINT64 ui64Address; IMG_DEVMEM_OFFSET_T uiOffset; IMG_DEVMEM_SIZE_T uiSize; IMG_HANDLE hPMR; - IMG_INT32 i32NumRBF; PVRSRV_CACHE_OP iuCacheOp; } __packed PVRSRV_BRIDGE_IN_CACHEOPLOG; diff --git a/drivers/gpu/drm/img-rogue/common_dmabuf_bridge.h b/drivers/gpu/drm/img-rogue/common_dmabuf_bridge.h index 2a1456c05..7547d9f76 100644 --- a/drivers/gpu/drm/img-rogue/common_dmabuf_bridge.h +++ b/drivers/gpu/drm/img-rogue/common_dmabuf_bridge.h @@ -55,9 +55,9 @@ CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. #define PVRSRV_BRIDGE_DMABUF_CMD_FIRST 0 #define PVRSRV_BRIDGE_DMABUF_PHYSMEMIMPORTDMABUF PVRSRV_BRIDGE_DMABUF_CMD_FIRST+0 -#define PVRSRV_BRIDGE_DMABUF_PHYSMEMEXPORTDMABUF PVRSRV_BRIDGE_DMABUF_CMD_FIRST+1 -#define PVRSRV_BRIDGE_DMABUF_PHYSMEMIMPORTSPARSEDMABUF PVRSRV_BRIDGE_DMABUF_CMD_FIRST+2 -#define PVRSRV_BRIDGE_DMABUF_PHYSMEMIMPORTDMABUFLOCKED PVRSRV_BRIDGE_DMABUF_CMD_FIRST+3 +#define PVRSRV_BRIDGE_DMABUF_PHYSMEMIMPORTDMABUFLOCKED PVRSRV_BRIDGE_DMABUF_CMD_FIRST+1 +#define PVRSRV_BRIDGE_DMABUF_PHYSMEMEXPORTDMABUF PVRSRV_BRIDGE_DMABUF_CMD_FIRST+2 +#define PVRSRV_BRIDGE_DMABUF_PHYSMEMIMPORTSPARSEDMABUF PVRSRV_BRIDGE_DMABUF_CMD_FIRST+3 #define PVRSRV_BRIDGE_DMABUF_CMD_LAST (PVRSRV_BRIDGE_DMABUF_CMD_FIRST+3) /******************************************* @@ -82,6 +82,28 @@ typedef struct PVRSRV_BRIDGE_OUT_PHYSMEMIMPORTDMABUF_TAG PVRSRV_ERROR eError; } __packed PVRSRV_BRIDGE_OUT_PHYSMEMIMPORTDMABUF; +/******************************************* + PhysmemImportDmaBufLocked + *******************************************/ + +/* Bridge in structure for PhysmemImportDmaBufLocked */ +typedef struct PVRSRV_BRIDGE_IN_PHYSMEMIMPORTDMABUFLOCKED_TAG +{ + const IMG_CHAR *puiName; + IMG_INT ifd; + IMG_UINT32 ui32NameSize; + PVRSRV_MEMALLOCFLAGS_T uiFlags; +} __packed PVRSRV_BRIDGE_IN_PHYSMEMIMPORTDMABUFLOCKED; + +/* Bridge out structure for PhysmemImportDmaBufLocked */ +typedef struct PVRSRV_BRIDGE_OUT_PHYSMEMIMPORTDMABUFLOCKED_TAG +{ + IMG_DEVMEM_ALIGN_T uiAlign; + IMG_DEVMEM_SIZE_T uiSize; + IMG_HANDLE hPMRPtr; + PVRSRV_ERROR eError; +} __packed PVRSRV_BRIDGE_OUT_PHYSMEMIMPORTDMABUFLOCKED; + /******************************************* PhysmemExportDmaBuf *******************************************/ @@ -125,26 +147,4 @@ typedef struct PVRSRV_BRIDGE_OUT_PHYSMEMIMPORTSPARSEDMABUF_TAG PVRSRV_ERROR eError; } __packed PVRSRV_BRIDGE_OUT_PHYSMEMIMPORTSPARSEDMABUF; -/******************************************* - PhysmemImportDmaBufLocked - *******************************************/ - -/* Bridge in structure for PhysmemImportDmaBufLocked */ -typedef struct PVRSRV_BRIDGE_IN_PHYSMEMIMPORTDMABUFLOCKED_TAG -{ - const IMG_CHAR *puiName; - IMG_INT ifd; - IMG_UINT32 ui32NameSize; - PVRSRV_MEMALLOCFLAGS_T uiFlags; -} __packed PVRSRV_BRIDGE_IN_PHYSMEMIMPORTDMABUFLOCKED; - -/* Bridge out structure for PhysmemImportDmaBufLocked */ -typedef struct PVRSRV_BRIDGE_OUT_PHYSMEMIMPORTDMABUFLOCKED_TAG -{ - IMG_DEVMEM_ALIGN_T uiAlign; - IMG_DEVMEM_SIZE_T uiSize; - IMG_HANDLE hPMRPtr; - PVRSRV_ERROR eError; -} __packed PVRSRV_BRIDGE_OUT_PHYSMEMIMPORTDMABUFLOCKED; - #endif /* COMMON_DMABUF_BRIDGE_H */ diff --git a/drivers/gpu/drm/img-rogue/common_mm_bridge.h b/drivers/gpu/drm/img-rogue/common_mm_bridge.h index 21a893c0a..bbb419b3f 100644 --- a/drivers/gpu/drm/img-rogue/common_mm_bridge.h +++ b/drivers/gpu/drm/img-rogue/common_mm_bridge.h @@ -96,7 +96,9 @@ CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. #define PVRSRV_BRIDGE_MM_GETHEAPPHYSMEMUSAGE PVRSRV_BRIDGE_MM_CMD_FIRST+37 #define PVRSRV_BRIDGE_MM_DEVMEMGETFAULTADDRESS PVRSRV_BRIDGE_MM_CMD_FIRST+38 #define PVRSRV_BRIDGE_MM_PVRSRVUPDATEOOMSTATS PVRSRV_BRIDGE_MM_CMD_FIRST+39 -#define PVRSRV_BRIDGE_MM_CMD_LAST (PVRSRV_BRIDGE_MM_CMD_FIRST+39) +#define PVRSRV_BRIDGE_MM_PHYSHEAPGETMEMINFOPKD PVRSRV_BRIDGE_MM_CMD_FIRST+40 +#define PVRSRV_BRIDGE_MM_GETHEAPPHYSMEMUSAGEPKD PVRSRV_BRIDGE_MM_CMD_FIRST+41 +#define PVRSRV_BRIDGE_MM_CMD_LAST (PVRSRV_BRIDGE_MM_CMD_FIRST+41) /******************************************* PMRExportPMR @@ -837,4 +839,41 @@ typedef struct PVRSRV_BRIDGE_OUT_PVRSRVUPDATEOOMSTATS_TAG PVRSRV_ERROR eError; } __packed PVRSRV_BRIDGE_OUT_PVRSRVUPDATEOOMSTATS; +/******************************************* + PhysHeapGetMemInfoPkd + *******************************************/ + +/* Bridge in structure for PhysHeapGetMemInfoPkd */ +typedef struct PVRSRV_BRIDGE_IN_PHYSHEAPGETMEMINFOPKD_TAG +{ + PHYS_HEAP_MEM_STATS_PKD *psapPhysHeapMemStats; + PVRSRV_PHYS_HEAP *peaPhysHeapID; + IMG_UINT32 ui32PhysHeapCount; +} __packed PVRSRV_BRIDGE_IN_PHYSHEAPGETMEMINFOPKD; + +/* Bridge out structure for PhysHeapGetMemInfoPkd */ +typedef struct PVRSRV_BRIDGE_OUT_PHYSHEAPGETMEMINFOPKD_TAG +{ + PHYS_HEAP_MEM_STATS_PKD *psapPhysHeapMemStats; + PVRSRV_ERROR eError; +} __packed PVRSRV_BRIDGE_OUT_PHYSHEAPGETMEMINFOPKD; + +/******************************************* + GetHeapPhysMemUsagePkd + *******************************************/ + +/* Bridge in structure for GetHeapPhysMemUsagePkd */ +typedef struct PVRSRV_BRIDGE_IN_GETHEAPPHYSMEMUSAGEPKD_TAG +{ + PHYS_HEAP_MEM_STATS_PKD *psapPhysHeapMemStats; + IMG_UINT32 ui32PhysHeapCount; +} __packed PVRSRV_BRIDGE_IN_GETHEAPPHYSMEMUSAGEPKD; + +/* Bridge out structure for GetHeapPhysMemUsagePkd */ +typedef struct PVRSRV_BRIDGE_OUT_GETHEAPPHYSMEMUSAGEPKD_TAG +{ + PHYS_HEAP_MEM_STATS_PKD *psapPhysHeapMemStats; + PVRSRV_ERROR eError; +} __packed PVRSRV_BRIDGE_OUT_GETHEAPPHYSMEMUSAGEPKD; + #endif /* COMMON_MM_BRIDGE_H */ diff --git a/drivers/gpu/drm/img-rogue/common_rgxcmp_bridge.h b/drivers/gpu/drm/img-rogue/common_rgxcmp_bridge.h index dc6ed7d06..396bd3f01 100644 --- a/drivers/gpu/drm/img-rogue/common_rgxcmp_bridge.h +++ b/drivers/gpu/drm/img-rogue/common_rgxcmp_bridge.h @@ -174,7 +174,6 @@ typedef struct PVRSRV_BRIDGE_IN_RGXKICKCDM2_TAG IMG_HANDLE *phSyncPMRs; PVRSRV_FENCE hCheckFenceFd; PVRSRV_TIMELINE hUpdateTimeline; - IMG_UINT32 ui32ClientCacheOpSeqNum; IMG_UINT32 ui32ClientUpdateCount; IMG_UINT32 ui32CmdSize; IMG_UINT32 ui32ExtJobRef; diff --git a/drivers/gpu/drm/img-rogue/common_rgxkicksync_bridge.h b/drivers/gpu/drm/img-rogue/common_rgxkicksync_bridge.h index d0c1df3b6..afd882ca7 100644 --- a/drivers/gpu/drm/img-rogue/common_rgxkicksync_bridge.h +++ b/drivers/gpu/drm/img-rogue/common_rgxkicksync_bridge.h @@ -110,7 +110,6 @@ typedef struct PVRSRV_BRIDGE_IN_RGXKICKSYNC2_TAG IMG_HANDLE *phUpdateUFODevVarBlock; PVRSRV_FENCE hCheckFenceFD; PVRSRV_TIMELINE hTimelineFenceFD; - IMG_UINT32 ui32ClientCacheOpSeqNum; IMG_UINT32 ui32ClientUpdateCount; IMG_UINT32 ui32ExtJobRef; } __packed PVRSRV_BRIDGE_IN_RGXKICKSYNC2; diff --git a/drivers/gpu/drm/img-rogue/common_rgxta3d_bridge.h b/drivers/gpu/drm/img-rogue/common_rgxta3d_bridge.h index 65b001bca..b5fedd7fc 100644 --- a/drivers/gpu/drm/img-rogue/common_rgxta3d_bridge.h +++ b/drivers/gpu/drm/img-rogue/common_rgxta3d_bridge.h @@ -80,32 +80,32 @@ CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. /* Bridge in structure for RGXCreateHWRTDataSet */ typedef struct PVRSRV_BRIDGE_IN_RGXCREATEHWRTDATASET_TAG { - IMG_DEV_VIRTADDR sTailPtrsDevVAddr; - IMG_DEV_VIRTADDR ssRTCDevVAddr; - IMG_DEV_VIRTADDR ssVHeapTableDevVAddr; IMG_UINT64 ui64FlippedMultiSampleCtl; IMG_UINT64 ui64MultiSampleCtl; IMG_DEV_VIRTADDR *psMacrotileArrayDevVAddr; IMG_DEV_VIRTADDR *psPMMlistDevVAddr; + IMG_DEV_VIRTADDR *psRTCDevVAddr; IMG_DEV_VIRTADDR *psRgnHeaderDevVAddr; + IMG_DEV_VIRTADDR *psTailPtrsDevVAddr; + IMG_DEV_VIRTADDR *psVHeapTableDevVAddr; IMG_HANDLE *phKmHwRTDataSet; IMG_HANDLE *phapsFreeLists; + IMG_UINT32 ui32ISPMergeLowerX; + IMG_UINT32 ui32ISPMergeLowerY; + IMG_UINT32 ui32ISPMergeScaleX; + IMG_UINT32 ui32ISPMergeScaleY; + IMG_UINT32 ui32ISPMergeUpperX; + IMG_UINT32 ui32ISPMergeUpperY; + IMG_UINT32 ui32ISPMtileSize; IMG_UINT32 ui32MTileStride; IMG_UINT32 ui32PPPScreen; + IMG_UINT32 ui32RgnHeaderSize; IMG_UINT32 ui32TEAA; IMG_UINT32 ui32TEMTILE1; IMG_UINT32 ui32TEMTILE2; IMG_UINT32 ui32TEScreen; IMG_UINT32 ui32TPCSize; IMG_UINT32 ui32TPCStride; - IMG_UINT32 ui32ui32ISPMergeLowerX; - IMG_UINT32 ui32ui32ISPMergeLowerY; - IMG_UINT32 ui32ui32ISPMergeScaleX; - IMG_UINT32 ui32ui32ISPMergeScaleY; - IMG_UINT32 ui32ui32ISPMergeUpperX; - IMG_UINT32 ui32ui32ISPMergeUpperY; - IMG_UINT32 ui32ui32ISPMtileSize; - IMG_UINT32 ui32uiRgnHeaderSize; IMG_UINT16 ui16MaxRTs; } __packed PVRSRV_BRIDGE_IN_RGXCREATEHWRTDATASET; @@ -261,6 +261,7 @@ typedef struct PVRSRV_BRIDGE_IN_RGXCREATERENDERCONTEXT_TAG IMG_UINT32 ui32PackedCCBSizeU8888; IMG_UINT32 ui32Priority; IMG_UINT32 ui32StaticRenderContextStateSize; + IMG_UINT32 ui32ui32CallStackDepth; } __packed PVRSRV_BRIDGE_IN_RGXCREATERENDERCONTEXT; /* Bridge out structure for RGXCreateRenderContext */ @@ -359,16 +360,15 @@ typedef struct PVRSRV_BRIDGE_IN_RGXKICKTA3D2_TAG IMG_UINT32 ui323DCmdSize; IMG_UINT32 ui323DPRCmdSize; IMG_UINT32 ui32Client3DUpdateCount; - IMG_UINT32 ui32ClientCacheOpSeqNum; IMG_UINT32 ui32ClientTAFenceCount; IMG_UINT32 ui32ClientTAUpdateCount; IMG_UINT32 ui32ExtJobRef; - IMG_UINT32 ui32FRFenceUFOSyncOffset; - IMG_UINT32 ui32FRFenceValue; IMG_UINT32 ui32NumberOfDrawCalls; IMG_UINT32 ui32NumberOfIndices; IMG_UINT32 ui32NumberOfMRTs; IMG_UINT32 ui32PDumpFlags; + IMG_UINT32 ui32PRFenceUFOSyncOffset; + IMG_UINT32 ui32PRFenceValue; IMG_UINT32 ui32RenderTargetSize; IMG_UINT32 ui32SyncPMRCount; IMG_UINT32 ui32TACmdSize; diff --git a/drivers/gpu/drm/img-rogue/common_rgxtq2_bridge.h b/drivers/gpu/drm/img-rogue/common_rgxtq2_bridge.h index c76562780..9489ddae2 100644 --- a/drivers/gpu/drm/img-rogue/common_rgxtq2_bridge.h +++ b/drivers/gpu/drm/img-rogue/common_rgxtq2_bridge.h @@ -72,10 +72,11 @@ CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. /* Bridge in structure for RGXTDMCreateTransferContext */ typedef struct PVRSRV_BRIDGE_IN_RGXTDMCREATETRANSFERCONTEXT_TAG { + IMG_UINT64 ui64RobustnessAddress; IMG_HANDLE hPrivData; IMG_BYTE *pui8FrameworkCmd; IMG_UINT32 ui32ContextFlags; - IMG_UINT32 ui32FrameworkCmdize; + IMG_UINT32 ui32FrameworkCmdSize; IMG_UINT32 ui32PackedCCBSizeU88; IMG_UINT32 ui32Priority; } __packed PVRSRV_BRIDGE_IN_RGXTDMCREATETRANSFERCONTEXT; @@ -157,7 +158,6 @@ typedef struct PVRSRV_BRIDGE_IN_RGXTDMSUBMITTRANSFER2_TAG PVRSRV_TIMELINE hUpdateTimeline; IMG_UINT32 ui32Characteristic1; IMG_UINT32 ui32Characteristic2; - IMG_UINT32 ui32ClientCacheOpSeqNum; IMG_UINT32 ui32ClientUpdateCount; IMG_UINT32 ui32CommandSize; IMG_UINT32 ui32ExternalJobReference; diff --git a/drivers/gpu/drm/img-rogue/common_rgxtq_bridge.h b/drivers/gpu/drm/img-rogue/common_rgxtq_bridge.h index ce320bb4c..b8642845e 100644 --- a/drivers/gpu/drm/img-rogue/common_rgxtq_bridge.h +++ b/drivers/gpu/drm/img-rogue/common_rgxtq_bridge.h @@ -69,6 +69,7 @@ CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. /* Bridge in structure for RGXCreateTransferContext */ typedef struct PVRSRV_BRIDGE_IN_RGXCREATETRANSFERCONTEXT_TAG { + IMG_UINT64 ui64RobustnessAddress; IMG_HANDLE hPrivData; IMG_BYTE *pui8FrameworkCmd; IMG_UINT32 ui32ContextFlags; @@ -140,7 +141,6 @@ typedef struct PVRSRV_BRIDGE_IN_RGXSUBMITTRANSFER2_TAG PVRSRV_TIMELINE h2DUpdateTimeline; PVRSRV_TIMELINE h3DUpdateTimeline; PVRSRV_FENCE hCheckFenceFD; - IMG_UINT32 ui32ClientCacheOpSeqNum; IMG_UINT32 ui32ExtJobRef; IMG_UINT32 ui32PrepareCount; IMG_UINT32 ui32SyncPMRCount; diff --git a/drivers/gpu/drm/img-rogue/config_kernel.h b/drivers/gpu/drm/img-rogue/config_kernel.h index 4a3869d62..09dfc5b07 100644 --- a/drivers/gpu/drm/img-rogue/config_kernel.h +++ b/drivers/gpu/drm/img-rogue/config_kernel.h @@ -3,12 +3,11 @@ #define RGX_FW_FILENAME "rgx.fw" #define RGX_SH_FILENAME "rgx.sh" #define PVR_BUILD_DIR "thead_linux" -#define PVR_BUILD_TYPE "release" #define PVRSRV_MODNAME "pvrsrvkm" #define PVRSYNC_MODNAME "pvr_sync" #define SUPPORT_RGX 1 #define DISPLAY_CONTROLLER drm_nulldisp -#define RELEASE +#define PVRSRV_HWPERF_COUNTERS_PERBLK 12 #define RGX_BVNC_CORE_KM_HEADER "cores/rgxcore_km_36.52.104.182.h" #define RGX_BNC_CONFIG_KM_HEADER "configs/rgxconfig_km_36.V.104.182.h" #define PVRSRV_NEED_PVR_DPF @@ -51,7 +50,6 @@ #define PVRSRV_APPHINT_ENABLERANDOMCONTEXTSWITCH 0 #define PVRSRV_APPHINT_ENABLESOFTRESETCNTEXTSWITCH 0 #define PVRSRV_APPHINT_ENABLEFWCONTEXTSWITCH RGXFWIF_INICFG_OS_CTXSWITCH_DM_ALL -#define PVRSRV_APPHINT_VDMCONTEXTSWITCHMODE RGXFWIF_INICFG_VDM_CTX_STORE_MODE_INDEX #define PVRSRV_APPHINT_ENABLERDPOWERISLAND RGX_RD_POWER_ISLAND_DEFAULT #define PVRSRV_APPHINT_FIRMWAREPERF FW_PERF_CONF_NONE #define PVRSRV_APPHINT_FWCONTEXTSWITCHPROFILE RGXFWIF_CTXSWITCH_PROFILE_MEDIUM_EN @@ -104,6 +102,7 @@ #define PVRSRV_APPHINT_PHYSMEMTESTPASSES APPHNT_PHYSMEMTEST_ENABLE #define PVRSRV_APPHINT_TESTSLRINTERVAL 0 #define PVRSRV_APPHINT_RISCVDMITEST 0 +#define PVRSRV_APPHINT_VALIDATESOCUSCTIMERS 0 #define SOC_TIMER_FREQ 20 #define PDVFS_COM_HOST 1 #define PDVFS_COM_AP 2 @@ -115,8 +114,9 @@ #define PVR_GPIO_MODE PVR_GPIO_MODE_GENERAL #define PVRSRV_ENABLE_PROCESS_STATS #define SUPPORT_USC_BREAKPOINT +#define SUPPORT_AGP #define RGXFW_SAFETY_WATCHDOG_PERIOD_IN_US 1000000 -#define PVR_ANNOTATION_MAX_LEN 63 +#define PVRSRV_DEVICE_INIT_MODE PVRSRV_LINUX_DEV_INIT_ON_CONNECT #define SUPPORT_DI_BRG_IMPL #define PVR_LINUX_PHYSMEM_MAX_POOL_PAGES 10240 #define PVR_LINUX_PHYSMEM_MAX_EXCESS_POOL_PAGES 20480 @@ -148,3 +148,16 @@ #define PVRSRV_RGX_LOG2_CLIENT_CCB_MAX_SIZE_TDM 17 #define PVRSRV_RGX_LOG2_CLIENT_CCB_MAX_SIZE_RDM 15 #define SUPPORT_BUFFER_SYNC 1 +#ifdef CONFIG_DRM_POWERVR_ROGUE_DEBUG +#define DEBUG +#define DEBUG_BRIDGE_KM +#define PVRSRV_ENABLE_GPU_MEMORY_INFO +#define PVRSRV_ENABLE_SYNC_POISONING +#define PVR_ANNOTATION_MAX_LEN 96 +#define PVR_BUILD_TYPE "debug" +#define TRACK_FW_BOOT +#else +#define PVR_ANNOTATION_MAX_LEN 63 +#define PVR_BUILD_TYPE "release" +#define RELEASE +#endif diff --git a/drivers/gpu/drm/img-rogue/config_kernel.mk b/drivers/gpu/drm/img-rogue/config_kernel.mk index 42219560a..a727f5e8e 100644 --- a/drivers/gpu/drm/img-rogue/config_kernel.mk +++ b/drivers/gpu/drm/img-rogue/config_kernel.mk @@ -1,3 +1,4 @@ +override PVRSRV_DIR := services override HOST_PRIMARY_ARCH := host_x86_64 override HOST_32BIT_ARCH := host_i386 override HOST_FORCE_32BIT := -m32 @@ -20,7 +21,9 @@ override PVR_SYSTEM := rgx_thead override PVR_LOADER := override SORT_BRIDGE_STRUCTS := 1 override DEBUGLINK := 1 +override RGX_BNC := 36.V.104.182 override SUPPORT_PHYSMEM_TEST := 1 +override SUPPORT_MIPS_64K_PAGE_SIZE := override RGX_NUM_OS_SUPPORTED := 1 override VMM_TYPE := stub override SUPPORT_POWMON_COMPONENT := 1 @@ -48,4 +51,3 @@ else override BUILD := release override PVR_BUILD_TYPE := release endif - diff --git a/drivers/gpu/drm/img-rogue/configs/rgxconfig_km_1.V.4.5.h b/drivers/gpu/drm/img-rogue/configs/rgxconfig_km_1.V.4.5.h index 44be042e7..b29afcf0a 100644 --- a/drivers/gpu/drm/img-rogue/configs/rgxconfig_km_1.V.4.5.h +++ b/drivers/gpu/drm/img-rogue/configs/rgxconfig_km_1.V.4.5.h @@ -59,6 +59,8 @@ CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. #define RGX_FEATURE_COMPUTE_OVERLAP #define RGX_FEATURE_FBCDC_ALGORITHM (1U) #define RGX_FEATURE_FBCDC_ARCHITECTURE (1U) +#define RGX_FEATURE_FBC_MAX_DEFAULT_DESCRIPTORS (0U) +#define RGX_FEATURE_FBC_MAX_LARGE_DESCRIPTORS (0U) #define RGX_FEATURE_GS_RTA_SUPPORT #define RGX_FEATURE_LAYOUT_MARS (0U) #define RGX_FEATURE_META (MTP218) diff --git a/drivers/gpu/drm/img-rogue/configs/rgxconfig_km_36.V.104.182.h b/drivers/gpu/drm/img-rogue/configs/rgxconfig_km_36.V.104.182.h index cb251a8c7..0a6cdb0cd 100644 --- a/drivers/gpu/drm/img-rogue/configs/rgxconfig_km_36.V.104.182.h +++ b/drivers/gpu/drm/img-rogue/configs/rgxconfig_km_36.V.104.182.h @@ -62,6 +62,8 @@ CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. #define RGX_FEATURE_FBCDC (50U) #define RGX_FEATURE_FBCDC_ALGORITHM (50U) #define RGX_FEATURE_FBCDC_ARCHITECTURE (7U) +#define RGX_FEATURE_FBC_MAX_DEFAULT_DESCRIPTORS (0U) +#define RGX_FEATURE_FBC_MAX_LARGE_DESCRIPTORS (0U) #define RGX_FEATURE_GPU_MULTICORE_SUPPORT #define RGX_FEATURE_GPU_VIRTUALISATION #define RGX_FEATURE_GS_RTA_SUPPORT @@ -87,12 +89,14 @@ CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. /* size must be sourced from */ /* register. */ #define RGX_FEATURE_SLC_SIZE_IN_KILOBYTES (16U) +#define RGX_FEATURE_SOC_TIMER #define RGX_FEATURE_SYS_BUS_SECURE_RESET #define RGX_FEATURE_TILE_SIZE_X (16U) #define RGX_FEATURE_TILE_SIZE_Y (16U) #define RGX_FEATURE_TPU_CEM_DATAMASTER_GLOBAL_REGISTERS #define RGX_FEATURE_TPU_DM_GLOBAL_REGISTERS #define RGX_FEATURE_VIRTUAL_ADDRESS_SPACE_BITS (40U) +#define RGX_FEATURE_XE_ARCHITECTURE (1U) #define RGX_FEATURE_XE_MEMORY_HIERARCHY #define RGX_FEATURE_XPU_MAX_REGBANKS_ADDR_WIDTH (19U) #define RGX_FEATURE_XPU_MAX_SLAVES (3U) diff --git a/drivers/gpu/drm/img-rogue/connection_server.c b/drivers/gpu/drm/img-rogue/connection_server.c index 3c6ab13cb..92e0551e7 100644 --- a/drivers/gpu/drm/img-rogue/connection_server.c +++ b/drivers/gpu/drm/img-rogue/connection_server.c @@ -53,6 +53,7 @@ CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. #include "pdump_km.h" #include "osfunc.h" #include "tlstream.h" +#include "rgxhwperf_common.h" /* PID associated with Connection currently being purged by Cleanup thread */ static IMG_PID gCurrentPurgeConnectionPid; @@ -91,41 +92,9 @@ static PVRSRV_ERROR ConnectionDataDestroy(CONNECTION_DATA *psConnection) if (psProcessHandleBase != NULL) { - /* acquire the lock now to ensure unref and removal from the - * hash table is atomic. - * if the refcount becomes zero then the lock needs to be held - * until the entry is removed from the hash table. - */ - OSLockAcquire(psPVRSRVData->hProcessHandleBase_Lock); - - /* In case the refcount becomes 0 we can remove the process handle base */ - if (OSAtomicDecrement(&psProcessHandleBase->iRefCount) == 0) - { - uintptr_t uiHashValue; - - uiHashValue = HASH_Remove(psPVRSRVData->psProcessHandleBase_Table, psConnection->pid); - OSLockRelease(psPVRSRVData->hProcessHandleBase_Lock); - - if (!uiHashValue) - { - PVR_DPF((PVR_DBG_ERROR, - "%s: Failed to remove handle base from hash table.", - __func__)); - return PVRSRV_ERROR_UNABLE_TO_REMOVE_HASH_VALUE; - } - - eError = PVRSRVFreeKernelHandles(psProcessHandleBase->psHandleBase); - PVR_LOG_RETURN_IF_ERROR(eError, "PVRSRVFreeKernelHandles"); - - eError = PVRSRVFreeHandleBase(psProcessHandleBase->psHandleBase, ui64MaxBridgeTime); - PVR_LOG_RETURN_IF_ERROR(eError, "PVRSRVFreeHandleBase:1"); - - OSFreeMem(psProcessHandleBase); - } - else - { - OSLockRelease(psPVRSRVData->hProcessHandleBase_Lock); - } + eError = PVRSRVReleaseProcessHandleBase(psProcessHandleBase, psConnection->pid, + ui64MaxBridgeTime); + PVR_LOG_RETURN_IF_ERROR(eError, "PVRSRVReleaseProcessHandleBase"); psConnection->psProcessHandleBase = NULL; } @@ -195,7 +164,6 @@ PVRSRV_ERROR PVRSRVCommonConnectionConnect(void **ppvPrivData, void *pvOSData) CONNECTION_DATA *psConnection; PVRSRV_ERROR eError; PROCESS_HANDLE_BASE *psProcessHandleBase; - PVRSRV_DATA *psPVRSRVData = PVRSRVGetPVRSRVData(); /* Allocate connection data area, no stats since process not registered yet */ psConnection = OSAllocZMemNoStats(sizeof(*psConnection)); @@ -245,46 +213,14 @@ PVRSRV_ERROR PVRSRVCommonConnectionConnect(void **ppvPrivData, void *pvOSData) PVRSRV_HANDLE_BASE_TYPE_CONNECTION); PVR_LOG_GOTO_IF_ERROR(eError, "PVRSRVAllocHandleBase", failure); - /* Try to get process handle base if it already exists */ - OSLockAcquire(psPVRSRVData->hProcessHandleBase_Lock); - psProcessHandleBase = (PROCESS_HANDLE_BASE*) HASH_Retrieve(PVRSRVGetPVRSRVData()->psProcessHandleBase_Table, - psConnection->pid); - - /* In case there is none we are going to allocate one */ - if (psProcessHandleBase == NULL) - { - psProcessHandleBase = OSAllocZMem(sizeof(PROCESS_HANDLE_BASE)); - PVR_LOG_GOTO_IF_NOMEM(psProcessHandleBase, eError, failureLock); - - OSAtomicWrite(&psProcessHandleBase->iRefCount, 0); - - /* Allocate handle base for this process */ - eError = PVRSRVAllocHandleBase(&psProcessHandleBase->psHandleBase, - PVRSRV_HANDLE_BASE_TYPE_PROCESS); - if (eError != PVRSRV_OK) - { - PVR_LOG_ERROR(eError, "PVRSRVAllocHandleBase"); - OSFreeMem(psProcessHandleBase); - goto failureLock; - } - - /* Insert the handle base into the global hash table */ - if (!HASH_Insert(PVRSRVGetPVRSRVData()->psProcessHandleBase_Table, - psConnection->pid, - (uintptr_t) psProcessHandleBase)) - { - PVRSRVFreeHandleBase(psProcessHandleBase->psHandleBase, 0); - - OSFreeMem(psProcessHandleBase); - PVR_GOTO_WITH_ERROR(eError, PVRSRV_ERROR_UNABLE_TO_INSERT_HASH_VALUE, failureLock); - } - } - OSAtomicIncrement(&psProcessHandleBase->iRefCount); - - OSLockRelease(psPVRSRVData->hProcessHandleBase_Lock); + /* get process handle base (if it doesn't exist it will be allocated) */ + eError = PVRSRVAcquireProcessHandleBase(psConnection->pid, &psProcessHandleBase); + PVR_LOG_GOTO_IF_ERROR(eError, "PVRSRVAcquireProcessHandleBase", failure); /* hConnectionsLock now resides in PVRSRV_DEVICE_NODE */ { + IMG_BOOL bHostStreamIsNull; + PVRSRV_RGXDEV_INFO *psRgxDevInfo; PVRSRV_DEVICE_NODE *psDevNode = OSGetDevNode(psConnection); OSLockAcquire(psDevNode->hConnectionsLock); @@ -294,6 +230,24 @@ PVRSRV_ERROR PVRSRVCommonConnectionConnect(void **ppvPrivData, void *pvOSData) psDevNode->sDevId.ui32InternalID)); #endif OSLockRelease(psDevNode->hConnectionsLock); + + if (!PVRSRV_VZ_MODE_IS(GUEST)) + { + psRgxDevInfo = _RGX_DEVICE_INFO_FROM_NODE(psDevNode); + + OSLockAcquire(psRgxDevInfo->hLockHWPerfHostStream); + bHostStreamIsNull = (IMG_BOOL)(psRgxDevInfo->hHWPerfHostStream == NULL); + OSLockRelease(psRgxDevInfo->hLockHWPerfHostStream); + + if (!bHostStreamIsNull) + { + if (TLStreamIsOpenForReading(psRgxDevInfo->hHWPerfHostStream)) + { + /* Announce this client connection in the host stream, if event mask is set */ + RGXSRV_HWPERF_HOST_CLIENT_INFO_PROCESS_NAME(psDevNode, psConnection->pid, psConnection->pszProcName); + } + } + } } psConnection->psProcessHandleBase = psProcessHandleBase; @@ -302,8 +256,6 @@ PVRSRV_ERROR PVRSRVCommonConnectionConnect(void **ppvPrivData, void *pvOSData) return PVRSRV_OK; -failureLock: - OSLockRelease(psPVRSRVData->hProcessHandleBase_Lock); failure: ConnectionDataDestroy(psConnection); @@ -461,80 +413,79 @@ void PVRSRVConnectionDebugNotify(PVRSRV_DEVICE_NODE *psDevNode, if (psDevNode->eDevState != PVRSRV_DEVICE_STATE_ACTIVE) { PVR_DUMPDEBUG_LOG("Connections: No Devices: No active connections"); + return; + } + + OSLockAcquire(psDevNode->hConnectionsLock); + if (dllist_is_empty(&psDevNode->sConnections)) + { + PVR_DUMPDEBUG_LOG(CONNECTIONS_PREFIX " No active connections", + (unsigned char)psDevNode->sDevId.ui32InternalID, + (unsigned char)psDevNode->sDevId.i32OsDeviceID); } else { - OSLockAcquire(psDevNode->hConnectionsLock); - if (dllist_is_empty(&psDevNode->sConnections)) - { - PVR_DUMPDEBUG_LOG(CONNECTIONS_PREFIX " No active connections", - (unsigned char)psDevNode->sDevId.ui32InternalID, - (unsigned char)psDevNode->sDevId.i32OsDeviceID); - } - else - { - IMG_CHAR sActiveConnections[MAX_DEBUG_DUMP_STRING_LEN]; - IMG_UINT16 i, uiPos = 0; - IMG_BOOL bPrinted = IMG_FALSE; - size_t uiSize = sizeof(sActiveConnections); + IMG_CHAR sActiveConnections[MAX_DEBUG_DUMP_STRING_LEN]; + IMG_UINT16 i, uiPos = 0; + IMG_BOOL bPrinted = IMG_FALSE; + size_t uiSize = sizeof(sActiveConnections); - IMG_CHAR szTmpConBuff[MAX_CONNECTIONS_PREFIX + 1]; - i = OSSNPrintf(szTmpConBuff, - MAX_CONNECTIONS_PREFIX, - CONNECTIONS_PREFIX, - (unsigned char)psDevNode->sDevId.ui32InternalID, - (unsigned char)psDevNode->sDevId.i32OsDeviceID); - OSStringLCopy(sActiveConnections+uiPos, szTmpConBuff, uiSize); + IMG_CHAR szTmpConBuff[MAX_CONNECTIONS_PREFIX + 1]; + i = OSSNPrintf(szTmpConBuff, + MAX_CONNECTIONS_PREFIX, + CONNECTIONS_PREFIX, + (unsigned char)psDevNode->sDevId.ui32InternalID, + (unsigned char)psDevNode->sDevId.i32OsDeviceID); + OSStringLCopy(sActiveConnections+uiPos, szTmpConBuff, uiSize); + + /* Move the write offset to the end of the current string */ + uiPos += i; + /* Update the amount of remaining space available to copy into */ + uiSize -= i; + + dllist_foreach_node(&psDevNode->sConnections, pNode, pNext) + { + CONNECTION_DATA *sData = IMG_CONTAINER_OF(pNode, CONNECTION_DATA, sConnectionListNode); + + IMG_CHAR sTmpBuff[MAX_DEBUG_DUMP_CONNECTION_STR_LEN]; + i = OSSNPrintf(sTmpBuff, MAX_DEBUG_DUMP_CONNECTION_STR_LEN, + DEBUG_DUMP_CONNECTION_FORMAT_STR, sData->pid, sData->vpid, sData->tid, sData->pszProcName); + i = MIN(MAX_DEBUG_DUMP_CONNECTION_STR_LEN, i); + bPrinted = IMG_FALSE; + + OSStringLCopy(sActiveConnections+uiPos, sTmpBuff, uiSize); /* Move the write offset to the end of the current string */ uiPos += i; /* Update the amount of remaining space available to copy into */ uiSize -= i; - dllist_foreach_node(&psDevNode->sConnections, pNode, pNext) + /* If there is not enough space to add another connection to this line, output the line */ + if (uiSize <= MAX_DEBUG_DUMP_CONNECTION_STR_LEN) { - CONNECTION_DATA *sData = IMG_CONTAINER_OF(pNode, CONNECTION_DATA, sConnectionListNode); - - IMG_CHAR sTmpBuff[MAX_DEBUG_DUMP_CONNECTION_STR_LEN]; - i = OSSNPrintf(sTmpBuff, MAX_DEBUG_DUMP_CONNECTION_STR_LEN, - DEBUG_DUMP_CONNECTION_FORMAT_STR, sData->pid, sData->vpid, sData->tid, sData->pszProcName); - i = MIN(MAX_DEBUG_DUMP_CONNECTION_STR_LEN, i); - bPrinted = IMG_FALSE; - - OSStringLCopy(sActiveConnections+uiPos, sTmpBuff, uiSize); - - /* Move the write offset to the end of the current string */ - uiPos += i; - /* Update the amount of remaining space available to copy into */ - uiSize -= i; - - /* If there is not enough space to add another connection to this line, output the line */ - if (uiSize <= MAX_DEBUG_DUMP_CONNECTION_STR_LEN) - { - PVR_DUMPDEBUG_LOG("%s", sActiveConnections); - - /* - * Remove the "Connections:" prefix from the buffer. - * Leave the subsequent buffer contents indented by the same - * amount to aid in interpreting the debug output. - */ - uiPos = sizeof(CONNECTIONS_PREFIX) - 1; - /* Reset the amount of space available to copy into */ - uiSize = MAX_DEBUG_DUMP_STRING_LEN - uiPos; - bPrinted = IMG_TRUE; - } - } - - /* Only print the current line if it hasn't already been printed */ - if (!bPrinted) - { - // Strip of the final comma - sActiveConnections[OSStringNLength(sActiveConnections, MAX_DEBUG_DUMP_STRING_LEN) - 1] = '\0'; PVR_DUMPDEBUG_LOG("%s", sActiveConnections); + + /* + * Remove the "Connections:" prefix from the buffer. + * Leave the subsequent buffer contents indented by the same + * amount to aid in interpreting the debug output. + */ + uiPos = sizeof(CONNECTIONS_PREFIX) - 1; + /* Reset the amount of space available to copy into */ + uiSize = MAX_DEBUG_DUMP_STRING_LEN - uiPos; + bPrinted = IMG_TRUE; } + } + + /* Only print the current line if it hasn't already been printed */ + if (!bPrinted) + { + /* Strip off the final comma */ + sActiveConnections[OSStringNLength(sActiveConnections, MAX_DEBUG_DUMP_STRING_LEN) - 1] = '\0'; + PVR_DUMPDEBUG_LOG("%s", sActiveConnections); + } #undef MAX_DEBUG_DUMP_STRING_LEN #undef MAX_DEBUG_DUMP_CONNECTIONS_PER_LINE - } - OSLockRelease(psDevNode->hConnectionsLock); } + OSLockRelease(psDevNode->hConnectionsLock); } diff --git a/drivers/gpu/drm/img-rogue/connection_server.h b/drivers/gpu/drm/img-rogue/connection_server.h index 27b2d1aad..d11a6eae8 100644 --- a/drivers/gpu/drm/img-rogue/connection_server.h +++ b/drivers/gpu/drm/img-rogue/connection_server.h @@ -117,6 +117,15 @@ typedef struct _CONNECTION_DATA_ PVRSRV_ERROR PVRSRVCommonConnectionConnect(void **ppvPrivData, void *pvOSData); void PVRSRVCommonConnectionDisconnect(void *pvPrivData); +/**************************************************************************/ /*! +@Function PVRSRVGetPurgeConnectionPid + +@Description Returns PID associated with Connection currently being purged by + Cleanup Thread. If no Connection is purged 0 is returned. + +@Return PID associated with currently purged connection or 0 if no + connection is being purged +*/ /***************************************************************************/ IMG_PID PVRSRVGetPurgeConnectionPid(void); void PVRSRVConnectionDebugNotify(PVRSRV_DEVICE_NODE *psDevNode, diff --git a/drivers/gpu/drm/img-rogue/cores/rgxcore_km_1.82.4.5.h b/drivers/gpu/drm/img-rogue/cores/rgxcore_km_1.82.4.5.h index da5f543d9..7629672b1 100644 --- a/drivers/gpu/drm/img-rogue/cores/rgxcore_km_1.82.4.5.h +++ b/drivers/gpu/drm/img-rogue/cores/rgxcore_km_1.82.4.5.h @@ -42,7 +42,7 @@ CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. #ifndef RGXCORE_KM_1_82_4_5_H #define RGXCORE_KM_1_82_4_5_H -/* Automatically generated file (29/06/2021 09:01:16): Do not edit manually */ +/* Automatically generated file (04/10/2021 09:01:50): Do not edit manually */ /* CS: @2503111 */ /****************************************************************************** diff --git a/drivers/gpu/drm/img-rogue/cores/rgxcore_km_36.52.104.182.h b/drivers/gpu/drm/img-rogue/cores/rgxcore_km_36.52.104.182.h index 6657f5410..a3f09195c 100644 --- a/drivers/gpu/drm/img-rogue/cores/rgxcore_km_36.52.104.182.h +++ b/drivers/gpu/drm/img-rogue/cores/rgxcore_km_36.52.104.182.h @@ -42,7 +42,7 @@ CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. #ifndef RGXCORE_KM_36_52_104_182_H #define RGXCORE_KM_36_52_104_182_H -/* Automatically generated file (29/06/2021 09:01:17): Do not edit manually */ +/* Automatically generated file (04/10/2021 09:01:50): Do not edit manually */ /* CS: @5849605 */ /****************************************************************************** diff --git a/drivers/gpu/drm/img-rogue/debug_common.c b/drivers/gpu/drm/img-rogue/debug_common.c index 9b0e4ead8..ee17281cb 100644 --- a/drivers/gpu/drm/img-rogue/debug_common.c +++ b/drivers/gpu/drm/img-rogue/debug_common.c @@ -58,17 +58,13 @@ CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. #include "rgxdevice.h" #include "rgxdebug.h" #include "rgxinit.h" +#include "rgxmmudefs_km.h" static IMG_HANDLE ghGpuUtilUserDebugFS; #endif static DI_ENTRY *gpsVersionDIEntry; static DI_ENTRY *gpsStatusDIEntry; -#ifdef SUPPORT_RGX -#ifdef SUPPORT_FIRMWARE_GCOV -static DI_ENTRY *gpsFirmwareGcovDIEntry; -#endif /* SUPPORT_FIRMWARE_GCOV */ -#endif /* SUPPORT_RGX */ #ifdef SUPPORT_VALIDATION static DI_ENTRY *gpsTestMemLeakDIEntry; #endif /* SUPPORT_VALIDATION */ @@ -108,6 +104,7 @@ static void *_VersionDIStart(OSDI_IMPL_ENTRY *psEntry, IMG_UINT64 *pui64Pos) { PVRSRV_DATA *psPVRSRVData = DIGetPrivData(psEntry); IMG_UINT64 uiCurrentPosition = 1; + PVRSRV_DEVICE_NODE *psDeviceNode; PVR_UNREFERENCED_PARAMETER(psEntry); @@ -121,10 +118,14 @@ static void *_VersionDIStart(OSDI_IMPL_ENTRY *psEntry, IMG_UINT64 *pui64Pos) return DI_START_TOKEN; } - return List_PVRSRV_DEVICE_NODE_Any_va(psPVRSRVData->psDeviceNodeList, + OSWRLockAcquireRead(psPVRSRVData->hDeviceNodeListLock); + psDeviceNode = List_PVRSRV_DEVICE_NODE_Any_va(psPVRSRVData->psDeviceNodeList, _DebugVersionCompare_AnyVaCb, &uiCurrentPosition, *pui64Pos); + OSWRLockReleaseRead(psPVRSRVData->hDeviceNodeListLock); + + return psDeviceNode; } static void _VersionDIStop(OSDI_IMPL_ENTRY *psEntry, void *pvPriv) @@ -138,13 +139,18 @@ static void *_VersionDINext(OSDI_IMPL_ENTRY *psEntry,void *pvPriv, { PVRSRV_DATA *psPVRSRVData = DIGetPrivData(psEntry); IMG_UINT64 uiCurrentPosition = 1; + PVRSRV_DEVICE_NODE *psDeviceNode; (*pui64Pos)++; - return List_PVRSRV_DEVICE_NODE_Any_va(psPVRSRVData->psDeviceNodeList, + OSWRLockAcquireRead(psPVRSRVData->hDeviceNodeListLock); + psDeviceNode = List_PVRSRV_DEVICE_NODE_Any_va(psPVRSRVData->psDeviceNodeList, _DebugVersionCompare_AnyVaCb, &uiCurrentPosition, *pui64Pos); + OSWRLockReleaseRead(psPVRSRVData->hDeviceNodeListLock); + + return psDeviceNode; } #define DI_PRINT_VERSION_FMTSPEC \ @@ -518,16 +524,21 @@ static void *_DebugStatusDIStart(OSDI_IMPL_ENTRY *psEntry, IMG_UINT64 *pui64Pos) { PVRSRV_DATA *psPVRSRVData = DIGetPrivData(psEntry); IMG_UINT64 uiCurrentPosition = 1; + PVRSRV_DEVICE_NODE *psDeviceNode; if (*pui64Pos == 0) { return DI_START_TOKEN; } - return List_PVRSRV_DEVICE_NODE_Any_va(psPVRSRVData->psDeviceNodeList, + OSWRLockAcquireRead(psPVRSRVData->hDeviceNodeListLock); + psDeviceNode = List_PVRSRV_DEVICE_NODE_Any_va(psPVRSRVData->psDeviceNodeList, _DebugStatusCompare_AnyVaCb, &uiCurrentPosition, *pui64Pos); + OSWRLockReleaseRead(psPVRSRVData->hDeviceNodeListLock); + + return psDeviceNode; } static void _DebugStatusDIStop(OSDI_IMPL_ENTRY *psEntry, void *pvData) @@ -542,15 +553,20 @@ static void *_DebugStatusDINext(OSDI_IMPL_ENTRY *psEntry, { PVRSRV_DATA *psPVRSRVData = DIGetPrivData(psEntry); IMG_UINT64 uiCurrentPosition = 1; + PVRSRV_DEVICE_NODE *psDeviceNode; PVR_UNREFERENCED_PARAMETER(pvData); (*pui64Pos)++; - return List_PVRSRV_DEVICE_NODE_Any_va(psPVRSRVData->psDeviceNodeList, + OSWRLockAcquireRead(psPVRSRVData->hDeviceNodeListLock); + psDeviceNode = List_PVRSRV_DEVICE_NODE_Any_va(psPVRSRVData->psDeviceNodeList, _DebugStatusCompare_AnyVaCb, &uiCurrentPosition, *pui64Pos); + OSWRLockReleaseRead(psPVRSRVData->hDeviceNodeListLock); + + return psDeviceNode; } static int _DebugStatusDIShow(OSDI_IMPL_ENTRY *psEntry, void *pvData) @@ -779,26 +795,155 @@ static int _DebugFWTraceDIShow(OSDI_IMPL_ENTRY *psEntry, void *pvData) return 0; } -#ifdef SUPPORT_FIRMWARE_GCOV +/*************************************************************************/ /*! + Firmware Translated Page Tables DebugFS entry +*/ /**************************************************************************/ -static PVRSRV_RGXDEV_INFO *getPsDevInfo(OSDI_IMPL_ENTRY *psEntry) +static void _DocumentFwMapping(OSDI_IMPL_ENTRY *psEntry, + PVRSRV_RGXDEV_INFO *psDevInfo, + IMG_UINT32 ui32FwVA, + IMG_CPU_PHYADDR sCpuPA, + IMG_DEV_PHYADDR sDevPA, + IMG_UINT64 ui64PTE) { - PVRSRV_DATA *psPVRSRVData = DIGetPrivData(psEntry); - - if (psPVRSRVData != NULL) +#if defined(RGX_FEATURE_MIPS_BIT_MASK) + if (RGX_IS_FEATURE_SUPPORTED(psDevInfo, MIPS)) { - if (psPVRSRVData->psDeviceNodeList != NULL) + DIPrintf(psEntry, "| 0x%8X | " + "0x%16" IMG_UINT64_FMTSPECX " | " + "0x%16" IMG_UINT64_FMTSPECX " | " + "%s%s%s |\n", + ui32FwVA, + (IMG_UINT64) sCpuPA.uiAddr, + sDevPA.uiAddr, + gapszMipsPermissionPTFlags[RGXMIPSFW_TLB_GET_INHIBIT(ui64PTE)], + gapszMipsDirtyGlobalValidPTFlags[RGXMIPSFW_TLB_GET_DGV(ui64PTE)], + gapszMipsCoherencyPTFlags[RGXMIPSFW_TLB_GET_COHERENCY(ui64PTE)]); + } + else +#endif + { + /* META and RISCV use a subset of the GPU's virtual address space */ + DIPrintf(psEntry, "| 0x%8X | " + "0x%16" IMG_UINT64_FMTSPECX " | " + "0x%16" IMG_UINT64_FMTSPECX " | " + "%s%s%s%s%s%s |\n", + ui32FwVA, + (IMG_UINT64) sCpuPA.uiAddr, + sDevPA.uiAddr, + BITMASK_HAS(ui64PTE, RGX_MMUCTRL_PT_DATA_ENTRY_PENDING_EN) ? "P" : " ", + BITMASK_HAS(ui64PTE, RGX_MMUCTRL_PT_DATA_PM_SRC_EN) ? "PM" : " ", +#if defined(RGX_MMUCTRL_PT_DATA_SLC_BYPASS_CTRL_EN) + BITMASK_HAS(ui64PTE, RGX_MMUCTRL_PT_DATA_SLC_BYPASS_CTRL_EN) ? "B" : " ", +#else + " ", +#endif + BITMASK_HAS(ui64PTE, RGX_MMUCTRL_PT_DATA_CC_EN) ? "C" : " ", + BITMASK_HAS(ui64PTE, RGX_MMUCTRL_PT_DATA_READ_ONLY_EN) ? "RO" : "RW", + BITMASK_HAS(ui64PTE, RGX_MMUCTRL_PT_DATA_VALID_EN) ? "V" : " "); + } +} + +static int _FirmwareMappingsDIShow(OSDI_IMPL_ENTRY *psEntry, void *pvData) +{ + PVRSRV_DEVICE_NODE *psDeviceNode; + PVRSRV_RGXDEV_INFO *psDevInfo; + IMG_UINT32 ui32FwVA; + IMG_UINT32 ui32FwPageSize; + IMG_UINT32 ui32OSID; + + psDeviceNode = DIGetPrivData(psEntry); + + if ((psDeviceNode == NULL) || + (psDeviceNode->pvDevice == NULL) || + (((PVRSRV_RGXDEV_INFO *)psDeviceNode->pvDevice)->psKernelMMUCtx == NULL)) + { + /* The Kernel MMU context containing the Firmware mappings is not initialised */ + return 0; + } + + psDevInfo = psDeviceNode->pvDevice; + + DIPrintf(psEntry, "+-----------------+------------------------+------------------------+--------------+\n" + "| Firmware | CPU | Device | PTE |\n" + "| Virtual Address | Physical Address | Physical Address | Flags |\n" + "+-----------------+------------------------+------------------------+ +\n"); + +#if defined(RGX_FEATURE_MIPS_BIT_MASK) + if (RGX_IS_FEATURE_SUPPORTED(psDevInfo, MIPS)) + { + DIPrintf(psEntry, "| RI/XI = Read / Execution Inhibit |\n" + "| C = Cache Coherent |\n" + "| D = Dirty Page Table Entry |\n" + "| V = Valid Page Table Entry |\n" + "| G = Global Page Table Entry |\n" + "+-----------------+------------------------+------------------------+--------------+\n"); + + /* MIPS uses the same page size as the OS */ + ui32FwPageSize = OSGetPageSize(); + } + else +#endif + { + DIPrintf(psEntry, "| P = Pending Page Table Entry |\n" + "| PM = Parameter Manager Source |\n" + "| B = Bypass SLC |\n" + "| C = Cache Coherent |\n" + "| RW/RO = Device Access Rights |\n" + "| V = Valid Page Table Entry |\n" + "+-----------------+------------------------+------------------------+--------------+\n"); + + ui32FwPageSize = BIT(RGX_MMUCTRL_PAGE_4KB_RANGE_SHIFT); + } + + for (ui32OSID = 0; ui32OSID < RGX_NUM_OS_SUPPORTED; ui32OSID++) + { + IMG_UINT32 ui32FwHeapBase = (IMG_UINT32) ((RGX_FIRMWARE_RAW_HEAP_BASE + + (ui32OSID * RGX_FIRMWARE_RAW_HEAP_SIZE)) & UINT_MAX); + IMG_UINT32 ui32FwHeapEnd = ui32FwHeapBase + (IMG_UINT32) (RGX_FIRMWARE_RAW_HEAP_SIZE & UINT_MAX); + + DIPrintf(psEntry, "| OS ID %u |\n" + "+-----------------+------------------------+------------------------+--------------+\n", ui32OSID); + + for (ui32FwVA = ui32FwHeapBase; + ui32FwVA < ui32FwHeapEnd; + ui32FwVA += ui32FwPageSize) { - PVRSRV_RGXDEV_INFO *psDevInfo = (PVRSRV_RGXDEV_INFO*)psPVRSRVData->psDeviceNodeList->pvDevice; - return psDevInfo; + PVRSRV_ERROR eError; + IMG_UINT64 ui64PTE = 0U; + IMG_CPU_PHYADDR sCpuPA = {0U}; + IMG_DEV_PHYADDR sDevPA = {0U}; + + eError = RGXGetFwMapping(psDevInfo, ui32FwVA, &sCpuPA, &sDevPA, &ui64PTE); + + if (eError == PVRSRV_OK) + { + _DocumentFwMapping(psEntry, psDevInfo, ui32FwVA, sCpuPA, sDevPA, ui64PTE); + } + else if (eError != PVRSRV_ERROR_DEVICEMEM_NO_MAPPING) + { + PVR_LOG_ERROR(eError, "RGXGetFwMapping"); + return -EIO; + } + } + + DIPrintf(psEntry, "+-----------------+------------------------+------------------------+--------------+\n"); + + if (PVRSRV_VZ_MODE_IS(NATIVE)) + { + break; } } - return NULL; + + return 0; } +#ifdef SUPPORT_FIRMWARE_GCOV + static void *_FirmwareGcovDIStart(OSDI_IMPL_ENTRY *psEntry, IMG_UINT64 *pui64Pos) { - PVRSRV_RGXDEV_INFO *psDevInfo = getPsDevInfo(psEntry); + PVRSRV_DEVICE_NODE *psDeviceNode = DIGetPrivData(psEntry); + PVRSRV_RGXDEV_INFO *psDevInfo = psDeviceNode->pvDevice; if (psDevInfo != NULL) { @@ -815,7 +960,8 @@ static void *_FirmwareGcovDIStart(OSDI_IMPL_ENTRY *psEntry, IMG_UINT64 *pui64Pos static void _FirmwareGcovDIStop(OSDI_IMPL_ENTRY *psEntry, void *pvData) { - PVRSRV_RGXDEV_INFO *psDevInfo = getPsDevInfo(psEntry); + PVRSRV_DEVICE_NODE *psDeviceNode = DIGetPrivData(psEntry); + PVRSRV_RGXDEV_INFO *psDevInfo = psDeviceNode->pvDevice; PVR_UNREFERENCED_PARAMETER(pvData); @@ -840,7 +986,8 @@ static void *_FirmwareGcovDINext(OSDI_IMPL_ENTRY *psEntry, static int _FirmwareGcovDIShow(OSDI_IMPL_ENTRY *psEntry, void *pvData) { - PVRSRV_RGXDEV_INFO *psDevInfo = getPsDevInfo(psEntry); + PVRSRV_DEVICE_NODE *psDeviceNode = DIGetPrivData(psEntry); + PVRSRV_RGXDEV_INFO *psDevInfo = psDeviceNode->pvDevice; if (psDevInfo != NULL) { @@ -1225,35 +1372,22 @@ PVRSRV_ERROR DebugCommonInitDriver(void) .pfnStop = _DebugStatusDIStop, .pfnNext = _DebugStatusDINext, .pfnShow = _DebugStatusDIShow, - .pfnWrite = DebugStatusSet + .pfnWrite = DebugStatusSet, + //'K' expected + Null terminator + .ui32WriteLenMax= ((1U)+1U) }; eError = DICreateEntry("status", NULL, &sIterator, psPVRSRVData, DI_ENTRY_TYPE_GENERIC, &gpsStatusDIEntry); PVR_GOTO_IF_ERROR(eError, return_error_); } -#ifdef SUPPORT_RGX -#ifdef SUPPORT_FIRMWARE_GCOV - { - DI_ITERATOR_CB sIterator = { - .pfnStart = _FirmwareGcovDIStart, - .pfnStop = _FirmwareGcovDIStop, - .pfnNext = _FirmwareGcovDINext, - .pfnShow = _FirmwareGcovDIShow - }; - - eError = DICreateEntry("firmware_gcov", NULL, &sIterator, psPVRSRVData, - DI_ENTRY_TYPE_GENERIC, &gpsFirmwareGcovDIEntry); - PVR_GOTO_IF_ERROR(eError, return_error_); - } -#endif /* SUPPORT_FIRMWARE_GCOV */ -#endif /* SUPPORT_RGX */ - #ifdef SUPPORT_VALIDATION { DI_ITERATOR_CB sIterator = { .pfnShow = TestMemLeakDIShow, - .pfnWrite = TestMemLeakDISet + .pfnWrite = TestMemLeakDISet, + //Function only allows max 15 chars + Null terminator + .ui32WriteLenMax = ((15U)+1U) }; eError = DICreateEntry("test_memleak", NULL, &sIterator, psPVRSRVData, DI_ENTRY_TYPE_GENERIC, &gpsTestMemLeakDIEntry); @@ -1265,7 +1399,9 @@ PVRSRV_ERROR DebugCommonInitDriver(void) { DI_ITERATOR_CB sIterator = { .pfnShow = DebugLevelDIShow, - .pfnWrite = DebugLevelSet + .pfnWrite = DebugLevelSet, + //Max value of 255(3 char) + Null terminator + .ui32WriteLenMax =((3U)+1U) }; eError = DICreateEntry("debug_level", NULL, &sIterator, NULL, DI_ENTRY_TYPE_GENERIC, &gpsDebugLevelDIEntry); @@ -1298,15 +1434,6 @@ void DebugCommonDeInitDriver(void) } #endif /* defined(SUPPORT_RGX) && !defined(NO_HARDWARE) */ -#ifdef SUPPORT_RGX -#ifdef SUPPORT_FIRMWARE_GCOV - if (gpsFirmwareGcovDIEntry != NULL) - { - DIDestroyEntry(gpsFirmwareGcovDIEntry); - } -#endif /* SUPPORT_FIRMWARE_GCOV */ -#endif /* SUPPORT_RGX */ - #ifdef SUPPORT_VALIDATION if (gpsTestMemLeakDIEntry != NULL) { @@ -1359,11 +1486,36 @@ PVRSRV_ERROR DebugCommonInitDevice(PVRSRV_DEVICE_NODE *psDeviceNode) PVR_GOTO_IF_ERROR(eError, return_error_); } +#ifdef SUPPORT_FIRMWARE_GCOV + { + DI_ITERATOR_CB sIterator = { + .pfnStart = _FirmwareGcovDIStart, + .pfnStop = _FirmwareGcovDIStop, + .pfnNext = _FirmwareGcovDINext, + .pfnShow = _FirmwareGcovDIShow + }; + + eError = DICreateEntry("firmware_gcov", psDebugInfo->psGroup, &sIterator, + psDeviceNode, DI_ENTRY_TYPE_GENERIC, + &psDebugInfo->psFWGCOVEntry); + PVR_GOTO_IF_ERROR(eError, return_error_); + } +#endif /* SUPPORT_FIRMWARE_GCOV */ + + { + DI_ITERATOR_CB sIterator = {.pfnShow = _FirmwareMappingsDIShow}; + eError = DICreateEntry("firmware_mappings", psDebugInfo->psGroup, &sIterator, + psDeviceNode, DI_ENTRY_TYPE_GENERIC, + &psDebugInfo->psFWMappingsEntry); + PVR_GOTO_IF_ERROR(eError, return_error_); + } + #if defined(SUPPORT_VALIDATION) || defined(SUPPORT_RISCV_GDB) { DI_ITERATOR_CB sIterator = { .pfnRead = _RiscvDmiRead, - .pfnWrite = _RiscvDmiWrite + .pfnWrite = _RiscvDmiWrite, + .ui32WriteLenMax = ((RISCV_DMI_SIZE)+1U) }; eError = DICreateEntry("riscv_dmi", psDebugInfo->psGroup, &sIterator, psDeviceNode, DI_ENTRY_TYPE_RANDOM_ACCESS, &psDebugInfo->psRiscvDmiDIEntry); @@ -1377,7 +1529,9 @@ PVRSRV_ERROR DebugCommonInitDevice(PVRSRV_DEVICE_NODE *psDeviceNode) DI_ITERATOR_CB sIterator = { .pfnSeek = _RgxRegsSeek, .pfnRead = _RgxRegsRead, - .pfnWrite = _RgxRegsWrite + .pfnWrite = _RgxRegsWrite, + //Max size of input binary data is 4 bytes (UINT32) or 8 bytes (UINT64) + .ui32WriteLenMax = ((8U)+1U) }; eError = DICreateEntry("rgxregs", psDebugInfo->psGroup, &sIterator, psDeviceNode, DI_ENTRY_TYPE_RANDOM_ACCESS, &psDebugInfo->psRGXRegsEntry); @@ -1401,7 +1555,9 @@ PVRSRV_ERROR DebugCommonInitDevice(PVRSRV_DEVICE_NODE *psDeviceNode) { DI_ITERATOR_CB sIterator = { .pfnShow = _DebugPowerDataDIShow, - .pfnWrite = PowerDataSet + .pfnWrite = PowerDataSet, + //Expects '0' or '1' plus Null terminator + .ui32WriteLenMax = ((1U)+1U) }; eError = DICreateEntry("power_data", psDebugInfo->psGroup, &sIterator, psDeviceNode, DI_ENTRY_TYPE_GENERIC, &psDebugInfo->psPowerDataEntry); @@ -1453,6 +1609,20 @@ void DebugCommonDeInitDevice(PVRSRV_DEVICE_NODE *psDeviceNode) psDebugInfo->psFWTraceEntry = NULL; } +#ifdef SUPPORT_FIRMWARE_GCOV + if (psDebugInfo->psFWGCOVEntry != NULL) + { + DIDestroyEntry(psDebugInfo->psFWGCOVEntry); + psDebugInfo->psFWGCOVEntry = NULL; + } +#endif + + if (psDebugInfo->psFWMappingsEntry != NULL) + { + DIDestroyEntry(psDebugInfo->psFWMappingsEntry); + psDebugInfo->psFWMappingsEntry = NULL; + } + #if defined(SUPPORT_VALIDATION) || defined(SUPPORT_RISCV_GDB) if (psDebugInfo->psRiscvDmiDIEntry != NULL) { diff --git a/drivers/gpu/drm/img-rogue/device.h b/drivers/gpu/drm/img-rogue/device.h index 29ee8cb1c..f5948d773 100644 --- a/drivers/gpu/drm/img-rogue/device.h +++ b/drivers/gpu/drm/img-rogue/device.h @@ -124,33 +124,6 @@ typedef struct _DEVICE_MEMORY_INFO_ DEVMEM_HEAP_BLUEPRINT *psDeviceMemoryHeap; } DEVICE_MEMORY_INFO; - -typedef struct _PG_HANDLE_ -{ - union - { - void *pvHandle; - IMG_UINT64 ui64Handle; - }u; - /* The allocation order is log2 value of the number of pages to allocate. - * As such this is a correspondingly small value. E.g, for order 4 we - * are talking 2^4 * PAGE_SIZE contiguous allocation. - * DevPxAlloc API does not need to support orders higher than 4. - */ -#if defined(SUPPORT_GPUVIRT_VALIDATION) - IMG_BYTE uiOrder; /* Order of the corresponding allocation */ - IMG_BYTE uiOSid; /* OSid to use for allocation arena. - * Connection-specific. */ - IMG_BYTE uiPad1, - uiPad2; /* Spare */ -#else - IMG_BYTE uiOrder; /* Order of the corresponding allocation */ - IMG_BYTE uiPad1, - uiPad2, - uiPad3; /* Spare */ -#endif -} PG_HANDLE; - #define MMU_BAD_PHYS_ADDR (0xbadbad00badULL) #define DUMMY_PAGE ("DUMMY_PAGE") #define DEV_ZERO_PAGE ("DEV_ZERO_PAGE") @@ -208,36 +181,6 @@ typedef enum _PVRSRV_DEVICE_DEBUG_DUMP_STATUS_ PVRSRV_DEVICE_DEBUG_DUMP_CAPTURE } PVRSRV_DEVICE_DEBUG_DUMP_STATUS; -typedef struct _MMU_PX_SETUP_ -{ -#if defined(SUPPORT_GPUVIRT_VALIDATION) - PVRSRV_ERROR (*pfnDevPxAllocGPV)(struct _PVRSRV_DEVICE_NODE_ *psDevNode, size_t uiSize, - PG_HANDLE *psMemHandle, IMG_DEV_PHYADDR *psDevPAddr, - IMG_UINT32 ui32OSid, IMG_PID uiPid); -#endif - PVRSRV_ERROR (*pfnDevPxAlloc)(struct _PVRSRV_DEVICE_NODE_ *psDevNode, size_t uiSize, - PG_HANDLE *psMemHandle, IMG_DEV_PHYADDR *psDevPAddr, - IMG_PID uiPid); - - void (*pfnDevPxFree)(struct _PVRSRV_DEVICE_NODE_ *psDevNode, PG_HANDLE *psMemHandle); - - PVRSRV_ERROR (*pfnDevPxMap)(struct _PVRSRV_DEVICE_NODE_ *psDevNode, PG_HANDLE *pshMemHandle, - size_t uiSize, IMG_DEV_PHYADDR *psDevPAddr, - void **pvPtr); - - void (*pfnDevPxUnMap)(struct _PVRSRV_DEVICE_NODE_ *psDevNode, - PG_HANDLE *psMemHandle, void *pvPtr); - - PVRSRV_ERROR (*pfnDevPxClean)(struct _PVRSRV_DEVICE_NODE_ *psDevNode, - PG_HANDLE *pshMemHandle, - IMG_UINT32 uiOffset, - IMG_UINT32 uiLength); - - IMG_UINT32 uiMMUPxLog2AllocGran; - - RA_ARENA *psPxRA; -} MMU_PX_SETUP; - #ifndef DI_GROUP_DEFINED #define DI_GROUP_DEFINED typedef struct DI_GROUP DI_GROUP; @@ -253,6 +196,10 @@ typedef struct _PVRSRV_DEVICE_DEBUG_INFO_ DI_ENTRY *psDumpDebugEntry; #ifdef SUPPORT_RGX DI_ENTRY *psFWTraceEntry; +#ifdef SUPPORT_FIRMWARE_GCOV + DI_ENTRY *psFWGCOVEntry; +#endif + DI_ENTRY *psFWMappingsEntry; #if defined(SUPPORT_VALIDATION) || defined(SUPPORT_RISCV_GDB) DI_ENTRY *psRiscvDmiDIEntry; IMG_UINT64 ui64RiscvDmi; @@ -325,7 +272,7 @@ typedef struct _PVRSRV_DEVICE_NODE_ /* Device specific MMU firmware attributes, used only in some devices */ MMU_DEVICEATTRIBS *psFirmwareMMUDevAttrs; - MMU_PX_SETUP sDevMMUPxSetup; + PHYS_HEAP *psMMUPhysHeap; /* lock for power state transitions */ POS_LOCK hPowerLock; @@ -431,8 +378,6 @@ typedef struct _PVRSRV_DEVICE_NODE_ #if defined(SUPPORT_GPUVIRT_VALIDATION) RA_ARENA *psOSSharedArena; RA_ARENA *psOSidSubArena[GPUVIRT_VALIDATION_NUM_OS]; - /* Number of supported OSid for this device node given available memory */ - IMG_UINT32 ui32NumOSId; #endif /* FW_MAIN, FW_CONFIG and FW_GUEST heaps. Should be part of registered heaps? */ @@ -455,9 +400,11 @@ typedef struct _PVRSRV_DEVICE_NODE_ PHYS_HEAP *apsPhysHeap[PVRSRV_PHYS_HEAP_LAST]; IMG_UINT32 ui32UserAllocHeapCount; - /* RA reserved for storing the MMU mappings of firmware. - * The memory backing up this RA must persist between driver or OS reboots */ - RA_ARENA *psFwMMUReservedMemArena; +#if defined(SUPPORT_AUTOVZ) + /* Phys Heap reserved for storing the MMU mappings of firmware. + * The memory backing up this Phys Heap must persist between driver or OS reboots */ + PHYS_HEAP *psFwMMUReservedPhysHeap; +#endif /* Flag indicating if the firmware has been initialised during the * 1st boot of the Host driver according to the AutoVz life-cycle. */ @@ -507,6 +454,7 @@ typedef struct _PVRSRV_DEVICE_NODE_ IMG_HANDLE hCmdCompNotify; IMG_HANDLE hDbgReqNotify; IMG_HANDLE hAppHintDbgReqNotify; + IMG_HANDLE hPhysHeapDbgReqNotify; PVRSRV_DEF_PAGE sDummyPage; PVRSRV_DEF_PAGE sDevZeroPage; @@ -551,11 +499,13 @@ typedef struct _PVRSRV_DEVICE_NODE_ #endif #if defined(SUPPORT_VALIDATION) - POS_LOCK hValidationLock; + POS_LOCK hValidationLock; #endif + /* Members for linking which connections are open on this device */ POS_LOCK hConnectionsLock; /*!< Lock protecting sConnections */ DLLIST_NODE sConnections; /*!< The list of currently active connection objects for this device node */ + #if defined(PVRSRV_DEBUG_LISR_EXECUTION) LISR_EXECUTION_INFO sLISRExecutionInfo; /*!< Information about the last execution of the LISR */ IMG_UINT64 ui64nLISR; /*!< Number of LISR calls seen */ diff --git a/drivers/gpu/drm/img-rogue/devicemem.c b/drivers/gpu/drm/img-rogue/devicemem.c index 029f80f2b..1516b9416 100644 --- a/drivers/gpu/drm/img-rogue/devicemem.c +++ b/drivers/gpu/drm/img-rogue/devicemem.c @@ -81,10 +81,12 @@ CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. #include "pvr_ricommon.h" #include "pvrsrv_apphint.h" #include "oskm_apphint.h" +#include "srvcore.h" #if defined(__linux__) #include "linux/kernel.h" #endif #else +#include "srvcore_intern.h" #include "rgxdefs.h" #endif @@ -108,8 +110,7 @@ IMG_UINT64 _GetPremappedVA(PMR *psPMR, PVRSRV_DEVICE_NODE *psDevNode) IMG_DEV_PHYADDR sDevAddr; IMG_BOOL bValid; - PVRSRV_PHYS_HEAP eFirstHeap = (PVRSRV_VZ_MODE_IS(GUEST) ? PVRSRV_PHYS_HEAP_FW_CONFIG : PVRSRV_PHYS_HEAP_FW_MAIN); - PHYS_HEAP *psPhysHeap = psDevNode->apsPhysHeap[eFirstHeap]; + PHYS_HEAP *psPhysHeap = psDevNode->apsPhysHeap[PVRSRV_PHYS_HEAP_FW_MAIN]; IMG_DEV_PHYADDR sHeapAddr; eError = PhysHeapGetDevPAddr(psPhysHeap, &sHeapAddr); @@ -881,8 +882,10 @@ DevmemDestroyContext(DEVMEM_CONTEXT *psCtx) goto e1; } - eError = BridgeDevmemIntCtxDestroy(GetBridgeHandle(psCtx->hDevConnection), - psCtx->hDevMemServerContext); + eError = DestroyServerResource(psCtx->hDevConnection, + NULL, + BridgeDevmemIntCtxDestroy, + psCtx->hDevMemServerContext); if (bDoCheck) { PVR_LOG_GOTO_IF_ERROR(eError, "BridgeDevMemIntCtxDestroy", e1); @@ -1293,8 +1296,11 @@ DevmemDestroyHeap(DEVMEM_HEAP *psHeap) } } - eError = BridgeDevmemIntHeapDestroy(GetBridgeHandle(psHeap->psCtx->hDevConnection), - psHeap->hDevMemServerHeap); + eError = DestroyServerResource(psHeap->psCtx->hDevConnection, + NULL, + BridgeDevmemIntHeapDestroy, + psHeap->hDevMemServerHeap); + #if defined(PVRSRV_FORCE_UNLOAD_IF_BAD_STATE) if (bDoCheck) #endif @@ -1361,27 +1367,12 @@ DevmemSubAllocateAndMap(IMG_UINT8 uiPreAllocMultiplier, fail_map: DevmemFree(*ppsMemDescPtr); fail_alloc: - ppsMemDescPtr = NULL; + *ppsMemDescPtr = NULL; + PVR_ASSERT(eError != PVRSRV_OK); return eError; } -static INLINE void _MemSet(void *pvMem, - IMG_UINT8 uiPattern, - IMG_DEVMEM_SIZE_T uiSize, - PVRSRV_MEMALLOCFLAGS_T uiFlags) -{ - if (PVRSRV_CHECK_CPU_UNCACHED(uiFlags)) - { - OSDeviceMemSet(pvMem, uiPattern, uiSize); - } - else - { - /* it's safe to use OSCachedMemSet() for cached and wc memory */ - OSCachedMemSet(pvMem, uiPattern, uiSize); - } -} - IMG_INTERNAL PVRSRV_ERROR DevmemSubAllocate(IMG_UINT8 uiPreAllocMultiplier, DEVMEM_HEAP *psHeap, @@ -1524,6 +1515,10 @@ DevmemSubAllocate(IMG_UINT8 uiPreAllocMultiplier, psImport, uiSize); +#if defined(DEBUG) + DevmemMemDescSetPoF(psMemDesc, uiFlags); +#endif + bImportClean = ((uiProperties & DEVMEM_PROPERTIES_IMPORT_IS_CLEAN) != 0); /* Zero the memory */ @@ -1546,7 +1541,7 @@ DevmemSubAllocate(IMG_UINT8 uiPreAllocMultiplier, */ PVR_ASSERT(uiSize < IMG_UINT32_MAX); - _MemSet(pvAddr, 0, uiSize, uiFlags); + DevmemCPUMemSet(pvAddr, 0, uiSize, uiFlags); #if defined(PDUMP) DevmemPDumpLoadZeroMem(psMemDesc, 0, uiSize, PDUMP_FLAGS_CONTINUOUS); @@ -1565,7 +1560,7 @@ DevmemSubAllocate(IMG_UINT8 uiPreAllocMultiplier, eError = DevmemAcquireCpuVirtAddr(psMemDesc, &pvAddr); PVR_GOTO_IF_ERROR(eError, failMaintenance); - _MemSet(pvAddr, PVRSRV_POISON_ON_ALLOC_VALUE, uiSize, uiFlags); + DevmemCPUMemSet(pvAddr, PVRSRV_POISON_ON_ALLOC_VALUE, uiSize, uiFlags); bPoisonOnAlloc = IMG_TRUE; } @@ -1574,8 +1569,6 @@ DevmemSubAllocate(IMG_UINT8 uiPreAllocMultiplier, /* Flush or invalidate */ if (bCPUCached && !bImportClean && (bZero || bCPUCleanFlag || bPoisonOnAlloc)) { - /* BridgeCacheOpQueue _may_ be deferred so use BridgeCacheOpExec - to ensure this cache maintenance is actioned immediately */ eError = BridgeCacheOpExec (GetBridgeHandle(psMemDesc->psImport->hDevConnection), psMemDesc->psImport->hPMR, (IMG_UINT64)(uintptr_t) @@ -1695,6 +1688,10 @@ DevmemAllocateExportable(SHARED_DEV_CONNECTION hDevConnection, psImport, uiSize); +#if defined(DEBUG) + DevmemMemDescSetPoF(psMemDesc, uiFlags); +#endif + *ppsMemDescPtr = psMemDesc; /* copy the allocation descriptive name and size so it can be passed to DevicememHistory when @@ -1795,6 +1792,10 @@ DevmemAllocateSparse(SHARED_DEV_CONNECTION hDevConnection, psImport, uiSize); +#if defined(DEBUG) + DevmemMemDescSetPoF(psMemDesc, uiFlags); +#endif + /* copy the allocation descriptive name and size so it can be passed to DevicememHistory when * the allocation gets mapped/unmapped */ @@ -1858,7 +1859,10 @@ IMG_INTERNAL PVRSRV_ERROR DevmemUnmakeLocalImportHandle(SHARED_DEV_CONNECTION hDevConnection, IMG_HANDLE hLocalImportHandle) { - return BridgePMRUnmakeLocalImportHandle(GetBridgeHandle(hDevConnection), hLocalImportHandle); + return DestroyServerResource(hDevConnection, + NULL, + BridgePMRUnmakeLocalImportHandle, + hLocalImportHandle); } /***************************************************************************** @@ -1925,8 +1929,10 @@ _Mapping_Unexport(DEVMEM_IMPORT *psImport, PVR_ASSERT (psImport != NULL); - eError = BridgePMRUnexportPMR(GetBridgeHandle(psImport->hDevConnection), - hPMRExportHandle); + eError = DestroyServerResource(psImport->hDevConnection, + NULL, + BridgePMRUnexportPMR, + hPMRExportHandle); PVR_ASSERT(eError == PVRSRV_OK); } @@ -2553,45 +2559,12 @@ DevmemAcquireCpuVirtAddr(DEVMEM_MEMDESC *psMemDesc, void **ppvCpuVirtAddr) { PVRSRV_ERROR eError; - DEVMEM_PROPERTIES_T uiProperties; PVR_ASSERT(psMemDesc != NULL); PVR_ASSERT(ppvCpuVirtAddr != NULL); - uiProperties = GetImportProperties(psMemDesc->psImport); - - if (uiProperties & - (DEVMEM_PROPERTIES_UNPINNED | DEVMEM_PROPERTIES_SECURE)) - { -#if defined(SUPPORT_SECURITY_VALIDATION) - if (uiProperties & DEVMEM_PROPERTIES_SECURE) - { - PVR_DPF((PVR_DBG_WARNING, - "%s: Allocation is a secure buffer. " - "It should not be possible to map to CPU, but for security " - "validation this will be allowed for testing purposes, " - "as long as the buffer is pinned.", - __func__)); - } - - if (uiProperties & DEVMEM_PROPERTIES_UNPINNED) -#endif - { - PVR_DPF((PVR_DBG_ERROR, - "%s: Allocation is currently unpinned or a secure buffer. " - "Not possible to map to CPU!", - __func__)); - return PVRSRV_ERROR_INVALID_MAP_REQUEST; - } - } - - if (uiProperties & DEVMEM_PROPERTIES_NO_CPU_MAPPING) - { - PVR_DPF((PVR_DBG_ERROR, - "%s: CPU Mapping is not possible on this allocation!", - __func__)); - return PVRSRV_ERROR_INVALID_MAP_REQUEST; - } + eError = DevmemCPUMapCheckImportProperties(psMemDesc); + PVR_LOG_RETURN_IF_ERROR(eError, "DevmemCPUMapCheckImportProperties"); OSLockAcquire(psMemDesc->sCPUMemDesc.hLock); DEVMEM_REFCOUNT_PRINT("%s (%p) %d->%d", @@ -2758,7 +2731,7 @@ DevmemGetReservation(DEVMEM_MEMDESC *psMemDesc, * memdescs of buffers allocated in the FW memory context * that is created in the Server */ -PVRSRV_ERROR +void DevmemGetPMRData(DEVMEM_MEMDESC *psMemDesc, IMG_HANDLE *phPMR, IMG_DEVMEM_OFFSET_T *puiPMROffset) @@ -2771,8 +2744,6 @@ DevmemGetPMRData(DEVMEM_MEMDESC *psMemDesc, PVR_ASSERT(psImport); *phPMR = psImport->hPMR; - - return PVRSRV_OK; } #if defined(__KERNEL__) diff --git a/drivers/gpu/drm/img-rogue/devicemem.h b/drivers/gpu/drm/img-rogue/devicemem.h index 430169a1b..1466eb387 100644 --- a/drivers/gpu/drm/img-rogue/devicemem.h +++ b/drivers/gpu/drm/img-rogue/devicemem.h @@ -636,7 +636,7 @@ PVRSRV_ERROR DevmemGetReservation(DEVMEM_MEMDESC *psMemDesc, IMG_HANDLE *hReservation); -IMG_INTERNAL PVRSRV_ERROR +IMG_INTERNAL void DevmemGetPMRData(DEVMEM_MEMDESC *psMemDesc, IMG_HANDLE *hPMR, IMG_DEVMEM_OFFSET_T *puiPMROffset); diff --git a/drivers/gpu/drm/img-rogue/devicemem_server.c b/drivers/gpu/drm/img-rogue/devicemem_server.c index 65762fd3a..089fa9cd1 100644 --- a/drivers/gpu/drm/img-rogue/devicemem_server.c +++ b/drivers/gpu/drm/img-rogue/devicemem_server.c @@ -64,6 +64,8 @@ CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. #include "pvrsrv.h" /* for PVRSRVGetPVRSRVData() */ #define DEVMEMCTX_FLAGS_FAULT_ADDRESS_AVAILABLE (1 << 0) +#define DEVMEMHEAP_REFCOUNT_MIN 1 +#define DEVMEMHEAP_REFCOUNT_MAX IMG_INT32_MAX struct _DEVMEMINT_CTX_ { @@ -111,7 +113,7 @@ struct _DEVMEMINT_HEAP_ { struct _DEVMEMINT_CTX_ *psDevmemCtx; IMG_UINT32 uiLog2PageSize; - ATOMIC_T hRefCount; + ATOMIC_T uiRefCount; }; struct _DEVMEMINT_RESERVATION_ @@ -193,11 +195,21 @@ static INLINE void DevmemIntCtxRelease(DEVMEMINT_CTX *psDevmemCtx) /*************************************************************************/ /*! @Function DevmemIntHeapAcquire @Description Acquire a reference to the provided device memory heap. -@Return None +@Return IMG_TRUE if referenced and IMG_FALSE in case of error */ /**************************************************************************/ -static INLINE void DevmemIntHeapAcquire(DEVMEMINT_HEAP *psDevmemHeap) +static INLINE IMG_BOOL DevmemIntHeapAcquire(DEVMEMINT_HEAP *psDevmemHeap) { - OSAtomicIncrement(&psDevmemHeap->hRefCount); + IMG_BOOL bSuccess = OSAtomicAddUnless(&psDevmemHeap->uiRefCount, 1, + DEVMEMHEAP_REFCOUNT_MAX); + + if (!bSuccess) + { + PVR_DPF((PVR_DBG_ERROR, "%s(): Failed to acquire the device memory " + "heap, reference count has overflowed.", __func__)); + return IMG_FALSE; + } + + return IMG_TRUE; } /*************************************************************************/ /*! @@ -209,7 +221,14 @@ static INLINE void DevmemIntHeapAcquire(DEVMEMINT_HEAP *psDevmemHeap) */ /**************************************************************************/ static INLINE void DevmemIntHeapRelease(DEVMEMINT_HEAP *psDevmemHeap) { - OSAtomicDecrement(&psDevmemHeap->hRefCount); + IMG_BOOL bSuccess = OSAtomicSubtractUnless(&psDevmemHeap->uiRefCount, 1, + DEVMEMHEAP_REFCOUNT_MIN); + + if (!bSuccess) + { + PVR_DPF((PVR_DBG_ERROR, "%s(): Failed to acquire the device memory " + "heap, reference count has underflowed.", __func__)); + } } PVRSRV_ERROR @@ -495,7 +514,7 @@ DevmemIntHeapCreate(DEVMEMINT_CTX *psDevmemCtx, DevmemIntCtxAcquire(psDevmemHeap->psDevmemCtx); - OSAtomicWrite(&psDevmemHeap->hRefCount, 1); + OSAtomicWrite(&psDevmemHeap->uiRefCount, 1); psDevmemHeap->uiLog2PageSize = uiLog2DataPageSize; @@ -603,6 +622,9 @@ DevmemIntMapPages(DEVMEMINT_RESERVATION *psReservation, { PVRSRV_ERROR eError; + PVR_LOG_RETURN_IF_INVALID_PARAM((ui32PageCount < PMR_MAX_SUPPORTED_PAGE_COUNT), "ui32PageCount"); + PVR_LOG_RETURN_IF_INVALID_PARAM((ui32PhysicalPgOffset < PMR_MAX_SUPPORTED_PAGE_COUNT), "ui32PhysicalPgOffset"); + if (psReservation->psDevmemHeap->uiLog2PageSize > PMR_GetLog2Contiguity(psPMR)) { PVR_DPF((PVR_DBG_ERROR, @@ -632,6 +654,8 @@ DevmemIntUnmapPages(DEVMEMINT_RESERVATION *psReservation, IMG_DEV_VIRTADDR sDevVAddrBase, IMG_UINT32 ui32PageCount) { + PVR_LOG_RETURN_IF_INVALID_PARAM((ui32PageCount < PMR_MAX_SUPPORTED_PAGE_COUNT), "ui32PageCount"); + /* Unmap the pages and mark them invalid in the MMU PTE */ MMU_UnmapPages(psReservation->psDevmemHeap->psDevmemCtx->psMMUContext, 0, @@ -674,13 +698,21 @@ DevmemIntMapPMR(DEVMEMINT_HEAP *psDevmemHeap, __func__, uiLog2HeapContiguity, PMR_GetLog2Contiguity(psPMR) )); - PVR_GOTO_WITH_ERROR(eError, PVRSRV_ERROR_INVALID_PARAMS, e0); + PVR_GOTO_WITH_ERROR(eError, PVRSRV_ERROR_INVALID_PARAMS, ErrorReturnError); } psDevNode = psDevmemHeap->psDevmemCtx->psDevNode; + /* Don't bother with refcount on reservation, as a reservation + only ever holds one mapping, so we directly increment the + refcount on the heap instead */ + if (!DevmemIntHeapAcquire(psDevmemHeap)) + { + PVR_GOTO_WITH_ERROR(eError, PVRSRV_ERROR_REFCOUNT_OVERFLOW, ErrorReturnError); + } + /* allocate memory to record the mapping info */ psMapping = OSAllocMem(sizeof(*psMapping)); - PVR_LOG_GOTO_IF_NOMEM(psMapping, eError, e0); + PVR_LOG_GOTO_IF_NOMEM(psMapping, eError, ErrorUnreference); uiAllocationSize = psReservation->uiLength; @@ -688,7 +720,7 @@ DevmemIntMapPMR(DEVMEMINT_HEAP *psDevmemHeap, PVR_ASSERT((IMG_DEVMEM_SIZE_T) ui32NumDevPages << uiLog2HeapContiguity == uiAllocationSize); eError = PMRLockSysPhysAddresses(psPMR); - PVR_GOTO_IF_ERROR(eError, e2); + PVR_GOTO_IF_ERROR(eError, ErrorFreeMapping); sAllocationDevVAddr = psReservation->sBase; @@ -731,7 +763,7 @@ DevmemIntMapPMR(DEVMEMINT_HEAP *psDevmemHeap, uiInitValue, pszPageName, IMG_TRUE); - PVR_GOTO_IF_ERROR(eError, e3); + PVR_GOTO_IF_ERROR(eError, ErrorUnlockPhysAddr); } /* N.B. We pass mapping permission flags to MMU_MapPages and let @@ -744,7 +776,7 @@ DevmemIntMapPMR(DEVMEMINT_HEAP *psDevmemHeap, ui32NumDevPages, NULL, uiLog2HeapContiguity); - PVR_GOTO_IF_ERROR(eError, e4); + PVR_GOTO_IF_ERROR(eError, ErrorFreeDefBackingPage); } else { @@ -754,22 +786,18 @@ DevmemIntMapPMR(DEVMEMINT_HEAP *psDevmemHeap, (IMG_DEVMEM_SIZE_T) ui32NumDevPages << uiLog2HeapContiguity, uiMapFlags, uiLog2HeapContiguity); - PVR_GOTO_IF_ERROR(eError, e3); + PVR_GOTO_IF_ERROR(eError, ErrorUnlockPhysAddr); } psMapping->psReservation = psReservation; psMapping->uiNumPages = ui32NumDevPages; psMapping->psPMR = psPMR; - /* Don't bother with refcount on reservation, as a reservation - only ever holds one mapping, so we directly increment the - refcount on the heap instead */ - DevmemIntHeapAcquire(psMapping->psReservation->psDevmemHeap); - *ppsMappingPtr = psMapping; return PVRSRV_OK; -e4: + +ErrorFreeDefBackingPage: if (bNeedBacking) { /*if the mapping failed, the allocated dummy ref count need @@ -778,18 +806,24 @@ e4: psDefPage, pszPageName); } -e3: + +ErrorUnlockPhysAddr: { - PVRSRV_ERROR eError1=PVRSRV_OK; + PVRSRV_ERROR eError1 = PVRSRV_OK; eError1 = PMRUnlockSysPhysAddresses(psPMR); PVR_LOG_IF_ERROR(eError1, "PMRUnlockSysPhysAddresses"); *ppsMappingPtr = NULL; } -e2: + +ErrorFreeMapping: OSFreeMem(psMapping); -e0: +ErrorUnreference: + /* if fails there's not much to do (the function will print an error) */ + DevmemIntHeapRelease(psDevmemHeap); + +ErrorReturnError: PVR_ASSERT (eError != PVRSRV_OK); return eError; } @@ -851,14 +885,13 @@ DevmemIntUnmapPMR(DEVMEMINT_MAPPING *psMapping) psMapping->psReservation->psDevmemHeap->uiLog2PageSize); } - - eError = PMRUnlockSysPhysAddresses(psMapping->psPMR); PVR_ASSERT(eError == PVRSRV_OK); - /* Don't bother with refcount on reservation, as a reservation - only ever holds one mapping, so we directly decrement the - refcount on the heap instead */ + /* Don't bother with refcount on reservation, as a reservation only ever + * holds one mapping, so we directly decrement the refcount on the heap + * instead. + * Function will print an error if the heap could not be unreferenced. */ DevmemIntHeapRelease(psDevmemHeap); OSFreeMem(psMapping); @@ -876,9 +909,15 @@ DevmemIntReserveRange(DEVMEMINT_HEAP *psDevmemHeap, PVRSRV_ERROR eError; DEVMEMINT_RESERVATION *psReservation; + if (!DevmemIntHeapAcquire(psDevmemHeap)) + { + PVR_GOTO_WITH_ERROR(eError, PVRSRV_ERROR_REFCOUNT_OVERFLOW, + ErrorReturnError); + } + /* allocate memory to record the reservation info */ psReservation = OSAllocMem(sizeof(*psReservation)); - PVR_LOG_GOTO_IF_NOMEM(psReservation, eError, e0); + PVR_LOG_GOTO_IF_NOMEM(psReservation, eError, ErrorUnreference); psReservation->sBase = sAllocationDevVAddr; psReservation->uiLength = uiAllocationSize; @@ -890,14 +929,12 @@ DevmemIntReserveRange(DEVMEMINT_HEAP *psDevmemHeap, 0, /* alignment is n/a since we supply devvaddr */ &sAllocationDevVAddr, psDevmemHeap->uiLog2PageSize); - PVR_GOTO_IF_ERROR(eError, e1); + PVR_GOTO_IF_ERROR(eError, ErrorFreeReservation); /* since we supplied the virt addr, MMU_Alloc shouldn't have chosen a new one for us */ PVR_ASSERT(sAllocationDevVAddr.uiAddr == psReservation->sBase.uiAddr); - DevmemIntHeapAcquire(psDevmemHeap); - psReservation->psDevmemHeap = psDevmemHeap; *ppsReservationPtr = psReservation; @@ -907,10 +944,14 @@ DevmemIntReserveRange(DEVMEMINT_HEAP *psDevmemHeap, * error exit paths follow */ -e1: +ErrorFreeReservation: OSFreeMem(psReservation); -e0: +ErrorUnreference: + /* if fails there's not much to do (the function will print an error) */ + DevmemIntHeapRelease(psDevmemHeap); + +ErrorReturnError: PVR_ASSERT(eError != PVRSRV_OK); return eError; } @@ -927,22 +968,27 @@ DevmemIntUnreserveRange(DEVMEMINT_RESERVATION *psReservation) uiLength, uiLog2DataPageSize); + /* Don't bother with refcount on reservation, as a reservation only ever + * holds one mapping, so we directly decrement the refcount on the heap + * instead. + * Function will print an error if the heap could not be unreferenced. */ DevmemIntHeapRelease(psReservation->psDevmemHeap); + OSFreeMem(psReservation); - return PVRSRV_OK; + return PVRSRV_OK; } PVRSRV_ERROR DevmemIntHeapDestroy(DEVMEMINT_HEAP *psDevmemHeap) { - if (OSAtomicRead(&psDevmemHeap->hRefCount) != 1) + if (OSAtomicRead(&psDevmemHeap->uiRefCount) != DEVMEMHEAP_REFCOUNT_MIN) { PVR_DPF((PVR_DBG_ERROR, "BUG! %s called but has too many references (%d) " - "which probably means allocations have been made from the heap and not freed", - __func__, - OSAtomicRead(&psDevmemHeap->hRefCount))); + "which probably means reservations & mappings have been made from " + "the heap and not freed", __func__, + OSAtomicRead(&psDevmemHeap->uiRefCount))); /* * Try again later when you've freed all the memory @@ -958,7 +1004,7 @@ DevmemIntHeapDestroy(DEVMEMINT_HEAP *psDevmemHeap) return PVRSRV_ERROR_RETRY; } - PVR_ASSERT(OSAtomicRead(&psDevmemHeap->hRefCount) == 1); + PVR_ASSERT(OSAtomicRead(&psDevmemHeap->uiRefCount) == DEVMEMHEAP_REFCOUNT_MIN); DevmemIntCtxRelease(psDevmemHeap->psDevmemCtx); @@ -1660,54 +1706,6 @@ DevmemIntPDumpSaveToFileVirtual(DEVMEMINT_CTX *psDevmemCtx, return PVRSRV_OK; } - -PVRSRV_ERROR -DevmemIntPDumpBitmap(CONNECTION_DATA * psConnection, - PVRSRV_DEVICE_NODE *psDeviceNode, - IMG_CHAR *pszFileName, - IMG_UINT32 ui32FileOffset, - IMG_UINT32 ui32Width, - IMG_UINT32 ui32Height, - IMG_UINT32 ui32StrideInBytes, - IMG_DEV_VIRTADDR sDevBaseAddr, - DEVMEMINT_CTX *psDevMemContext, - IMG_UINT32 ui32Size, - PDUMP_PIXEL_FORMAT ePixelFormat, - IMG_UINT32 ui32AddrMode, - IMG_UINT32 ui32PDumpFlags) -{ - IMG_UINT32 ui32ContextID; - PVRSRV_ERROR eError; - - PVR_UNREFERENCED_PARAMETER(psConnection); - - eError = MMU_AcquirePDumpMMUContext(psDevMemContext->psMMUContext, &ui32ContextID, ui32PDumpFlags); - - if (eError != PVRSRV_OK) - { - PVR_LOG_ERROR(eError, "MMU_AcquirePDumpMMUContext"); - return PVRSRV_ERROR_FAILED_TO_ALLOC_MMUCONTEXT_ID; - } - - eError = PDumpBitmapKM(psDeviceNode, - pszFileName, - ui32FileOffset, - ui32Width, - ui32Height, - ui32StrideInBytes, - sDevBaseAddr, - ui32ContextID, - ui32Size, - ePixelFormat, - ui32AddrMode, - ui32PDumpFlags); - - /* Don't care about return value */ - MMU_ReleasePDumpMMUContext(psDevMemContext->psMMUContext, ui32PDumpFlags); - - return eError; -} - PVRSRV_ERROR DevmemIntPDumpImageDescriptor(CONNECTION_DATA * psConnection, PVRSRV_DEVICE_NODE *psDeviceNode, diff --git a/drivers/gpu/drm/img-rogue/devicemem_server.h b/drivers/gpu/drm/img-rogue/devicemem_server.h index d4c7f215f..30a2b2e52 100644 --- a/drivers/gpu/drm/img-rogue/devicemem_server.h +++ b/drivers/gpu/drm/img-rogue/devicemem_server.h @@ -478,21 +478,6 @@ DevmemIntPDumpSaveToFileVirtual(DEVMEMINT_CTX *psDevmemCtx, IMG_UINT32 DevmemIntMMUContextID(DEVMEMINT_CTX *psDevMemContext); -PVRSRV_ERROR -DevmemIntPDumpBitmap(CONNECTION_DATA * psConnection, - PVRSRV_DEVICE_NODE *psDeviceNode, - IMG_CHAR *pszFileName, - IMG_UINT32 ui32FileOffset, - IMG_UINT32 ui32Width, - IMG_UINT32 ui32Height, - IMG_UINT32 ui32StrideInBytes, - IMG_DEV_VIRTADDR sDevBaseAddr, - DEVMEMINT_CTX *psDevMemContext, - IMG_UINT32 ui32Size, - PDUMP_PIXEL_FORMAT ePixelFormat, - IMG_UINT32 ui32AddrMode, - IMG_UINT32 ui32PDumpFlags); - PVRSRV_ERROR DevmemIntPDumpImageDescriptor(CONNECTION_DATA * psConnection, PVRSRV_DEVICE_NODE *psDeviceNode, @@ -550,40 +535,6 @@ DevmemIntPDumpSaveToFileVirtual(DEVMEMINT_CTX *psDevmemCtx, return PVRSRV_OK; } -#ifdef INLINE_IS_PRAGMA -#pragma inline(DevmemIntPDumpBitmap) -#endif -static INLINE PVRSRV_ERROR -DevmemIntPDumpBitmap(CONNECTION_DATA * psConnection, - PVRSRV_DEVICE_NODE *psDeviceNode, - IMG_CHAR *pszFileName, - IMG_UINT32 ui32FileOffset, - IMG_UINT32 ui32Width, - IMG_UINT32 ui32Height, - IMG_UINT32 ui32StrideInBytes, - IMG_DEV_VIRTADDR sDevBaseAddr, - DEVMEMINT_CTX *psDevMemContext, - IMG_UINT32 ui32Size, - PDUMP_PIXEL_FORMAT ePixelFormat, - IMG_UINT32 ui32AddrMode, - IMG_UINT32 ui32PDumpFlags) -{ - PVR_UNREFERENCED_PARAMETER(psConnection); - PVR_UNREFERENCED_PARAMETER(psDeviceNode); - PVR_UNREFERENCED_PARAMETER(pszFileName); - PVR_UNREFERENCED_PARAMETER(ui32FileOffset); - PVR_UNREFERENCED_PARAMETER(ui32Width); - PVR_UNREFERENCED_PARAMETER(ui32Height); - PVR_UNREFERENCED_PARAMETER(ui32StrideInBytes); - PVR_UNREFERENCED_PARAMETER(sDevBaseAddr); - PVR_UNREFERENCED_PARAMETER(psDevMemContext); - PVR_UNREFERENCED_PARAMETER(ui32Size); - PVR_UNREFERENCED_PARAMETER(ePixelFormat); - PVR_UNREFERENCED_PARAMETER(ui32AddrMode); - PVR_UNREFERENCED_PARAMETER(ui32PDumpFlags); - return PVRSRV_OK; -} - #ifdef INLINE_IS_PRAGMA #pragma inline(DevmemIntPDumpImageDescriptor) #endif diff --git a/drivers/gpu/drm/img-rogue/devicemem_server_utils.h b/drivers/gpu/drm/img-rogue/devicemem_server_utils.h index 4b54753de..ad85c07cd 100644 --- a/drivers/gpu/drm/img-rogue/devicemem_server_utils.h +++ b/drivers/gpu/drm/img-rogue/devicemem_server_utils.h @@ -68,11 +68,7 @@ static INLINE PVRSRV_ERROR DevmemCPUCacheMode(PVRSRV_DEVICE_NODE *psDeviceNode, break; case PVRSRV_MEMALLOCFLAG_CPU_CACHE_INCOHERENT: -#if defined(SAFETY_CRITICAL_BUILD) - ui32Ret = PVRSRV_MEMALLOCFLAG_CPU_UNCACHED_WC; -#else ui32Ret = PVRSRV_MEMALLOCFLAG_CPU_CACHED; -#endif break; case PVRSRV_MEMALLOCFLAG_CPU_CACHE_COHERENT: @@ -90,11 +86,7 @@ static INLINE PVRSRV_ERROR DevmemCPUCacheMode(PVRSRV_DEVICE_NODE *psDeviceNode, } else { -#if defined(SAFETY_CRITICAL_BUILD) - ui32Ret = PVRSRV_MEMALLOCFLAG_CPU_UNCACHED_WC; -#else ui32Ret = PVRSRV_MEMALLOCFLAG_CPU_CACHED; -#endif } break; @@ -136,11 +128,7 @@ static INLINE PVRSRV_ERROR DevmemDeviceCacheMode(PVRSRV_DEVICE_NODE *psDeviceNod break; case PVRSRV_MEMALLOCFLAG_GPU_CACHE_INCOHERENT: -#if defined(SAFETY_CRITICAL_BUILD) - ui32Ret = PVRSRV_MEMALLOCFLAG_GPU_UNCACHED_WC; -#else ui32Ret = PVRSRV_MEMALLOCFLAG_GPU_CACHED; -#endif break; case PVRSRV_MEMALLOCFLAG_GPU_CACHE_COHERENT: @@ -158,11 +146,7 @@ static INLINE PVRSRV_ERROR DevmemDeviceCacheMode(PVRSRV_DEVICE_NODE *psDeviceNod } else { -#if defined(SAFETY_CRITICAL_BUILD) - ui32Ret = PVRSRV_MEMALLOCFLAG_GPU_UNCACHED_WC; -#else ui32Ret = PVRSRV_MEMALLOCFLAG_GPU_CACHED; -#endif } break; diff --git a/drivers/gpu/drm/img-rogue/devicemem_typedefs.h b/drivers/gpu/drm/img-rogue/devicemem_typedefs.h index 98ad36c91..dd66fccf3 100644 --- a/drivers/gpu/drm/img-rogue/devicemem_typedefs.h +++ b/drivers/gpu/drm/img-rogue/devicemem_typedefs.h @@ -137,6 +137,6 @@ typedef IMG_UINT32 SPARSE_MEM_RESIZE_FLAGS; /* Defines the max length for PMR, MemDesc, Device memory History and RI debug * annotations stored in memory, including the null terminator. */ -#define DEVMEM_ANNOTATION_MAX_LEN (PVR_ANNOTATION_MAX_LEN + 1U) +#define DEVMEM_ANNOTATION_MAX_LEN ((IMG_UINT32)PVR_ANNOTATION_MAX_LEN + 1U) #endif /* #ifndef DEVICEMEM_TYPEDEFS_H */ diff --git a/drivers/gpu/drm/img-rogue/devicemem_utils.c b/drivers/gpu/drm/img-rogue/devicemem_utils.c index 44c9822d2..d4416ae57 100644 --- a/drivers/gpu/drm/img-rogue/devicemem_utils.c +++ b/drivers/gpu/drm/img-rogue/devicemem_utils.c @@ -49,6 +49,7 @@ CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. #include "ra.h" #include "devicemem_utils.h" #include "client_mm_bridge.h" +#include "client_cache_bridge.h" #if defined(PVRSRV_ENABLE_GPU_MEMORY_INFO) #include "client_ri_bridge.h" #if defined(__KERNEL__) @@ -62,6 +63,12 @@ CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. #include "proc_stats.h" #endif +#if defined(__KERNEL__) +#include "srvcore.h" +#else +#include "srvcore_intern.h" +#endif + /* SVM heap management support functions for CPU (un)mapping */ @@ -371,8 +378,12 @@ IMG_BOOL DevmemImportStructRelease(DEVMEM_IMPORT *psImport) if (iRefCount == 0) { - BridgePMRUnrefPMR(GetBridgeHandle(psImport->hDevConnection), - psImport->hPMR); + PVRSRV_ERROR eError = DestroyServerResource(psImport->hDevConnection, + NULL, + BridgePMRUnrefPMR, + psImport->hPMR); + PVR_ASSERT(eError == PVRSRV_OK); + OSLockDestroy(psImport->sCPUImport.hLock); OSLockDestroy(psImport->sDeviceImport.hLock); OSLockDestroy(psImport->hLock); @@ -455,9 +466,24 @@ void DevmemMemDescInit(DEVMEM_MEMDESC *psMemDesc, psMemDesc->hPrivData = NULL; psMemDesc->ui32AllocationIndex = DEVICEMEM_HISTORY_ALLOC_INDEX_NONE; +#if defined(DEBUG) + psMemDesc->bPoisonOnFree = IMG_FALSE; +#endif + OSAtomicWrite(&psMemDesc->hRefCount, 1); } +#if defined(DEBUG) +IMG_INTERNAL +void DevmemMemDescSetPoF(DEVMEM_MEMDESC *psMemDesc, PVRSRV_MEMALLOCFLAGS_T uiFlags) +{ + if (PVRSRV_CHECK_POISON_ON_FREE(uiFlags)) + { + psMemDesc->bPoisonOnFree = IMG_TRUE; + } +} +#endif + IMG_INTERNAL void DevmemMemDescAcquire(DEVMEM_MEMDESC *psMemDesc) { @@ -473,6 +499,48 @@ void DevmemMemDescAcquire(DEVMEM_MEMDESC *psMemDesc) PVR_UNREFERENCED_PARAMETER(iRefCount); } +#if defined(DEBUG) +static void _DevmemPoisonOnFree(DEVMEM_MEMDESC *psMemDesc) +{ + void *pvAddr = NULL; + IMG_UINT8 *pui8CPUVAddr; + PVRSRV_ERROR eError; + + eError = DevmemCPUMapCheckImportProperties(psMemDesc); + PVR_LOG_RETURN_VOID_IF_ERROR(eError, "DevmemCPUMapCheckImportProperties"); + + OSLockAcquire(psMemDesc->sCPUMemDesc.hLock); + eError = DevmemImportStructCPUMap(psMemDesc->psImport); + OSLockRelease(psMemDesc->sCPUMemDesc.hLock); + PVR_LOG_RETURN_VOID_IF_ERROR(eError, "DevmemImportStructCPUMap"); + + pui8CPUVAddr = psMemDesc->psImport->sCPUImport.pvCPUVAddr; + pui8CPUVAddr += psMemDesc->uiOffset; + pvAddr = pui8CPUVAddr; + + DevmemCPUMemSet(pvAddr, + PVRSRV_POISON_ON_FREE_VALUE, + psMemDesc->uiAllocSize, + psMemDesc->psImport->uiFlags); + + if (PVRSRV_CHECK_CPU_CACHE_COHERENT(psMemDesc->psImport->uiFlags) || + PVRSRV_CHECK_CPU_CACHE_INCOHERENT(psMemDesc->psImport->uiFlags)) + { + eError = BridgeCacheOpExec(GetBridgeHandle(psMemDesc->psImport->hDevConnection), + psMemDesc->psImport->hPMR, + (IMG_UINT64) (uintptr_t) + pvAddr - psMemDesc->uiOffset, + psMemDesc->uiOffset, + psMemDesc->uiAllocSize, + PVRSRV_CACHE_OP_FLUSH); + PVR_LOG_IF_ERROR(eError, "BridgeCacheOpExec"); + } + + DevmemImportStructCPUUnmap(psMemDesc->psImport); + pvAddr = NULL; +} +#endif + IMG_INTERNAL IMG_BOOL DevmemMemDescRelease(DEVMEM_MEMDESC *psMemDesc) { @@ -496,8 +564,10 @@ IMG_BOOL DevmemMemDescRelease(DEVMEM_MEMDESC *psMemDesc) { PVRSRV_ERROR eError; - eError = BridgeRIDeleteMEMDESCEntry(GetBridgeHandle(psMemDesc->psImport->hDevConnection), - psMemDesc->hRIHandle); + eError = DestroyServerResource(psMemDesc->psImport->hDevConnection, + NULL, + BridgeRIDeleteMEMDESCEntry, + psMemDesc->hRIHandle); PVR_LOG_IF_ERROR(eError, "BridgeRIDeleteMEMDESCEntry"); } #endif @@ -508,7 +578,6 @@ IMG_BOOL DevmemMemDescRelease(DEVMEM_MEMDESC *psMemDesc) /* As soon as the first sub-allocation on the psImport is freed * we might get dirty memory when reusing it. * We have to delete the ZEROED, CLEAN & POISONED flag */ - psMemDesc->psImport->uiProperties &= ~(DEVMEM_PROPERTIES_IMPORT_IS_ZEROED | DEVMEM_PROPERTIES_IMPORT_IS_CLEAN | @@ -516,6 +585,13 @@ IMG_BOOL DevmemMemDescRelease(DEVMEM_MEMDESC *psMemDesc) OSLockRelease(psMemDesc->psImport->hLock); +#if defined(DEBUG) + if (psMemDesc->bPoisonOnFree) + { + _DevmemPoisonOnFree(psMemDesc); + } +#endif + RA_Free(psMemDesc->psImport->sDeviceImport.psHeap->psSubAllocRA, psMemDesc->psImport->sDeviceImport.sDevVAddr.uiAddr + psMemDesc->uiOffset); @@ -579,8 +655,13 @@ PVRSRV_ERROR DevmemValidateParams(IMG_DEVMEM_SIZE_T uiSize, return PVRSRV_ERROR_INVALID_PARAMS; } - /* If zero flag is set we have to have write access to the page. */ - if (PVRSRV_CHECK_ZERO_ON_ALLOC(*puiFlags) || PVRSRV_CHECK_CPU_WRITEABLE(*puiFlags)) + /* If zero or poison flags are set we have to have write access to the page. */ + if (PVRSRV_CHECK_ZERO_ON_ALLOC(*puiFlags) || + PVRSRV_CHECK_POISON_ON_ALLOC(*puiFlags) || +#if defined(DEBUG) + PVRSRV_CHECK_POISON_ON_FREE(*puiFlags) || +#endif + PVRSRV_CHECK_CPU_WRITEABLE(*puiFlags)) { (*puiFlags) |= PVRSRV_MEMALLOCFLAG_CPU_WRITEABLE | PVRSRV_MEMALLOCFLAG_CPU_READABLE; @@ -1035,13 +1116,17 @@ IMG_BOOL DevmemImportStructDevUnmap(DEVMEM_IMPORT *psImport) { if (psDeviceImport->bMapped) { - eError = BridgeDevmemIntUnmapPMR(GetBridgeHandle(psImport->hDevConnection), - psDeviceImport->hMapping); + eError = DestroyServerResource(psImport->hDevConnection, + NULL, + BridgeDevmemIntUnmapPMR, + psDeviceImport->hMapping); PVR_ASSERT(eError == PVRSRV_OK); } - eError = BridgeDevmemIntUnreserveRange(GetBridgeHandle(psImport->hDevConnection), - psDeviceImport->hReservation); + eError = DestroyServerResource(psImport->hDevConnection, + NULL, + BridgeDevmemIntUnreserveRange, + psDeviceImport->hReservation); PVR_ASSERT(eError == PVRSRV_OK); } diff --git a/drivers/gpu/drm/img-rogue/devicemem_utils.h b/drivers/gpu/drm/img-rogue/devicemem_utils.h index 621ca5115..3dcef24fa 100644 --- a/drivers/gpu/drm/img-rogue/devicemem_utils.h +++ b/drivers/gpu/drm/img-rogue/devicemem_utils.h @@ -54,6 +54,7 @@ CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. #include "osfunc.h" #include "lock.h" #include "osmmap.h" +#include "pvrsrv_memallocflags_internal.h" #define DEVMEM_HEAPNAME_MAXLENGTH 160 @@ -288,6 +289,10 @@ struct DEVMEM_MEMDESC_TAG IMG_UINT32 ui32AllocationIndex; +#if defined(DEBUG) + IMG_BOOL bPoisonOnFree; +#endif + #if defined(PVRSRV_ENABLE_GPU_MEMORY_INFO) IMG_HANDLE hRIHandle; /*!< Handle to RI information */ #endif @@ -444,7 +449,7 @@ IMG_BOOL DevmemImportStructRelease(DEVMEM_IMPORT *psImport); /****************************************************************************** @Function DevmemImportDiscard -@Description Discard a created, but unitilised import structure. +@Description Discard a created, but uninitialised import structure. This must only be called before DevmemImportStructInit after which DevmemImportStructRelease must be used to "free" the import structure. @@ -459,6 +464,16 @@ void DevmemImportDiscard(DEVMEM_IMPORT *psImport); ******************************************************************************/ PVRSRV_ERROR DevmemMemDescAlloc(DEVMEM_MEMDESC **ppsMemDesc); +#if defined(DEBUG) +/****************************************************************************** +@Function DevmemMemDescSetPoF +@Description Sets the Poison on Free flag to true for this MemDesc if the + given MemAllocFlags have the Poison on Free bit set. + Poison on Free is a debug only feature. +******************************************************************************/ +void DevmemMemDescSetPoF(DEVMEM_MEMDESC *psMemDesc, PVRSRV_MEMALLOCFLAGS_T uiFlags); +#endif + /****************************************************************************** @Function DevmemMemDescInit @Description Sets the given offset and import struct fields in the MemDesc. @@ -519,4 +534,72 @@ static INLINE DEVMEM_PROPERTIES_T GetImportProperties(DEVMEM_IMPORT *psImport) return uiProperties; } +/****************************************************************************** +@Function DevmemCPUMemSet +@Description Given a CPU Mapped Devmem address, set the memory at that + range (address, address + size) to the uiPattern provided. + Flags determine the OS abstracted MemSet method to use. +******************************************************************************/ +static INLINE void DevmemCPUMemSet(void *pvMem, + IMG_UINT8 uiPattern, + IMG_DEVMEM_SIZE_T uiSize, + PVRSRV_MEMALLOCFLAGS_T uiFlags) +{ + if (PVRSRV_CHECK_CPU_UNCACHED(uiFlags)) + { + OSDeviceMemSet(pvMem, uiPattern, uiSize); + } + else + { + /* it's safe to use OSCachedMemSet() for cached and wc memory */ + OSCachedMemSet(pvMem, uiPattern, uiSize); + } +} + +/****************************************************************************** +@Function DevmemCPUMapCheckImportProperties +@Description Given a MemDesc check that the import properties are correct + to allow for mapping the MemDesc to the CPU. + Returns PVRSRV_OK on success. +******************************************************************************/ +static INLINE PVRSRV_ERROR DevmemCPUMapCheckImportProperties(DEVMEM_MEMDESC *psMemDesc) +{ + DEVMEM_PROPERTIES_T uiProperties = GetImportProperties(psMemDesc->psImport); + + if (uiProperties & + (DEVMEM_PROPERTIES_UNPINNED | DEVMEM_PROPERTIES_SECURE)) + { +#if defined(SUPPORT_SECURITY_VALIDATION) + if (uiProperties & DEVMEM_PROPERTIES_SECURE) + { + PVR_DPF((PVR_DBG_WARNING, + "%s: Allocation is a secure buffer. " + "It should not be possible to map to CPU, but for security " + "validation this will be allowed for testing purposes, " + "as long as the buffer is pinned.", + __func__)); + } + + if (uiProperties & DEVMEM_PROPERTIES_UNPINNED) +#endif + { + PVR_DPF((PVR_DBG_ERROR, + "%s: Allocation is currently unpinned or a secure buffer. " + "Not possible to map to CPU!", + __func__)); + return PVRSRV_ERROR_INVALID_MAP_REQUEST; + } + } + + if (uiProperties & DEVMEM_PROPERTIES_NO_CPU_MAPPING) + { + PVR_DPF((PVR_DBG_ERROR, + "%s: CPU Mapping is not possible on this allocation!", + __func__)); + return PVRSRV_ERROR_INVALID_MAP_REQUEST; + } + + return PVRSRV_OK; +} + #endif /* DEVICEMEM_UTILS_H */ diff --git a/drivers/gpu/drm/img-rogue/di_common.h b/drivers/gpu/drm/img-rogue/di_common.h index c262495e8..a10178708 100644 --- a/drivers/gpu/drm/img-rogue/di_common.h +++ b/drivers/gpu/drm/img-rogue/di_common.h @@ -226,9 +226,11 @@ typedef struct DI_ITERATOR_CB DI_PFN_SEEK pfnSeek; /*!< Sets data pointer in an entry. */ DI_PFN_READ pfnRead; /*!< Reads data from an entry. */ - /* Optional writing to entry interface. */ + /* Optional writing to entry interface. Null terminated. */ DI_PFN_WRITE pfnWrite; /*!< Performs write operation on an entry. */ + IMG_UINT32 ui32WriteLenMax; /*!< Maximum char length of entry + accepted for write. Includes \0 */ } DI_ITERATOR_CB; #endif /* DI_COMMON_H */ diff --git a/drivers/gpu/drm/img-rogue/di_impl_brg.c b/drivers/gpu/drm/img-rogue/di_impl_brg.c index 7188c317a..5670af07f 100644 --- a/drivers/gpu/drm/img-rogue/di_impl_brg.c +++ b/drivers/gpu/drm/img-rogue/di_impl_brg.c @@ -193,6 +193,12 @@ static void _WriteWithRetires(void *pvNativeHandle, const IMG_CHAR *pszStr, PVR_LOG_IF_ERROR(eError, "TLStreamWrite"); } +static void _WriteData(void *pvNativeHandle, const void *pvData, + IMG_UINT32 uiSize) +{ + _WriteWithRetires(pvNativeHandle, pvData, uiSize); +} + __printf(2, 0) static void _VPrintf(void *pvNativeHandle, const IMG_CHAR *pszFmt, va_list pArgs) @@ -216,6 +222,7 @@ static IMG_BOOL _HasOverflowed(void *pvNativeHandle) } static OSDI_IMPL_ENTRY_CB _g_sEntryCallbacks = { + .pfnWrite = _WriteData, .pfnVPrintf = _VPrintf, .pfnPuts = _Puts, .pfnHasOverflowed = _HasOverflowed, diff --git a/drivers/gpu/drm/img-rogue/di_server.c b/drivers/gpu/drm/img-rogue/di_server.c index 1899b431c..391f3aa13 100644 --- a/drivers/gpu/drm/img-rogue/di_server.c +++ b/drivers/gpu/drm/img-rogue/di_server.c @@ -265,7 +265,7 @@ static PVRSRV_ERROR _CreateNativeEntry(DI_ENTRY *psEntry, psEntry->pvPrivData, psNativeParent->pvHandle, &psNativeEntry->pvHandle); - PVR_LOG_GOTO_IF_ERROR(eError, "psImpl->sCb.pfnCreateGroup", free_memory_); + PVR_LOG_GOTO_IF_ERROR(eError, "psImpl->sCb.pfnCreateEntry", free_memory_); psNativeEntry->psDiImpl = psImpl; @@ -526,6 +526,17 @@ void *DIGetPrivData(const OSDI_IMPL_ENTRY *psEntry) return psEntry->pvPrivData; } +void DIWrite(const OSDI_IMPL_ENTRY *psEntry, const void *pvData, + IMG_UINT32 uiSize) +{ + PVR_ASSERT(psEntry != NULL); + PVR_ASSERT(psEntry->psCb != NULL); + PVR_ASSERT(psEntry->psCb->pfnWrite != NULL); + PVR_ASSERT(psEntry->pvNative != NULL); + + psEntry->psCb->pfnWrite(psEntry->pvNative, pvData, uiSize); +} + void DIPrintf(const OSDI_IMPL_ENTRY *psEntry, const IMG_CHAR *pszFmt, ...) { va_list args; diff --git a/drivers/gpu/drm/img-rogue/di_server.h b/drivers/gpu/drm/img-rogue/di_server.h index 198efb4d8..a68894b1b 100644 --- a/drivers/gpu/drm/img-rogue/di_server.h +++ b/drivers/gpu/drm/img-rogue/di_server.h @@ -43,7 +43,17 @@ CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. #ifndef DI_SERVER_H #define DI_SERVER_H -#include +#if defined(__linux__) + #include + + #if (LINUX_VERSION_CODE >= KERNEL_VERSION(5, 15, 0)) + #include + #else + #include + #endif /* LINUX_VERSION_CODE >= KERNEL_VERSION(5, 15, 0) */ +#else + #include +#endif /* __linux__ */ #include "di_common.h" #include "pvrsrv_error.h" @@ -150,6 +160,19 @@ void DIDestroyGroup(DI_GROUP *psGroup); */ void *DIGetPrivData(const OSDI_IMPL_ENTRY *psEntry); +/*! @Function DIWrite + * + * @Description + * Writes the binary data of the DI entry to the output sync, whatever that may + * be for the DI implementation. + * + * @Input psEntry pointer to OSDI_IMPL_ENTRY object + * @Input pvData data + * @Input uiSize pvData length + */ +void DIWrite(const OSDI_IMPL_ENTRY *psEntry, const void *pvData, + IMG_UINT32 uiSize); + /*! @Function DIPrintf * * @Description diff --git a/drivers/gpu/drm/img-rogue/drm_nulldisp_drv.c b/drivers/gpu/drm/img-rogue/drm_nulldisp_drv.c index 8c722f62e..5c9b7094b 100644 --- a/drivers/gpu/drm/img-rogue/drm_nulldisp_drv.c +++ b/drivers/gpu/drm/img-rogue/drm_nulldisp_drv.c @@ -2064,7 +2064,9 @@ static int nulldisp_early_load(struct drm_device *dev) goto err_workqueue_cleanup; } +#if (LINUX_VERSION_CODE < KERNEL_VERSION(5, 15, 0)) dev->irq_enabled = true; +#endif nulldisp_dev->nlpvrdpy = nlpvrdpy_create(dev, nulldisp_nl_disconnect_cb, @@ -2087,7 +2089,9 @@ err_vblank_cleanup: #endif err_workqueue_cleanup: destroy_workqueue(nulldisp_dev->workqueue); +#if (LINUX_VERSION_CODE < KERNEL_VERSION(5, 15, 0)) dev->irq_enabled = false; +#endif err_gem_cleanup: #if defined(LMA) pdp_gem_cleanup(nulldisp_dev->pdp_gem_priv); @@ -2143,7 +2147,9 @@ static void nulldisp_late_unload(struct drm_device *dev) #endif destroy_workqueue(nulldisp_dev->workqueue); +#if (LINUX_VERSION_CODE < KERNEL_VERSION(5, 15, 0)) dev->irq_enabled = false; +#endif #if defined(LMA) pdp_gem_cleanup(nulldisp_dev->pdp_gem_priv); @@ -2248,24 +2254,6 @@ static const struct vm_operations_struct nulldisp_gem_vm_ops = { #endif }; -#if (LINUX_VERSION_CODE >= KERNEL_VERSION(5, 9, 0)) -const struct drm_gem_object_funcs nulldisp_gem_funcs = { -#if defined(LMA) - .free = pdp_gem_object_free, - .export = pdp_gem_prime_export, -#else - .export = drm_gem_prime_export, - .pin = nulldisp_gem_prime_pin, - .unpin = nulldisp_gem_prime_unpin, - .get_sg_table = nulldisp_gem_prime_get_sg_table, - .vmap = nulldisp_gem_prime_vmap, - .vunmap = nulldisp_gem_prime_vunmap, - .free = nulldisp_gem_object_free, -#endif /* defined(LMA) */ - .vm_ops = &nulldisp_gem_vm_ops, -}; -#endif /* LINUX_VERSION_CODE >= KERNEL_VERSION(5, 9, 0) */ - #if defined(LMA) static int pdp_gem_dumb_create(struct drm_file *file, struct drm_device *dev, @@ -2366,15 +2354,32 @@ static int nulldisp_gem_object_cpu_fini_ioctl(struct drm_device *dev, return pdp_gem_object_cpu_fini_ioctl(dev, &pdp_args, file); } -static void pdp_gem_object_free(struct drm_gem_object *obj) +static void nulldisp_pdp_gem_object_free(struct drm_gem_object *obj) { struct nulldisp_display_device *nulldisp_dev = obj->dev->dev_private; pdp_gem_object_free_priv(nulldisp_dev->pdp_gem_priv, obj); } - #endif +#if (LINUX_VERSION_CODE >= KERNEL_VERSION(5, 9, 0)) +const struct drm_gem_object_funcs nulldisp_gem_funcs = { +#if defined(LMA) + .free = nulldisp_pdp_gem_object_free, + .export = pdp_gem_prime_export, +#else + .export = drm_gem_prime_export, + .pin = nulldisp_gem_prime_pin, + .unpin = nulldisp_gem_prime_unpin, + .get_sg_table = nulldisp_gem_prime_get_sg_table, + .vmap = nulldisp_gem_prime_vmap, + .vunmap = nulldisp_gem_prime_vunmap, + .free = nulldisp_gem_object_free, +#endif /* defined(LMA) */ + .vm_ops = &nulldisp_gem_vm_ops, +}; +#endif /* LINUX_VERSION_CODE >= KERNEL_VERSION(5, 9, 0) */ + static const struct drm_ioctl_desc nulldisp_ioctls[] = { DRM_IOCTL_DEF_DRV(NULLDISP_GEM_CREATE, nulldisp_gem_object_create_ioctl, @@ -2462,7 +2467,7 @@ static struct drm_driver nulldisp_drm_driver = { #if defined(LMA) #if (LINUX_VERSION_CODE < KERNEL_VERSION(5, 9, 0)) - .gem_free_object = pdp_gem_object_free, + .gem_free_object = nulldisp_pdp_gem_object_free, .gem_prime_export = pdp_gem_prime_export, #endif /* LINUX_VERSION_CODE < KERNEL_VERSION(5, 9, 0) */ .gem_prime_import = pdp_gem_prime_import, diff --git a/drivers/gpu/drm/img-rogue/drm_nulldisp_gem.c b/drivers/gpu/drm/img-rogue/drm_nulldisp_gem.c index c47fb6519..b24ae6d54 100644 --- a/drivers/gpu/drm/img-rogue/drm_nulldisp_gem.c +++ b/drivers/gpu/drm/img-rogue/drm_nulldisp_gem.c @@ -463,7 +463,7 @@ int nulldisp_gem_object_cpu_prep_ioctl(struct drm_device *dev, void *data, if (wait) { long lerr; - lerr = dma_resv_wait_timeout_rcu(nulldisp_obj->resv, + lerr = dma_resv_wait_timeout(nulldisp_obj->resv, write, true, 30 * HZ); @@ -480,7 +480,7 @@ int nulldisp_gem_object_cpu_prep_ioctl(struct drm_device *dev, void *data, * Remap return value (false indicates busy state, * true success). */ - if (!dma_resv_test_signaled_rcu(nulldisp_obj->resv, + if (!dma_resv_test_signaled(nulldisp_obj->resv, write)) err = -EBUSY; else diff --git a/drivers/gpu/drm/img-rogue/handle.c b/drivers/gpu/drm/img-rogue/handle.c index baa11f6fc..c5dd5d77b 100644 --- a/drivers/gpu/drm/img-rogue/handle.c +++ b/drivers/gpu/drm/img-rogue/handle.c @@ -62,10 +62,12 @@ CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. #include "handle_impl.h" #include "allocmem.h" #include "pvr_debug.h" +#include "osfunc.h" +#include "lock.h" #include "connection_server.h" -#include "pvrsrv.h" -#define HANDLE_HASH_TAB_INIT_SIZE 32 +#define HANDLE_HASH_TAB_INIT_SIZE 32 +#define HANDLE_PROC_HANDLE_HASH_INIT_SIZE 10 #define TEST_FLAG(v, f) BITMASK_HAS(v, f) #define TEST_ALLOC_FLAG(psHandleData, f) BITMASK_HAS((psHandleData)->eFlag, f) @@ -107,10 +109,13 @@ typedef struct _HANDLE_DATA_ /* List entry for sibling subhandles */ HANDLE_LIST sSiblings; - /* Reference count. The pfnReleaseData callback gets called when the - * reference count hits zero - */ - IMG_UINT32 ui32RefCount; + /* Reference count of lookups made. It helps track which resources are in + * use in concurrent bridge calls. */ + IMG_INT32 iLookupCount; + /* State of a handle. If the handle was already destroyed this is false. + * If this is false and iLookupCount is 0 the pfnReleaseData callback is + * called on the handle. */ + IMG_BOOL bCanLookup; #if defined(PVRSRV_DEBUG_HANDLE_LOCK) /* Store the handle base used for this handle, so we @@ -179,6 +184,12 @@ static HANDLE_IMPL_FUNCTAB const *gpsHandleFuncs; static POS_LOCK gKernelHandleLock; static IMG_BOOL gbLockInitialised = IMG_FALSE; +/* Pointer to process handle base currently being freed */ +static PVRSRV_HANDLE_BASE *g_psProcessHandleBaseBeingFreed; +/* Lock for the process handle base table */ +static POS_LOCK g_hProcessHandleBaseLock; +/* Hash table with process handle bases */ +static HASH_TABLE *g_psProcessHandleBaseTable; void LockHandle(PVRSRV_HANDLE_BASE *psBase) { @@ -196,11 +207,11 @@ void UnlockHandle(PVRSRV_HANDLE_BASE *psBase) */ PVRSRV_HANDLE_BASE *gpsKernelHandleBase = NULL; -/* Increase the reference count on the given handle. +/* Increase the lookup reference count on the given handle. * The handle lock must already be acquired. * Returns: the reference count after the increment */ -static inline IMG_UINT32 _HandleRef(HANDLE_DATA *psHandleData) +static inline IMG_UINT32 HandleGet(HANDLE_DATA *psHandleData) { #if defined(PVRSRV_DEBUG_HANDLE_LOCK) if (!OSLockIsLocked(psHandleData->psBase->hLock)) @@ -209,15 +220,23 @@ static inline IMG_UINT32 _HandleRef(HANDLE_DATA *psHandleData) OSDumpStack(); } #endif - psHandleData->ui32RefCount++; - return psHandleData->ui32RefCount; + +#ifdef DEBUG_REFCNT + PVR_DPF((PVR_DBG_ERROR, "%s: bCanLookup = %u, iLookupCount %d -> %d", + __func__, psHandleData->bCanLookup, psHandleData->iLookupCount, + psHandleData->iLookupCount + 1)); +#endif /* DEBUG_REFCNT */ + + PVR_ASSERT(psHandleData->bCanLookup); + + return ++psHandleData->iLookupCount; } -/* Decrease the reference count on the given handle. +/* Decrease the lookup reference count on the given handle. * The handle lock must already be acquired. * Returns: the reference count after the decrement */ -static inline IMG_UINT32 _HandleUnref(HANDLE_DATA *psHandleData) +static inline IMG_UINT32 HandlePut(HANDLE_DATA *psHandleData) { #if defined(PVRSRV_DEBUG_HANDLE_LOCK) if (!OSLockIsLocked(psHandleData->psBase->hLock)) @@ -226,10 +245,22 @@ static inline IMG_UINT32 _HandleUnref(HANDLE_DATA *psHandleData) OSDumpStack(); } #endif - PVR_ASSERT(psHandleData->ui32RefCount > 0); - psHandleData->ui32RefCount--; - return psHandleData->ui32RefCount; +#ifdef DEBUG_REFCNT + PVR_DPF((PVR_DBG_ERROR, "%s: bCanLookup = %u, iLookupCount %d -> %d", + __func__, psHandleData->bCanLookup, psHandleData->iLookupCount, + psHandleData->iLookupCount - 1)); +#endif /* DEBUG_REFCNT */ + + /* psHandleData->bCanLookup can be false at this point */ + PVR_ASSERT(psHandleData->iLookupCount > 0); + + return --psHandleData->iLookupCount; +} + +static inline IMG_BOOL IsRetryError(PVRSRV_ERROR eError) +{ + return eError == PVRSRV_ERROR_RETRY || eError == PVRSRV_ERROR_KERNEL_CCB_FULL; } #if defined(PVRSRV_NEED_PVR_DPF) @@ -266,6 +297,21 @@ static const IMG_CHAR *HandleBaseTypeToString(PVRSRV_HANDLE_BASE_TYPE eType) } #endif +static PVRSRV_ERROR HandleUnrefAndMaybeMarkForFree(PVRSRV_HANDLE_BASE *psBase, + HANDLE_DATA *psHandleData, + IMG_HANDLE hHandle, + PVRSRV_HANDLE_TYPE eType); + +static PVRSRV_ERROR HandleFreePrivData(PVRSRV_HANDLE_BASE *psBase, + HANDLE_DATA *psHandleData, + IMG_HANDLE hHandle, + PVRSRV_HANDLE_TYPE eType); + +static PVRSRV_ERROR HandleFreeDestroy(PVRSRV_HANDLE_BASE *psBase, + HANDLE_DATA *psHandleData, + IMG_HANDLE hHandle, + PVRSRV_HANDLE_TYPE eType); + /*! ******************************************************************************* @Function GetHandleData @@ -817,107 +863,6 @@ void InitKey(HAND_KEY aKey, aKey[HAND_KEY_PARENT] = (uintptr_t)hParent; } -static PVRSRV_ERROR FreeHandleWrapper(PVRSRV_HANDLE_BASE *psBase, IMG_HANDLE hHandle); - -/*! -******************************************************************************* - @Function FreeHandle - @Description Free a handle data structure. - @Input psBase - Pointer to handle base structure - hHandle - Handle to be freed - eType - Type of the handle to be freed - ppvData - Location for data associated with the freed handle - @Output ppvData - Points to the data associated with the freed handle - @Return PVRSRV_OK or PVRSRV_ERROR -******************************************************************************/ -static PVRSRV_ERROR FreeHandle(PVRSRV_HANDLE_BASE *psBase, - IMG_HANDLE hHandle, - PVRSRV_HANDLE_TYPE eType, - void **ppvData) -{ - HANDLE_DATA *psHandleData = NULL; - HANDLE_DATA *psReleasedHandleData; - PVRSRV_ERROR eError; - - eError = GetHandleData(psBase, &psHandleData, hHandle, eType); - PVR_LOG_RETURN_IF_ERROR(eError, "GetHandleData"); - - if (_HandleUnref(psHandleData) > 0) - { - /* this handle still has references so do not destroy it - * or the underlying object yet - */ - return PVRSRV_OK; - } - - /* Call the release data callback for each reference on the handle */ - if (psHandleData->pfnReleaseData != NULL) - { - eError = psHandleData->pfnReleaseData(psHandleData->pvData); - if (eError == PVRSRV_ERROR_RETRY) - { - PVR_DPF((PVR_DBG_MESSAGE, - "%s: " - "Got retry while calling release data callback for %p (type = %d)", - __func__, - hHandle, - (IMG_UINT32)psHandleData->eType)); - - /* the caller should retry, so retain a reference on the handle */ - _HandleRef(psHandleData); - - return eError; - } - else if (eError != PVRSRV_OK) - { - return eError; - } - } - - if (!TEST_ALLOC_FLAG(psHandleData, PVRSRV_HANDLE_ALLOC_FLAG_MULTI)) - { - HAND_KEY aKey; - IMG_HANDLE hRemovedHandle; - - InitKey(aKey, psBase, psHandleData->pvData, psHandleData->eType, ParentIfPrivate(psHandleData)); - - hRemovedHandle = (IMG_HANDLE)HASH_Remove_Extended(psBase->psHashTab, aKey); - - PVR_ASSERT(hRemovedHandle != NULL); - PVR_ASSERT(hRemovedHandle == psHandleData->hHandle); - PVR_UNREFERENCED_PARAMETER(hRemovedHandle); - } - - eError = UnlinkFromParent(psBase, psHandleData); - PVR_LOG_RETURN_IF_ERROR(eError, "UnlinkFromParent"); - - /* Free children */ - eError = IterateOverChildren(psBase, psHandleData, FreeHandleWrapper); - PVR_LOG_RETURN_IF_ERROR(eError, "IterateOverChildren"); - - eError = gpsHandleFuncs->pfnReleaseHandle(psBase->psImplBase, - psHandleData->hHandle, - (void **)&psReleasedHandleData); - if (unlikely(eError == PVRSRV_OK)) - { - PVR_ASSERT(psReleasedHandleData == psHandleData); - } - - if (ppvData) - { - *ppvData = psHandleData->pvData; - } - - OSFreeMem(psHandleData); - - return eError; -} - -static PVRSRV_ERROR FreeHandleWrapper(PVRSRV_HANDLE_BASE *psBase, IMG_HANDLE hHandle) -{ - return FreeHandle(psBase, hHandle, PVRSRV_HANDLE_TYPE_NONE, NULL); -} - /*! ******************************************************************************* @Function FindHandle @@ -1013,7 +958,12 @@ static PVRSRV_ERROR AllocHandle(PVRSRV_HANDLE_BASE *psBase, psNewHandleData->eFlag = eFlag; psNewHandleData->pvData = pvData; psNewHandleData->pfnReleaseData = pfnReleaseData; - psNewHandleData->ui32RefCount = 1; + psNewHandleData->iLookupCount = 0; + psNewHandleData->bCanLookup = IMG_TRUE; + +#ifdef DEBUG_REFCNT + PVR_DPF((PVR_DBG_ERROR, "%s: bCanLookup = true", __func__)); +#endif /* DEBUG_REFCNT */ InitParentList(psNewHandleData); #if defined(DEBUG) @@ -1197,7 +1147,7 @@ PVRSRV_ERROR PVRSRVAllocSubHandleUnlocked(PVRSRV_HANDLE_BASE *psBase, return PVRSRV_OK; ExitFreeHandle: - (void) FreeHandle(psBase, hHandle, eType, NULL); + PVRSRVDestroyHandleUnlocked(psBase, hHandle, eType); Exit: return eError; } @@ -1337,14 +1287,16 @@ PVRSRV_ERROR PVRSRVLookupHandleUnlocked(PVRSRV_HANDLE_BASE *psBase, return eError; } - if (psHandleData->ui32RefCount == 0) + /* If bCanLookup is false it means that a destroy operation was already + * called on this handle; therefore it can no longer be looked up. */ + if (!psHandleData->bCanLookup) { - return PVRSRV_ERROR_HANDLE_INDEX_OUT_OF_RANGE; + return PVRSRV_ERROR_HANDLE_NOT_ALLOCATED; } if (bRef) { - _HandleRef(psHandleData); + HandleGet(psHandleData); } *ppvData = psHandleData->pvData; @@ -1424,17 +1376,13 @@ ExitUnlock: eType - handle type @Return Error code or PVRSRV_OK ******************************************************************************/ -PVRSRV_ERROR PVRSRVReleaseHandle(PVRSRV_HANDLE_BASE *psBase, - IMG_HANDLE hHandle, - PVRSRV_HANDLE_TYPE eType) +void PVRSRVReleaseHandle(PVRSRV_HANDLE_BASE *psBase, + IMG_HANDLE hHandle, + PVRSRV_HANDLE_TYPE eType) { - PVRSRV_ERROR eError; - LockHandle(psBase); - eError = PVRSRVReleaseHandleUnlocked(psBase, hHandle, eType); + PVRSRVReleaseHandleUnlocked(psBase, hHandle, eType); UnlockHandle(psBase); - - return eError; } @@ -1446,19 +1394,40 @@ PVRSRV_ERROR PVRSRVReleaseHandle(PVRSRV_HANDLE_BASE *psBase, hold the lock when called. @Input hHandle - handle from client eType - handle type - @Return Error code or PVRSRV_OK ******************************************************************************/ -PVRSRV_ERROR PVRSRVReleaseHandleUnlocked(PVRSRV_HANDLE_BASE *psBase, - IMG_HANDLE hHandle, - PVRSRV_HANDLE_TYPE eType) +void PVRSRVReleaseHandleUnlocked(PVRSRV_HANDLE_BASE *psBase, + IMG_HANDLE hHandle, + PVRSRV_HANDLE_TYPE eType) { + HANDLE_DATA *psHandleData = NULL; + PVRSRV_ERROR eError; + /* PVRSRV_HANDLE_TYPE_NONE is reserved for internal use */ + PVR_ASSERT(psBase != NULL); PVR_ASSERT(eType != PVRSRV_HANDLE_TYPE_NONE); PVR_ASSERT(gpsHandleFuncs); - PVR_LOG_RETURN_IF_INVALID_PARAM(psBase != NULL, "psBase"); + PVR_LOG_RETURN_VOID_IF_FALSE(psBase != NULL, "invalid psBase"); - return FreeHandle(psBase, hHandle, eType, NULL); + eError = GetHandleData(psBase, &psHandleData, hHandle, eType); + if (unlikely(eError != PVRSRV_OK)) + { + PVR_DPF((PVR_DBG_ERROR, "%s: Error (%s) looking up handle %p of type %s " + "for base %p of type %s.", __func__, PVRSRVGetErrorString(eError), + (void*) hHandle, HandleTypeToString(eType), psBase, + HandleBaseTypeToString(psBase->eType))); + + PVR_ASSERT(eError == PVRSRV_OK); + + return; + } + + PVR_ASSERT(psHandleData->bCanLookup); + PVR_ASSERT(psHandleData->iLookupCount > 0); + + /* If there are still outstanding lookups for this handle or the handle + * has not been destroyed yet, return early */ + HandlePut(psHandleData); } /*! @@ -1483,88 +1452,94 @@ PVRSRV_ERROR PVRSRVPurgeHandles(PVRSRV_HANDLE_BASE *psBase) return eError; } -static PVRSRV_ERROR HandleUnrefAndMaybeMarkForFree(PVRSRV_HANDLE_BASE *psBase, - IMG_HANDLE hHandle, - PVRSRV_HANDLE_TYPE eType); - static PVRSRV_ERROR HandleUnrefAndMaybeMarkForFreeWrapper(PVRSRV_HANDLE_BASE *psBase, IMG_HANDLE hHandle) { - return HandleUnrefAndMaybeMarkForFree(psBase, hHandle, PVRSRV_HANDLE_TYPE_NONE); + HANDLE_DATA *psHandleData; + PVRSRV_ERROR eError = GetHandleData(psBase, &psHandleData, hHandle, + PVRSRV_HANDLE_TYPE_NONE); + PVR_RETURN_IF_ERROR(eError); + + return HandleUnrefAndMaybeMarkForFree(psBase, psHandleData, hHandle, PVRSRV_HANDLE_TYPE_NONE); } static PVRSRV_ERROR HandleUnrefAndMaybeMarkForFree(PVRSRV_HANDLE_BASE *psBase, + HANDLE_DATA *psHandleData, IMG_HANDLE hHandle, PVRSRV_HANDLE_TYPE eType) { - HANDLE_DATA *psHandleData = NULL; PVRSRV_ERROR eError; - eError = GetHandleData(psBase, &psHandleData, hHandle, eType); - PVR_RETURN_IF_ERROR(eError); - - if (psHandleData->ui32RefCount == 0) + /* If bCanLookup is false it means that the destructor was called more than + * once on this handle. */ + if (!psHandleData->bCanLookup) { - /* the handle is already in the destruction phase - * i.e. its refcount has already reached 0 - */ - return PVRSRV_OK; + PVR_DPF((PVR_DBG_ERROR, "%s: Handle %p of type %s already freed.", + __func__, psHandleData->hHandle, + HandleTypeToString(psHandleData->eType))); + return PVRSRV_ERROR_HANDLE_NOT_FOUND; } - if (_HandleUnref(psHandleData) > 0) + if (psHandleData->iLookupCount > 0) { - /* this handle still has references so do not destroy it - * or the underlying object yet - */ return PVRSRV_ERROR_OBJECT_STILL_REFERENCED; } + /* Mark this handle as freed only if it's no longer referenced by any + * lookup. The user space should retry freeing this handle once there are + * no outstanding lookups. */ + psHandleData->bCanLookup = IMG_FALSE; + +#ifdef DEBUG_REFCNT + PVR_DPF((PVR_DBG_ERROR, "%s: bCanLookup = false, iLookupCount = %d", __func__, + psHandleData->iLookupCount)); +#endif /* DEBUG_REFCNT */ + /* Prepare children for destruction */ eError = IterateOverChildren(psBase, psHandleData, HandleUnrefAndMaybeMarkForFreeWrapper); - PVR_LOG_RETURN_IF_ERROR(eError, "IterateOverChildren->HandleUnrefAndMaybeMarkForFree"); + PVR_LOG_RETURN_IF_ERROR(eError, "HandleUnrefAndMaybeMarkForFreeWrapper"); return PVRSRV_OK; } -static PVRSRV_ERROR HandleFreePrivData(PVRSRV_HANDLE_BASE *psBase, - IMG_HANDLE hHandle, - PVRSRV_HANDLE_TYPE eType); - static PVRSRV_ERROR HandleFreePrivDataWrapper(PVRSRV_HANDLE_BASE *psBase, IMG_HANDLE hHandle) { - return HandleFreePrivData(psBase, hHandle, PVRSRV_HANDLE_TYPE_NONE); + HANDLE_DATA *psHandleData; + PVRSRV_ERROR eError = GetHandleData(psBase, &psHandleData, hHandle, + PVRSRV_HANDLE_TYPE_NONE); + PVR_RETURN_IF_ERROR(eError); + + return HandleFreePrivData(psBase, psHandleData, hHandle, PVRSRV_HANDLE_TYPE_NONE); } static PVRSRV_ERROR HandleFreePrivData(PVRSRV_HANDLE_BASE *psBase, + HANDLE_DATA *psHandleData, IMG_HANDLE hHandle, PVRSRV_HANDLE_TYPE eType) { - HANDLE_DATA *psHandleData = NULL; PVRSRV_ERROR eError; - eError = GetHandleData(psBase, &psHandleData, hHandle, eType); - PVR_RETURN_IF_ERROR(eError); - /* Call the release data callback for each reference on the handle */ if (psHandleData->pfnReleaseData != NULL) { eError = psHandleData->pfnReleaseData(psHandleData->pvData); - if (eError == PVRSRV_ERROR_RETRY) + if (eError != PVRSRV_OK) { - PVR_DPF((PVR_DBG_MESSAGE, - "FreeHandle: " - "Got retry while calling release data callback for %p (type = %d)", - hHandle, - (IMG_UINT32)psHandleData->eType)); + if (IsRetryError(eError)) + { + PVR_DPF((PVR_DBG_MESSAGE, "%s: Got retry while calling release " + "data callback for handle %p of type = %s", __func__, + hHandle, HandleTypeToString(psHandleData->eType))); + } + else + { + PVR_LOG_ERROR(eError, "pfnReleaseData"); + } return eError; } - else if (eError != PVRSRV_OK) - { - return eError; - } /* we don't need this so make sure it's not called on * the pvData for the second time @@ -1580,27 +1555,25 @@ static PVRSRV_ERROR HandleFreePrivData(PVRSRV_HANDLE_BASE *psBase, return PVRSRV_OK; } -static PVRSRV_ERROR HandleFreeDestroy(PVRSRV_HANDLE_BASE *psBase, - IMG_HANDLE hHandle, - PVRSRV_HANDLE_TYPE eType); - static PVRSRV_ERROR HandleFreeDestroyWrapper(PVRSRV_HANDLE_BASE *psBase, - IMG_HANDLE hHandle) + IMG_HANDLE hHandle) { - return HandleFreeDestroy(psBase, hHandle, PVRSRV_HANDLE_TYPE_NONE); + HANDLE_DATA *psHandleData; + PVRSRV_ERROR eError = GetHandleData(psBase, &psHandleData, hHandle, + PVRSRV_HANDLE_TYPE_NONE); + PVR_RETURN_IF_ERROR(eError); + + return HandleFreeDestroy(psBase, psHandleData, hHandle, PVRSRV_HANDLE_TYPE_NONE); } static PVRSRV_ERROR HandleFreeDestroy(PVRSRV_HANDLE_BASE *psBase, + HANDLE_DATA *psHandleData, IMG_HANDLE hHandle, PVRSRV_HANDLE_TYPE eType) { - HANDLE_DATA *psHandleData = NULL; HANDLE_DATA *psReleasedHandleData; PVRSRV_ERROR eError; - eError = GetHandleData(psBase, &psHandleData, hHandle, eType); - PVR_RETURN_IF_ERROR(eError); - eError = UnlinkFromParent(psBase, psHandleData); PVR_LOG_RETURN_IF_ERROR(eError, "UnlinkFromParent"); @@ -1633,40 +1606,122 @@ static PVRSRV_ERROR HandleFreeDestroy(PVRSRV_HANDLE_BASE *psBase, return PVRSRV_OK; } -PVRSRV_ERROR PVRSRVReleaseHandleStagedUnlock(PVRSRV_HANDLE_BASE *psBase, - IMG_HANDLE hHandle, - PVRSRV_HANDLE_TYPE eType) +static PVRSRV_ERROR DestroyHandle(PVRSRV_HANDLE_BASE *psBase, + IMG_HANDLE hHandle, + PVRSRV_HANDLE_TYPE eType, + IMG_BOOL bReleaseLock) { PVRSRV_ERROR eError; + HANDLE_DATA *psHandleData = NULL; PVR_ASSERT(eType != PVRSRV_HANDLE_TYPE_NONE); PVR_ASSERT(gpsHandleFuncs); - PVR_LOG_RETURN_IF_FALSE(psBase != NULL, "psBase invalid", - PVRSRV_ERROR_INVALID_PARAMS); + PVR_LOG_RETURN_IF_INVALID_PARAM(psBase != NULL, "psBase"); - eError = HandleUnrefAndMaybeMarkForFree(psBase, hHandle, eType); - if (eError == PVRSRV_ERROR_OBJECT_STILL_REFERENCED) + eError = GetHandleData(psBase, &psHandleData, hHandle, eType); + PVR_RETURN_IF_ERROR(eError); + + eError = HandleUnrefAndMaybeMarkForFree(psBase, psHandleData, hHandle, eType); + PVR_RETURN_IF_ERROR(eError); + + if (bReleaseLock) { - return PVRSRV_OK; - } - else if (eError != PVRSRV_OK) - { - return eError; + UnlockHandle(psBase); } - UnlockHandle(psBase); - - eError = HandleFreePrivData(psBase, hHandle, eType); + eError = HandleFreePrivData(psBase, psHandleData, hHandle, eType); if (eError != PVRSRV_OK) { - LockHandle(psBase); + if (bReleaseLock) + { + LockHandle(psBase); + } + + /* If the data could not be freed due to a temporary condition the + * handle must be kept alive so that the next destroy call can try again */ + if (IsRetryError(eError)) + { + psHandleData->bCanLookup = IMG_TRUE; + } + return eError; } - LockHandle(psBase); + if (bReleaseLock) + { + LockHandle(psBase); + } - return HandleFreeDestroy(psBase, hHandle, eType); + return HandleFreeDestroy(psBase, psHandleData, hHandle, eType); +} + +/*! +******************************************************************************* + @Function PVRSRVDestroyHandle + @Description Destroys a handle that is no longer needed. Will + acquiring the handle lock for duration of the call. + Can return RETRY or KERNEL_CCB_FULL if resource could not be + destroyed, caller should retry sometime later. + @Input psBase - pointer to handle base structure + hHandle - handle from client + eType - handle type + @Return Error code or PVRSRV_OK +******************************************************************************/ +PVRSRV_ERROR PVRSRVDestroyHandle(PVRSRV_HANDLE_BASE *psBase, + IMG_HANDLE hHandle, + PVRSRV_HANDLE_TYPE eType) +{ + PVRSRV_ERROR eError; + + LockHandle(psBase); + eError = DestroyHandle(psBase, hHandle, eType, IMG_FALSE); + UnlockHandle(psBase); + + return eError; +} + +/*! +******************************************************************************* + @Function PVRSRVDestroyHandleUnlocked + @Description Destroys a handle that is no longer needed without + acquiring/releasing the handle lock. The function assumes you + hold the lock when called. + Can return RETRY or KERNEL_CCB_FULL if resource could not be + destroyed, caller should retry sometime later. + @Input psBase - pointer to handle base structure + hHandle - handle from client + eType - handle type + @Return Error code or PVRSRV_OK +******************************************************************************/ +PVRSRV_ERROR PVRSRVDestroyHandleUnlocked(PVRSRV_HANDLE_BASE *psBase, + IMG_HANDLE hHandle, + PVRSRV_HANDLE_TYPE eType) +{ + return DestroyHandle(psBase, hHandle, eType, IMG_FALSE); +} + +/*! +******************************************************************************* + @Function PVRSRVDestroyHandleStagedUnlocked + @Description Destroys a handle that is no longer needed without + acquiring/releasing the handle lock. The function assumes you + hold the lock when called. This function, unlike + PVRSRVDestroyHandleUnlocked(), releases the handle lock while + destroying handle private data. This is done to open the + bridge for other bridge calls. + Can return RETRY or KERNEL_CCB_FULL if resource could not be + destroyed, caller should retry sometime later. + @Input psBase - pointer to handle base structure + hHandle - handle from client + eType - handle type + @Return Error code or PVRSRV_OK +******************************************************************************/ +PVRSRV_ERROR PVRSRVDestroyHandleStagedUnlocked(PVRSRV_HANDLE_BASE *psBase, + IMG_HANDLE hHandle, + PVRSRV_HANDLE_TYPE eType) +{ + return DestroyHandle(psBase, hHandle, eType, IMG_TRUE); } /*! @@ -1778,12 +1833,11 @@ static PVRSRV_ERROR ListHandlesInBase(IMG_HANDLE hHandle, void *pvData) if (psHandleData != NULL) { - PVR_DPF((PVR_DBG_WARNING, " Handle: %6u, Refs: %3u, Type: %s (%u), pvData<%p>", - (IMG_UINT32) (uintptr_t) psHandleData->hHandle, - psHandleData->ui32RefCount, - HandleTypeToString(psHandleData->eType), - psHandleData->eType, - psHandleData->pvData)); + PVR_DPF((PVR_DBG_WARNING, + " Handle: %6u, CanLookup: %u, LookupCount: %3u, Type: %s (%u), pvData<%p>", + (IMG_UINT32) (uintptr_t) psHandleData->hHandle, psHandleData->bCanLookup, + psHandleData->iLookupCount, HandleTypeToString(psHandleData->eType), + psHandleData->eType, psHandleData->pvData)); } return PVRSRV_OK; @@ -1794,7 +1848,7 @@ static PVRSRV_ERROR ListHandlesInBase(IMG_HANDLE hHandle, void *pvData) static INLINE IMG_BOOL _CheckIfMaxTimeExpired(IMG_UINT64 ui64TimeStart, IMG_UINT64 ui64MaxBridgeTime) { /* unsigned arithmetic is well defined so this will wrap around correctly */ - return (OSClockns64() - ui64TimeStart) >= ui64MaxBridgeTime; + return (IMG_BOOL)((OSClockns64() - ui64TimeStart) >= ui64MaxBridgeTime); } static PVRSRV_ERROR FreeKernelHandlesWrapperIterKernel(IMG_HANDLE hHandle, void *pvData) @@ -1888,21 +1942,18 @@ static PVRSRV_ERROR FreeHandleDataWrapper(IMG_HANDLE hHandle, void *pvData) return PVRSRV_OK; } - PVR_ASSERT(psHandleData->ui32RefCount > 0); + PVR_ASSERT(psHandleData->bCanLookup && psHandleData->iLookupCount == 0); - while (psHandleData->ui32RefCount != 0) + if (psHandleData->bCanLookup) { if (psHandleData->pfnReleaseData != NULL) { eError = psHandleData->pfnReleaseData(psHandleData->pvData); if (eError == PVRSRV_ERROR_RETRY) { - PVR_DPF((PVR_DBG_MESSAGE, - "%s: " - "Got retry while calling release data callback for %p (type = %d)", - __func__, - hHandle, - (IMG_UINT32)psHandleData->eType)); + PVR_DPF((PVR_DBG_MESSAGE, "%s: Got retry while calling release " + "data callback for handle %p of type = %s", __func__, + hHandle, HandleTypeToString(psHandleData->eType))); return eError; } @@ -1912,7 +1963,7 @@ static PVRSRV_ERROR FreeHandleDataWrapper(IMG_HANDLE hHandle, void *pvData) } } - _HandleUnref(psHandleData); + psHandleData->bCanLookup = IMG_FALSE; } if (!TEST_ALLOC_FLAG(psHandleData, PVRSRV_HANDLE_ALLOC_FLAG_MULTI)) @@ -1946,10 +1997,10 @@ static PVRSRV_ERROR FreeHandleDataWrapper(IMG_HANDLE hHandle, void *pvData) "%s: Lock timeout (timeout: %" IMG_UINT64_FMTSPEC")", __func__, psData->ui64MaxBridgeTime)); - /* UnlockHandle(psData->psBase); - func only run in single thread ctx */ + UnlockHandle(psData->psBase); /* Invoke the scheduler to check if other processes are waiting for the lock */ OSReleaseThreadQuanta(); - /* LockHandle(psData->psBase); - func only run in single thread ctx */ + LockHandle(psData->psBase); /* Set again lock timeout and reset the counter */ psData->ui64TimeStart = OSClockns64(); PVR_DPF((PVR_DBG_MESSAGE, "%s: Lock acquired again", __func__)); @@ -1998,6 +2049,9 @@ static const PVRSRV_HANDLE_TYPE g_aeOrderedFreeList[] = PVRSRV_HANDLE_TYPE_RGX_SERVER_COMPUTE_CONTEXT, PVRSRV_HANDLE_TYPE_RGX_SERVER_RAY_CONTEXT, PVRSRV_HANDLE_TYPE_RGX_SERVER_KICKSYNC_CONTEXT, +#if defined(PVR_TESTING_UTILS) && defined(SUPPORT_VALIDATION) + PVRSRV_HANDLE_TYPE_RGX_SERVER_GPUMAP_CONTEXT, +#endif PVRSRV_HANDLE_TYPE_RI_HANDLE, PVRSRV_HANDLE_TYPE_SYNC_RECORD_HANDLE, PVRSRV_HANDLE_TYPE_SYNC_PRIMITIVE_BLOCK, @@ -2069,19 +2123,21 @@ PVRSRV_HANDLE_BASE *PVRSRVRetrieveProcessHandleBase(void) { PVRSRV_HANDLE_BASE *psHandleBase = NULL; PROCESS_HANDLE_BASE *psProcHandleBase = NULL; - PVRSRV_DATA *psPvrData = PVRSRVGetPVRSRVData(); IMG_PID ui32PurgePid = PVRSRVGetPurgeConnectionPid(); + IMG_PID uiCleanupPid = PVRSRVCleanupThreadGetPid(); + uintptr_t uiCleanupTid = PVRSRVCleanupThreadGetTid(); - OSLockAcquire(psPvrData->hProcessHandleBase_Lock); + OSLockAcquire(g_hProcessHandleBaseLock); /* Check to see if we're being called from the cleanup thread... */ - if ((OSGetCurrentClientProcessIDKM() == psPvrData->cleanupThreadPid) && - (ui32PurgePid > 0)) + if ((OSGetCurrentProcessID() == uiCleanupPid) && + (OSGetCurrentThreadID() == uiCleanupTid) && + (ui32PurgePid > 0)) { /* Check to see if the cleanup thread has already removed the * process handle base from the HASH table. */ - psHandleBase = psPvrData->psProcessHandleBaseBeingFreed; + psHandleBase = g_psProcessHandleBaseBeingFreed; /* psHandleBase shouldn't be null, as cleanup thread * should be removing this from the HASH table before * we get here, so assert if not. @@ -2093,10 +2149,11 @@ PVRSRV_HANDLE_BASE *PVRSRVRetrieveProcessHandleBase(void) /* Not being called from the cleanup thread, so return the process * handle base for the current process. */ - psProcHandleBase = (PROCESS_HANDLE_BASE*) HASH_Retrieve(psPvrData->psProcessHandleBase_Table, - OSGetCurrentClientProcessIDKM()); + psProcHandleBase = (PROCESS_HANDLE_BASE *) + HASH_Retrieve(g_psProcessHandleBaseTable, OSGetCurrentClientProcessIDKM()); } - OSLockRelease(psPvrData->hProcessHandleBase_Lock); + + OSLockRelease(g_hProcessHandleBaseLock); if (psHandleBase == NULL && psProcHandleBase != NULL) { @@ -2105,6 +2162,112 @@ PVRSRV_HANDLE_BASE *PVRSRVRetrieveProcessHandleBase(void) return psHandleBase; } +/*! +******************************************************************************* + @Function PVRSRVAcquireProcessHandleBase + @Description Increments reference count on a process handle base identified + by uiPid and returns pointer to the base. If the handle base + does not exist it will be allocated. + @Inout uiPid - PID of a process + @Output ppsBase - pointer to a handle base for the process identified by + uiPid + @Return Error code or PVRSRV_OK +******************************************************************************/ +PVRSRV_ERROR PVRSRVAcquireProcessHandleBase(IMG_PID uiPid, PROCESS_HANDLE_BASE **ppsBase) +{ + PROCESS_HANDLE_BASE *psBase; + PVRSRV_ERROR eError; + + OSLockAcquire(g_hProcessHandleBaseLock); + + psBase = (PROCESS_HANDLE_BASE*) HASH_Retrieve(g_psProcessHandleBaseTable, uiPid); + + /* In case there is none we are going to allocate one */ + if (psBase == NULL) + { + IMG_BOOL bSuccess; + + psBase = OSAllocZMem(sizeof(*psBase)); + PVR_LOG_GOTO_IF_NOMEM(psBase, eError, ErrorUnlock); + + /* Allocate handle base for this process */ + eError = PVRSRVAllocHandleBase(&psBase->psHandleBase, PVRSRV_HANDLE_BASE_TYPE_PROCESS); + PVR_LOG_GOTO_IF_ERROR(eError, "PVRSRVAllocHandleBase", ErrorFreeProcessHandleBase); + + /* Insert the handle base into the global hash table */ + bSuccess = HASH_Insert(g_psProcessHandleBaseTable, uiPid, (uintptr_t) psBase); + PVR_LOG_GOTO_IF_FALSE(bSuccess, "HASH_Insert failed", ErrorFreeHandleBase); + } + + OSAtomicIncrement(&psBase->iRefCount); + + OSLockRelease(g_hProcessHandleBaseLock); + + *ppsBase = psBase; + + return PVRSRV_OK; + +ErrorFreeHandleBase: + PVRSRVFreeHandleBase(psBase->psHandleBase, 0); +ErrorFreeProcessHandleBase: + OSFreeMem(psBase); +ErrorUnlock: + OSLockRelease(g_hProcessHandleBaseLock); + + return eError; +} + +/*! +******************************************************************************* + @Function PVRSRVReleaseProcessHandleBase + @Description Decrements reference count on a process handle base psBase + for a process identified by uiPid. If the reference count + reaches 0 the handle base will be freed.. + @Input psBase - pointer to a process handle base + @Inout uiPid - PID of a process + @Inout ui64MaxBridgeTime - maximum time a handle destroy operation + can hold the handle base lock (after that + time a lock will be release and reacquired + for another time slice) + @Return Error code or PVRSRV_OK +******************************************************************************/ +PVRSRV_ERROR PVRSRVReleaseProcessHandleBase(PROCESS_HANDLE_BASE *psBase, IMG_PID uiPid, + IMG_UINT64 ui64MaxBridgeTime) +{ + PVRSRV_ERROR eError; + IMG_INT iRefCount; + uintptr_t uiHashValue; + + OSLockAcquire(g_hProcessHandleBaseLock); + + iRefCount = OSAtomicDecrement(&psBase->iRefCount); + + if (iRefCount != 0) + { + OSLockRelease(g_hProcessHandleBaseLock); + return PVRSRV_OK; + } + + /* in case the refcount becomes 0 we can remove the process handle base + * and all related objects */ + + uiHashValue = HASH_Remove(g_psProcessHandleBaseTable, uiPid); + OSLockRelease(g_hProcessHandleBaseLock); + + PVR_LOG_RETURN_IF_FALSE(uiHashValue != 0, "HASH_Remove failed", + PVRSRV_ERROR_UNABLE_TO_REMOVE_HASH_VALUE); + + eError = PVRSRVFreeKernelHandles(psBase->psHandleBase); + PVR_LOG_RETURN_IF_ERROR(eError, "PVRSRVFreeKernelHandles"); + + eError = PVRSRVFreeHandleBase(psBase->psHandleBase, ui64MaxBridgeTime); + PVR_LOG_RETURN_IF_ERROR(eError, "PVRSRVFreeHandleBase"); + + OSFreeMem(psBase); + + return PVRSRV_OK; +} + /*! ******************************************************************************* @Function PVRSRVFreeHandleBase @@ -2120,20 +2283,21 @@ PVRSRV_ERROR PVRSRVFreeHandleBase(PVRSRV_HANDLE_BASE *psBase, IMG_UINT64 ui64Max FREE_HANDLE_DATA sHandleData = {NULL}; IMG_UINT32 i; PVRSRV_ERROR eError; - PVRSRV_DATA *psPVRSRVData = PVRSRVGetPVRSRVData(); - IMG_PID uiCleanupPid = psPVRSRVData->cleanupThreadPid; + IMG_PID uiCleanupPid = PVRSRVCleanupThreadGetPid(); + uintptr_t uiCleanupTid = PVRSRVCleanupThreadGetTid(); PVR_ASSERT(gpsHandleFuncs); - /* LockHandle(psBase); - func only run in single thread ctx */ + LockHandle(psBase); /* If this is a process handle base being freed by the cleanup - * thread, store this in psPVRSRVData->psProcessHandleBaseBeingFreed + * thread, store this in g_psProcessHandleBaseBeingFreed */ - if ((OSGetCurrentClientProcessIDKM() == uiCleanupPid) && + if ((OSGetCurrentProcessID() == uiCleanupPid) && + (OSGetCurrentThreadID() == uiCleanupTid) && (psBase->eType == PVRSRV_HANDLE_BASE_TYPE_PROCESS)) { - psPVRSRVData->psProcessHandleBaseBeingFreed = psBase; + g_psProcessHandleBaseBeingFreed = psBase; } sHandleData.psBase = psBase; @@ -2152,7 +2316,7 @@ PVRSRV_ERROR PVRSRVFreeHandleBase(PVRSRV_HANDLE_BASE *psBase, IMG_UINT64 ui64Max if (sCountData.uiHandleDataCount != 0) { - IMG_BOOL bList = sCountData.uiHandleDataCount < HANDLE_DEBUG_LISTING_MAX_NUM; + IMG_BOOL bList = (IMG_BOOL)(sCountData.uiHandleDataCount < HANDLE_DEBUG_LISTING_MAX_NUM); PVR_DPF((PVR_DBG_WARNING, "%s: %u remaining handles in handle base 0x%p " @@ -2200,18 +2364,19 @@ PVRSRV_ERROR PVRSRVFreeHandleBase(PVRSRV_HANDLE_BASE *psBase, IMG_UINT64 ui64Max eError = gpsHandleFuncs->pfnDestroyHandleBase(psBase->psImplBase); PVR_GOTO_IF_ERROR(eError, ExitUnlock); - /* UnlockHandle(psBase); - func only run in single thread ctx */ + UnlockHandle(psBase); OSLockDestroy(psBase->hLock); OSFreeMem(psBase); return eError; ExitUnlock: - if (OSGetCurrentClientProcessIDKM() == uiCleanupPid) + if ((OSGetCurrentProcessID() == uiCleanupPid) && + (OSGetCurrentThreadID() == uiCleanupTid)) { - psPVRSRVData->psProcessHandleBaseBeingFreed = NULL; + g_psProcessHandleBaseBeingFreed = NULL; } - /* UnlockHandle(psBase); - func only run in single thread ctx */ + UnlockHandle(psBase); return eError; } @@ -2228,10 +2393,15 @@ PVRSRV_ERROR PVRSRVHandleInit(void) PVR_ASSERT(gpsKernelHandleBase == NULL); PVR_ASSERT(gpsHandleFuncs == NULL); + PVR_ASSERT(g_hProcessHandleBaseLock == NULL); + PVR_ASSERT(g_psProcessHandleBaseTable == NULL); PVR_ASSERT(!gbLockInitialised); eError = OSLockCreate(&gKernelHandleLock); - PVR_LOG_RETURN_IF_ERROR(eError, "OSLockCreate"); + PVR_LOG_RETURN_IF_ERROR(eError, "OSLockCreate:1"); + + eError = OSLockCreate(&g_hProcessHandleBaseLock); + PVR_LOG_GOTO_IF_ERROR(eError, "OSLockCreate:2", ErrorHandleDeinit); gbLockInitialised = IMG_TRUE; @@ -2242,9 +2412,11 @@ PVRSRV_ERROR PVRSRVHandleInit(void) PVRSRV_HANDLE_BASE_TYPE_GLOBAL); PVR_LOG_GOTO_IF_ERROR(eError, "PVRSRVAllocHandleBase", ErrorHandleDeinit); + g_psProcessHandleBaseTable = HASH_Create(HANDLE_PROC_HANDLE_HASH_INIT_SIZE); + PVR_LOG_GOTO_IF_NOMEM(g_psProcessHandleBaseTable, eError, ErrorHandleDeinit); + eError = gpsHandleFuncs->pfnEnableHandlePurging(gpsKernelHandleBase->psImplBase); - PVR_LOG_GOTO_IF_ERROR(eError, "pfnEnableHandlePurging", - ErrorHandleDeinit); + PVR_LOG_GOTO_IF_ERROR(eError, "pfnEnableHandlePurging", ErrorHandleDeinit); return PVRSRV_OK; @@ -2290,7 +2462,19 @@ PVRSRV_ERROR PVRSRVHandleDeInit(void) PVR_ASSERT(gpsKernelHandleBase == NULL); } - if (gbLockInitialised) + if (g_psProcessHandleBaseTable != NULL) + { + HASH_Delete(g_psProcessHandleBaseTable); + g_psProcessHandleBaseTable = NULL; + } + + if (g_hProcessHandleBaseLock != NULL) + { + OSLockDestroy(g_hProcessHandleBaseLock); + g_hProcessHandleBaseLock = NULL; + } + + if (gKernelHandleLock != NULL) { OSLockDestroy(gKernelHandleLock); gbLockInitialised = IMG_FALSE; diff --git a/drivers/gpu/drm/img-rogue/handle.h b/drivers/gpu/drm/img-rogue/handle.h index d9db37133..92946b6fb 100644 --- a/drivers/gpu/drm/img-rogue/handle.h +++ b/drivers/gpu/drm/img-rogue/handle.h @@ -99,7 +99,7 @@ CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. * Given a handle for a resource of type eType, return the pointer to the * resource. * - * PVRSRV_ERROR PVRSRVLookuSubHandle(PVRSRV_HANDLE_BASE *psBase, + * PVRSRV_ERROR PVRSRVLookupSubHandle(PVRSRV_HANDLE_BASE *psBase, * void **ppvData, IMG_HANDLE hHandle, PVRSRV_HANDLE_TYPE eType, * IMH_HANDLE hAncestor); * @@ -152,7 +152,6 @@ typedef struct _PROCESS_HANDLE_BASE_ { PVRSRV_HANDLE_BASE *psHandleBase; ATOMIC_T iRefCount; - } PROCESS_HANDLE_BASE; extern PVRSRV_HANDLE_BASE *gpsKernelHandleBase; @@ -176,9 +175,12 @@ PVRSRV_ERROR PVRSRVLookupHandleUnlocked(PVRSRV_HANDLE_BASE *psBase, void **ppvDa PVRSRV_ERROR PVRSRVLookupSubHandle(PVRSRV_HANDLE_BASE *psBase, void **ppvData, IMG_HANDLE hHandle, PVRSRV_HANDLE_TYPE eType, IMG_HANDLE hAncestor); -PVRSRV_ERROR PVRSRVReleaseHandle(PVRSRV_HANDLE_BASE *psBase, IMG_HANDLE hHandle, PVRSRV_HANDLE_TYPE eType); -PVRSRV_ERROR PVRSRVReleaseHandleUnlocked(PVRSRV_HANDLE_BASE *psBase, IMG_HANDLE hHandle, PVRSRV_HANDLE_TYPE eType); -PVRSRV_ERROR PVRSRVReleaseHandleStagedUnlock(PVRSRV_HANDLE_BASE *psBase, IMG_HANDLE hHandle, PVRSRV_HANDLE_TYPE eType); +void PVRSRVReleaseHandle(PVRSRV_HANDLE_BASE *psBase, IMG_HANDLE hHandle, PVRSRV_HANDLE_TYPE eType); +void PVRSRVReleaseHandleUnlocked(PVRSRV_HANDLE_BASE *psBase, IMG_HANDLE hHandle, PVRSRV_HANDLE_TYPE eType); + +PVRSRV_ERROR PVRSRVDestroyHandle(PVRSRV_HANDLE_BASE *psBase, IMG_HANDLE hHandle, PVRSRV_HANDLE_TYPE eType); +PVRSRV_ERROR PVRSRVDestroyHandleUnlocked(PVRSRV_HANDLE_BASE *psBase, IMG_HANDLE hHandle, PVRSRV_HANDLE_TYPE eType); +PVRSRV_ERROR PVRSRVDestroyHandleStagedUnlocked(PVRSRV_HANDLE_BASE *psBase, IMG_HANDLE hHandle, PVRSRV_HANDLE_TYPE eType); PVRSRV_ERROR PVRSRVPurgeHandles(PVRSRV_HANDLE_BASE *psBase); @@ -195,6 +197,9 @@ PVRSRV_ERROR PVRSRVHandleDeInit(void); PVRSRV_HANDLE_BASE *PVRSRVRetrieveProcessHandleBase(void); +PVRSRV_ERROR PVRSRVAcquireProcessHandleBase(IMG_PID uiPid, PROCESS_HANDLE_BASE **ppsBase); +PVRSRV_ERROR PVRSRVReleaseProcessHandleBase(PROCESS_HANDLE_BASE *psBase, IMG_PID uiPid, IMG_UINT64 ui64MaxBridgeTime); + void LockHandle(PVRSRV_HANDLE_BASE *psBase); void UnlockHandle(PVRSRV_HANDLE_BASE *psBase); diff --git a/drivers/gpu/drm/img-rogue/handle_types.h b/drivers/gpu/drm/img-rogue/handle_types.h index 4e3a9d994..795e20618 100644 --- a/drivers/gpu/drm/img-rogue/handle_types.h +++ b/drivers/gpu/drm/img-rogue/handle_types.h @@ -63,6 +63,9 @@ HANDLETYPE(RGX_SERVER_TQ_TDM_CONTEXT) HANDLETYPE(RGX_SERVER_COMPUTE_CONTEXT) HANDLETYPE(RGX_SERVER_RAY_CONTEXT) HANDLETYPE(RGX_SERVER_KICKSYNC_CONTEXT) +#if defined(PVR_TESTING_UTILS) && defined(SUPPORT_VALIDATION) +HANDLETYPE(RGX_SERVER_GPUMAP_CONTEXT) +#endif HANDLETYPE(SYNC_PRIMITIVE_BLOCK) HANDLETYPE(SYNC_RECORD_HANDLE) HANDLETYPE(PVRSRV_TIMELINE_SERVER) diff --git a/drivers/gpu/drm/img-rogue/htbuffer.c b/drivers/gpu/drm/img-rogue/htbuffer.c index 00dbe926b..c326ae261 100644 --- a/drivers/gpu/drm/img-rogue/htbuffer.c +++ b/drivers/gpu/drm/img-rogue/htbuffer.c @@ -45,7 +45,18 @@ IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. */ /**************************************************************************/ -#include +#if defined(__linux__) + #include + + #if (LINUX_VERSION_CODE >= KERNEL_VERSION(5, 15, 0)) + #include + #else + #include + #endif /* LINUX_VERSION_CODE >= KERNEL_VERSION(5, 15, 0) */ +#else + #include +#endif /* __linux__ */ + #include "htbuffer.h" #include "osfunc.h" #include "client_htbuffer_bridge.h" diff --git a/drivers/gpu/drm/img-rogue/img_defs.h b/drivers/gpu/drm/img-rogue/img_defs.h index 294d05b0d..a79e8a65d 100644 --- a/drivers/gpu/drm/img-rogue/img_defs.h +++ b/drivers/gpu/drm/img-rogue/img_defs.h @@ -150,19 +150,19 @@ CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. do { \ assert(!(msg)); \ __builtin_unreachable(); \ - } while (0) + } while (false) #elif defined(_MSC_VER) #define unreachable(msg) \ do { \ assert(!(msg)); \ __assume(0); \ - } while (0) + } while (false) #else #define unreachable(msg) \ do { \ assert(!(msg)); \ while (1); \ - } while (0) + } while (false) #endif /* @@ -175,13 +175,13 @@ CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. do { \ assert(expr); \ __builtin_assume(expr); \ - } while (0) + } while (false) #elif defined(_MSC_VER) #define assume(expr) \ do { \ assert(expr); \ __assume(expr); \ - } while (0) + } while (false) #elif defined(__linux__) && defined(__KERNEL__) #define assume(expr) ((void)(expr)) #elif GCC_VERSION_AT_LEAST(4, 5) || has_clang_builtin(__builtin_unreachable) @@ -189,7 +189,7 @@ CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. do { \ if (unlikely(!(expr))) \ unreachable("Assumption isn't true: " # expr); \ - } while (0) + } while (false) #else #define assume(expr) assert(expr) #endif @@ -506,6 +506,7 @@ CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. #define VG_MARK_INITIALIZED(pvData,ui32Size) VALGRIND_MAKE_MEM_DEFINED(pvData,ui32Size) #define VG_MARK_NOACCESS(pvData,ui32Size) VALGRIND_MAKE_MEM_NOACCESS(pvData,ui32Size) #define VG_MARK_ACCESS(pvData,ui32Size) VALGRIND_MAKE_MEM_UNDEFINED(pvData,ui32Size) + #define VG_ASSERT_DEFINED(pvData,ui32Size) VALGRIND_CHECK_MEM_IS_DEFINED(pvData,ui32Size) #else #if defined(_MSC_VER) # define PVR_MSC_SUPPRESS_4127 __pragma(warning(suppress:4127)) @@ -513,9 +514,10 @@ CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. # define PVR_MSC_SUPPRESS_4127 #endif - #define VG_MARK_INITIALIZED(pvData,ui32Size) PVR_MSC_SUPPRESS_4127 do { } while (0) - #define VG_MARK_NOACCESS(pvData,ui32Size) PVR_MSC_SUPPRESS_4127 do { } while (0) - #define VG_MARK_ACCESS(pvData,ui32Size) PVR_MSC_SUPPRESS_4127 do { } while (0) + #define VG_MARK_INITIALIZED(pvData,ui32Size) PVR_MSC_SUPPRESS_4127 do { } while (false) + #define VG_MARK_NOACCESS(pvData,ui32Size) PVR_MSC_SUPPRESS_4127 do { } while (false) + #define VG_MARK_ACCESS(pvData,ui32Size) PVR_MSC_SUPPRESS_4127 do { } while (false) + #define VG_ASSERT_DEFINED(pvData,ui32Size) PVR_MSC_SUPPRESS_4127 do { } while (false) #endif #define IMG_STRINGIFY_IMPL(x) # x diff --git a/drivers/gpu/drm/img-rogue/img_types.h b/drivers/gpu/drm/img-rogue/img_types.h index 826f03e9f..c2654d21e 100644 --- a/drivers/gpu/drm/img-rogue/img_types.h +++ b/drivers/gpu/drm/img-rogue/img_types.h @@ -254,13 +254,19 @@ typedef struct { #if defined(UNDER_WDDM) || defined(WINDOWS_WDF) uintptr_t uiAddr; -#define IMG_CAST_TO_CPUPHYADDR_UINT(var) (uintptr_t)(var) +#define IMG_CAST_TO_CPUPHYADDR_UINT(var) (uintptr_t)(var) +#define CPUPHYADDR_FMTARG(var) (IMG_UINT64)(var) +#define CPUPHYADDR_UINT_FMTSPEC "0x%016" IMG_UINT64_FMTSPECx #elif defined(__linux__) && defined(__KERNEL__) phys_addr_t uiAddr; -#define IMG_CAST_TO_CPUPHYADDR_UINT(var) (phys_addr_t)(var) +#define IMG_CAST_TO_CPUPHYADDR_UINT(var) (phys_addr_t)(var) +#define CPUPHYADDR_FMTARG(var) (&var) +#define CPUPHYADDR_UINT_FMTSPEC "%pa" #else IMG_UINT64 uiAddr; -#define IMG_CAST_TO_CPUPHYADDR_UINT(var) (IMG_UINT64)(var) +#define IMG_CAST_TO_CPUPHYADDR_UINT(var) (IMG_UINT64)(var) +#define CPUPHYADDR_FMTARG(var) (var) +#define CPUPHYADDR_UINT_FMTSPEC "0x%016" IMG_UINT64_FMTSPECx #endif } IMG_CPU_PHYADDR; diff --git a/drivers/gpu/drm/img-rogue/include/devicemem_typedefs.h b/drivers/gpu/drm/img-rogue/include/devicemem_typedefs.h index 98ad36c91..dd66fccf3 100644 --- a/drivers/gpu/drm/img-rogue/include/devicemem_typedefs.h +++ b/drivers/gpu/drm/img-rogue/include/devicemem_typedefs.h @@ -137,6 +137,6 @@ typedef IMG_UINT32 SPARSE_MEM_RESIZE_FLAGS; /* Defines the max length for PMR, MemDesc, Device memory History and RI debug * annotations stored in memory, including the null terminator. */ -#define DEVMEM_ANNOTATION_MAX_LEN (PVR_ANNOTATION_MAX_LEN + 1U) +#define DEVMEM_ANNOTATION_MAX_LEN ((IMG_UINT32)PVR_ANNOTATION_MAX_LEN + 1U) #endif /* #ifndef DEVICEMEM_TYPEDEFS_H */ diff --git a/drivers/gpu/drm/img-rogue/include/drm/pvr_drm.h b/drivers/gpu/drm/img-rogue/include/drm/pvr_drm.h index 65c293be6..c0d00c98d 100644 --- a/drivers/gpu/drm/img-rogue/include/drm/pvr_drm.h +++ b/drivers/gpu/drm/img-rogue/include/drm/pvr_drm.h @@ -89,6 +89,17 @@ struct pvr_sw_timeline_advance_data { __u64 sync_pt_idx; }; +#define PVR_SRVKM_SERVICES_INIT 1 +#define PVR_SRVKM_SYNC_INIT 2 +struct drm_pvr_srvkm_init_data { + __u32 init_module; +}; + +/* Values used to configure the PVRSRV_DEVICE_INIT_MODE tunable (Linux-only) */ +#define PVRSRV_LINUX_DEV_INIT_ON_PROBE 1 +#define PVRSRV_LINUX_DEV_INIT_ON_OPEN 2 +#define PVRSRV_LINUX_DEV_INIT_ON_CONNECT 3 + /* * DRM command numbers, relative to DRM_COMMAND_BASE. * These defines must be prefixed with "DRM_". @@ -105,6 +116,9 @@ struct pvr_sw_timeline_advance_data { #define DRM_PVR_SW_SYNC_CREATE_FENCE_CMD 3 #define DRM_PVR_SW_SYNC_INC_CMD 4 +/* PVR Services Render Device Init command */ +#define DRM_PVR_SRVKM_INIT 5 + /* These defines must be prefixed with "DRM_IOCTL_". */ #define DRM_IOCTL_PVR_SRVKM_CMD \ DRM_IOWR(DRM_COMMAND_BASE + DRM_PVR_SRVKM_CMD, \ @@ -125,4 +139,8 @@ struct pvr_sw_timeline_advance_data { DRM_IOR(DRM_COMMAND_BASE + DRM_PVR_SW_SYNC_INC_CMD, \ struct pvr_sw_timeline_advance_data) +#define DRM_IOCTL_PVR_SRVKM_INIT \ + DRM_IOW(DRM_COMMAND_BASE + DRM_PVR_SRVKM_INIT, \ + struct drm_pvr_srvkm_init_data) + #endif /* defined(__PVR_DRM_H__) */ diff --git a/drivers/gpu/drm/img-rogue/include/img_defs.h b/drivers/gpu/drm/img-rogue/include/img_defs.h index 294d05b0d..a79e8a65d 100644 --- a/drivers/gpu/drm/img-rogue/include/img_defs.h +++ b/drivers/gpu/drm/img-rogue/include/img_defs.h @@ -150,19 +150,19 @@ CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. do { \ assert(!(msg)); \ __builtin_unreachable(); \ - } while (0) + } while (false) #elif defined(_MSC_VER) #define unreachable(msg) \ do { \ assert(!(msg)); \ __assume(0); \ - } while (0) + } while (false) #else #define unreachable(msg) \ do { \ assert(!(msg)); \ while (1); \ - } while (0) + } while (false) #endif /* @@ -175,13 +175,13 @@ CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. do { \ assert(expr); \ __builtin_assume(expr); \ - } while (0) + } while (false) #elif defined(_MSC_VER) #define assume(expr) \ do { \ assert(expr); \ __assume(expr); \ - } while (0) + } while (false) #elif defined(__linux__) && defined(__KERNEL__) #define assume(expr) ((void)(expr)) #elif GCC_VERSION_AT_LEAST(4, 5) || has_clang_builtin(__builtin_unreachable) @@ -189,7 +189,7 @@ CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. do { \ if (unlikely(!(expr))) \ unreachable("Assumption isn't true: " # expr); \ - } while (0) + } while (false) #else #define assume(expr) assert(expr) #endif @@ -506,6 +506,7 @@ CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. #define VG_MARK_INITIALIZED(pvData,ui32Size) VALGRIND_MAKE_MEM_DEFINED(pvData,ui32Size) #define VG_MARK_NOACCESS(pvData,ui32Size) VALGRIND_MAKE_MEM_NOACCESS(pvData,ui32Size) #define VG_MARK_ACCESS(pvData,ui32Size) VALGRIND_MAKE_MEM_UNDEFINED(pvData,ui32Size) + #define VG_ASSERT_DEFINED(pvData,ui32Size) VALGRIND_CHECK_MEM_IS_DEFINED(pvData,ui32Size) #else #if defined(_MSC_VER) # define PVR_MSC_SUPPRESS_4127 __pragma(warning(suppress:4127)) @@ -513,9 +514,10 @@ CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. # define PVR_MSC_SUPPRESS_4127 #endif - #define VG_MARK_INITIALIZED(pvData,ui32Size) PVR_MSC_SUPPRESS_4127 do { } while (0) - #define VG_MARK_NOACCESS(pvData,ui32Size) PVR_MSC_SUPPRESS_4127 do { } while (0) - #define VG_MARK_ACCESS(pvData,ui32Size) PVR_MSC_SUPPRESS_4127 do { } while (0) + #define VG_MARK_INITIALIZED(pvData,ui32Size) PVR_MSC_SUPPRESS_4127 do { } while (false) + #define VG_MARK_NOACCESS(pvData,ui32Size) PVR_MSC_SUPPRESS_4127 do { } while (false) + #define VG_MARK_ACCESS(pvData,ui32Size) PVR_MSC_SUPPRESS_4127 do { } while (false) + #define VG_ASSERT_DEFINED(pvData,ui32Size) PVR_MSC_SUPPRESS_4127 do { } while (false) #endif #define IMG_STRINGIFY_IMPL(x) # x diff --git a/drivers/gpu/drm/img-rogue/include/img_drm_fourcc_internal.h b/drivers/gpu/drm/img-rogue/include/img_drm_fourcc_internal.h index 162a646af..ee88e90cd 100644 --- a/drivers/gpu/drm/img-rogue/include/img_drm_fourcc_internal.h +++ b/drivers/gpu/drm/img-rogue/include/img_drm_fourcc_internal.h @@ -61,7 +61,7 @@ CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. */ #define DRM_FORMAT_MOD_PVR_FBCDC_8x8_V0 fourcc_mod_code(PVR, 1) #define DRM_FORMAT_MOD_PVR_FBCDC_8x8_V0_FIX fourcc_mod_code(PVR, 2) /* Fix for HW_BRN_37464 */ -#define DRM_FORMAT_MOD_PVR_FBCDC_8x8_V1 fourcc_mod_code(PVR, 3) +/* DRM_FORMAT_MOD_PVR_FBCDC_8x8_V1 - moved to the public header */ #define DRM_FORMAT_MOD_PVR_FBCDC_8x8_V2 fourcc_mod_code(PVR, 4) #define DRM_FORMAT_MOD_PVR_FBCDC_8x8_V3 fourcc_mod_code(PVR, 5) /* DRM_FORMAT_MOD_PVR_FBCDC_8x8_V7 - moved to the public header */ @@ -74,7 +74,7 @@ CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. /* DRM_FORMAT_MOD_PVR_FBCDC_8x8_LOSSY75_V13 - moved to the public header */ #define DRM_FORMAT_MOD_PVR_FBCDC_16x4_V0 fourcc_mod_code(PVR, 7) #define DRM_FORMAT_MOD_PVR_FBCDC_16x4_V0_FIX fourcc_mod_code(PVR, 8) /* Fix for HW_BRN_37464 */ -#define DRM_FORMAT_MOD_PVR_FBCDC_16x4_V1 fourcc_mod_code(PVR, 9) +/* DRM_FORMAT_MOD_PVR_FBCDC_16x4_V1 - moved to the public header */ #define DRM_FORMAT_MOD_PVR_FBCDC_16x4_V2 fourcc_mod_code(PVR, 10) #define DRM_FORMAT_MOD_PVR_FBCDC_16x4_V3 fourcc_mod_code(PVR, 11) /* DRM_FORMAT_MOD_PVR_FBCDC_16x4_V7 - moved to the public header */ diff --git a/drivers/gpu/drm/img-rogue/include/img_types.h b/drivers/gpu/drm/img-rogue/include/img_types.h index 826f03e9f..c2654d21e 100644 --- a/drivers/gpu/drm/img-rogue/include/img_types.h +++ b/drivers/gpu/drm/img-rogue/include/img_types.h @@ -254,13 +254,19 @@ typedef struct { #if defined(UNDER_WDDM) || defined(WINDOWS_WDF) uintptr_t uiAddr; -#define IMG_CAST_TO_CPUPHYADDR_UINT(var) (uintptr_t)(var) +#define IMG_CAST_TO_CPUPHYADDR_UINT(var) (uintptr_t)(var) +#define CPUPHYADDR_FMTARG(var) (IMG_UINT64)(var) +#define CPUPHYADDR_UINT_FMTSPEC "0x%016" IMG_UINT64_FMTSPECx #elif defined(__linux__) && defined(__KERNEL__) phys_addr_t uiAddr; -#define IMG_CAST_TO_CPUPHYADDR_UINT(var) (phys_addr_t)(var) +#define IMG_CAST_TO_CPUPHYADDR_UINT(var) (phys_addr_t)(var) +#define CPUPHYADDR_FMTARG(var) (&var) +#define CPUPHYADDR_UINT_FMTSPEC "%pa" #else IMG_UINT64 uiAddr; -#define IMG_CAST_TO_CPUPHYADDR_UINT(var) (IMG_UINT64)(var) +#define IMG_CAST_TO_CPUPHYADDR_UINT(var) (IMG_UINT64)(var) +#define CPUPHYADDR_FMTARG(var) (var) +#define CPUPHYADDR_UINT_FMTSPEC "0x%016" IMG_UINT64_FMTSPECx #endif } IMG_CPU_PHYADDR; diff --git a/drivers/gpu/drm/img-rogue/include/lock_types.h b/drivers/gpu/drm/img-rogue/include/lock_types.h index c9e784ef8..370ffc025 100644 --- a/drivers/gpu/drm/img-rogue/include/lock_types.h +++ b/drivers/gpu/drm/img-rogue/include/lock_types.h @@ -60,29 +60,29 @@ typedef atomic_t ATOMIC_T; #else /* defined(__linux__) && defined(__KERNEL__) */ #include "img_types.h" /* needed for IMG_INT */ -typedef struct _OS_LOCK_ *POS_LOCK; +typedef struct OS_LOCK_TAG *POS_LOCK; #if defined(__linux__) || defined(__QNXNTO__) || defined(INTEGRITY_OS) -typedef struct _OSWR_LOCK_ *POSWR_LOCK; +typedef struct OSWR_LOCK_TAG *POSWR_LOCK; #else /* defined(__linux__) || defined(__QNXNTO__) || defined(INTEGRITY_OS) */ -typedef struct _OSWR_LOCK_ { +typedef struct OSWR_LOCK_TAG { IMG_UINT32 ui32Dummy; } *POSWR_LOCK; #endif /* defined(__linux__) || defined(__QNXNTO__) || defined(INTEGRITY_OS) */ #if defined(__linux__) - typedef struct _OS_ATOMIC {IMG_INT32 counter;} ATOMIC_T; + typedef struct OS_ATOMIC_TAG {IMG_INT32 counter;} ATOMIC_T; #elif defined(__QNXNTO__) - typedef struct _OS_ATOMIC {IMG_INT32 counter;} ATOMIC_T; + typedef struct OS_ATOMIC_TAG {IMG_INT32 counter;} ATOMIC_T; #elif defined(_WIN32) /* * Dummy definition. WDDM doesn't use Services, but some headers * still have to be shared. This is one such case. */ - typedef struct _OS_ATOMIC {IMG_INT32 counter;} ATOMIC_T; + typedef struct OS_ATOMIC_TAG {IMG_INT32 counter;} ATOMIC_T; #elif defined(INTEGRITY_OS) /* Only lower 32bits are used in OS ATOMIC APIs to have consistent behaviour across all OS */ - typedef struct _OS_ATOMIC {IMG_INT64 counter;} ATOMIC_T; + typedef struct OS_ATOMIC_TAG {IMG_INT64 counter;} ATOMIC_T; #else #error "Please type-define an atomic lock for this environment" #endif diff --git a/drivers/gpu/drm/img-rogue/include/log2.h b/drivers/gpu/drm/img-rogue/include/log2.h index 4cba23f9d..2182a0223 100644 --- a/drivers/gpu/drm/img-rogue/include/log2.h +++ b/drivers/gpu/drm/img-rogue/include/log2.h @@ -270,7 +270,7 @@ static INLINE uint32_t __const_function FloorLog2(uint32_t n) { uint32_t ui32log2 = 0; - while (n >>= 1) + while ((n >>= 1) != 0U) { ui32log2++; } @@ -287,7 +287,7 @@ static INLINE uint32_t __const_function FloorLog2_64(uint64_t n) { uint32_t ui32log2 = 0; - while (n >>= 1) + while ((n >>= 1) != 0U) { ui32log2++; } @@ -311,7 +311,7 @@ static INLINE uint32_t __const_function CeilLog2(uint32_t n) n--; /* Handle powers of 2 */ - while (n) + while (n != 0U) { ui32log2++; n >>= 1; @@ -336,7 +336,7 @@ static INLINE uint32_t __const_function CeilLog2_64(uint64_t n) n--; /* Handle powers of 2 */ - while (n) + while (n != 0U) { ui32log2++; n >>= 1; diff --git a/drivers/gpu/drm/img-rogue/include/osfunc_common.h b/drivers/gpu/drm/img-rogue/include/osfunc_common.h index f209bede8..539ef2c04 100644 --- a/drivers/gpu/drm/img-rogue/include/osfunc_common.h +++ b/drivers/gpu/drm/img-rogue/include/osfunc_common.h @@ -154,7 +154,14 @@ size_t StringLCopy(IMG_CHAR *pszDest, const IMG_CHAR *pszSrc, size_t uDataSize); @Input c the number of bytes to be set to the given value @Return Pointer to the destination memory. */ /**************************************************************************/ -#define OSDeviceMemSet(a,b,c) memset((a), (b), (c)) +#define OSDeviceMemSet(a,b,c) \ + do { \ + if ((c) != 0) \ + { \ + (void) memset((a), (b), (c)); \ + (void) *(volatile IMG_UINT32*)((void*)(a)); \ + } \ + } while (false) /**************************************************************************/ /*! @Function OSDeviceMemCopy @@ -167,7 +174,14 @@ size_t StringLCopy(IMG_CHAR *pszDest, const IMG_CHAR *pszSrc, size_t uDataSize); @Input c the number of bytes to be copied @Return Pointer to the destination memory. */ /**************************************************************************/ -#define OSDeviceMemCopy(a,b,c) memcpy((a), (b), (c)) +#define OSDeviceMemCopy(a,b,c) \ + do { \ + if ((c) != 0) \ + { \ + memcpy((a), (b), (c)); \ + (void) *(volatile IMG_UINT32*)((void*)(a)); \ + } \ + } while (false) #endif /* (defined(__arm64__) || defined(__aarch64__) || defined(PVRSRV_DEVMEM_TEST_SAFE_MEMSETCPY)) */ @@ -181,7 +195,7 @@ size_t StringLCopy(IMG_CHAR *pszDest, const IMG_CHAR *pszSrc, size_t uDataSize); @Input c the number of bytes to be set to the given value @Return Pointer to the destination memory. */ /**************************************************************************/ -#define OSCachedMemSet(a,b,c) memset((a), (b), (c)) +#define OSCachedMemSet(a,b,c) (void) memset((a), (b), (c)) /**************************************************************************/ /*! @Function OSCachedMemCopy @@ -210,12 +224,22 @@ size_t StringLCopy(IMG_CHAR *pszDest, const IMG_CHAR *pszSrc, size_t uDataSize); @Input c the number of bytes to be set to the given value @Return Pointer to the destination memory. */ /**************************************************************************/ +#if !defined(SERVICES_SC) +#define OSCachedMemSetWMB(a,b,c) \ + do { \ + if ((c) != 0) \ + { \ + (void) memset((a), (b), (c)); \ + OSWriteMemoryBarrier(a); \ + } \ + } while (false) +#else #define OSCachedMemSetWMB(a,b,c) \ do { \ (void) memset((a), (b), (c)); \ OSWriteMemoryBarrier(); \ - } while (0) - + } while (false) +#endif /* !defined(SERVICES_SC) */ /**************************************************************************/ /*! @Function OSCachedMemCopy @Description Copy values from one area of memory, to another, when both @@ -228,12 +252,22 @@ size_t StringLCopy(IMG_CHAR *pszDest, const IMG_CHAR *pszSrc, size_t uDataSize); @Input c the number of bytes to be copied @Return Pointer to the destination memory. */ /**************************************************************************/ +#if !defined(SERVICES_SC) +#define OSCachedMemCopyWMB(a,b,c) \ + do { \ + if ((c) != 0) \ + { \ + (void) memcpy((a), (b), (c)); \ + OSWriteMemoryBarrier(a); \ + } \ + } while (false) +#else #define OSCachedMemCopyWMB(a,b,c) \ do { \ (void) memcpy((a), (b), (c)); \ OSWriteMemoryBarrier(); \ - } while (0) - + } while (false) +#endif /* !defined(SERVICES_SC) */ #endif /* defined(__KERNEL__) */ /**************************************************************************/ /*! diff --git a/drivers/gpu/drm/img-rogue/include/public/powervr/img_drm_fourcc.h b/drivers/gpu/drm/img-rogue/include/public/powervr/img_drm_fourcc.h index 4856a8d11..5fd79a6c4 100644 --- a/drivers/gpu/drm/img-rogue/include/public/powervr/img_drm_fourcc.h +++ b/drivers/gpu/drm/img-rogue/include/public/powervr/img_drm_fourcc.h @@ -114,6 +114,9 @@ THE SOFTWARE. #define DRM_FORMAT_MOD_LINEAR fourcc_mod_code(NONE, 0) #endif +#define DRM_FORMAT_MOD_PVR_FBCDC_8x8_V1 fourcc_mod_code(PVR, 3) +#define DRM_FORMAT_MOD_PVR_FBCDC_16x4_V1 fourcc_mod_code(PVR, 9) + #define DRM_FORMAT_MOD_PVR_FBCDC_8x8_V7 fourcc_mod_code(PVR, 6) #define DRM_FORMAT_MOD_PVR_FBCDC_16x4_V7 fourcc_mod_code(PVR, 12) diff --git a/drivers/gpu/drm/img-rogue/include/pvr_debug.h b/drivers/gpu/drm/img-rogue/include/pvr_debug.h index 003afd490..56bbb13f1 100644 --- a/drivers/gpu/drm/img-rogue/include/pvr_debug.h +++ b/drivers/gpu/drm/img-rogue/include/pvr_debug.h @@ -119,7 +119,7 @@ __noreturn void klocwork_abort(void); * them. */ #if defined(__KLOCWORK__) -#define PVR_ASSERT(x) do { if (!(x)) {klocwork_abort();} } while (0) +#define PVR_ASSERT(x) do { if (!(x)) {klocwork_abort();} } while (false) #else /* ! __KLOCWORKS__ */ #if defined(_WIN32) @@ -133,7 +133,7 @@ __noreturn void klocwork_abort(void); __debugbreak(); \ } \ MSC_SUPPRESS_4127 \ - } while (0) + } while (false) #else @@ -152,7 +152,7 @@ __noreturn void klocwork_abort(void); "Debug assertion failed!"); \ WARN_ON(1); \ } \ - } while (0) + } while (false) #else /* defined(__linux__) && defined(__KERNEL__) */ @@ -177,14 +177,14 @@ PVRSRVDebugAssertFail(const IMG_CHAR *pszFile, { \ PVRSRVDebugAssertFail(__FILE__, __LINE__, #EXPR); \ } \ - } while (0) + } while (false) #endif /* defined(__linux__) && defined(__KERNEL__) */ #endif /* defined(_WIN32) */ #endif /* defined(__KLOCWORK__) */ #if defined(__KLOCWORK__) - #define PVR_DBG_BREAK do { klocwork_abort(); } while (0) + #define PVR_DBG_BREAK do { klocwork_abort(); } while (false) #else #if defined(WIN32) #define PVR_DBG_BREAK __debugbreak() /*!< Implementation of PVR_DBG_BREAK for (non-WinCE) Win32 */ @@ -214,8 +214,8 @@ PVRSRVDebugAssertFail(const IMG_CHAR *pszFile, * macros in a special way when the code is analysed by Klocwork avoids * them. */ - #if defined(__KLOCWORK__) - #define PVR_ASSERT(EXPR) do { if (!(EXPR)) {klocwork_abort();} } while (0) + #if defined(__KLOCWORK__) && !defined(SERVICES_SC) + #define PVR_ASSERT(EXPR) do { if (!(EXPR)) {klocwork_abort();} } while (false) #else #define PVR_ASSERT(EXPR) (void)(EXPR) /*!< Null Implementation of PVR_ASSERT (does nothing) */ #endif @@ -294,21 +294,21 @@ PVRSRVDebugAssertFail(const IMG_CHAR *pszFile, PVR_DPF((PVR_DBG_ERROR, "%s() failed (%s) in %s()", _call, PVRSRVGETERRORSTRING(_rc), __func__)); \ } \ MSC_SUPPRESS_4127\ - } while (0) + } while (false) #define PVR_WARN_IF_ERROR(_rc, _call) do \ { if (unlikely(_rc != PVRSRV_OK)) { \ PVR_DPF((PVR_DBG_WARNING, "%s() failed (%s) in %s()", _call, PVRSRVGETERRORSTRING(_rc), __func__)); \ } \ MSC_SUPPRESS_4127\ - } while (0) + } while (false) #define PVR_LOG_RETURN_IF_NOMEM(_expr, _call) do \ { if (unlikely(_expr == NULL)) { \ PVR_DPF((PVR_DBG_ERROR, "%s failed (PVRSRV_ERROR_OUT_OF_MEMORY) in %s()", _call, __func__)); \ return PVRSRV_ERROR_OUT_OF_MEMORY; } \ MSC_SUPPRESS_4127\ - } while (0) + } while (false) #define PVR_LOG_GOTO_IF_NOMEM(_expr, _err, _go) do \ { if (unlikely(_expr == NULL)) { \ @@ -316,70 +316,70 @@ PVRSRVDebugAssertFail(const IMG_CHAR *pszFile, _err = PVRSRV_ERROR_OUT_OF_MEMORY; \ goto _go; } \ MSC_SUPPRESS_4127\ - } while (0) + } while (false) #define PVR_LOG_RETURN_IF_ERROR(_rc, _call) do \ { if (unlikely(_rc != PVRSRV_OK)) { \ PVR_DPF((PVR_DBG_ERROR, "%s() failed (%s) in %s()", _call, PVRSRVGETERRORSTRING(_rc), __func__)); \ return _rc; } \ MSC_SUPPRESS_4127\ - } while (0) + } while (false) #define PVR_LOG_RETURN_VOID_IF_ERROR(_rc, _call) do \ { if (unlikely(_rc != PVRSRV_OK)) { \ PVR_DPF((PVR_DBG_ERROR, "%s() failed (%s) in %s()", _call, PVRSRVGETERRORSTRING(_rc), __func__)); \ return; } \ MSC_SUPPRESS_4127\ - } while (0) + } while (false) #define PVR_LOG_GOTO_IF_ERROR(_rc, _call, _go) do \ { if (unlikely(_rc != PVRSRV_OK)) { \ PVR_DPF((PVR_DBG_ERROR, "%s() failed (%s) in %s()", _call, PVRSRVGETERRORSTRING(_rc), __func__)); \ goto _go; } \ MSC_SUPPRESS_4127\ - } while (0) + } while (false) #define PVR_LOG_GOTO_WITH_ERROR(_call, _err, _rc, _go) do \ { PVR_DPF((PVR_DBG_ERROR, "%s() failed (%s) in %s()", _call, PVRSRVGETERRORSTRING(_rc), __func__)); \ _err = _rc; \ goto _go; \ MSC_SUPPRESS_4127\ - } while (0) + } while (false) #define PVR_LOG_IF_FALSE(_expr, _msg) do \ { if (unlikely(!(_expr))) { \ PVR_DPF((PVR_DBG_ERROR, "%s in %s()", _msg, __func__)); \ } \ MSC_SUPPRESS_4127\ - } while (0) + } while (false) #define PVR_LOG_RETURN_IF_FALSE(_expr, _msg, _rc) do \ { if (unlikely(!(_expr))) { \ PVR_DPF((PVR_DBG_ERROR, "%s in %s()", _msg, __func__)); \ return _rc; } \ MSC_SUPPRESS_4127\ - } while (0) + } while (false) #define PVR_LOG_RETURN_VOID_IF_FALSE(_expr, _msg) do \ { if (unlikely(!(_expr))) { \ PVR_DPF((PVR_DBG_ERROR, "%s in %s()", _msg, __func__)); \ return; } \ MSC_SUPPRESS_4127\ - } while (0) + } while (false) #define PVR_LOG_GOTO_IF_FALSE(_expr, _msg, _go) do \ { if (unlikely(!(_expr))) { \ PVR_DPF((PVR_DBG_ERROR, "%s in %s()", _msg, __func__)); \ goto _go; } \ MSC_SUPPRESS_4127\ - } while (0) + } while (false) #define PVR_LOG_RETURN_IF_INVALID_PARAM(_expr, _param) do \ { if (unlikely(!(_expr))) { \ PVR_DPF((PVR_DBG_ERROR, "%s invalid in %s()", _param, __func__)); \ return PVRSRV_ERROR_INVALID_PARAMS; } \ MSC_SUPPRESS_4127\ - } while (0) + } while (false) #define PVR_LOG_GOTO_IF_INVALID_PARAM(_expr, _err, _go) do \ { if (unlikely(!(_expr))) { \ @@ -387,7 +387,7 @@ PVRSRVDebugAssertFail(const IMG_CHAR *pszFile, _err = PVRSRV_ERROR_INVALID_PARAMS; \ goto _go; } \ MSC_SUPPRESS_4127\ - } while (0) + } while (false) #define PVR_LOG_MSG(_lvl, _msg) \ PVR_DPF((_lvl, ("In %s() "_msg), __func__)) @@ -400,42 +400,42 @@ PVRSRVDebugAssertFail(const IMG_CHAR *pszFile, PVR_DPF((_lvl, ("In %s() "_msg), __func__, __VA_ARGS__)); \ } \ MSC_SUPPRESS_4127\ - } while (0) + } while (false) #define PVR_LOG_IF_FALSE_VA(_lvl, _expr, _msg, ...) do \ { if (unlikely(!(_expr))) { \ PVR_DPF((_lvl, ("In %s() "_msg), __func__, __VA_ARGS__)); \ } \ MSC_SUPPRESS_4127\ - } while (0) + } while (false) #define PVR_LOG_RETURN_IF_ERROR_VA(_rc, _msg, ...) do \ { if (unlikely(_rc != PVRSRV_OK)) { \ PVR_DPF((PVR_DBG_ERROR, ("In %s() "_msg), __func__, __VA_ARGS__)); \ return _rc; \ } MSC_SUPPRESS_4127\ - } while (0) + } while (false) #define PVR_LOG_GOTO_IF_ERROR_VA(_rc, _go, _msg, ...) do \ { if (unlikely(_rc != PVRSRV_OK)) { \ PVR_DPF((PVR_DBG_ERROR, ("In %s() "_msg), __func__, __VA_ARGS__)); \ goto _go; \ } MSC_SUPPRESS_4127\ - } while (0) + } while (false) #define PVR_LOG_RETURN_IF_FALSE_VA(_expr, _rc, _msg, ...) do \ { if (unlikely(!(_expr))) { \ PVR_DPF((PVR_DBG_ERROR, ("At %s: "_msg), __func__, __VA_ARGS__)); \ return _rc; \ } MSC_SUPPRESS_4127\ - } while (0) + } while (false) #define PVR_LOG_GOTO_IF_FALSE_VA(_expr, _go, _msg, ...) do \ { if (unlikely(!(_expr))) { \ PVR_DPF((PVR_DBG_ERROR, ("In %s() "_msg), __func__, __VA_ARGS__)); \ goto _go; \ } MSC_SUPPRESS_4127\ - } while (0) + } while (false) #else /* defined(PVRSRV_NEED_PVR_DPF) */ @@ -450,27 +450,27 @@ PVRSRVDebugAssertFail(const IMG_CHAR *pszFile, #define PVR_LOG_IF_ERROR_VA(_lvl, _rc, _msg, ...) (void)(_rc) #define PVR_LOG_IF_FALSE_VA(_lvl, _expr, _msg, ...) (void)(_expr) - #define PVR_LOG_RETURN_IF_NOMEM(_expr, _call) do { if (unlikely(_expr == NULL)) { return PVRSRV_ERROR_OUT_OF_MEMORY; } MSC_SUPPRESS_4127 } while (0) - #define PVR_LOG_GOTO_IF_NOMEM(_expr, _err, _go) do { if (unlikely(_expr == NULL)) { _err = PVRSRV_ERROR_OUT_OF_MEMORY; goto _go; } MSC_SUPPRESS_4127 } while (0) + #define PVR_LOG_RETURN_IF_NOMEM(_expr, _call) do { if (unlikely(_expr == NULL)) { return PVRSRV_ERROR_OUT_OF_MEMORY; } MSC_SUPPRESS_4127 } while (false) + #define PVR_LOG_GOTO_IF_NOMEM(_expr, _err, _go) do { if (unlikely(_expr == NULL)) { _err = PVRSRV_ERROR_OUT_OF_MEMORY; goto _go; } MSC_SUPPRESS_4127 } while (false) - #define PVR_LOG_RETURN_IF_ERROR(_rc, _call) do { if (unlikely(_rc != PVRSRV_OK)) { return (_rc); } MSC_SUPPRESS_4127 } while (0) - #define PVR_LOG_RETURN_IF_ERROR_VA(_rc, _msg, ...) do { if (unlikely(_rc != PVRSRV_OK)) { return (_rc); } MSC_SUPPRESS_4127 } while (0) - #define PVR_LOG_RETURN_VOID_IF_ERROR(_rc, _call) do { if (unlikely(_rc != PVRSRV_OK)) { return; } MSC_SUPPRESS_4127 } while (0) + #define PVR_LOG_RETURN_IF_ERROR(_rc, _call) do { if (unlikely(_rc != PVRSRV_OK)) { return (_rc); } MSC_SUPPRESS_4127 } while (false) + #define PVR_LOG_RETURN_IF_ERROR_VA(_rc, _msg, ...) do { if (unlikely(_rc != PVRSRV_OK)) { return (_rc); } MSC_SUPPRESS_4127 } while (false) + #define PVR_LOG_RETURN_VOID_IF_ERROR(_rc, _call) do { if (unlikely(_rc != PVRSRV_OK)) { return; } MSC_SUPPRESS_4127 } while (false) - #define PVR_LOG_GOTO_IF_ERROR(_rc, _call, _go) do { if (unlikely(_rc != PVRSRV_OK)) { goto _go; } MSC_SUPPRESS_4127 } while (0) - #define PVR_LOG_GOTO_IF_ERROR_VA(_rc, _go, _msg, ...) do { if (unlikely(_rc != PVRSRV_OK)) { goto _go; } MSC_SUPPRESS_4127 } while (0) - #define PVR_LOG_GOTO_WITH_ERROR(_call, _err, _rc, _go) do { _err = _rc; goto _go; MSC_SUPPRESS_4127 } while (0) + #define PVR_LOG_GOTO_IF_ERROR(_rc, _call, _go) do { if (unlikely(_rc != PVRSRV_OK)) { goto _go; } MSC_SUPPRESS_4127 } while (false) + #define PVR_LOG_GOTO_IF_ERROR_VA(_rc, _go, _msg, ...) do { if (unlikely(_rc != PVRSRV_OK)) { goto _go; } MSC_SUPPRESS_4127 } while (false) + #define PVR_LOG_GOTO_WITH_ERROR(_call, _err, _rc, _go) do { _err = _rc; goto _go; MSC_SUPPRESS_4127 } while (false) #define PVR_LOG_IF_FALSE(_expr, _msg) (void)(_expr) - #define PVR_LOG_RETURN_IF_FALSE(_expr, _msg, _rc) do { if (unlikely(!(_expr))) { return (_rc); } MSC_SUPPRESS_4127 } while (0) - #define PVR_LOG_RETURN_IF_FALSE_VA(_expr, _rc, _msg, ...) do { if (unlikely(!(_expr))) { return (_rc); } MSC_SUPPRESS_4127 } while (0) + #define PVR_LOG_RETURN_IF_FALSE(_expr, _msg, _rc) do { if (unlikely(!(_expr))) { return (_rc); } MSC_SUPPRESS_4127 } while (false) + #define PVR_LOG_RETURN_IF_FALSE_VA(_expr, _rc, _msg, ...) do { if (unlikely(!(_expr))) { return (_rc); } MSC_SUPPRESS_4127 } while (false) - #define PVR_LOG_RETURN_VOID_IF_FALSE(_expr, _msg) do { if (unlikely(!(_expr))) { return; } MSC_SUPPRESS_4127 } while (0) - #define PVR_LOG_GOTO_IF_FALSE(_expr, _msg, _go) do { if (unlikely(!(_expr))) { goto _go; } MSC_SUPPRESS_4127 } while (0) - #define PVR_LOG_GOTO_IF_FALSE_VA(_expr, _go, _msg, ...) do { if (unlikely(!(_expr))) { goto _go; } MSC_SUPPRESS_4127 } while (0) + #define PVR_LOG_RETURN_VOID_IF_FALSE(_expr, _msg) do { if (unlikely(!(_expr))) { return; } MSC_SUPPRESS_4127 } while (false) + #define PVR_LOG_GOTO_IF_FALSE(_expr, _msg, _go) do { if (unlikely(!(_expr))) { goto _go; } MSC_SUPPRESS_4127 } while (false) + #define PVR_LOG_GOTO_IF_FALSE_VA(_expr, _go, _msg, ...) do { if (unlikely(!(_expr))) { goto _go; } MSC_SUPPRESS_4127 } while (false) - #define PVR_LOG_RETURN_IF_INVALID_PARAM(_expr, _param) do { if (unlikely(!(_expr))) { return PVRSRV_ERROR_INVALID_PARAMS; } MSC_SUPPRESS_4127 } while (0) - #define PVR_LOG_GOTO_IF_INVALID_PARAM(_expr, _err, _go) do { if (unlikely(!(_expr))) { _err = PVRSRV_ERROR_INVALID_PARAMS; goto _go; } MSC_SUPPRESS_4127 } while (0) + #define PVR_LOG_RETURN_IF_INVALID_PARAM(_expr, _param) do { if (unlikely(!(_expr))) { return PVRSRV_ERROR_INVALID_PARAMS; } MSC_SUPPRESS_4127 } while (false) + #define PVR_LOG_GOTO_IF_INVALID_PARAM(_expr, _err, _go) do { if (unlikely(!(_expr))) { _err = PVRSRV_ERROR_INVALID_PARAMS; goto _go; } MSC_SUPPRESS_4127 } while (false) #undef PVR_DPF_FUNCTION_TRACE_ON @@ -520,8 +520,10 @@ IMG_EXPORT void IMG_CALLCONV PVRSRVDebugPrintf(IMG_UINT32 ui32DebugLevel, */ /**************************************************************************/ IMG_EXPORT void IMG_CALLCONV PVRSRVDebugPrintfDumpCCB(void); +#if !defined(DOXYGEN) #define PVR_DPF_FUNC__(lvl, message, ...) PVR_DPF((lvl, "%s: " message, __func__, ##__VA_ARGS__)) #define PVR_DPF_FUNC(x) PVR_DPF_FUNC__ x +#endif /*!defined(DOXYGEN) */ /* Note: Use only when a log message due to the error absolutely should not * be printed. Otherwise use PVR_LOG_RETURN_IF_ERROR macro. @@ -530,7 +532,7 @@ IMG_EXPORT void IMG_CALLCONV PVRSRVDebugPrintfDumpCCB(void); { if (unlikely(_rc != PVRSRV_OK)) { \ return _rc; } \ MSC_SUPPRESS_4127 \ - } while (0) + } while (false) /* Note: Use only when a log message due to the error absolutely should not * be printed. Otherwise use PVR_LOG_RETURN_IF_FALSE macro. @@ -539,7 +541,7 @@ IMG_EXPORT void IMG_CALLCONV PVRSRVDebugPrintfDumpCCB(void); { if (unlikely(!(_expr))) { \ return _rc; } \ MSC_SUPPRESS_4127 \ - } while (0) + } while (false) /* Note: Use only when a log message due to the error absolutely should not * be printed. Otherwise use PVR_LOG_RETURN_IF_INVALID_PARAM macro. @@ -548,7 +550,7 @@ IMG_EXPORT void IMG_CALLCONV PVRSRVDebugPrintfDumpCCB(void); { if (unlikely(!(_expr))) { \ return PVRSRV_ERROR_INVALID_PARAMS; } \ MSC_SUPPRESS_4127 \ - } while (0) + } while (false) /* Note: Use only when a log message due to the error absolutely should not * be printed. Otherwise use PVR_LOG_RETURN_IF_NOMEM macro. @@ -557,7 +559,7 @@ IMG_EXPORT void IMG_CALLCONV PVRSRVDebugPrintfDumpCCB(void); { if (unlikely(!(_expr))) { \ return PVRSRV_ERROR_OUT_OF_MEMORY; } \ MSC_SUPPRESS_4127 \ - } while (0) + } while (false) /* Note: Use only when a log message due to the error absolutely should not * be printed. Otherwise use PVR_LOG_GOTO_IF_NOMEM macro. @@ -567,7 +569,7 @@ IMG_EXPORT void IMG_CALLCONV PVRSRVDebugPrintfDumpCCB(void); _err = PVRSRV_ERROR_OUT_OF_MEMORY; \ goto _go; } \ MSC_SUPPRESS_4127 \ - } while (0) + } while (false) /* Note: Use only when a log message due to the error absolutely should not * be printed. Otherwise use PVR_LOG_GOTO_IF_INVALID_PARAM macro. @@ -577,7 +579,7 @@ IMG_EXPORT void IMG_CALLCONV PVRSRVDebugPrintfDumpCCB(void); _err = PVRSRV_ERROR_INVALID_PARAMS; \ goto _go; } \ MSC_SUPPRESS_4127 \ - } while (0) + } while (false) /* Note: Use only when a log message due to the error absolutely should not * be printed. Otherwise use PVR_LOG_GOTO_IF_FALSE macro. @@ -586,7 +588,7 @@ IMG_EXPORT void IMG_CALLCONV PVRSRVDebugPrintfDumpCCB(void); { if (unlikely(!(_expr))) { \ goto _go; } \ MSC_SUPPRESS_4127 \ - } while (0) + } while (false) /* Note: Use only when a log message due to the error absolutely should not * be printed. Otherwise use PVR_LOG_GOTO_IF_ERROR macro. @@ -595,7 +597,7 @@ IMG_EXPORT void IMG_CALLCONV PVRSRVDebugPrintfDumpCCB(void); { if (unlikely(_rc != PVRSRV_OK)) { \ goto _go; } \ MSC_SUPPRESS_4127\ - } while (0) + } while (false) /* Note: Use only when a log message due to the error absolutely should not * be printed. Otherwise use PVR_LOG_GOTO_WITH_ERROR macro. @@ -603,7 +605,7 @@ IMG_EXPORT void IMG_CALLCONV PVRSRVDebugPrintfDumpCCB(void); #define PVR_GOTO_WITH_ERROR(_err, _rc, _go) do \ { _err = _rc; goto _go; \ MSC_SUPPRESS_4127 \ - } while (0) + } while (false) /*! @cond Doxygen_Suppress */ #if defined(PVR_DPF_FUNCTION_TRACE_ON) @@ -615,19 +617,19 @@ IMG_EXPORT void IMG_CALLCONV PVRSRVDebugPrintfDumpCCB(void); PVR_DPF((PVR_DBG_CALLTRACE, "|-> %s:%d entered (0x%lx)", __func__, __LINE__, ((unsigned long)p1))) #define PVR_DPF_RETURN_RC(a) \ - do { int _r = (a); PVR_DPF((PVR_DBG_CALLTRACE, "<-| %s:%d returned %d", __func__, __LINE__, (_r))); return (_r); MSC_SUPPRESS_4127 } while (0) + do { int _r = (a); PVR_DPF((PVR_DBG_CALLTRACE, "<-| %s:%d returned %d", __func__, __LINE__, (_r))); return (_r); MSC_SUPPRESS_4127 } while (false) #define PVR_DPF_RETURN_RC1(a,p1) \ - do { int _r = (a); PVR_DPF((PVR_DBG_CALLTRACE, "<-| %s:%d returned %d (0x%lx)", __func__, __LINE__, (_r), ((unsigned long)p1))); return (_r); MSC_SUPPRESS_4127 } while (0) + do { int _r = (a); PVR_DPF((PVR_DBG_CALLTRACE, "<-| %s:%d returned %d (0x%lx)", __func__, __LINE__, (_r), ((unsigned long)p1))); return (_r); MSC_SUPPRESS_4127 } while (false) #define PVR_DPF_RETURN_VAL(a) \ - do { PVR_DPF((PVR_DBG_CALLTRACE, "<-| %s:%d returned with value", __func__, __LINE__)); return (a); MSC_SUPPRESS_4127 } while (0) + do { PVR_DPF((PVR_DBG_CALLTRACE, "<-| %s:%d returned with value", __func__, __LINE__)); return (a); MSC_SUPPRESS_4127 } while (false) #define PVR_DPF_RETURN_OK \ - do { PVR_DPF((PVR_DBG_CALLTRACE, "<-| %s:%d returned ok", __func__, __LINE__)); return PVRSRV_OK; MSC_SUPPRESS_4127 } while (0) + do { PVR_DPF((PVR_DBG_CALLTRACE, "<-| %s:%d returned ok", __func__, __LINE__)); return PVRSRV_OK; MSC_SUPPRESS_4127 } while (false) #define PVR_DPF_RETURN \ - do { PVR_DPF((PVR_DBG_CALLTRACE, "<-| %s:%d returned", __func__, __LINE__)); return; MSC_SUPPRESS_4127 } while (0) + do { PVR_DPF((PVR_DBG_CALLTRACE, "<-| %s:%d returned", __func__, __LINE__)); return; MSC_SUPPRESS_4127 } while (false) #if !defined(DEBUG) #error PVR DPF Function trace enabled in release build, rectify @@ -742,7 +744,7 @@ IMG_EXPORT void IMG_CALLCONV PVRSRVTrace(const IMG_CHAR* pszFormat, ... ) #define PVR_DBG_FILELINE_ARG , pszaFile, ui32Line #define PVR_DBG_FILELINE_FMT " %s:%u" #define PVR_DBG_FILELINE_UNREF() do { PVR_UNREFERENCED_PARAMETER(pszaFile); \ - PVR_UNREFERENCED_PARAMETER(ui32Line); } while (0) + PVR_UNREFERENCED_PARAMETER(ui32Line); } while (false) #else #define PVR_DBG_FILELINE #define PVR_DBG_FILELINE_PARAM @@ -840,7 +842,7 @@ IMG_EXPORT void IMG_CALLCONV PVRSRVTrace(const IMG_CHAR* pszFormat, ... ) @brief Goes to a label if expression is false. @def PVR_GOTO_IF_FALSE - @def Goes to a label if expression is false. + @brief Goes to a label if expression is false. @def PVR_GOTO_IF_ERROR @brief Goes to a label if the error code is different than PVRSRV_OK; @@ -852,6 +854,29 @@ IMG_EXPORT void IMG_CALLCONV PVRSRVTrace(const IMG_CHAR* pszFormat, ... ) @brief Prints message to a log unconditionally. This macro will print messages only if PVRSRV_NEED_PVR_LOG macro is defined. + @def PVR_LOG_MSG + @brief Prints message to a log with the given log-level. + + @def PVR_LOG_VA + @brief Prints message with var-args to a log with the given log-level. + + @def PVR_LOG_IF_ERROR_VA + @brief Prints message with var-args to a log if the error code is different than PVRSRV_OK. + + @def PVR_LOG_IF_FALSE_VA + @brief Prints message with var-args if expression is false. + + @def PVR_LOG_RETURN_IF_ERROR_VA + @brief Prints message with var-args to a log and returns the error code. + + @def PVR_LOG_GOTO_IF_ERROR_VA + @brief Prints message with var-args to a log and goes to a label if the error code is different than PVRSRV_OK. + + @def PVR_LOG_RETURN_IF_FALSE_VA + @brief Logs the error message with var-args if the expression is false and returns the error code. + + @def PVR_LOG_GOTO_IF_FALSE_VA + @brief Logs the error message with var-args and goes to a label if the expression is false. @def PVR_TRACE_EMPTY_LINE @brief Prints empty line to a log (PVRSRV_NEED_PVR_LOG must be defined). diff --git a/drivers/gpu/drm/img-rogue/include/pvrsrv_errors.h b/drivers/gpu/drm/img-rogue/include/pvrsrv_errors.h index d571d6279..59b9cfe84 100644 --- a/drivers/gpu/drm/img-rogue/include/pvrsrv_errors.h +++ b/drivers/gpu/drm/img-rogue/include/pvrsrv_errors.h @@ -406,3 +406,5 @@ PVRE(PVRSRV_ERROR_TOO_MANY_SYNCS) PVRE(PVRSRV_ERROR_ION_NO_CLIENT) PVRE(PVRSRV_ERROR_ION_FAILED_TO_ALLOC) PVRE(PVRSRV_ERROR_PDUMP_CAPTURE_BOUND_TO_ANOTHER_DEVICE) +PVRE(PVRSRV_ERROR_REFCOUNT_OVERFLOW) +PVRE(PVRSRV_ERROR_OUT_OF_RANGE) diff --git a/drivers/gpu/drm/img-rogue/include/pvrsrv_memalloc_physheap.h b/drivers/gpu/drm/img-rogue/include/pvrsrv_memalloc_physheap.h index f002a1af3..1072ba857 100644 --- a/drivers/gpu/drm/img-rogue/include/pvrsrv_memalloc_physheap.h +++ b/drivers/gpu/drm/img-rogue/include/pvrsrv_memalloc_physheap.h @@ -56,41 +56,115 @@ CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. * * NOTE: Enum order important, table in physheap.c must change if order changed. */ -typedef enum -{ - /* Services client accessible heaps */ - PVRSRV_PHYS_HEAP_DEFAULT = 0, /* default phys heap for device memory allocations */ - PVRSRV_PHYS_HEAP_GPU_LOCAL = 1, /* used for buffers with more GPU access than CPU */ - PVRSRV_PHYS_HEAP_CPU_LOCAL = 2, /* used for buffers with more CPU access than GPU */ - PVRSRV_PHYS_HEAP_GPU_PRIVATE = 3, /* used for buffers that only required GPU read/write access, not visible to the CPU. */ +typedef IMG_UINT32 PVRSRV_PHYS_HEAP; +/* Services client accessible heaps */ +#define PVRSRV_PHYS_HEAP_DEFAULT 0U /* default phys heap for device memory allocations */ +#define PVRSRV_PHYS_HEAP_GPU_LOCAL 1U /* used for buffers with more GPU access than CPU */ +#define PVRSRV_PHYS_HEAP_CPU_LOCAL 2U /* used for buffers with more CPU access than GPU */ +#define PVRSRV_PHYS_HEAP_GPU_PRIVATE 3U /* used for buffers that only required GPU read/write access, not visible to the CPU. */ - /* Services internal heaps */ - PVRSRV_PHYS_HEAP_FW_MAIN = 4, /* runtime data, e.g. CCBs, sync objects */ - PVRSRV_PHYS_HEAP_EXTERNAL = 5, /* used by some PMR import/export factories where the physical memory heap is not managed by the pvrsrv driver */ - PVRSRV_PHYS_HEAP_GPU_COHERENT = 6, /* used for a cache coherent region */ - PVRSRV_PHYS_HEAP_GPU_SECURE = 7, /* used by security validation */ - PVRSRV_PHYS_HEAP_FW_CONFIG = 8, /* subheap of FW_MAIN, configuration data for FW init */ - PVRSRV_PHYS_HEAP_FW_CODE = 9, /* used by security validation or dedicated fw */ - PVRSRV_PHYS_HEAP_FW_PRIV_DATA = 10, /* internal FW data (like the stack, FW control data structures, etc.) */ - PVRSRV_PHYS_HEAP_FW_PREMAP0 = 11, /* Host OS premap fw heap */ - PVRSRV_PHYS_HEAP_FW_PREMAP1 = 12, /* Guest OS 1 premap fw heap */ - PVRSRV_PHYS_HEAP_FW_PREMAP2 = 13, /* Guest OS 2 premap fw heap */ - PVRSRV_PHYS_HEAP_FW_PREMAP3 = 14, /* Guest OS 3 premap fw heap */ - PVRSRV_PHYS_HEAP_FW_PREMAP4 = 15, /* Guest OS 4 premap fw heap */ - PVRSRV_PHYS_HEAP_FW_PREMAP5 = 16, /* Guest OS 5 premap fw heap */ - PVRSRV_PHYS_HEAP_FW_PREMAP6 = 17, /* Guest OS 6 premap fw heap */ - PVRSRV_PHYS_HEAP_FW_PREMAP7 = 18, /* Guest OS 7 premap fw heap */ - PVRSRV_PHYS_HEAP_LAST -} PVRSRV_PHYS_HEAP; +#define HEAPSTR(x) #x +static inline const IMG_CHAR *PVRSRVGetClientPhysHeapName(PVRSRV_PHYS_HEAP ePhysHeapID) +{ + switch (ePhysHeapID) + { + case PVRSRV_PHYS_HEAP_DEFAULT: + return HEAPSTR(PVRSRV_PHYS_HEAP_DEFAULT); + case PVRSRV_PHYS_HEAP_GPU_LOCAL: + return HEAPSTR(PVRSRV_PHYS_HEAP_GPU_LOCAL); + case PVRSRV_PHYS_HEAP_CPU_LOCAL: + return HEAPSTR(PVRSRV_PHYS_HEAP_CPU_LOCAL); + case PVRSRV_PHYS_HEAP_GPU_PRIVATE: + return HEAPSTR(PVRSRV_PHYS_HEAP_GPU_PRIVATE); + default: + return "Unknown Heap"; + } +} + +/* Services internal heaps */ +#define PVRSRV_PHYS_HEAP_FW_MAIN 4U /* runtime data, e.g. CCBs, sync objects */ +#define PVRSRV_PHYS_HEAP_EXTERNAL 5U /* used by some PMR import/export factories where the physical memory heap is not managed by the pvrsrv driver */ +#define PVRSRV_PHYS_HEAP_GPU_COHERENT 6U /* used for a cache coherent region */ +#define PVRSRV_PHYS_HEAP_GPU_SECURE 7U /* used by security validation */ +#define PVRSRV_PHYS_HEAP_FW_CONFIG 8U /* subheap of FW_MAIN, configuration data for FW init */ +#define PVRSRV_PHYS_HEAP_FW_CODE 9U /* used by security validation or dedicated fw */ +#define PVRSRV_PHYS_HEAP_FW_PRIV_DATA 10U /* internal FW data (like the stack, FW control data structures, etc.) */ +#define PVRSRV_PHYS_HEAP_FW_PREMAP0 11U /* Host OS premap fw heap */ +#define PVRSRV_PHYS_HEAP_FW_PREMAP1 12U /* Guest OS 1 premap fw heap */ +#define PVRSRV_PHYS_HEAP_FW_PREMAP2 13U /* Guest OS 2 premap fw heap */ +#define PVRSRV_PHYS_HEAP_FW_PREMAP3 14U /* Guest OS 3 premap fw heap */ +#define PVRSRV_PHYS_HEAP_FW_PREMAP4 15U /* Guest OS 4 premap fw heap */ +#define PVRSRV_PHYS_HEAP_FW_PREMAP5 16U /* Guest OS 5 premap fw heap */ +#define PVRSRV_PHYS_HEAP_FW_PREMAP6 17U /* Guest OS 6 premap fw heap */ +#define PVRSRV_PHYS_HEAP_FW_PREMAP7 18U /* Guest OS 7 premap fw heap */ +#define PVRSRV_PHYS_HEAP_LAST 19U static_assert(PVRSRV_PHYS_HEAP_LAST <= (0x1FU + 1U), "Ensure enum fits in memalloc flags bitfield."); -typedef struct _PHYS_HEAP_MEM_STATS_ +/*! Type conveys the class of physical heap to instantiate within Services + * for the physical pool of memory. */ +typedef enum _PHYS_HEAP_TYPE_ +{ + PHYS_HEAP_TYPE_UNKNOWN = 0, /*!< Not a valid value for any config */ + PHYS_HEAP_TYPE_UMA, /*!< Heap represents OS managed physical memory heap + i.e. system RAM. Unified Memory Architecture + physmem_osmem PMR factory */ + PHYS_HEAP_TYPE_LMA, /*!< Heap represents physical memory pool managed by + Services i.e. carve out from system RAM or local + card memory. Local Memory Architecture + physmem_lma PMR factory */ +#if defined(__KERNEL__) + PHYS_HEAP_TYPE_DMA, /*!< Heap represents a physical memory pool managed by + Services, alias of LMA and is only used on + VZ non-native system configurations for + a heap used for PHYS_HEAP_USAGE_FW_MAIN tagged + buffers */ +#if defined(SUPPORT_WRAP_EXTMEMOBJECT) + PHYS_HEAP_TYPE_WRAP, /*!< Heap used to group UM buffers given + to Services. Integrity OS port only. */ +#endif +#endif +} PHYS_HEAP_TYPE; + +/* Defines used when interpreting the ui32PhysHeapFlags in PHYS_HEAP_MEM_STATS + 0x000000000000dttt + d = is this the default heap? (1=yes, 0=no) + ttt = heap type (000 = PHYS_HEAP_TYPE_UNKNOWN, + 001 = PHYS_HEAP_TYPE_UMA, + 010 = PHYS_HEAP_TYPE_LMA, + 011 = PHYS_HEAP_TYPE_DMA) +*/ +#define PVRSRV_PHYS_HEAP_FLAGS_TYPE_MASK (0x7U << 0) +#define PVRSRV_PHYS_HEAP_FLAGS_IS_DEFAULT (0x1U << 7) + +typedef struct PHYS_HEAP_MEM_STATS_TAG { - IMG_UINT64 ePhysHeapID; IMG_UINT64 ui64TotalSize; IMG_UINT64 ui64FreeSize; + IMG_UINT32 ui32PhysHeapFlags; }PHYS_HEAP_MEM_STATS, *PHYS_HEAP_MEM_STATS_PTR; +typedef struct PHYS_HEAP_MEM_STATS_PKD_TAG +{ + IMG_UINT64 ui64TotalSize; + IMG_UINT64 ui64FreeSize; + IMG_UINT32 ui32PhysHeapFlags; + IMG_UINT32 ui32Dummy; +}PHYS_HEAP_MEM_STATS_PKD, *PHYS_HEAP_MEM_STATS_PKD_PTR; + +static inline const IMG_CHAR *PVRSRVGetClientPhysHeapTypeName(PHYS_HEAP_TYPE ePhysHeapType) +{ + switch (ePhysHeapType) + { + case PHYS_HEAP_TYPE_UMA: + return HEAPSTR(PHYS_HEAP_TYPE_UMA); + case PHYS_HEAP_TYPE_LMA: + return HEAPSTR(PHYS_HEAP_TYPE_LMA); + default: + return "Unknown Heap Type"; + } +} +#undef HEAPSTR + #endif /* PVRSRV_MEMALLOC_PHYSHEAP_H */ diff --git a/drivers/gpu/drm/img-rogue/include/pvrsrv_memallocflags.h b/drivers/gpu/drm/img-rogue/include/pvrsrv_memallocflags.h index 28a4c018f..3b87dbf49 100644 --- a/drivers/gpu/drm/img-rogue/include/pvrsrv_memallocflags.h +++ b/drivers/gpu/drm/img-rogue/include/pvrsrv_memallocflags.h @@ -58,7 +58,7 @@ CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. typedef IMG_UINT64 PVRSRV_MEMALLOCFLAGS_T; #define PVRSRV_MEMALLOCFLAGS_FMTSPEC IMG_UINT64_FMTSPECx -#if defined(__KERNEL__) || defined(SERVICES_SC) +#if defined(__KERNEL__) #include "pvrsrv_memallocflags_internal.h" #endif /* __KERNEL__ */ @@ -538,7 +538,7 @@ typedef IMG_UINT64 PVRSRV_MEMALLOCFLAGS_T; /*! Indicates the particular memory that's being allocated is sparse and the sparse regions should not be backed by dummy page -*/ + */ #define PVRSRV_MEMALLOCFLAG_SPARSE_NO_DUMMY_BACKING (1ULL << 18) /*! @@ -549,9 +549,12 @@ typedef IMG_UINT64 PVRSRV_MEMALLOCFLAGS_T; #define PVRSRV_IS_SPARSE_DUMMY_BACKING_REQUIRED(uiFlags) (((uiFlags) & PVRSRV_MEMALLOCFLAG_SPARSE_NO_DUMMY_BACKING) == 0U) /*! - Services is going to clean the cache for the allocated memory. - For performance reasons avoid usage if allocation is written to by the - CPU anyway before the next GPU kick. + Used to force Services to carry out at least one CPU cache invalidate on a + CPU cached buffer during allocation of the memory. Applicable to incoherent + systems, it must be used for buffers which are CPU cached and which will not + be 100% written to by the CPU before the GPU accesses it. For performance + reasons, avoid usage if the whole buffer that is allocated is written to by + the CPU anyway before the next GPU kick, or if the system is coherent. */ #define PVRSRV_MEMALLOCFLAG_CPU_CACHE_CLEAN (1ULL<<19) @@ -570,7 +573,7 @@ typedef IMG_UINT64 PVRSRV_MEMALLOCFLAGS_T; by zero page at the time of mapping. The zero backed page is always with read only attribute irrespective of its original attributes. -*/ + */ #define PVRSRV_MEMALLOCFLAG_SPARSE_ZERO_BACKING (1ULL << 20) #define PVRSRV_IS_SPARSE_ZERO_BACKING_REQUIRED(uiFlags) (((uiFlags) & \ PVRSRV_MEMALLOCFLAG_SPARSE_ZERO_BACKING) == PVRSRV_MEMALLOCFLAG_SPARSE_ZERO_BACKING) @@ -650,8 +653,10 @@ typedef IMG_UINT64 PVRSRV_MEMALLOCFLAGS_T; */ #define PVRSRV_CHECK_POISON_ON_ALLOC(uiFlags) (((uiFlags) & PVRSRV_MEMALLOCFLAG_POISON_ON_ALLOC) != 0U) +#if defined(DEBUG) || defined(SERVICES_SC) /*! - Causes memory to be trashed when freed, as a lazy man's security measure. + Causes memory to be trashed when freed, used when debugging only, not to be used + as a security measure. */ #define PVRSRV_MEMALLOCFLAG_POISON_ON_FREE (1ULL<<29) @@ -661,6 +666,7 @@ typedef IMG_UINT64 PVRSRV_MEMALLOCFLAGS_T; @Return True if the flag is set, false otherwise */ #define PVRSRV_CHECK_POISON_ON_FREE(uiFlags) (((uiFlags) & PVRSRV_MEMALLOCFLAG_POISON_ON_FREE) != 0U) +#endif /* DEBUG */ /*! Avoid address alignment to a CPU or GPU cache line size. @@ -822,20 +828,27 @@ typedef IMG_UINT64 PVRSRV_MEMALLOCFLAGS_T; * Trusted device mask -- Flags in the mask are allowed for trusted device * because the driver cannot access the memory */ +#if defined(DEBUG) || defined(SERVICES_SC) #define PVRSRV_MEMALLOCFLAGS_TDFWMASK ~(PVRSRV_MEMALLOCFLAG_KERNEL_CPU_MAPPABLE | \ PVRSRV_MEMALLOCFLAG_ZERO_ON_ALLOC | \ PVRSRV_MEMALLOCFLAG_POISON_ON_ALLOC | \ - PVRSRV_MEMALLOCFLAG_POISON_ON_FREE | \ + PVRSRV_MEMALLOCFLAG_POISON_ON_FREE | \ PVRSRV_MEMALLOCFLAGS_CPU_MMUFLAGSMASK | \ PVRSRV_MEMALLOCFLAG_SPARSE_NO_DUMMY_BACKING) - +#else +#define PVRSRV_MEMALLOCFLAGS_TDFWMASK ~(PVRSRV_MEMALLOCFLAG_KERNEL_CPU_MAPPABLE | \ + PVRSRV_MEMALLOCFLAG_ZERO_ON_ALLOC | \ + PVRSRV_MEMALLOCFLAG_POISON_ON_ALLOC | \ + PVRSRV_MEMALLOCFLAGS_CPU_MMUFLAGSMASK | \ + PVRSRV_MEMALLOCFLAG_SPARSE_NO_DUMMY_BACKING) +#endif /*! PMR flags mask -- for internal services use only. This is the set of flags that will be passed down and stored with the PMR, this also includes the MMU flags which the PMR has to pass down to mm_common.c at PMRMap time. */ - +#if defined(DEBUG) || defined(SERVICES_SC) #define PVRSRV_MEMALLOCFLAGS_PMRFLAGSMASK (PVRSRV_MEMALLOCFLAG_DEVICE_FLAGS_MASK | \ PVRSRV_MEMALLOCFLAG_CPU_CACHE_CLEAN | \ PVRSRV_MEMALLOCFLAG_KERNEL_CPU_MAPPABLE | \ @@ -848,8 +861,23 @@ typedef IMG_UINT64 PVRSRV_MEMALLOCFLAGS_T; PVRSRV_MEMALLOCFLAG_NO_OSPAGES_ON_ALLOC | \ PVRSRV_MEMALLOCFLAG_SPARSE_NO_DUMMY_BACKING | \ PVRSRV_MEMALLOCFLAG_SPARSE_ZERO_BACKING | \ - PVRSRV_MEMALLOCFLAG_VAL_SHARED_BUFFER | \ + PVRSRV_MEMALLOCFLAG_VAL_SHARED_BUFFER | \ PVRSRV_PHYS_HEAP_HINT_MASK) +#else +#define PVRSRV_MEMALLOCFLAGS_PMRFLAGSMASK (PVRSRV_MEMALLOCFLAG_DEVICE_FLAGS_MASK | \ + PVRSRV_MEMALLOCFLAG_CPU_CACHE_CLEAN | \ + PVRSRV_MEMALLOCFLAG_KERNEL_CPU_MAPPABLE | \ + PVRSRV_MEMALLOCFLAG_ZERO_ON_ALLOC | \ + PVRSRV_MEMALLOCFLAG_SVM_ALLOC | \ + PVRSRV_MEMALLOCFLAG_POISON_ON_ALLOC | \ + PVRSRV_MEMALLOCFLAGS_GPU_MMUFLAGSMASK | \ + PVRSRV_MEMALLOCFLAGS_CPU_MMUFLAGSMASK | \ + PVRSRV_MEMALLOCFLAG_NO_OSPAGES_ON_ALLOC | \ + PVRSRV_MEMALLOCFLAG_SPARSE_NO_DUMMY_BACKING | \ + PVRSRV_MEMALLOCFLAG_SPARSE_ZERO_BACKING | \ + PVRSRV_MEMALLOCFLAG_VAL_SHARED_BUFFER | \ + PVRSRV_PHYS_HEAP_HINT_MASK) +#endif /*! * CPU mappable mask -- Any flag set in the mask requires memory to be CPU mappable @@ -874,11 +902,18 @@ typedef IMG_UINT64 PVRSRV_MEMALLOCFLAGS_T; memory might be reused. */ +#if defined(DEBUG) || defined(SERVICES_SC) +#define PVRSRV_MEMALLOCFLAGS_RA_DIFFERENTIATION_MASK (PVRSRV_MEMALLOCFLAGS_PMRFLAGSMASK \ + & \ + ~(PVRSRV_MEMALLOCFLAG_ZERO_ON_ALLOC | \ + PVRSRV_MEMALLOCFLAG_POISON_ON_ALLOC | \ + PVRSRV_MEMALLOCFLAG_POISON_ON_FREE)) +#else #define PVRSRV_MEMALLOCFLAGS_RA_DIFFERENTIATION_MASK (PVRSRV_MEMALLOCFLAGS_PMRFLAGSMASK \ & \ ~(PVRSRV_MEMALLOCFLAG_ZERO_ON_ALLOC | \ PVRSRV_MEMALLOCFLAG_POISON_ON_ALLOC)) - +#endif /*! Flags that affect _allocation_ */ @@ -903,6 +938,7 @@ typedef IMG_UINT64 PVRSRV_MEMALLOCFLAGS_T; /*! Flags that affect _physical allocations_ in the DevMemX API */ +#if defined(DEBUG) || defined(SERVICES_SC) #define PVRSRV_MEMALLOCFLAGS_DEVMEMX_PHYSICAL_MASK (PVRSRV_MEMALLOCFLAGS_CPU_MMUFLAGSMASK | \ PVRSRV_MEMALLOCFLAG_GPU_CACHE_MODE_MASK | \ PVRSRV_MEMALLOCFLAG_CPU_READ_PERMITTED | \ @@ -912,6 +948,16 @@ typedef IMG_UINT64 PVRSRV_MEMALLOCFLAGS_T; PVRSRV_MEMALLOCFLAG_POISON_ON_ALLOC | \ PVRSRV_MEMALLOCFLAG_POISON_ON_FREE | \ PVRSRV_PHYS_HEAP_HINT_MASK) +#else +#define PVRSRV_MEMALLOCFLAGS_DEVMEMX_PHYSICAL_MASK (PVRSRV_MEMALLOCFLAGS_CPU_MMUFLAGSMASK | \ + PVRSRV_MEMALLOCFLAG_GPU_CACHE_MODE_MASK | \ + PVRSRV_MEMALLOCFLAG_CPU_READ_PERMITTED | \ + PVRSRV_MEMALLOCFLAG_CPU_WRITE_PERMITTED | \ + PVRSRV_MEMALLOCFLAG_CPU_CACHE_CLEAN | \ + PVRSRV_MEMALLOCFLAG_ZERO_ON_ALLOC | \ + PVRSRV_MEMALLOCFLAG_POISON_ON_ALLOC | \ + PVRSRV_PHYS_HEAP_HINT_MASK) +#endif /*! Flags that affect _virtual allocations_ in the DevMemX API diff --git a/drivers/gpu/drm/img-rogue/include/pvrsrv_tlcommon.h b/drivers/gpu/drm/img-rogue/include/pvrsrv_tlcommon.h index 7b5761397..28999e5d2 100644 --- a/drivers/gpu/drm/img-rogue/include/pvrsrv_tlcommon.h +++ b/drivers/gpu/drm/img-rogue/include/pvrsrv_tlcommon.h @@ -170,7 +170,7 @@ typedef IMG_UINT32 PVRSRVTL_PACKETTYPE; */ #define PVRSRVTL_SET_PACKET_DATA(len) (len) | (PVRSRVTL_PACKETTYPE_DATA << PVRSRVTL_PACKETHDR_TYPE_OFFSET) #define PVRSRVTL_SET_PACKET_PADDING(len) (len) | (PVRSRVTL_PACKETTYPE_PADDING << PVRSRVTL_PACKETHDR_TYPE_OFFSET) -#define PVRSRVTL_SET_PACKET_WRITE_FAILED (0) | (PVRSRVTL_PACKETTYPE_MOST_RECENT_WRITE_FAILED << PVRSRVTL_PACKETHDR_TYPE_OFFSET) +#define PVRSRVTL_SET_PACKET_WRITE_FAILED (0U) | (PVRSRVTL_PACKETTYPE_MOST_RECENT_WRITE_FAILED << PVRSRVTL_PACKETHDR_TYPE_OFFSET) #define PVRSRVTL_SET_PACKET_HDR(len, type) (len) | ((type) << PVRSRVTL_PACKETHDR_TYPE_OFFSET) /*! Returns the number of bytes of data in the packet. diff --git a/drivers/gpu/drm/img-rogue/include/pvrversion.h b/drivers/gpu/drm/img-rogue/include/pvrversion.h index 53db28ba8..c62b3f752 100644 --- a/drivers/gpu/drm/img-rogue/include/pvrversion.h +++ b/drivers/gpu/drm/img-rogue/include/pvrversion.h @@ -45,21 +45,21 @@ CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. #define PVRVERSION_H #define PVRVERSION_MAJ 1U -#define PVRVERSION_MIN 16U +#define PVRVERSION_MIN 17U #define PVRVERSION_FAMILY "rogueddk" -#define PVRVERSION_BRANCHNAME "1.16" -#define PVRVERSION_BUILD 6099580 +#define PVRVERSION_BRANCHNAME "1.17" +#define PVRVERSION_BUILD 6210866 #define PVRVERSION_BSCONTROL "Rogue_DDK_Linux_WS" -#define PVRVERSION_STRING "Rogue_DDK_Linux_WS rogueddk 1.16@6099580" -#define PVRVERSION_STRING_SHORT "1.16@6099580" +#define PVRVERSION_STRING "Rogue_DDK_Linux_WS rogueddk 1.17@6210866" +#define PVRVERSION_STRING_SHORT "1.17@6210866" #define COPYRIGHT_TXT "Copyright (c) Imagination Technologies Ltd. All Rights Reserved." -#define PVRVERSION_BUILD_HI 609 -#define PVRVERSION_BUILD_LO 9580 -#define PVRVERSION_STRING_NUMERIC "1.16.609.9580" +#define PVRVERSION_BUILD_HI 621 +#define PVRVERSION_BUILD_LO 866 +#define PVRVERSION_STRING_NUMERIC "1.17.621.866" #define PVRVERSION_PACK(MAJOR,MINOR) (((IMG_UINT32)((IMG_UINT32)(MAJOR) & 0xFFFFU) << 16U) | (((MINOR) & 0xFFFFU) << 0U)) #define PVRVERSION_UNPACK_MAJ(VERSION) (((VERSION) >> 16U) & 0xFFFFU) diff --git a/drivers/gpu/drm/img-rogue/include/rgx_common.h b/drivers/gpu/drm/img-rogue/include/rgx_common.h index b20d0456e..b6ae1500a 100644 --- a/drivers/gpu/drm/img-rogue/include/rgx_common.h +++ b/drivers/gpu/drm/img-rogue/include/rgx_common.h @@ -52,20 +52,7 @@ extern "C" { /* Included to get the BVNC_KM_N defined and other feature defs */ #include "km/rgxdefs_km.h" -/*! This macro represents a mask of LSBs that must be zero on data structure - * sizes and offsets to ensure they are 8-byte granular on types shared between - * the FW and host driver */ -#define RGX_FW_ALIGNMENT_LSB (7U) - -/*! Macro to test structure size alignment */ -#define RGX_FW_STRUCT_SIZE_ASSERT(_a) \ - static_assert((sizeof(_a) & RGX_FW_ALIGNMENT_LSB) == 0U, \ - "Size of " #_a " is not properly aligned") - -/*! Macro to test structure member alignment */ -#define RGX_FW_STRUCT_OFFSET_ASSERT(_a, _b) \ - static_assert((offsetof(_a, _b) & RGX_FW_ALIGNMENT_LSB) == 0U, \ - "Offset of " #_a "." #_b " is not properly aligned") +#include "rgx_common_asserts.h" /* Virtualisation validation builds are meant to test the VZ-related hardware without a fully virtualised platform. @@ -99,25 +86,25 @@ typedef IMG_UINT32 RGXFWIF_DM; #define RGXFWIF_DM_CDM IMG_UINT32_C(4) #define RGXFWIF_DM_RAY IMG_UINT32_C(5) #define RGXFWIF_DM_GEOM2 IMG_UINT32_C(6) +#define RGXFWIF_DM_GEOM3 IMG_UINT32_C(7) +#define RGXFWIF_DM_GEOM4 IMG_UINT32_C(8) -#define RGXFWIF_DM_LAST RGXFWIF_DM_GEOM2 +#define RGXFWIF_DM_LAST RGXFWIF_DM_GEOM4 -typedef enum _RGX_KICK_TYPE_DM_ -{ - RGX_KICK_TYPE_DM_GP = 0x001, - RGX_KICK_TYPE_DM_TDM_2D = 0x002, - RGX_KICK_TYPE_DM_TA = 0x004, - RGX_KICK_TYPE_DM_3D = 0x008, - RGX_KICK_TYPE_DM_CDM = 0x010, - RGX_KICK_TYPE_DM_RTU = 0x020, - RGX_KICK_TYPE_DM_SHG = 0x040, - RGX_KICK_TYPE_DM_TQ2D = 0x080, - RGX_KICK_TYPE_DM_TQ3D = 0x100, - RGX_KICK_TYPE_DM_RAY = 0x200, - RGX_KICK_TYPE_DM_LAST = 0x400 -} RGX_KICK_TYPE_DM; +typedef IMG_UINT32 RGX_KICK_TYPE_DM; +#define RGX_KICK_TYPE_DM_GP IMG_UINT32_C(0x001) +#define RGX_KICK_TYPE_DM_TDM_2D IMG_UINT32_C(0x002) +#define RGX_KICK_TYPE_DM_TA IMG_UINT32_C(0x004) +#define RGX_KICK_TYPE_DM_3D IMG_UINT32_C(0x008) +#define RGX_KICK_TYPE_DM_CDM IMG_UINT32_C(0x010) +#define RGX_KICK_TYPE_DM_RTU IMG_UINT32_C(0x020) +#define RGX_KICK_TYPE_DM_SHG IMG_UINT32_C(0x040) +#define RGX_KICK_TYPE_DM_TQ2D IMG_UINT32_C(0x080) +#define RGX_KICK_TYPE_DM_TQ3D IMG_UINT32_C(0x100) +#define RGX_KICK_TYPE_DM_RAY IMG_UINT32_C(0x200) +#define RGX_KICK_TYPE_DM_LAST IMG_UINT32_C(0x400) -/* Maximum number of DM in use: GP, 2D/TDM, GEOM, 3D, CDM, RDM, GEOM2 */ +/* Maximum number of DM in use: GP, 2D/TDM, GEOM, 3D, CDM, RDM, GEOM2, GEOM3, GEOM4 */ #define RGXFWIF_DM_MAX (RGXFWIF_DM_LAST + 1U) /* @@ -201,10 +188,18 @@ typedef enum _RGX_KICK_TYPE_DM_ #define RGX_MAX_NUM_REGISTER_PROGRAMMER_WRITES (128U) /* FW common context priority. */ -#define RGX_CTX_PRIORITY_REALTIME (UINT32_MAX) -#define RGX_CTX_PRIORITY_HIGH (2U) -#define RGX_CTX_PRIORITY_MEDIUM (1U) -#define RGX_CTX_PRIORITY_LOW (0) +/*! + * @AddToGroup WorkloadContexts + * @{ + */ +#define RGX_CTX_PRIORITY_REALTIME (INT32_MAX) +#define RGX_CTX_PRIORITY_HIGH (2U) /*!< HIGH priority */ +#define RGX_CTX_PRIORITY_MEDIUM (1U) /*!< MEDIUM priority */ +#define RGX_CTX_PRIORITY_LOW (0) /*!< LOW priority */ +/*! + * @} End of AddToGroup WorkloadContexts + */ + /* * Use of the 32-bit context property flags mask @@ -220,6 +215,9 @@ typedef enum _RGX_KICK_TYPE_DM_ */ #define RGX_CONTEXT_FLAG_DISABLESLR (1UL << 0) /*!< Disable SLR */ +/* Bitmask of context flags allowed to be modified after context create. */ +#define RGX_CONTEXT_FLAGS_WRITEABLE_MASK (RGX_CONTEXT_FLAG_DISABLESLR) + /* List of attributes that may be set for a context */ typedef enum _RGX_CONTEXT_PROPERTY_ { diff --git a/drivers/gpu/drm/img-rogue/include/rgx_common_asserts.h b/drivers/gpu/drm/img-rogue/include/rgx_common_asserts.h new file mode 100644 index 000000000..c571cc6f0 --- /dev/null +++ b/drivers/gpu/drm/img-rogue/include/rgx_common_asserts.h @@ -0,0 +1,73 @@ +/*************************************************************************/ /*! +@File +@Title RGX Common Types and Defines Header +@Copyright Copyright (c) Imagination Technologies Ltd. All Rights Reserved +@Description Common types and definitions for RGX software +@License Dual MIT/GPLv2 + +The contents of this file are subject to the MIT license as set out below. + +Permission is hereby granted, free of charge, to any person obtaining a copy +of this software and associated documentation files (the "Software"), to deal +in the Software without restriction, including without limitation the rights +to use, copy, modify, merge, publish, distribute, sublicense, and/or sell +copies of the Software, and to permit persons to whom the Software is +furnished to do so, subject to the following conditions: + +The above copyright notice and this permission notice shall be included in +all copies or substantial portions of the Software. + +Alternatively, the contents of this file may be used under the terms of +the GNU General Public License Version 2 ("GPL") in which case the provisions +of GPL are applicable instead of those above. + +If you wish to allow use of your version of this file only under the terms of +GPL, and not to allow others to use your version of this file under the terms +of the MIT license, indicate your decision by deleting the provisions above +and replace them with the notice and other provisions required by GPL as set +out in the file called "GPL-COPYING" included in this distribution. If you do +not delete the provisions above, a recipient may use your version of this file +under the terms of either the MIT license or GPL. + +This License is also included in this distribution in the file called +"MIT-COPYING". + +EXCEPT AS OTHERWISE STATED IN A NEGOTIATED AGREEMENT: (A) THE SOFTWARE IS +PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING +BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR +PURPOSE AND NONINFRINGEMENT; AND (B) IN NO EVENT SHALL THE AUTHORS OR +COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER +IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN +CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +*/ /**************************************************************************/ +#ifndef RGX_COMMON_ASSERTS_H +#define RGX_COMMON_ASSERTS_H + +#if defined(__cplusplus) +extern "C" { +#endif + +/*! This macro represents a mask of LSBs that must be zero on data structure + * sizes and offsets to ensure they are 8-byte granular on types shared between + * the FW and host driver */ +#define RGX_FW_ALIGNMENT_LSB (7U) + +/*! Macro to test structure size alignment */ +#define RGX_FW_STRUCT_SIZE_ASSERT(_a) \ + static_assert((sizeof(_a) & RGX_FW_ALIGNMENT_LSB) == 0U, \ + "Size of " #_a " is not properly aligned") + +/*! Macro to test structure member alignment */ +#define RGX_FW_STRUCT_OFFSET_ASSERT(_a, _b) \ + static_assert((offsetof(_a, _b) & RGX_FW_ALIGNMENT_LSB) == 0U, \ + "Offset of " #_a "." #_b " is not properly aligned") + +#if defined(__cplusplus) +} +#endif + +#endif /* RGX_COMMON_ASSERTS_H */ + +/****************************************************************************** + End of file +******************************************************************************/ diff --git a/drivers/gpu/drm/img-rogue/include/rgx_compat_bvnc.h b/drivers/gpu/drm/img-rogue/include/rgx_compat_bvnc.h index 748a59113..c3e1333cd 100644 --- a/drivers/gpu/drm/img-rogue/include/rgx_compat_bvnc.h +++ b/drivers/gpu/drm/img-rogue/include/rgx_compat_bvnc.h @@ -110,7 +110,7 @@ CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. (bvnc) = ((L).ui64BVNC == (R).ui64BVNC); \ } \ (all) = (version) && (bvnc); \ - } while (0) + } while (false) /**************************************************************************//** diff --git a/drivers/gpu/drm/img-rogue/include/rgx_fwif_resetframework.h b/drivers/gpu/drm/img-rogue/include/rgx_fwif_resetframework.h index 84575635f..e60bafd84 100644 --- a/drivers/gpu/drm/img-rogue/include/rgx_fwif_resetframework.h +++ b/drivers/gpu/drm/img-rogue/include/rgx_fwif_resetframework.h @@ -48,21 +48,17 @@ CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. typedef struct { -#if defined(RGX_FEATURE_CDM_USER_MODE_QUEUE) - IMG_UINT64 uCDMReg_CDM_CB_QUEUE; - IMG_UINT64 uCDMReg_CDM_CB_BASE; - IMG_UINT64 uCDMReg_CDM_CB; -#else - IMG_UINT64 uCDMReg_CDM_CTRL_STREAM_BASE; -#endif + union + { + IMG_UINT64 uCDMReg_CDM_CB_BASE; // defined(RGX_FEATURE_CDM_USER_MODE_QUEUE) + IMG_UINT64 uCDMReg_CDM_CTRL_STREAM_BASE; // !defined(RGX_FEATURE_CDM_USER_MODE_QUEUE) + }; + IMG_UINT64 uCDMReg_CDM_CB_QUEUE; // !defined(RGX_FEATURE_CDM_USER_MODE_QUEUE) + IMG_UINT64 uCDMReg_CDM_CB; // !defined(RGX_FEATURE_CDM_USER_MODE_QUEUE) } RGXFWIF_RF_REGISTERS; -#define RGXFWIF_RF_FLAG_ENABLE 0x00000001U /*!< enables the reset framework in the firmware */ - typedef struct { - IMG_UINT32 ui32Flags; - /* THIS MUST BE THE LAST MEMBER OF THE CONTAINING STRUCTURE */ RGXFWIF_RF_REGISTERS RGXFW_ALIGN sFWRegisters; diff --git a/drivers/gpu/drm/img-rogue/include/rgx_fwif_sf.h b/drivers/gpu/drm/img-rogue/include/rgx_fwif_sf.h index 9cb64d898..9238cf8ca 100644 --- a/drivers/gpu/drm/img-rogue/include/rgx_fwif_sf.h +++ b/drivers/gpu/drm/img-rogue/include/rgx_fwif_sf.h @@ -71,6 +71,10 @@ CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. X(RGXFW_GROUP_DMA,DMA) \ X(RGXFW_GROUP_DBG,DBG) +/*! + * @InGroup SRVAndFWTracing + * @Brief FW Trace log groups(GID) list + */ enum RGXFW_LOG_SFGROUPS { #define X(A,B) A, RGXFW_LOG_SFGROUPLIST @@ -284,7 +288,7 @@ X(181, RGXFW_GROUP_MAIN, RGXFW_SF_MAIN_SIGNAL_UPDATE, "Signal update, Snoop Filt X(182, RGXFW_GROUP_MAIN, RGXFW_SF_MAIN_DEV_SERIES8_DEPRECATED, "WARNING: Skipping FW KCCB Cmd type %d which is not yet supported on Series8.", 1) \ X(183, RGXFW_GROUP_MAIN, RGXFW_SF_MAIN_INCONSISTENT_MMU_FLAGS, "MMU context cache data NULL, but cache flags=0x%x (sync counter=%u, update value=%u) OSId=%u", 4) \ X(184, RGXFW_GROUP_MAIN, RGXFW_SF_MAIN_SLC_FLUSH, "SLC range based flush: Context=%u VAddr=0x%02x%08x, Size=0x%08x, Invalidate=%d", 5) \ -X(185, RGXFW_GROUP_MAIN, RGXFW_SF_MAIN_FBSC_INVAL, "FBSC invalidate for Context [0x%08x]: Entry mask 0x%08x%08x.", 3) \ +X(185, RGXFW_GROUP_MAIN, RGXFW_SF_MAIN_FBSC_INVAL, "FBSC invalidate for Context Set [0x%08x]: Entry mask 0x%08x%08x.", 3) \ X(186, RGXFW_GROUP_MAIN, RGXFW_SF_MAIN_TDM_BRN66284_UPDATE, "TDM context switch check: Roff %u was not valid for kick starting at %u, moving back to %u", 3) \ X(187, RGXFW_GROUP_MAIN, RGXFW_SF_MAIN_SPFILTER_UPDATES, "Signal updates: FIFO: %u, Signals: 0x%08x", 2) \ X(188, RGXFW_GROUP_MAIN, RGXFW_SF_MAIN_INVALID_FBSC_CMD, "Invalid FBSC cmd: FWCtx 0x%08x, MemCtx 0x%08x", 2) \ @@ -318,8 +322,8 @@ X(215, RGXFW_GROUP_MAIN, RGXFW_SF_MAIN_USC_TASKS_RANGE, "DM%d USC tasks range li X(216, RGXFW_GROUP_MAIN, RGXFW_SF_MAIN_GPU_ECC_FAULT, "ECC fault GPU=0x%08x", 1) \ X(217, RGXFW_GROUP_MAIN, RGXFW_SF_MAIN_GPU_SAFETY_RESET, "GPU Hardware units reset to prevent transient faults.", 0) \ X(218, RGXFW_GROUP_MAIN, RGXFW_SF_MAIN_ABORTCMD, "Kick Abort cmd: FWCtx 0x%08.8x @ %d", 2) \ -X(219, RGXFW_GROUP_MAIN, RGXFW_SF_MAIN_KICK_RAY, "Kick Ray: FWCtx 0x%08.8x @ %d. (PID:%d, prio:%d, frame:%d, ext:0x%08x, int:0x%08x)", 7)\ -X(220, RGXFW_GROUP_MAIN, RGXFW_SF_MAIN_RAY_FINISHED, "Ray finished", 0) \ +X(219, RGXFW_GROUP_MAIN, RGXFW_SF_MAIN_KICK_RAY_DEPRECATED, "Kick Ray: FWCtx 0x%08.8x @ %d. (PID:%d, prio:%d, frame:%d, ext:0x%08x, int:0x%08x)", 7)\ +X(220, RGXFW_GROUP_MAIN, RGXFW_SF_MAIN_RAY_FINISHED_DEPRECATED, "Ray finished", 0) \ X(221, RGXFW_GROUP_MAIN, RGXFW_SF_MAIN_FWDATA_INIT_STATUS, "State of firmware's private data at boot time: %d (0 = uninitialised, 1 = initialised); Fw State Flags = 0x%08X", 2) \ X(222, RGXFW_GROUP_MAIN, RGXFW_SF_MAIN_CFI_TIMEOUT, "CFI Timeout detected (%d increasing to %d)", 2) \ X(223, RGXFW_GROUP_MAIN, RGXFW_SF_MAIN_CFI_TIMEOUT_FBM, "CFI Timeout detected for FBM (%d increasing to %d)", 2) \ @@ -327,6 +331,17 @@ X(224, RGXFW_GROUP_MAIN, RGXFW_SF_MAIN_GEOM_OOM_DISALLOWED, "Geom OOM event not X(225, RGXFW_GROUP_MAIN, RGXFW_SF_MAIN_OS_PRIORITY_CHANGE, "Changing OSid %d's priority from %u to %u; Isolation = %u (0 = off; 1 = on)", 4) \ X(226, RGXFW_GROUP_MAIN, RGXFW_SF_MAIN_SKIP_ALREADY_RUN_GEOM, "Skipping already executed TA FWCtx 0x%08.8x @ %d", 2) \ X(227, RGXFW_GROUP_MAIN, RGXFW_SF_MAIN_ATTEMPT_TO_RUN_AHEAD_GEOM, "Attempt to execute TA FWCtx 0x%08.8x @ %d ahead of time on other GEOM", 2) \ +X(228, RGXFW_GROUP_MAIN, RGXFW_SF_MAIN_KICK_TDM_DEPRECATED2, "Kick TDM: Kick ID %u FWCtx 0x%08.8x @ %d. (PID:%d, prio:%d, frame:%d, ext:0x%08x, int:0x%08x)", 8) \ +X(229, RGXFW_GROUP_MAIN, RGXFW_SF_MAIN_KICK_TA_PIPELINE, "Kick TA: Kick ID %u FWCtx 0x%08.8x @ %d, RTD 0x%08x, First kick:%d, Last kick:%d, CSW resume:%d. (PID:%d, prio:%d, frame:%d, ext:0x%08x, int:0x%08x)", 12) \ +X(230, RGXFW_GROUP_MAIN, RGXFW_SF_MAIN_KICK_3D_PIPELINE, "Kick 3D: Kick ID %u FWCtx 0x%08.8x @ %d, RTD 0x%08x, Partial render:%d, CSW resume:%d. (PID:%d, prio:%d, frame:%d, ext:0x%08x, int:0x%08x)", 11) \ +X(231, RGXFW_GROUP_MAIN, RGXFW_SF_MAIN_KICK_COMPUTE_PIPELINE, "Kick Compute: Kick ID %u FWCtx 0x%08.8x @ %d. (PID:%d, prio:%d, ext:0x%08x, int:0x%08x)", 7) \ +X(232, RGXFW_GROUP_MAIN, RGXFW_SF_MAIN_TDM_FINISHED_PIPELINE, "TDM finished: Kick ID %u ", 1) \ +X(233, RGXFW_GROUP_MAIN, RGXFW_SF_MAIN_TA_FINISHED_PIPELINE, "TA finished: Kick ID %u ", 1) \ +X(234, RGXFW_GROUP_MAIN, RGXFW_SF_MAIN_3D_FINISHED_PIPELINE, "3D finished: Kick ID %u , HWRTData0State=%x, HWRTData1State=%x", 3) \ +X(235, RGXFW_GROUP_MAIN, RGXFW_SF_MAIN_COMPUTE_FINISHED_PIPELINE, "Compute finished: Kick ID %u ", 1) \ +X(236, RGXFW_GROUP_MAIN, RGXFW_SF_MAIN_KICK_TDM_PIPELINE, "Kick TDM: Kick ID %u FWCtx 0x%08.8x @ %d, Base 0x%08x%08x. (PID:%d, prio:%d, frame:%d, ext:0x%08x, int:0x%08x)", 10) \ +X(237, RGXFW_GROUP_MAIN, RGXFW_SF_MAIN_KICK_RAY_PIPELINE, "Kick Ray: Kick ID %u FWCtx 0x%08.8x @ %d. (PID:%d, prio:%d, frame:%d, ext:0x%08x, int:0x%08x)", 8)\ +X(238, RGXFW_GROUP_MAIN, RGXFW_SF_MAIN_RAY_FINISHED_PIPELINE, "Ray finished: Kick ID %u ", 1) \ \ X( 1, RGXFW_GROUP_MTS, RGXFW_SF_MTS_BG_KICK_DEPRECATED, "Bg Task DM = %u, counted = %d", 2) \ X( 2, RGXFW_GROUP_MTS, RGXFW_SF_MTS_BG_COMPLETE_DEPRECATED, "Bg Task complete DM = %u", 1) \ @@ -348,6 +363,7 @@ X( 17, RGXFW_GROUP_MTS, RGXFW_SF_MTS_KCCBCMD_RTN_VALUE, "KCCB Slot %u: Return va X( 18, RGXFW_GROUP_MTS, RGXFW_SF_MTS_BG_KICK, "Bg Task OSid = %u", 1) \ X( 19, RGXFW_GROUP_MTS, RGXFW_SF_MTS_KCCBCMD_EXEC, "KCCB Slot %u: Cmd=0x%08x, OSid=%u", 3) \ X( 20, RGXFW_GROUP_MTS, RGXFW_SF_MTS_IRQ_KICK, "Irq Task (EVENT_STATUS=0x%08x)", 1) \ +X( 21, RGXFW_GROUP_MTS, RGXFW_SF_MTS_VZ_SIDEBAND, "VZ sideband test, kicked with OSid=%u from MTS, OSid for test=%u", 2) \ \ X( 1, RGXFW_GROUP_CLEANUP, RGXFW_SF_CLEANUP_FWCTX_CLEANUP, "FwCommonContext [0x%08x] cleaned", 1) \ X( 2, RGXFW_GROUP_CLEANUP, RGXFW_SF_CLEANUP_FWCTX_BUSY, "FwCommonContext [0x%08x] is busy: ReadOffset = %d, WriteOffset = %d", 3) \ @@ -425,9 +441,9 @@ X( 54, RGXFW_GROUP_CSW, RGXFW_SF_CSW_RDM_RESUME, "RDM FWCtx 0x%08.8x resume", 1) \ X( 1, RGXFW_GROUP_BIF, RGXFW_SF_BIF_ACTIVATE_BIFREQ_DEPRECATED, "Activate MemCtx=0x%08x BIFreq=%d secure=%d", 3) \ X( 2, RGXFW_GROUP_BIF, RGXFW_SF_BIF_DEACTIVATE, "Deactivate MemCtx=0x%08x", 1) \ -X( 3, RGXFW_GROUP_BIF, RGXFW_SF_BIF_PCREG_ALLOC, "Alloc PC reg %d", 1) \ -X( 4, RGXFW_GROUP_BIF, RGXFW_SF_BIF_PCREG_GRAB, "Grab reg %d refcount now %d", 2) \ -X( 5, RGXFW_GROUP_BIF, RGXFW_SF_BIF_PCREG_UNGRAB, "Ungrab reg %d refcount now %d", 2) \ +X( 3, RGXFW_GROUP_BIF, RGXFW_SF_BIF_PCREG_ALLOC_DEPRECATED, "Alloc PC reg %d", 1) \ +X( 4, RGXFW_GROUP_BIF, RGXFW_SF_BIF_PCSET_GRAB, "Grab reg set %d refcount now %d", 2) \ +X( 5, RGXFW_GROUP_BIF, RGXFW_SF_BIF_PCSET_UNGRAB, "Ungrab reg set %d refcount now %d", 2) \ X( 6, RGXFW_GROUP_BIF, RGXFW_SF_BIF_SETUP_REG_BIFREQ_DEPRECATED, "Setup reg=%d BIFreq=%d, expect=0x%08x%08x, actual=0x%08x%08x", 6) \ X( 7, RGXFW_GROUP_BIF, RGXFW_SF_BIF_TRUST_DEPRECATED, "Trust enabled:%d, for BIFreq=%d", 2) \ X( 8, RGXFW_GROUP_BIF, RGXFW_SF_BIF_TILECFG_DEPRECATED, "BIF Tiling Cfg %d base 0x%08x%08x len 0x%08x%08x enable %d stride %d --> 0x%08x%08x", 9) \ @@ -437,10 +453,12 @@ X( 11, RGXFW_GROUP_BIF, RGXFW_SF_BIF_OSIDx, "ui32OSid = %u, Catbase = %u, Reg Ad X( 12, RGXFW_GROUP_BIF, RGXFW_SF_BIF_MAP_GPU_MEMORY_BIFREQ_DEPRECATED, "Map GPU memory DevVAddr 0x%x%08x, Size %u, Context ID %u, BIFREQ %u", 5) \ X( 13, RGXFW_GROUP_BIF, RGXFW_SF_BIF_UNMAP_GPU_MEMORY, "Unmap GPU memory (event status 0x%x)", 1) \ X( 14, RGXFW_GROUP_BIF, RGXFW_SF_BIF_ACTIVATE_DM, "Activate MemCtx=0x%08x DM=%d secure=%d", 3) \ -X( 15, RGXFW_GROUP_BIF, RGXFW_SF_BIF_SETUP_REG_DM, "Setup reg=%d DM=%d, expect=0x%08x%08x, actual=0x%08x%08x", 6) \ +X( 15, RGXFW_GROUP_BIF, RGXFW_SF_BIF_SETUP_REG_DM_DEPRECATED, "Setup reg=%d DM=%d, expect=0x%08x%08x, actual=0x%08x%08x", 6) \ X( 16, RGXFW_GROUP_BIF, RGXFW_SF_BIF_MAP_GPU_MEMORY, "Map GPU memory DevVAddr 0x%x%08x, Size %u, Context ID %u", 4) \ X( 17, RGXFW_GROUP_BIF, RGXFW_SF_BIF_TRUST_DM, "Trust enabled:%d, for DM=%d", 2) \ X( 18, RGXFW_GROUP_BIF, RGXFW_SF_BIF_MAP_GPU_MEMORY_DM, "Map GPU memory DevVAddr 0x%x%08x, Size %u, Context ID %u, DM %u", 5) \ +X( 19, RGXFW_GROUP_BIF, RGXFW_SF_BIF_SETUP_REG_DM, "Setup register set=%d DM=%d, PC address=0x%08x%08x, OSid=%u, NewPCRegRequired=%d", 6) \ +X( 20, RGXFW_GROUP_BIF, RGXFW_SF_BIF_PCSET_ALLOC, "Alloc PC set %d as register range [%u - %u]", 3) \ \ X( 1, RGXFW_GROUP_MISC, RGXFW_SF_MISC_GPIO_WRITE, "GPIO write 0x%02x", 1) \ X( 2, RGXFW_GROUP_MISC, RGXFW_SF_MISC_GPIO_READ, "GPIO read 0x%02x", 1) \ @@ -505,6 +523,8 @@ X( 28, RGXFW_GROUP_PM, RGXFW_SF_PM_3D_TIMEOUT, "3D Timeout Now for FWCtx 0x%08.8 X( 29, RGXFW_GROUP_PM, RGXFW_SF_PM_RECYCLE, "GEOM PM Recycle for FWCtx 0x%08.8x", 1) \ X( 30, RGXFW_GROUP_PM, RGXFW_SF_PM_PRIMARY_CONFIG, "PM running primary config (Core %d)", 1) \ X( 31, RGXFW_GROUP_PM, RGXFW_SF_PM_SECONDARY_CONFIG, "PM running secondary config (Core %d)", 1) \ +X( 32, RGXFW_GROUP_PM, RGXFW_SF_PM_TERTIARY_CONFIG, "PM running tertiary config (Core %d)", 1) \ +X( 33, RGXFW_GROUP_PM, RGXFW_SF_PM_QUATERNARY_CONFIG, "PM running quaternary config (Core %d)", 1) \ \ X( 1, RGXFW_GROUP_RPM, RGXFW_SF_RPM_GLL_DYNAMIC_STATUS_DEPRECATED, "Global link list dynamic page count: vertex 0x%x, varying 0x%x, node 0x%x", 3) \ X( 2, RGXFW_GROUP_RPM, RGXFW_SF_RPM_GLL_STATIC_STATUS_DEPRECATED, "Global link list static page count: vertex 0x%x, varying 0x%x, node 0x%x", 3) \ @@ -628,6 +648,7 @@ X( 54, RGXFW_GROUP_SPM, RGXFW_SF_SPM_ACK_GROW_UPDATE, "Received grow update, FL X( 66, RGXFW_GROUP_SPM, RGXFW_SF_SPM_OOM_TACMD, "OOM TA/3D PR Check: [0x%08.8x] is 0x%08.8x requires 0x%08.8x", 3) \ X( 67, RGXFW_GROUP_SPM, RGXFW_SF_SPM_RESUMED_TA, "OOM: Resumed TA with ready pages, FL addr: 0x%02x%08x, current pages: %u", 3) \ X( 68, RGXFW_GROUP_SPM, RGXFW_SF_SPM_PR_DEADLOCK_UNBLOCKED, "OOM TA/3D PR deadlock unblocked reordering DM%d runlist head from Context 0x%08x to 0x%08x", 3) \ +X( 69, RGXFW_GROUP_SPM, RGXFW_SF_SPM_STATE_PR_FORCEFREE, "SPM State = PR force free", 0) \ \ X( 1, RGXFW_GROUP_POW, RGXFW_SF_POW_CHECK_DEPRECATED, "Check Pow state DM%d int: 0x%x, ext: 0x%x, pow flags: 0x%x", 4) \ X( 2, RGXFW_GROUP_POW, RGXFW_SF_POW_GPU_IDLE, "GPU idle (might be powered down). Pow state int: 0x%x, ext: 0x%x, flags: 0x%x", 3) \ @@ -697,6 +718,10 @@ X( 66, RGXFW_GROUP_POW, RGXFW_SF_POW_POWMON_PERF_MODE, "PPA block started in per X( 67, RGXFW_GROUP_POW, RGXFW_SF_POW_POWMON_RESET, "Reset PPA block state %u (1=reset, 0=recalculate).", 1) \ X( 68, RGXFW_GROUP_POW, RGXFW_SF_POW_POWCTRL_ABORT_WITH_CORE, "Power controller returned ABORT for Core-%d last request so retrying.", 1) \ X( 69, RGXFW_GROUP_POW, RGXFW_SF_POW_HWREQ64BIT, "HW Request On(1)/Off(0): %d, Units: 0x%08x%08x", 3) \ +X( 70, RGXFW_GROUP_POW, RGXFW_SF_POW_SPU_RAC_POW_STATE_CHANGE_REQ, "Request to change SPU power state mask from 0x%x to 0x%x and RAC from 0x%x to 0x%x. Pow flags: 0x%x", 5) \ +X( 71, RGXFW_GROUP_POW, RGXFW_SF_POW_SPU_RAC_POW_STATE_CHANGE, "Changing SPU power state mask from 0x%x to 0x%x and RAC from 0x%x to 0x%x", 4) \ +X( 72, RGXFW_GROUP_POW, RGXFW_SF_POW_REQUESTEDOFF_RAC, "RAC pending? %d, RAC Active? %d", 2) \ +X( 73, RGXFW_GROUP_POW, RGXFW_SF_POW_INIOFF_RAC, "Initiate powoff query for RAC.", 0) \ \ X( 1, RGXFW_GROUP_HWR, RGXFW_SF_HWR_LOCKUP_DEPRECATED, "Lockup detected on DM%d, FWCtx: 0x%08.8x", 2) \ X( 2, RGXFW_GROUP_HWR, RGXFW_SF_HWR_RESET_FW_DEPRECATED, "Reset fw state for DM%d, FWCtx: 0x%08.8x, MemCtx: 0x%08.8x", 3) \ @@ -786,14 +811,15 @@ X( 85, RGXFW_GROUP_HWR, RGXFW_SF_HWR_FULL_CHECK, "Full Signature Check result fo X( 86, RGXFW_GROUP_HWR, RGXFW_SF_HWR_USC_SLOTS_CHECK, "USC Slots result for Core%u, DM%u is HWRNeeded=%u USCSlotsUsedByDM=%d", 4) \ X( 87, RGXFW_GROUP_HWR, RGXFW_SF_HWR_WATCHDOG_CHECK, "USC Watchdog result for Core%u DM%u is HWRNeeded=%u Status=%u USCs={0x%x} with HWRChecksToGo=%u", 6) \ X( 88, RGXFW_GROUP_HWR, RGXFW_SF_HWR_MMU_RISCV_FAULT, "RISC-V MMU page fault detected (FWCORE MMU Status 0x%08x Req Status 0x%08x%08x)", 3) \ -X( 89, RGXFW_GROUP_HWR, RGXFW_SF_HWR_HWR_FAULT_POLL_BIF_TEXAS1_PFS_DEPRECATED, "After FW fault was raised, TEXAS1_PFS poll failed on core %d with value 0x%08x", 2) \ -X( 90, RGXFW_GROUP_HWR, RGXFW_SF_HWR_HWR_FAULT_POLL_BIF_PFS, "After FW fault was raised, BIF_PFS poll failed on core %d with value 0x%08x", 2) \ -X( 91, RGXFW_GROUP_HWR, RGXFW_SF_HWR_HWR_FAULT_POLL_SET_ABORT_PM_STATUS, "After FW fault was raised, MMU_ABORT_PM_STATUS set poll failed on core %d with value 0x%08x", 2) \ -X( 92, RGXFW_GROUP_HWR, RGXFW_SF_HWR_HWR_FAULT_POLL_UNSET_ABORT_PM_STATUS, "After FW fault was raised, MMU_ABORT_PM_STATUS unset poll failed on core %d with value 0x%08x", 2) \ -X( 93, RGXFW_GROUP_HWR, RGXFW_SF_HWR_HWR_FAULT_POLL_SLC_INVAL, "After FW fault was raised, MMU_CTRL_INVAL poll (all but fw) failed on core %d with value 0x%08x", 2) \ -X( 94, RGXFW_GROUP_HWR, RGXFW_SF_HWR_HWR_FAULT_POLL_SLCMMU_INVAL, "After FW fault was raised, MMU_CTRL_INVAL poll (all) failed on core %d with value 0x%08x", 2) \ -X( 95, RGXFW_GROUP_HWR, RGXFW_SF_HWR_HWR_FAULT_POLL_BIF_TEXAS_PFS, "After FW fault was raised, TEXAS%d_PFS poll failed on core %d with value 0x%08x", 3) \ +X( 89, RGXFW_GROUP_HWR, RGXFW_SF_HWR_HWR_FAULT_POLL_BIF_TEXAS1_PFS_DEPRECATED, "TEXAS1_PFS poll failed on core %d with value 0x%08x", 2) \ +X( 90, RGXFW_GROUP_HWR, RGXFW_SF_HWR_HWR_FAULT_POLL_BIF_PFS, "BIF_PFS poll failed on core %d with value 0x%08x", 2) \ +X( 91, RGXFW_GROUP_HWR, RGXFW_SF_HWR_HWR_FAULT_POLL_SET_ABORT_PM_STATUS, "MMU_ABORT_PM_STATUS set poll failed on core %d with value 0x%08x", 2) \ +X( 92, RGXFW_GROUP_HWR, RGXFW_SF_HWR_HWR_FAULT_POLL_UNSET_ABORT_PM_STATUS, "MMU_ABORT_PM_STATUS unset poll failed on core %d with value 0x%08x", 2) \ +X( 93, RGXFW_GROUP_HWR, RGXFW_SF_HWR_HWR_FAULT_POLL_SLC_INVAL, "MMU_CTRL_INVAL poll (all but fw) failed on core %d with value 0x%08x", 2) \ +X( 94, RGXFW_GROUP_HWR, RGXFW_SF_HWR_HWR_FAULT_POLL_SLCMMU_INVAL, "MMU_CTRL_INVAL poll (all) failed on core %d with value 0x%08x", 2) \ +X( 95, RGXFW_GROUP_HWR, RGXFW_SF_HWR_HWR_FAULT_POLL_BIF_TEXAS_PFS, "TEXAS%d_PFS poll failed on core %d with value 0x%08x", 3) \ X( 96, RGXFW_GROUP_HWR, RGXFW_SF_HWR_EXTRA_CHECK, "Extra Registers Check result for Core%u, DM%u is HWRNeeded=%u", 3) \ +X( 97, RGXFW_GROUP_HWR, RGXFW_SF_HWR_WRITE_TO_GPU_READONLY_ADDR, "FW attempted to write to read-only GPU address 0x%08x", 1) \ \ X( 1, RGXFW_GROUP_HWP, RGXFW_SF_HWP_I_CFGBLK, "Block 0x%x mapped to Config Idx %u", 2) \ X( 2, RGXFW_GROUP_HWP, RGXFW_SF_HWP_I_OMTBLK, "Block 0x%x omitted from event - not enabled in HW", 1) \ diff --git a/drivers/gpu/drm/img-rogue/include/rgx_heap_firmware.h b/drivers/gpu/drm/img-rogue/include/rgx_heap_firmware.h index 36150640d..db2b90b9f 100644 --- a/drivers/gpu/drm/img-rogue/include/rgx_heap_firmware.h +++ b/drivers/gpu/drm/img-rogue/include/rgx_heap_firmware.h @@ -57,7 +57,7 @@ CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. * of the map / unmap functions must take into consideration * the entire range (i.e. main and config heap). */ -#define RGX_FIRMWARE_NUMBER_OF_FW_HEAPS (2) +#define RGX_FIRMWARE_NUMBER_OF_FW_HEAPS (IMG_UINT32_C(2)) #define RGX_FIRMWARE_HEAP_SHIFT RGX_FW_HEAP_SHIFT #define RGX_FIRMWARE_RAW_HEAP_BASE (0xE1C0000000ULL) #define RGX_FIRMWARE_RAW_HEAP_SIZE (IMG_UINT32_C(1) << RGX_FIRMWARE_HEAP_SHIFT) @@ -73,9 +73,9 @@ CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. * 1st PMR: RGXFWIF_CONNECTION_CTL * 2nd PMR: RGXFWIF_OSINIT * 3rd PMR: RGXFWIF_SYSINIT */ -#define RGX_FIRMWARE_CONFIG_HEAP_SIZE (3*RGX_FIRMWARE_CONFIG_HEAP_ALLOC_GRANULARITY) +#define RGX_FIRMWARE_CONFIG_HEAP_SIZE (IMG_UINT32_C(3)*RGX_FIRMWARE_CONFIG_HEAP_ALLOC_GRANULARITY) -#define RGX_FIRMWARE_META_MAIN_HEAP_SIZE (RGX_FIRMWARE_RAW_HEAP_SIZE - RGX_FIRMWARE_CONFIG_HEAP_SIZE) +#define RGX_FIRMWARE_DEFAULT_MAIN_HEAP_SIZE (RGX_FIRMWARE_RAW_HEAP_SIZE - RGX_FIRMWARE_CONFIG_HEAP_SIZE) /* * MIPS FW needs space in the Main heap to map GPU memory. * This space is taken from the MAIN heap, to avoid creating a new heap. @@ -83,36 +83,30 @@ CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. #define RGX_FIRMWARE_MIPS_GPU_MAP_RESERVED_SIZE_NORMAL (IMG_UINT32_C(0x100000)) /* 1MB */ #define RGX_FIRMWARE_MIPS_GPU_MAP_RESERVED_SIZE_BRN65101 (IMG_UINT32_C(0x400000)) /* 4MB */ -#define RGX_FIRMWARE_MIPS_MAIN_HEAP_SIZE_NORMAL (RGX_FIRMWARE_RAW_HEAP_SIZE - RGX_FIRMWARE_CONFIG_HEAP_SIZE - \ - RGX_FIRMWARE_MIPS_GPU_MAP_RESERVED_SIZE_NORMAL) +#define RGX_FIRMWARE_HOST_MIPS_MAIN_HEAP_SIZE_NORMAL (RGX_FIRMWARE_RAW_HEAP_SIZE - RGX_FIRMWARE_CONFIG_HEAP_SIZE - \ + RGX_FIRMWARE_MIPS_GPU_MAP_RESERVED_SIZE_NORMAL) -#define RGX_FIRMWARE_MIPS_MAIN_HEAP_SIZE_BRN65101 (RGX_FIRMWARE_RAW_HEAP_SIZE - RGX_FIRMWARE_CONFIG_HEAP_SIZE - \ - RGX_FIRMWARE_MIPS_GPU_MAP_RESERVED_SIZE_BRN65101) +#define RGX_FIRMWARE_HOST_MIPS_MAIN_HEAP_SIZE_BRN65101 (RGX_FIRMWARE_RAW_HEAP_SIZE - RGX_FIRMWARE_CONFIG_HEAP_SIZE - \ + RGX_FIRMWARE_MIPS_GPU_MAP_RESERVED_SIZE_BRN65101) #if !defined(__KERNEL__) #if defined(FIX_HW_BRN_65101) #define RGX_FIRMWARE_MIPS_GPU_MAP_RESERVED_SIZE RGX_FIRMWARE_MIPS_GPU_MAP_RESERVED_SIZE_BRN65101 -#define RGX_FIRMWARE_MIPS_MAIN_HEAP_SIZE RGX_FIRMWARE_MIPS_MAIN_HEAP_SIZE_BRN65101 +#define RGX_FIRMWARE_HOST_MIPS_MAIN_HEAP_SIZE RGX_FIRMWARE_HOST_MIPS_MAIN_HEAP_SIZE_BRN65101 #include "img_defs.h" static_assert((RGX_FIRMWARE_RAW_HEAP_SIZE) >= IMG_UINT32_C(0x800000), "MIPS GPU map size cannot be increased due to BRN65101 with a small FW heap"); #else #define RGX_FIRMWARE_MIPS_GPU_MAP_RESERVED_SIZE RGX_FIRMWARE_MIPS_GPU_MAP_RESERVED_SIZE_NORMAL -#define RGX_FIRMWARE_MIPS_MAIN_HEAP_SIZE RGX_FIRMWARE_MIPS_MAIN_HEAP_SIZE_NORMAL +#define RGX_FIRMWARE_HOST_MIPS_MAIN_HEAP_SIZE RGX_FIRMWARE_HOST_MIPS_MAIN_HEAP_SIZE_NORMAL #endif #endif /* !defined(__KERNEL__) */ -/* Host sub-heap order: MAIN + CONFIG */ -#define RGX_FIRMWARE_HOST_MAIN_HEAP_BASE RGX_FIRMWARE_RAW_HEAP_BASE -#define RGX_FIRMWARE_HOST_CONFIG_HEAP_BASE (RGX_FIRMWARE_HOST_MAIN_HEAP_BASE + \ - RGX_FIRMWARE_RAW_HEAP_SIZE - \ - RGX_FIRMWARE_CONFIG_HEAP_SIZE) - -/* Guest sub-heap order: CONFIG + MAIN */ -#define RGX_FIRMWARE_GUEST_CONFIG_HEAP_BASE RGX_FIRMWARE_RAW_HEAP_BASE -#define RGX_FIRMWARE_GUEST_MAIN_HEAP_BASE (RGX_FIRMWARE_GUEST_CONFIG_HEAP_BASE + \ - RGX_FIRMWARE_CONFIG_HEAP_SIZE) +#define RGX_FIRMWARE_MAIN_HEAP_BASE RGX_FIRMWARE_RAW_HEAP_BASE +#define RGX_FIRMWARE_CONFIG_HEAP_BASE (RGX_FIRMWARE_MAIN_HEAP_BASE + \ + RGX_FIRMWARE_RAW_HEAP_SIZE - \ + RGX_FIRMWARE_CONFIG_HEAP_SIZE) /* * The maximum configurable size via RGX_FW_HEAP_SHIFT is 32MiB (1<<25) and diff --git a/drivers/gpu/drm/img-rogue/include/rgx_hwperf_common.h b/drivers/gpu/drm/img-rogue/include/rgx_hwperf_common.h new file mode 100644 index 000000000..0635a5157 --- /dev/null +++ b/drivers/gpu/drm/img-rogue/include/rgx_hwperf_common.h @@ -0,0 +1,482 @@ +/*************************************************************************/ /*! +@File +@Title RGX HWPerf and Debug Types and Defines Header +@Copyright Copyright (c) Imagination Technologies Ltd. All Rights Reserved +@Description Common data types definitions for hardware performance API +@License Dual MIT/GPLv2 + +The contents of this file are subject to the MIT license as set out below. + +Permission is hereby granted, free of charge, to any person obtaining a copy +of this software and associated documentation files (the "Software"), to deal +in the Software without restriction, including without limitation the rights +to use, copy, modify, merge, publish, distribute, sublicense, and/or sell +copies of the Software, and to permit persons to whom the Software is +furnished to do so, subject to the following conditions: + +The above copyright notice and this permission notice shall be included in +all copies or substantial portions of the Software. + +Alternatively, the contents of this file may be used under the terms of +the GNU General Public License Version 2 ("GPL") in which case the provisions +of GPL are applicable instead of those above. + +If you wish to allow use of your version of this file only under the terms of +GPL, and not to allow others to use your version of this file under the terms +of the MIT license, indicate your decision by deleting the provisions above +and replace them with the notice and other provisions required by GPL as set +out in the file called "GPL-COPYING" included in this distribution. If you do +not delete the provisions above, a recipient may use your version of this file +under the terms of either the MIT license or GPL. + +This License is also included in this distribution in the file called +"MIT-COPYING". + +EXCEPT AS OTHERWISE STATED IN A NEGOTIATED AGREEMENT: (A) THE SOFTWARE IS +PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING +BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR +PURPOSE AND NONINFRINGEMENT; AND (B) IN NO EVENT SHALL THE AUTHORS OR +COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER +IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN +CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +*/ /**************************************************************************/ +#ifndef RGX_HWPERF_COMMON_H_ +#define RGX_HWPERF_COMMON_H_ + +#if defined(__cplusplus) +extern "C" { +#endif + +/* These structures are used on both GPU and CPU and must be a size that is a + * multiple of 64 bits, 8 bytes to allow the FW to write 8 byte quantities at + * 8 byte aligned addresses. RGX_FW_STRUCT_*_ASSERT() is used to check this. + */ + +/****************************************************************************** + * Includes and Defines + *****************************************************************************/ + +#include "img_types.h" +#include "img_defs.h" + +#include "rgx_common_asserts.h" +#include "pvrsrv_tlcommon.h" + + +/****************************************************************************** + * Packet Event Type Enumerations + *****************************************************************************/ + +/*! Type used to encode the event that generated the packet. + * NOTE: When this type is updated the corresponding hwperfbin2json tool + * source needs to be updated as well. The RGX_HWPERF_EVENT_MASK_* macros will + * also need updating when adding new types. + * + * @par + * The event type values are incrementing integers for use as a shift ordinal + * in the event filtering process at the point events are generated. + * This scheme thus implies a limit of 63 event types. + */ + +typedef IMG_UINT32 RGX_HWPERF_EVENT_TYPE; + +#define RGX_HWPERF_INVALID 0x00U /*!< Invalid. Reserved value. */ + +/*! FW types 0x01..0x06 */ +#define RGX_HWPERF_FW_EVENT_RANGE_FIRST_TYPE 0x01U + +#define RGX_HWPERF_FW_BGSTART 0x01U /*!< Background task processing start */ +#define RGX_HWPERF_FW_BGEND 0x02U /*!< Background task end */ +#define RGX_HWPERF_FW_IRQSTART 0x03U /*!< IRQ task processing start */ + +#define RGX_HWPERF_FW_IRQEND 0x04U /*!< IRQ task end */ +#define RGX_HWPERF_FW_DBGSTART 0x05U /*!< Debug event start */ +#define RGX_HWPERF_FW_DBGEND 0x06U /*!< Debug event end */ + +#define RGX_HWPERF_FW_EVENT_RANGE_LAST_TYPE 0x06U + +/*! HW types 0x07..0x19 */ +#define RGX_HWPERF_HW_EVENT_RANGE0_FIRST_TYPE 0x07U + +#define RGX_HWPERF_HW_PMOOM_TAPAUSE 0x07U /*!< TA Pause at PM Out of Memory */ + +#define RGX_HWPERF_HW_TAKICK 0x08U /*!< TA task started */ +#define RGX_HWPERF_HW_TAFINISHED 0x09U /*!< TA task finished */ +#define RGX_HWPERF_HW_3DTQKICK 0x0AU /*!< 3D TQ started */ +#define RGX_HWPERF_HW_3DKICK 0x0BU /*!< 3D task started */ +#define RGX_HWPERF_HW_3DFINISHED 0x0CU /*!< 3D task finished */ +#define RGX_HWPERF_HW_CDMKICK 0x0DU /*!< CDM task started */ +#define RGX_HWPERF_HW_CDMFINISHED 0x0EU /*!< CDM task finished */ +#define RGX_HWPERF_HW_TLAKICK 0x0FU /*!< TLA task started */ +#define RGX_HWPERF_HW_TLAFINISHED 0x10U /*!< TLS task finished */ +#define RGX_HWPERF_HW_3DSPMKICK 0x11U /*!< 3D SPM task started */ +#define RGX_HWPERF_HW_PERIODIC 0x12U /*!< Periodic event with updated HW counters */ +#define RGX_HWPERF_HW_RTUKICK 0x13U /*!< Reserved, future use */ +#define RGX_HWPERF_HW_RTUFINISHED 0x14U /*!< Reserved, future use */ +#define RGX_HWPERF_HW_SHGKICK 0x15U /*!< Reserved, future use */ +#define RGX_HWPERF_HW_SHGFINISHED 0x16U /*!< Reserved, future use */ +#define RGX_HWPERF_HW_3DTQFINISHED 0x17U /*!< 3D TQ finished */ +#define RGX_HWPERF_HW_3DSPMFINISHED 0x18U /*!< 3D SPM task finished */ + +#define RGX_HWPERF_HW_PMOOM_TARESUME 0x19U /*!< TA Resume after PM Out of Memory */ + +/*! HW_EVENT_RANGE0 used up. Use next empty range below to add new hardware events */ +#define RGX_HWPERF_HW_EVENT_RANGE0_LAST_TYPE 0x19U + +/*! other types 0x1A..0x1F */ +#define RGX_HWPERF_CLKS_CHG 0x1AU /*!< Clock speed change in GPU */ +#define RGX_HWPERF_GPU_STATE_CHG 0x1BU /*!< GPU work state change */ + +/*! power types 0x20..0x27 */ +#define RGX_HWPERF_PWR_EST_RANGE_FIRST_TYPE 0x20U +#define RGX_HWPERF_PWR_EST_REQUEST 0x20U /*!< Power estimate requested (via GPIO) */ +#define RGX_HWPERF_PWR_EST_READY 0x21U /*!< Power estimate inputs ready */ +#define RGX_HWPERF_PWR_EST_RESULT 0x22U /*!< Power estimate result calculated */ +#define RGX_HWPERF_PWR_EST_RANGE_LAST_TYPE 0x22U + +#define RGX_HWPERF_PWR_CHG 0x23U /*!< Power state change */ + +/*! HW_EVENT_RANGE1 0x28..0x2F, for accommodating new hardware events */ +#define RGX_HWPERF_HW_EVENT_RANGE1_FIRST_TYPE 0x28U + +#define RGX_HWPERF_HW_TDMKICK 0x28U /*!< TDM task started */ +#define RGX_HWPERF_HW_TDMFINISHED 0x29U /*!< TDM task finished */ +#define RGX_HWPERF_HW_NULLKICK 0x2AU /*!< NULL event */ + +#define RGX_HWPERF_HW_EVENT_RANGE1_LAST_TYPE 0x2AU + +/*! context switch types 0x30..0x31 */ +#define RGX_HWPERF_CSW_START 0x30U /*!< HW context store started */ +#define RGX_HWPERF_CSW_FINISHED 0x31U /*!< HW context store finished */ + +/*! DVFS events */ +#define RGX_HWPERF_DVFS 0x32U /*!< Dynamic voltage/frequency scaling events */ + +/*! firmware misc 0x38..0x39 */ +#define RGX_HWPERF_UFO 0x38U /*!< FW UFO Check / Update */ +#define RGX_HWPERF_FWACT 0x39U /*!< FW Activity notification */ + +/*! last */ +#define RGX_HWPERF_LAST_TYPE 0x3BU + +/*! This enumeration must have a value that is a power of two as it is + * used in masks and a filter bit field (currently 64 bits long). + */ +#define RGX_HWPERF_MAX_TYPE 0x40U + +static_assert(RGX_HWPERF_LAST_TYPE < RGX_HWPERF_MAX_TYPE, "Too many HWPerf event types"); + +/*! Macro used to check if an event type ID is present in the known set of hardware type events */ +#define HWPERF_PACKET_IS_HW_TYPE(_etype) (((_etype) >= RGX_HWPERF_HW_EVENT_RANGE0_FIRST_TYPE && (_etype) <= RGX_HWPERF_HW_EVENT_RANGE0_LAST_TYPE) || \ + ((_etype) >= RGX_HWPERF_HW_EVENT_RANGE1_FIRST_TYPE && (_etype) <= RGX_HWPERF_HW_EVENT_RANGE1_LAST_TYPE)) + +/*! Macro used to check if an event type ID is present in the known set of firmware type events */ +#define HWPERF_PACKET_IS_FW_TYPE(_etype) \ + ((_etype) >= RGX_HWPERF_FW_EVENT_RANGE_FIRST_TYPE && \ + (_etype) <= RGX_HWPERF_FW_EVENT_RANGE_LAST_TYPE) + + +typedef enum { + RGX_HWPERF_HOST_INVALID = 0x00, /*!< Invalid, do not use. */ + RGX_HWPERF_HOST_ENQ = 0x01, /*!< ``0x01`` Kernel driver has queued GPU work. + See RGX_HWPERF_HOST_ENQ_DATA */ + RGX_HWPERF_HOST_UFO = 0x02, /*!< ``0x02`` UFO updated by the driver. + See RGX_HWPERF_HOST_UFO_DATA */ + RGX_HWPERF_HOST_ALLOC = 0x03, /*!< ``0x03`` Resource allocated. + See RGX_HWPERF_HOST_ALLOC_DATA */ + RGX_HWPERF_HOST_CLK_SYNC = 0x04, /*!< ``0x04`` GPU / Host clocks correlation data. + See RGX_HWPERF_HOST_CLK_SYNC_DATA */ + RGX_HWPERF_HOST_FREE = 0x05, /*!< ``0x05`` Resource freed, + See RGX_HWPERF_HOST_FREE_DATA */ + RGX_HWPERF_HOST_MODIFY = 0x06, /*!< ``0x06`` Resource modified / updated. + See RGX_HWPERF_HOST_MODIFY_DATA */ + RGX_HWPERF_HOST_DEV_INFO = 0x07, /*!< ``0x07`` Device Health status. + See RGX_HWPERF_HOST_DEV_INFO_DATA */ + RGX_HWPERF_HOST_INFO = 0x08, /*!< ``0x08`` Device memory usage information. + See RGX_HWPERF_HOST_INFO_DATA */ + RGX_HWPERF_HOST_SYNC_FENCE_WAIT = 0x09, /*!< ``0x09`` Wait for sync event. + See RGX_HWPERF_HOST_SYNC_FENCE_WAIT_DATA */ + RGX_HWPERF_HOST_SYNC_SW_TL_ADVANCE = 0x0A, /*!< ``0x0A`` Software timeline advanced. + See RGX_HWPERF_HOST_SYNC_SW_TL_ADV_DATA */ + RGX_HWPERF_HOST_CLIENT_INFO = 0x0B, /*!< ``0x0B`` Additional client info. + See RGX_HWPERF_HOST_CLIENT_INFO_DATA */ + + /*! last */ + RGX_HWPERF_HOST_LAST_TYPE, + + /*! This enumeration must have a value that is a power of two as it is + * used in masks and a filter bit field (currently 32 bits long). + */ + RGX_HWPERF_HOST_MAX_TYPE = 0x20 +} RGX_HWPERF_HOST_EVENT_TYPE; + +/*!< The event type values are incrementing integers for use as a shift ordinal + * in the event filtering process at the point events are generated. + * This scheme thus implies a limit of 31 event types. + */ +static_assert(RGX_HWPERF_HOST_LAST_TYPE < RGX_HWPERF_HOST_MAX_TYPE, "Too many HWPerf host event types"); + + +/****************************************************************************** + * Packet Header Format Version 2 Types + *****************************************************************************/ + +/*! Major version number of the protocol in operation + */ +#define RGX_HWPERF_V2_FORMAT 2 + +/*! Signature ASCII pattern 'HWP2' found in the first word of a HWPerfV2 packet + */ +#define HWPERF_PACKET_V2_SIG 0x48575032 + +/*! Signature ASCII pattern 'HWPA' found in the first word of a HWPerfV2a packet + */ +#define HWPERF_PACKET_V2A_SIG 0x48575041 + +/*! Signature ASCII pattern 'HWPB' found in the first word of a HWPerfV2b packet + */ +#define HWPERF_PACKET_V2B_SIG 0x48575042 + +/*! Signature ASCII pattern 'HWPC' found in the first word of a HWPerfV2c packet + */ +#define HWPERF_PACKET_V2C_SIG 0x48575043 + +#define HWPERF_PACKET_ISVALID(_val) (((_val) == HWPERF_PACKET_V2_SIG) || ((_val) == HWPERF_PACKET_V2A_SIG) || ((_val) == HWPERF_PACKET_V2B_SIG) || ((_val) == HWPERF_PACKET_V2C_SIG)) +/*!< Checks that the packet signature is one of the supported versions */ + +/*! Type defines the HWPerf packet header common to all events. */ +typedef struct +{ + IMG_UINT32 ui32Sig; /*!< Always the value HWPERF_PACKET_SIG */ + IMG_UINT32 ui32Size; /*!< Overall packet size in bytes */ + IMG_UINT32 eTypeId; /*!< Event type information field */ + IMG_UINT32 ui32Ordinal; /*!< Sequential number of the packet */ + IMG_UINT64 ui64Timestamp; /*!< Event timestamp */ +} RGX_HWPERF_V2_PACKET_HDR, *RGX_PHWPERF_V2_PACKET_HDR; + +RGX_FW_STRUCT_OFFSET_ASSERT(RGX_HWPERF_V2_PACKET_HDR, ui64Timestamp); + +RGX_FW_STRUCT_SIZE_ASSERT(RGX_HWPERF_V2_PACKET_HDR); + + +/*! Mask for use with the IMG_UINT32 ui32Size header field */ +#define RGX_HWPERF_SIZE_MASK 0xFFFFU + +/*! This macro defines an upper limit to which the size of the largest variable + * length HWPerf packet must fall within, currently 3KB. This constant may be + * used to allocate a buffer to hold one packet. + * This upper limit is policed by packet producing code. + */ +#define RGX_HWPERF_MAX_PACKET_SIZE 0xC00U + +/*! Defines an upper limit to the size of a variable length packet payload. + */ +#define RGX_HWPERF_MAX_PAYLOAD_SIZE ((IMG_UINT32)(RGX_HWPERF_MAX_PACKET_SIZE-\ + sizeof(RGX_HWPERF_V2_PACKET_HDR))) + +/*! Macro which takes a structure name and provides the packet size for + * a fixed size payload packet, rounded up to 8 bytes to align packets + * for 64 bit architectures. */ +#define RGX_HWPERF_MAKE_SIZE_FIXED(_struct) ((IMG_UINT32)(RGX_HWPERF_SIZE_MASK&(sizeof(RGX_HWPERF_V2_PACKET_HDR)+PVR_ALIGN(sizeof(_struct), PVRSRVTL_PACKET_ALIGNMENT)))) + +/*! Macro which takes the number of bytes written in the data payload of a + * packet for a variable size payload packet, rounded up to 8 bytes to + * align packets for 64 bit architectures. */ +#define RGX_HWPERF_MAKE_SIZE_VARIABLE(_size) ((IMG_UINT32)(RGX_HWPERF_SIZE_MASK&((IMG_UINT32)sizeof(RGX_HWPERF_V2_PACKET_HDR)+PVR_ALIGN((_size), PVRSRVTL_PACKET_ALIGNMENT)))) + +/*! Macro to obtain the size of the packet */ +#define RGX_HWPERF_GET_SIZE(_packet_addr) ((IMG_UINT16)(((_packet_addr)->ui32Size) & RGX_HWPERF_SIZE_MASK)) + +/*! Macro to obtain the size of the packet data */ +#define RGX_HWPERF_GET_DATA_SIZE(_packet_addr) (RGX_HWPERF_GET_SIZE(_packet_addr) - sizeof(RGX_HWPERF_V2_PACKET_HDR)) + +/*! Masks for use with the IMG_UINT32 eTypeId header field */ +#define RGX_HWPERF_TYPEID_MASK 0x0007FFFFU +#define RGX_HWPERF_TYPEID_EVENT_MASK 0x00007FFFU +#define RGX_HWPERF_TYPEID_THREAD_MASK 0x00008000U +#define RGX_HWPERF_TYPEID_STREAM_MASK 0x00070000U +#define RGX_HWPERF_TYPEID_META_DMA_MASK 0x00080000U +#define RGX_HWPERF_TYPEID_M_CORE_MASK 0x00100000U +#define RGX_HWPERF_TYPEID_OSID_MASK 0x07000000U + +/*! Meta thread macros for encoding the ID into the type field of a packet */ +#define RGX_HWPERF_META_THREAD_SHIFT 15U +#define RGX_HWPERF_META_THREAD_ID0 0x0U /*!< Meta Thread 0 ID */ +#define RGX_HWPERF_META_THREAD_ID1 0x1U /*!< Meta Thread 1 ID */ +/*! Obsolete, kept for source compatibility */ +#define RGX_HWPERF_META_THREAD_MASK 0x1U +/*! Stream ID macros for encoding the ID into the type field of a packet */ +#define RGX_HWPERF_STREAM_SHIFT 16U +/*! Meta DMA macro for encoding how the packet was generated into the type field of a packet */ +#define RGX_HWPERF_META_DMA_SHIFT 19U +/*! Bit-shift macro used for encoding multi-core data into the type field of a packet */ +#define RGX_HWPERF_M_CORE_SHIFT 20U +/*! OSID bit-shift macro used for encoding OSID into type field of a packet */ +#define RGX_HWPERF_OSID_SHIFT 24U +typedef enum { + RGX_HWPERF_STREAM_ID0_FW, /*!< Events from the Firmware/GPU */ + RGX_HWPERF_STREAM_ID1_HOST, /*!< Events from the Server host driver component */ + RGX_HWPERF_STREAM_ID2_CLIENT, /*!< Events from the Client host driver component */ + RGX_HWPERF_STREAM_ID_LAST, +} RGX_HWPERF_STREAM_ID; + +/* Checks if all stream IDs can fit under RGX_HWPERF_TYPEID_STREAM_MASK. */ +static_assert(((IMG_UINT32)RGX_HWPERF_STREAM_ID_LAST - 1U) < (RGX_HWPERF_TYPEID_STREAM_MASK >> RGX_HWPERF_STREAM_SHIFT), + "Too many HWPerf stream IDs."); + +/*! Compile-time value used to seed the Multi-Core (MC) bit in the typeID field. + * Only set by RGX_FIRMWARE builds. + */ +#if defined(RGX_FIRMWARE) +# if defined(RGX_FEATURE_GPU_MULTICORE_SUPPORT) +#define RGX_HWPERF_M_CORE_VALUE 1U /*!< 1 => Multi-core supported */ +# else +#define RGX_HWPERF_M_CORE_VALUE 0U /*!< 0 => Multi-core not supported */ +# endif +#else +#define RGX_HWPERF_M_CORE_VALUE 0U /*!< 0 => Multi-core not supported */ +#endif + +/*! Macros used to set the packet type and encode meta thread ID (0|1), + * HWPerf stream ID, multi-core capability and OSID within the typeID */ +#define RGX_HWPERF_MAKE_TYPEID(_stream, _type, _thread, _metadma, _osid)\ + ((IMG_UINT32) ((RGX_HWPERF_TYPEID_STREAM_MASK&((IMG_UINT32)(_stream) << RGX_HWPERF_STREAM_SHIFT)) | \ + (RGX_HWPERF_TYPEID_THREAD_MASK & ((IMG_UINT32)(_thread) << RGX_HWPERF_META_THREAD_SHIFT)) | \ + (RGX_HWPERF_TYPEID_EVENT_MASK & (IMG_UINT32)(_type)) | \ + (RGX_HWPERF_TYPEID_META_DMA_MASK & ((IMG_UINT32)(_metadma) << RGX_HWPERF_META_DMA_SHIFT)) | \ + (RGX_HWPERF_TYPEID_OSID_MASK & ((IMG_UINT32)(_osid) << RGX_HWPERF_OSID_SHIFT)) | \ + (RGX_HWPERF_TYPEID_M_CORE_MASK & ((IMG_UINT32)(RGX_HWPERF_M_CORE_VALUE) << RGX_HWPERF_M_CORE_SHIFT)))) + +/*! Obtains the event type that generated the packet */ +#define RGX_HWPERF_GET_TYPE(_packet_addr) (((_packet_addr)->eTypeId) & RGX_HWPERF_TYPEID_EVENT_MASK) + +/*! Obtains the META Thread number that generated the packet */ +#define RGX_HWPERF_GET_THREAD_ID(_packet_addr) (((((_packet_addr)->eTypeId) & RGX_HWPERF_TYPEID_THREAD_MASK) >> RGX_HWPERF_META_THREAD_SHIFT)) + +/*! Determines if the packet generated contains multi-core data */ +#define RGX_HWPERF_GET_M_CORE(_packet_addr) (((_packet_addr)->eTypeId & RGX_HWPERF_TYPEID_M_CORE_MASK) >> RGX_HWPERF_M_CORE_SHIFT) + +/*! Obtains the guest OSID which resulted in packet generation */ +#define RGX_HWPERF_GET_OSID(_packet_addr) (((_packet_addr)->eTypeId & RGX_HWPERF_TYPEID_OSID_MASK) >> RGX_HWPERF_OSID_SHIFT) + +/*! Obtain stream id */ +#define RGX_HWPERF_GET_STREAM_ID(_packet_addr) (((((_packet_addr)->eTypeId) & RGX_HWPERF_TYPEID_STREAM_MASK) >> RGX_HWPERF_STREAM_SHIFT)) + +/*! Obtain information about how the packet was generated, which might affect payload total size */ +#define RGX_HWPERF_GET_META_DMA_INFO(_packet_addr) (((((_packet_addr)->eTypeId) & RGX_HWPERF_TYPEID_META_DMA_MASK) >> RGX_HWPERF_META_DMA_SHIFT)) + +/*! Obtains a typed pointer to a packet given a buffer address */ +#define RGX_HWPERF_GET_PACKET(_buffer_addr) ((RGX_HWPERF_V2_PACKET_HDR *)(void *) (_buffer_addr)) +/*! Obtains a typed pointer to a data structure given a packet address */ +#define RGX_HWPERF_GET_PACKET_DATA_BYTES(_packet_addr) (IMG_OFFSET_ADDR((_packet_addr), sizeof(RGX_HWPERF_V2_PACKET_HDR))) +/*! Obtains a typed pointer to the next packet given a packet address */ +#define RGX_HWPERF_GET_NEXT_PACKET(_packet_addr) ((RGX_HWPERF_V2_PACKET_HDR *) (IMG_OFFSET_ADDR((_packet_addr), RGX_HWPERF_SIZE_MASK&((_packet_addr)->ui32Size)))) + +/*! Obtains a typed pointer to a packet header given the packet data address */ +#define RGX_HWPERF_GET_PACKET_HEADER(_packet_addr) ((RGX_HWPERF_V2_PACKET_HDR *) (IMG_OFFSET_ADDR((_packet_addr), -(IMG_INT32)sizeof(RGX_HWPERF_V2_PACKET_HDR)))) + + +/****************************************************************************** + * Other Common Defines + *****************************************************************************/ + +/*! This macro is not a real array size, but indicates the array has a variable + * length only known at run-time but always contains at least 1 element. The + * final size of the array is deduced from the size field of a packet header. + */ +#define RGX_HWPERF_ONE_OR_MORE_ELEMENTS 1U + +/*! This macro is not a real array size, but indicates the array is optional + * and if present has a variable length only known at run-time. The final + * size of the array is deduced from the size field of a packet header. */ +#define RGX_HWPERF_ZERO_OR_MORE_ELEMENTS 1U + + +/*! Masks for use with the IMG_UINT32 ui32BlkInfo field */ +#define RGX_HWPERF_BLKINFO_BLKCOUNT_MASK 0xFFFF0000U +#define RGX_HWPERF_BLKINFO_BLKOFFSET_MASK 0x0000FFFFU + +/*! Shift for the NumBlocks and counter block offset field in ui32BlkInfo */ +#define RGX_HWPERF_BLKINFO_BLKCOUNT_SHIFT 16U +#define RGX_HWPERF_BLKINFO_BLKOFFSET_SHIFT 0U + +/*! Macro used to set the block info word as a combination of two 16-bit integers */ +#define RGX_HWPERF_MAKE_BLKINFO(_numblks, _blkoffset) ((IMG_UINT32) ((RGX_HWPERF_BLKINFO_BLKCOUNT_MASK&((_numblks) << RGX_HWPERF_BLKINFO_BLKCOUNT_SHIFT)) | (RGX_HWPERF_BLKINFO_BLKOFFSET_MASK&((_blkoffset) << RGX_HWPERF_BLKINFO_BLKOFFSET_SHIFT)))) + +/*! Macro used to obtain the number of counter blocks present in the packet */ +#define RGX_HWPERF_GET_BLKCOUNT(_blkinfo) (((_blkinfo) & RGX_HWPERF_BLKINFO_BLKCOUNT_MASK) >> RGX_HWPERF_BLKINFO_BLKCOUNT_SHIFT) + +/*! Obtains the offset of the counter block stream in the packet */ +#define RGX_HWPERF_GET_BLKOFFSET(_blkinfo) (((_blkinfo) & RGX_HWPERF_BLKINFO_BLKOFFSET_MASK) >> RGX_HWPERF_BLKINFO_BLKOFFSET_SHIFT) + +/*! This macro gets the number of blocks depending on the packet version */ +#define RGX_HWPERF_GET_NUMBLKS(_sig, _packet_data, _numblocks) \ + do { \ + if (HWPERF_PACKET_V2B_SIG == (_sig) || HWPERF_PACKET_V2C_SIG == (_sig)) \ + { \ + (_numblocks) = RGX_HWPERF_GET_BLKCOUNT((_packet_data)->ui32BlkInfo);\ + } \ + else \ + { \ + IMG_UINT32 ui32VersionOffset = (((_sig) == HWPERF_PACKET_V2_SIG) ? 1 : 3);\ + (_numblocks) = *(IMG_UINT16 *)(IMG_OFFSET_ADDR(&(_packet_data)->ui32WorkTarget, ui32VersionOffset)); \ + } \ + } while (0) + +/*! This macro gets the counter stream pointer depending on the packet version */ +#define RGX_HWPERF_GET_CNTSTRM(_sig, _hw_packet_data, _cntstream_ptr) \ +{ \ + if (HWPERF_PACKET_V2B_SIG == (_sig) || HWPERF_PACKET_V2C_SIG == (_sig)) \ + { \ + (_cntstream_ptr) = (IMG_UINT32 *)(IMG_OFFSET_ADDR((_hw_packet_data), RGX_HWPERF_GET_BLKOFFSET((_hw_packet_data)->ui32BlkInfo))); \ + } \ + else \ + { \ + IMG_UINT32 ui32BlkStreamOffsetInWords = (((_sig) == HWPERF_PACKET_V2_SIG) ? 6 : 8); \ + (_cntstream_ptr) = (IMG_UINT32 *)(IMG_OFFSET_ADDR_DW((_hw_packet_data), ui32BlkStreamOffsetInWords)); \ + } \ +} + +/*! Masks for use with the IMG_UINT32 ui32KickInfo field */ +#define RGX_HWPERF_KICKINFO_KICKID_MASK 0x000000FFU + +/*! Shift for the Kick ID field in ui32KickInfo */ +#define RGX_HWPERF_KICKINFO_KICKID_SHIFT 0U + +/*! Macro used to set the kick info field. */ +#define RGX_HWPERF_MAKE_KICKINFO(_kickid) ((IMG_UINT32) (RGX_HWPERF_KICKINFO_KICKID_MASK&((_kickid) << RGX_HWPERF_KICKINFO_KICKID_SHIFT))) + +/*! Macro used to obtain the Kick ID if present in the packet */ +#define RGX_HWPERF_GET_KICKID(_kickinfo) (((_kickinfo) & RGX_HWPERF_KICKINFO_KICKID_MASK) >> RGX_HWPERF_KICKINFO_KICKID_SHIFT) + +/*! Masks for use with the RGX_HWPERF_UFO_EV eEvType field */ +#define RGX_HWPERF_UFO_STREAMSIZE_MASK 0xFFFF0000U +#define RGX_HWPERF_UFO_STREAMOFFSET_MASK 0x0000FFFFU + +/*! Shift for the UFO count and data stream fields */ +#define RGX_HWPERF_UFO_STREAMSIZE_SHIFT 16U +#define RGX_HWPERF_UFO_STREAMOFFSET_SHIFT 0U + +/*! Macro used to set UFO stream info word as a combination of two 16-bit integers */ +#define RGX_HWPERF_MAKE_UFOPKTINFO(_ssize, _soff) \ + ((IMG_UINT32) ((RGX_HWPERF_UFO_STREAMSIZE_MASK&((_ssize) << RGX_HWPERF_UFO_STREAMSIZE_SHIFT)) | \ + (RGX_HWPERF_UFO_STREAMOFFSET_MASK&((_soff) << RGX_HWPERF_UFO_STREAMOFFSET_SHIFT)))) + +/*! Macro used to obtain UFO count*/ +#define RGX_HWPERF_GET_UFO_STREAMSIZE(_streaminfo) \ + (((_streaminfo) & RGX_HWPERF_UFO_STREAMSIZE_MASK) >> RGX_HWPERF_UFO_STREAMSIZE_SHIFT) + +/*! Obtains the offset of the UFO stream in the packet */ +#define RGX_HWPERF_GET_UFO_STREAMOFFSET(_streaminfo) \ + (((_streaminfo) & RGX_HWPERF_UFO_STREAMOFFSET_MASK) >> RGX_HWPERF_UFO_STREAMOFFSET_SHIFT) + + +#if defined(__cplusplus) +} +#endif + +#endif /* RGX_HWPERF_COMMON_H_ */ + +/****************************************************************************** + End of file +******************************************************************************/ diff --git a/drivers/gpu/drm/img-rogue/include/rgx_meta.h b/drivers/gpu/drm/img-rogue/include/rgx_meta.h index e88d21308..bdff11ffb 100644 --- a/drivers/gpu/drm/img-rogue/include/rgx_meta.h +++ b/drivers/gpu/drm/img-rogue/include/rgx_meta.h @@ -74,7 +74,7 @@ CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. #define META_CR_PERF_COUNT_THR_SHIFT (24) #define META_CR_PERF_COUNT_THR_MASK (0x0F000000) #define META_CR_PERF_COUNT_THR_0 (IMG_UINT32_C(0x1) << META_CR_PERF_COUNT_THR_SHIFT) -#define META_CR_PERF_COUNT_THR_1 (IMG_UINT32_C(0x2) << META_CR_PERF_COUNT_THR_1) +#define META_CR_PERF_COUNT_THR_1 (IMG_UINT32_C(0x2) << META_CR_PERF_COUNT_THR_SHIFT) #define META_CR_TxVECINT_BHALT (0x04820500) #define META_CR_PERF_ICORE0 (0x0480FFD0) @@ -248,11 +248,11 @@ typedef struct * The interface has been kept the same to simplify the code changes. * The bifdm argument is ignored (no longer relevant) in S7 and volcanic. */ -#define RGXFW_SEGMMU_OUTADDR_TOP_VIVT_SLC(pers, slc_policy, mmu_ctx) ((((IMG_UINT64) ((pers) & 0x3)) << 52) | \ - (((IMG_UINT64) ((mmu_ctx) & 0xFF)) << 44) | \ - (((IMG_UINT64) ((slc_policy) & 0x1)) << 40)) -#define RGXFW_SEGMMU_OUTADDR_TOP_VIVT_SLC_CACHED(mmu_ctx) RGXFW_SEGMMU_OUTADDR_TOP_VIVT_SLC(0x3, 0x0, mmu_ctx) -#define RGXFW_SEGMMU_OUTADDR_TOP_VIVT_SLC_UNCACHED(mmu_ctx) RGXFW_SEGMMU_OUTADDR_TOP_VIVT_SLC(0x0, 0x1, mmu_ctx) +#define RGXFW_SEGMMU_OUTADDR_TOP_VIVT_SLC(pers, slc_policy, mmu_ctx) ((((IMG_UINT64) ((pers) & 0x3U)) << 52) | \ + (((IMG_UINT64) ((mmu_ctx) & 0xFFU)) << 44) | \ + (((IMG_UINT64) ((slc_policy) & 0x1U)) << 40)) +#define RGXFW_SEGMMU_OUTADDR_TOP_VIVT_SLC_CACHED(mmu_ctx) RGXFW_SEGMMU_OUTADDR_TOP_VIVT_SLC(0x3U, 0x0U, mmu_ctx) +#define RGXFW_SEGMMU_OUTADDR_TOP_VIVT_SLC_UNCACHED(mmu_ctx) RGXFW_SEGMMU_OUTADDR_TOP_VIVT_SLC(0x0U, 0x1U, mmu_ctx) /* To configure the Page Catalog and BIF-DM fed into the BIF for Garten * accesses through this segment diff --git a/drivers/gpu/drm/img-rogue/include/rgx_mips.h b/drivers/gpu/drm/img-rogue/include/rgx_mips.h index d3947127f..c2f381882 100644 --- a/drivers/gpu/drm/img-rogue/include/rgx_mips.h +++ b/drivers/gpu/drm/img-rogue/include/rgx_mips.h @@ -72,7 +72,7 @@ CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. /* Total number of TLB entries */ #define RGXMIPSFW_NUMBER_OF_TLB_ENTRIES (16) /* "Uncached" caching policy */ -#define RGXMIPSFW_UNCACHED_CACHE_POLICY (0X00000002) +#define RGXMIPSFW_UNCACHED_CACHE_POLICY (0X00000002U) /* "Write-back write-allocate" caching policy */ #define RGXMIPSFW_WRITEBACK_CACHE_POLICY (0X00000003) /* "Write-through no write-allocate" caching policy */ @@ -91,11 +91,11 @@ CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. #define RGXMIPSFW_ENTRYLO_READ_INHIBIT_SHIFT (31U) #define RGXMIPSFW_ENTRYLO_READ_INHIBIT_CLRMSK (0X7FFFFFFF) -#define RGXMIPSFW_ENTRYLO_READ_INHIBIT_EN (0X80000000) +#define RGXMIPSFW_ENTRYLO_READ_INHIBIT_EN (0X80000000U) #define RGXMIPSFW_ENTRYLO_EXEC_INHIBIT_SHIFT (30U) #define RGXMIPSFW_ENTRYLO_EXEC_INHIBIT_CLRMSK (0XBFFFFFFF) -#define RGXMIPSFW_ENTRYLO_EXEC_INHIBIT_EN (0X40000000) +#define RGXMIPSFW_ENTRYLO_EXEC_INHIBIT_EN (0X40000000U) /* Page Frame Number */ #define RGXMIPSFW_ENTRYLO_PFN_SHIFT (6) @@ -104,25 +104,25 @@ CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. #define RGXMIPSFW_ENTRYLO_PFN_MASK (0x03FFFFC0) #define RGXMIPSFW_ENTRYLO_PFN_SIZE (20) /* Mask used for the MIPS Page Table in case of physical bus on more than 32 bit */ -#define RGXMIPSFW_ENTRYLO_PFN_MASK_ABOVE_32BIT (0x3FFFFFC0) +#define RGXMIPSFW_ENTRYLO_PFN_MASK_ABOVE_32BIT (0x3FFFFFC0U) #define RGXMIPSFW_ENTRYLO_PFN_SIZE_ABOVE_32BIT (24) #define RGXMIPSFW_ADDR_TO_ENTRYLO_PFN_RSHIFT (RGXMIPSFW_ENTRYLO_PFN_ALIGNSHIFT - \ RGXMIPSFW_ENTRYLO_PFN_SHIFT) #define RGXMIPSFW_ENTRYLO_CACHE_POLICY_SHIFT (3U) -#define RGXMIPSFW_ENTRYLO_CACHE_POLICY_CLRMSK (0XFFFFFFC7) +#define RGXMIPSFW_ENTRYLO_CACHE_POLICY_CLRMSK (0XFFFFFFC7U) #define RGXMIPSFW_ENTRYLO_DIRTY_SHIFT (2U) #define RGXMIPSFW_ENTRYLO_DIRTY_CLRMSK (0XFFFFFFFB) -#define RGXMIPSFW_ENTRYLO_DIRTY_EN (0X00000004) +#define RGXMIPSFW_ENTRYLO_DIRTY_EN (0X00000004U) #define RGXMIPSFW_ENTRYLO_VALID_SHIFT (1U) #define RGXMIPSFW_ENTRYLO_VALID_CLRMSK (0XFFFFFFFD) -#define RGXMIPSFW_ENTRYLO_VALID_EN (0X00000002) +#define RGXMIPSFW_ENTRYLO_VALID_EN (0X00000002U) #define RGXMIPSFW_ENTRYLO_GLOBAL_SHIFT (0U) #define RGXMIPSFW_ENTRYLO_GLOBAL_CLRMSK (0XFFFFFFFE) -#define RGXMIPSFW_ENTRYLO_GLOBAL_EN (0X00000001) +#define RGXMIPSFW_ENTRYLO_GLOBAL_EN (0X00000001U) #define RGXMIPSFW_ENTRYLO_DVG (RGXMIPSFW_ENTRYLO_DIRTY_EN | \ RGXMIPSFW_ENTRYLO_VALID_EN | \ @@ -158,14 +158,14 @@ CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. */ #define RGXMIPSFW_TRAMPOLINE_LOG2_NUMPAGES (2) -#define RGXMIPSFW_TRAMPOLINE_NUMPAGES (1 << RGXMIPSFW_TRAMPOLINE_LOG2_NUMPAGES) +#define RGXMIPSFW_TRAMPOLINE_NUMPAGES (1U << RGXMIPSFW_TRAMPOLINE_LOG2_NUMPAGES) #define RGXMIPSFW_TRAMPOLINE_SIZE (RGXMIPSFW_TRAMPOLINE_NUMPAGES << RGXMIPSFW_LOG2_PAGE_SIZE_4K) #define RGXMIPSFW_TRAMPOLINE_LOG2_SEGMENT_SIZE (RGXMIPSFW_TRAMPOLINE_LOG2_NUMPAGES + RGXMIPSFW_LOG2_PAGE_SIZE_4K) #define RGXMIPSFW_TRAMPOLINE_TARGET_PHYS_ADDR (RGXMIPSFW_BOOT_REMAP_PHYS_ADDR_IN) #define RGXMIPSFW_TRAMPOLINE_OFFSET(a) (a - RGXMIPSFW_BOOT_REMAP_PHYS_ADDR_IN) -#define RGXMIPSFW_SENSITIVE_ADDR(a) (RGXMIPSFW_BOOT_REMAP_PHYS_ADDR_IN == (~((1UL << RGXMIPSFW_TRAMPOLINE_LOG2_SEGMENT_SIZE)-1) & a)) +#define RGXMIPSFW_SENSITIVE_ADDR(a) (RGXMIPSFW_BOOT_REMAP_PHYS_ADDR_IN == (~((1UL << RGXMIPSFW_TRAMPOLINE_LOG2_SEGMENT_SIZE)-1U) & a)) /* * Firmware virtual layout and remap configuration @@ -183,20 +183,20 @@ CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. /* Boot remap setup */ #define RGXMIPSFW_BOOT_REMAP_VIRTUAL_BASE (0xBFC00000) -#define RGXMIPSFW_BOOT_REMAP_PHYS_ADDR_IN (0x1FC00000) +#define RGXMIPSFW_BOOT_REMAP_PHYS_ADDR_IN (0x1FC00000U) #define RGXMIPSFW_BOOT_REMAP_LOG2_SEGMENT_SIZE (12) #define RGXMIPSFW_BOOT_NMI_CODE_VIRTUAL_BASE (RGXMIPSFW_BOOT_REMAP_VIRTUAL_BASE) /* Data remap setup */ #define RGXMIPSFW_DATA_REMAP_VIRTUAL_BASE (0xBFC01000) #define RGXMIPSFW_DATA_CACHED_REMAP_VIRTUAL_BASE (0x9FC01000) -#define RGXMIPSFW_DATA_REMAP_PHYS_ADDR_IN (0x1FC01000) +#define RGXMIPSFW_DATA_REMAP_PHYS_ADDR_IN (0x1FC01000U) #define RGXMIPSFW_DATA_REMAP_LOG2_SEGMENT_SIZE (12) #define RGXMIPSFW_BOOT_NMI_DATA_VIRTUAL_BASE (RGXMIPSFW_DATA_REMAP_VIRTUAL_BASE) /* Code remap setup */ #define RGXMIPSFW_CODE_REMAP_VIRTUAL_BASE (0x9FC02000) -#define RGXMIPSFW_CODE_REMAP_PHYS_ADDR_IN (0x1FC02000) +#define RGXMIPSFW_CODE_REMAP_PHYS_ADDR_IN (0x1FC02000U) #define RGXMIPSFW_CODE_REMAP_LOG2_SEGMENT_SIZE (12) #define RGXMIPSFW_EXCEPTIONS_VIRTUAL_BASE (RGXMIPSFW_CODE_REMAP_VIRTUAL_BASE) @@ -211,7 +211,7 @@ CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. */ /* Bootloader configuration offset (where RGXMIPSFW_BOOT_DATA lives) * within the bootloader/NMI data page */ -#define RGXMIPSFW_BOOTLDR_CONF_OFFSET (0x0) +#define RGXMIPSFW_BOOTLDR_CONF_OFFSET (0x0U) /* @@ -292,10 +292,10 @@ typedef struct #define RGXMIPSFW_C0_NBHWIRQ 8 /* Macros to decode C0_Cause register */ -#define RGXMIPSFW_C0_CAUSE_EXCCODE(CAUSE) (((CAUSE) & 0x7c) >> 2) +#define RGXMIPSFW_C0_CAUSE_EXCCODE(CAUSE) (((CAUSE) & 0x7cU) >> 2U) #define RGXMIPSFW_C0_CAUSE_EXCCODE_FWERROR 9 /* Use only when Coprocessor Unusable exception */ -#define RGXMIPSFW_C0_CAUSE_UNUSABLE_UNIT(CAUSE) (((CAUSE) >> 28) & 0x3) +#define RGXMIPSFW_C0_CAUSE_UNUSABLE_UNIT(CAUSE) (((CAUSE) >> 28U) & 0x3U) #define RGXMIPSFW_C0_CAUSE_PENDING_HWIRQ(CAUSE) (((CAUSE) & 0x3fc00) >> 10) #define RGXMIPSFW_C0_CAUSE_FDCIPENDING (1UL << 21) #define RGXMIPSFW_C0_CAUSE_IV (1UL << 23) @@ -305,7 +305,7 @@ typedef struct #define RGXMIPSFW_C0_CAUSE_BRANCH_DELAY (1UL << 31) /* Macros to decode C0_Debug register */ -#define RGXMIPSFW_C0_DEBUG_EXCCODE(DEBUG) (((DEBUG) >> 10) & 0x1f) +#define RGXMIPSFW_C0_DEBUG_EXCCODE(DEBUG) (((DEBUG) >> 10U) & 0x1fU) #define RGXMIPSFW_C0_DEBUG_DSS (1UL << 0) #define RGXMIPSFW_C0_DEBUG_DBP (1UL << 1) #define RGXMIPSFW_C0_DEBUG_DDBL (1UL << 2) @@ -325,7 +325,7 @@ typedef struct /* Macros to decode TLB entries */ #define RGXMIPSFW_TLB_GET_MASK(PAGE_MASK) (((PAGE_MASK) >> 13) & 0XFFFFU) -#define RGXMIPSFW_TLB_GET_PAGE_SIZE(PAGE_MASK) ((((PAGE_MASK) | 0x1FFF) + 1) >> 11) /* page size in KB */ +#define RGXMIPSFW_TLB_GET_PAGE_SIZE(PAGE_MASK) ((((PAGE_MASK) | 0x1FFFU) + 1U) >> 11U) /* page size in KB */ #define RGXMIPSFW_TLB_GET_PAGE_MASK(PAGE_SIZE) ((((PAGE_SIZE) << 11) - 1) & ~0x7FF) /* page size in KB */ #define RGXMIPSFW_TLB_GET_VPN2(ENTRY_HI) ((ENTRY_HI) >> 13) #define RGXMIPSFW_TLB_GET_COHERENCY(ENTRY_LO) (((ENTRY_LO) >> 3) & 0x7U) diff --git a/drivers/gpu/drm/img-rogue/include/rgx_riscv.h b/drivers/gpu/drm/img-rogue/include/rgx_riscv.h index 1ce9ab569..e5be2a562 100644 --- a/drivers/gpu/drm/img-rogue/include/rgx_riscv.h +++ b/drivers/gpu/drm/img-rogue/include/rgx_riscv.h @@ -76,7 +76,7 @@ CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. #define RGXRISCVFW_COREMEM_REGION IMG_UINT32_C(0x8) #define RGXRISCVFW_COREMEM_MAX_SIZE IMG_UINT32_C(0x10000000) /* 256 MB */ #define RGXRISCVFW_COREMEM_BASE (RGXRISCVFW_GET_REGION_BASE(RGXRISCVFW_COREMEM_REGION)) -#define RGXRISCVFW_COREMEM_END (RGXRISCVFW_COREMEM_BASE + RGXRISCVFW_COREMEM_MAX_SIZE - 1) +#define RGXRISCVFW_COREMEM_END (RGXRISCVFW_COREMEM_BASE + RGXRISCVFW_COREMEM_MAX_SIZE - 1U) /* diff --git a/drivers/gpu/drm/img-rogue/include/rogue/rgx_fwif_hwperf.h b/drivers/gpu/drm/img-rogue/include/rogue/rgx_fwif_hwperf.h index a75a07b55..7001092c7 100644 --- a/drivers/gpu/drm/img-rogue/include/rogue/rgx_fwif_hwperf.h +++ b/drivers/gpu/drm/img-rogue/include/rogue/rgx_fwif_hwperf.h @@ -68,6 +68,20 @@ typedef struct IMG_UINT32 aui32SelectedCountersIDs[RGX_HWPERF_MAX_CUSTOM_CNTRS]; } RGXFW_HWPERF_SELECT; +/* Structure used to hold a Direct-Addressable block's parameters for passing + * between the BG context and the IRQ context when applying a configuration + * request. RGX_FEATURE_HWPERF_OCEANIC use only. + */ +typedef struct +{ + IMG_UINT32 uiEnabled; + IMG_UINT32 uiNumCounters; + IMG_UINT32 eBlockID; + RGXFWIF_DEV_VIRTADDR psModel; + IMG_UINT32 aui32Counters[RGX_CNTBLK_COUNTERS_MAX]; +} RGXFWIF_HWPERF_DA_BLK; + + /* Structure to hold the whole configuration request details for all blocks * The block masks and counts are used to optimise reading of this data. */ typedef struct @@ -77,8 +91,8 @@ typedef struct IMG_UINT32 ui32SelectedCountersBlockMask; RGXFW_HWPERF_SELECT RGXFW_ALIGN SelCntr[RGX_HWPERF_MAX_CUSTOM_BLKS]; - IMG_UINT32 ui32EnabledBlksCount; - RGXFWIF_HWPERF_CTL_BLK RGXFW_ALIGN sBlkCfg[RGX_HWPERF_MAX_DEFINED_BLKS]; + IMG_UINT32 ui32EnabledMUXBlksCount; + RGXFWIF_HWPERF_CTL_BLK RGXFW_ALIGN sBlkCfg[RGX_HWPERF_MAX_MUX_BLKS]; } UNCACHED_ALIGN RGXFWIF_HWPERF_CTL; /* NOTE: The switch statement in this function must be kept in alignment with @@ -90,7 +104,7 @@ typedef struct #ifdef INLINE_IS_PRAGMA #pragma inline(rgxfw_hwperf_get_block_ctl) #endif -static INLINE RGXFWIF_HWPERF_CTL_BLK* rgxfw_hwperf_get_block_ctl( +static INLINE RGXFWIF_HWPERF_CTL_BLK *rgxfw_hwperf_get_block_ctl( RGX_HWPERF_CNTBLK_ID eBlockID, RGXFWIF_HWPERF_CTL *psHWPerfInitData) { IMG_UINT32 ui32Idx; @@ -221,4 +235,18 @@ static INLINE RGXFWIF_HWPERF_CTL_BLK* rgxfw_hwperf_get_block_ctl( return &psHWPerfInitData->sBlkCfg[ui32Idx]; } +/* Stub routine for rgxfw_hwperf_get_da_block_ctl() for non + * RGX_FEATURE_HWPERF_OCEANIC systems. Just return a NULL. + */ +#ifdef INLINE_IS_PRAGMA +#pragma inline(rgxfw_hwperf_get_da_block_ctl) +#endif +static INLINE RGXFWIF_HWPERF_DA_BLK* rgxfw_hwperf_get_da_block_ctl( + RGX_HWPERF_CNTBLK_ID eBlockID, RGXFWIF_HWPERF_CTL *psHWPerfInitData) +{ + PVR_UNREFERENCED_PARAMETER(eBlockID); + PVR_UNREFERENCED_PARAMETER(psHWPerfInitData); + + return NULL; +} #endif diff --git a/drivers/gpu/drm/img-rogue/include/rogue/rgx_fwif_km.h b/drivers/gpu/drm/img-rogue/include/rogue/rgx_fwif_km.h index 16f5cd489..724f6eecd 100644 --- a/drivers/gpu/drm/img-rogue/include/rogue/rgx_fwif_km.h +++ b/drivers/gpu/drm/img-rogue/include/rogue/rgx_fwif_km.h @@ -109,21 +109,21 @@ typedef struct { #define RGXFWIF_LOG_ENABLED_GROUPS_LIST_PFSPEC "%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s" /* Used in a print statement to display log group state, one per group */ -#define RGXFWIF_LOG_ENABLED_GROUPS_LIST(types) (((types) & RGXFWIF_LOG_TYPE_GROUP_MAIN) ?("main ") :("")), \ - (((types) & RGXFWIF_LOG_TYPE_GROUP_MTS) ?("mts ") :("")), \ - (((types) & RGXFWIF_LOG_TYPE_GROUP_CLEANUP) ?("cleanup ") :("")), \ - (((types) & RGXFWIF_LOG_TYPE_GROUP_CSW) ?("csw ") :("")), \ - (((types) & RGXFWIF_LOG_TYPE_GROUP_BIF) ?("bif ") :("")), \ - (((types) & RGXFWIF_LOG_TYPE_GROUP_PM) ?("pm ") :("")), \ - (((types) & RGXFWIF_LOG_TYPE_GROUP_RTD) ?("rtd ") :("")), \ - (((types) & RGXFWIF_LOG_TYPE_GROUP_SPM) ?("spm ") :("")), \ - (((types) & RGXFWIF_LOG_TYPE_GROUP_POW) ?("pow ") :("")), \ - (((types) & RGXFWIF_LOG_TYPE_GROUP_HWR) ?("hwr ") :("")), \ - (((types) & RGXFWIF_LOG_TYPE_GROUP_HWP) ?("hwp ") :("")), \ - (((types) & RGXFWIF_LOG_TYPE_GROUP_RPM) ?("rpm ") :("")), \ - (((types) & RGXFWIF_LOG_TYPE_GROUP_DMA) ?("dma ") :("")), \ - (((types) & RGXFWIF_LOG_TYPE_GROUP_MISC) ?("misc ") :("")), \ - (((types) & RGXFWIF_LOG_TYPE_GROUP_DEBUG) ?("debug ") :("")) +#define RGXFWIF_LOG_ENABLED_GROUPS_LIST(types) ((((types) & RGXFWIF_LOG_TYPE_GROUP_MAIN) != 0U) ?("main ") :("")), \ + ((((types) & RGXFWIF_LOG_TYPE_GROUP_MTS) != 0U) ?("mts ") :("")), \ + ((((types) & RGXFWIF_LOG_TYPE_GROUP_CLEANUP) != 0U) ?("cleanup ") :("")), \ + ((((types) & RGXFWIF_LOG_TYPE_GROUP_CSW) != 0U) ?("csw ") :("")), \ + ((((types) & RGXFWIF_LOG_TYPE_GROUP_BIF) != 0U) ?("bif ") :("")), \ + ((((types) & RGXFWIF_LOG_TYPE_GROUP_PM) != 0U) ?("pm ") :("")), \ + ((((types) & RGXFWIF_LOG_TYPE_GROUP_RTD) != 0U) ?("rtd ") :("")), \ + ((((types) & RGXFWIF_LOG_TYPE_GROUP_SPM) != 0U) ?("spm ") :("")), \ + ((((types) & RGXFWIF_LOG_TYPE_GROUP_POW) != 0U) ?("pow ") :("")), \ + ((((types) & RGXFWIF_LOG_TYPE_GROUP_HWR) != 0U) ?("hwr ") :("")), \ + ((((types) & RGXFWIF_LOG_TYPE_GROUP_HWP) != 0U) ?("hwp ") :("")), \ + ((((types) & RGXFWIF_LOG_TYPE_GROUP_RPM) != 0U) ?("rpm ") :("")), \ + ((((types) & RGXFWIF_LOG_TYPE_GROUP_DMA) != 0U) ?("dma ") :("")), \ + ((((types) & RGXFWIF_LOG_TYPE_GROUP_MISC) != 0U) ?("misc ") :("")), \ + ((((types) & RGXFWIF_LOG_TYPE_GROUP_DEBUG) != 0U) ?("debug ") :("")) /************************************************************************ @@ -156,20 +156,31 @@ typedef struct IMG_UINT32 ui32LineNum; } UNCACHED_ALIGN RGXFWIF_FILE_INFO_BUF; +/*! + * @Defgroup SRVAndFWTracing Services and Firmware Tracing data interface + * @Brief The document groups/lists the data structures and the interfaces related to Services and Firmware Tracing + * @{ + */ + +/*! + * @Brief Firmware trace buffer details + */ typedef struct { - IMG_UINT32 ui32TracePointer; + IMG_UINT32 ui32TracePointer; /*!< Trace pointer (write index into Trace Buffer)*/ #if defined(RGX_FIRMWARE) - IMG_UINT32 *pui32RGXFWIfTraceBuffer; /* To be used by firmware for writing into trace buffer */ + IMG_UINT32 *pui32RGXFWIfTraceBuffer; /*!< Trace buffer address (FW address), to be used by firmware for writing into trace buffer */ #else - RGXFWIF_DEV_VIRTADDR pui32RGXFWIfTraceBuffer; + RGXFWIF_DEV_VIRTADDR pui32RGXFWIfTraceBuffer; /*!< Trace buffer address (FW address)*/ #endif - IMG_PUINT32 pui32TraceBuffer; /* To be used by host when reading from trace buffer */ + IMG_PUINT32 pui32TraceBuffer; /*!< Trace buffer address (Host address), to be used by host when reading from trace buffer */ - RGXFWIF_FILE_INFO_BUF sAssertBuf; + RGXFWIF_FILE_INFO_BUF sAssertBuf; } UNCACHED_ALIGN RGXFWIF_TRACEBUF_SPACE; +/*! @} End of Defgroup SRVAndFWTracing */ + #define RGXFWIF_FWFAULTINFO_MAX (8U) /* Total number of FW fault logs stored */ typedef struct @@ -229,14 +240,12 @@ typedef IMG_UINT32 RGXFWIF_HWR_STATEFLAGS; #define RGXFWIF_DM_STATE_GPU_ECC_HWR (IMG_UINT32_C(0x1) << 10) /*!< DM was forced into HWR due to an uncorrected GPU ECC error */ /* Firmware's connection state */ -typedef enum -{ - RGXFW_CONNECTION_FW_OFFLINE = 0, /*!< Firmware is offline */ - RGXFW_CONNECTION_FW_READY, /*!< Firmware is initialised */ - RGXFW_CONNECTION_FW_ACTIVE, /*!< Firmware connection is fully established */ - RGXFW_CONNECTION_FW_OFFLOADING, /*!< Firmware is clearing up connection data */ - RGXFW_CONNECTION_FW_STATE_COUNT -} RGXFWIF_CONNECTION_FW_STATE; +typedef IMG_UINT32 RGXFWIF_CONNECTION_FW_STATE; +#define RGXFW_CONNECTION_FW_OFFLINE 0U /*!< Firmware is offline */ +#define RGXFW_CONNECTION_FW_READY 1U /*!< Firmware is initialised */ +#define RGXFW_CONNECTION_FW_ACTIVE 2U /*!< Firmware connection is fully established */ +#define RGXFW_CONNECTION_FW_OFFLOADING 3U /*!< Firmware is clearing up connection data */ +#define RGXFW_CONNECTION_FW_STATE_COUNT 4U /* OS' connection state */ typedef enum @@ -259,7 +268,7 @@ typedef struct typedef IMG_UINT32 RGXFWIF_HWR_RECOVERYFLAGS; #if defined(PVRSRV_STALLED_CCB_ACTION) -#define PVR_SLR_LOG_ENTRIES 10 +#define PVR_SLR_LOG_ENTRIES 10U #define PVR_SLR_LOG_STRLEN 30 /*!< MAX_CLIENT_CCB_NAME not visible to this header */ typedef struct @@ -271,14 +280,17 @@ typedef struct } UNCACHED_ALIGN RGXFWIF_SLR_ENTRY; #endif -/* firmware trace control data */ +/*! + * @InGroup SRVAndFWTracing + * @Brief Firmware trace control data + */ typedef struct { - IMG_UINT32 ui32LogType; - RGXFWIF_TRACEBUF_SPACE sTraceBuf[RGXFW_THREAD_NUM]; - IMG_UINT32 ui32TraceBufSizeInDWords; /*!< Member initialised only when sTraceBuf is actually allocated - * (in RGXTraceBufferInitOnDemandResources) */ - IMG_UINT32 ui32TracebufFlags; /*!< Compatibility and other flags */ + IMG_UINT32 ui32LogType; /*!< FW trace log group configuration */ + RGXFWIF_TRACEBUF_SPACE sTraceBuf[RGXFW_THREAD_NUM]; /*!< FW Trace buffer */ + IMG_UINT32 ui32TraceBufSizeInDWords; /*!< FW Trace buffer size in dwords, Member initialised only when sTraceBuf is actually allocated + (in RGXTraceBufferInitOnDemandResources) */ + IMG_UINT32 ui32TracebufFlags; /*!< Compatibility and other flags */ } UNCACHED_ALIGN RGXFWIF_TRACEBUF; /*! @Brief Firmware system data shared with the Host driver */ @@ -320,6 +332,7 @@ typedef struct RGXFWIF_HWR_STATEFLAGS ui32HWRStateFlags; /*!< Firmware's Current HWR state */ RGXFWIF_HWR_RECOVERYFLAGS aui32HWRRecoveryFlags[RGXFWIF_DM_MAX]; /*!< Each DM's HWR state */ IMG_UINT32 ui32FwSysDataFlags; /*!< Compatibility and other flags */ + IMG_UINT32 ui32McConfig; /*!< Identify whether MC config is P-P or P-S */ } UNCACHED_ALIGN RGXFWIF_SYSDATA; /*! @@ -533,18 +546,13 @@ typedef struct #define RGXFWIF_INICFG_FBCDC_V3_1_EN (IMG_UINT32_C(0x1) << 6) #define RGXFWIF_INICFG_CHECK_MLIST_EN (IMG_UINT32_C(0x1) << 7) #define RGXFWIF_INICFG_DISABLE_CLKGATING_EN (IMG_UINT32_C(0x1) << 8) -#define RGXFWIF_INICFG_POLL_COUNTERS_EN (IMG_UINT32_C(0x1) << 9) -#define RGXFWIF_INICFG_VDM_CTX_STORE_MODE_SHIFT (10) -#define RGXFWIF_INICFG_VDM_CTX_STORE_MODE_INDEX ((IMG_UINT32)RGX_CR_VDM_CONTEXT_STORE_MODE_MODE_INDEX << RGXFWIF_INICFG_VDM_CTX_STORE_MODE_SHIFT) -#define RGXFWIF_INICFG_VDM_CTX_STORE_MODE_INSTANCE ((IMG_UINT32)RGX_CR_VDM_CONTEXT_STORE_MODE_MODE_INSTANCE << RGXFWIF_INICFG_VDM_CTX_STORE_MODE_SHIFT) -#define RGXFWIF_INICFG_VDM_CTX_STORE_MODE_LIST ((IMG_UINT32)RGX_CR_VDM_CONTEXT_STORE_MODE_MODE_LIST << RGXFWIF_INICFG_VDM_CTX_STORE_MODE_SHIFT) -#define RGXFWIF_INICFG_VDM_CTX_STORE_MODE_MASK (RGXFWIF_INICFG_VDM_CTX_STORE_MODE_INDEX |\ - RGXFWIF_INICFG_VDM_CTX_STORE_MODE_INSTANCE |\ - RGXFWIF_INICFG_VDM_CTX_STORE_MODE_LIST) +/* 9 unused */ +/* 10 unused */ +/* 11 unused */ #define RGXFWIF_INICFG_REGCONFIG_EN (IMG_UINT32_C(0x1) << 12) #define RGXFWIF_INICFG_ASSERT_ON_OUTOFMEMORY (IMG_UINT32_C(0x1) << 13) #define RGXFWIF_INICFG_HWP_DISABLE_FILTER (IMG_UINT32_C(0x1) << 14) -#define RGXFWIF_INICFG_CUSTOM_PERF_TIMER_EN (IMG_UINT32_C(0x1) << 15) +/* 15 unused */ #define RGXFWIF_INICFG_CTXSWITCH_PROFILE_SHIFT (16) #define RGXFWIF_INICFG_CTXSWITCH_PROFILE_FAST (RGXFWIF_CTXSWITCH_PROFILE_FAST_EN << RGXFWIF_INICFG_CTXSWITCH_PROFILE_SHIFT) #define RGXFWIF_INICFG_CTXSWITCH_PROFILE_MEDIUM (RGXFWIF_CTXSWITCH_PROFILE_MEDIUM_EN << RGXFWIF_INICFG_CTXSWITCH_PROFILE_SHIFT) @@ -575,7 +583,12 @@ typedef struct /* Extended Flag definitions affecting the firmware globally */ #define RGXFWIF_INICFG_EXT_TFBC_CONTROL_SHIFT (0) -#define RGXFWIF_INICFG_EXT_TFBC_CONTROL_MASK (IMG_UINT32_C(0x7F)) /* RGX_CR_TFBC_COMPRESSION_CONTROL_MASKFULL */ +/* [7] YUV10 override + * [6:4] Quality + * [3] Quality enable + * [2:1] Compression scheme + * [0] Lossy group */ +#define RGXFWIF_INICFG_EXT_TFBC_CONTROL_MASK (IMG_UINT32_C(0xFF)) /* RGX_CR_TFBC_COMPRESSION_CONTROL_MASKFULL */ #define RGXFWIF_INICFG_EXT_ALL (RGXFWIF_INICFG_EXT_TFBC_CONTROL_MASK) #define RGXFWIF_INICFG_SYS_CTXSWITCH_CLRMSK ~(RGXFWIF_INICFG_CTXSWITCH_MODE_RAND | \ @@ -599,7 +612,7 @@ typedef struct #define RGXFWIF_INICFG_OS_LOW_PRIO_CS_3D (IMG_UINT32_C(0x1) << 6) #define RGXFWIF_INICFG_OS_LOW_PRIO_CS_CDM (IMG_UINT32_C(0x1) << 7) -#define RGXFWIF_INICFG_OS_ALL (0xFF) +#define RGXFWIF_INICFG_OS_ALL (0xFFU) #define RGXFWIF_INICFG_OS_CTXSWITCH_DM_ALL (RGXFWIF_INICFG_OS_CTXSWITCH_GEOM_EN | \ RGXFWIF_INICFG_OS_CTXSWITCH_3D_EN | \ @@ -617,12 +630,10 @@ typedef struct #define RGXFWIF_FILTCFG_TRUNCATE_INT (IMG_UINT32_C(0x1) << 2) #define RGXFWIF_FILTCFG_NEW_FILTER_MODE (IMG_UINT32_C(0x1) << 1) -typedef enum -{ - RGX_ACTIVEPM_FORCE_OFF = 0, - RGX_ACTIVEPM_FORCE_ON = 1, - RGX_ACTIVEPM_DEFAULT = 2 -} RGX_ACTIVEPM_CONF; +typedef IMG_UINT32 RGX_ACTIVEPM_CONF; +#define RGX_ACTIVEPM_FORCE_OFF 0U +#define RGX_ACTIVEPM_FORCE_ON 1U +#define RGX_ACTIVEPM_DEFAULT 2U typedef enum { @@ -675,6 +686,7 @@ typedef RGXFWIF_DEV_VIRTADDR PRGXFWIF_GPU_UTIL_FWCB; typedef RGXFWIF_DEV_VIRTADDR PRGXFWIF_REG_CFG; typedef RGXFWIF_DEV_VIRTADDR PRGXFWIF_HWPERF_CTL; typedef RGXFWIF_DEV_VIRTADDR PRGX_HWPERF_CONFIG_MUX_CNTBLK; +typedef RGXFWIF_DEV_VIRTADDR PRGX_HWPERF_CONFIG_CNTBLK; typedef RGXFWIF_DEV_VIRTADDR PRGX_HWPERF_SELECT_CUSTOM_CNTRS; typedef RGXFWIF_DEV_VIRTADDR PRGXFWIF_CCB_CTL; typedef RGXFWIF_DEV_VIRTADDR PRGXFWIF_CCB; @@ -701,7 +713,7 @@ typedef RGXFWIF_DEV_VIRTADDR PRGXFWIF_RF_CMD; /*! * This number is used to represent unallocated page catalog base register */ -#define RGXFW_BIF_INVALID_PCREG 0xFFFFFFFFU +#define RGXFW_BIF_INVALID_PCSET 0xFFFFFFFFU /*! Firmware memory context. @@ -709,7 +721,7 @@ typedef RGXFWIF_DEV_VIRTADDR PRGXFWIF_RF_CMD; typedef struct { IMG_DEV_PHYADDR RGXFW_ALIGN sPCDevPAddr; /*!< device physical address of context's page catalogue */ - IMG_UINT32 uiPageCatBaseRegID; /*!< associated page catalog base register (RGXFW_BIF_INVALID_PCREG == unallocated) */ + IMG_UINT32 uiPageCatBaseRegSet; /*!< associated page catalog base register (RGXFW_BIF_INVALID_PCSET == unallocated) */ IMG_UINT32 uiBreakpointAddr; /*!< breakpoint address */ IMG_UINT32 uiBPHandlerAddr; /*!< breakpoint handler address */ IMG_UINT32 uiBreakpointCtl; /*!< DM and enable control for BP */ @@ -728,6 +740,7 @@ typedef struct #define RGXFWIF_CONTEXT_FLAGS_NEED_RESUME (0x00000001U) #define RGXFWIF_CONTEXT_FLAGS_MC_NEED_RESUME_MASKFULL (0x000000FFU) #define RGXFWIF_CONTEXT_FLAGS_TDM_HEADER_STALE (0x00000100U) +#define RGXFWIF_CONTEXT_FLAGS_LAST_KICK_SECURE (0x00000200U) /*! * @InGroup ContextSwitching @@ -738,11 +751,14 @@ typedef struct /* FW-accessible TA state which must be written out to memory on context store */ IMG_UINT64 RGXFW_ALIGN uTAReg_VDM_CALL_STACK_POINTER; /*!< VDM control stream stack pointer, to store in mid-TA */ IMG_UINT64 RGXFW_ALIGN uTAReg_VDM_CALL_STACK_POINTER_Init; /*!< Initial value of VDM control stream stack pointer (in case is 'lost' due to a lock-up) */ - IMG_UINT64 RGXFW_ALIGN uTAReg_VBS_SO_PRIM0; - IMG_UINT64 RGXFW_ALIGN uTAReg_VBS_SO_PRIM1; - IMG_UINT64 RGXFW_ALIGN uTAReg_VBS_SO_PRIM2; - IMG_UINT64 RGXFW_ALIGN uTAReg_VBS_SO_PRIM3; + IMG_UINT32 uTAReg_VBS_SO_PRIM[4]; IMG_UINT16 ui16TACurrentIdx; +} UNCACHED_ALIGN RGXFWIF_TACTX_STATE_PER_GEOM; + +typedef struct +{ + /* FW-accessible TA state which must be written out to memory on context store */ + RGXFWIF_TACTX_STATE_PER_GEOM asGeomCore[RGX_NUM_GEOM_CORES]; } UNCACHED_ALIGN RGXFWIF_TACTX_STATE; /*! @@ -761,7 +777,7 @@ typedef struct IMG_UINT32 au3DReg_ISP_STORE[]; /*!< ISP state (per-pipe) */ } UNCACHED_ALIGN RGXFWIF_3DCTX_STATE; -static_assert(sizeof(RGXFWIF_3DCTX_STATE) <= 16, +static_assert(sizeof(RGXFWIF_3DCTX_STATE) <= 16U, "Size of structure RGXFWIF_3DCTX_STATE exceeds maximum expected size."); #define RGXFWIF_CTX_USING_BUFFER_A (0) @@ -788,7 +804,7 @@ typedef struct RGXFWIF_FWCOMMONCONTEXT_ /* Flags e.g. for context switching */ IMG_UINT32 ui32FWComCtxFlags; - IMG_UINT32 ui32Priority; /*!< Priority level */ + IMG_INT32 i32Priority; /*!< Priority level */ IMG_UINT32 ui32PrioritySeqNum; /* Framework state */ @@ -823,7 +839,7 @@ typedef struct RGXFWIF_FWCOMMONCONTEXT_ } UNCACHED_ALIGN RGXFWIF_FWCOMMONCONTEXT; -static_assert(sizeof(RGXFWIF_FWCOMMONCONTEXT) <= 256, +static_assert(sizeof(RGXFWIF_FWCOMMONCONTEXT) <= 256U, "Size of structure RGXFWIF_FWCOMMONCONTEXT exceeds maximum expected size."); typedef IMG_UINT64 RGXFWIF_TRP_CHECKSUM_TQ[RGX_TRP_MAX_NUM_CORES][1]; @@ -846,6 +862,10 @@ typedef struct IMG_UINT32 ui32FwRenderCtxFlags; /*!< Compatibility and other flags */ +#if defined(SUPPORT_TRP) + RGXFWIF_TRP_CHECKSUM_3D aui64TRPChecksums3D; + RGXFWIF_TRP_CHECKSUM_GEOM aui64TRPChecksumsGeom; +#endif } UNCACHED_ALIGN RGXFWIF_FWRENDERCONTEXT; /*! @@ -935,7 +955,11 @@ typedef struct #if !defined(RGX_FEATURE_SLC_VIVT) #define RGXFWIF_MMUCACHEDATA_FLAGS_PMTLB (0x10U) /* can't use PM_TLB0 bit from BIFPM_CTRL reg because it collides with PT bit from BIF_CTRL reg */ +#if !defined(RGX_FEATURE_XE_ARCHITECTURE) || (RGX_FEATURE_XE_ARCHITECTURE < 2) #define RGXFWIF_MMUCACHEDATA_FLAGS_TLB (RGXFWIF_MMUCACHEDATA_FLAGS_PMTLB | 0x8U) /* BIF_CTRL_INVAL_TLB1_EN */ +#else +#define RGXFWIF_MMUCACHEDATA_FLAGS_TLB (RGXFWIF_MMUCACHEDATA_FLAGS_PMTLB) +#endif #define RGXFWIF_MMUCACHEDATA_FLAGS_CTX_ALL (0x0U) /* not used */ #else /* RGX_FEATURE_SLC_VIVT */ @@ -1106,6 +1130,12 @@ typedef struct PRGX_HWPERF_CONFIG_MUX_CNTBLK sBlockConfigs; /*!< Address of the RGX_HWPERF_CONFIG_MUX_CNTBLK array */ } RGXFWIF_HWPERF_CONFIG_ENABLE_BLKS; +typedef struct +{ + IMG_UINT32 ui32NumBlocks; /*!< Number of RGX_HWPERF_CONFIG_CNTBLK in the array */ + PRGX_HWPERF_CONFIG_CNTBLK sBlockConfigs; /*!< Address of the RGX_HWPERF_CONFIG_CNTBLK array */ +} RGXFWIF_HWPERF_CONFIG_DA_BLKS; + /*! * @Brief Command data for \ref RGXFWIF_KCCB_CMD_CORECLKSPEEDCHANGE type command */ @@ -1151,6 +1181,13 @@ typedef struct IMG_UINT32 ui32RegAddr; IMG_UINT64 RGXFW_ALIGN ui64RegVal; } RGXFWIF_RGXREG_DATA; + +typedef struct +{ + IMG_UINT64 ui64BaseAddress; + PRGXFWIF_FWCOMMONCONTEXT psContext; + IMG_UINT32 ui32Size; +} RGXFWIF_GPUMAP_DATA; #endif /*! @@ -1340,6 +1377,10 @@ typedef enum RGXFWIF_KCCB_CMD_COUNTER_DUMP = 216U | RGX_CMD_MAGIC_DWORD_SHIFTED, /*!< Controls counter dumping in the FW */ RGXFWIF_KCCB_CMD_HWPERF_CONFIG_ENABLE_BLKS = 217U | RGX_CMD_MAGIC_DWORD_SHIFTED, /*!< Configure, clear and enable multiple HWPerf blocks */ RGXFWIF_KCCB_CMD_HWPERF_SELECT_CUSTOM_CNTRS = 218U | RGX_CMD_MAGIC_DWORD_SHIFTED, /*!< Configure the custom counters for HWPerf */ +#if defined(SUPPORT_VALIDATION) + RGXFWIF_KCCB_CMD_GPUMAP = 219U | RGX_CMD_MAGIC_DWORD_SHIFTED, /*!< Request a FW GPU mapping which is written into by the FW with a pattern */ +#endif + RGXFWIF_KCCB_CMD_HWPERF_CONFIG_BLKS = 220U | RGX_CMD_MAGIC_DWORD_SHIFTED, /*!< Configure directly addressable counters for HWPerf */ } RGXFWIF_KCCB_CMD_TYPE; #define RGXFWIF_LAST_ALLOWED_GUEST_KCCB_CMD (RGXFWIF_KCCB_CMD_REGCONFIG - 1) @@ -1366,7 +1407,8 @@ typedef struct RGXFWIF_HWPERF_CTRL sHWPerfCtrl; /*!< Data for HWPerf control command */ RGXFWIF_HWPERF_CONFIG_ENABLE_BLKS sHWPerfCfgEnableBlks; /*!< Data for HWPerf configure, clear and enable performance counter block command */ RGXFWIF_HWPERF_CTRL_BLKS sHWPerfCtrlBlks; /*!< Data for HWPerf enable or disable performance counter block commands */ - RGXFWIF_HWPERF_SELECT_CUSTOM_CNTRS sHWPerfSelectCstmCntrs; /*!< Data for HWPerf configure the custom counters to read */ + RGXFWIF_HWPERF_SELECT_CUSTOM_CNTRS sHWPerfSelectCstmCntrs; /*!< Data for HWPerf configure the custom counters to read */ + RGXFWIF_HWPERF_CONFIG_DA_BLKS sHWPerfCfgDABlks; /*!< Data for HWPerf configure Directly Addressable blocks */ RGXFWIF_CORECLKSPEEDCHANGE_DATA sCoreClkSpeedChangeData;/*!< Data for core clock speed change */ RGXFWIF_ZSBUFFER_BACKING_DATA sZSBufferBackingData; /*!< Feedback for Z/S Buffer backing/unbacking */ RGXFWIF_FREELIST_GS_DATA sFreeListGSData; /*!< Feedback for Freelist grow/shrink */ @@ -1381,6 +1423,7 @@ typedef struct RGXFWIF_KCCB_CMD_FORCE_UPDATE_DATA sForceUpdateData; /*!< Data for signalling all unmet fences for a given CCB */ #if defined(SUPPORT_VALIDATION) RGXFWIF_RGXREG_DATA sFwRgxData; /*!< Data for reading off an RGX register */ + RGXFWIF_GPUMAP_DATA sGPUMapData; /*!< Data for requesting a FW GPU mapping which is written into by the FW with a pattern */ #endif } UNCACHED_ALIGN uCmdData; } UNCACHED_ALIGN RGXFWIF_KCCB_CMD; @@ -1664,7 +1707,7 @@ typedef struct /*! @Brief Command data for \ref RGXFWIF_CCB_CMD_TYPE_PRIORITY type client CCB command */ typedef struct { - IMG_UINT32 ui32Priority; /*!< Priority level */ + IMG_INT32 i32Priority; /*!< Priority level */ } RGXFWIF_CMD_PRIORITY; /*! @} End of ClientCCBTypes */ @@ -1721,7 +1764,7 @@ typedef struct do { \ (name).ui32LayoutVersion = RGXFWIF_COMPCHECKS_LAYOUT_VERSION; \ (name).ui64BVNC = 0; \ - } while (0) + } while (false) typedef struct { @@ -1831,8 +1874,6 @@ typedef enum FW_PERF_CONF_NONE = 0, FW_PERF_CONF_ICACHE = 1, FW_PERF_CONF_DCACHE = 2, - FW_PERF_CONF_POLLS = 3, - FW_PERF_CONF_CUSTOM_TIMER = 4, FW_PERF_CONF_JTLB_INSTR = 5, FW_PERF_CONF_INSTRUCTIONS = 6 } FW_PERF_CONF; @@ -1915,6 +1956,9 @@ typedef struct IMG_DEV_VIRTADDR RGXFW_ALIGN sPDSExecBase; /*!< PDS execution base */ IMG_DEV_VIRTADDR RGXFW_ALIGN sUSCExecBase; /*!< USC execution base */ + IMG_DEV_VIRTADDR RGXFW_ALIGN sFBCDCStateTableBase; /*!< FBCDC bindless texture state table base */ + IMG_DEV_VIRTADDR RGXFW_ALIGN sFBCDCLargeStateTableBase; + IMG_DEV_VIRTADDR RGXFW_ALIGN sTextureHeapBase; /*!< Texture state base */ IMG_UINT64 RGXFW_ALIGN ui64HWPerfFilter; /*! Event filter for Firmware events */ @@ -2002,10 +2046,11 @@ typedef struct /* Value to write into RGX_CR_TFBC_COMPRESSION_CONTROL */ IMG_UINT32 ui32TFBCCompressionControl; -} UNCACHED_ALIGN RGXFWIF_SYSINIT; +#if defined(SUPPORT_AUTOVZ) + IMG_UINT32 ui32VzWdgPeriod; +#endif -static_assert(sizeof(RGXFWIF_SYSINIT) <= 792, - "Size of structure RGXFW_SYSINIT exceeds maximum expected size."); +} UNCACHED_ALIGN RGXFWIF_SYSINIT; #if defined(SUPPORT_GPUVIRT_VALIDATION) #define RGXFWIF_KICK_TEST_ENABLED_BIT 0x1 @@ -2134,67 +2179,33 @@ typedef struct IMG_UINT32 ui32RTACtlFlags; /* Compatibility and other flags */ } UNCACHED_ALIGN RGXFWIF_RTA_CTL; -/*! @Brief Firmware Freelist holding usage state of the Parameter Buffers */ +/*! + * @InGroup RenderTarget + * @Brief Firmware Freelist holding usage state of the Parameter Buffers + */ typedef struct { - IMG_DEV_VIRTADDR RGXFW_ALIGN psFreeListDevVAddr; - IMG_UINT64 RGXFW_ALIGN ui64CurrentDevVAddr; - IMG_UINT32 ui32CurrentStackTop; - IMG_UINT32 ui32MaxPages; - IMG_UINT32 ui32GrowPages; - IMG_UINT32 ui32CurrentPages; /* HW pages */ - IMG_UINT32 ui32AllocatedPageCount; - IMG_UINT32 ui32AllocatedMMUPageCount; + IMG_DEV_VIRTADDR RGXFW_ALIGN psFreeListDevVAddr; /*!< Freelist page table base */ + IMG_UINT64 RGXFW_ALIGN ui64CurrentDevVAddr;/*!< Freelist page table entry for current free page */ + IMG_UINT32 ui32CurrentStackTop; /*!< Freelist current free page */ + IMG_UINT32 ui32MaxPages; /*!< Max no. of pages can be added to the freelist */ + IMG_UINT32 ui32GrowPages; /*!< No pages to add in each freelist grow */ + IMG_UINT32 ui32CurrentPages; /*!< Total no. of pages made available to the PM HW */ + IMG_UINT32 ui32AllocatedPageCount; /*!< No. of pages allocated by PM HW */ + IMG_UINT32 ui32AllocatedMMUPageCount; /*!< No. of pages allocated for GPU MMU for PM*/ #if defined(SUPPORT_SHADOW_FREELISTS) - IMG_UINT32 ui32HWRCounter; + IMG_UINT32 ui32HWRCounter; PRGXFWIF_FWMEMCONTEXT psFWMemContext; #endif - IMG_UINT32 ui32FreeListID; - IMG_BOOL bGrowPending; - IMG_UINT32 ui32ReadyPages; /* Pages that should be used only when OOM is reached */ - IMG_UINT32 ui32FreelistFlags; /* Compatibility and other flags */ + IMG_UINT32 ui32FreeListID; /*!< Unique Freelist ID */ + IMG_BOOL bGrowPending; /*!< Freelist grow is pending */ + IMG_UINT32 ui32ReadyPages; /*!< Reserved pages to be used only on PM OOM event */ + IMG_UINT32 ui32FreelistFlags; /*!< Compatibility and other flags */ +#if defined(SUPPORT_AGP) + IMG_UINT32 ui32PmGlobalPb; /*!< PM Global PB on which Freelist is loaded */ +#endif } UNCACHED_ALIGN RGXFWIF_FREELIST; -/*! - ****************************************************************************** - * Parameter Management (PM) control data for RGX - *****************************************************************************/ - -/* Used only by Firmware but defined here for similarity with Volcanic where it's required for SW TRP */ - -typedef enum -{ - RGXFW_SPM_STATE_NONE = 0, - RGXFW_SPM_STATE_PR_BLOCKED, - RGXFW_SPM_STATE_WAIT_FOR_GROW, - RGXFW_SPM_STATE_WAIT_FOR_HW, - RGXFW_SPM_STATE_PR_RUNNING, - RGXFW_SPM_STATE_PR_AVOIDED, - RGXFW_SPM_STATE_PR_EXECUTED, -} RGXFW_SPM_STATE; - -/*! - ****************************************************************************** - * @Brief RGX firmware SPM Control Data: - * This structure holds all the internal SPM control Data of the firmware. - *****************************************************************************/ -typedef struct -{ - RGXFW_SPM_STATE eSPMState; /*!< Current state of TA OOM event */ - RGXFWIF_UFO sPartialRenderTA3DFence; /*!< TA/3D fence object holding the value to let through the 3D partial command */ -#if defined(RGX_FIRMWARE) - RGXFWIF_FWCOMMONCONTEXT *ps3dContext; /*!< Pointer to the 3D Context holding the partial render */ - RGXFWIF_PRBUFFER *apsPRBuffer[RGXFWIF_PRBUFFER_MAXSUPPORTED]; /*!< Array of pointers to PR Buffers which may be used if partial render is needed */ -#else - RGXFWIF_DEV_VIRTADDR ps3dContext; /*!< Pointer to the 3D Context holding the partial render */ - RGXFWIF_DEV_VIRTADDR apsPRBuffer[RGXFWIF_PRBUFFER_MAXSUPPORTED]; /*!< Array of pointers to PR Buffers which may be used if partial render is needed */ -#endif - IMG_UINT32 ui32CmdOffset; /*!< CCCB offset of the command holding the partial render */ - bool b3DMemFreeDetected; /*!< Indicates if a 3D Memory Free has been detected, which resolves OOM */ -} RGXFW_ALIGN_DCACHEL RGXFW_SPMCTL; - -static_assert(sizeof(RGXFW_SPMCTL) <= 64, - "Size of structure RGXFW_SPMCTL exceeds maximum expected size."); /*! ****************************************************************************** * HWRTData @@ -2202,12 +2213,19 @@ static_assert(sizeof(RGXFW_SPMCTL) <= 64, /* HWRTData flags */ /* Deprecated flags 1:0 */ -#define HWRTDATA_HAS_LAST_TA (1U << 2) -#define HWRTDATA_PARTIAL_RENDERED (1U << 3) -#define HWRTDATA_DISABLE_TILE_REORDERING (1U << 4) -#define HWRTDATA_NEED_BRN65101_BLIT (1U << 5) -#define HWRTDATA_FIRST_BRN65101_STRIP (1U << 6) -#define HWRTDATA_NEED_BRN67182_2ND_RENDER (1U << 7) +#define HWRTDATA_HAS_LAST_TA (1UL << 2) +#define HWRTDATA_PARTIAL_RENDERED (1UL << 3) +#define HWRTDATA_DISABLE_TILE_REORDERING (1UL << 4) +#define HWRTDATA_NEED_BRN65101_BLIT (1UL << 5) +#define HWRTDATA_FIRST_BRN65101_STRIP (1UL << 6) +#define HWRTDATA_NEED_BRN67182_2ND_RENDER (1UL << 7) +#if defined(SUPPORT_AGP) +#define HWRTDATA_GLOBAL_PB_NUMBER_BIT0 (1UL << 8) +#if defined(SUPPORT_AGP4) +#define HWRTDATA_GLOBAL_PB_NUMBER_BIT1 (1UL << 9) +#endif +#define HWRTDATA_GEOM_NEEDS_RESUME (1UL << 10) +#endif typedef enum { @@ -2251,51 +2269,55 @@ typedef struct IMG_UINT32 ui32ISPMtileSize; } UNCACHED_ALIGN RGXFWIF_HWRTDATA_COMMON; -/*! @Brief Firmware Render Target data i.e. HWRTDATA used to hold the PM context */ +/*! + * @InGroup RenderTarget + * @Brief Firmware Render Target data i.e. HWRTDATA used to hold the PM context + */ typedef struct { - IMG_DEV_VIRTADDR RGXFW_ALIGN psPMMListDevVAddr; /*!< MList Data Store */ + IMG_DEV_VIRTADDR RGXFW_ALIGN psPMMListDevVAddr; /*!< MList Data Store */ - IMG_UINT64 RGXFW_ALIGN ui64VCECatBase[4]; - IMG_UINT64 RGXFW_ALIGN ui64VCELastCatBase[4]; - IMG_UINT64 RGXFW_ALIGN ui64TECatBase[4]; - IMG_UINT64 RGXFW_ALIGN ui64TELastCatBase[4]; - IMG_UINT64 RGXFW_ALIGN ui64AlistCatBase; - IMG_UINT64 RGXFW_ALIGN ui64AlistLastCatBase; + IMG_UINT64 RGXFW_ALIGN ui64VCECatBase[4]; /*!< VCE Page Catalogue base */ + IMG_UINT64 RGXFW_ALIGN ui64VCELastCatBase[4]; + IMG_UINT64 RGXFW_ALIGN ui64TECatBase[4]; /*!< TE Page Catalogue base */ + IMG_UINT64 RGXFW_ALIGN ui64TELastCatBase[4]; + IMG_UINT64 RGXFW_ALIGN ui64AlistCatBase; /*!< Alist Page Catalogue base */ + IMG_UINT64 RGXFW_ALIGN ui64AlistLastCatBase; - IMG_UINT64 RGXFW_ALIGN ui64PMAListStackPointer; - IMG_UINT32 ui32PMMListStackPointer; + IMG_UINT64 RGXFW_ALIGN ui64PMAListStackPointer; /*!< Freelist page table entry for current Mlist page */ + IMG_UINT32 ui32PMMListStackPointer; /*!< Current Mlist page */ - RGXFWIF_DEV_VIRTADDR sHWRTDataCommonFwAddr; + RGXFWIF_DEV_VIRTADDR sHWRTDataCommonFwAddr; /*!< Render target dimension dependent data */ - IMG_UINT32 ui32HWRTDataFlags; - RGXFWIF_RTDATA_STATE eState; + IMG_UINT32 ui32HWRTDataFlags; + RGXFWIF_RTDATA_STATE eState; /*!< Current workload processing state of HWRTDATA */ - PRGXFWIF_FREELIST RGXFW_ALIGN apsFreeLists[RGXFW_MAX_FREELISTS]; - IMG_UINT32 aui32FreeListHWRSnapshot[RGXFW_MAX_FREELISTS]; + PRGXFWIF_FREELIST RGXFW_ALIGN apsFreeLists[RGXFW_MAX_FREELISTS]; /*!< Freelist to use */ + IMG_UINT32 aui32FreeListHWRSnapshot[RGXFW_MAX_FREELISTS]; - IMG_DEV_VIRTADDR RGXFW_ALIGN psVHeapTableDevVAddr; + IMG_DEV_VIRTADDR RGXFW_ALIGN psVHeapTableDevVAddr; /*!< VHeap table base */ - RGXFWIF_CLEANUP_CTL sCleanupState; + RGXFWIF_CLEANUP_CTL sCleanupState; /*!< Render target clean up state */ - RGXFWIF_RTA_CTL sRTACtl; + RGXFWIF_RTA_CTL sRTACtl; /*!< Render target array data */ - IMG_DEV_VIRTADDR RGXFW_ALIGN sTailPtrsDevVAddr; - IMG_DEV_VIRTADDR RGXFW_ALIGN sMacrotileArrayDevVAddr; - IMG_DEV_VIRTADDR RGXFW_ALIGN sRgnHeaderDevVAddr; - IMG_DEV_VIRTADDR RGXFW_ALIGN sRTCDevVAddr; + IMG_DEV_VIRTADDR RGXFW_ALIGN sTailPtrsDevVAddr; /*!< Tail pointers base */ + IMG_DEV_VIRTADDR RGXFW_ALIGN sMacrotileArrayDevVAddr; /*!< Macrotiling array base */ + IMG_DEV_VIRTADDR RGXFW_ALIGN sRgnHeaderDevVAddr; /*!< Region headers base */ + IMG_DEV_VIRTADDR RGXFW_ALIGN sRTCDevVAddr; /*!< Render target cache base */ #if defined(RGX_FIRMWARE) - struct RGXFWIF_FWCOMMONCONTEXT_* RGXFW_ALIGN psOwnerGeom; + struct RGXFWIF_FWCOMMONCONTEXT_* RGXFW_ALIGN psOwnerGeom; #else - RGXFWIF_DEV_VIRTADDR RGXFW_ALIGN pui32OwnerGeomNotUsedByHost; + RGXFWIF_DEV_VIRTADDR RGXFW_ALIGN pui32OwnerGeomNotUsedByHost; #endif #if defined(SUPPORT_TRP) - IMG_UINT32 ui32KickFlagsCopy; - IMG_UINT32 ui32TRPState; - RGXFWIF_TRP_CHECKSUM_3D aui64TRPChecksums3D; - RGXFWIF_TRP_CHECKSUM_GEOM aui64TRPChecksumsGeom; - IMG_UINT32 ui32TEPageCopy; - IMG_UINT32 ui32VCEPageCopy; + IMG_UINT32 ui32KickFlagsCopy; + IMG_UINT32 ui32TRPState; + IMG_UINT32 ui32TEPageCopy; + IMG_UINT32 ui32VCEPageCopy; +#endif +#if defined(SUPPORT_AGP) + IMG_BOOL bTACachesNeedZeroing; #endif } UNCACHED_ALIGN RGXFWIF_HWRTDATA; diff --git a/drivers/gpu/drm/img-rogue/include/rogue/rgx_fwif_shared.h b/drivers/gpu/drm/img-rogue/include/rogue/rgx_fwif_shared.h index 3d47224e6..13844ad4e 100644 --- a/drivers/gpu/drm/img-rogue/include/rogue/rgx_fwif_shared.h +++ b/drivers/gpu/drm/img-rogue/include/rogue/rgx_fwif_shared.h @@ -51,7 +51,17 @@ CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. #include "powervr/mem_types.h" /* Indicates the number of RTDATAs per RTDATASET */ -#define RGXMKIF_NUM_RTDATAS 2U +#if defined(SUPPORT_AGP) +#define RGXMKIF_NUM_RTDATAS 4U +#define RGXMKIF_NUM_GEOMDATAS 4U +#define RGXMKIF_NUM_RTDATA_FREELISTS 12U /* RGXMKIF_NUM_RTDATAS * RGXFW_MAX_FREELISTS */ +#define RGX_NUM_GEOM_CORES (2U) +#else +#define RGXMKIF_NUM_RTDATAS 2U +#define RGXMKIF_NUM_GEOMDATAS 1U +#define RGXMKIF_NUM_RTDATA_FREELISTS 2U /* RGXMKIF_NUM_RTDATAS * RGXFW_MAX_FREELISTS */ +#define RGX_NUM_GEOM_CORES (1U) +#endif /* Maximum number of UFOs in a CCB command. * The number is based on having 32 sync prims (as originally), plus 32 sync @@ -121,13 +131,17 @@ typedef enum RGXFWIF_PRBUFFER_UNBACKING_PENDING, }RGXFWIF_PRBUFFER_STATE; +/*! + * @InGroup RenderTarget + * @Brief OnDemand Z/S/MSAA Buffers + */ typedef struct { - IMG_UINT32 ui32BufferID; /*!< Buffer ID*/ - IMG_BOOL bOnDemand; /*!< Needs On-demand Z/S/MSAA Buffer allocation */ - RGXFWIF_PRBUFFER_STATE eState; /*!< Z/S/MSAA -Buffer state */ - RGXFWIF_CLEANUP_CTL sCleanupState; /*!< Cleanup state */ - IMG_UINT32 ui32PRBufferFlags; /*!< Compatibility and other flags */ + IMG_UINT32 ui32BufferID; /*!< Buffer ID*/ + IMG_BOOL bOnDemand; /*!< Needs On-demand Z/S/MSAA Buffer allocation */ + RGXFWIF_PRBUFFER_STATE eState; /*!< Z/S/MSAA -Buffer state */ + RGXFWIF_CLEANUP_CTL sCleanupState; /*!< Cleanup state */ + IMG_UINT32 ui32PRBufferFlags; /*!< Compatibility and other flags */ } UNCACHED_ALIGN RGXFWIF_PRBUFFER; /* @@ -188,7 +202,15 @@ typedef struct * Points to commands not ready, i.e. * fence dependencies are not met. */ IMG_UINT32 ui32WrapMask; /*!< Offset wrapping mask, total capacity - * in bytes of the CCB-1 */ + in bytes of the CCB-1 */ +#if defined(SUPPORT_AGP) + IMG_UINT32 ui32ReadOffset2; +#if defined(SUPPORT_AGP4) + IMG_UINT32 ui32ReadOffset3; + IMG_UINT32 ui32ReadOffset4; +#endif +#endif + } UNCACHED_ALIGN RGXFWIF_CCCB_CTL; @@ -196,7 +218,13 @@ typedef IMG_UINT32 RGXFW_FREELIST_TYPE; #define RGXFW_LOCAL_FREELIST IMG_UINT32_C(0) #define RGXFW_GLOBAL_FREELIST IMG_UINT32_C(1) +#if defined(SUPPORT_AGP) +#define RGXFW_GLOBAL2_FREELIST IMG_UINT32_C(2) +#define RGXFW_MAX_FREELISTS (RGXFW_GLOBAL2_FREELIST + 1U) +#else #define RGXFW_MAX_FREELISTS (RGXFW_GLOBAL_FREELIST + 1U) +#endif +#define RGXFW_MAX_HWFREELISTS (2U) /*! * @Defgroup ContextSwitching Context switching data interface @@ -256,7 +284,7 @@ typedef struct */ typedef struct { - RGXFWIF_TAREGISTERS_CSWITCH RGXFW_ALIGN sCtxSwitch_Regs; /*!< Geom registers for ctx switch */ + RGXFWIF_TAREGISTERS_CSWITCH RGXFW_ALIGN asCtxSwitch_GeomRegs[RGX_NUM_GEOM_CORES]; /*!< Geom registers for ctx switch */ } RGXFWIF_STATIC_RENDERCONTEXT_STATE; #define RGXFWIF_STATIC_RENDERCONTEXT_SIZE sizeof(RGXFWIF_STATIC_RENDERCONTEXT_STATE) diff --git a/drivers/gpu/drm/img-rogue/include/rogue/rgx_heaps.h b/drivers/gpu/drm/img-rogue/include/rogue/rgx_heaps.h index 4c7e53582..e41e4002b 100644 --- a/drivers/gpu/drm/img-rogue/include/rogue/rgx_heaps.h +++ b/drivers/gpu/drm/img-rogue/include/rogue/rgx_heaps.h @@ -54,6 +54,7 @@ CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. #define RGX_VK_CAPT_REPLAY_HEAP_IDENT "Vulkan Capture Replay" /*!< RGX Vulkan capture replay buffer Heap Identifier */ #define RGX_SIGNALS_HEAP_IDENT "Signals" /*!< Signals Heap Identifier */ #define RGX_FBCDC_HEAP_IDENT "FBCDC" /*!< RGX FBCDC State Table Heap Identifier */ +#define RGX_FBCDC_LARGE_HEAP_IDENT "Large FBCDC" /*!< RGX Large FBCDC State Table Heap Identifier */ #define RGX_CMP_MISSION_RMW_HEAP_IDENT "Compute Mission RMW" /*!< Compute Mission RMW Heap Identifier */ #define RGX_CMP_SAFETY_RMW_HEAP_IDENT "Compute Safety RMW" /*!< Compute Safety RMW Heap Identifier */ #define RGX_TEXTURE_STATE_HEAP_IDENT "Texture State" /*!< Texture State Heap Identifier */ diff --git a/drivers/gpu/drm/img-rogue/include/rogue/rgx_hwperf.h b/drivers/gpu/drm/img-rogue/include/rogue/rgx_hwperf.h index e8d159c15..fa711b0b6 100644 --- a/drivers/gpu/drm/img-rogue/include/rogue/rgx_hwperf.h +++ b/drivers/gpu/drm/img-rogue/include/rogue/rgx_hwperf.h @@ -60,6 +60,7 @@ extern "C" { #include "img_defs.h" #include "rgx_common.h" +#include "rgx_hwperf_common.h" #include "pvrsrv_tlcommon.h" #include "pvrsrv_sync_km.h" @@ -141,404 +142,8 @@ static_assert(RGX_FEATURE_NUM_CLUSTERS <= 16U, "Cluster count too large for HWPe /*! The number of counters supported in each non-mux counter block */ #define RGX_HWPERF_MAX_CUSTOM_CNTRS 8U -/*! The number of non-mux counter blocks supported */ -#if defined(SUPPORT_VALIDATION) -#define RGX_CNTBLK_COUNTERS_MAX 64U -#else -#define RGX_CNTBLK_COUNTERS_MAX 12U -#endif - -/****************************************************************************** - * Packet Event Type Enumerations - *****************************************************************************/ - -/*! Type used to encode the event that generated the packet. - * NOTE: When this type is updated the corresponding hwperfbin2json tool - * source needs to be updated as well. The RGX_HWPERF_EVENT_MASK_* macros will - * also need updating when adding new types. - * - * @par - * The event type values are incrementing integers for use as a shift ordinal - * in the event filtering process at the point events are generated. - * This scheme thus implies a limit of 63 event types. - */ - -typedef IMG_UINT32 RGX_HWPERF_EVENT_TYPE; - -#define RGX_HWPERF_INVALID 0x00U /*!< Invalid. Reserved value. */ - -/*! FW types 0x01..0x06 */ -#define RGX_HWPERF_FW_EVENT_RANGE_FIRST_TYPE 0x01U - -#define RGX_HWPERF_FW_BGSTART 0x01U /*!< Background task processing start */ -#define RGX_HWPERF_FW_BGEND 0x02U /*!< Background task end */ -#define RGX_HWPERF_FW_IRQSTART 0x03U /*!< IRQ task processing start */ - -#define RGX_HWPERF_FW_IRQEND 0x04U /*!< IRQ task end */ -#define RGX_HWPERF_FW_DBGSTART 0x05U /*!< Debug event start */ -#define RGX_HWPERF_FW_DBGEND 0x06U /*!< Debug event end */ - -#define RGX_HWPERF_FW_EVENT_RANGE_LAST_TYPE 0x06U - -/*! HW types 0x07..0x19 */ -#define RGX_HWPERF_HW_EVENT_RANGE0_FIRST_TYPE 0x07U - -#define RGX_HWPERF_HW_PMOOM_TAPAUSE 0x07U /*!< TA Pause at PM Out of Memory */ - -#define RGX_HWPERF_HW_TAKICK 0x08U /*!< TA task started */ -#define RGX_HWPERF_HW_TAFINISHED 0x09U /*!< TA task finished */ -#define RGX_HWPERF_HW_3DTQKICK 0x0AU /*!< 3D TQ started */ -#define RGX_HWPERF_HW_3DKICK 0x0BU /*!< 3D task started */ -#define RGX_HWPERF_HW_3DFINISHED 0x0CU /*!< 3D task finished */ -#define RGX_HWPERF_HW_CDMKICK 0x0DU /*!< CDM task started */ -#define RGX_HWPERF_HW_CDMFINISHED 0x0EU /*!< CDM task finished */ -#define RGX_HWPERF_HW_TLAKICK 0x0FU /*!< TLA task started */ -#define RGX_HWPERF_HW_TLAFINISHED 0x10U /*!< TLS task finished */ -#define RGX_HWPERF_HW_3DSPMKICK 0x11U /*!< 3D SPM task started */ -#define RGX_HWPERF_HW_PERIODIC 0x12U /*!< Periodic event with updated HW counters */ -#define RGX_HWPERF_HW_RTUKICK 0x13U /*!< Reserved, future use */ -#define RGX_HWPERF_HW_RTUFINISHED 0x14U /*!< Reserved, future use */ -#define RGX_HWPERF_HW_SHGKICK 0x15U /*!< Reserved, future use */ -#define RGX_HWPERF_HW_SHGFINISHED 0x16U /*!< Reserved, future use */ -#define RGX_HWPERF_HW_3DTQFINISHED 0x17U /*!< 3D TQ finished */ -#define RGX_HWPERF_HW_3DSPMFINISHED 0x18U /*!< 3D SPM task finished */ - -#define RGX_HWPERF_HW_PMOOM_TARESUME 0x19U /*!< TA Resume after PM Out of Memory */ - -/*! HW_EVENT_RANGE0 used up. Use next empty range below to add new hardware events */ -#define RGX_HWPERF_HW_EVENT_RANGE0_LAST_TYPE 0x19U - -/*! other types 0x1A..0x1F */ -#define RGX_HWPERF_CLKS_CHG 0x1AU /*!< Clock speed change in GPU */ -#define RGX_HWPERF_GPU_STATE_CHG 0x1BU /*!< GPU work state change */ - -/*! power types 0x20..0x27 */ -#define RGX_HWPERF_PWR_EST_RANGE_FIRST_TYPE 0x20U -#define RGX_HWPERF_PWR_EST_REQUEST 0x20U /*!< Power estimate requested (via GPIO) */ -#define RGX_HWPERF_PWR_EST_READY 0x21U /*!< Power estimate inputs ready */ -#define RGX_HWPERF_PWR_EST_RESULT 0x22U /*!< Power estimate result calculated */ -#define RGX_HWPERF_PWR_EST_RANGE_LAST_TYPE 0x22U - -#define RGX_HWPERF_PWR_CHG 0x23U /*!< Power state change */ - -/*! HW_EVENT_RANGE1 0x28..0x2F, for accommodating new hardware events */ -#define RGX_HWPERF_HW_EVENT_RANGE1_FIRST_TYPE 0x28U - -#define RGX_HWPERF_HW_TDMKICK 0x28U /*!< TDM task started */ -#define RGX_HWPERF_HW_TDMFINISHED 0x29U /*!< TDM task finished */ -#define RGX_HWPERF_HW_NULLKICK 0x2AU /*!< NULL event */ - -#define RGX_HWPERF_HW_EVENT_RANGE1_LAST_TYPE 0x2AU - -/*! context switch types 0x30..0x31 */ -#define RGX_HWPERF_CSW_START 0x30U /*!< HW context store started */ -#define RGX_HWPERF_CSW_FINISHED 0x31U /*!< HW context store finished */ - -/*! DVFS events */ -#define RGX_HWPERF_DVFS 0x32U /*!< Dynamic voltage/frequency scaling events */ - -/*! firmware misc 0x38..0x39 */ -#define RGX_HWPERF_UFO 0x38U /*!< FW UFO Check / Update */ -#define RGX_HWPERF_FWACT 0x39U /*!< FW Activity notification */ - -/*! last */ -#define RGX_HWPERF_LAST_TYPE 0x3BU - -/*! This enumeration must have a value that is a power of two as it is - * used in masks and a filter bit field (currently 64 bits long). - */ -#define RGX_HWPERF_MAX_TYPE 0x40U - -static_assert(RGX_HWPERF_LAST_TYPE < RGX_HWPERF_MAX_TYPE, "Too many HWPerf event types"); - -/*! Macro used to check if an event type ID is present in the known set of hardware type events */ -#define HWPERF_PACKET_IS_HW_TYPE(_etype) (((_etype) >= RGX_HWPERF_HW_EVENT_RANGE0_FIRST_TYPE && (_etype) <= RGX_HWPERF_HW_EVENT_RANGE0_LAST_TYPE) || \ - ((_etype) >= RGX_HWPERF_HW_EVENT_RANGE1_FIRST_TYPE && (_etype) <= RGX_HWPERF_HW_EVENT_RANGE1_LAST_TYPE)) - -/*! Macro used to check if an event type ID is present in the known set of firmware type events */ -#define HWPERF_PACKET_IS_FW_TYPE(_etype) \ - ((_etype) >= RGX_HWPERF_FW_EVENT_RANGE_FIRST_TYPE && \ - (_etype) <= RGX_HWPERF_FW_EVENT_RANGE_LAST_TYPE) - - -typedef enum { - RGX_HWPERF_HOST_INVALID = 0x00, /*!< Invalid, do not use. */ - RGX_HWPERF_HOST_ENQ = 0x01, /*!< ``0x01`` Kernel driver has queued GPU work. - See RGX_HWPERF_HOST_ENQ_DATA */ - RGX_HWPERF_HOST_UFO = 0x02, /*!< ``0x02`` UFO updated by the driver. - See RGX_HWPERF_HOST_UFO_DATA */ - RGX_HWPERF_HOST_ALLOC = 0x03, /*!< ``0x03`` Resource allocated. - See RGX_HWPERF_HOST_ALLOC_DATA */ - RGX_HWPERF_HOST_CLK_SYNC = 0x04, /*!< ``0x04`` GPU / Host clocks correlation data. - See RGX_HWPERF_HOST_CLK_SYNC_DATA */ - RGX_HWPERF_HOST_FREE = 0x05, /*!< ``0x05`` Resource freed, - See RGX_HWPERF_HOST_FREE_DATA */ - RGX_HWPERF_HOST_MODIFY = 0x06, /*!< ``0x06`` Resource modified / updated. - See RGX_HWPERF_HOST_MODIFY_DATA */ - RGX_HWPERF_HOST_DEV_INFO = 0x07, /*!< ``0x07`` Device Health status. - See RGX_HWPERF_HOST_DEV_INFO_DATA */ - RGX_HWPERF_HOST_INFO = 0x08, /*!< ``0x08`` Device memory usage information. - See RGX_HWPERF_HOST_INFO_DATA */ - RGX_HWPERF_HOST_SYNC_FENCE_WAIT = 0x09, /*!< ``0x09`` Wait for sync event. - See RGX_HWPERF_HOST_SYNC_FENCE_WAIT_DATA */ - RGX_HWPERF_HOST_SYNC_SW_TL_ADVANCE = 0x0A, /*!< ``0x0A`` Software timeline advanced. - See RGX_HWPERF_HOST_SYNC_SW_TL_ADV_DATA */ - - /*! last */ - RGX_HWPERF_HOST_LAST_TYPE, - - /*! This enumeration must have a value that is a power of two as it is - * used in masks and a filter bit field (currently 32 bits long). - */ - RGX_HWPERF_HOST_MAX_TYPE = 0x20 -} RGX_HWPERF_HOST_EVENT_TYPE; - -/*!< The event type values are incrementing integers for use as a shift ordinal - * in the event filtering process at the point events are generated. - * This scheme thus implies a limit of 31 event types. - */ -static_assert(RGX_HWPERF_HOST_LAST_TYPE < RGX_HWPERF_HOST_MAX_TYPE, "Too many HWPerf host event types"); - - -/****************************************************************************** - * Packet Header Format Version 2 Types - *****************************************************************************/ - -/*! Major version number of the protocol in operation - */ -#define RGX_HWPERF_V2_FORMAT 2 - -/*! Signature ASCII pattern 'HWP2' found in the first word of a HWPerfV2 packet - */ -#define HWPERF_PACKET_V2_SIG 0x48575032 - -/*! Signature ASCII pattern 'HWPA' found in the first word of a HWPerfV2a packet - */ -#define HWPERF_PACKET_V2A_SIG 0x48575041 - -/*! Signature ASCII pattern 'HWPB' found in the first word of a HWPerfV2b packet - */ -#define HWPERF_PACKET_V2B_SIG 0x48575042 - -#define HWPERF_PACKET_ISVALID(_ptr) (((_ptr) == HWPERF_PACKET_V2_SIG) || ((_ptr) == HWPERF_PACKET_V2A_SIG)|| ((_ptr) == HWPERF_PACKET_V2B_SIG)) -/*!< Checks that the packet signature is one of the supported versions */ - -/*! Type defines the HWPerf packet header common to all events. */ -typedef struct -{ - IMG_UINT32 ui32Sig; /*!< Always the value HWPERF_PACKET_SIG */ - IMG_UINT32 ui32Size; /*!< Overall packet size in bytes */ - IMG_UINT32 eTypeId; /*!< Event type information field */ - IMG_UINT32 ui32Ordinal; /*!< Sequential number of the packet */ - IMG_UINT64 ui64Timestamp; /*!< Event timestamp */ -} RGX_HWPERF_V2_PACKET_HDR, *RGX_PHWPERF_V2_PACKET_HDR; - -#ifndef __CHECKER__ -RGX_FW_STRUCT_OFFSET_ASSERT(RGX_HWPERF_V2_PACKET_HDR, ui64Timestamp); - -RGX_FW_STRUCT_SIZE_ASSERT(RGX_HWPERF_V2_PACKET_HDR); -#endif - - -/*! Mask for use with the IMG_UINT32 ui32Size header field */ -#define RGX_HWPERF_SIZE_MASK 0xFFFFU - -/*! This macro defines an upper limit to which the size of the largest variable - * length HWPerf packet must fall within, currently 3KB. This constant may be - * used to allocate a buffer to hold one packet. - * This upper limit is policed by packet producing code. - */ -#define RGX_HWPERF_MAX_PACKET_SIZE 0xC00U - -/*! Defines an upper limit to the size of a variable length packet payload. - */ -#define RGX_HWPERF_MAX_PAYLOAD_SIZE ((IMG_UINT32)(RGX_HWPERF_MAX_PACKET_SIZE-\ - sizeof(RGX_HWPERF_V2_PACKET_HDR))) - -/*! Macro which takes a structure name and provides the packet size for - * a fixed size payload packet, rounded up to 8 bytes to align packets - * for 64 bit architectures. */ -#define RGX_HWPERF_MAKE_SIZE_FIXED(_struct) ((IMG_UINT32)(RGX_HWPERF_SIZE_MASK&(sizeof(RGX_HWPERF_V2_PACKET_HDR)+PVR_ALIGN(sizeof(_struct), PVRSRVTL_PACKET_ALIGNMENT)))) - -/*! Macro which takes the number of bytes written in the data payload of a - * packet for a variable size payload packet, rounded up to 8 bytes to - * align packets for 64 bit architectures. */ -#define RGX_HWPERF_MAKE_SIZE_VARIABLE(_size) ((IMG_UINT32)(RGX_HWPERF_SIZE_MASK&(sizeof(RGX_HWPERF_V2_PACKET_HDR)+PVR_ALIGN((_size), PVRSRVTL_PACKET_ALIGNMENT)))) - -/*! Macro to obtain the size of the packet */ -#define RGX_HWPERF_GET_SIZE(_packet_addr) ((IMG_UINT16)(((_packet_addr)->ui32Size) & RGX_HWPERF_SIZE_MASK)) - -/*! Macro to obtain the size of the packet data */ -#define RGX_HWPERF_GET_DATA_SIZE(_packet_addr) (RGX_HWPERF_GET_SIZE(_packet_addr) - sizeof(RGX_HWPERF_V2_PACKET_HDR)) - -/*! Masks for use with the IMG_UINT32 eTypeId header field */ -#define RGX_HWPERF_TYPEID_MASK 0x0007FFFFU -#define RGX_HWPERF_TYPEID_EVENT_MASK 0x00007FFFU -#define RGX_HWPERF_TYPEID_THREAD_MASK 0x00008000U -#define RGX_HWPERF_TYPEID_STREAM_MASK 0x00070000U -#define RGX_HWPERF_TYPEID_META_DMA_MASK 0x00080000U -#define RGX_HWPERF_TYPEID_M_CORE_MASK 0x00100000U -#define RGX_HWPERF_TYPEID_OSID_MASK 0x07000000U - -/*! Meta thread macros for encoding the ID into the type field of a packet */ -#define RGX_HWPERF_META_THREAD_SHIFT 15U -#define RGX_HWPERF_META_THREAD_ID0 0x0U /*!< Meta Thread 0 ID */ -#define RGX_HWPERF_META_THREAD_ID1 0x1U /*!< Meta Thread 1 ID */ -/*! Obsolete, kept for source compatibility */ -#define RGX_HWPERF_META_THREAD_MASK 0x1U -/*! Stream ID macros for encoding the ID into the type field of a packet */ -#define RGX_HWPERF_STREAM_SHIFT 16U -/*! Meta DMA macro for encoding how the packet was generated into the type field of a packet */ -#define RGX_HWPERF_META_DMA_SHIFT 19U -/*! Bit-shift macro used for encoding multi-core data into the type field of a packet */ -#define RGX_HWPERF_M_CORE_SHIFT 20U -/*! OSID bit-shift macro used for encoding OSID into type field of a packet */ -#define RGX_HWPERF_OSID_SHIFT 24U -typedef enum { - RGX_HWPERF_STREAM_ID0_FW, /*!< Events from the Firmware/GPU */ - RGX_HWPERF_STREAM_ID1_HOST, /*!< Events from the Server host driver component */ - RGX_HWPERF_STREAM_ID2_CLIENT, /*!< Events from the Client host driver component */ - RGX_HWPERF_STREAM_ID_LAST, -} RGX_HWPERF_STREAM_ID; - -/* Checks if all stream IDs can fit under RGX_HWPERF_TYPEID_STREAM_MASK. */ -static_assert(((IMG_UINT32)RGX_HWPERF_STREAM_ID_LAST - 1U) < (RGX_HWPERF_TYPEID_STREAM_MASK >> RGX_HWPERF_STREAM_SHIFT), - "Too many HWPerf stream IDs."); - -/*! Compile-time value used to seed the Multi-Core (MC) bit in the typeID field. - * Only set by RGX_FIRMWARE builds. - */ -#if defined(RGX_FIRMWARE) -# if defined(RGX_FEATURE_GPU_MULTICORE_SUPPORT) -#define RGX_HWPERF_M_CORE_VALUE 1U /*!< 1 => Multi-core supported */ -# else -#define RGX_HWPERF_M_CORE_VALUE 0U /*!< 0 => Multi-core not supported */ -# endif -#else -#define RGX_HWPERF_M_CORE_VALUE 0U /*!< 0 => Multi-core not supported */ -#endif - -/*! Macros used to set the packet type and encode meta thread ID (0|1), - * HWPerf stream ID, multi-core capability and OSID within the typeID */ -#define RGX_HWPERF_MAKE_TYPEID(_stream, _type, _thread, _metadma, _osid)\ - ((IMG_UINT32) ((RGX_HWPERF_TYPEID_STREAM_MASK&((IMG_UINT32)(_stream) << RGX_HWPERF_STREAM_SHIFT)) | \ - (RGX_HWPERF_TYPEID_THREAD_MASK & ((IMG_UINT32)(_thread) << RGX_HWPERF_META_THREAD_SHIFT)) | \ - (RGX_HWPERF_TYPEID_EVENT_MASK & (IMG_UINT32)(_type)) | \ - (RGX_HWPERF_TYPEID_META_DMA_MASK & ((IMG_UINT32)(_metadma) << RGX_HWPERF_META_DMA_SHIFT)) | \ - (RGX_HWPERF_TYPEID_OSID_MASK & ((IMG_UINT32)(_osid) << RGX_HWPERF_OSID_SHIFT)) | \ - (RGX_HWPERF_TYPEID_M_CORE_MASK & ((IMG_UINT32)(RGX_HWPERF_M_CORE_VALUE) << RGX_HWPERF_M_CORE_SHIFT)))) - -/*! Obtains the event type that generated the packet */ -#define RGX_HWPERF_GET_TYPE(_packet_addr) (((_packet_addr)->eTypeId) & RGX_HWPERF_TYPEID_EVENT_MASK) - -/*! Obtains the META Thread number that generated the packet */ -#define RGX_HWPERF_GET_THREAD_ID(_packet_addr) (((((_packet_addr)->eTypeId) & RGX_HWPERF_TYPEID_THREAD_MASK) >> RGX_HWPERF_META_THREAD_SHIFT)) - -/*! Determines if the packet generated contains multi-core data */ -#define RGX_HWPERF_GET_M_CORE(_packet_addr) (((_packet_addr)->eTypeId & RGX_HWPERF_TYPEID_M_CORE_MASK) >> RGX_HWPERF_M_CORE_SHIFT) - -/*! Obtains the guest OSID which resulted in packet generation */ -#define RGX_HWPERF_GET_OSID(_packet_addr) (((_packet_addr)->eTypeId & RGX_HWPERF_TYPEID_OSID_MASK) >> RGX_HWPERF_OSID_SHIFT) - -/*! Obtain stream id */ -#define RGX_HWPERF_GET_STREAM_ID(_packet_addr) (((((_packet_addr)->eTypeId) & RGX_HWPERF_TYPEID_STREAM_MASK) >> RGX_HWPERF_STREAM_SHIFT)) - -/*! Obtain information about how the packet was generated, which might affect payload total size */ -#define RGX_HWPERF_GET_META_DMA_INFO(_packet_addr) (((((_packet_addr)->eTypeId) & RGX_HWPERF_TYPEID_META_DMA_MASK) >> RGX_HWPERF_META_DMA_SHIFT)) - -/*! Obtains a typed pointer to a packet given a buffer address */ -#define RGX_HWPERF_GET_PACKET(_buffer_addr) ((RGX_HWPERF_V2_PACKET_HDR *)(void *) (_buffer_addr)) -/*! Obtains a typed pointer to a data structure given a packet address */ -#define RGX_HWPERF_GET_PACKET_DATA_BYTES(_packet_addr) (IMG_OFFSET_ADDR((_packet_addr), sizeof(RGX_HWPERF_V2_PACKET_HDR))) -/*! Obtains a typed pointer to the next packet given a packet address */ -#define RGX_HWPERF_GET_NEXT_PACKET(_packet_addr) ((RGX_HWPERF_V2_PACKET_HDR *) (IMG_OFFSET_ADDR((_packet_addr), RGX_HWPERF_SIZE_MASK&((_packet_addr)->ui32Size)))) - -/*! Obtains a typed pointer to a packet header given the packet data address */ -#define RGX_HWPERF_GET_PACKET_HEADER(_packet_addr) ((RGX_HWPERF_V2_PACKET_HDR *) (IMG_OFFSET_ADDR((_packet_addr), -(IMG_INT32)sizeof(RGX_HWPERF_V2_PACKET_HDR)))) - - -/****************************************************************************** - * Other Common Defines - *****************************************************************************/ - -/*! This macro is not a real array size, but indicates the array has a variable - * length only known at run-time but always contains at least 1 element. The - * final size of the array is deduced from the size field of a packet header. - */ -#define RGX_HWPERF_ONE_OR_MORE_ELEMENTS 1U - -/*! This macro is not a real array size, but indicates the array is optional - * and if present has a variable length only known at run-time. The final - * size of the array is deduced from the size field of a packet header. */ -#define RGX_HWPERF_ZERO_OR_MORE_ELEMENTS 1U - - -/*! Masks for use with the IMG_UINT32 ui32BlkInfo field */ -#define RGX_HWPERF_BLKINFO_BLKCOUNT_MASK 0xFFFF0000U -#define RGX_HWPERF_BLKINFO_BLKOFFSET_MASK 0x0000FFFFU - -/*! Shift for the NumBlocks and counter block offset field in ui32BlkInfo */ -#define RGX_HWPERF_BLKINFO_BLKCOUNT_SHIFT 16U -#define RGX_HWPERF_BLKINFO_BLKOFFSET_SHIFT 0U - -/*! Macro used to set the block info word as a combination of two 16-bit integers */ -#define RGX_HWPERF_MAKE_BLKINFO(_numblks, _blkoffset) ((IMG_UINT32) ((RGX_HWPERF_BLKINFO_BLKCOUNT_MASK&((_numblks) << RGX_HWPERF_BLKINFO_BLKCOUNT_SHIFT)) | (RGX_HWPERF_BLKINFO_BLKOFFSET_MASK&((_blkoffset) << RGX_HWPERF_BLKINFO_BLKOFFSET_SHIFT)))) - -/*! Macro used to obtain the number of counter blocks present in the packet */ -#define RGX_HWPERF_GET_BLKCOUNT(_blkinfo) (((_blkinfo) & RGX_HWPERF_BLKINFO_BLKCOUNT_MASK) >> RGX_HWPERF_BLKINFO_BLKCOUNT_SHIFT) - -/*! Obtains the offset of the counter block stream in the packet */ -#define RGX_HWPERF_GET_BLKOFFSET(_blkinfo) (((_blkinfo) & RGX_HWPERF_BLKINFO_BLKOFFSET_MASK) >> RGX_HWPERF_BLKINFO_BLKOFFSET_SHIFT) - -/*! This macro gets the number of blocks depending on the packet version */ -#define RGX_HWPERF_GET_NUMBLKS(_sig, _packet_data, _numblocks) \ - do { \ - if (HWPERF_PACKET_V2B_SIG == (_sig)) \ - { \ - (_numblocks) = RGX_HWPERF_GET_BLKCOUNT((_packet_data)->ui32BlkInfo);\ - } \ - else \ - { \ - IMG_UINT32 ui32VersionOffset = (((_sig) == HWPERF_PACKET_V2_SIG) ? 1 : 3);\ - (_numblocks) = *(IMG_UINT16 *)(IMG_OFFSET_ADDR(&(_packet_data)->ui32WorkTarget, ui32VersionOffset)); \ - } \ - } while (0) - -/*! This macro gets the counter stream pointer depending on the packet version */ -#define RGX_HWPERF_GET_CNTSTRM(_sig, _hw_packet_data, _cntstream_ptr) \ -{ \ - if (HWPERF_PACKET_V2B_SIG == (_sig)) \ - { \ - (_cntstream_ptr) = (IMG_UINT32 *)(IMG_OFFSET_ADDR((_hw_packet_data), RGX_HWPERF_GET_BLKOFFSET((_hw_packet_data)->ui32BlkInfo))); \ - } \ - else \ - { \ - IMG_UINT32 ui32BlkStreamOffsetInWords = (((_sig) == HWPERF_PACKET_V2_SIG) ? 6 : 8); \ - (_cntstream_ptr) = (IMG_UINT32 *)(IMG_OFFSET_ADDR_DW((_hw_packet_data), ui32BlkStreamOffsetInWords)); \ - } \ -} - -/*! Masks for use with the RGX_HWPERF_UFO_EV eEvType field */ -#define RGX_HWPERF_UFO_STREAMSIZE_MASK 0xFFFF0000U -#define RGX_HWPERF_UFO_STREAMOFFSET_MASK 0x0000FFFFU - -/*! Shift for the UFO count and data stream fields */ -#define RGX_HWPERF_UFO_STREAMSIZE_SHIFT 16U -#define RGX_HWPERF_UFO_STREAMOFFSET_SHIFT 0U - -/*! Macro used to set UFO stream info word as a combination of two 16-bit integers */ -#define RGX_HWPERF_MAKE_UFOPKTINFO(_ssize, _soff) \ - ((IMG_UINT32) ((RGX_HWPERF_UFO_STREAMSIZE_MASK&((_ssize) << RGX_HWPERF_UFO_STREAMSIZE_SHIFT)) | \ - (RGX_HWPERF_UFO_STREAMOFFSET_MASK&((_soff) << RGX_HWPERF_UFO_STREAMOFFSET_SHIFT)))) - -/*! Macro used to obtain UFO count*/ -#define RGX_HWPERF_GET_UFO_STREAMSIZE(_streaminfo) \ - (((_streaminfo) & RGX_HWPERF_UFO_STREAMSIZE_MASK) >> RGX_HWPERF_UFO_STREAMSIZE_SHIFT) - -/*! Obtains the offset of the UFO stream in the packet */ -#define RGX_HWPERF_GET_UFO_STREAMOFFSET(_streaminfo) \ - (((_streaminfo) & RGX_HWPERF_UFO_STREAMOFFSET_MASK) >> RGX_HWPERF_UFO_STREAMOFFSET_SHIFT) - +/*! The number of directly-addressable counters allowed in non-mux counter blocks */ +#define RGX_CNTBLK_COUNTERS_MAX ((IMG_UINT32)PVRSRV_HWPERF_COUNTERS_PERBLK + 0U) /****************************************************************************** @@ -565,18 +170,20 @@ typedef enum { RGX_HWPERF_DM_INVALID = 0x1FFFFFFF } RGX_HWPERF_DM; -/*! Enum containing bit position for 32bit feature flags used in hwperf and api */ -typedef enum { - RGX_HWPERF_FEATURE_PERFBUS_FLAG = 0x001, - RGX_HWPERF_FEATURE_S7_TOP_INFRASTRUCTURE_FLAG = 0x002, - RGX_HWPERF_FEATURE_XT_TOP_INFRASTRUCTURE_FLAG = 0x004, - RGX_HWPERF_FEATURE_PERF_COUNTER_BATCH_FLAG = 0x008, - RGX_HWPERF_FEATURE_ROGUEXE_FLAG = 0x010, - RGX_HWPERF_FEATURE_DUST_POWER_ISLAND_S7_FLAG = 0x020, - RGX_HWPERF_FEATURE_PBE2_IN_XE_FLAG = 0x040, - RGX_HWPERF_FEATURE_WORKLOAD_ESTIMATION = 0x080, - RGX_HWPERF_FEATURE_MULTICORE_FLAG = 0x100 -} RGX_HWPERF_FEATURE_FLAGS; +/*! Define containing bit position for 32bit feature flags used in hwperf and api */ +typedef IMG_UINT32 RGX_HWPERF_FEATURE_FLAGS; +#define RGX_HWPERF_FEATURE_PERFBUS_FLAG 0x0001U +#define RGX_HWPERF_FEATURE_S7_TOP_INFRASTRUCTURE_FLAG 0x0002U +#define RGX_HWPERF_FEATURE_XT_TOP_INFRASTRUCTURE_FLAG 0x0004U +#define RGX_HWPERF_FEATURE_PERF_COUNTER_BATCH_FLAG 0x0008U +#define RGX_HWPERF_FEATURE_ROGUEXE_FLAG 0x0010U +#define RGX_HWPERF_FEATURE_DUST_POWER_ISLAND_S7_FLAG 0x0020U +#define RGX_HWPERF_FEATURE_PBE2_IN_XE_FLAG 0x0040U +#define RGX_HWPERF_FEATURE_WORKLOAD_ESTIMATION 0x0080U +#define RGX_HWPERF_FEATURE_MULTICORE_FLAG 0x0100U +#define RGX_HWPERF_FEATURE_VOLCANIC_FLAG 0x0800U +#define RGX_HWPERF_FEATURE_ROGUE_FLAG 0x1000U +#define RGX_HWPERF_FEATURE_OCEANIC_FLAG 0x2000U /*! This structure holds the data of a firmware packet. */ typedef struct @@ -606,11 +213,14 @@ typedef struct IMG_UINT32 ui32WorkCtx; /*!< Work context: Render Context for TA/3D; RayTracing Context for RTU/SHG; 0x0 otherwise */ IMG_UINT32 ui32CtxPriority; /*!< Context priority */ IMG_UINT32 ui32GPUIdMask; /*!< GPU IDs active within this event */ - IMG_UINT32 aui32CountBlksStream[RGX_HWPERF_ZERO_OR_MORE_ELEMENTS]; /*!< Counter data */ - IMG_UINT32 ui32Padding2; /*!< Reserved. To ensure correct alignment */ + IMG_UINT32 ui32KickInfo; /*!< <31..8> Reserved <7..0> GPU Pipeline DM kick ID, 0 if not using Pipeline DMs */ + IMG_UINT32 ui32Padding; /*!< Reserved. To ensure correct alignment */ + IMG_UINT32 aui32CountBlksStream[RGX_HWPERF_ZERO_OR_MORE_ELEMENTS]; /*!< Optional variable length Counter data */ + IMG_UINT32 ui32Padding2; /*!< Reserved. To ensure correct alignment (not written in the packet) */ } RGX_HWPERF_HW_DATA; RGX_FW_STRUCT_SIZE_ASSERT(RGX_HWPERF_HW_DATA); +RGX_FW_STRUCT_OFFSET_ASSERT(RGX_HWPERF_HW_DATA, aui32CountBlksStream); typedef struct { @@ -914,6 +524,26 @@ typedef struct RGX_FW_STRUCT_SIZE_ASSERT(RGX_HWPERF_BVNC); +/*! Performance Counter Configuration data element. */ +typedef struct +{ + IMG_UINT32 ui32BlockID; /*!< Counter Block ID. See RGX_HWPERF_CNTBLK_ID */ + IMG_UINT32 ui32NumCounters; /*!< Number of counters configured */ + IMG_UINT32 ui32CounterVals[RGX_CNTBLK_COUNTERS_MAX]; /*!< Counters configured (ui32NumCounters worth of entries) */ +} RGX_HWPERF_COUNTER_CFG_DATA_EL; + +RGX_FW_STRUCT_SIZE_ASSERT(RGX_HWPERF_COUNTER_CFG_DATA_EL); + +/*! Performance Counter Configuration data. */ +typedef struct +{ + IMG_UINT32 ui32EnabledBlocks; /*!< Number of Enabled Blocks. */ + RGX_HWPERF_COUNTER_CFG_DATA_EL uData; /*!< Start of variable length data. See RGX_HWPERF_COUNTER_CFG_DATA_EL */ + IMG_UINT32 ui32Padding; /*!< reserved */ +} RGX_HWPERF_COUNTER_CFG; + +RGX_FW_STRUCT_SIZE_ASSERT(RGX_HWPERF_COUNTER_CFG); + /*! Sub-event's data. */ typedef union { @@ -930,7 +560,7 @@ typedef union IMG_UINT32 ui32EvMaskLo; /*!< Low order 32 bits of Filter Mask */ IMG_UINT32 ui32EvMaskHi; /*!< High order 32 bits of Filter Mask */ } sEvMsk; /*!< HW Filter Mask */ - + RGX_HWPERF_COUNTER_CFG sPCC; /*!< Performance Counter Config. See RGX_HWPERF_COUNTER_CFG */ } RGX_HWPERF_FWACT_DETAIL; RGX_FW_STRUCT_SIZE_ASSERT(RGX_HWPERF_FWACT_DETAIL); @@ -1456,6 +1086,49 @@ typedef struct static_assert((sizeof(RGX_HWPERF_HOST_SYNC_SW_TL_ADV_DATA) & (PVRSRVTL_PACKET_ALIGNMENT-1U)) == 0U, "sizeof(RGX_HWPERF_HOST_SYNC_SW_TL_ADV_DATA) must be a multiple PVRSRVTL_PACKET_ALIGNMENT"); +typedef enum +{ + RGX_HWPERF_HOST_CLIENT_INFO_TYPE_INVALID = 0, /*!< Invalid */ + RGX_HWPERF_HOST_CLIENT_INFO_TYPE_PROCESS_NAME, /*!< Process Name */ + + RGX_HWPERF_HOST_CLIENT_INFO_TYPE_LAST, /*!< Do not use */ +} RGX_HWPERF_HOST_CLIENT_INFO_TYPE; + +typedef struct +{ + IMG_PID uiClientPID; /*!< Client process identifier */ + IMG_UINT32 ui32Length; /*!< Number of bytes present in ``acName`` */ + IMG_CHAR acName[RGX_HWPERF_ONE_OR_MORE_ELEMENTS]; /*!< Process name string, null terminated */ +} RGX_HWPERF_HOST_CLIENT_PROC_NAME; + +#define RGX_HWPERF_HOST_CLIENT_PROC_NAME_SIZE(ui32NameLen) \ + ((IMG_UINT32)(offsetof(RGX_HWPERF_HOST_CLIENT_PROC_NAME, acName) + (ui32NameLen))) + +typedef union +{ + struct + { + IMG_UINT32 ui32Count; /*!< Number of elements in ``asProcNames`` */ + RGX_HWPERF_HOST_CLIENT_PROC_NAME asProcNames[RGX_HWPERF_ONE_OR_MORE_ELEMENTS]; + } sProcName; +} RGX_HWPERF_HOST_CLIENT_INFO_DETAIL; + +typedef struct +{ + IMG_UINT32 uiReserved1; /*!< Reserved. Align structure size to 8 bytes */ + RGX_HWPERF_HOST_CLIENT_INFO_TYPE eType; + /*!< Type of the subevent, see + RGX_HWPERF_HOST_CLIENT_INFO_TYPE */ + RGX_HWPERF_HOST_CLIENT_INFO_DETAIL uDetail; + /*!< Union of structures. Size of data + varies with union member that is present, + check ``eType`` value to decode */ + +} RGX_HWPERF_HOST_CLIENT_INFO_DATA; + +static_assert((sizeof(RGX_HWPERF_HOST_CLIENT_INFO_DATA) & (PVRSRVTL_PACKET_ALIGNMENT-1U)) == 0U, + "sizeof(RGX_HWPERF_HOST_CLIENT_INFO_DATA) must be a multiple PVRSRVTL_PACKET_ALIGNMENT"); + typedef enum { RGX_HWPERF_RESOURCE_CAPTURE_TYPE_NONE, @@ -1581,6 +1254,9 @@ typedef union events ``0x09`` (Host) */ RGX_HWPERF_HOST_SYNC_SW_TL_ADV_DATA sSWTLADV; /*!< Host SW-timeline advance data, events ``0x0A`` (Host) */ + RGX_HWPERF_HOST_CLIENT_INFO_DATA sHClientInfo; /*!< Host client info, + events ``0x0B`` (Host) */ + } RGX_HWPERF_V2_PACKET_DATA, *RGX_PHWPERF_V2_PACKET_DATA; RGX_FW_STRUCT_SIZE_ASSERT(RGX_HWPERF_V2_PACKET_DATA); @@ -1612,7 +1288,11 @@ typedef IMG_UINT32 RGX_HWPERF_CNTBLK_ID; #define RGX_CNTBLK_ID_HUB 0x0002U /*!< Non-cluster grouping cores */ #define RGX_CNTBLK_ID_TORNADO 0x0003U /*!< XT cores */ #define RGX_CNTBLK_ID_JONES 0x0004U /*!< S7 cores */ +#if defined(RGX_FEATURE_HWPERF_OCEANIC) +#define RGX_CNTBLK_ID_DIRECT_LAST 0x0003U /*!< Indirect blocks start from here */ +#else #define RGX_CNTBLK_ID_DIRECT_LAST 0x0005U /*!< Indirect blocks start from here */ +#endif /* defined(RGX_FEATURE_HWPERF_OCEANIC) */ #define RGX_CNTBLK_ID_BF_DEPRECATED 0x0005U /*!< Doppler unit (DEPRECATED) */ #define RGX_CNTBLK_ID_BT_DEPRECATED 0x0006U /*!< Doppler unit (DEPRECATED) */ @@ -1747,6 +1427,19 @@ typedef IMG_UINT32 RGX_HWPERF_CNTBLK_ID; /*! The number of layout blocks defined with configurable multiplexed * performance counters, hence excludes custom counter blocks. */ +#if defined(RGX_FEATURE_HWPERF_OCEANIC) +#define RGX_HWPERF_MAX_MUX_BLKS (\ + (IMG_UINT32)RGX_CNTBLK_ID_DIRECT_LAST +\ + RGX_CNTBLK_INDIRECT_COUNT(PBE, 0) ) + +#define RGX_HWPERF_MAX_DA_BLKS (\ + (IMG_UINT32)RGX_CNTBLK_INDIRECT_COUNT(TPU_MCU, 0)+\ + RGX_CNTBLK_INDIRECT_COUNT(USC, 0) ) + +#define RGX_HWPERF_MAX_DEFINED_BLKS (\ + (IMG_UINT32)RGX_HWPERF_MAX_MUX_BLKS +\ + RGX_HWPERF_MAX_DA_BLKS ) +#else #define RGX_HWPERF_MAX_DEFINED_BLKS (\ (IMG_UINT32)RGX_CNTBLK_ID_DIRECT_LAST +\ RGX_CNTBLK_INDIRECT_COUNT(TPU_MCU, 7)+\ @@ -1755,12 +1448,15 @@ typedef IMG_UINT32 RGX_HWPERF_CNTBLK_ID; RGX_CNTBLK_INDIRECT_COUNT(RASTER, 3)+\ RGX_CNTBLK_INDIRECT_COUNT(BLACKPEARL, 3)+\ RGX_CNTBLK_INDIRECT_COUNT(PBE, 15) ) +#define RGX_HWPERF_MAX_MUX_BLKS (\ + RGX_HWPERF_MAX_DEFINED_BLKS ) +#endif static_assert( ((RGX_CNTBLK_ID_DIRECT_LAST + ((RGX_CNTBLK_ID_LAST & RGX_CNTBLK_ID_GROUP_MASK) >> RGX_CNTBLK_ID_GROUP_SHIFT)) <= RGX_HWPERF_MAX_BVNC_BLOCK_LEN), "RGX_HWPERF_MAX_BVNC_BLOCK_LEN insufficient"); -#define RGX_HWPERF_EVENT_MASK_VALUE(e) (IMG_UINT64_C(1) << (e)) +#define RGX_HWPERF_EVENT_MASK_VALUE(e) (IMG_UINT64_C(1) << (IMG_UINT32)(e)) #define RGX_CUSTOM_FW_CNTRS \ X(TA_LOCAL_FL_SIZE, 0x0, RGX_HWPERF_EVENT_MASK_VALUE(RGX_HWPERF_HW_TAKICK) | \ diff --git a/drivers/gpu/drm/img-rogue/include/rogue/rgxheapconfig.h b/drivers/gpu/drm/img-rogue/include/rogue/rgxheapconfig.h index 2c24cad1d..abb63084a 100644 --- a/drivers/gpu/drm/img-rogue/include/rogue/rgxheapconfig.h +++ b/drivers/gpu/drm/img-rogue/include/rogue/rgxheapconfig.h @@ -231,8 +231,13 @@ CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. #define RGX_FBCDC_HEAP_BASE IMG_UINT64_C(0xEC00000000) #define RGX_FBCDC_HEAP_SIZE RGX_HEAP_SIZE_2MiB -/* 0xEC_0020_0000 - 0xED_FFFF_FFFF **/ - /* 945 GiB to 952 GiB, size of 7 GiB : RESERVED VOLCANIC **/ +/* 0xEC_4000_0000 - 0xEC_401F_FFFF **/ + /* 945 GiB to 946 GiB, size 2 MiB : FBCDC_LARGE_HEAP **/ + #define RGX_FBCDC_LARGE_HEAP_BASE IMG_UINT64_C(0xEC40000000) + #define RGX_FBCDC_LARGE_HEAP_SIZE RGX_HEAP_SIZE_2MiB + +/* 0xEC_8000_0000 - 0xED_FFFF_FFFF **/ + /* 946 GiB to 952 GiB, size of 6 GiB : RESERVED VOLCANIC **/ /* 0xEE_0000_0000 - 0xEE_3FFF_FFFF **/ /* 952 GiB to 953 GiB, size of 1 GiB : CMP_MISSION_RMW_HEAP **/ diff --git a/drivers/gpu/drm/img-rogue/include/servicesext.h b/drivers/gpu/drm/img-rogue/include/servicesext.h index 23fab1dac..5d685b2ad 100644 --- a/drivers/gpu/drm/img-rogue/include/servicesext.h +++ b/drivers/gpu/drm/img-rogue/include/servicesext.h @@ -88,25 +88,19 @@ typedef enum _PVRSRV_SYS_POWER_STATE_ /*! Device Power State Enum */ -typedef enum _PVRSRV_DEV_POWER_STATE_ -{ - PVRSRV_DEV_POWER_STATE_DEFAULT = -1, /*!< Default state for the device */ - PVRSRV_DEV_POWER_STATE_OFF = 0, /*!< Unpowered */ - PVRSRV_DEV_POWER_STATE_ON = 1, /*!< Running */ - - PVRSRV_DEV_POWER_STATE_FORCE_I32 = 0x7fffffff /*!< Force enum to be at least 32-bits wide */ - -} PVRSRV_DEV_POWER_STATE, *PPVRSRV_DEV_POWER_STATE; /*!< Typedef for ptr to PVRSRV_DEV_POWER_STATE */ /* PRQA S 3205 */ +typedef IMG_INT32 PVRSRV_DEV_POWER_STATE; +typedef IMG_INT32 *PPVRSRV_DEV_POWER_STATE; /*!< Typedef for ptr to PVRSRV_DEV_POWER_STATE */ /* PRQA S 3205 */ +#define PVRSRV_DEV_POWER_STATE_DEFAULT -1 /*!< Default state for the device */ +#define PVRSRV_DEV_POWER_STATE_OFF 0 /*!< Unpowered */ +#define PVRSRV_DEV_POWER_STATE_ON 1 /*!< Running */ /*! Power Flags Enum */ -typedef enum _PVRSRV_POWER_FLAGS_ -{ - PVRSRV_POWER_FLAGS_NONE = 0, /*!< No flags */ - PVRSRV_POWER_FLAGS_FORCED = 1 << 0, /*!< Power the transition should not fail */ - PVRSRV_POWER_FLAGS_SUSPEND = 1 << 1, /*!< Power transition is due to OS suspend request */ -} PVRSRV_POWER_FLAGS; +typedef IMG_UINT32 PVRSRV_POWER_FLAGS; +#define PVRSRV_POWER_FLAGS_NONE 0U /*!< No flags */ +#define PVRSRV_POWER_FLAGS_FORCED 1U << 0 /*!< Power the transition should not fail */ +#define PVRSRV_POWER_FLAGS_SUSPEND 1U << 1 /*!< Power transition is due to OS suspend request */ /* Clock speed handler prototypes */ diff --git a/drivers/gpu/drm/img-rogue/include/sync_checkpoint_external.h b/drivers/gpu/drm/img-rogue/include/sync_checkpoint_external.h index 399e38084..19b5011aa 100644 --- a/drivers/gpu/drm/img-rogue/include/sync_checkpoint_external.h +++ b/drivers/gpu/drm/img-rogue/include/sync_checkpoint_external.h @@ -49,9 +49,9 @@ CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. #ifndef CHECKPOINT_TYPES #define CHECKPOINT_TYPES -typedef struct _SYNC_CHECKPOINT_CONTEXT *PSYNC_CHECKPOINT_CONTEXT; +typedef struct SYNC_CHECKPOINT_CONTEXT_TAG *PSYNC_CHECKPOINT_CONTEXT; -typedef struct _SYNC_CHECKPOINT *PSYNC_CHECKPOINT; +typedef struct SYNC_CHECKPOINT_TAG *PSYNC_CHECKPOINT; #endif /* PVRSRV_SYNC_CHECKPOINT states. @@ -68,7 +68,7 @@ typedef IMG_UINT32 PVRSRV_SYNC_CHECKPOINT_STATE; #define PVRSRV_SYNC_CHECKPOINT_ERRORED 0xeffU /*!< checkpoint has been errored */ -#define PVRSRV_UFO_IS_SYNC_CHECKPOINT_FWADDR(fwaddr) ((fwaddr) & 0x1U) +#define PVRSRV_UFO_IS_SYNC_CHECKPOINT_FWADDR(fwaddr) (((fwaddr) & 0x1U) != 0U) #define PVRSRV_UFO_IS_SYNC_CHECKPOINT(ufoptr) (PVRSRV_UFO_IS_SYNC_CHECKPOINT_FWADDR((ufoptr)->puiAddrUFO.ui32Addr)) /* Maximum number of sync checkpoints the firmware supports in one fence */ diff --git a/drivers/gpu/drm/img-rogue/include/virt_validation_defs.h b/drivers/gpu/drm/img-rogue/include/virt_validation_defs.h new file mode 100644 index 000000000..5b8908f71 --- /dev/null +++ b/drivers/gpu/drm/img-rogue/include/virt_validation_defs.h @@ -0,0 +1,63 @@ +/*************************************************************************/ /*! +@File +@Title Definitions for virtualization +@Copyright Copyright (c) Imagination Technologies Ltd. All Rights Reserved +@Description Services shared header for virtualization definitions +@License Dual MIT/GPLv2 + +The contents of this file are subject to the MIT license as set out below. + +Permission is hereby granted, free of charge, to any person obtaining a copy +of this software and associated documentation files (the "Software"), to deal +in the Software without restriction, including without limitation the rights +to use, copy, modify, merge, publish, distribute, sublicense, and/or sell +copies of the Software, and to permit persons to whom the Software is +furnished to do so, subject to the following conditions: + +The above copyright notice and this permission notice shall be included in +all copies or substantial portions of the Software. + +Alternatively, the contents of this file may be used under the terms of +the GNU General Public License Version 2 ("GPL") in which case the provisions +of GPL are applicable instead of those above. + +If you wish to allow use of your version of this file only under the terms of +GPL, and not to allow others to use your version of this file under the terms +of the MIT license, indicate your decision by deleting the provisions above +and replace them with the notice and other provisions required by GPL as set +out in the file called "GPL-COPYING" included in this distribution. If you do +not delete the provisions above, a recipient may use your version of this file +under the terms of either the MIT license or GPL. + +This License is also included in this distribution in the file called +"MIT-COPYING". + +EXCEPT AS OTHERWISE STATED IN A NEGOTIATED AGREEMENT: (A) THE SOFTWARE IS +PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING +BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR +PURPOSE AND NONINFRINGEMENT; AND (B) IN NO EVENT SHALL THE AUTHORS OR +COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER +IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN +CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +*/ /**************************************************************************/ + +#ifndef SRV_VIRT_DEFS_H +#define SRV_VIRT_DEFS_H + +#if !defined(GPUVIRT_VALIDATION_MAX_STRING_LENGTH) + #define GPUVIRT_VALIDATION_MAX_STRING_LENGTH 512 +#endif + +#define GPUVIRT_VALIDATION_MAX_OS 8 + +#define GPUVIRT_VALIDATION_NUM_REGIONS 2 +#define GPUVIRT_VAL_REGION_SECURE 0 +#define GPUVIRT_VAL_REGION_SHARED 1 + +/* Shared region 1MB */ +#define GPUVIRT_SIZEOF_SHARED 0x100000 + +/* Min region size 64MB */ +#define GPUVIRT_MIN_SIZE 0x4000000 + +#endif /* SRV_VIRT_DEFS_H */ diff --git a/drivers/gpu/drm/img-rogue/include/volcanic/rgx_fwif_km.h b/drivers/gpu/drm/img-rogue/include/volcanic/rgx_fwif_km.h index fffe4934c..2d7ea7ce5 100644 --- a/drivers/gpu/drm/img-rogue/include/volcanic/rgx_fwif_km.h +++ b/drivers/gpu/drm/img-rogue/include/volcanic/rgx_fwif_km.h @@ -156,20 +156,31 @@ typedef struct IMG_UINT32 ui32LineNum; } UNCACHED_ALIGN RGXFWIF_FILE_INFO_BUF; +/*! + * @Defgroup SRVAndFWTracing Services and Firmware Tracing data interface + * @Brief The document groups/lists the data structures and the interfaces related to Services and Firmware Tracing + * @{ + */ + +/*! + * @Brief Firmware trace buffer details + */ typedef struct { - IMG_UINT32 ui32TracePointer; + IMG_UINT32 ui32TracePointer; /*!< Trace pointer (write index into Trace Buffer)*/ #if defined(RGX_FIRMWARE) - IMG_UINT32 *pui32RGXFWIfTraceBuffer; /* To be used by firmware for writing into trace buffer */ + IMG_UINT32 *pui32RGXFWIfTraceBuffer; /*!< Trace buffer address (FW address), to be used by firmware for writing into trace buffer */ #else - RGXFWIF_DEV_VIRTADDR pui32RGXFWIfTraceBuffer; + RGXFWIF_DEV_VIRTADDR pui32RGXFWIfTraceBuffer; /*!< Trace buffer address (FW address)*/ #endif - IMG_PUINT32 pui32TraceBuffer; /* To be used by host when reading from trace buffer */ + IMG_PUINT32 pui32TraceBuffer; /*!< Trace buffer address (Host address), to be used by host when reading from trace buffer */ - RGXFWIF_FILE_INFO_BUF sAssertBuf; + RGXFWIF_FILE_INFO_BUF sAssertBuf; } UNCACHED_ALIGN RGXFWIF_TRACEBUF_SPACE; +/*! @} End of Defgroup SRVAndFWTracing */ + #define RGXFWIF_FWFAULTINFO_MAX (8U) /* Total number of FW fault logs stored */ typedef struct @@ -271,14 +282,17 @@ typedef struct } UNCACHED_ALIGN RGXFWIF_SLR_ENTRY; #endif -/* firmware trace control data */ +/*! + * @InGroup SRVAndFWTracing + * @Brief Firmware trace control data + */ typedef struct { - IMG_UINT32 ui32LogType; - RGXFWIF_TRACEBUF_SPACE sTraceBuf[RGXFW_THREAD_NUM]; - IMG_UINT32 ui32TraceBufSizeInDWords; /*!< Member initialised only when sTraceBuf is actually allocated - * (in RGXTraceBufferInitOnDemandResources) */ - IMG_UINT32 ui32TracebufFlags; /*!< Compatibility and other flags */ + IMG_UINT32 ui32LogType; /*!< FW trace log group configuration */ + RGXFWIF_TRACEBUF_SPACE sTraceBuf[RGXFW_THREAD_NUM]; /*!< FW Trace buffer */ + IMG_UINT32 ui32TraceBufSizeInDWords; /*!< FW Trace buffer size in dwords, Member initialised only when sTraceBuf is actually allocated + (in RGXTraceBufferInitOnDemandResources) */ + IMG_UINT32 ui32TracebufFlags; /*!< Compatibility and other flags */ } UNCACHED_ALIGN RGXFWIF_TRACEBUF; /*! @Brief Firmware system data shared with the Host driver */ @@ -547,13 +561,13 @@ typedef struct #define RGXFWIF_INICFG_FBCDC_V3_1_EN (IMG_UINT32_C(0x1) << 6) #define RGXFWIF_INICFG_CHECK_MLIST_EN (IMG_UINT32_C(0x1) << 7) #define RGXFWIF_INICFG_DISABLE_CLKGATING_EN (IMG_UINT32_C(0x1) << 8) -#define RGXFWIF_INICFG_POLL_COUNTERS_EN (IMG_UINT32_C(0x1) << 9) +/* 9 unused */ /* 10 unused */ /* 11 unused */ #define RGXFWIF_INICFG_REGCONFIG_EN (IMG_UINT32_C(0x1) << 12) #define RGXFWIF_INICFG_ASSERT_ON_OUTOFMEMORY (IMG_UINT32_C(0x1) << 13) #define RGXFWIF_INICFG_HWP_DISABLE_FILTER (IMG_UINT32_C(0x1) << 14) -#define RGXFWIF_INICFG_CUSTOM_PERF_TIMER_EN (IMG_UINT32_C(0x1) << 15) +/* 15 unused */ #define RGXFWIF_INICFG_CTXSWITCH_PROFILE_SHIFT (16) #define RGXFWIF_INICFG_CTXSWITCH_PROFILE_FAST (RGXFWIF_CTXSWITCH_PROFILE_FAST_EN << RGXFWIF_INICFG_CTXSWITCH_PROFILE_SHIFT) #define RGXFWIF_INICFG_CTXSWITCH_PROFILE_MEDIUM (RGXFWIF_CTXSWITCH_PROFILE_MEDIUM_EN << RGXFWIF_INICFG_CTXSWITCH_PROFILE_SHIFT) @@ -691,9 +705,9 @@ typedef RGXFWIF_DEV_VIRTADDR PRGXFWIF_RF_CMD; #define RGXFWIF_INVALID_PC_PHYADDR 0xFFFFFFFFFFFFFFFFLLU /*! - * This number is used to represent unallocated page catalog base register + * This number is used to represent an unallocated set of page catalog base registers */ -#define RGXFW_BIF_INVALID_PCREG 0xFFFFFFFFU +#define RGXFW_BIF_INVALID_PCSET 0xFFFFFFFFU /*! Firmware memory context. @@ -701,7 +715,7 @@ typedef RGXFWIF_DEV_VIRTADDR PRGXFWIF_RF_CMD; typedef struct { IMG_DEV_PHYADDR RGXFW_ALIGN sPCDevPAddr; /*!< device physical address of context's page catalogue */ - IMG_UINT32 uiPageCatBaseRegID; /*!< associated page catalog base register (RGXFW_BIF_INVALID_PCREG == unallocated) */ + IMG_UINT32 uiPageCatBaseRegSet; /*!< index of the associated set of page catalog base registers (RGXFW_BIF_INVALID_PCSET == unallocated) */ IMG_UINT32 uiBreakpointAddr; /*!< breakpoint address */ IMG_UINT32 uiBPHandlerAddr; /*!< breakpoint handler address */ IMG_UINT32 uiBreakpointCtl; /*!< DM and enable control for BP */ @@ -720,6 +734,7 @@ typedef struct */ #define RGXFWIF_CONTEXT_FLAGS_NEED_RESUME (0x00000001U) #define RGXFWIF_CONTEXT_FLAGS_TDM_HEADER_STALE (0x00000002U) +#define RGXFWIF_CONTEXT_FLAGS_LAST_KICK_SECURE (0x00000200U) /*! * @InGroup ContextSwitching @@ -798,7 +813,7 @@ typedef struct RGXFWIF_FWCOMMONCONTEXT_ /* Flags e.g. for context switching */ IMG_UINT32 ui32FWComCtxFlags; - IMG_UINT32 ui32Priority; /*!< Priority level */ + IMG_INT32 i32Priority; /*!< Priority level */ IMG_UINT32 ui32PrioritySeqNum; /* Framework state */ @@ -831,6 +846,7 @@ typedef struct RGXFWIF_FWCOMMONCONTEXT_ IMG_BOOL bGeomOOMDisabled; /*!< True when Geom DM OOM is not allowed */ + IMG_UINT32 ui32PipelinedKicks; /*!< Number of kick from this CCB currently submitted to the DM pipeline */ } UNCACHED_ALIGN RGXFWIF_FWCOMMONCONTEXT; static_assert(sizeof(RGXFWIF_FWCOMMONCONTEXT) <= 256, @@ -851,10 +867,13 @@ typedef struct RGXFWIF_STATIC_RENDERCONTEXT_STATE sStaticRenderContextState; - IMG_UINT32 ui32TotalNumPartialRenders; /*!< Total number of partial renders */ - IMG_UINT32 ui32TotalNumOutOfMemory; /*!< Total number of OOMs */ IMG_UINT32 ui32WorkEstCCBSubmitted; /*!< Number of commands submitted to the WorkEst FW CCB */ IMG_UINT32 ui32FwRenderCtxFlags; /*!< Compatibility and other flags */ + +#if defined(SUPPORT_TRP) + RGXFWIF_TRP_CHECKSUM_3D aui64TRPChecksums3D; + RGXFWIF_TRP_CHECKSUM_GEOM aui64TRPChecksumsGeom; +#endif } UNCACHED_ALIGN RGXFWIF_FWRENDERCONTEXT; /*! @@ -1058,7 +1077,11 @@ typedef struct RGXFWIF_POWER_TYPE ePowType; /*!< Type of power request */ union { - IMG_UINT32 ui32PowUnitsStateMask; /*!< New power units state mask */ + struct + { + IMG_UINT32 ui32PowUnitsStateMask; /*!< New power units state mask */ + IMG_UINT32 ui32RACStateMask; /*!< New RAC state mask */ + }; IMG_BOOL bForced; /*!< If the operation is mandatory */ RGXFWIF_POWER_FORCE_IDLE_TYPE ePowRequestType; /*!< Type of Request. Consolidating Force Idle, Cancel Forced Idle, Host Timeout */ } uPowerReqData; @@ -1146,6 +1169,13 @@ typedef struct IMG_UINT32 ui32RegAddr; IMG_UINT64 RGXFW_ALIGN ui64RegVal; } RGXFWIF_RGXREG_DATA; + +typedef struct +{ + IMG_UINT64 ui64BaseAddress; + PRGXFWIF_FWCOMMONCONTEXT psContext; + IMG_UINT32 ui32Size; +} RGXFWIF_GPUMAP_DATA; #endif /*! @@ -1317,6 +1347,9 @@ typedef enum RGXFWIF_KCCB_CMD_RGXREG = 214U | RGX_CMD_MAGIC_DWORD_SHIFTED, /*!< Read RGX Register from FW */ #endif RGXFWIF_KCCB_CMD_WDG_CFG = 215U | RGX_CMD_MAGIC_DWORD_SHIFTED, /*!< Configure Safety Firmware Watchdog */ +#if defined(SUPPORT_VALIDATION) + RGXFWIF_KCCB_CMD_GPUMAP = 219U | RGX_CMD_MAGIC_DWORD_SHIFTED, /*!< Request a FW GPU mapping which is written into by the FW with a pattern */ +#endif } RGXFWIF_KCCB_CMD_TYPE; #define RGXFWIF_LAST_ALLOWED_GUEST_KCCB_CMD (RGXFWIF_KCCB_CMD_REGCONFIG - 1) @@ -1358,6 +1391,7 @@ typedef struct RGXFWIF_KCCB_CMD_FORCE_UPDATE_DATA sForceUpdateData; /*!< Data for signalling all unmet fences for a given CCB */ #if defined(SUPPORT_VALIDATION) RGXFWIF_RGXREG_DATA sFwRgxData; /*!< Data for reading off an RGX register */ + RGXFWIF_GPUMAP_DATA sGPUMapData; /*!< Data for requesting a FW GPU mapping which is written into by the FW with a pattern */ #endif } UNCACHED_ALIGN uCmdData; } UNCACHED_ALIGN RGXFWIF_KCCB_CMD; @@ -1643,7 +1677,7 @@ typedef struct /*! @Brief Command data for \ref RGXFWIF_CCB_CMD_TYPE_PRIORITY type client CCB command */ typedef struct { - IMG_UINT32 ui32Priority; /*!< Priority level */ + IMG_INT32 i32Priority; /*!< Priority level */ } RGXFWIF_CMD_PRIORITY; /*! @} End of ClientCCBTypes */ @@ -1719,6 +1753,7 @@ typedef struct IMG_BOOL bActivePMLatencyPersistant; /* If set, APM latency does not reset to system default each GPU power transition */ IMG_UINT32 ui32CoreClockSpeed; /* Core clock speed, currently only used to calculate timer ticks */ IMG_UINT32 ui32PowUnitsStateMask; /* Power Unit state mask set by the host */ + IMG_UINT32 ui32RACStateMask; /* RAC state mask set by the host */ IMG_UINT32 ui32PHRMode; /* Periodic Hardware Reset configuration values */ IMG_UINT32 ui32HCSDeadlineMS; /* New number of milliseconds C/S is allowed to last */ IMG_UINT32 ui32WdgPeriodUs; /* The watchdog period in microseconds */ @@ -1822,8 +1857,6 @@ typedef enum FW_PERF_CONF_NONE = 0, FW_PERF_CONF_ICACHE = 1, FW_PERF_CONF_DCACHE = 2, - FW_PERF_CONF_POLLS = 3, - FW_PERF_CONF_CUSTOM_TIMER = 4, FW_PERF_CONF_JTLB_INSTR = 5, FW_PERF_CONF_INSTRUCTIONS = 6 } FW_PERF_CONF; @@ -2000,9 +2033,13 @@ typedef struct IMG_UINT32 ui32OSKickTest; #endif +#if defined(SUPPORT_AUTOVZ) + IMG_UINT32 ui32VzWdgPeriod; +#endif + } UNCACHED_ALIGN RGXFWIF_SYSINIT; -static_assert(sizeof(RGXFWIF_SYSINIT) <= 952, +static_assert(sizeof(RGXFWIF_SYSINIT) <= 968, "Size of structure RGXFWIF_SYSINIT exceeds maximum expected size."); #if defined(SUPPORT_GPUVIRT_VALIDATION) @@ -2131,95 +2168,42 @@ typedef struct IMG_UINT32 ui32RTACtlFlags; /* Compatibility and other flags */ } UNCACHED_ALIGN RGXFWIF_RTA_CTL; -/*! @Brief Firmware Freelist holding usage state of the Parameter Buffers */ +/*! + * @InGroup RenderTarget + * @Brief Firmware Freelist holding usage state of the Parameter Buffers + */ typedef struct { - IMG_DEV_VIRTADDR RGXFW_ALIGN sFreeListBaseDevVAddr; /*!< Free list device base address */ - IMG_DEV_VIRTADDR RGXFW_ALIGN sFreeListStateDevVAddr; /*!< Free list state buffer */ - IMG_DEV_VIRTADDR RGXFW_ALIGN sFreeListLastGrowDevVAddr; /*!< Free list base address at last grow */ + IMG_DEV_VIRTADDR RGXFW_ALIGN sFreeListBaseDevVAddr; /*!< Freelist page table base address */ + IMG_DEV_VIRTADDR RGXFW_ALIGN sFreeListStateDevVAddr; /*!< Freelist state buffer base address */ + IMG_DEV_VIRTADDR RGXFW_ALIGN sFreeListLastGrowDevVAddr; /*!< Freelist base address at last grow */ #if defined(PM_INTERACTIVE_MODE) - IMG_UINT64 RGXFW_ALIGN ui64CurrentDevVAddr; - IMG_UINT32 ui32CurrentStackTop; + IMG_UINT64 RGXFW_ALIGN ui64CurrentDevVAddr;/*!< Freelist page table entry for current free page */ + IMG_UINT32 ui32CurrentStackTop; /*!< Freelist current free page */ #endif - IMG_UINT32 ui32MaxPages; - IMG_UINT32 ui32GrowPages; - IMG_UINT32 ui32CurrentPages; /* HW pages */ + IMG_UINT32 ui32MaxPages; /*!< Max no. of pages can be added to the freelist */ + IMG_UINT32 ui32GrowPages; /*!< No pages to add in each freelist grow */ + IMG_UINT32 ui32CurrentPages; /*!< Total no. of pages made available to the PM HW */ #if defined(PM_INTERACTIVE_MODE) - IMG_UINT32 ui32AllocatedPageCount; - IMG_UINT32 ui32AllocatedMMUPageCount; + IMG_UINT32 ui32AllocatedPageCount; /*!< No. of pages allocated by PM HW */ + IMG_UINT32 ui32AllocatedMMUPageCount; /*!< No. of pages allocated for GPU MMU for PM*/ #endif #if defined(SUPPORT_SHADOW_FREELISTS) - IMG_UINT32 ui32HWRCounter; + IMG_UINT32 ui32HWRCounter; PRGXFWIF_FWMEMCONTEXT psFWMemContext; #endif - IMG_UINT32 ui32FreeListID; - IMG_BOOL bGrowPending; - IMG_UINT32 ui32ReadyPages; /* Pages that should be used only when OOM is reached */ - IMG_UINT32 ui32FreelistFlags; /* Compatibility and other flags */ + IMG_UINT32 ui32FreeListID; /*!< Unique Freelist ID */ + IMG_BOOL bGrowPending; /*!< Freelist grow is pending */ + IMG_UINT32 ui32ReadyPages; /*!< Reserved pages to be used only on PM OOM event */ + IMG_UINT32 ui32FreelistFlags; /*!< Compatibility and other flags */ - IMG_BOOL bUpdatePending; - IMG_UINT32 ui32UpdateNewPages; - IMG_UINT32 ui32UpdateNewReadyPages; + IMG_BOOL bUpdatePending; + IMG_UINT32 ui32UpdateNewPages; + IMG_UINT32 ui32UpdateNewReadyPages; } UNCACHED_ALIGN RGXFWIF_FREELIST; - -#if defined(SUPPORT_SW_TRP) -#define SW_TRP_SIGNATURE_FIRST_KICK 0U -#define SW_TRP_SIGNATURE_SECOND_KICK 1U -#define SW_TRP_SIGNATURE_COUNT 2U -#define SW_TRP_GEOMETRY_SIGNATURE_SIZE 8U -#define SW_TRP_FRAGMENT_SIGNATURE_SIZE 8U -/* Space for tile usage bitmap, one bit per tile on screen */ -#define RGX_FEATURE_TILE_SIZE_X (32U) -#define RGX_FEATURE_TILE_SIZE_Y (32U) -#define SW_TRP_TILE_USED_SIZE ((ROGUE_RENDERSIZE_MAXX / RGX_FEATURE_TILE_SIZE_X + ROGUE_RENDERSIZE_MAXY / RGX_FEATURE_TILE_SIZE_Y) / (8U * sizeof(IMG_UINT32))) -#endif - -/*! - ****************************************************************************** - * Parameter Management (PM) control data for RGX - *****************************************************************************/ -typedef enum -{ - RGXFW_SPM_STATE_NONE = 0, - RGXFW_SPM_STATE_PR_BLOCKED, - RGXFW_SPM_STATE_WAIT_FOR_GROW, - RGXFW_SPM_STATE_WAIT_FOR_HW, - RGXFW_SPM_STATE_PR_RUNNING, - RGXFW_SPM_STATE_PR_AVOIDED, - RGXFW_SPM_STATE_PR_EXECUTED, - RGXFW_SPM_STATE_PR_FORCEFREE, -} RGXFW_SPM_STATE; - -/*! - ****************************************************************************** - * @Brief RGX firmware SPM Control Data: - * This structure holds all the internal SPM control Data of the firmware. - *****************************************************************************/ -typedef struct -{ - RGXFW_SPM_STATE eSPMState; /*!< Current state of TA OOM event */ - RGXFWIF_UFO sPartialRenderTA3DFence; /*!< TA/3D fence object holding the value to let through the 3D partial command */ -#if defined(RGX_FIRMWARE) - RGXFWIF_FWCOMMONCONTEXT *ps3dContext; /*!< Pointer to the 3D Context holding the partial render */ - RGXFWIF_PRBUFFER *apsPRBuffer[RGXFWIF_PRBUFFER_MAXSUPPORTED]; /*!< Array of pointers to PR Buffers which may be used if partial render is needed */ -#else - RGXFWIF_DEV_VIRTADDR ps3dContext; /*!< Pointer to the 3D Context holding the partial render */ - RGXFWIF_DEV_VIRTADDR apsPRBuffer[RGXFWIF_PRBUFFER_MAXSUPPORTED]; /*!< Array of pointers to PR Buffers which may be used if partial render is needed */ -#endif - IMG_UINT32 ui32CmdOffset; /*!< CCCB offset of the command holding the partial render */ - bool b3DMemFreeDetected; /*!< Indicates if a 3D Memory Free has been detected, which resolves OOM */ -#if defined(SUPPORT_AGP) - IMG_UINT32 ui32OOMCoreMask; /*!< Mask of all the cores that are OOM */ - RGXFWIF_DM eCurrentDM; /*!< Current DM that is in SPM */ -#endif -} RGXFW_ALIGN_DCACHEL RGXFW_SPMCTL; - -static_assert(sizeof(RGXFW_SPMCTL) <= 64, - "Size of structure RGXFW_SPMCTL exceeds maximum expected size."); - /*! ****************************************************************************** * HWRTData @@ -2227,13 +2211,16 @@ static_assert(sizeof(RGXFW_SPMCTL) <= 64, /* HWRTData flags */ /* Deprecated flags 1:0 */ -#define HWRTDATA_HAS_LAST_TA (1U << 2) -#define HWRTDATA_PARTIAL_RENDERED (1U << 3) -#define HWRTDATA_KILLED (1U << 4) -#define HWRTDATA_KILL_AFTER_TARESTART (1U << 5) +#define HWRTDATA_HAS_LAST_TA (1UL << 2) +#define HWRTDATA_PARTIAL_RENDERED (1UL << 3) +#define HWRTDATA_KILLED (1UL << 4) +#define HWRTDATA_KILL_AFTER_TARESTART (1UL << 5) #if defined(SUPPORT_AGP) -#define HWRTDATA_USE_SECONDARY_GLOBAL_PB (1U << 6) -#define HWRTDATA_GEOM_NEEDS_RESUME (1U << 7) +#define HWRTDATA_GLOBAL_PB_NUMBER_BIT0 (1UL << 6) +#if defined(SUPPORT_AGP4) +#define HWRTDATA_GLOBAL_PB_NUMBER_BIT1 (1UL << 7) +#endif +#define HWRTDATA_GEOM_NEEDS_RESUME (1UL << 8) #endif typedef enum @@ -2273,67 +2260,54 @@ typedef struct IMG_UINT32 ui32ISPMergeScaleY; } UNCACHED_ALIGN RGXFWIF_HWRTDATA_COMMON; -/*! @Brief Firmware Render Target data i.e. HWRTDATA used to hold the PM context */ +/*! + * @InGroup RenderTarget + * @Brief Firmware Render Target data i.e. HWRTDATA used to hold the PM context + */ typedef struct { - IMG_UINT64 RGXFW_ALIGN ui64VCECatBase[4]; - IMG_UINT64 RGXFW_ALIGN ui64VCELastCatBase[4]; - IMG_UINT64 RGXFW_ALIGN ui64TECatBase[4]; - IMG_UINT64 RGXFW_ALIGN ui64TELastCatBase[4]; - IMG_UINT64 RGXFW_ALIGN ui64AlistCatBase; - IMG_UINT64 RGXFW_ALIGN ui64AlistLastCatBase; + IMG_UINT64 RGXFW_ALIGN ui64VCECatBase[4]; /*!< VCE Page Catalogue base */ + IMG_UINT64 RGXFW_ALIGN ui64VCELastCatBase[4]; + IMG_UINT64 RGXFW_ALIGN ui64TECatBase[4]; /*!< TE Page Catalogue base */ + IMG_UINT64 RGXFW_ALIGN ui64TELastCatBase[4]; + IMG_UINT64 RGXFW_ALIGN ui64AlistCatBase; /*!< Alist Page Catalogue base */ + IMG_UINT64 RGXFW_ALIGN ui64AlistLastCatBase; #if defined(PM_INTERACTIVE_MODE) - IMG_DEV_VIRTADDR RGXFW_ALIGN psVHeapTableDevVAddr; - IMG_DEV_VIRTADDR RGXFW_ALIGN sPMMListDevVAddr; + IMG_DEV_VIRTADDR RGXFW_ALIGN psVHeapTableDevVAddr; /*!< VHeap table base */ + IMG_DEV_VIRTADDR RGXFW_ALIGN sPMMListDevVAddr; /*!< Mlist table base */ #else - /* Series8 PM State buffers */ - IMG_DEV_VIRTADDR RGXFW_ALIGN sPMRenderStateDevVAddr; - IMG_DEV_VIRTADDR RGXFW_ALIGN sPMSecureRenderStateDevVAddr; + IMG_DEV_VIRTADDR RGXFW_ALIGN sPMRenderStateDevVAddr; /*!< Series8 PM State buffers */ + IMG_DEV_VIRTADDR RGXFW_ALIGN sPMSecureRenderStateDevVAddr; #endif - PRGXFWIF_FREELIST RGXFW_ALIGN apsFreeLists[RGXFW_MAX_FREELISTS]; - IMG_UINT32 aui32FreeListHWRSnapshot[RGXFW_MAX_FREELISTS]; - IMG_BOOL bRenderStateNeedsReset; + PRGXFWIF_FREELIST RGXFW_ALIGN apsFreeLists[RGXFW_MAX_FREELISTS]; /*!< Freelist to use */ + IMG_UINT32 aui32FreeListHWRSnapshot[RGXFW_MAX_FREELISTS]; + IMG_BOOL bRenderStateNeedsReset; - RGXFWIF_DEV_VIRTADDR sHWRTDataCommonFwAddr; + RGXFWIF_DEV_VIRTADDR sHWRTDataCommonFwAddr; /*!< Render target dimension dependent data */ - IMG_UINT32 ui32HWRTDataFlags; - RGXFWIF_RTDATA_STATE eState; + IMG_UINT32 ui32HWRTDataFlags; + RGXFWIF_RTDATA_STATE eState; /*!< Current workload processing state of HWRTDATA */ - RGXFWIF_CLEANUP_CTL sCleanupState; + RGXFWIF_CLEANUP_CTL sCleanupState; /*!< Render target clean up state */ - RGXFWIF_RTA_CTL sRTACtl; + RGXFWIF_RTA_CTL sRTACtl; /*!< Render target array data */ - IMG_DEV_VIRTADDR RGXFW_ALIGN sTailPtrsDevVAddr; + IMG_DEV_VIRTADDR RGXFW_ALIGN sTailPtrsDevVAddr; /*!< Tail pointers base */ #if defined(RGX_FIRMWARE) - struct RGXFWIF_FWCOMMONCONTEXT_* psOwnerGeom; + struct RGXFWIF_FWCOMMONCONTEXT_* psOwnerGeom; #else - RGXFWIF_DEV_VIRTADDR pui32OwnerGeomNotUsedByHost; + RGXFWIF_DEV_VIRTADDR pui32OwnerGeomNotUsedByHost; #endif #if defined(PM_INTERACTIVE_MODE) - IMG_UINT64 RGXFW_ALIGN ui64PMAListStackPointer; - IMG_UINT32 ui32PMMListStackPointer; -#endif -#if defined(SUPPORT_SW_TRP) - /* SW-TRP state and signature data - * - * Stored state is used to kick the same geometry or 3D twice, - * State is stored before first kick and restored before second to rerun the same data. - * Signatures from both kicks are stored and compared */ - IMG_UINT32 aaui32GeometrySignature[SW_TRP_SIGNATURE_COUNT][SW_TRP_GEOMETRY_SIGNATURE_SIZE]; - IMG_UINT32 aaui32FragmentSignature[SW_TRP_SIGNATURE_COUNT][SW_TRP_FRAGMENT_SIGNATURE_SIZE]; - IMG_UINT32 ui32KickFlagsCopy; - IMG_UINT32 ui32SW_TRPState; - IMG_UINT32 aui32TileUsed[SW_TRP_TILE_USED_SIZE]; - RGXFW_SPMCTL sSPMCtlCopy; + IMG_UINT64 RGXFW_ALIGN ui64PMAListStackPointer; /*!< Freelist page table entry for current Mlist page */ + IMG_UINT32 ui32PMMListStackPointer; /*!< Current Mlist page */ #endif #if defined(SUPPORT_TRP) - IMG_UINT32 ui32KickFlagsCopy; - IMG_UINT32 ui32TRPState; - RGXFWIF_TRP_CHECKSUM_3D aui64TRPChecksums3D; - RGXFWIF_TRP_CHECKSUM_GEOM aui64TRPChecksumsGeom; + IMG_UINT32 ui32KickFlagsCopy; + IMG_UINT32 ui32TRPState; #endif } UNCACHED_ALIGN RGXFWIF_HWRTDATA; diff --git a/drivers/gpu/drm/img-rogue/include/volcanic/rgx_fwif_shared.h b/drivers/gpu/drm/img-rogue/include/volcanic/rgx_fwif_shared.h index 570ccdd68..ad7cb3213 100644 --- a/drivers/gpu/drm/img-rogue/include/volcanic/rgx_fwif_shared.h +++ b/drivers/gpu/drm/img-rogue/include/volcanic/rgx_fwif_shared.h @@ -52,10 +52,17 @@ CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. /* Indicates the number of RTDATAs per RTDATASET */ #if defined(SUPPORT_AGP) +#if defined(SUPPORT_AGP4) +#define RGXMKIF_NUM_RTDATAS 4U +#define RGXMKIF_NUM_GEOMDATAS 4U +#define RGXMKIF_NUM_RTDATA_FREELISTS 20U /* RGXMKIF_NUM_RTDATAS * RGXFW_MAX_FREELISTS */ +#define RGX_NUM_GEOM_CORES (4U) +#else #define RGXMKIF_NUM_RTDATAS 4U #define RGXMKIF_NUM_GEOMDATAS 4U #define RGXMKIF_NUM_RTDATA_FREELISTS 12U /* RGXMKIF_NUM_RTDATAS * RGXFW_MAX_FREELISTS */ #define RGX_NUM_GEOM_CORES (2U) +#endif #else #define RGXMKIF_NUM_RTDATAS 2U #define RGXMKIF_NUM_GEOMDATAS 1U @@ -131,13 +138,17 @@ typedef enum RGXFWIF_PRBUFFER_UNBACKING_PENDING, }RGXFWIF_PRBUFFER_STATE; +/*! + * @InGroup RenderTarget + * @Brief OnDemand Z/S/MSAA Buffers + */ typedef struct { - IMG_UINT32 ui32BufferID; /*!< Buffer ID*/ - IMG_BOOL bOnDemand; /*!< Needs On-demand Z/S/MSAA Buffer allocation */ - RGXFWIF_PRBUFFER_STATE eState; /*!< Z/S/MSAA -Buffer state */ - RGXFWIF_CLEANUP_CTL sCleanupState; /*!< Cleanup state */ - IMG_UINT32 ui32PRBufferFlags; /*!< Compatibility and other flags */ + IMG_UINT32 ui32BufferID; /*!< Buffer ID*/ + IMG_BOOL bOnDemand; /*!< Needs On-demand Z/S/MSAA Buffer allocation */ + RGXFWIF_PRBUFFER_STATE eState; /*!< Z/S/MSAA -Buffer state */ + RGXFWIF_CLEANUP_CTL sCleanupState; /*!< Cleanup state */ + IMG_UINT32 ui32PRBufferFlags; /*!< Compatibility and other flags */ } UNCACHED_ALIGN RGXFWIF_PRBUFFER; /* @@ -201,6 +212,10 @@ typedef struct in bytes of the CCB-1 */ #if defined(SUPPORT_AGP) IMG_UINT32 ui32ReadOffset2; +#if defined(SUPPORT_AGP4) + IMG_UINT32 ui32ReadOffset3; + IMG_UINT32 ui32ReadOffset4; +#endif #endif } UNCACHED_ALIGN RGXFWIF_CCCB_CTL; @@ -209,7 +224,12 @@ typedef IMG_UINT32 RGXFW_FREELIST_TYPE; #define RGXFW_LOCAL_FREELIST IMG_UINT32_C(0) #define RGXFW_GLOBAL_FREELIST IMG_UINT32_C(1) -#if defined(SUPPORT_AGP) +#if defined(SUPPORT_AGP4) +#define RGXFW_GLOBAL2_FREELIST IMG_UINT32_C(2) +#define RGXFW_GLOBAL3_FREELIST IMG_UINT32_C(3) +#define RGXFW_GLOBAL4_FREELIST IMG_UINT32_C(4) +#define RGXFW_MAX_FREELISTS (RGXFW_GLOBAL4_FREELIST + 1U) +#elif defined(SUPPORT_AGP) #define RGXFW_GLOBAL2_FREELIST IMG_UINT32_C(2) #define RGXFW_MAX_FREELISTS (RGXFW_GLOBAL2_FREELIST + 1U) #else diff --git a/drivers/gpu/drm/img-rogue/include/volcanic/rgx_hwperf.h b/drivers/gpu/drm/img-rogue/include/volcanic/rgx_hwperf.h index 4a88727d1..408b76901 100644 --- a/drivers/gpu/drm/img-rogue/include/volcanic/rgx_hwperf.h +++ b/drivers/gpu/drm/img-rogue/include/volcanic/rgx_hwperf.h @@ -60,6 +60,7 @@ extern "C" { #include "img_defs.h" #include "rgx_common.h" +#include "rgx_hwperf_common.h" #include "pvrsrv_tlcommon.h" #include "pvrsrv_sync_km.h" @@ -77,400 +78,6 @@ static_assert(RGX_FEATURE_NUM_CLUSTERS <= 16U, #define RGX_HWPERF_CTRL_COMP_FULLRANGE (2U) /*!< selectable compute counters are full range */ #define RGX_HWPERF_CTRL_TDM_FULLRANGE (4U) /*!< selectable TDM counters are full range */ -/****************************************************************************** - * Packet Event Type Enumerations - *****************************************************************************/ - -/*! Type used to encode the event that generated the packet. - * NOTE: When this type is updated the corresponding hwperfbin2json tool - * source needs to be updated as well. The RGX_HWPERF_EVENT_MASK_* macros will - * also need updating when adding new types. - * - * @par - * The event type values are incrementing integers for use as a shift ordinal - * in the event filtering process at the point events are generated. - * This scheme thus implies a limit of 63 event types. - */ - -typedef IMG_UINT32 RGX_HWPERF_EVENT_TYPE; - -#define RGX_HWPERF_INVALID 0x00U /*!< Invalid. Reserved value. */ - -/*! FW types 0x01..0x06 */ -#define RGX_HWPERF_FW_EVENT_RANGE_FIRST_TYPE 0x01U - -#define RGX_HWPERF_FW_BGSTART 0x01U /*!< Background task processing start */ -#define RGX_HWPERF_FW_BGEND 0x02U /*!< Background task end */ -#define RGX_HWPERF_FW_IRQSTART 0x03U /*!< IRQ task processing start */ - -#define RGX_HWPERF_FW_IRQEND 0x04U /*!< IRQ task end */ -#define RGX_HWPERF_FW_DBGSTART 0x05U /*!< Debug event start */ -#define RGX_HWPERF_FW_DBGEND 0x06U /*!< Debug event end */ - -#define RGX_HWPERF_FW_EVENT_RANGE_LAST_TYPE 0x06U - -/*! HW types 0x07..0x19 */ -#define RGX_HWPERF_HW_EVENT_RANGE0_FIRST_TYPE 0x07U - -#define RGX_HWPERF_HW_PMOOM_TAPAUSE 0x07U /*!< TA Pause at PM Out of Memory */ - -#define RGX_HWPERF_HW_TAKICK 0x08U /*!< TA task started */ -#define RGX_HWPERF_HW_TAFINISHED 0x09U /*!< TA task finished */ -#define RGX_HWPERF_HW_3DTQKICK 0x0AU /*!< 3D TQ started */ -#define RGX_HWPERF_HW_3DKICK 0x0BU /*!< 3D task started */ -#define RGX_HWPERF_HW_3DFINISHED 0x0CU /*!< 3D task finished */ -#define RGX_HWPERF_HW_CDMKICK 0x0DU /*!< CDM task started */ -#define RGX_HWPERF_HW_CDMFINISHED 0x0EU /*!< CDM task finished */ -#define RGX_HWPERF_HW_TLAKICK 0x0FU /*!< TLA task started */ -#define RGX_HWPERF_HW_TLAFINISHED 0x10U /*!< TLS task finished */ -#define RGX_HWPERF_HW_3DSPMKICK 0x11U /*!< 3D SPM task started */ -#define RGX_HWPERF_HW_PERIODIC 0x12U /*!< Periodic event with updated HW counters */ -#define RGX_HWPERF_HW_RTUKICK 0x13U /*!< Reserved, future use */ -#define RGX_HWPERF_HW_RTUFINISHED 0x14U /*!< Reserved, future use */ -#define RGX_HWPERF_HW_SHGKICK 0x15U /*!< Reserved, future use */ -#define RGX_HWPERF_HW_SHGFINISHED 0x16U /*!< Reserved, future use */ -#define RGX_HWPERF_HW_3DTQFINISHED 0x17U /*!< 3D TQ finished */ -#define RGX_HWPERF_HW_3DSPMFINISHED 0x18U /*!< 3D SPM task finished */ - -#define RGX_HWPERF_HW_PMOOM_TARESUME 0x19U /*!< TA Resume after PM Out of Memory */ - -/*! HW_EVENT_RANGE0 used up. Use next empty range below to add new hardware events */ -#define RGX_HWPERF_HW_EVENT_RANGE0_LAST_TYPE 0x19U - -/*! other types 0x1A..0x1F */ -#define RGX_HWPERF_CLKS_CHG 0x1AU /*!< Clock speed change in GPU */ -#define RGX_HWPERF_GPU_STATE_CHG 0x1BU /*!< GPU work state change */ - -/*! power types 0x20..0x27 */ -#define RGX_HWPERF_PWR_EST_RANGE_FIRST_TYPE 0x20U -#define RGX_HWPERF_PWR_EST_REQUEST 0x20U /*!< Power estimate requested (via GPIO) */ -#define RGX_HWPERF_PWR_EST_READY 0x21U /*!< Power estimate inputs ready */ -#define RGX_HWPERF_PWR_EST_RESULT 0x22U /*!< Power estimate result calculated */ -#define RGX_HWPERF_PWR_EST_RANGE_LAST_TYPE 0x22U - -#define RGX_HWPERF_PWR_CHG 0x23U /*!< Power state change */ - -/*! HW_EVENT_RANGE1 0x28..0x2F, for accommodating new hardware events */ -#define RGX_HWPERF_HW_EVENT_RANGE1_FIRST_TYPE 0x28U - -#define RGX_HWPERF_HW_TDMKICK 0x28U /*!< TDM task started */ -#define RGX_HWPERF_HW_TDMFINISHED 0x29U /*!< TDM task finished */ -#define RGX_HWPERF_HW_NULLKICK 0x2AU /*!< NULL event */ - -#define RGX_HWPERF_HW_EVENT_RANGE1_LAST_TYPE 0x2AU - -/*! context switch types 0x30..0x31 */ -#define RGX_HWPERF_CSW_START 0x30U /*!< HW context store started */ -#define RGX_HWPERF_CSW_FINISHED 0x31U /*!< HW context store finished */ - -/*! DVFS events */ -#define RGX_HWPERF_DVFS 0x32U /*!< Dynamic voltage/frequency scaling events */ - -/*! firmware misc 0x38..0x39 */ -#define RGX_HWPERF_UFO 0x38U /*!< FW UFO Check / Update */ -#define RGX_HWPERF_FWACT 0x39U /*!< FW Activity notification */ - -/*! last */ -#define RGX_HWPERF_LAST_TYPE 0x3BU - -/*! This enumeration must have a value that is a power of two as it is - * used in masks and a filter bit field (currently 64 bits long). - */ -#define RGX_HWPERF_MAX_TYPE 0x40U - -static_assert(RGX_HWPERF_LAST_TYPE < RGX_HWPERF_MAX_TYPE, "Too many HWPerf event types"); - -/*! Macro used to check if an event type ID is present in the known set of hardware type events */ -#define HWPERF_PACKET_IS_HW_TYPE(_etype) (((_etype) >= RGX_HWPERF_HW_EVENT_RANGE0_FIRST_TYPE && (_etype) <= RGX_HWPERF_HW_EVENT_RANGE0_LAST_TYPE) || \ - ((_etype) >= RGX_HWPERF_HW_EVENT_RANGE1_FIRST_TYPE && (_etype) <= RGX_HWPERF_HW_EVENT_RANGE1_LAST_TYPE)) - -/*! Macro used to check if an event type ID is present in the known set of firmware type events */ -#define HWPERF_PACKET_IS_FW_TYPE(_etype) \ - ((_etype) >= RGX_HWPERF_FW_EVENT_RANGE_FIRST_TYPE && \ - (_etype) <= RGX_HWPERF_FW_EVENT_RANGE_LAST_TYPE) - - -typedef enum { - RGX_HWPERF_HOST_INVALID = 0x00, /*!< Invalid, do not use. */ - RGX_HWPERF_HOST_ENQ = 0x01, /*!< ``0x01`` Kernel driver has queued GPU work. - See RGX_HWPERF_HOST_ENQ_DATA */ - RGX_HWPERF_HOST_UFO = 0x02, /*!< ``0x02`` UFO updated by the driver. - See RGX_HWPERF_HOST_UFO_DATA */ - RGX_HWPERF_HOST_ALLOC = 0x03, /*!< ``0x03`` Resource allocated. - See RGX_HWPERF_HOST_ALLOC_DATA */ - RGX_HWPERF_HOST_CLK_SYNC = 0x04, /*!< ``0x04`` GPU / Host clocks correlation data. - See RGX_HWPERF_HOST_CLK_SYNC_DATA */ - RGX_HWPERF_HOST_FREE = 0x05, /*!< ``0x05`` Resource freed, - See RGX_HWPERF_HOST_FREE_DATA */ - RGX_HWPERF_HOST_MODIFY = 0x06, /*!< ``0x06`` Resource modified / updated. - See RGX_HWPERF_HOST_MODIFY_DATA */ - RGX_HWPERF_HOST_DEV_INFO = 0x07, /*!< ``0x07`` Device Health status. - See RGX_HWPERF_HOST_DEV_INFO_DATA */ - RGX_HWPERF_HOST_INFO = 0x08, /*!< ``0x08`` Device memory usage information. - See RGX_HWPERF_HOST_INFO_DATA */ - RGX_HWPERF_HOST_SYNC_FENCE_WAIT = 0x09, /*!< ``0x09`` Wait for sync event. - See RGX_HWPERF_HOST_SYNC_FENCE_WAIT_DATA */ - RGX_HWPERF_HOST_SYNC_SW_TL_ADVANCE = 0x0A, /*!< ``0x0A`` Software timeline advanced. - See RGX_HWPERF_HOST_SYNC_SW_TL_ADV_DATA */ - - /*! last */ - RGX_HWPERF_HOST_LAST_TYPE, - - /*! This enumeration must have a value that is a power of two as it is - * used in masks and a filter bit field (currently 32 bits long). - */ - RGX_HWPERF_HOST_MAX_TYPE = 0x20 -} RGX_HWPERF_HOST_EVENT_TYPE; - -/*!< The event type values are incrementing integers for use as a shift ordinal - * in the event filtering process at the point events are generated. - * This scheme thus implies a limit of 31 event types. - */ -static_assert(RGX_HWPERF_HOST_LAST_TYPE < RGX_HWPERF_HOST_MAX_TYPE, "Too many HWPerf host event types"); - - -/****************************************************************************** - * Packet Header Format Version 2 Types - *****************************************************************************/ - -/*! Major version number of the protocol in operation - */ -#define RGX_HWPERF_V2_FORMAT 2 - -/*! Signature ASCII pattern 'HWP2' found in the first word of a HWPerfV2 packet - */ -#define HWPERF_PACKET_V2_SIG 0x48575032 - -/*! Signature ASCII pattern 'HWPA' found in the first word of a HWPerfV2a packet - */ -#define HWPERF_PACKET_V2A_SIG 0x48575041 - -/*! Signature ASCII pattern 'HWPB' found in the first word of a HWPerfV2b packet - */ -#define HWPERF_PACKET_V2B_SIG 0x48575042 - -/*! Signature ASCII pattern 'HWPC' found in the first word of a HWPerfV2c packet - */ -#define HWPERF_PACKET_V2C_SIG 0x48575043 - -#define HWPERF_PACKET_ISVALID(_val) (((_val) == HWPERF_PACKET_V2_SIG) || ((_val) == HWPERF_PACKET_V2A_SIG) || ((_val) == HWPERF_PACKET_V2B_SIG) || ((_val) == HWPERF_PACKET_V2C_SIG)) -/*!< Checks that the packet signature is one of the supported versions */ - -/*! Type defines the HWPerf packet header common to all events. */ -typedef struct -{ - IMG_UINT32 ui32Sig; /*!< Always the value HWPERF_PACKET_SIG */ - IMG_UINT32 ui32Size; /*!< Overall packet size in bytes */ - IMG_UINT32 eTypeId; /*!< Event type information field */ - IMG_UINT32 ui32Ordinal; /*!< Sequential number of the packet */ - IMG_UINT64 ui64Timestamp; /*!< Event timestamp */ -} RGX_HWPERF_V2_PACKET_HDR, *RGX_PHWPERF_V2_PACKET_HDR; - -RGX_FW_STRUCT_OFFSET_ASSERT(RGX_HWPERF_V2_PACKET_HDR, ui64Timestamp); - -RGX_FW_STRUCT_SIZE_ASSERT(RGX_HWPERF_V2_PACKET_HDR); - - -/*! Mask for use with the IMG_UINT32 ui32Size header field */ -#define RGX_HWPERF_SIZE_MASK 0xFFFFU - -/*! This macro defines an upper limit to which the size of the largest variable - * length HWPerf packet must fall within, currently 3KB. This constant may be - * used to allocate a buffer to hold one packet. - * This upper limit is policed by packet producing code. - */ -#define RGX_HWPERF_MAX_PACKET_SIZE 0xC00U - -/*! Defines an upper limit to the size of a variable length packet payload. - */ -#define RGX_HWPERF_MAX_PAYLOAD_SIZE ((IMG_UINT32)(RGX_HWPERF_MAX_PACKET_SIZE-\ - sizeof(RGX_HWPERF_V2_PACKET_HDR))) - -/*! Macro which takes a structure name and provides the packet size for - * a fixed size payload packet, rounded up to 8 bytes to align packets - * for 64 bit architectures. */ -#define RGX_HWPERF_MAKE_SIZE_FIXED(_struct) ((IMG_UINT32)(RGX_HWPERF_SIZE_MASK&(sizeof(RGX_HWPERF_V2_PACKET_HDR)+PVR_ALIGN(sizeof(_struct), PVRSRVTL_PACKET_ALIGNMENT)))) - -/*! Macro which takes the number of bytes written in the data payload of a - * packet for a variable size payload packet, rounded up to 8 bytes to - * align packets for 64 bit architectures. */ -#define RGX_HWPERF_MAKE_SIZE_VARIABLE(_size) ((IMG_UINT32)(RGX_HWPERF_SIZE_MASK&(sizeof(RGX_HWPERF_V2_PACKET_HDR)+PVR_ALIGN((_size), PVRSRVTL_PACKET_ALIGNMENT)))) - -/*! Macro to obtain the size of the packet */ -#define RGX_HWPERF_GET_SIZE(_packet_addr) ((IMG_UINT16)(((_packet_addr)->ui32Size) & RGX_HWPERF_SIZE_MASK)) - -/*! Macro to obtain the size of the packet data */ -#define RGX_HWPERF_GET_DATA_SIZE(_packet_addr) (RGX_HWPERF_GET_SIZE(_packet_addr) - sizeof(RGX_HWPERF_V2_PACKET_HDR)) - -/*! Masks for use with the IMG_UINT32 eTypeId header field */ -#define RGX_HWPERF_TYPEID_MASK 0x0007FFFFU -#define RGX_HWPERF_TYPEID_EVENT_MASK 0x00007FFFU -#define RGX_HWPERF_TYPEID_THREAD_MASK 0x00008000U -#define RGX_HWPERF_TYPEID_STREAM_MASK 0x00070000U -#define RGX_HWPERF_TYPEID_META_DMA_MASK 0x00080000U -#define RGX_HWPERF_TYPEID_M_CORE_MASK 0x00100000U -#define RGX_HWPERF_TYPEID_OSID_MASK 0x07000000U - -/*! Meta thread macros for encoding the ID into the type field of a packet */ -#define RGX_HWPERF_META_THREAD_SHIFT 15U -#define RGX_HWPERF_META_THREAD_ID0 0x0U /*!< Meta Thread 0 ID */ -#define RGX_HWPERF_META_THREAD_ID1 0x1U /*!< Meta Thread 1 ID */ -/*! Obsolete, kept for source compatibility */ -#define RGX_HWPERF_META_THREAD_MASK 0x1U -/*! Stream ID macros for encoding the ID into the type field of a packet */ -#define RGX_HWPERF_STREAM_SHIFT 16U -/*! Meta DMA macro for encoding how the packet was generated into the type field of a packet */ -#define RGX_HWPERF_META_DMA_SHIFT 19U -/*! Bit-shift macro used for encoding multi-core data into the type field of a packet */ -#define RGX_HWPERF_M_CORE_SHIFT 20U -/*! OSID bit-shift macro used for encoding OSID into type field of a packet */ -#define RGX_HWPERF_OSID_SHIFT 24U -typedef enum { - RGX_HWPERF_STREAM_ID0_FW, /*!< Events from the Firmware/GPU */ - RGX_HWPERF_STREAM_ID1_HOST, /*!< Events from the Server host driver component */ - RGX_HWPERF_STREAM_ID2_CLIENT, /*!< Events from the Client host driver component */ - RGX_HWPERF_STREAM_ID_LAST, -} RGX_HWPERF_STREAM_ID; - -/* Checks if all stream IDs can fit under RGX_HWPERF_TYPEID_STREAM_MASK. */ -static_assert(((IMG_UINT32)RGX_HWPERF_STREAM_ID_LAST - 1U) < (RGX_HWPERF_TYPEID_STREAM_MASK >> RGX_HWPERF_STREAM_SHIFT), - "Too many HWPerf stream IDs."); - -/*! Compile-time value used to seed the Multi-Core (MC) bit in the typeID field. - * Only set by RGX_FIRMWARE builds. - */ -#if defined(RGX_FIRMWARE) -# if defined(RGX_FEATURE_GPU_MULTICORE_SUPPORT) -#define RGX_HWPERF_M_CORE_VALUE 1U /*!< 1 => Multi-core supported */ -# else -#define RGX_HWPERF_M_CORE_VALUE 0U /*!< 0 => Multi-core not supported */ -# endif -#else -#define RGX_HWPERF_M_CORE_VALUE 0U /*!< 0 => Multi-core not supported */ -#endif - -/*! Macros used to set the packet type and encode meta thread ID (0|1), - * HWPerf stream ID, multi-core capability and OSID within the typeID */ -#define RGX_HWPERF_MAKE_TYPEID(_stream, _type, _thread, _metadma, _osid)\ - ((IMG_UINT32) ((RGX_HWPERF_TYPEID_STREAM_MASK&((IMG_UINT32)(_stream) << RGX_HWPERF_STREAM_SHIFT)) | \ - (RGX_HWPERF_TYPEID_THREAD_MASK & ((IMG_UINT32)(_thread) << RGX_HWPERF_META_THREAD_SHIFT)) | \ - (RGX_HWPERF_TYPEID_EVENT_MASK & (IMG_UINT32)(_type)) | \ - (RGX_HWPERF_TYPEID_META_DMA_MASK & ((IMG_UINT32)(_metadma) << RGX_HWPERF_META_DMA_SHIFT)) | \ - (RGX_HWPERF_TYPEID_OSID_MASK & ((IMG_UINT32)(_osid) << RGX_HWPERF_OSID_SHIFT)) | \ - (RGX_HWPERF_TYPEID_M_CORE_MASK & ((IMG_UINT32)(RGX_HWPERF_M_CORE_VALUE) << RGX_HWPERF_M_CORE_SHIFT)))) - -/*! Obtains the event type that generated the packet */ -#define RGX_HWPERF_GET_TYPE(_packet_addr) (((_packet_addr)->eTypeId) & RGX_HWPERF_TYPEID_EVENT_MASK) - -/*! Obtains the META Thread number that generated the packet */ -#define RGX_HWPERF_GET_THREAD_ID(_packet_addr) (((((_packet_addr)->eTypeId) & RGX_HWPERF_TYPEID_THREAD_MASK) >> RGX_HWPERF_META_THREAD_SHIFT)) - -/*! Determines if the packet generated contains multi-core data */ -#define RGX_HWPERF_GET_M_CORE(_packet_addr) (((_packet_addr)->eTypeId & RGX_HWPERF_TYPEID_M_CORE_MASK) >> RGX_HWPERF_M_CORE_SHIFT) - -/*! Obtains the guest OSID which resulted in packet generation */ -#define RGX_HWPERF_GET_OSID(_packet_addr) (((_packet_addr)->eTypeId & RGX_HWPERF_TYPEID_OSID_MASK) >> RGX_HWPERF_OSID_SHIFT) - -/*! Obtain stream id */ -#define RGX_HWPERF_GET_STREAM_ID(_packet_addr) (((((_packet_addr)->eTypeId) & RGX_HWPERF_TYPEID_STREAM_MASK) >> RGX_HWPERF_STREAM_SHIFT)) - -/*! Obtain information about how the packet was generated, which might affect payload total size */ -#define RGX_HWPERF_GET_META_DMA_INFO(_packet_addr) (((((_packet_addr)->eTypeId) & RGX_HWPERF_TYPEID_META_DMA_MASK) >> RGX_HWPERF_META_DMA_SHIFT)) - -/*! Obtains a typed pointer to a packet given a buffer address */ -#define RGX_HWPERF_GET_PACKET(_buffer_addr) ((RGX_HWPERF_V2_PACKET_HDR *)(void *) (_buffer_addr)) -/*! Obtains a typed pointer to a data structure given a packet address */ -#define RGX_HWPERF_GET_PACKET_DATA_BYTES(_packet_addr) (IMG_OFFSET_ADDR((_packet_addr), sizeof(RGX_HWPERF_V2_PACKET_HDR))) -/*! Obtains a typed pointer to the next packet given a packet address */ -#define RGX_HWPERF_GET_NEXT_PACKET(_packet_addr) ((RGX_HWPERF_V2_PACKET_HDR *) (IMG_OFFSET_ADDR((_packet_addr), RGX_HWPERF_SIZE_MASK&((_packet_addr)->ui32Size)))) - -/*! Obtains a typed pointer to a packet header given the packet data address */ -#define RGX_HWPERF_GET_PACKET_HEADER(_packet_addr) ((RGX_HWPERF_V2_PACKET_HDR *) (IMG_OFFSET_ADDR((_packet_addr), -(IMG_INT32)sizeof(RGX_HWPERF_V2_PACKET_HDR)))) - - -/****************************************************************************** - * Other Common Defines - *****************************************************************************/ - -/*! This macro is not a real array size, but indicates the array has a variable - * length only known at run-time but always contains at least 1 element. The - * final size of the array is deduced from the size field of a packet header. - */ -#define RGX_HWPERF_ONE_OR_MORE_ELEMENTS 1U - -/*! This macro is not a real array size, but indicates the array is optional - * and if present has a variable length only known at run-time. The final - * size of the array is deduced from the size field of a packet header. */ -#define RGX_HWPERF_ZERO_OR_MORE_ELEMENTS 1U - - -/*! Masks for use with the IMG_UINT32 ui32BlkInfo field */ -#define RGX_HWPERF_BLKINFO_BLKCOUNT_MASK 0xFFFF0000U -#define RGX_HWPERF_BLKINFO_BLKOFFSET_MASK 0x0000FFFFU - -/*! Shift for the NumBlocks and counter block offset field in ui32BlkInfo */ -#define RGX_HWPERF_BLKINFO_BLKCOUNT_SHIFT 16U -#define RGX_HWPERF_BLKINFO_BLKOFFSET_SHIFT 0U - -/*! Macro used to set the block info word as a combination of two 16-bit integers */ -#define RGX_HWPERF_MAKE_BLKINFO(_numblks, _blkoffset) ((IMG_UINT32) ((RGX_HWPERF_BLKINFO_BLKCOUNT_MASK&((_numblks) << RGX_HWPERF_BLKINFO_BLKCOUNT_SHIFT)) | (RGX_HWPERF_BLKINFO_BLKOFFSET_MASK&((_blkoffset) << RGX_HWPERF_BLKINFO_BLKOFFSET_SHIFT)))) - -/*! Macro used to obtain the number of counter blocks present in the packet */ -#define RGX_HWPERF_GET_BLKCOUNT(_blkinfo) (((_blkinfo) & RGX_HWPERF_BLKINFO_BLKCOUNT_MASK) >> RGX_HWPERF_BLKINFO_BLKCOUNT_SHIFT) - -/*! Obtains the offset of the counter block stream in the packet */ -#define RGX_HWPERF_GET_BLKOFFSET(_blkinfo) (((_blkinfo) & RGX_HWPERF_BLKINFO_BLKOFFSET_MASK) >> RGX_HWPERF_BLKINFO_BLKOFFSET_SHIFT) - -/*! This macro gets the number of blocks depending on the packet version */ -#define RGX_HWPERF_GET_NUMBLKS(_sig, _packet_data, _numblocks) \ - do { \ - if (HWPERF_PACKET_V2B_SIG == _sig || HWPERF_PACKET_V2C_SIG == _sig) \ - { \ - (_numblocks) = RGX_HWPERF_GET_BLKCOUNT((_packet_data)->ui32BlkInfo);\ - } \ - else \ - { \ - IMG_UINT32 ui32VersionOffset = (((_sig) == HWPERF_PACKET_V2_SIG) ? 1 : 3);\ - (_numblocks) = *(IMG_UINT16 *)(IMG_OFFSET_ADDR(&(_packet_data)->ui32WorkTarget, ui32VersionOffset)); \ - } \ - } while (0) - -/*! This macro gets the counter stream pointer depending on the packet version */ -#define RGX_HWPERF_GET_CNTSTRM(_sig, _hw_packet_data, _cntstream_ptr) \ -{ \ - if (HWPERF_PACKET_V2B_SIG == _sig || HWPERF_PACKET_V2C_SIG == _sig) \ - { \ - (_cntstream_ptr) = (IMG_UINT32 *)(IMG_OFFSET_ADDR((_hw_packet_data), RGX_HWPERF_GET_BLKOFFSET((_hw_packet_data)->ui32BlkInfo))); \ - } \ - else \ - { \ - IMG_UINT32 ui32BlkStreamOffsetInWords = ((_sig == HWPERF_PACKET_V2_SIG) ? 6 : 8); \ - (_cntstream_ptr) = (IMG_UINT32 *)(IMG_OFFSET_ADDR((_hw_packet_data), ui32BlkStreamOffsetInWords)); \ - } \ -} - -/*! Masks for use with the RGX_HWPERF_UFO_EV eEvType field */ -#define RGX_HWPERF_UFO_STREAMSIZE_MASK 0xFFFF0000U -#define RGX_HWPERF_UFO_STREAMOFFSET_MASK 0x0000FFFFU - -/*! Shift for the UFO count and data stream fields */ -#define RGX_HWPERF_UFO_STREAMSIZE_SHIFT 16U -#define RGX_HWPERF_UFO_STREAMOFFSET_SHIFT 0U - -/*! Macro used to set UFO stream info word as a combination of two 16-bit integers */ -#define RGX_HWPERF_MAKE_UFOPKTINFO(_ssize, _soff) \ - ((IMG_UINT32) ((RGX_HWPERF_UFO_STREAMSIZE_MASK&((_ssize) << RGX_HWPERF_UFO_STREAMSIZE_SHIFT)) | \ - (RGX_HWPERF_UFO_STREAMOFFSET_MASK&((_soff) << RGX_HWPERF_UFO_STREAMOFFSET_SHIFT)))) - -/*! Macro used to obtain UFO count*/ -#define RGX_HWPERF_GET_UFO_STREAMSIZE(_streaminfo) \ - (((_streaminfo) & RGX_HWPERF_UFO_STREAMSIZE_MASK) >> RGX_HWPERF_UFO_STREAMSIZE_SHIFT) - -/*! Obtains the offset of the UFO stream in the packet */ -#define RGX_HWPERF_GET_UFO_STREAMOFFSET(_streaminfo) \ - (((_streaminfo) & RGX_HWPERF_UFO_STREAMOFFSET_MASK) >> RGX_HWPERF_UFO_STREAMOFFSET_SHIFT) - - /****************************************************************************** * Data Stream Common Types @@ -496,17 +103,20 @@ typedef enum { /*! Enum containing bit position for 32bit feature flags used in hwperf and api */ typedef enum { - RGX_HWPERF_FEATURE_PERFBUS_FLAG = 0x001, - RGX_HWPERF_FEATURE_S7_TOP_INFRASTRUCTURE_FLAG = 0x002, - RGX_HWPERF_FEATURE_XT_TOP_INFRASTRUCTURE_FLAG = 0x004, - RGX_HWPERF_FEATURE_PERF_COUNTER_BATCH_FLAG = 0x008, - RGX_HWPERF_FEATURE_ROGUEXE_FLAG = 0x010, - RGX_HWPERF_FEATURE_DUST_POWER_ISLAND_S7_FLAG = 0x020, - RGX_HWPERF_FEATURE_PBE2_IN_XE_FLAG = 0x040, - RGX_HWPERF_FEATURE_WORKLOAD_ESTIMATION = 0x080, - RGX_HWPERF_FEATURE_MULTICORE_FLAG = 0x100, - RGX_HWPERF_FEATURE_RAYTRACING_FLAG = 0x200, - RGX_HWPERF_FEATURE_CXT_TOP_INFRASTRUCTURE_FLAG = 0x400 + RGX_HWPERF_FEATURE_PERFBUS_FLAG = 0x0001, + RGX_HWPERF_FEATURE_S7_TOP_INFRASTRUCTURE_FLAG = 0x0002, + RGX_HWPERF_FEATURE_XT_TOP_INFRASTRUCTURE_FLAG = 0x0004, + RGX_HWPERF_FEATURE_PERF_COUNTER_BATCH_FLAG = 0x0008, + RGX_HWPERF_FEATURE_ROGUEXE_FLAG = 0x0010, + RGX_HWPERF_FEATURE_DUST_POWER_ISLAND_S7_FLAG = 0x0020, + RGX_HWPERF_FEATURE_PBE2_IN_XE_FLAG = 0x0040, + RGX_HWPERF_FEATURE_WORKLOAD_ESTIMATION = 0x0080, + RGX_HWPERF_FEATURE_MULTICORE_FLAG = 0x0100, + RGX_HWPERF_FEATURE_RAYTRACING_FLAG = 0x0200, + RGX_HWPERF_FEATURE_CXT_TOP_INFRASTRUCTURE_FLAG = 0x0400, + RGX_HWPERF_FEATURE_VOLCANIC_FLAG = 0x0800, + RGX_HWPERF_FEATURE_ROGUE_FLAG = 0x1000, + RGX_HWPERF_FEATURE_OCEANIC_FLAG = 0x2000 } RGX_HWPERF_FEATURE_FLAGS; /*! This structure holds the data of a firmware packet. */ @@ -537,11 +147,14 @@ typedef struct IMG_UINT32 ui32WorkCtx; /*!< Work context: Render Context for TA/3D; RayTracing Context for RTU/SHG; 0x0 otherwise */ IMG_UINT32 ui32CtxPriority; /*!< Context priority */ IMG_UINT32 ui32GPUIdMask; /*!< GPU IDs active within this event */ - IMG_UINT32 aui32CountBlksStream[RGX_HWPERF_ZERO_OR_MORE_ELEMENTS]; /*!< Counter data */ - IMG_UINT32 ui32Padding2; /*!< Reserved. To ensure correct alignment */ + IMG_UINT32 ui32KickInfo; /*!< <31..8> Reserved <7..0> GPU Pipeline DM kick ID, 0 if not using Pipeline DMs */ + IMG_UINT32 ui32Padding; /*!< Reserved. To ensure correct alignment */ + IMG_UINT32 aui32CountBlksStream[RGX_HWPERF_ZERO_OR_MORE_ELEMENTS]; /*!< Optional variable length Counter data */ + IMG_UINT32 ui32Padding2; /*!< Reserved. To ensure correct alignment (not written in the packet) */ } RGX_HWPERF_HW_DATA; RGX_FW_STRUCT_SIZE_ASSERT(RGX_HWPERF_HW_DATA); +RGX_FW_STRUCT_OFFSET_ASSERT(RGX_HWPERF_HW_DATA, aui32CountBlksStream); /*! Mask for use with the aui32CountBlksStream field when decoding the * counter block ID and mask word. */ @@ -549,11 +162,7 @@ RGX_FW_STRUCT_SIZE_ASSERT(RGX_HWPERF_HW_DATA); #define RGX_HWPERF_CNTBLK_ID_SHIFT 16U /*! MAX value used in server handling of counter config arrays */ -#if defined(SUPPORT_VALIDATION) -#define RGX_CNTBLK_COUNTERS_MAX 64 -#else -#define RGX_CNTBLK_COUNTERS_MAX 12 -#endif +#define RGX_CNTBLK_COUNTERS_MAX PVRSRV_HWPERF_COUNTERS_PERBLK /*! Obtains the counter block ID word from an aui32CountBlksStream field. @@ -957,12 +566,14 @@ RGX_FW_STRUCT_SIZE_ASSERT(RGX_HWPERF_UFO_DATA); */ typedef enum { - RGX_HWPERF_KICK_TYPE_TA3D, /*!< TA 3D Kick */ + RGX_HWPERF_KICK_TYPE_TA3D, /*!< Replaced by separate TA and 3D types */ RGX_HWPERF_KICK_TYPE_CDM, /*!< Compute Data Master Kick */ RGX_HWPERF_KICK_TYPE_RS, /*!< Ray Store Kick */ RGX_HWPERF_KICK_TYPE_SHG, /*!< Scene Hierarchy Generator Kick */ RGX_HWPERF_KICK_TYPE_TQTDM, /*!< TQ 2D Data Master Kick */ RGX_HWPERF_KICK_TYPE_SYNC, /*!< Sync Kick */ + RGX_HWPERF_KICK_TYPE_TA, /*!< TA Kick */ + RGX_HWPERF_KICK_TYPE_3D, /*!< 3D Kick */ RGX_HWPERF_KICK_TYPE_LAST, RGX_HWPERF_KICK_TYPE_FORCE_32BIT = 0x7fffffff @@ -1395,6 +1006,49 @@ typedef struct static_assert((sizeof(RGX_HWPERF_HOST_SYNC_SW_TL_ADV_DATA) & (PVRSRVTL_PACKET_ALIGNMENT-1U)) == 0U, "sizeof(RGX_HWPERF_HOST_SYNC_SW_TL_ADV_DATA) must be a multiple PVRSRVTL_PACKET_ALIGNMENT"); +typedef enum +{ + RGX_HWPERF_HOST_CLIENT_INFO_TYPE_INVALID = 0, /*!< Invalid */ + RGX_HWPERF_HOST_CLIENT_INFO_TYPE_PROCESS_NAME, /*!< Process Name */ + + RGX_HWPERF_HOST_CLIENT_INFO_TYPE_LAST, /*!< Do not use */ +} RGX_HWPERF_HOST_CLIENT_INFO_TYPE; + +typedef struct +{ + IMG_PID uiClientPID; /*!< Client process identifier */ + IMG_UINT32 ui32Length; /*!< Number of bytes present in ``acName`` */ + IMG_CHAR acName[RGX_HWPERF_ONE_OR_MORE_ELEMENTS]; /*!< Process name string, null terminated */ +} RGX_HWPERF_HOST_CLIENT_PROC_NAME; + +#define RGX_HWPERF_HOST_CLIENT_PROC_NAME_SIZE(ui32NameLen) \ + ((IMG_UINT32)(offsetof(RGX_HWPERF_HOST_CLIENT_PROC_NAME, acName) + (ui32NameLen))) + +typedef union +{ + struct + { + IMG_UINT32 ui32Count; /*!< Number of elements in ``asProcNames`` */ + RGX_HWPERF_HOST_CLIENT_PROC_NAME asProcNames[RGX_HWPERF_ONE_OR_MORE_ELEMENTS]; + } sProcName; +} RGX_HWPERF_HOST_CLIENT_INFO_DETAIL; + +typedef struct +{ + IMG_UINT32 uiReserved1; /*!< Reserved. Align structure size to 8 bytes */ + RGX_HWPERF_HOST_CLIENT_INFO_TYPE eType; + /*!< Type of the subevent, see + RGX_HWPERF_HOST_CLIENT_INFO_TYPE */ + RGX_HWPERF_HOST_CLIENT_INFO_DETAIL uDetail; + /*!< Union of structures. Size of data + varies with union member that is present, + check ``eType`` value to decode */ + +} RGX_HWPERF_HOST_CLIENT_INFO_DATA; + +static_assert((sizeof(RGX_HWPERF_HOST_CLIENT_INFO_DATA) & (PVRSRVTL_PACKET_ALIGNMENT-1U)) == 0U, + "sizeof(RGX_HWPERF_HOST_CLIENT_INFO_DATA) must be a multiple PVRSRVTL_PACKET_ALIGNMENT"); + typedef enum { RGX_HWPERF_RESOURCE_CAPTURE_TYPE_NONE, @@ -1480,7 +1134,8 @@ typedef union RGX_HWPERF_FW_DATA sFW; /*!< Firmware event packet data, events ``0x01-0x06`` */ RGX_HWPERF_HW_DATA sHW; /*!< Hardware event packet data, - events ``0x07-0x19``, ``0x28-0x29`` */ + events ``0x07-0x19``, ``0x28-0x29`` + See RGX_HWPERF_HW_DATA */ RGX_HWPERF_CLKS_CHG_DATA sCLKSCHG; /*!< Clock change event packet data, events ``0x1A`` */ RGX_HWPERF_GPU_STATE_CHG_DATA sGPUSTATECHG; /*!< GPU utilisation state @@ -1520,6 +1175,8 @@ typedef union events ``0x09`` (Host) */ RGX_HWPERF_HOST_SYNC_SW_TL_ADV_DATA sSWTLADV; /*!< Host SW-timeline advance data, events ``0x0A`` (Host) */ + RGX_HWPERF_HOST_CLIENT_INFO_DATA sHClientInfo; /*!< Host client info, + events ``0x0B`` (Host) */ } RGX_HWPERF_V2_PACKET_DATA, *RGX_PHWPERF_V2_PACKET_DATA; RGX_FW_STRUCT_SIZE_ASSERT(RGX_HWPERF_V2_PACKET_DATA); diff --git a/drivers/gpu/drm/img-rogue/kernel_compatibility.h b/drivers/gpu/drm/img-rogue/kernel_compatibility.h index 50d17e665..6a94c8c12 100644 --- a/drivers/gpu/drm/img-rogue/kernel_compatibility.h +++ b/drivers/gpu/drm/img-rogue/kernel_compatibility.h @@ -507,4 +507,15 @@ struct dma_buf_map { #endif /* (LINUX_VERSION_CODE < KERNEL_VERSION(5, 13, 0)) */ +/* + * Linux 5.11 renames the privileged uaccess routines for arm64 and Android + * kernel v5.10 merges the change as well. These routines are only used for + * arm64 so CONFIG_ARM64 testing can be ignored. + */ +#if (LINUX_VERSION_CODE < KERNEL_VERSION(5, 10, 0)) || \ + ((LINUX_VERSION_CODE < KERNEL_VERSION(5, 11, 0)) && !defined(ANDROID)) +#define uaccess_enable_privileged() uaccess_enable() +#define uaccess_disable_privileged() uaccess_disable() +#endif + #endif /* __KERNEL_COMPATIBILITY_H__ */ diff --git a/drivers/gpu/drm/img-rogue/km/rgx_bvnc_defs_km.h b/drivers/gpu/drm/img-rogue/km/rgx_bvnc_defs_km.h index 6b05a14ca..0aa00beb1 100644 --- a/drivers/gpu/drm/img-rogue/km/rgx_bvnc_defs_km.h +++ b/drivers/gpu/drm/img-rogue/km/rgx_bvnc_defs_km.h @@ -177,53 +177,59 @@ CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. #define RGX_FEATURE_SLC_VIVT_POS (37U) #define RGX_FEATURE_SLC_VIVT_BIT_MASK (IMG_UINT64_C(0x0000002000000000)) -#define RGX_FEATURE_SYS_BUS_SECURE_RESET_POS (38U) -#define RGX_FEATURE_SYS_BUS_SECURE_RESET_BIT_MASK (IMG_UINT64_C(0x0000004000000000)) +#define RGX_FEATURE_SOC_TIMER_POS (38U) +#define RGX_FEATURE_SOC_TIMER_BIT_MASK (IMG_UINT64_C(0x0000004000000000)) -#define RGX_FEATURE_TDM_PDS_CHECKSUM_POS (39U) -#define RGX_FEATURE_TDM_PDS_CHECKSUM_BIT_MASK (IMG_UINT64_C(0x0000008000000000)) +#define RGX_FEATURE_SYS_BUS_SECURE_RESET_POS (39U) +#define RGX_FEATURE_SYS_BUS_SECURE_RESET_BIT_MASK (IMG_UINT64_C(0x0000008000000000)) -#define RGX_FEATURE_TESSELLATION_POS (40U) -#define RGX_FEATURE_TESSELLATION_BIT_MASK (IMG_UINT64_C(0x0000010000000000)) +#define RGX_FEATURE_TDM_PDS_CHECKSUM_POS (40U) +#define RGX_FEATURE_TDM_PDS_CHECKSUM_BIT_MASK (IMG_UINT64_C(0x0000010000000000)) -#define RGX_FEATURE_TFBC_DELTA_CORRELATION_POS (41U) -#define RGX_FEATURE_TFBC_DELTA_CORRELATION_BIT_MASK (IMG_UINT64_C(0x0000020000000000)) +#define RGX_FEATURE_TESSELLATION_POS (41U) +#define RGX_FEATURE_TESSELLATION_BIT_MASK (IMG_UINT64_C(0x0000020000000000)) -#define RGX_FEATURE_TFBC_LOSSY_37_PERCENT_POS (42U) -#define RGX_FEATURE_TFBC_LOSSY_37_PERCENT_BIT_MASK (IMG_UINT64_C(0x0000040000000000)) +#define RGX_FEATURE_TFBC_DELTA_CORRELATION_POS (42U) +#define RGX_FEATURE_TFBC_DELTA_CORRELATION_BIT_MASK (IMG_UINT64_C(0x0000040000000000)) -#define RGX_FEATURE_TFBC_NATIVE_YUV10_POS (43U) -#define RGX_FEATURE_TFBC_NATIVE_YUV10_BIT_MASK (IMG_UINT64_C(0x0000080000000000)) +#define RGX_FEATURE_TFBC_LOSSY_37_PERCENT_POS (43U) +#define RGX_FEATURE_TFBC_LOSSY_37_PERCENT_BIT_MASK (IMG_UINT64_C(0x0000080000000000)) -#define RGX_FEATURE_TILE_REGION_PROTECTION_POS (44U) -#define RGX_FEATURE_TILE_REGION_PROTECTION_BIT_MASK (IMG_UINT64_C(0x0000100000000000)) +#define RGX_FEATURE_TFBC_NATIVE_YUV10_POS (44U) +#define RGX_FEATURE_TFBC_NATIVE_YUV10_BIT_MASK (IMG_UINT64_C(0x0000100000000000)) -#define RGX_FEATURE_TLA_POS (45U) -#define RGX_FEATURE_TLA_BIT_MASK (IMG_UINT64_C(0x0000200000000000)) +#define RGX_FEATURE_TILE_REGION_PROTECTION_POS (45U) +#define RGX_FEATURE_TILE_REGION_PROTECTION_BIT_MASK (IMG_UINT64_C(0x0000200000000000)) -#define RGX_FEATURE_TPU_CEM_DATAMASTER_GLOBAL_REGISTERS_POS (46U) -#define RGX_FEATURE_TPU_CEM_DATAMASTER_GLOBAL_REGISTERS_BIT_MASK (IMG_UINT64_C(0x0000400000000000)) +#define RGX_FEATURE_TLA_POS (46U) +#define RGX_FEATURE_TLA_BIT_MASK (IMG_UINT64_C(0x0000400000000000)) -#define RGX_FEATURE_TPU_DM_GLOBAL_REGISTERS_POS (47U) -#define RGX_FEATURE_TPU_DM_GLOBAL_REGISTERS_BIT_MASK (IMG_UINT64_C(0x0000800000000000)) +#define RGX_FEATURE_TPU_CEM_DATAMASTER_GLOBAL_REGISTERS_POS (47U) +#define RGX_FEATURE_TPU_CEM_DATAMASTER_GLOBAL_REGISTERS_BIT_MASK (IMG_UINT64_C(0x0000800000000000)) -#define RGX_FEATURE_TPU_FILTERING_MODE_CONTROL_POS (48U) -#define RGX_FEATURE_TPU_FILTERING_MODE_CONTROL_BIT_MASK (IMG_UINT64_C(0x0001000000000000)) +#define RGX_FEATURE_TPU_DM_GLOBAL_REGISTERS_POS (48U) +#define RGX_FEATURE_TPU_DM_GLOBAL_REGISTERS_BIT_MASK (IMG_UINT64_C(0x0001000000000000)) -#define RGX_FEATURE_VDM_DRAWINDIRECT_POS (49U) -#define RGX_FEATURE_VDM_DRAWINDIRECT_BIT_MASK (IMG_UINT64_C(0x0002000000000000)) +#define RGX_FEATURE_TPU_FILTERING_MODE_CONTROL_POS (49U) +#define RGX_FEATURE_TPU_FILTERING_MODE_CONTROL_BIT_MASK (IMG_UINT64_C(0x0002000000000000)) -#define RGX_FEATURE_VDM_OBJECT_LEVEL_LLS_POS (50U) -#define RGX_FEATURE_VDM_OBJECT_LEVEL_LLS_BIT_MASK (IMG_UINT64_C(0x0004000000000000)) +#define RGX_FEATURE_VDM_DRAWINDIRECT_POS (50U) +#define RGX_FEATURE_VDM_DRAWINDIRECT_BIT_MASK (IMG_UINT64_C(0x0004000000000000)) -#define RGX_FEATURE_WATCHDOG_TIMER_POS (51U) -#define RGX_FEATURE_WATCHDOG_TIMER_BIT_MASK (IMG_UINT64_C(0x0008000000000000)) +#define RGX_FEATURE_VDM_OBJECT_LEVEL_LLS_POS (51U) +#define RGX_FEATURE_VDM_OBJECT_LEVEL_LLS_BIT_MASK (IMG_UINT64_C(0x0008000000000000)) -#define RGX_FEATURE_XE_MEMORY_HIERARCHY_POS (52U) -#define RGX_FEATURE_XE_MEMORY_HIERARCHY_BIT_MASK (IMG_UINT64_C(0x0010000000000000)) +#define RGX_FEATURE_WATCHDOG_TIMER_POS (52U) +#define RGX_FEATURE_WATCHDOG_TIMER_BIT_MASK (IMG_UINT64_C(0x0010000000000000)) -#define RGX_FEATURE_XT_TOP_INFRASTRUCTURE_POS (53U) -#define RGX_FEATURE_XT_TOP_INFRASTRUCTURE_BIT_MASK (IMG_UINT64_C(0x0020000000000000)) +#define RGX_FEATURE_WORKGROUP_PROTECTION_POS (53U) +#define RGX_FEATURE_WORKGROUP_PROTECTION_BIT_MASK (IMG_UINT64_C(0x0020000000000000)) + +#define RGX_FEATURE_XE_MEMORY_HIERARCHY_POS (54U) +#define RGX_FEATURE_XE_MEMORY_HIERARCHY_BIT_MASK (IMG_UINT64_C(0x0040000000000000)) + +#define RGX_FEATURE_XT_TOP_INFRASTRUCTURE_POS (55U) +#define RGX_FEATURE_XT_TOP_INFRASTRUCTURE_BIT_MASK (IMG_UINT64_C(0x0080000000000000)) /****************************************************************************** @@ -236,6 +242,8 @@ CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. #define RGX_FEATURE_FBCDC_MAX_VALUE_IDX (4) #define RGX_FEATURE_FBCDC_ALGORITHM_MAX_VALUE_IDX (6) #define RGX_FEATURE_FBCDC_ARCHITECTURE_MAX_VALUE_IDX (4) +#define RGX_FEATURE_FBC_MAX_DEFAULT_DESCRIPTORS_MAX_VALUE_IDX (2) +#define RGX_FEATURE_FBC_MAX_LARGE_DESCRIPTORS_MAX_VALUE_IDX (2) #define RGX_FEATURE_LAYOUT_MARS_MAX_VALUE_IDX (3) #define RGX_FEATURE_META_MAX_VALUE_IDX (4) #define RGX_FEATURE_META_COREMEM_BANKS_MAX_VALUE_IDX (1) @@ -255,6 +263,7 @@ CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. #define RGX_FEATURE_TILE_SIZE_X_MAX_VALUE_IDX (3) #define RGX_FEATURE_TILE_SIZE_Y_MAX_VALUE_IDX (3) #define RGX_FEATURE_VIRTUAL_ADDRESS_SPACE_BITS_MAX_VALUE_IDX (2) +#define RGX_FEATURE_XE_ARCHITECTURE_MAX_VALUE_IDX (2) #define RGX_FEATURE_XPU_MAX_REGBANKS_ADDR_WIDTH_MAX_VALUE_IDX (2) #define RGX_FEATURE_XPU_MAX_SLAVES_MAX_VALUE_IDX (2) #define RGX_FEATURE_XPU_REGISTER_BROADCAST_MAX_VALUE_IDX (2) @@ -269,6 +278,8 @@ typedef enum _RGX_FEATURE_WITH_VALUE_INDEX_ { RGX_FEATURE_FBCDC_IDX, RGX_FEATURE_FBCDC_ALGORITHM_IDX, RGX_FEATURE_FBCDC_ARCHITECTURE_IDX, + RGX_FEATURE_FBC_MAX_DEFAULT_DESCRIPTORS_IDX, + RGX_FEATURE_FBC_MAX_LARGE_DESCRIPTORS_IDX, RGX_FEATURE_LAYOUT_MARS_IDX, RGX_FEATURE_META_IDX, RGX_FEATURE_META_COREMEM_BANKS_IDX, @@ -288,6 +299,7 @@ typedef enum _RGX_FEATURE_WITH_VALUE_INDEX_ { RGX_FEATURE_TILE_SIZE_X_IDX, RGX_FEATURE_TILE_SIZE_Y_IDX, RGX_FEATURE_VIRTUAL_ADDRESS_SPACE_BITS_IDX, + RGX_FEATURE_XE_ARCHITECTURE_IDX, RGX_FEATURE_XPU_MAX_REGBANKS_ADDR_WIDTH_IDX, RGX_FEATURE_XPU_MAX_SLAVES_IDX, RGX_FEATURE_XPU_REGISTER_BROADCAST_IDX, diff --git a/drivers/gpu/drm/img-rogue/km/rgx_bvnc_table_km.h b/drivers/gpu/drm/img-rogue/km/rgx_bvnc_table_km.h index c63818edf..4044507ca 100644 --- a/drivers/gpu/drm/img-rogue/km/rgx_bvnc_table_km.h +++ b/drivers/gpu/drm/img-rogue/km/rgx_bvnc_table_km.h @@ -76,6 +76,10 @@ static const IMG_UINT16 aui16_RGX_FEATURE_FBCDC_ALGORITHM_values[RGX_FEATURE_FBC static const IMG_UINT16 aui16_RGX_FEATURE_FBCDC_ARCHITECTURE_values[RGX_FEATURE_FBCDC_ARCHITECTURE_MAX_VALUE_IDX] = {(IMG_UINT16)RGX_FEATURE_VALUE_DISABLED, 1, 2, 7, }; +static const IMG_UINT16 aui16_RGX_FEATURE_FBC_MAX_DEFAULT_DESCRIPTORS_values[RGX_FEATURE_FBC_MAX_DEFAULT_DESCRIPTORS_MAX_VALUE_IDX] = {(IMG_UINT16)RGX_FEATURE_VALUE_DISABLED, 0, }; + +static const IMG_UINT16 aui16_RGX_FEATURE_FBC_MAX_LARGE_DESCRIPTORS_values[RGX_FEATURE_FBC_MAX_LARGE_DESCRIPTORS_MAX_VALUE_IDX] = {(IMG_UINT16)RGX_FEATURE_VALUE_DISABLED, 0, }; + static const IMG_UINT16 aui16_RGX_FEATURE_LAYOUT_MARS_values[RGX_FEATURE_LAYOUT_MARS_MAX_VALUE_IDX] = {(IMG_UINT16)RGX_FEATURE_VALUE_DISABLED, 0, 1, }; static const IMG_UINT16 aui16_RGX_FEATURE_META_values[RGX_FEATURE_META_MAX_VALUE_IDX] = {(IMG_UINT16)RGX_FEATURE_VALUE_DISABLED, LTP217, LTP218, MTP218, }; @@ -114,6 +118,8 @@ static const IMG_UINT16 aui16_RGX_FEATURE_TILE_SIZE_Y_values[RGX_FEATURE_TILE_SI static const IMG_UINT16 aui16_RGX_FEATURE_VIRTUAL_ADDRESS_SPACE_BITS_values[RGX_FEATURE_VIRTUAL_ADDRESS_SPACE_BITS_MAX_VALUE_IDX] = {(IMG_UINT16)RGX_FEATURE_VALUE_DISABLED, 40, }; +static const IMG_UINT16 aui16_RGX_FEATURE_XE_ARCHITECTURE_values[RGX_FEATURE_XE_ARCHITECTURE_MAX_VALUE_IDX] = {(IMG_UINT16)RGX_FEATURE_VALUE_DISABLED, 1, }; + static const IMG_UINT16 aui16_RGX_FEATURE_XPU_MAX_REGBANKS_ADDR_WIDTH_values[RGX_FEATURE_XPU_MAX_REGBANKS_ADDR_WIDTH_MAX_VALUE_IDX] = {(IMG_UINT16)RGX_FEATURE_VALUE_DISABLED, 19, }; static const IMG_UINT16 aui16_RGX_FEATURE_XPU_MAX_SLAVES_values[RGX_FEATURE_XPU_MAX_SLAVES_MAX_VALUE_IDX] = {(IMG_UINT16)RGX_FEATURE_VALUE_DISABLED, 3, }; @@ -133,6 +139,8 @@ static const IMG_UINT16 * const gaFeaturesValues[RGX_FEATURE_WITH_VALUES_MAX_IDX aui16_RGX_FEATURE_FBCDC_values, aui16_RGX_FEATURE_FBCDC_ALGORITHM_values, aui16_RGX_FEATURE_FBCDC_ARCHITECTURE_values, + aui16_RGX_FEATURE_FBC_MAX_DEFAULT_DESCRIPTORS_values, + aui16_RGX_FEATURE_FBC_MAX_LARGE_DESCRIPTORS_values, aui16_RGX_FEATURE_LAYOUT_MARS_values, aui16_RGX_FEATURE_META_values, aui16_RGX_FEATURE_META_COREMEM_BANKS_values, @@ -152,6 +160,7 @@ static const IMG_UINT16 * const gaFeaturesValues[RGX_FEATURE_WITH_VALUES_MAX_IDX aui16_RGX_FEATURE_TILE_SIZE_X_values, aui16_RGX_FEATURE_TILE_SIZE_Y_values, aui16_RGX_FEATURE_VIRTUAL_ADDRESS_SPACE_BITS_values, + aui16_RGX_FEATURE_XE_ARCHITECTURE_values, aui16_RGX_FEATURE_XPU_MAX_REGBANKS_ADDR_WIDTH_values, aui16_RGX_FEATURE_XPU_MAX_SLAVES_values, aui16_RGX_FEATURE_XPU_REGISTER_BROADCAST_values, @@ -170,6 +179,8 @@ static const IMG_UINT16 gaFeaturesValuesMaxIndexes[] = { RGX_FEATURE_FBCDC_MAX_VALUE_IDX, RGX_FEATURE_FBCDC_ALGORITHM_MAX_VALUE_IDX, RGX_FEATURE_FBCDC_ARCHITECTURE_MAX_VALUE_IDX, + RGX_FEATURE_FBC_MAX_DEFAULT_DESCRIPTORS_MAX_VALUE_IDX, + RGX_FEATURE_FBC_MAX_LARGE_DESCRIPTORS_MAX_VALUE_IDX, RGX_FEATURE_LAYOUT_MARS_MAX_VALUE_IDX, RGX_FEATURE_META_MAX_VALUE_IDX, RGX_FEATURE_META_COREMEM_BANKS_MAX_VALUE_IDX, @@ -189,6 +200,7 @@ static const IMG_UINT16 gaFeaturesValuesMaxIndexes[] = { RGX_FEATURE_TILE_SIZE_X_MAX_VALUE_IDX, RGX_FEATURE_TILE_SIZE_Y_MAX_VALUE_IDX, RGX_FEATURE_VIRTUAL_ADDRESS_SPACE_BITS_MAX_VALUE_IDX, + RGX_FEATURE_XE_ARCHITECTURE_MAX_VALUE_IDX, RGX_FEATURE_XPU_MAX_REGBANKS_ADDR_WIDTH_MAX_VALUE_IDX, RGX_FEATURE_XPU_MAX_SLAVES_MAX_VALUE_IDX, RGX_FEATURE_XPU_REGISTER_BROADCAST_MAX_VALUE_IDX, @@ -205,28 +217,31 @@ static const IMG_UINT16 aui16FeaturesWithValuesBitPositions[] = { (4U), /* RGX_FEATURE_FBCDC_POS */ (7U), /* RGX_FEATURE_FBCDC_ALGORITHM_POS */ (10U), /* RGX_FEATURE_FBCDC_ARCHITECTURE_POS */ - (13U), /* RGX_FEATURE_LAYOUT_MARS_POS */ - (15U), /* RGX_FEATURE_META_POS */ - (18U), /* RGX_FEATURE_META_COREMEM_BANKS_POS */ - (19U), /* RGX_FEATURE_META_COREMEM_SIZE_POS */ - (21U), /* RGX_FEATURE_META_DMA_CHANNEL_COUNT_POS */ - (22U), /* RGX_FEATURE_NUM_CLUSTERS_POS */ - (25U), /* RGX_FEATURE_NUM_ISP_IPP_PIPES_POS */ - (29U), /* RGX_FEATURE_NUM_OSIDS_POS */ - (31U), /* RGX_FEATURE_NUM_RASTER_PIPES_POS */ - (33U), /* RGX_FEATURE_PHYS_BUS_WIDTH_POS */ - (36U), /* RGX_FEATURE_SCALABLE_TE_ARCH_POS */ - (37U), /* RGX_FEATURE_SCALABLE_VCE_POS */ - (38U), /* RGX_FEATURE_SIMPLE_PARAMETER_FORMAT_VERSION_POS */ - (40U), /* RGX_FEATURE_SLC_BANKS_POS */ - (43U), /* RGX_FEATURE_SLC_CACHE_LINE_SIZE_BITS_POS */ - (45U), /* RGX_FEATURE_SLC_SIZE_IN_KILOBYTES_POS */ - (48U), /* RGX_FEATURE_TILE_SIZE_X_POS */ - (50U), /* RGX_FEATURE_TILE_SIZE_Y_POS */ - (52U), /* RGX_FEATURE_VIRTUAL_ADDRESS_SPACE_BITS_POS */ - (54U), /* RGX_FEATURE_XPU_MAX_REGBANKS_ADDR_WIDTH_POS */ - (56U), /* RGX_FEATURE_XPU_MAX_SLAVES_POS */ - (58U), /* RGX_FEATURE_XPU_REGISTER_BROADCAST_POS */ + (13U), /* RGX_FEATURE_FBC_MAX_DEFAULT_DESCRIPTORS_POS */ + (15U), /* RGX_FEATURE_FBC_MAX_LARGE_DESCRIPTORS_POS */ + (17U), /* RGX_FEATURE_LAYOUT_MARS_POS */ + (19U), /* RGX_FEATURE_META_POS */ + (22U), /* RGX_FEATURE_META_COREMEM_BANKS_POS */ + (23U), /* RGX_FEATURE_META_COREMEM_SIZE_POS */ + (25U), /* RGX_FEATURE_META_DMA_CHANNEL_COUNT_POS */ + (26U), /* RGX_FEATURE_NUM_CLUSTERS_POS */ + (29U), /* RGX_FEATURE_NUM_ISP_IPP_PIPES_POS */ + (33U), /* RGX_FEATURE_NUM_OSIDS_POS */ + (35U), /* RGX_FEATURE_NUM_RASTER_PIPES_POS */ + (37U), /* RGX_FEATURE_PHYS_BUS_WIDTH_POS */ + (40U), /* RGX_FEATURE_SCALABLE_TE_ARCH_POS */ + (41U), /* RGX_FEATURE_SCALABLE_VCE_POS */ + (42U), /* RGX_FEATURE_SIMPLE_PARAMETER_FORMAT_VERSION_POS */ + (44U), /* RGX_FEATURE_SLC_BANKS_POS */ + (47U), /* RGX_FEATURE_SLC_CACHE_LINE_SIZE_BITS_POS */ + (49U), /* RGX_FEATURE_SLC_SIZE_IN_KILOBYTES_POS */ + (52U), /* RGX_FEATURE_TILE_SIZE_X_POS */ + (54U), /* RGX_FEATURE_TILE_SIZE_Y_POS */ + (56U), /* RGX_FEATURE_VIRTUAL_ADDRESS_SPACE_BITS_POS */ + (58U), /* RGX_FEATURE_XE_ARCHITECTURE_POS */ + (60U), /* RGX_FEATURE_XPU_MAX_REGBANKS_ADDR_WIDTH_POS */ + (62U), /* RGX_FEATURE_XPU_MAX_SLAVES_POS */ + (64U), /* RGX_FEATURE_XPU_REGISTER_BROADCAST_POS */ }; @@ -240,28 +255,31 @@ static const IMG_UINT64 aui64FeaturesWithValuesBitMasks[] = { (IMG_UINT64_C(0x0000000000000070)), /* RGX_FEATURE_FBCDC_BIT_MASK */ (IMG_UINT64_C(0x0000000000000380)), /* RGX_FEATURE_FBCDC_ALGORITHM_BIT_MASK */ (IMG_UINT64_C(0x0000000000001C00)), /* RGX_FEATURE_FBCDC_ARCHITECTURE_BIT_MASK */ - (IMG_UINT64_C(0x0000000000006000)), /* RGX_FEATURE_LAYOUT_MARS_BIT_MASK */ - (IMG_UINT64_C(0x0000000000038000)), /* RGX_FEATURE_META_BIT_MASK */ - (IMG_UINT64_C(0x0000000000040000)), /* RGX_FEATURE_META_COREMEM_BANKS_BIT_MASK */ - (IMG_UINT64_C(0x0000000000180000)), /* RGX_FEATURE_META_COREMEM_SIZE_BIT_MASK */ - (IMG_UINT64_C(0x0000000000200000)), /* RGX_FEATURE_META_DMA_CHANNEL_COUNT_BIT_MASK */ - (IMG_UINT64_C(0x0000000001C00000)), /* RGX_FEATURE_NUM_CLUSTERS_BIT_MASK */ - (IMG_UINT64_C(0x000000001E000000)), /* RGX_FEATURE_NUM_ISP_IPP_PIPES_BIT_MASK */ - (IMG_UINT64_C(0x0000000060000000)), /* RGX_FEATURE_NUM_OSIDS_BIT_MASK */ - (IMG_UINT64_C(0x0000000180000000)), /* RGX_FEATURE_NUM_RASTER_PIPES_BIT_MASK */ - (IMG_UINT64_C(0x0000000E00000000)), /* RGX_FEATURE_PHYS_BUS_WIDTH_BIT_MASK */ - (IMG_UINT64_C(0x0000001000000000)), /* RGX_FEATURE_SCALABLE_TE_ARCH_BIT_MASK */ - (IMG_UINT64_C(0x0000002000000000)), /* RGX_FEATURE_SCALABLE_VCE_BIT_MASK */ - (IMG_UINT64_C(0x000000C000000000)), /* RGX_FEATURE_SIMPLE_PARAMETER_FORMAT_VERSION_BIT_MASK */ - (IMG_UINT64_C(0x0000070000000000)), /* RGX_FEATURE_SLC_BANKS_BIT_MASK */ - (IMG_UINT64_C(0x0000180000000000)), /* RGX_FEATURE_SLC_CACHE_LINE_SIZE_BITS_BIT_MASK */ - (IMG_UINT64_C(0x0000E00000000000)), /* RGX_FEATURE_SLC_SIZE_IN_KILOBYTES_BIT_MASK */ - (IMG_UINT64_C(0x0003000000000000)), /* RGX_FEATURE_TILE_SIZE_X_BIT_MASK */ - (IMG_UINT64_C(0x000C000000000000)), /* RGX_FEATURE_TILE_SIZE_Y_BIT_MASK */ - (IMG_UINT64_C(0x0030000000000000)), /* RGX_FEATURE_VIRTUAL_ADDRESS_SPACE_BITS_BIT_MASK */ - (IMG_UINT64_C(0x00C0000000000000)), /* RGX_FEATURE_XPU_MAX_REGBANKS_ADDR_WIDTH_BIT_MASK */ - (IMG_UINT64_C(0x0300000000000000)), /* RGX_FEATURE_XPU_MAX_SLAVES_BIT_MASK */ - (IMG_UINT64_C(0x0C00000000000000)), /* RGX_FEATURE_XPU_REGISTER_BROADCAST_BIT_MASK */ + (IMG_UINT64_C(0x0000000000006000)), /* RGX_FEATURE_FBC_MAX_DEFAULT_DESCRIPTORS_BIT_MASK */ + (IMG_UINT64_C(0x0000000000018000)), /* RGX_FEATURE_FBC_MAX_LARGE_DESCRIPTORS_BIT_MASK */ + (IMG_UINT64_C(0x0000000000060000)), /* RGX_FEATURE_LAYOUT_MARS_BIT_MASK */ + (IMG_UINT64_C(0x0000000000380000)), /* RGX_FEATURE_META_BIT_MASK */ + (IMG_UINT64_C(0x0000000000400000)), /* RGX_FEATURE_META_COREMEM_BANKS_BIT_MASK */ + (IMG_UINT64_C(0x0000000001800000)), /* RGX_FEATURE_META_COREMEM_SIZE_BIT_MASK */ + (IMG_UINT64_C(0x0000000002000000)), /* RGX_FEATURE_META_DMA_CHANNEL_COUNT_BIT_MASK */ + (IMG_UINT64_C(0x000000001C000000)), /* RGX_FEATURE_NUM_CLUSTERS_BIT_MASK */ + (IMG_UINT64_C(0x00000001E0000000)), /* RGX_FEATURE_NUM_ISP_IPP_PIPES_BIT_MASK */ + (IMG_UINT64_C(0x0000000600000000)), /* RGX_FEATURE_NUM_OSIDS_BIT_MASK */ + (IMG_UINT64_C(0x0000001800000000)), /* RGX_FEATURE_NUM_RASTER_PIPES_BIT_MASK */ + (IMG_UINT64_C(0x000000E000000000)), /* RGX_FEATURE_PHYS_BUS_WIDTH_BIT_MASK */ + (IMG_UINT64_C(0x0000010000000000)), /* RGX_FEATURE_SCALABLE_TE_ARCH_BIT_MASK */ + (IMG_UINT64_C(0x0000020000000000)), /* RGX_FEATURE_SCALABLE_VCE_BIT_MASK */ + (IMG_UINT64_C(0x00000C0000000000)), /* RGX_FEATURE_SIMPLE_PARAMETER_FORMAT_VERSION_BIT_MASK */ + (IMG_UINT64_C(0x0000700000000000)), /* RGX_FEATURE_SLC_BANKS_BIT_MASK */ + (IMG_UINT64_C(0x0001800000000000)), /* RGX_FEATURE_SLC_CACHE_LINE_SIZE_BITS_BIT_MASK */ + (IMG_UINT64_C(0x000E000000000000)), /* RGX_FEATURE_SLC_SIZE_IN_KILOBYTES_BIT_MASK */ + (IMG_UINT64_C(0x0030000000000000)), /* RGX_FEATURE_TILE_SIZE_X_BIT_MASK */ + (IMG_UINT64_C(0x00C0000000000000)), /* RGX_FEATURE_TILE_SIZE_Y_BIT_MASK */ + (IMG_UINT64_C(0x0300000000000000)), /* RGX_FEATURE_VIRTUAL_ADDRESS_SPACE_BITS_BIT_MASK */ + (IMG_UINT64_C(0x0C00000000000000)), /* RGX_FEATURE_XE_ARCHITECTURE_BIT_MASK */ + (IMG_UINT64_C(0x3000000000000000)), /* RGX_FEATURE_XPU_MAX_REGBANKS_ADDR_WIDTH_BIT_MASK */ + (IMG_UINT64_C(0xC000000000000000)), /* RGX_FEATURE_XPU_MAX_SLAVES_BIT_MASK */ + (IMG_UINT64_C(0x0000000000000003)), /* RGX_FEATURE_XPU_REGISTER_BROADCAST_BIT_MASK */ }; @@ -270,41 +288,40 @@ static const IMG_UINT64 aui64FeaturesWithValuesBitMasks[] = { *****************************************************************************/ -static const IMG_UINT64 gaFeatures[][3]= +static const IMG_UINT64 gaFeatures[][4]= { - { IMG_UINT64_C(0x000100000002001e), IMG_UINT64_C(0x0000200000402025), IMG_UINT64_C(0x001aa8068689a481) }, /* 1.0.2.30 */ - { IMG_UINT64_C(0x0001000000040005), IMG_UINT64_C(0x0000200000402024), IMG_UINT64_C(0x001aa80686c9a481) }, /* 1.0.4.5 */ - { IMG_UINT64_C(0x0001000000040013), IMG_UINT64_C(0x0000200000402025), IMG_UINT64_C(0x001aa80686c9a481) }, /* 1.0.4.19 */ - { IMG_UINT64_C(0x0004000000020033), IMG_UINT64_C(0x0021600000c0222f), IMG_UINT64_C(0x001aa8068e912901) }, /* 4.0.2.51 */ - { IMG_UINT64_C(0x000400000002003a), IMG_UINT64_C(0x0021600000c0322f), IMG_UINT64_C(0x001aa806ce912901) }, /* 4.0.2.58 */ - { IMG_UINT64_C(0x0004000000040037), IMG_UINT64_C(0x0021600000c0222e), IMG_UINT64_C(0x001aa8068ed12901) }, /* 4.0.4.55 */ - { IMG_UINT64_C(0x000400000006003e), IMG_UINT64_C(0x0021600000c0322f), IMG_UINT64_C(0x001aab074f112901) }, /* 4.0.6.62 */ - { IMG_UINT64_C(0x000500000001002e), IMG_UINT64_C(0x0000000004402205), IMG_UINT64_C(0x001a69068248a501) }, /* 5.0.1.46 */ - { IMG_UINT64_C(0x0006000000040023), IMG_UINT64_C(0x0021600000c0222f), IMG_UINT64_C(0x001aa8068ed12901) }, /* 6.0.4.35 */ - { IMG_UINT64_C(0x000f000000010040), IMG_UINT64_C(0x0000000004403205), IMG_UINT64_C(0x001a8906c448a501) }, /* 15.0.1.64 */ - { IMG_UINT64_C(0x0016000000150010), IMG_UINT64_C(0x00000045844b3025), IMG_UINT64_C(0x00154942c4402001) }, /* 22.0.21.16 */ - { IMG_UINT64_C(0x0016000000360019), IMG_UINT64_C(0x00000045844b3025), IMG_UINT64_C(0x00158942c6402001) }, /* 22.0.54.25 */ - { IMG_UINT64_C(0x001600000036001e), IMG_UINT64_C(0x00000045844b3025), IMG_UINT64_C(0x00158942c8402001) }, /* 22.0.54.30 */ - { IMG_UINT64_C(0x0016000000360026), IMG_UINT64_C(0x00000045844b3025), IMG_UINT64_C(0x00158944c8402001) }, /* 22.0.54.38 */ - { IMG_UINT64_C(0x001600000036014a), IMG_UINT64_C(0x00000045844b3025), IMG_UINT64_C(0x00158942c8402591) }, /* 22.0.54.330 */ - { IMG_UINT64_C(0x0016000000680012), IMG_UINT64_C(0x00000045844b3025), IMG_UINT64_C(0x00158944cc402001) }, /* 22.0.104.18 */ - { IMG_UINT64_C(0x00160000006800da), IMG_UINT64_C(0x00000045844b3025), IMG_UINT64_C(0x00158944cc402591) }, /* 22.0.104.218 */ - { IMG_UINT64_C(0x0016000000d0013e), IMG_UINT64_C(0x00000045844b3025), IMG_UINT64_C(0x00158a4550802591) }, /* 22.0.208.318 */ - { IMG_UINT64_C(0x00180000003600cc), IMG_UINT64_C(0x001000c2844f7425), IMG_UINT64_C(0x00158984c8402591) }, /* 24.0.54.204 */ - { IMG_UINT64_C(0x00180000006801f8), IMG_UINT64_C(0x001000c2844f7425), IMG_UINT64_C(0x00158984ca402591) }, /* 24.0.104.504 */ - { IMG_UINT64_C(0x0018000000d001f8), IMG_UINT64_C(0x001000c2844f7425), IMG_UINT64_C(0x0015aa8550802591) }, /* 24.0.208.504 */ - { IMG_UINT64_C(0x0018000000d001f9), IMG_UINT64_C(0x001000c2844f7425), IMG_UINT64_C(0x0015aa8550802591) }, /* 24.0.208.505 */ - { IMG_UINT64_C(0x001d0000003400ca), IMG_UINT64_C(0x0010c0c2844f74a5), IMG_UINT64_C(0x00156984c4402621) }, /* 29.0.52.202 */ - { IMG_UINT64_C(0x001d0000006c00d0), IMG_UINT64_C(0x0010c0c2844f74a5), IMG_UINT64_C(0x0015aa854e802621) }, /* 29.0.108.208 */ - { IMG_UINT64_C(0x00210000000b0003), IMG_UINT64_C(0x00100052844b5085), IMG_UINT64_C(0x00152984a2402001) }, /* 33.0.11.3 */ - { IMG_UINT64_C(0x0021000000160001), IMG_UINT64_C(0x0010c042854b70a5), IMG_UINT64_C(0x00156984c4402001) }, /* 33.0.22.1 */ - { IMG_UINT64_C(0x0024000000360067), IMG_UINT64_C(0x0010c052844b38a5), IMG_UINT64_C(0x00156984c8402eb1) }, /* 36.0.54.103 */ - { IMG_UINT64_C(0x00240000003600b6), IMG_UINT64_C(0x0010c052844b78a5), IMG_UINT64_C(0x05556984c8404eb1) }, /* 36.0.54.182 */ - { IMG_UINT64_C(0x00240000003600b7), IMG_UINT64_C(0x0010c052844b78a5), IMG_UINT64_C(0x05556984c8404eb1) }, /* 36.0.54.183 */ - { IMG_UINT64_C(0x0024000000360118), IMG_UINT64_C(0x0010ce52844b78a5), IMG_UINT64_C(0x05556984c8404eb1) }, /* 36.0.54.280 */ - { IMG_UINT64_C(0x00240000006800b6), IMG_UINT64_C(0x0010c052844b78a5), IMG_UINT64_C(0x05556984ca404eb1) }, /* 36.0.104.182 */ - { IMG_UINT64_C(0x00240000006800b7), IMG_UINT64_C(0x0010c052844b78a5), IMG_UINT64_C(0x05556984ca404eb1) }, /* 36.0.104.183 */ - { IMG_UINT64_C(0x002400000068031c), IMG_UINT64_C(0x0018d052864a78a5), IMG_UINT64_C(0x05556984ca404eb5) }, /* 36.0.104.796 */ + { IMG_UINT64_C(0x000100000002001e), IMG_UINT64_C(0x0000400000402025), IMG_UINT64_C(0x01aa8068689aa481), IMG_UINT64_C(0x0000000000000000) }, /* 1.0.2.30 */ + { IMG_UINT64_C(0x0001000000040005), IMG_UINT64_C(0x0000400000402024), IMG_UINT64_C(0x01aa80686c9aa481), IMG_UINT64_C(0x0000000000000000) }, /* 1.0.4.5 */ + { IMG_UINT64_C(0x0001000000040013), IMG_UINT64_C(0x0000400000402025), IMG_UINT64_C(0x01aa80686c9aa481), IMG_UINT64_C(0x0000000000000000) }, /* 1.0.4.19 */ + { IMG_UINT64_C(0x0004000000020033), IMG_UINT64_C(0x0082c04000c0222f), IMG_UINT64_C(0x01aa8068e912a901), IMG_UINT64_C(0x0000000000000000) }, /* 4.0.2.51 */ + { IMG_UINT64_C(0x000400000002003a), IMG_UINT64_C(0x0082c04000c0322f), IMG_UINT64_C(0x01aa806ce912a901), IMG_UINT64_C(0x0000000000000000) }, /* 4.0.2.58 */ + { IMG_UINT64_C(0x0004000000040037), IMG_UINT64_C(0x0082c04000c0222e), IMG_UINT64_C(0x01aa8068ed12a901), IMG_UINT64_C(0x0000000000000000) }, /* 4.0.4.55 */ + { IMG_UINT64_C(0x000400000006003e), IMG_UINT64_C(0x0082c04000c0322f), IMG_UINT64_C(0x01aab074f112a901), IMG_UINT64_C(0x0000000000000000) }, /* 4.0.6.62 */ + { IMG_UINT64_C(0x000500000001002e), IMG_UINT64_C(0x0000004004402205), IMG_UINT64_C(0x05a69068248aa501), IMG_UINT64_C(0x0000000000000000) }, /* 5.0.1.46 */ + { IMG_UINT64_C(0x0006000000040023), IMG_UINT64_C(0x0082c04000c0222f), IMG_UINT64_C(0x01aa8068ed12a901), IMG_UINT64_C(0x0000000000000000) }, /* 6.0.4.35 */ + { IMG_UINT64_C(0x000f000000010040), IMG_UINT64_C(0x0000004004403205), IMG_UINT64_C(0x05a8906c448aa501), IMG_UINT64_C(0x0000000000000000) }, /* 15.0.1.64 */ + { IMG_UINT64_C(0x0016000000150010), IMG_UINT64_C(0x000000c5844b3025), IMG_UINT64_C(0x0554942c44020001), IMG_UINT64_C(0x0000000000000000) }, /* 22.0.21.16 */ + { IMG_UINT64_C(0x0016000000360019), IMG_UINT64_C(0x000000c5844b3025), IMG_UINT64_C(0x0558942c64020001), IMG_UINT64_C(0x0000000000000000) }, /* 22.0.54.25 */ + { IMG_UINT64_C(0x001600000036001e), IMG_UINT64_C(0x000000c5844b3025), IMG_UINT64_C(0x0558942c84020001), IMG_UINT64_C(0x0000000000000000) }, /* 22.0.54.30 */ + { IMG_UINT64_C(0x0016000000360026), IMG_UINT64_C(0x000000c5844b3025), IMG_UINT64_C(0x0558944c84020001), IMG_UINT64_C(0x0000000000000000) }, /* 22.0.54.38 */ + { IMG_UINT64_C(0x001600000036014a), IMG_UINT64_C(0x000000c5844b3025), IMG_UINT64_C(0x0558942c8402a591), IMG_UINT64_C(0x0000000000000000) }, /* 22.0.54.330 */ + { IMG_UINT64_C(0x0016000000680012), IMG_UINT64_C(0x000000c5844b3025), IMG_UINT64_C(0x0558944cc4020001), IMG_UINT64_C(0x0000000000000000) }, /* 22.0.104.18 */ + { IMG_UINT64_C(0x00160000006800da), IMG_UINT64_C(0x000000c5844b3025), IMG_UINT64_C(0x0558944cc402a591), IMG_UINT64_C(0x0000000000000000) }, /* 22.0.104.218 */ + { IMG_UINT64_C(0x0016000000d0013e), IMG_UINT64_C(0x000000c5844b3025), IMG_UINT64_C(0x0558a4550802a591), IMG_UINT64_C(0x0000000000000000) }, /* 22.0.208.318 */ + { IMG_UINT64_C(0x00180000003600cc), IMG_UINT64_C(0x004001c2844f7425), IMG_UINT64_C(0x0558984c8402a591), IMG_UINT64_C(0x0000000000000000) }, /* 24.0.54.204 */ + { IMG_UINT64_C(0x00180000006801f8), IMG_UINT64_C(0x004001c2844f7425), IMG_UINT64_C(0x0558984ca402a591), IMG_UINT64_C(0x0000000000000000) }, /* 24.0.104.504 */ + { IMG_UINT64_C(0x0018000000d001f8), IMG_UINT64_C(0x004001c2844f7425), IMG_UINT64_C(0x055aa8550802a591), IMG_UINT64_C(0x0000000000000000) }, /* 24.0.208.504 */ + { IMG_UINT64_C(0x0018000000d001f9), IMG_UINT64_C(0x004001c2844f7425), IMG_UINT64_C(0x055aa8550802a591), IMG_UINT64_C(0x0000000000000000) }, /* 24.0.208.505 */ + { IMG_UINT64_C(0x001d0000003400ca), IMG_UINT64_C(0x004181c2844f74a5), IMG_UINT64_C(0x0556984c4402a621), IMG_UINT64_C(0x0000000000000000) }, /* 29.0.52.202 */ + { IMG_UINT64_C(0x001d0000006c00d0), IMG_UINT64_C(0x004181c2844f74a5), IMG_UINT64_C(0x055aa854e802a621), IMG_UINT64_C(0x0000000000000000) }, /* 29.0.108.208 */ + { IMG_UINT64_C(0x00210000000b0003), IMG_UINT64_C(0x00400092844b5085), IMG_UINT64_C(0x0552984a24020001), IMG_UINT64_C(0x0000000000000000) }, /* 33.0.11.3 */ + { IMG_UINT64_C(0x0021000000160001), IMG_UINT64_C(0x004180c2854b70a5), IMG_UINT64_C(0x0556984c44020001), IMG_UINT64_C(0x0000000000000000) }, /* 33.0.22.1 */ + { IMG_UINT64_C(0x0024000000360067), IMG_UINT64_C(0x004180d2844b38a5), IMG_UINT64_C(0x0556984c8402aeb1), IMG_UINT64_C(0x0000000000000000) }, /* 36.0.54.103 */ + { IMG_UINT64_C(0x00240000003600b6), IMG_UINT64_C(0x004180d2844b78a5), IMG_UINT64_C(0x5556984c8404aeb1), IMG_UINT64_C(0x0000000000000001) }, /* 36.0.54.182 */ + { IMG_UINT64_C(0x00240000003600b7), IMG_UINT64_C(0x004180d2844b78a5), IMG_UINT64_C(0x5556984c8404aeb1), IMG_UINT64_C(0x0000000000000001) }, /* 36.0.54.183 */ + { IMG_UINT64_C(0x00240000006800b6), IMG_UINT64_C(0x004180d2844b78a5), IMG_UINT64_C(0x5556984ca404aeb1), IMG_UINT64_C(0x0000000000000001) }, /* 36.0.104.182 */ + { IMG_UINT64_C(0x00240000006800b7), IMG_UINT64_C(0x004180d2844b78a5), IMG_UINT64_C(0x5556984ca404aeb1), IMG_UINT64_C(0x0000000000000001) }, /* 36.0.104.183 */ + { IMG_UINT64_C(0x002400000068031c), IMG_UINT64_C(0x0071a0d2864a78a5), IMG_UINT64_C(0x5556984ca404aeb5), IMG_UINT64_C(0x0000000000000001) }, /* 36.0.104.796 */ }; /****************************************************************************** @@ -344,19 +361,17 @@ static const IMG_UINT64 gaErnsBrns[][2]= { IMG_UINT64_C(0x001d0013003400ca), IMG_UINT64_C(0x000000000006212a) }, /* 29.19.52.202 */ { IMG_UINT64_C(0x0021000800160001), IMG_UINT64_C(0x000000000000212a) }, /* 33.8.22.1 */ { IMG_UINT64_C(0x0021000f000b0003), IMG_UINT64_C(0x000000000000212a) }, /* 33.15.11.3 */ - { IMG_UINT64_C(0x0024001e003600b6), IMG_UINT64_C(0x000000000000212a) }, /* 36.30.54.182 */ { IMG_UINT64_C(0x00240032003600b6), IMG_UINT64_C(0x000000000000212a) }, /* 36.50.54.182 */ { IMG_UINT64_C(0x00240034006800b6), IMG_UINT64_C(0x000000000000212a) }, /* 36.52.104.182 */ { IMG_UINT64_C(0x002400350068031c), IMG_UINT64_C(0x000000000000012a) }, /* 36.53.104.796 */ { IMG_UINT64_C(0x00240036003600b7), IMG_UINT64_C(0x000000000000212a) }, /* 36.54.54.183 */ { IMG_UINT64_C(0x0024003700360067), IMG_UINT64_C(0x000000000000212a) }, /* 36.55.54.103 */ { IMG_UINT64_C(0x00240038006800b7), IMG_UINT64_C(0x000000000000212a) }, /* 36.56.104.183 */ - { IMG_UINT64_C(0x0024003c00360118), IMG_UINT64_C(0x000000000000212a) }, /* 36.60.54.280 */ }; #if defined(DEBUG) -#define FEATURE_NO_VALUES_NAMES_MAX_IDX (54) +#define FEATURE_NO_VALUES_NAMES_MAX_IDX (56) static const IMG_CHAR * const gaszFeaturesNoValuesNames[FEATURE_NO_VALUES_NAMES_MAX_IDX] = { @@ -398,6 +413,7 @@ static const IMG_CHAR * const gaszFeaturesNoValuesNames[FEATURE_NO_VALUES_NAMES_ "SLC_HYBRID_CACHELINE_64_128", "SLC_SIZE_CONFIGURABLE", "SLC_VIVT", + "SOC_TIMER", "SYS_BUS_SECURE_RESET", "TDM_PDS_CHECKSUM", "TESSELLATION", @@ -412,6 +428,7 @@ static const IMG_CHAR * const gaszFeaturesNoValuesNames[FEATURE_NO_VALUES_NAMES_ "VDM_DRAWINDIRECT", "VDM_OBJECT_LEVEL_LLS", "WATCHDOG_TIMER", + "WORKGROUP_PROTECTION", "XE_MEMORY_HIERARCHY", "XT_TOP_INFRASTRUCTURE", }; diff --git a/drivers/gpu/drm/img-rogue/km/rgx_cr_defs_km.h b/drivers/gpu/drm/img-rogue/km/rgx_cr_defs_km.h index 0a2cfc890..2464d91a7 100644 --- a/drivers/gpu/drm/img-rogue/km/rgx_cr_defs_km.h +++ b/drivers/gpu/drm/img-rogue/km/rgx_cr_defs_km.h @@ -69,6 +69,15 @@ CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. #define RGX_CR_RASTERISATION_INDIRECT_ADDRESS_CLRMSK (0xFFFFFFF0U) +/* + Register RGX_CR_USC_INDIRECT +*/ +#define RGX_CR_USC_INDIRECT (0x8000U) +#define RGX_CR_USC_INDIRECT_MASKFULL (IMG_UINT64_C(0x000000000000000F)) +#define RGX_CR_USC_INDIRECT_ADDRESS_SHIFT (0U) +#define RGX_CR_USC_INDIRECT_ADDRESS_CLRMSK (0xFFFFFFF0U) + + /* Register RGX_CR_PBE_INDIRECT */ @@ -492,6 +501,24 @@ CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. #define RGX_CR_CHANGESET_NUMBER_CHANGESET_NUMBER_CLRMSK (IMG_UINT64_C(0x0000000000000000)) +/* + Register RGX_CR_SOC_TIMER_GRAY +*/ +#define RGX_CR_SOC_TIMER_GRAY (0x00E0U) +#define RGX_CR_SOC_TIMER_GRAY_MASKFULL (IMG_UINT64_C(0xFFFFFFFFFFFFFFFF)) +#define RGX_CR_SOC_TIMER_GRAY_VALUE_SHIFT (0U) +#define RGX_CR_SOC_TIMER_GRAY_VALUE_CLRMSK (IMG_UINT64_C(0x0000000000000000)) + + +/* + Register RGX_CR_SOC_TIMER_BINARY +*/ +#define RGX_CR_SOC_TIMER_BINARY (0x00E8U) +#define RGX_CR_SOC_TIMER_BINARY_MASKFULL (IMG_UINT64_C(0xFFFFFFFFFFFFFFFF)) +#define RGX_CR_SOC_TIMER_BINARY_VALUE_SHIFT (0U) +#define RGX_CR_SOC_TIMER_BINARY_VALUE_CLRMSK (IMG_UINT64_C(0x0000000000000000)) + + /* Register RGX_CR_CLK_XTPLUS_CTRL */ @@ -5462,6 +5489,25 @@ Fast scale render */ #define RGX_CR_SLC_SIZE_IN_KB_SIZE_CLRMSK (0xFFFF0000U) +/* + Register RGX_CR_USC_TIMER +*/ +#define RGX_CR_USC_TIMER (0x46C8U) +#define RGX_CR_USC_TIMER_MASKFULL (IMG_UINT64_C(0x00000000FFFFFFFF)) +#define RGX_CR_USC_TIMER_CNT_SHIFT (0U) +#define RGX_CR_USC_TIMER_CNT_CLRMSK (0x00000000U) + + +/* + Register RGX_CR_USC_TIMER_CNT +*/ +#define RGX_CR_USC_TIMER_CNT (0x46D0U) +#define RGX_CR_USC_TIMER_CNT_MASKFULL (IMG_UINT64_C(0x0000000000000001)) +#define RGX_CR_USC_TIMER_CNT_RESET_SHIFT (0U) +#define RGX_CR_USC_TIMER_CNT_RESET_CLRMSK (0xFFFFFFFEU) +#define RGX_CR_USC_TIMER_CNT_RESET_EN (0x00000001U) + + /* Register RGX_CR_USC_UVS0_CHECKSUM */ diff --git a/drivers/gpu/drm/img-rogue/km/rgxdefs_km.h b/drivers/gpu/drm/img-rogue/km/rgxdefs_km.h index 7373f7c0a..64f4b366a 100644 --- a/drivers/gpu/drm/img-rogue/km/rgxdefs_km.h +++ b/drivers/gpu/drm/img-rogue/km/rgxdefs_km.h @@ -81,7 +81,7 @@ CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. #define RGX_BVNC_KM_V_ST RGX_BVNC_KM_ST(RGX_BVNC_KM_V) /* Maximum string size is [bb.vvvp.nnnn.cccc\0], includes null char */ -#define RGX_BVNC_STR_SIZE_MAX (2+1+4+1+4+1+4+1) +#define RGX_BVNC_STR_SIZE_MAX (2U+1U+4U+1U+4U+1U+4U+1U) #define RGX_BVNC_STR_FMTSPEC "%u.%u.%u.%u" #define RGX_BVNC_STRP_FMTSPEC "%u.%up.%u.%u" @@ -126,10 +126,10 @@ CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. #define RGXFW_THREAD_1 (1U) /* META cores (required for the RGX_FEATURE_META) */ -#define MTP218 (1) -#define MTP219 (2) -#define LTP218 (3) -#define LTP217 (4) +#define MTP218 (1U) +#define MTP219 (2U) +#define LTP218 (3U) +#define LTP217 (4U) /* META Core memory feature depending on META variants */ #define RGX_META_COREMEM_32K (32*1024) @@ -157,10 +157,14 @@ CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. #endif #endif -#define GET_ROGUE_CACHE_LINE_SIZE(x) ((((IMG_INT32)(x)) > 0) ? ((x)/8) : (0)) +#define GET_ROGUE_CACHE_LINE_SIZE(x) ((((IMG_UINT32)(x)) > 0U) ? ((IMG_UINT32)(x)/8U) : (0U)) +#if defined(SUPPORT_AGP) +#define MAX_HW_TA3DCONTEXTS 3U +#else #define MAX_HW_TA3DCONTEXTS 2U +#endif #define RGX_CR_CLK_CTRL_ALL_ON (IMG_UINT64_C(0x5555555555555555)&RGX_CR_CLK_CTRL_MASKFULL) #define RGX_CR_CLK_CTRL_ALL_AUTO (IMG_UINT64_C(0xaaaaaaaaaaaaaaaa)&RGX_CR_CLK_CTRL_MASKFULL) @@ -243,11 +247,11 @@ CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. * FW MMU contexts */ #if defined(SUPPORT_TRUSTED_DEVICE) && defined(RGX_FEATURE_META) -#define MMU_CONTEXT_MAPPING_FWPRIV (0x0) /* FW code/private data */ -#define MMU_CONTEXT_MAPPING_FWIF (0x7) /* Host/FW data */ +#define MMU_CONTEXT_MAPPING_FWPRIV (0x0U) /* FW code/private data */ +#define MMU_CONTEXT_MAPPING_FWIF (0x7U) /* Host/FW data */ #else -#define MMU_CONTEXT_MAPPING_FWPRIV (0x0) -#define MMU_CONTEXT_MAPPING_FWIF (0x0) +#define MMU_CONTEXT_MAPPING_FWPRIV (0x0U) +#define MMU_CONTEXT_MAPPING_FWIF (0x0U) #endif diff --git a/drivers/gpu/drm/img-rogue/km/rgxmhdefs_km.h b/drivers/gpu/drm/img-rogue/km/rgxmhdefs_km.h index 90e4b1b6c..fe8272b85 100644 --- a/drivers/gpu/drm/img-rogue/km/rgxmhdefs_km.h +++ b/drivers/gpu/drm/img-rogue/km/rgxmhdefs_km.h @@ -222,10 +222,10 @@ CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. #define RGX_MH_TAG_SB_MMU_ENCODING_MMU_TAG_PM_PC_WREQUEST (0x00000007U) -#define RGX_MH_TAG_ENCODING_MH_TAG_MMU_PT (0x00000000U) -#define RGX_MH_TAG_ENCODING_MH_TAG_MMU_PD (0x00000001U) -#define RGX_MH_TAG_ENCODING_MH_TAG_MMU_PC (0x00000002U) -#define RGX_MH_TAG_ENCODING_MH_TAG_MMU_PM (0x00000003U) +#define RGX_MH_TAG_ENCODING_MH_TAG_MMU (0x00000000U) +#define RGX_MH_TAG_ENCODING_MH_TAG_CPU_MMU (0x00000001U) +#define RGX_MH_TAG_ENCODING_MH_TAG_CPU_IFU (0x00000002U) +#define RGX_MH_TAG_ENCODING_MH_TAG_CPU_LSU (0x00000003U) #define RGX_MH_TAG_ENCODING_MH_TAG_MIPS (0x00000004U) #define RGX_MH_TAG_ENCODING_MH_TAG_CDM_STG0 (0x00000005U) #define RGX_MH_TAG_ENCODING_MH_TAG_CDM_STG1 (0x00000006U) diff --git a/drivers/gpu/drm/img-rogue/km_apphint.c b/drivers/gpu/drm/img-rogue/km_apphint.c index 4f2cf74a3..9246179ca 100644 --- a/drivers/gpu/drm/img-rogue/km_apphint.c +++ b/drivers/gpu/drm/img-rogue/km_apphint.c @@ -436,7 +436,8 @@ static void apphint_action_worker(struct work_struct *work) __func__, param_lookup[id].data_type, id)); } - if (PVRSRV_OK != result) { + /* Do not log errors if running in GUEST mode */ + if ((PVRSRV_OK != result) && !PVRSRV_VZ_MODE_IS(GUEST)) { PVR_DPF((PVR_DBG_ERROR, "%s: failed (%s)", __func__, PVRSRVGetErrorString(result))); @@ -1008,7 +1009,7 @@ static int apphint_debuginfo_init(const char *sub_dir, const DI_ITERATOR_CB iterator = { .pfnStart = apphint_di_start, .pfnStop = apphint_di_stop, .pfnNext = apphint_di_next, .pfnShow = apphint_di_show, - .pfnWrite = apphint_set + .pfnWrite = apphint_set, .ui32WriteLenMax = APPHINT_BUFFER_SIZE }; if (*rootdir) { @@ -1085,7 +1086,8 @@ static void apphint_pdump_values(void *pvDeviceNode, (void)vsnprintf(km_buffer, APPHINT_BUFFER_SIZE, format, ap); va_end(ap); - PDumpCommentKM(NULL, (PVRSRV_DEVICE_NODE*)pvDeviceNode, km_buffer, ui32Flags); + /* ui32CommentSize set to 0 here as function does not make use of the value. */ + PDumpCommentKM(NULL, (PVRSRV_DEVICE_NODE*)pvDeviceNode, 0, km_buffer, ui32Flags); } #endif diff --git a/drivers/gpu/drm/img-rogue/km_apphint_defs.h b/drivers/gpu/drm/img-rogue/km_apphint_defs.h index 1cec18697..16fc36b4e 100644 --- a/drivers/gpu/drm/img-rogue/km_apphint_defs.h +++ b/drivers/gpu/drm/img-rogue/km_apphint_defs.h @@ -73,13 +73,14 @@ CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. #define APPHINT_LIST_MODPARAM \ /* name, type, class, default, helper, */ \ X(EnableCDMKillingRandMode, BOOL, VALIDATION, PVRSRV_APPHINT_ENABLECDMKILLINGRANDMODE, NO_PARAM_TABLE ) \ -X(VDMContextSwitchMode, UINT32, VALIDATION, PVRSRV_APPHINT_VDMCONTEXTSWITCHMODE, NO_PARAM_TABLE ) \ \ X(HWPerfDisableCustomCounterFilter, BOOL, VALIDATION, PVRSRV_APPHINT_HWPERFDISABLECUSTOMCOUNTERFILTER, NO_PARAM_TABLE ) \ +X(ValidateSOCUSCTimer, BOOL, VALIDATION, PVRSRV_APPHINT_VALIDATESOCUSCTIMERS, NO_PARAM_TABLE ) \ X(ECCRAMErrInj, UINT32, VALIDATION, 0, NO_PARAM_TABLE ) \ \ X(TFBCCompressionControlGroup, UINT32, VALIDATION, PVRSRV_APPHINT_TFBCCOMPRESSIONCONTROLGROUP, NO_PARAM_TABLE ) \ X(TFBCCompressionControlScheme, UINT32, VALIDATION, PVRSRV_APPHINT_TFBCCOMPRESSIONCONTROLSCHEME, NO_PARAM_TABLE ) \ +X(TFBCCompressionControlYUVFormat, BOOL, VALIDATION, 0, NO_PARAM_TABLE ) \ /* ******************************************************************************* diff --git a/drivers/gpu/drm/img-rogue/km_apphint_defs_common.h b/drivers/gpu/drm/img-rogue/km_apphint_defs_common.h index 44d6ec450..987d37c10 100644 --- a/drivers/gpu/drm/img-rogue/km_apphint_defs_common.h +++ b/drivers/gpu/drm/img-rogue/km_apphint_defs_common.h @@ -54,7 +54,6 @@ CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. /* name, type, class, default, helper, */ \ X(EnableTrustedDeviceAceConfig, BOOL, GPUVIRT_VAL, PVRSRV_APPHINT_ENABLETRUSTEDDEVICEACECONFIG, NO_PARAM_TABLE ) \ X(CleanupThreadPriority, UINT32, NEVER, PVRSRV_APPHINT_CLEANUPTHREADPRIORITY, NO_PARAM_TABLE ) \ -X(CacheOpThreadPriority, UINT32, NEVER, PVRSRV_APPHINT_CACHEOPTHREADPRIORITY, NO_PARAM_TABLE ) \ X(WatchdogThreadPriority, UINT32, NEVER, PVRSRV_APPHINT_WATCHDOGTHREADPRIORITY, NO_PARAM_TABLE ) \ X(HWPerfClientBufferSize, UINT32, ALWAYS, PVRSRV_APPHINT_HWPERFCLIENTBUFFERSIZE, NO_PARAM_TABLE ) \ @@ -157,7 +156,7 @@ X(EnableAPM, UINT32, ALWAYS, PVRSRV_APPHINT_ X(DisableFEDLogging, BOOL, ALWAYS, PVRSRV_APPHINT_DISABLEFEDLOGGING, NO_PARAM_TABLE ) \ X(ZeroFreelist, BOOL, ALWAYS, PVRSRV_APPHINT_ZEROFREELIST, NO_PARAM_TABLE ) \ X(DisablePDumpPanic, BOOL, PDUMP, PVRSRV_APPHINT_DISABLEPDUMPPANIC, NO_PARAM_TABLE ) \ -X(EnableFWPoisonOnFree, BOOL, ALWAYS, PVRSRV_APPHINT_ENABLEFWPOISONONFREE, NO_PARAM_TABLE ) \ +X(EnableFWPoisonOnFree, BOOL, DEBUG, PVRSRV_APPHINT_ENABLEFWPOISONONFREE, NO_PARAM_TABLE ) \ X(GPUUnitsPowerChange, BOOL, VALIDATION, PVRSRV_APPHINT_GPUUNITSPOWERCHANGE, NO_PARAM_TABLE ) \ X(HWPerfHostFilter, UINT32, ALWAYS, PVRSRV_APPHINT_HWPERFHOSTFILTER, NO_PARAM_TABLE ) diff --git a/drivers/gpu/drm/img-rogue/lists.h b/drivers/gpu/drm/img-rogue/lists.h index cef724e47..2e2c29a0b 100644 --- a/drivers/gpu/drm/img-rogue/lists.h +++ b/drivers/gpu/drm/img-rogue/lists.h @@ -46,7 +46,19 @@ CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. /* instruct QAC to ignore warnings about the following custom formatted macros */ /* PRQA S 0881,3410 ++ */ -#include + +#if defined(__linux__) + #include + + #if (LINUX_VERSION_CODE >= KERNEL_VERSION(5, 15, 0)) + #include + #else + #include + #endif /* LINUX_VERSION_CODE >= KERNEL_VERSION(5, 15, 0) */ +#else + #include +#endif /* __linux__ */ + #include "img_types.h" #include "device.h" #include "power.h" diff --git a/drivers/gpu/drm/img-rogue/lock.h b/drivers/gpu/drm/img-rogue/lock.h index 0f965ccb3..3ef78215f 100644 --- a/drivers/gpu/drm/img-rogue/lock.h +++ b/drivers/gpu/drm/img-rogue/lock.h @@ -64,12 +64,12 @@ CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. *(phLock) = OSAllocMem(sizeof(struct mutex)); \ if (*(phLock)) { mutex_init(*(phLock)); e = PVRSRV_OK; }; \ e;}) -#define OSLockDestroy(hLock) ({mutex_destroy((hLock)); OSFreeMem((hLock)); PVRSRV_OK;}) -#define OSLockDestroyNoStats(hLock) ({mutex_destroy((hLock)); OSFreeMemNoStats((hLock)); PVRSRV_OK;}) +#define OSLockDestroy(hLock) ({mutex_destroy((hLock)); OSFreeMem((hLock));}) +#define OSLockDestroyNoStats(hLock) ({mutex_destroy((hLock)); OSFreeMemNoStats((hLock));}) -#define OSLockAcquire(hLock) ({mutex_lock((hLock)); PVRSRV_OK;}) -#define OSLockAcquireNested(hLock, subclass) ({mutex_lock_nested((hLock), (subclass)); PVRSRV_OK;}) -#define OSLockRelease(hLock) ({mutex_unlock((hLock)); PVRSRV_OK;}) +#define OSLockAcquire(hLock) ({mutex_lock((hLock));}) +#define OSLockAcquireNested(hLock, subclass) ({mutex_lock_nested((hLock), (subclass));}) +#define OSLockRelease(hLock) ({mutex_unlock((hLock));}) #define OSLockIsLocked(hLock) ((mutex_is_locked((hLock)) == 1) ? IMG_TRUE : IMG_FALSE) #define OSTryLockAcquire(hLock) ((mutex_trylock(hLock) == 1) ? IMG_TRUE : IMG_FALSE) @@ -114,10 +114,10 @@ static inline IMG_INT OSAtomicOr(ATOMIC_T *pCounter, IMG_INT iVal) } #define OSAtomicAdd(pCounter, incr) atomic_add_return(incr,pCounter) -#define OSAtomicAddUnless(pCounter, incr, test) __atomic_add_unless(pCounter,incr,test) +#define OSAtomicAddUnless(pCounter, incr, test) atomic_add_unless(pCounter, (incr), (test)) #define OSAtomicSubtract(pCounter, incr) atomic_add_return(-(incr),pCounter) -#define OSAtomicSubtractUnless(pCounter, incr, test) OSAtomicAddUnless(pCounter, -(incr), test) +#define OSAtomicSubtractUnless(pCounter, incr, test) OSAtomicAddUnless(pCounter, -(incr), (test)) #else /* defined(__linux__) && defined(__KERNEL__) */ @@ -147,7 +147,7 @@ PVRSRV_ERROR OSLockCreate(POS_LOCK *phLock); @Return None. */ /**************************************************************************/ IMG_INTERNAL -PVRSRV_ERROR OSLockDestroy(POS_LOCK hLock); +void OSLockDestroy(POS_LOCK hLock); #if defined(INTEGRITY_OS) #define OSLockDestroyNoStats OSLockDestroy @@ -412,11 +412,17 @@ IMG_INT32 OSAtomicOr(ATOMIC_T *pCounter, IMG_INT32 iVal); /* For now, spin-locks are required on Linux only, so other platforms fake * spinlocks with normal mutex locks */ +/*! Type definitions for OS_SPINLOCK accessor and creation / deletion */ typedef unsigned long OS_SPINLOCK_FLAGS; +/*! Pointer to an OS Spinlock */ #define POS_SPINLOCK POS_LOCK +/*! Wrapper for OSLockCreate() */ #define OSSpinLockCreate(ppLock) OSLockCreate(ppLock) +/*! Wrapper for OSLockDestroy() */ #define OSSpinLockDestroy(pLock) OSLockDestroy(pLock) +/*! Wrapper for OSLockAcquire() */ #define OSSpinLockAcquire(pLock, flags) {flags = 0; OSLockAcquire(pLock);} +/*! Wrapper for OSLockRelease() */ #define OSSpinLockRelease(pLock, flags) {flags = 0; OSLockRelease(pLock);} #endif /* defined(__linux__) */ diff --git a/drivers/gpu/drm/img-rogue/lock_types.h b/drivers/gpu/drm/img-rogue/lock_types.h index c9e784ef8..370ffc025 100644 --- a/drivers/gpu/drm/img-rogue/lock_types.h +++ b/drivers/gpu/drm/img-rogue/lock_types.h @@ -60,29 +60,29 @@ typedef atomic_t ATOMIC_T; #else /* defined(__linux__) && defined(__KERNEL__) */ #include "img_types.h" /* needed for IMG_INT */ -typedef struct _OS_LOCK_ *POS_LOCK; +typedef struct OS_LOCK_TAG *POS_LOCK; #if defined(__linux__) || defined(__QNXNTO__) || defined(INTEGRITY_OS) -typedef struct _OSWR_LOCK_ *POSWR_LOCK; +typedef struct OSWR_LOCK_TAG *POSWR_LOCK; #else /* defined(__linux__) || defined(__QNXNTO__) || defined(INTEGRITY_OS) */ -typedef struct _OSWR_LOCK_ { +typedef struct OSWR_LOCK_TAG { IMG_UINT32 ui32Dummy; } *POSWR_LOCK; #endif /* defined(__linux__) || defined(__QNXNTO__) || defined(INTEGRITY_OS) */ #if defined(__linux__) - typedef struct _OS_ATOMIC {IMG_INT32 counter;} ATOMIC_T; + typedef struct OS_ATOMIC_TAG {IMG_INT32 counter;} ATOMIC_T; #elif defined(__QNXNTO__) - typedef struct _OS_ATOMIC {IMG_INT32 counter;} ATOMIC_T; + typedef struct OS_ATOMIC_TAG {IMG_INT32 counter;} ATOMIC_T; #elif defined(_WIN32) /* * Dummy definition. WDDM doesn't use Services, but some headers * still have to be shared. This is one such case. */ - typedef struct _OS_ATOMIC {IMG_INT32 counter;} ATOMIC_T; + typedef struct OS_ATOMIC_TAG {IMG_INT32 counter;} ATOMIC_T; #elif defined(INTEGRITY_OS) /* Only lower 32bits are used in OS ATOMIC APIs to have consistent behaviour across all OS */ - typedef struct _OS_ATOMIC {IMG_INT64 counter;} ATOMIC_T; + typedef struct OS_ATOMIC_TAG {IMG_INT64 counter;} ATOMIC_T; #else #error "Please type-define an atomic lock for this environment" #endif diff --git a/drivers/gpu/drm/img-rogue/log2.h b/drivers/gpu/drm/img-rogue/log2.h index 4cba23f9d..2182a0223 100644 --- a/drivers/gpu/drm/img-rogue/log2.h +++ b/drivers/gpu/drm/img-rogue/log2.h @@ -270,7 +270,7 @@ static INLINE uint32_t __const_function FloorLog2(uint32_t n) { uint32_t ui32log2 = 0; - while (n >>= 1) + while ((n >>= 1) != 0U) { ui32log2++; } @@ -287,7 +287,7 @@ static INLINE uint32_t __const_function FloorLog2_64(uint64_t n) { uint32_t ui32log2 = 0; - while (n >>= 1) + while ((n >>= 1) != 0U) { ui32log2++; } @@ -311,7 +311,7 @@ static INLINE uint32_t __const_function CeilLog2(uint32_t n) n--; /* Handle powers of 2 */ - while (n) + while (n != 0U) { ui32log2++; n >>= 1; @@ -336,7 +336,7 @@ static INLINE uint32_t __const_function CeilLog2_64(uint64_t n) n--; /* Handle powers of 2 */ - while (n) + while (n != 0U) { ui32log2++; n >>= 1; diff --git a/drivers/gpu/drm/img-rogue/mmu_common.c b/drivers/gpu/drm/img-rogue/mmu_common.c index 71975e744..1d9bfd71d 100644 --- a/drivers/gpu/drm/img-rogue/mmu_common.c +++ b/drivers/gpu/drm/img-rogue/mmu_common.c @@ -337,7 +337,7 @@ _FreeMMUMapping(PVRSRV_DEVICE_NODE *psDevNode, MMU_MEMORY_MAPPING, sMMUMappingItem); - psDevNode->sDevMMUPxSetup.pfnDevPxFree(psDevNode, &psMapping->sMemHandle); + PhysHeapPagesFree(psDevNode->psMMUPhysHeap, &psMapping->sMemHandle); dllist_remove_node(psNode); OSFreeMem(psMapping); } @@ -722,10 +722,10 @@ void RGXMapBRN71422TargetPhysicalAddress(MMU_CONTEXT *psMMUContext) { PVRSRV_ERROR eError; PVRSRV_DEVICE_NODE *psDevNode = (PVRSRV_DEVICE_NODE *)psMMUContext->psPhysMemCtx->psDevNode; - eError = psDevNode->sDevMMUPxSetup.pfnDevPxClean(psDevNode, - &psMemDesc->psMapping->sMemHandle, - psMemDesc->uiOffset, - psMemDesc->uiSize); + eError = PhysHeapPagesClean(psDevNode->psMMUPhysHeap, + &psMemDesc->psMapping->sMemHandle, + psMemDesc->uiOffset, + psMemDesc->uiSize); PVR_LOG_IF_ERROR(eError, "pfnDevPxClean"); } @@ -795,18 +795,18 @@ static PVRSRV_ERROR _MMU_PhysMem_RAImportAlloc(RA_PERARENA_HANDLE hArenaHandle, * pfnDevPxFree() routine. */ psMapping->sMemHandle.uiOSid = psPhysMemCtx->ui32OSid; - eError = psDevNode->sDevMMUPxSetup.pfnDevPxAllocGPV(psDevNode, - TRUNCATE_64BITS_TO_SIZE_T(uiSize), - &psMapping->sMemHandle, - &psMapping->sDevPAddr, - psPhysMemCtx->ui32OSid, - uiPid); + eError = PhysHeapPagesAllocGPV(psDevNode->psMMUPhysHeap, + TRUNCATE_64BITS_TO_SIZE_T(uiSize), + &psMapping->sMemHandle, + &psMapping->sDevPAddr, + psPhysMemCtx->ui32OSid, + uiPid); #else - eError = psDevNode->sDevMMUPxSetup.pfnDevPxAlloc(psDevNode, - TRUNCATE_64BITS_TO_SIZE_T(uiSize), - &psMapping->sMemHandle, - &psMapping->sDevPAddr, - uiPid); + eError = PhysHeapPagesAlloc(psDevNode->psMMUPhysHeap, + TRUNCATE_64BITS_TO_SIZE_T(uiSize), + &psMapping->sMemHandle, + &psMapping->sDevPAddr, + uiPid); #endif if (eError != PVRSRV_OK) { @@ -915,11 +915,11 @@ static PVRSRV_ERROR _MMU_PhysMemAlloc(MMU_PHYSMEM_CONTEXT *psPhysMemCtx, if (psMemDesc->psMapping->uiCpuVAddrRefCount == 0) { - eError = psPhysMemCtx->psDevNode->sDevMMUPxSetup.pfnDevPxMap(psPhysMemCtx->psDevNode, - &psMemDesc->psMapping->sMemHandle, - psMemDesc->psMapping->uiSize, - &psMemDesc->psMapping->sDevPAddr, - &psMemDesc->psMapping->pvCpuVAddr); + eError = PhysHeapPagesMap(psPhysMemCtx->psDevNode->psMMUPhysHeap, + &psMemDesc->psMapping->sMemHandle, + psMemDesc->psMapping->uiSize, + &psMemDesc->psMapping->sDevPAddr, + &psMemDesc->psMapping->pvCpuVAddr); if (eError != PVRSRV_OK) { RA_Free(psPhysMemCtx->psPhysMemRA, psMemDesc->sDevPAddr.uiAddr); @@ -957,9 +957,9 @@ static void _MMU_PhysMemFree(MMU_PHYSMEM_CONTEXT *psPhysMemCtx, if (--psMemDesc->psMapping->uiCpuVAddrRefCount == 0) { - psPhysMemCtx->psDevNode->sDevMMUPxSetup.pfnDevPxUnMap(psPhysMemCtx->psDevNode, - &psMemDesc->psMapping->sMemHandle, - psMemDesc->psMapping->pvCpuVAddr); + PhysHeapPagesUnMap(psPhysMemCtx->psDevNode->psMMUPhysHeap, + &psMemDesc->psMapping->sMemHandle, + psMemDesc->psMapping->pvCpuVAddr); } psMemDesc->pvCpuVAddr = NULL; @@ -1125,10 +1125,10 @@ static PVRSRV_ERROR _PxMemAlloc(MMU_CONTEXT *psMMUContext, */ OSCachedMemSet(psMemDesc->pvCpuVAddr, 0, uiBytes); - eError = psDevNode->sDevMMUPxSetup.pfnDevPxClean(psDevNode, - &psMemDesc->psMapping->sMemHandle, - psMemDesc->uiOffset, - psMemDesc->uiSize); + eError = PhysHeapPagesClean(psDevNode->psMMUPhysHeap, + &psMemDesc->psMapping->sMemHandle, + psMemDesc->uiOffset, + psMemDesc->uiSize); PVR_GOTO_IF_ERROR(eError, e1); #if defined(PDUMP) @@ -1654,10 +1654,10 @@ static IMG_BOOL _MMU_FreeLevel(MMU_CONTEXT *psMMUContext, /* Level one flushing is done when we actually write the table entries */ if ((aeMMULevel[uiThisLevel] != MMU_LEVEL_1) && (psLevel != NULL)) { - psDevNode->sDevMMUPxSetup.pfnDevPxClean(psDevNode, - &psLevel->sMemDesc.psMapping->sMemHandle, - uiStartIndex * psConfig->uiBytesPerEntry + psLevel->sMemDesc.uiOffset, - (uiEndIndex - uiStartIndex) * psConfig->uiBytesPerEntry); + PhysHeapPagesClean(psDevNode->psMMUPhysHeap, + &psLevel->sMemDesc.psMapping->sMemHandle, + uiStartIndex * psConfig->uiBytesPerEntry + psLevel->sMemDesc.uiOffset, + (uiEndIndex - uiStartIndex) * psConfig->uiBytesPerEntry); } MMU_OBJ_DBG((PVR_DBG_ERROR, "_MMU_FreeLevel end: level = %d, refcount = %d", @@ -1872,10 +1872,10 @@ static PVRSRV_ERROR _MMU_AllocLevel(MMU_CONTEXT *psMMUContext, /* Level one flushing is done when we actually write the table entries */ if (aeMMULevel[uiThisLevel] != MMU_LEVEL_1) { - eError = psDevNode->sDevMMUPxSetup.pfnDevPxClean(psDevNode, - &psLevel->sMemDesc.psMapping->sMemHandle, - uiStartIndex * psConfig->uiBytesPerEntry + psLevel->sMemDesc.uiOffset, - (uiEndIndex - uiStartIndex) * psConfig->uiBytesPerEntry); + eError = PhysHeapPagesClean(psDevNode->psMMUPhysHeap, + &psLevel->sMemDesc.psMapping->sMemHandle, + uiStartIndex * psConfig->uiBytesPerEntry + psLevel->sMemDesc.uiOffset, + (uiEndIndex - uiStartIndex) * psConfig->uiBytesPerEntry); PVR_GOTO_IF_ERROR(eError, e0); } @@ -2267,7 +2267,7 @@ static void _FreePageTables(MMU_CONTEXT *psMMUContext, static INLINE void _MMU_GetPTInfo(MMU_CONTEXT *psMMUContext, IMG_DEV_VIRTADDR sDevVAddr, const MMU_DEVVADDR_CONFIG *psDevVAddrConfig, - MMU_Levelx_INFO **psLevel, + MMU_Levelx_INFO **ppsLevel, IMG_UINT32 *pui32PTEIndex) { MMU_Levelx_INFO *psLocalLevel = NULL; @@ -2278,8 +2278,7 @@ static INLINE void _MMU_GetPTInfo(MMU_CONTEXT *psMMUContext, if ((eMMULevel <= MMU_LEVEL_0) || (eMMULevel >= MMU_LEVEL_LAST)) { PVR_DPF((PVR_DBG_ERROR, "_MMU_GetPTEInfo: Invalid MMU level")); - psLevel = NULL; - return; + PVR_ASSERT(0); } for (; eMMULevel > MMU_LEVEL_0; eMMULevel--) @@ -2319,7 +2318,7 @@ static INLINE void _MMU_GetPTInfo(MMU_CONTEXT *psMMUContext, } } } - *psLevel = psLocalLevel; + *ppsLevel = psLocalLevel; } /*************************************************************************/ /*! @@ -2499,7 +2498,7 @@ MMU_ContextCreate(CONNECTION_DATA *psConnection, psPhysMemCtx->psPhysMemRA = RA_Create(psPhysMemCtx->pszPhysMemRAName, /* subsequent import */ - psDevNode->sDevMMUPxSetup.uiMMUPxLog2AllocGran, + PhysHeapGetPageShift(psDevNode->psMMUPhysHeap), RA_LOCKCLASS_1, _MMU_PhysMem_RAImportAlloc, _MMU_PhysMem_RAImportFree, @@ -2843,17 +2842,6 @@ MMU_MapPages(MMU_CONTEXT *psMMUContext, (IMG_UINT64)(ui32MapPageCount * uiPageSize)); #endif /*PDUMP*/ -#if defined(TC_MEMORY_CONFIG) || defined(PLATO_MEMORY_CONFIG) - /* We're aware that on TC based platforms, accesses from GPU to CPU_LOCAL - * allocated DevMem fail, so we forbid mapping such a PMR into device mmu */ - if (PVRSRV_CHECK_PHYS_HEAP(CPU_LOCAL, PMR_Flags(psPMR))) - { - PVR_DPF((PVR_DBG_ERROR, - "%s: Mapping a CPU_LOCAL PMR to device is forbidden on this platform", __func__)); - return PVRSRV_ERROR_PMR_NOT_PERMITTED; - } -#endif - /* Validate the most essential parameters */ PVR_LOG_GOTO_IF_INVALID_PARAM(psMMUContext, eError, e0); PVR_LOG_GOTO_IF_INVALID_PARAM(psPMR, eError, e0); @@ -2952,17 +2940,11 @@ MMU_MapPages(MMU_CONTEXT *psMMUContext, { uiDummyProtFlags = psMMUContext->psDevAttrs->pfnDerivePTEProt8(uiMMUProtFlags , uiLog2HeapPageSize); } - else if (psConfig->uiBytesPerEntry == 4) - { - uiDummyProtFlags = psMMUContext->psDevAttrs->pfnDerivePTEProt4(uiMMUProtFlags); - } else { - PVR_DPF((PVR_DBG_ERROR, - "%s: The page table entry byte length is not supported", - __func__)); - eError = PVRSRV_ERROR_INVALID_PARAMS; - goto e2; + /* We've already validated possible values of uiBytesPerEntry at the start of this function */ + PVR_ASSERT(psConfig->uiBytesPerEntry == 4); + uiDummyProtFlags = psMMUContext->psDevAttrs->pfnDerivePTEProt4(uiMMUProtFlags); } } } @@ -3086,10 +3068,10 @@ MMU_MapPages(MMU_CONTEXT *psMMUContext, /* Flush if we moved to another psLevel, i.e. page table */ if (psPrevLevel != NULL) { - eError = psDevNode->sDevMMUPxSetup.pfnDevPxClean(psDevNode, - &psPrevLevel->sMemDesc.psMapping->sMemHandle, - uiFlushStart * psConfig->uiBytesPerEntry + psPrevLevel->sMemDesc.uiOffset, - (uiFlushEnd+1 - uiFlushStart) * psConfig->uiBytesPerEntry); + eError = PhysHeapPagesClean(psDevNode->psMMUPhysHeap, + &psPrevLevel->sMemDesc.psMapping->sMemHandle, + uiFlushStart * psConfig->uiBytesPerEntry + psPrevLevel->sMemDesc.uiOffset, + (uiFlushEnd+1 - uiFlushStart) * psConfig->uiBytesPerEntry); PVR_GOTO_IF_ERROR(eError, e3); } @@ -3136,10 +3118,10 @@ MMU_MapPages(MMU_CONTEXT *psMMUContext, /* Flush the last level we touched */ if (psLevel != NULL) { - eError = psDevNode->sDevMMUPxSetup.pfnDevPxClean(psDevNode, - &psLevel->sMemDesc.psMapping->sMemHandle, - uiFlushStart * psConfig->uiBytesPerEntry + psLevel->sMemDesc.uiOffset, - (uiFlushEnd+1 - uiFlushStart) * psConfig->uiBytesPerEntry); + eError = PhysHeapPagesClean(psDevNode->psMMUPhysHeap, + &psLevel->sMemDesc.psMapping->sMemHandle, + uiFlushStart * psConfig->uiBytesPerEntry + psLevel->sMemDesc.uiOffset, + (uiFlushEnd+1 - uiFlushStart) * psConfig->uiBytesPerEntry); PVR_GOTO_IF_ERROR(eError, e3); } @@ -3303,10 +3285,10 @@ MMU_UnmapPages(MMU_CONTEXT *psMMUContext, /* Flush if we moved to another psLevel, i.e. page table */ if (psPrevLevel != NULL) { - psDevNode->sDevMMUPxSetup.pfnDevPxClean(psDevNode, - &psPrevLevel->sMemDesc.psMapping->sMemHandle, - uiFlushStart * psConfig->uiBytesPerEntry + psPrevLevel->sMemDesc.uiOffset, - (uiFlushEnd+1 - uiFlushStart) * psConfig->uiBytesPerEntry); + PhysHeapPagesClean(psDevNode->psMMUPhysHeap, + &psPrevLevel->sMemDesc.psMapping->sMemHandle, + uiFlushStart * psConfig->uiBytesPerEntry + psPrevLevel->sMemDesc.uiOffset, + (uiFlushEnd+1 - uiFlushStart) * psConfig->uiBytesPerEntry); } uiFlushStart = uiPTEIndex; @@ -3342,10 +3324,10 @@ MMU_UnmapPages(MMU_CONTEXT *psMMUContext, /* Flush the last level we touched */ if (psLevel != NULL) { - psDevNode->sDevMMUPxSetup.pfnDevPxClean(psDevNode, - &psLevel->sMemDesc.psMapping->sMemHandle, - uiFlushStart * psConfig->uiBytesPerEntry + psLevel->sMemDesc.uiOffset, - (uiFlushEnd+1 - uiFlushStart) * psConfig->uiBytesPerEntry); + PhysHeapPagesClean(psDevNode->psMMUPhysHeap, + &psLevel->sMemDesc.psMapping->sMemHandle, + uiFlushStart * psConfig->uiBytesPerEntry + psLevel->sMemDesc.uiOffset, + (uiFlushEnd+1 - uiFlushStart) * psConfig->uiBytesPerEntry); } OSLockRelease(psMMUContext->hLock); @@ -3407,17 +3389,6 @@ MMU_MapPMRFast (MMU_CONTEXT *psMMUContext, PVR_ASSERT (psMMUContext != NULL); PVR_ASSERT (psPMR != NULL); -#if defined(TC_MEMORY_CONFIG) || defined(PLATO_MEMORY_CONFIG) - /* We're aware that on TC based platforms, accesses from GPU to CPU_LOCAL - * allocated DevMem fail, so we forbid mapping such a PMR into device mmu */ - if (PVRSRV_CHECK_PHYS_HEAP(CPU_LOCAL, PMR_Flags(psPMR))) - { - PVR_DPF((PVR_DBG_ERROR, - "%s: Mapping a CPU_LOCAL PMR to device is forbidden on this platform", __func__)); - return PVRSRV_ERROR_PMR_NOT_PERMITTED; - } -#endif - /* Allocate memory for page-frame-numbers and validity states, N.B. assert could be triggered by an illegal uiSizeBytes */ uiCount = uiSizeBytes >> uiLog2HeapPageSize; @@ -3551,10 +3522,10 @@ MMU_MapPMRFast (MMU_CONTEXT *psMMUContext, } else { - eError = psDevNode->sDevMMUPxSetup.pfnDevPxClean(psDevNode, - &psLevel->sMemDesc.psMapping->sMemHandle, - uiFlushStart * psConfig->uiBytesPerEntry + psLevel->sMemDesc.uiOffset, - (uiPTEIndex+1 - uiFlushStart) * psConfig->uiBytesPerEntry); + eError = PhysHeapPagesClean(psDevNode->psMMUPhysHeap, + &psLevel->sMemDesc.psMapping->sMemHandle, + uiFlushStart * psConfig->uiBytesPerEntry + psLevel->sMemDesc.uiOffset, + (uiPTEIndex+1 - uiFlushStart) * psConfig->uiBytesPerEntry); PVR_GOTO_IF_ERROR(eError, unlock_mmu_context); @@ -3695,16 +3666,10 @@ MMU_UnmapPMRFast(MMU_CONTEXT *psMMUContext, { ((IMG_UINT64*)psLevel->sMemDesc.pvCpuVAddr)[uiPTEIndex] = uiEntry; } - else if (psConfig->uiBytesPerEntry == 4) - { - ((IMG_UINT32*)psLevel->sMemDesc.pvCpuVAddr)[uiPTEIndex] = (IMG_UINT32) uiEntry; - } else { - PVR_DPF((PVR_DBG_ERROR, - "%s: The page table entry byte length is not supported", - __func__)); - goto e1; + PVR_ASSERT(psConfig->uiBytesPerEntry == 4); + ((IMG_UINT32*)psLevel->sMemDesc.pvCpuVAddr)[uiPTEIndex] = (IMG_UINT32) uiEntry; } /* Log modifications */ @@ -3748,10 +3713,10 @@ MMU_UnmapPMRFast(MMU_CONTEXT *psMMUContext, } else { - psDevNode->sDevMMUPxSetup.pfnDevPxClean(psDevNode, - &psLevel->sMemDesc.psMapping->sMemHandle, - uiFlushStart * psConfig->uiBytesPerEntry + psLevel->sMemDesc.uiOffset, - (uiPTEIndex+1 - uiFlushStart) * psConfig->uiBytesPerEntry); + PhysHeapPagesClean(psDevNode->psMMUPhysHeap, + &psLevel->sMemDesc.psMapping->sMemHandle, + uiFlushStart * psConfig->uiBytesPerEntry + psLevel->sMemDesc.uiOffset, + (uiPTEIndex+1 - uiFlushStart) * psConfig->uiBytesPerEntry); _MMU_GetPTInfo(psMMUContext, sDevVAddr, psDevVAddrConfig, &psLevel, &uiPTEIndex); @@ -3771,9 +3736,6 @@ MMU_UnmapPMRFast(MMU_CONTEXT *psMMUContext, return; -e1: - OSLockRelease(psMMUContext->hLock); - _MMU_PutPTConfig(psMMUContext, hPriv); e0: PVR_DPF((PVR_DBG_ERROR, "%s: Failed to map/unmap page table", __func__)); PVR_ASSERT(0); @@ -3911,10 +3873,10 @@ MMU_ChangeValidity(MMU_CONTEXT *psMMUContext, else { - eError = psDevNode->sDevMMUPxSetup.pfnDevPxClean(psDevNode, - &psLevel->sMemDesc.psMapping->sMemHandle, - uiFlushStart * psConfig->uiBytesPerEntry + psLevel->sMemDesc.uiOffset, - (uiPTIndex+1 - uiFlushStart) * psConfig->uiBytesPerEntry); + eError = PhysHeapPagesClean(psDevNode->psMMUPhysHeap, + &psLevel->sMemDesc.psMapping->sMemHandle, + uiFlushStart * psConfig->uiBytesPerEntry + psLevel->sMemDesc.uiOffset, + (uiPTIndex+1 - uiFlushStart) * psConfig->uiBytesPerEntry); PVR_GOTO_IF_ERROR(eError, e_exit); _MMU_GetPTInfo(psMMUContext, sDevVAddr, psDevVAddrConfig, @@ -3955,6 +3917,23 @@ MMU_AcquireBaseAddr(MMU_CONTEXT *psMMUContext, IMG_DEV_PHYADDR *psPhysAddr) return PVRSRV_OK; } +/* + MMU_AcquireCPUBaseAddr + */ +PVRSRV_ERROR +MMU_AcquireCPUBaseAddr(MMU_CONTEXT *psMMUContext, void **ppvCPUVAddr) +{ + if (!psMMUContext) + { + *ppvCPUVAddr = NULL; + return PVRSRV_ERROR_INVALID_PARAMS; + } + + *ppvCPUVAddr = psMMUContext->sBaseLevelInfo.sMemDesc.pvCpuVAddr; + + return PVRSRV_OK; +} + /* MMU_ReleaseBaseAddr */ diff --git a/drivers/gpu/drm/img-rogue/mmu_common.h b/drivers/gpu/drm/img-rogue/mmu_common.h index 1a745e4ad..a84fa697f 100644 --- a/drivers/gpu/drm/img-rogue/mmu_common.h +++ b/drivers/gpu/drm/img-rogue/mmu_common.h @@ -554,6 +554,22 @@ MMU_ChangeValidity(MMU_CONTEXT *psMMUContext, PVRSRV_ERROR MMU_AcquireBaseAddr(MMU_CONTEXT *psMMUContext, IMG_DEV_PHYADDR *psPhysAddr); +/*************************************************************************/ /*! +@Function MMU_AcquireCPUBaseAddr + +@Description Acquire the CPU Virtual Address of the base level MMU object + +@Input psMMUContext MMU context to operate on + +@Output ppvCPUVAddr CPU Virtual Address of the base level + MMU object + +@Return PVRSRV_OK if successful +*/ +/*****************************************************************************/ +PVRSRV_ERROR +MMU_AcquireCPUBaseAddr(MMU_CONTEXT *psMMUContext, void **ppvCPUVAddr); + /*************************************************************************/ /*! @Function MMU_ReleaseBaseAddr diff --git a/drivers/gpu/drm/img-rogue/module_common.c b/drivers/gpu/drm/img-rogue/module_common.c index 0b6071c26..bf01dadbc 100644 --- a/drivers/gpu/drm/img-rogue/module_common.c +++ b/drivers/gpu/drm/img-rogue/module_common.c @@ -119,7 +119,7 @@ EXPORT_SYMBOL(RGXInitSLC); EXPORT_SYMBOL(RGXHWPerfConnect); EXPORT_SYMBOL(RGXHWPerfDisconnect); EXPORT_SYMBOL(RGXHWPerfControl); -#if defined(HWPERF_PACKET_V2C_SIG) +#if defined(RGX_FEATURE_HWPERF_VOLCANIC) EXPORT_SYMBOL(RGXHWPerfConfigureCounters); #else EXPORT_SYMBOL(RGXHWPerfConfigMuxCounters); @@ -137,13 +137,34 @@ EXPORT_SYMBOL(OSRemoveTimer); #endif #endif -CONNECTION_DATA *LinuxConnectionFromFile(struct file *pFile) +static int PVRSRVDeviceSyncOpen(struct _PVRSRV_DEVICE_NODE_ *psDeviceNode, + struct drm_file *psDRMFile); + +CONNECTION_DATA *LinuxServicesConnectionFromFile(struct file *pFile) { if (pFile) { struct drm_file *psDRMFile = pFile->private_data; + PVRSRV_CONNECTION_PRIV *psConnectionPriv = (PVRSRV_CONNECTION_PRIV*)psDRMFile->driver_priv; - return psDRMFile->driver_priv; + return (CONNECTION_DATA*)psConnectionPriv->pvConnectionData; + } + + return NULL; +} + +CONNECTION_DATA *LinuxSyncConnectionFromFile(struct file *pFile) +{ + if (pFile) + { + struct drm_file *psDRMFile = pFile->private_data; + PVRSRV_CONNECTION_PRIV *psConnectionPriv = (PVRSRV_CONNECTION_PRIV*)psDRMFile->driver_priv; + +#if (PVRSRV_DEVICE_INIT_MODE == PVRSRV_LINUX_DEV_INIT_ON_CONNECT) + return (CONNECTION_DATA*)psConnectionPriv->pvConnectionData; +#else + return (CONNECTION_DATA*)psConnectionPriv->pvSyncConnectionData; +#endif } return NULL; @@ -200,6 +221,21 @@ int PVRSRVDriverInit(void) } #endif +#if defined(ANDROID) +#if defined(CONFIG_PROC_FS) + error = PVRProcFsRegister(); + if (error != PVRSRV_OK) + { + return -ENOMEM; + } +#elif defined(CONFIG_DEBUG_FS) + error = PVRDebugFsRegister(); + if (error != PVRSRV_OK) + { + return -ENOMEM; + } +#endif /* defined(CONFIG_PROC_FS) || defined(CONFIG_DEBUG_FS) */ +#else #if defined(CONFIG_DEBUG_FS) error = PVRDebugFsRegister(); if (error != PVRSRV_OK) @@ -213,6 +249,7 @@ int PVRSRVDriverInit(void) return -ENOMEM; } #endif /* defined(CONFIG_DEBUG_FS) || defined(CONFIG_PROC_FS) */ +#endif /* defined(ANDROID) */ error = PVRSRVIonStatsInitialise(); if (error != PVRSRV_OK) @@ -410,21 +447,21 @@ int PVRSRVDeviceResume(PVRSRV_DEVICE_NODE *psDeviceNode) } /**************************************************************************/ /*! -@Function PVRSRVDeviceOpen -@Description Common device open. +@Function PVRSRVDeviceServicesOpen +@Description Services device open. @Input psDeviceNode The device node representing the device being opened by a user mode process @Input psDRMFile The DRM file data that backs the file handle returned to the user mode process @Return int 0 on success and a Linux error code otherwise */ /***************************************************************************/ -int PVRSRVDeviceOpen(PVRSRV_DEVICE_NODE *psDeviceNode, - struct drm_file *psDRMFile) +int PVRSRVDeviceServicesOpen(PVRSRV_DEVICE_NODE *psDeviceNode, + struct drm_file *psDRMFile) { static DEFINE_MUTEX(sDeviceInitMutex); PVRSRV_DATA *psPVRSRVData = PVRSRVGetPVRSRVData(); ENV_CONNECTION_PRIVATE_DATA sPrivData; - void *pvConnectionData; + PVRSRV_CONNECTION_PRIV *psConnectionPriv; PVRSRV_ERROR eError; int iErr = 0; @@ -449,6 +486,23 @@ int PVRSRVDeviceOpen(PVRSRV_DEVICE_NODE *psDeviceNode, goto out; } + if (psDRMFile->driver_priv == NULL) + { + /* Allocate psConnectionPriv (stores private data and release pfn under driver_priv) */ + psConnectionPriv = kzalloc(sizeof(*psConnectionPriv), GFP_KERNEL); + if (!psConnectionPriv) + { + PVR_DPF((PVR_DBG_ERROR, "%s: No memory to allocate driver_priv data", __func__)); + iErr = -ENOMEM; + mutex_unlock(&sDeviceInitMutex); + goto fail_alloc_connection_priv; + } + } + else + { + psConnectionPriv = (PVRSRV_CONNECTION_PRIV*)psDRMFile->driver_priv; + } + if (psDeviceNode->eDevState == PVRSRV_DEVICE_STATE_INIT) { eError = PVRSRVCommonDeviceInitialise(psDeviceNode); @@ -458,7 +512,7 @@ int PVRSRVDeviceOpen(PVRSRV_DEVICE_NODE *psDeviceNode, __func__, PVRSRVGetErrorString(eError))); iErr = -ENODEV; mutex_unlock(&sDeviceInitMutex); - goto out; + goto fail_device_init; } #if defined(SUPPORT_RGX) @@ -474,24 +528,125 @@ int PVRSRVDeviceOpen(PVRSRV_DEVICE_NODE *psDeviceNode, * OSConnectionPrivateDataInit function where we can save it so * we can back reference the file structure from its connection */ - eError = PVRSRVCommonConnectionConnect(&pvConnectionData, (void *) &sPrivData); + eError = PVRSRVCommonConnectionConnect(&psConnectionPriv->pvConnectionData, + (void *)&sPrivData); if (eError != PVRSRV_OK) { iErr = -ENOMEM; + goto fail_connect; + } + +#if (PVRSRV_DEVICE_INIT_MODE == PVRSRV_LINUX_DEV_INIT_ON_CONNECT) + psConnectionPriv->pfDeviceRelease = PVRSRVCommonConnectionDisconnect; +#endif + psDRMFile->driver_priv = (void*)psConnectionPriv; + goto out; + +fail_connect: +fail_device_init: + kfree(psConnectionPriv); +fail_alloc_connection_priv: +out: + return iErr; +} + +/**************************************************************************/ /*! +@Function PVRSRVDeviceSyncOpen +@Description Sync device open. +@Input psDeviceNode The device node representing the device being + opened by a user mode process +@Input psDRMFile The DRM file data that backs the file handle + returned to the user mode process +@Return int 0 on success and a Linux error code otherwise +*/ /***************************************************************************/ +static int PVRSRVDeviceSyncOpen(PVRSRV_DEVICE_NODE *psDeviceNode, + struct drm_file *psDRMFile) +{ + PVRSRV_DATA *psPVRSRVData = PVRSRVGetPVRSRVData(); + CONNECTION_DATA *psConnection = NULL; + ENV_CONNECTION_PRIVATE_DATA sPrivData; + PVRSRV_CONNECTION_PRIV *psConnectionPriv; + PVRSRV_ERROR eError; + int iErr = 0; + + if (!psPVRSRVData) + { + PVR_DPF((PVR_DBG_ERROR, "%s: No device data", __func__)); + iErr = -ENODEV; goto out; } + if (psDRMFile->driver_priv == NULL) + { + /* Allocate psConnectionPriv (stores private data and release pfn under driver_priv) */ + psConnectionPriv = kzalloc(sizeof(*psConnectionPriv), GFP_KERNEL); + if (!psConnectionPriv) + { + PVR_DPF((PVR_DBG_ERROR, "%s: No memory to allocate driver_priv data", __func__)); + iErr = -ENOMEM; + goto out; + } + } + else + { + psConnectionPriv = (PVRSRV_CONNECTION_PRIV*)psDRMFile->driver_priv; + } + + /* Allocate connection data area, no stats since process not registered yet */ + psConnection = kzalloc(sizeof(*psConnection), GFP_KERNEL); + if (!psConnection) + { + PVR_DPF((PVR_DBG_ERROR, "%s: No memory to allocate connection data", __func__)); + iErr = -ENOMEM; + goto fail_alloc_connection; + } +#if (PVRSRV_DEVICE_INIT_MODE == PVRSRV_LINUX_DEV_INIT_ON_CONNECT) + psConnectionPriv->pvConnectionData = (void*)psConnection; +#else + psConnectionPriv->pvSyncConnectionData = (void*)psConnection; +#endif + + sPrivData.psDevNode = psDeviceNode; + + /* Call environment specific connection data init function */ + eError = OSConnectionPrivateDataInit(&psConnection->hOsPrivateData, &sPrivData); + if (eError != PVRSRV_OK) + { + PVR_DPF((PVR_DBG_ERROR, "%s: OSConnectionPrivateDataInit() failed (%s)", + __func__, PVRSRVGetErrorString(eError))); + goto fail_private_data_init; + } + #if defined(SUPPORT_NATIVE_FENCE_SYNC) && !defined(USE_PVRSYNC_DEVNODE) - iErr = pvr_sync_open(pvConnectionData, psDRMFile); +#if (PVRSRV_DEVICE_INIT_MODE == PVRSRV_LINUX_DEV_INIT_ON_CONNECT) + iErr = pvr_sync_open(psConnectionPriv->pvConnectionData, psDRMFile); +#else + iErr = pvr_sync_open(psConnectionPriv->pvSyncConnectionData, psDRMFile); +#endif if (iErr) { - PVRSRVCommonConnectionDisconnect(pvConnectionData); - goto out; + PVR_DPF((PVR_DBG_ERROR, "%s: pvr_sync_open() failed(%d)", + __func__, iErr)); + goto fail_pvr_sync_open; } #endif - psDRMFile->driver_priv = pvConnectionData; +#if defined(SUPPORT_NATIVE_FENCE_SYNC) && !defined(USE_PVRSYNC_DEVNODE) +#if (PVRSRV_DEVICE_INIT_MODE == PVRSRV_LINUX_DEV_INIT_ON_CONNECT) + psConnectionPriv->pfDeviceRelease = pvr_sync_close; +#endif +#endif + psDRMFile->driver_priv = psConnectionPriv; + goto out; +#if defined(SUPPORT_NATIVE_FENCE_SYNC) && !defined(USE_PVRSYNC_DEVNODE) +fail_pvr_sync_open: + OSConnectionPrivateDataDeInit(psConnection->hOsPrivateData); +#endif +fail_private_data_init: + kfree(psConnection); +fail_alloc_connection: + kfree(psConnectionPriv); out: return iErr; } @@ -505,18 +660,63 @@ out: @Return void */ /***************************************************************************/ void PVRSRVDeviceRelease(PVRSRV_DEVICE_NODE *psDeviceNode, - struct drm_file *psDRMFile) + struct drm_file *psDRMFile) { - void *pvConnectionData = psDRMFile->driver_priv; - PVR_UNREFERENCED_PARAMETER(psDeviceNode); - psDRMFile->driver_priv = NULL; - if (pvConnectionData) + if (psDRMFile->driver_priv) { + PVRSRV_CONNECTION_PRIV *psConnectionPriv = (PVRSRV_CONNECTION_PRIV*)psDRMFile->driver_priv; + + if (psConnectionPriv->pvConnectionData) + { +#if (PVRSRV_DEVICE_INIT_MODE == PVRSRV_LINUX_DEV_INIT_ON_CONNECT) + if (psConnectionPriv->pfDeviceRelease) + { + psConnectionPriv->pfDeviceRelease(psConnectionPriv->pvConnectionData); + } +#else + if (psConnectionPriv->pvConnectionData) + PVRSRVCommonConnectionDisconnect(psConnectionPriv->pvConnectionData); + #if defined(SUPPORT_NATIVE_FENCE_SYNC) && !defined(USE_PVRSYNC_DEVNODE) - pvr_sync_close(pvConnectionData); + if (psConnectionPriv->pvSyncConnectionData) + pvr_sync_close(psConnectionPriv->pvSyncConnectionData); #endif - PVRSRVCommonConnectionDisconnect(pvConnectionData); +#endif + } + + kfree(psDRMFile->driver_priv); + psDRMFile->driver_priv = NULL; } } + +int +drm_pvr_srvkm_init(struct drm_device *dev, void *arg, struct drm_file *psDRMFile) +{ + struct drm_pvr_srvkm_init_data *data = arg; + struct pvr_drm_private *priv = dev->dev_private; + int iErr = 0; + + switch (data->init_module) + { + case PVR_SRVKM_SYNC_INIT: + { + iErr = PVRSRVDeviceSyncOpen(priv->dev_node, psDRMFile); + break; + } + case PVR_SRVKM_SERVICES_INIT: + { + iErr = PVRSRVDeviceServicesOpen(priv->dev_node, psDRMFile); + break; + } + default: + { + PVR_DPF((PVR_DBG_ERROR, "%s: invalid init_module (%d)", + __func__, data->init_module)); + iErr = -EINVAL; + } + } + + return iErr; +} diff --git a/drivers/gpu/drm/img-rogue/module_common.h b/drivers/gpu/drm/img-rogue/module_common.h index 1b2ffe19f..7317a0a79 100644 --- a/drivers/gpu/drm/img-rogue/module_common.h +++ b/drivers/gpu/drm/img-rogue/module_common.h @@ -43,11 +43,43 @@ CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. #ifndef MODULE_COMMON_H #define MODULE_COMMON_H +#include "pvr_drm.h" + /* DRVNAME is the name we use to register our driver. */ #define DRVNAME PVR_LDM_DRIVER_REGISTRATION_NAME struct _PVRSRV_DEVICE_NODE_; struct drm_file; +struct drm_device; + +/* psDRMFile->driver_priv will point to a PVRSV_CONNECTION_PRIV + * struct, which will contain a ptr to the CONNECTION_DATA and + * a pfn to the release function (which will differ depending + * on whether the connection is to Sync or Services). + */ +typedef void (*PFN_PVRSRV_DEV_RELEASE)(void *pvData); +typedef struct +{ + /* pvConnectionData is used to hold Services connection data + * for all PVRSRV_DEVICE_INIT_MODE options. + */ + void *pvConnectionData; + + /* pfDeviceRelease is used to indicate the release function + * to be called when PVRSRV_DEVICE_INIT_MODE is PVRSRV_LINUX_DEV_INIT_ON_CONNECT, + * as we can then have one connections made (either for Services or Sync) per + * psDRMFile, and need to know which type of connection is being released + * (as the ioctl release call is common for both). + */ + PFN_PVRSRV_DEV_RELEASE pfDeviceRelease; + + /* pvSyncConnectionData is used to hold Sync connection data + * when PVRSRV_DEVICE_INIT_MODE is not PVRSRV_LINUX_DEV_INIT_ON_CONNECT, + * as we can then have two connections made (for Services and Sync) to + * the same psDRMFile. + */ + void *pvSyncConnectionData; +} PVRSRV_CONNECTION_PRIV; int PVRSRVDriverInit(void); void PVRSRVDriverDeinit(void); @@ -59,9 +91,11 @@ void PVRSRVDeviceShutdown(struct _PVRSRV_DEVICE_NODE_ *psDeviceNode); int PVRSRVDeviceSuspend(struct _PVRSRV_DEVICE_NODE_ *psDeviceNode); int PVRSRVDeviceResume(struct _PVRSRV_DEVICE_NODE_ *psDeviceNode); -int PVRSRVDeviceOpen(struct _PVRSRV_DEVICE_NODE_ *psDeviceNode, - struct drm_file *psDRMFile); +int PVRSRVDeviceServicesOpen(struct _PVRSRV_DEVICE_NODE_ *psDeviceNode, + struct drm_file *psDRMFile); void PVRSRVDeviceRelease(struct _PVRSRV_DEVICE_NODE_ *psDeviceNode, - struct drm_file *psDRMFile); + struct drm_file *psDRMFile); +int drm_pvr_srvkm_init(struct drm_device *dev, + void *arg, struct drm_file *psDRMFile); #endif /* MODULE_COMMON_H */ diff --git a/drivers/gpu/drm/img-rogue/osconnection_server.h b/drivers/gpu/drm/img-rogue/osconnection_server.h index 7ce84b088..28a6dd382 100644 --- a/drivers/gpu/drm/img-rogue/osconnection_server.h +++ b/drivers/gpu/drm/img-rogue/osconnection_server.h @@ -47,7 +47,9 @@ CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. #include "handle.h" #include "osfunc.h" +/*! Function not implemented definition. */ #define OSCONNECTION_SERVER_NOT_IMPLEMENTED 0 +/*! Assert used for OSCONNECTION_SERVER_NOT_IMPLEMENTED. */ #define OSCONNECTION_SERVER_NOT_IMPLEMENTED_ASSERT() PVR_ASSERT(OSCONNECTION_SERVER_NOT_IMPLEMENTED) #if defined(__linux__) || defined(__QNXNTO__) || defined(INTEGRITY_OS) diff --git a/drivers/gpu/drm/img-rogue/osdi_impl.h b/drivers/gpu/drm/img-rogue/osdi_impl.h index c52a6d987..aa39814ef 100644 --- a/drivers/gpu/drm/img-rogue/osdi_impl.h +++ b/drivers/gpu/drm/img-rogue/osdi_impl.h @@ -52,6 +52,19 @@ CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. * implementation handles. */ typedef struct OSDI_IMPL_ENTRY_CB { + /*! @Function pfnWrite + * + * @Description + * Writes the binary data of the DI entry to the output sync, whatever that + * may be for the DI implementation. + * + * @Input pvNativeHandle native implementation handle + * @Input pvData data + * @Input uiSize pvData length + */ + void (*pfnWrite)(void *pvNativeHandle, const void *pvData, + IMG_UINT32 uiSize); + /*! @Function pfnVPrintf * * @Description diff --git a/drivers/gpu/drm/img-rogue/osfunc.c b/drivers/gpu/drm/img-rogue/osfunc.c index d2b5628c7..4c509adb4 100644 --- a/drivers/gpu/drm/img-rogue/osfunc.c +++ b/drivers/gpu/drm/img-rogue/osfunc.c @@ -172,10 +172,11 @@ void OSThreadDumpInfo(DUMPDEBUG_PRINTF_FUNC* pfnDumpDebugPrintf, } } -PVRSRV_ERROR OSPhyContigPagesAlloc(PVRSRV_DEVICE_NODE *psDevNode, size_t uiSize, +PVRSRV_ERROR OSPhyContigPagesAlloc(PHYS_HEAP *psPhysHeap, size_t uiSize, PG_HANDLE *psMemHandle, IMG_DEV_PHYADDR *psDevPAddr, IMG_PID uiPid) { + PVRSRV_DEVICE_NODE *psDevNode = PhysHeapDeviceNode(psPhysHeap); struct device *psDev = psDevNode->psDevConfig->pvOSDevice; IMG_CPU_PHYADDR sCpuPAddr; struct page *psPage; @@ -226,7 +227,7 @@ PVRSRV_ERROR OSPhyContigPagesAlloc(PVRSRV_DEVICE_NODE *psDevNode, size_t uiSize, * Even when more pages are allocated as base MMU object we still need one single physical address because * they are physically contiguous. */ - PhysHeapCpuPAddrToDevPAddr(psDevNode->apsPhysHeap[PVRSRV_PHYS_HEAP_CPU_LOCAL], 1, psDevPAddr, &sCpuPAddr); + PhysHeapCpuPAddrToDevPAddr(psPhysHeap, 1, psDevPAddr, &sCpuPAddr); #if defined(PVRSRV_ENABLE_PROCESS_STATS) #if !defined(PVRSRV_ENABLE_MEMORY_STATS) @@ -250,11 +251,13 @@ PVRSRV_ERROR OSPhyContigPagesAlloc(PVRSRV_DEVICE_NODE *psDevNode, size_t uiSize, return PVRSRV_OK; } -void OSPhyContigPagesFree(PVRSRV_DEVICE_NODE *psDevNode, PG_HANDLE *psMemHandle) +void OSPhyContigPagesFree(PHYS_HEAP *psPhysHeap, PG_HANDLE *psMemHandle) { struct page *psPage = (struct page*) psMemHandle->u.pvHandle; IMG_UINT32 uiSize, uiPageCount=0, ui32Order; + PVR_UNREFERENCED_PARAMETER(psPhysHeap); + ui32Order = psMemHandle->uiOrder; uiPageCount = (1 << ui32Order); uiSize = (uiPageCount * PAGE_SIZE); @@ -274,7 +277,7 @@ void OSPhyContigPagesFree(PVRSRV_DEVICE_NODE *psDevNode, PG_HANDLE *psMemHandle) psMemHandle->uiOrder = 0; } -PVRSRV_ERROR OSPhyContigPagesMap(PVRSRV_DEVICE_NODE *psDevNode, PG_HANDLE *psMemHandle, +PVRSRV_ERROR OSPhyContigPagesMap(PHYS_HEAP *psPhysHeap, PG_HANDLE *psMemHandle, size_t uiSize, IMG_DEV_PHYADDR *psDevPAddr, void **pvPtr) { @@ -285,7 +288,7 @@ PVRSRV_ERROR OSPhyContigPagesMap(PVRSRV_DEVICE_NODE *psDevNode, PG_HANDLE *psMem PVR_UNREFERENCED_PARAMETER(actualSize); /* If we don't take an #ifdef path */ PVR_UNREFERENCED_PARAMETER(uiSize); - PVR_UNREFERENCED_PARAMETER(psDevNode); + PVR_UNREFERENCED_PARAMETER(psPhysHeap); #if defined(PVRSRV_ENABLE_PROCESS_STATS) #if !defined(PVRSRV_ENABLE_MEMORY_STATS) @@ -309,7 +312,7 @@ PVRSRV_ERROR OSPhyContigPagesMap(PVRSRV_DEVICE_NODE *psDevNode, PG_HANDLE *psMem return PVRSRV_OK; } -void OSPhyContigPagesUnmap(PVRSRV_DEVICE_NODE *psDevNode, PG_HANDLE *psMemHandle, void *pvPtr) +void OSPhyContigPagesUnmap(PHYS_HEAP *psPhysHeap, PG_HANDLE *psMemHandle, void *pvPtr) { #if defined(PVRSRV_ENABLE_PROCESS_STATS) #if !defined(PVRSRV_ENABLE_MEMORY_STATS) @@ -324,17 +327,18 @@ void OSPhyContigPagesUnmap(PVRSRV_DEVICE_NODE *psDevNode, PG_HANDLE *psMemHandle #endif #endif - PVR_UNREFERENCED_PARAMETER(psDevNode); + PVR_UNREFERENCED_PARAMETER(psPhysHeap); PVR_UNREFERENCED_PARAMETER(pvPtr); kunmap((struct page*) psMemHandle->u.pvHandle); } -PVRSRV_ERROR OSPhyContigPagesClean(PVRSRV_DEVICE_NODE *psDevNode, +PVRSRV_ERROR OSPhyContigPagesClean(PHYS_HEAP *psPhysHeap, PG_HANDLE *psMemHandle, IMG_UINT32 uiOffset, IMG_UINT32 uiLength) { + PVRSRV_DEVICE_NODE *psDevNode = PhysHeapDeviceNode(psPhysHeap); PVRSRV_ERROR eError = PVRSRV_OK; struct page* psPage = (struct page*) psMemHandle->u.pvHandle; @@ -570,9 +574,9 @@ static PVRSRV_ERROR _NativeSyncInit(void) static void _NativeSyncDeinit(void) { - if (gpFenceStatusWq) { - destroy_workqueue(gpFenceStatusWq); - } + if (gpFenceStatusWq) { + destroy_workqueue(gpFenceStatusWq); + } } struct workqueue_struct *NativeSyncGetFenceStatusWq(void) @@ -618,6 +622,32 @@ void OSReleaseThreadQuanta(void) schedule(); } +void OSMemoryBarrier(volatile void *hReadback) +{ + mb(); + + if (hReadback) + { + /* Force a read-back to memory to avoid posted writes on certain buses + * e.g. PCI(E) + */ + (void) OSReadDeviceMem32(hReadback); + } +} + +void OSWriteMemoryBarrier(volatile void *hReadback) +{ + wmb(); + + if (hReadback) + { + /* Force a read-back to memory to avoid posted writes on certain buses + * e.g. PCI(E) + */ + (void) OSReadDeviceMem32(hReadback); + } +} + /* Not matching/aligning this API to the Clockus() API above to avoid necessary * multiplication/division operations in calling code. */ @@ -2425,7 +2455,7 @@ PVRSRV_ERROR OSDmaPrepareTransferSparse(PVRSRV_DEVICE_NODE *psDevNode, } } - if ((unsigned long long)pvNextAddress + transfer_size > PAGE_ALIGN((unsigned long long)pvNextAddress)) + if (((unsigned long long)pvNextAddress & (ui32PageSize - 1)) + transfer_size > ui32PageSize) { num_pages = 2; } diff --git a/drivers/gpu/drm/img-rogue/osfunc.h b/drivers/gpu/drm/img-rogue/osfunc.h index bf1202a09..93a94c40c 100644 --- a/drivers/gpu/drm/img-rogue/osfunc.h +++ b/drivers/gpu/drm/img-rogue/osfunc.h @@ -644,8 +644,7 @@ IMG_INT OSMemCmp(void *pvBufA, void *pvBufB, size_t uiLen); If allocations made by this function are CPU cached then OSPhyContigPagesClean has to be implemented to write the cached data to memory. -@Input psDevNode the device for which the allocation is - required +@Input psPhysHeap the heap from which to allocate @Input uiSize the size of the required allocation (in bytes) @Output psMemHandle a returned handle to be used to refer to this allocation @@ -654,24 +653,24 @@ IMG_INT OSMemCmp(void *pvBufA, void *pvBufB, size_t uiLen); be associated with @Return PVRSRV_OK on success, a failure code otherwise. *****************************************************************************/ -PVRSRV_ERROR OSPhyContigPagesAlloc(PVRSRV_DEVICE_NODE *psDevNode, size_t uiSize, +PVRSRV_ERROR OSPhyContigPagesAlloc(PHYS_HEAP *psPhysHeap, size_t uiSize, PG_HANDLE *psMemHandle, IMG_DEV_PHYADDR *psDevPAddr, IMG_PID uiPid); /*************************************************************************/ /*! @Function OSPhyContigPagesFree @Description Frees a previous allocation of contiguous physical pages -@Input psDevNode the device on which the allocation was made +@Input psPhysHeap the heap from which to allocate @Input psMemHandle the handle of the allocation to be freed @Return None. *****************************************************************************/ -void OSPhyContigPagesFree(PVRSRV_DEVICE_NODE *psDevNode, PG_HANDLE *psMemHandle); +void OSPhyContigPagesFree(PHYS_HEAP *psPhysHeap, PG_HANDLE *psMemHandle); /*************************************************************************/ /*! @Function OSPhyContigPagesMap @Description Maps the specified allocation of contiguous physical pages to a kernel virtual address -@Input psDevNode the device on which the allocation was made +@Input psPhysHeap the heap from which to allocate @Input psMemHandle the handle of the allocation to be mapped @Input uiSize the size of the allocation (in bytes) @Input psDevPAddr the physical address of the allocation @@ -679,7 +678,7 @@ void OSPhyContigPagesFree(PVRSRV_DEVICE_NODE *psDevNode, PG_HANDLE *psMemHandle) allocation is now mapped @Return PVRSRV_OK on success, a failure code otherwise. *****************************************************************************/ -PVRSRV_ERROR OSPhyContigPagesMap(PVRSRV_DEVICE_NODE *psDevNode, PG_HANDLE *psMemHandle, +PVRSRV_ERROR OSPhyContigPagesMap(PHYS_HEAP *psPhysHeap, PG_HANDLE *psMemHandle, size_t uiSize, IMG_DEV_PHYADDR *psDevPAddr, void **pvPtr); @@ -687,13 +686,13 @@ PVRSRV_ERROR OSPhyContigPagesMap(PVRSRV_DEVICE_NODE *psDevNode, PG_HANDLE *psMem @Function OSPhyContigPagesUnmap @Description Unmaps the kernel mapping for the specified allocation of contiguous physical pages -@Input psDevNode the device on which the allocation was made +@Input psPhysHeap the heap from which to allocate @Input psMemHandle the handle of the allocation to be unmapped @Input pvPtr the virtual kernel address to which the allocation is currently mapped @Return None. *****************************************************************************/ -void OSPhyContigPagesUnmap(PVRSRV_DEVICE_NODE *psDevNode, PG_HANDLE *psMemHandle, void *pvPtr); +void OSPhyContigPagesUnmap(PHYS_HEAP *psPhysHeap, PG_HANDLE *psMemHandle, void *pvPtr); /*************************************************************************/ /*! @Function OSPhyContigPagesClean @@ -704,14 +703,14 @@ void OSPhyContigPagesUnmap(PVRSRV_DEVICE_NODE *psDevNode, PG_HANDLE *psMemHandle (i.e. flush). If allocations returned by OSPhyContigPagesAlloc are always uncached this can be implemented as nop. -@Input psDevNode device on which the allocation was made +@Input psPhysHeap the heap from which to allocate @Input psMemHandle the handle of the allocation to be flushed @Input uiOffset the offset in bytes from the start of the allocation from where to start flushing @Input uiLength the amount to flush from the offset in bytes @Return PVRSRV_OK on success, a failure code otherwise. *****************************************************************************/ -PVRSRV_ERROR OSPhyContigPagesClean(PVRSRV_DEVICE_NODE *psDevNode, +PVRSRV_ERROR OSPhyContigPagesClean(PHYS_HEAP *psPhysHeap, PG_HANDLE *psMemHandle, IMG_UINT32 uiOffset, IMG_UINT32 uiLength); @@ -967,20 +966,9 @@ void OSSleepms(IMG_UINT32 ui32Timems); void OSReleaseThreadQuanta(void); #if defined(__linux__) && defined(__KERNEL__) -#define OSWriteMemoryBarrier() wmb() #define OSReadMemoryBarrier() rmb() -#define OSMemoryBarrier() mb() #else /*************************************************************************/ /*! -@Function OSWriteMemoryBarrier -@Description Insert a write memory barrier. - The write memory barrier guarantees that all store operations - (writes) specified before the barrier will appear to happen - before all of the store operations specified after the barrier. -@Return PVRSRV_OK on success, a failure code otherwise. -*/ /**************************************************************************/ -void OSWriteMemoryBarrier(void); -/*************************************************************************/ /*! @Function OSReadMemoryBarrier @Description Insert a read memory barrier. The read memory barrier guarantees that all load (read) @@ -988,6 +976,7 @@ void OSWriteMemoryBarrier(void); before all of the load operations specified after the barrier. */ /**************************************************************************/ void OSReadMemoryBarrier(void); +#endif /*************************************************************************/ /*! @Function OSMemoryBarrier @Description Insert a read/write memory barrier. @@ -995,10 +984,24 @@ void OSReadMemoryBarrier(void); (read) and all store (write) operations specified before the barrier will appear to happen before all of the load/store operations specified after the barrier. +@Input hReadback Optional pointer to memory to read back, can be + useful for flushing queues in bus interconnects to RAM before + device (GPU) access the shared memory. @Return None. */ /**************************************************************************/ -void OSMemoryBarrier(void); -#endif +void OSMemoryBarrier(volatile void *hReadback); +/*************************************************************************/ /*! +@Function OSWriteMemoryBarrier +@Description Insert a write memory barrier. + The write memory barrier guarantees that all store operations + (writes) specified before the barrier will appear to happen + before all of the store operations specified after the barrier. +@Input hReadback Optional pointer to memory to read back, can be + useful for flushing queues in bus interconnects to RAM before + device (GPU) access the shared memory. +@Return None. +*/ /**************************************************************************/ +void OSWriteMemoryBarrier(volatile void *hReadback); /*************************************************************************/ /*! */ /**************************************************************************/ @@ -1015,7 +1018,7 @@ void OSMemoryBarrier(void); #define OSWriteDeviceMem32WithWMB(addr, val) \ do { \ *((volatile IMG_UINT32 __force *)((void*)addr)) = (IMG_UINT32)(val); \ - OSWriteMemoryBarrier(); \ + OSWriteMemoryBarrier(addr); \ } while (0) #if defined(__linux__) && defined(__KERNEL__) && !defined(NO_HARDWARE) @@ -1051,14 +1054,14 @@ void OSMemoryBarrier(void); #elif defined(NO_HARDWARE) /* OSReadHWReg operations skipped in no hardware builds */ - #define OSReadHWReg8(addr, off) (0x4eU) - #define OSReadHWReg16(addr, off) (0x3a4eU) - #define OSReadHWReg32(addr, off) (0x30f73a4eU) + #define OSReadHWReg8(addr, off) ((void)(addr), 0x4eU) + #define OSReadHWReg16(addr, off) ((void)(addr), 0x3a4eU) + #define OSReadHWReg32(addr, off) ((void)(addr), 0x30f73a4eU) #if defined(__QNXNTO__) && __SIZEOF_LONG__ == 8 /* This is needed for 64-bit QNX builds where the size of a long is 64 bits */ - #define OSReadHWReg64(addr, off) (0x5b376c9d30f73a4eUL) + #define OSReadHWReg64(addr, off) ((void)(addr), 0x5b376c9d30f73a4eUL) #else - #define OSReadHWReg64(addr, off) (0x5b376c9d30f73a4eULL) + #define OSReadHWReg64(addr, off) ((void)(addr), 0x5b376c9d30f73a4eULL) #endif #define OSWriteHWReg8(addr, off, val) @@ -1350,9 +1353,8 @@ PVRSRV_ERROR OSPlatformBridgeInit(void); @Description Called during device destruction to allow the OS port to deregister its OS specific bridges and clean up other related resources. -@Return PVRSRV_OK on success, a failure code otherwise. */ /**************************************************************************/ -PVRSRV_ERROR OSPlatformBridgeDeInit(void); +void OSPlatformBridgeDeInit(void); /*************************************************************************/ /*! @Function PVRSRVToNativeError @@ -1400,7 +1402,9 @@ void OSWRLockReleaseWrite(POSWR_LOCK psLock); #else +/*! Function not implemented definition. */ #define OSFUNC_NOT_IMPLEMENTED 0 +/*! Assert used for OSFUNC_NOT_IMPLEMENTED. */ #define OSFUNC_NOT_IMPLEMENTED_ASSERT() PVR_ASSERT(OSFUNC_NOT_IMPLEMENTED) /*************************************************************************/ /*! diff --git a/drivers/gpu/drm/img-rogue/osfunc_arm64.c b/drivers/gpu/drm/img-rogue/osfunc_arm64.c index d2a8329e3..68d1285b0 100644 --- a/drivers/gpu/drm/img-rogue/osfunc_arm64.c +++ b/drivers/gpu/drm/img-rogue/osfunc_arm64.c @@ -52,6 +52,8 @@ CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. #include "osfunc.h" #include "pvr_debug.h" +#include "kernel_compatibility.h" + #if defined(CONFIG_OUTER_CACHE) /* If you encounter a 64-bit ARM system with an outer cache, you'll need * to add the necessary code to manage that cache. See osfunc_arm.c @@ -63,14 +65,14 @@ CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. static inline void begin_user_mode_access(void) { #if defined(CONFIG_ARM64) && defined(CONFIG_ARM64_SW_TTBR0_PAN) - uaccess_enable(); + uaccess_enable_privileged(); #endif } static inline void end_user_mode_access(void) { #if defined(CONFIG_ARM64) && defined(CONFIG_ARM64_SW_TTBR0_PAN) - uaccess_disable(); + uaccess_disable_privileged(); #endif } diff --git a/drivers/gpu/drm/img-rogue/osfunc_common.h b/drivers/gpu/drm/img-rogue/osfunc_common.h index f209bede8..539ef2c04 100644 --- a/drivers/gpu/drm/img-rogue/osfunc_common.h +++ b/drivers/gpu/drm/img-rogue/osfunc_common.h @@ -154,7 +154,14 @@ size_t StringLCopy(IMG_CHAR *pszDest, const IMG_CHAR *pszSrc, size_t uDataSize); @Input c the number of bytes to be set to the given value @Return Pointer to the destination memory. */ /**************************************************************************/ -#define OSDeviceMemSet(a,b,c) memset((a), (b), (c)) +#define OSDeviceMemSet(a,b,c) \ + do { \ + if ((c) != 0) \ + { \ + (void) memset((a), (b), (c)); \ + (void) *(volatile IMG_UINT32*)((void*)(a)); \ + } \ + } while (false) /**************************************************************************/ /*! @Function OSDeviceMemCopy @@ -167,7 +174,14 @@ size_t StringLCopy(IMG_CHAR *pszDest, const IMG_CHAR *pszSrc, size_t uDataSize); @Input c the number of bytes to be copied @Return Pointer to the destination memory. */ /**************************************************************************/ -#define OSDeviceMemCopy(a,b,c) memcpy((a), (b), (c)) +#define OSDeviceMemCopy(a,b,c) \ + do { \ + if ((c) != 0) \ + { \ + memcpy((a), (b), (c)); \ + (void) *(volatile IMG_UINT32*)((void*)(a)); \ + } \ + } while (false) #endif /* (defined(__arm64__) || defined(__aarch64__) || defined(PVRSRV_DEVMEM_TEST_SAFE_MEMSETCPY)) */ @@ -181,7 +195,7 @@ size_t StringLCopy(IMG_CHAR *pszDest, const IMG_CHAR *pszSrc, size_t uDataSize); @Input c the number of bytes to be set to the given value @Return Pointer to the destination memory. */ /**************************************************************************/ -#define OSCachedMemSet(a,b,c) memset((a), (b), (c)) +#define OSCachedMemSet(a,b,c) (void) memset((a), (b), (c)) /**************************************************************************/ /*! @Function OSCachedMemCopy @@ -210,12 +224,22 @@ size_t StringLCopy(IMG_CHAR *pszDest, const IMG_CHAR *pszSrc, size_t uDataSize); @Input c the number of bytes to be set to the given value @Return Pointer to the destination memory. */ /**************************************************************************/ +#if !defined(SERVICES_SC) +#define OSCachedMemSetWMB(a,b,c) \ + do { \ + if ((c) != 0) \ + { \ + (void) memset((a), (b), (c)); \ + OSWriteMemoryBarrier(a); \ + } \ + } while (false) +#else #define OSCachedMemSetWMB(a,b,c) \ do { \ (void) memset((a), (b), (c)); \ OSWriteMemoryBarrier(); \ - } while (0) - + } while (false) +#endif /* !defined(SERVICES_SC) */ /**************************************************************************/ /*! @Function OSCachedMemCopy @Description Copy values from one area of memory, to another, when both @@ -228,12 +252,22 @@ size_t StringLCopy(IMG_CHAR *pszDest, const IMG_CHAR *pszSrc, size_t uDataSize); @Input c the number of bytes to be copied @Return Pointer to the destination memory. */ /**************************************************************************/ +#if !defined(SERVICES_SC) +#define OSCachedMemCopyWMB(a,b,c) \ + do { \ + if ((c) != 0) \ + { \ + (void) memcpy((a), (b), (c)); \ + OSWriteMemoryBarrier(a); \ + } \ + } while (false) +#else #define OSCachedMemCopyWMB(a,b,c) \ do { \ (void) memcpy((a), (b), (c)); \ OSWriteMemoryBarrier(); \ - } while (0) - + } while (false) +#endif /* !defined(SERVICES_SC) */ #endif /* defined(__KERNEL__) */ /**************************************************************************/ /*! diff --git a/drivers/gpu/drm/img-rogue/oskm_apphint.h b/drivers/gpu/drm/img-rogue/oskm_apphint.h index abed95502..78d40407d 100644 --- a/drivers/gpu/drm/img-rogue/oskm_apphint.h +++ b/drivers/gpu/drm/img-rogue/oskm_apphint.h @@ -49,7 +49,7 @@ CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. #if !defined(OSKM_APPHINT_H) #define OSKM_APPHINT_H -/* Supplied to os_get_km_apphint_XXX() functions when the param/AppHint is +/*! Supplied to os_get_km_apphint_XXX() functions when the param/AppHint is * applicable to all devices and not a specific device. Typically used * for server-wide build and module AppHints. */ diff --git a/drivers/gpu/drm/img-rogue/osmmap.h b/drivers/gpu/drm/img-rogue/osmmap.h index 1b566e0e3..40a509d19 100644 --- a/drivers/gpu/drm/img-rogue/osmmap.h +++ b/drivers/gpu/drm/img-rogue/osmmap.h @@ -74,7 +74,6 @@ CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. be done (read-only, etc). These may not be honoured if the PMR does not permit them. -@Input uiPMRLength The size of the PMR. @Output phOSMMapPrivDataOut Returned private data. @Output ppvMappingAddressOut The returned mapping. @Output puiMappingLengthOut The size of the returned mapping. diff --git a/drivers/gpu/drm/img-rogue/pdump_km.h b/drivers/gpu/drm/img-rogue/pdump_km.h index f085d92c9..b9cb5f654 100644 --- a/drivers/gpu/drm/img-rogue/pdump_km.h +++ b/drivers/gpu/drm/img-rogue/pdump_km.h @@ -45,8 +45,17 @@ CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. #define PDUMP_KM_H #if defined(PDUMP) -#include -#endif + #if defined(__linux__) + #include + #if (LINUX_VERSION_CODE >= KERNEL_VERSION(5, 15, 0)) + #include + #else + #include + #endif /* LINUX_VERSION_CODE >= KERNEL_VERSION(5, 15, 0) */ + #else + #include + #endif /* __linux__ */ +#endif /* PDUMP */ /* services/srvkm/include/ */ #include "device.h" @@ -221,7 +230,9 @@ PVRSRV_ERROR PDumpGetFrameKM(CONNECTION_DATA *psConnection, IMG_UINT32* pui32Frame); PVRSRV_ERROR PDumpCommentKM(CONNECTION_DATA *psConnection, PVRSRV_DEVICE_NODE *psDeviceNode, - IMG_CHAR *pszComment, IMG_UINT32 ui32Flags); + IMG_UINT32 ui32CommentSize, + IMG_CHAR *pszComment, + IMG_UINT32 ui32Flags); PVRSRV_ERROR PDumpSetDefaultCaptureParamsKM(CONNECTION_DATA *psConnection, PVRSRV_DEVICE_NODE *psDeviceNode, @@ -348,19 +359,6 @@ PVRSRV_ERROR PDumpRegPolKM(PVRSRV_DEVICE_NODE *psDeviceNode, IMG_UINT32 ui32Flags, PDUMP_POLL_OPERATOR eOperator); -PVRSRV_ERROR PDumpBitmapKM(PVRSRV_DEVICE_NODE *psDeviceNode, - IMG_CHAR *pszFileName, - IMG_UINT32 ui32FileOffset, - IMG_UINT32 ui32Width, - IMG_UINT32 ui32Height, - IMG_UINT32 ui32StrideInBytes, - IMG_DEV_VIRTADDR sDevBaseAddr, - IMG_UINT32 ui32MMUContextID, - IMG_UINT32 ui32Size, - PDUMP_PIXEL_FORMAT ePixelFormat, - IMG_UINT32 ui32AddrMode, - IMG_UINT32 ui32PDumpFlags); - /**************************************************************************/ /*! @Function PDumpImageDescriptor @@ -548,8 +546,8 @@ PVRSRV_ERROR PDumpCOMCommand(PVRSRV_DEVICE_NODE *psDeviceNode, IMG_UINT32 ui32PDumpFlags, const IMG_CHAR *pszPDump); -void PDumpPowerTransitionStart(void); -void PDumpPowerTransitionEnd(void); +void PDumpPowerTransitionStart(PVRSRV_DEVICE_NODE *psDeviceNode); +void PDumpPowerTransitionEnd(PVRSRV_DEVICE_NODE *psDeviceNode); IMG_BOOL PDumpCheckFlagsWrite(PVRSRV_DEVICE_NODE *psDeviceNode, IMG_UINT32 ui32Flags); @@ -678,10 +676,8 @@ PDumpTransition(PVRSRV_DEVICE_NODE *psDeviceNode, PDUMP_TRANSITION_EVENT eEvent, IMG_UINT32 ui32PDumpFlags); -/* Check if writing to a PDump file is permitted - * (based on flags and device) - */ -IMG_BOOL PDumpIsPermitted(PVRSRV_DEVICE_NODE *psDeviceNode); +/* Check if writing to a PDump file is permitted for the given device */ +IMG_BOOL PDumpIsDevicePermitted(PVRSRV_DEVICE_NODE *psDeviceNode); /* _ui32PDumpFlags must be a variable in the local scope */ #define PDUMP_LOCK(_ui32PDumpFlags) do \ @@ -844,10 +840,13 @@ PDumpGetFrameKM(CONNECTION_DATA *psConnection, static INLINE PVRSRV_ERROR PDumpCommentKM(CONNECTION_DATA *psConnection, PVRSRV_DEVICE_NODE *psDeviceNode, - IMG_CHAR *pszComment, IMG_UINT32 ui32Flags) + IMG_UINT32 ui32CommentSize, + IMG_CHAR *pszComment, + IMG_UINT32 ui32Flags) { PVR_UNREFERENCED_PARAMETER(psConnection); PVR_UNREFERENCED_PARAMETER(psDeviceNode); + PVR_UNREFERENCED_PARAMETER(ui32CommentSize); PVR_UNREFERENCED_PARAMETER(pszComment); PVR_UNREFERENCED_PARAMETER(ui32Flags); return PVRSRV_OK; @@ -942,38 +941,6 @@ PDumpForceCaptureStopKM(CONNECTION_DATA *psConnection, return PVRSRV_OK; } -#ifdef INLINE_IS_PRAGMA -#pragma inline(PDumpBitmapKM) -#endif -static INLINE PVRSRV_ERROR -PDumpBitmapKM(PVRSRV_DEVICE_NODE *psDeviceNode, - IMG_CHAR *pszFileName, - IMG_UINT32 ui32FileOffset, - IMG_UINT32 ui32Width, - IMG_UINT32 ui32Height, - IMG_UINT32 ui32StrideInBytes, - IMG_DEV_VIRTADDR sDevBaseAddr, - IMG_UINT32 ui32MMUContextID, - IMG_UINT32 ui32Size, - PDUMP_PIXEL_FORMAT ePixelFormat, - IMG_UINT32 ui32AddrMode, - IMG_UINT32 ui32PDumpFlags) -{ - PVR_UNREFERENCED_PARAMETER(psDeviceNode); - PVR_UNREFERENCED_PARAMETER(pszFileName); - PVR_UNREFERENCED_PARAMETER(ui32FileOffset); - PVR_UNREFERENCED_PARAMETER(ui32Width); - PVR_UNREFERENCED_PARAMETER(ui32Height); - PVR_UNREFERENCED_PARAMETER(ui32StrideInBytes); - PVR_UNREFERENCED_PARAMETER(sDevBaseAddr); - PVR_UNREFERENCED_PARAMETER(ui32MMUContextID); - PVR_UNREFERENCED_PARAMETER(ui32Size); - PVR_UNREFERENCED_PARAMETER(ePixelFormat); - PVR_UNREFERENCED_PARAMETER(ui32AddrMode); - PVR_UNREFERENCED_PARAMETER(ui32PDumpFlags); - return PVRSRV_OK; -} - #ifdef INLINE_IS_PRAGMA #pragma inline(PDumpImageDescriptor) #endif diff --git a/drivers/gpu/drm/img-rogue/physheap.c b/drivers/gpu/drm/img-rogue/physheap.c index dd824ea6c..2155bcbe9 100644 --- a/drivers/gpu/drm/img-rogue/physheap.c +++ b/drivers/gpu/drm/img-rogue/physheap.c @@ -142,13 +142,141 @@ void PVRSRVGetDevicePhysHeapCount(PVRSRV_DEVICE_NODE *psDevNode, *pui32PhysHeapCount = psDevNode->ui32UserAllocHeapCount; } +static IMG_UINT32 PhysHeapOSGetPageShift(void) +{ + return (IMG_UINT32)OSGetPageShift(); +} + static PHEAP_IMPL_FUNCS _sPHEAPImplFuncs = { .pfnDestroyData = NULL, .pfnGetPMRFactoryMemStats = PhysmemGetOSRamMemStats, .pfnCreatePMR = PhysmemNewOSRamBackedPMR, + .pfnPagesAlloc = &OSPhyContigPagesAlloc, + .pfnPagesFree = &OSPhyContigPagesFree, + .pfnPagesMap = &OSPhyContigPagesMap, + .pfnPagesUnMap = &OSPhyContigPagesUnmap, + .pfnPagesClean = &OSPhyContigPagesClean, + .pfnGetPageShift = &PhysHeapOSGetPageShift, }; +/*************************************************************************/ /*! +@Function _PhysHeapDebugRequest +@Description This function is used to output debug information for a given + device's PhysHeaps. +@Input pfnDbgRequestHandle Data required by this function that is + passed through the RegisterDeviceDbgRequestNotify + function. +@Input ui32VerbLevel The maximum verbosity of the debug request. +@Input pfnDumpDebugPrintf The specified print function that should be + used to dump any debug information + (see PVRSRVDebugRequest). +@Input pvDumpDebugFile Optional file identifier to be passed to + the print function if required. +@Return void +*/ /**************************************************************************/ +static void _PhysHeapDebugRequest(PVRSRV_DBGREQ_HANDLE pfnDbgRequestHandle, + IMG_UINT32 ui32VerbLevel, + DUMPDEBUG_PRINTF_FUNC *pfnDumpDebugPrintf, + void *pvDumpDebugFile) +{ + static const IMG_CHAR *const pszTypeStrings[] = { + "UNKNOWN", + "UMA", + "LMA", + "DMA", +#if defined(SUPPORT_WRAP_EXTMEMOBJECT) + "WRAP" +#endif + }; + + PPVRSRV_DEVICE_NODE psDeviceNode = (PPVRSRV_DEVICE_NODE)pfnDbgRequestHandle; + PHYS_HEAP *psPhysHeap = NULL; + IMG_UINT64 ui64TotalSize; + IMG_UINT64 ui64FreeSize; + IMG_UINT32 i; + + PVR_LOG_RETURN_VOID_IF_FALSE(psDeviceNode != NULL, + "Phys Heap debug request failed. psDeviceNode was NULL"); + + PVR_DUMPDEBUG_LOG("------[ Device ID: %d - Phys Heaps ]------", + psDeviceNode->sDevId.i32OsDeviceID); + + for (i = 0; i < psDeviceNode->ui32RegisteredPhysHeaps; i++) + { + psPhysHeap = psDeviceNode->papsRegisteredPhysHeaps[i]; + + if (psPhysHeap->eType >= ARRAY_SIZE(pszTypeStrings)) + { + PVR_DPF((PVR_DBG_ERROR, + "PhysHeap at address %p eType is not a PHYS_HEAP_TYPE", + psPhysHeap)); + break; + } + + psPhysHeap->psImplFuncs->pfnGetPMRFactoryMemStats(psPhysHeap->pvImplData, + &ui64TotalSize, + &ui64FreeSize); + + if (psPhysHeap->eType == PHYS_HEAP_TYPE_LMA) + { + IMG_CPU_PHYADDR sCPUPAddr; + IMG_DEV_PHYADDR sGPUPAddr; + PVRSRV_ERROR eError; + + PVR_ASSERT(psPhysHeap->psImplFuncs->pfnGetCPUPAddr != NULL); + PVR_ASSERT(psPhysHeap->psImplFuncs->pfnGetDevPAddr != NULL); + + eError = psPhysHeap->psImplFuncs->pfnGetCPUPAddr(psPhysHeap->pvImplData, + &sCPUPAddr); + if (eError != PVRSRV_OK) + { + PVR_LOG_ERROR(eError, "pfnGetCPUPAddr"); + sCPUPAddr.uiAddr = IMG_CAST_TO_CPUPHYADDR_UINT(IMG_UINT64_MAX); + } + + eError = psPhysHeap->psImplFuncs->pfnGetDevPAddr(psPhysHeap->pvImplData, + &sGPUPAddr); + if (eError != PVRSRV_OK) + { + PVR_LOG_ERROR(eError, "pfnGetDevPAddr"); + sGPUPAddr.uiAddr = IMG_UINT64_MAX; + } + + PVR_DUMPDEBUG_LOG("0x%p -> Name: %s, Type: %s, " + + "CPU PA Base: " CPUPHYADDR_UINT_FMTSPEC", " + "GPU PA Base: 0x%08"IMG_UINT64_FMTSPECx", " + "Usage Flags: 0x%08x, Refs: %d, " + "Free Size: %"IMG_UINT64_FMTSPEC", " + "Total Size: %"IMG_UINT64_FMTSPEC, + psPhysHeap, + psPhysHeap->pszPDumpMemspaceName, + pszTypeStrings[psPhysHeap->eType], + CPUPHYADDR_FMTARG(sCPUPAddr.uiAddr), + sGPUPAddr.uiAddr, + psPhysHeap->ui32UsageFlags, + psPhysHeap->ui32RefCount, + ui64FreeSize, + ui64TotalSize); + } + else + { + PVR_DUMPDEBUG_LOG("0x%p -> Name: %s, Type: %s, " + "Usage Flags: 0x%08x, Refs: %d, " + "Free Size: %"IMG_UINT64_FMTSPEC", " + "Total Size: %"IMG_UINT64_FMTSPEC, + psPhysHeap, + psPhysHeap->pszPDumpMemspaceName, + pszTypeStrings[psPhysHeap->eType], + psPhysHeap->ui32UsageFlags, + psPhysHeap->ui32RefCount, + ui64FreeSize, + ui64TotalSize); + } + } +} + PVRSRV_ERROR PhysHeapCreateHeapFromConfig(PVRSRV_DEVICE_NODE *psDevNode, PHYS_HEAP_CONFIG *psConfig, @@ -181,27 +309,44 @@ PhysHeapCreateHeapFromConfig(PVRSRV_DEVICE_NODE *psDevNode, } PVRSRV_ERROR -PhysHeapCreateHeapsFromConfigs(PPVRSRV_DEVICE_NODE psDevNode, - PHYS_HEAP_CONFIG *pasConfigs, - IMG_UINT32 ui32NumConfigs, - PHYS_HEAP **papsPhysHeaps, - IMG_UINT32 *pui32NumHeaps) +PhysHeapCreateDeviceHeapsFromConfigs(PPVRSRV_DEVICE_NODE psDevNode, + PHYS_HEAP_CONFIG *pasConfigs, + IMG_UINT32 ui32NumConfigs) { IMG_UINT32 i; PVRSRV_ERROR eError; - *pui32NumHeaps = 0; + /* Register the physical memory heaps */ + psDevNode->papsRegisteredPhysHeaps = + OSAllocZMem(sizeof(*psDevNode->papsRegisteredPhysHeaps) * ui32NumConfigs); + PVR_LOG_RETURN_IF_NOMEM(psDevNode->papsRegisteredPhysHeaps, "OSAllocZMem"); + + psDevNode->ui32RegisteredPhysHeaps = 0; for (i = 0; i < ui32NumConfigs; i++) { eError = PhysHeapCreateHeapFromConfig(psDevNode, pasConfigs + i, - papsPhysHeaps + i); + psDevNode->papsRegisteredPhysHeaps + i); PVR_LOG_RETURN_IF_ERROR(eError, "PhysmemCreateHeap"); - (*pui32NumHeaps)++; + psDevNode->ui32RegisteredPhysHeaps++; } +#if defined(SUPPORT_PHYSMEM_TEST) + /* For a temporary device node there will never be a debug dump + * request targeting it */ + if (psDevNode->hDebugTable != NULL) +#endif + { + eError = PVRSRVRegisterDeviceDbgRequestNotify(&psDevNode->hPhysHeapDbgReqNotify, + psDevNode, + _PhysHeapDebugRequest, + DEBUG_REQUEST_SYS, + psDevNode); + + PVR_LOG_RETURN_IF_ERROR(eError, "PVRSRVRegisterDeviceDbgRequestNotify"); + } return PVRSRV_OK; } @@ -246,6 +391,24 @@ PVRSRV_ERROR PhysHeapCreate(PPVRSRV_DEVICE_NODE psDevNode, PVR_DPF_RETURN_RC1(PVRSRV_OK, *ppsPhysHeap); } +void PhysHeapDestroyDeviceHeaps(PPVRSRV_DEVICE_NODE psDevNode) +{ + IMG_UINT32 i; + + if (psDevNode->hPhysHeapDbgReqNotify) + { + PVRSRVUnregisterDeviceDbgRequestNotify(psDevNode->hPhysHeapDbgReqNotify); + } + + /* Unregister heaps */ + for (i = 0; i < psDevNode->ui32RegisteredPhysHeaps; i++) + { + PhysHeapDestroy(psDevNode->papsRegisteredPhysHeaps[i]); + } + + OSFreeMem(psDevNode->papsRegisteredPhysHeaps); +} + void PhysHeapDestroy(PHYS_HEAP *psPhysHeap) { PHEAP_IMPL_FUNCS *psImplFuncs = psPhysHeap->psImplFuncs; @@ -533,19 +696,75 @@ PhysHeapGetMemInfo(PVRSRV_DEVICE_NODE *psDevNode, psPhysHeap = _PhysHeapFindHeap(paePhysHeapID[i], psDevNode); + paPhysHeapMemStats[i].ui32PhysHeapFlags = 0; + if (psPhysHeap && PhysHeapUserModeAlloc(paePhysHeapID[i]) && psPhysHeap->psImplFuncs->pfnGetPMRFactoryMemStats) { psPhysHeap->psImplFuncs->pfnGetPMRFactoryMemStats(psPhysHeap->pvImplData, &paPhysHeapMemStats[i].ui64TotalSize, &paPhysHeapMemStats[i].ui64FreeSize); - paPhysHeapMemStats[i].ePhysHeapID = paePhysHeapID[i]; + paPhysHeapMemStats[i].ui32PhysHeapFlags |= PhysHeapGetType(psPhysHeap); + + if (paePhysHeapID[i] == psDevNode->psDevConfig->eDefaultHeap) + { + paPhysHeapMemStats[i].ui32PhysHeapFlags |= PVRSRV_PHYS_HEAP_FLAGS_IS_DEFAULT; + } + } + else + { + paPhysHeapMemStats[i].ui64TotalSize = 0; + paPhysHeapMemStats[i].ui64FreeSize = 0; + } + } + + return PVRSRV_OK; +} + +PVRSRV_ERROR +PhysHeapGetMemInfoPkd(PVRSRV_DEVICE_NODE *psDevNode, + IMG_UINT32 ui32PhysHeapCount, + PVRSRV_PHYS_HEAP *paePhysHeapID, + PHYS_HEAP_MEM_STATS_PKD_PTR paPhysHeapMemStats) +{ + IMG_UINT32 i = 0; + PHYS_HEAP *psPhysHeap; + + PVR_ASSERT(ui32PhysHeapCount <= PVRSRV_PHYS_HEAP_LAST); + + for (i = 0; i < ui32PhysHeapCount; i++) + { + if (paePhysHeapID[i] >= PVRSRV_PHYS_HEAP_LAST) + { + return PVRSRV_ERROR_PHYSHEAP_ID_INVALID; + } + + if (paePhysHeapID[i] == PVRSRV_PHYS_HEAP_DEFAULT) + { + return PVRSRV_ERROR_INVALID_PARAMS; + } + + psPhysHeap = _PhysHeapFindHeap(paePhysHeapID[i], psDevNode); + + paPhysHeapMemStats[i].ui32PhysHeapFlags = 0; + + if (psPhysHeap && PhysHeapUserModeAlloc(paePhysHeapID[i]) + && psPhysHeap->psImplFuncs->pfnGetPMRFactoryMemStats) + { + psPhysHeap->psImplFuncs->pfnGetPMRFactoryMemStats(psPhysHeap->pvImplData, + &paPhysHeapMemStats[i].ui64TotalSize, + &paPhysHeapMemStats[i].ui64FreeSize); + paPhysHeapMemStats[i].ui32PhysHeapFlags |= PhysHeapGetType(psPhysHeap); + + if (paePhysHeapID[i] == psDevNode->psDevConfig->eDefaultHeap) + { + paPhysHeapMemStats[i].ui32PhysHeapFlags |= PVRSRV_PHYS_HEAP_FLAGS_IS_DEFAULT; + } } else { paPhysHeapMemStats[i].ui64TotalSize = 0; paPhysHeapMemStats[i].ui64FreeSize = 0; - paPhysHeapMemStats[i].ePhysHeapID = INVALID_PHYS_HEAP; } } @@ -636,13 +855,11 @@ PVRSRV_ERROR PhysHeapInit(void) return PVRSRV_OK; } -PVRSRV_ERROR PhysHeapDeinit(void) +void PhysHeapDeinit(void) { PVR_ASSERT(g_psPhysHeapList == NULL); OSLockDestroy(g_hPhysHeapLock); - - return PVRSRV_OK; } PPVRSRV_DEVICE_NODE PhysHeapDeviceNode(PHYS_HEAP *psPhysHeap) @@ -665,3 +882,303 @@ IMG_BOOL PhysHeapUserModeAlloc(PVRSRV_PHYS_HEAP ePhysHeap) return gasHeapProperties[ePhysHeap].bUserModeAlloc; } + +#if defined(SUPPORT_GPUVIRT_VALIDATION) +/*************************************************************************/ /*! +@Function CreateGpuVirtValArenas +@Description Create virtualization validation arenas +@Input psDeviceNode The device node +@Return PVRSRV_ERROR PVRSRV_OK on success +*/ /**************************************************************************/ +static PVRSRV_ERROR CreateGpuVirtValArenas(PVRSRV_DEVICE_NODE *psDeviceNode) +{ + /* aui64OSidMin and aui64OSidMax are what we program into HW registers. + The values are different from base/size of arenas. */ + IMG_UINT64 aui64OSidMin[GPUVIRT_VALIDATION_NUM_REGIONS][GPUVIRT_VALIDATION_NUM_OS]; + IMG_UINT64 aui64OSidMax[GPUVIRT_VALIDATION_NUM_REGIONS][GPUVIRT_VALIDATION_NUM_OS]; + PHYS_HEAP_CONFIG *psGPULocalHeap = FindPhysHeapConfig(psDeviceNode->psDevConfig, PHYS_HEAP_USAGE_GPU_LOCAL); + PHYS_HEAP_CONFIG *psDisplayHeap = FindPhysHeapConfig(psDeviceNode->psDevConfig, PHYS_HEAP_USAGE_DISPLAY); + IMG_UINT64 uBase; + IMG_UINT64 uSize; + IMG_UINT64 uBaseShared; + IMG_UINT64 uSizeShared; + IMG_UINT64 uSizeSharedReg; + IMG_UINT32 i; + + /* Shared region is fixed size, the remaining space is divided amongst OSes */ + uSizeShared = PVR_ALIGN(GPUVIRT_SIZEOF_SHARED, (IMG_DEVMEM_SIZE_T)OSGetPageSize()); + uSize = psGPULocalHeap->uiSize - uSizeShared; + uSize /= GPUVIRT_VALIDATION_NUM_OS; + uSize = uSize & ~((IMG_UINT64)OSGetPageSize() - 1ULL); /* Align, round down */ + + uBase = psGPULocalHeap->sCardBase.uiAddr; + uBaseShared = uBase + uSize * GPUVIRT_VALIDATION_NUM_OS; + uSizeShared = psGPULocalHeap->uiSize - (uBaseShared - uBase); + + PVR_LOG(("GPUVIRT_VALIDATION split GPU_LOCAL base: 0x%" IMG_UINT64_FMTSPECX ", size: 0x%" IMG_UINT64_FMTSPECX ".", + psGPULocalHeap->sCardBase.uiAddr, + psGPULocalHeap->uiSize)); + + /* If a display heap config exists, include the display heap in the non-secure regions */ + if (psDisplayHeap) + { + /* Only works when DISPLAY heap follows GPU_LOCAL heap. */ + PVR_LOG(("GPUVIRT_VALIDATION include DISPLAY in shared, base: 0x%" IMG_UINT64_FMTSPECX ", size: 0x%" IMG_UINT64_FMTSPECX ".", + psDisplayHeap->sCardBase.uiAddr, + psDisplayHeap->uiSize)); + + uSizeSharedReg = uSizeShared + psDisplayHeap->uiSize; + } + else + { + uSizeSharedReg = uSizeShared; + } + + PVR_ASSERT(uSize >= GPUVIRT_MIN_SIZE); + PVR_ASSERT(uSizeSharedReg >= GPUVIRT_SIZEOF_SHARED); + + for (i = 0; i < GPUVIRT_VALIDATION_NUM_OS; i++) + { + IMG_CHAR aszOSRAName[RA_MAX_NAME_LENGTH]; + + PVR_LOG(("GPUVIRT_VALIDATION create arena OS: %d, base: 0x%" IMG_UINT64_FMTSPECX ", size: 0x%" IMG_UINT64_FMTSPECX ".", i, uBase, uSize)); + + OSSNPrintf(aszOSRAName, RA_MAX_NAME_LENGTH, "GPUVIRT_OS%d", i); + + psDeviceNode->psOSidSubArena[i] = RA_Create_With_Span(aszOSRAName, + OSGetPageShift(), + 0, + uBase, + uSize); + PVR_LOG_RETURN_IF_NOMEM(psDeviceNode->psOSidSubArena[i], "RA_Create_With_Span"); + + aui64OSidMin[GPUVIRT_VAL_REGION_SECURE][i] = uBase; + + if (i == 0) + { + /* OSid0 has access to all regions */ + aui64OSidMax[GPUVIRT_VAL_REGION_SECURE][i] = psGPULocalHeap->uiSize - 1ULL; + } + else + { + aui64OSidMax[GPUVIRT_VAL_REGION_SECURE][i] = uBase + uSize - 1ULL; + } + + /* uSizeSharedReg includes display heap */ + aui64OSidMin[GPUVIRT_VAL_REGION_SHARED][i] = uBaseShared; + aui64OSidMax[GPUVIRT_VAL_REGION_SHARED][i] = uBaseShared + uSizeSharedReg - 1ULL; + + PVR_LOG(("GPUVIRT_VALIDATION HW reg regions %d: min[0]: 0x%" IMG_UINT64_FMTSPECX ", max[0]: 0x%" IMG_UINT64_FMTSPECX ", min[1]: 0x%" IMG_UINT64_FMTSPECX ", max[1]: 0x%" IMG_UINT64_FMTSPECX ",", + i, + aui64OSidMin[GPUVIRT_VAL_REGION_SECURE][i], + aui64OSidMax[GPUVIRT_VAL_REGION_SECURE][i], + aui64OSidMin[GPUVIRT_VAL_REGION_SHARED][i], + aui64OSidMax[GPUVIRT_VAL_REGION_SHARED][i])); + uBase += uSize; + } + + PVR_LOG(("GPUVIRT_VALIDATION create arena Shared, base: 0x%" IMG_UINT64_FMTSPECX ", size: 0x%" IMG_UINT64_FMTSPECX ".", uBaseShared, uSizeShared)); + + PVR_ASSERT(uSizeShared >= GPUVIRT_SIZEOF_SHARED); + + /* uSizeShared does not include display heap */ + psDeviceNode->psOSSharedArena = RA_Create_With_Span("GPUVIRT_SHARED", + OSGetPageShift(), + 0, + uBaseShared, + uSizeShared); + PVR_LOG_RETURN_IF_NOMEM(psDeviceNode->psOSSharedArena, "RA_Create_With_Span"); + + if (psDeviceNode->psDevConfig->pfnSysDevVirtInit != NULL) + { + psDeviceNode->psDevConfig->pfnSysDevVirtInit(aui64OSidMin, aui64OSidMax); + } + + return PVRSRV_OK; +} + +/* + * Counter-part to CreateGpuVirtValArenas. + */ +static void DestroyGpuVirtValArenas(PVRSRV_DEVICE_NODE *psDeviceNode) +{ + IMG_UINT32 uiCounter = 0; + + /* + * NOTE: We overload psOSidSubArena[0] into the psLocalMemArena so we must + * not free it here as it gets cleared later. + */ + for (uiCounter = 1; uiCounter < GPUVIRT_VALIDATION_NUM_OS; uiCounter++) + { + if (psDeviceNode->psOSidSubArena[uiCounter] == NULL) + { + continue; + } + RA_Delete(psDeviceNode->psOSidSubArena[uiCounter]); + } + + if (psDeviceNode->psOSSharedArena != NULL) + { + RA_Delete(psDeviceNode->psOSSharedArena); + } +} +#endif + +PVRSRV_ERROR PhysHeapMMUPxSetup(PPVRSRV_DEVICE_NODE psDeviceNode) +{ + PHYS_HEAP_TYPE eHeapType; + PVRSRV_ERROR eError; + + eError = PhysHeapAcquireByDevPhysHeap(psDeviceNode->psDevConfig->eDefaultHeap, + psDeviceNode, &psDeviceNode->psMMUPhysHeap); + PVR_LOG_GOTO_IF_ERROR(eError, "PhysHeapAcquireByDevPhysHeap", ErrorDeinit); + + eHeapType = PhysHeapGetType(psDeviceNode->psMMUPhysHeap); + + if (eHeapType == PHYS_HEAP_TYPE_UMA) + { + PVR_DPF((PVR_DBG_MESSAGE, "%s: GPU physical heap uses OS System memory (UMA)", __func__)); + +#if defined(SUPPORT_GPUVIRT_VALIDATION) + PVR_DPF((PVR_DBG_ERROR, "%s: Virtualisation Validation builds are currently only" + " supported on systems with local memory (LMA).", __func__)); + eError = PVRSRV_ERROR_NOT_SUPPORTED; + goto ErrorDeinit; +#endif + } + else + { + PVR_DPF((PVR_DBG_MESSAGE, "%s: GPU physical heap uses local memory managed by the driver (LMA)", __func__)); + +#if defined(SUPPORT_GPUVIRT_VALIDATION) + eError = CreateGpuVirtValArenas(psDeviceNode); + PVR_LOG_GOTO_IF_ERROR(eError, "CreateGpuVirtValArenas", ErrorDeinit); +#endif + } + + return PVRSRV_OK; +ErrorDeinit: + return eError; +} + +void PhysHeapMMUPxDeInit(PPVRSRV_DEVICE_NODE psDeviceNode) +{ +#if defined(SUPPORT_GPUVIRT_VALIDATION) + /* Remove local LMA subarenas */ + DestroyGpuVirtValArenas(psDeviceNode); +#endif /* defined(SUPPORT_GPUVIRT_VALIDATION) */ + + if (psDeviceNode->psMMUPhysHeap != NULL) + { + PhysHeapRelease(psDeviceNode->psMMUPhysHeap); + psDeviceNode->psMMUPhysHeap = NULL; + } +} + +#if defined(SUPPORT_GPUVIRT_VALIDATION) +PVRSRV_ERROR PhysHeapPagesAllocGPV(PHYS_HEAP *psPhysHeap, size_t uiSize, + PG_HANDLE *psMemHandle, + IMG_DEV_PHYADDR *psDevPAddr, + IMG_UINT32 ui32OSid, IMG_PID uiPid) +{ + PHEAP_IMPL_FUNCS *psImplFuncs = psPhysHeap->psImplFuncs; + PVRSRV_ERROR eResult = PVRSRV_ERROR_NOT_IMPLEMENTED; + + if (psImplFuncs->pfnPagesAllocGPV != NULL) + { + eResult = psImplFuncs->pfnPagesAllocGPV(psPhysHeap, + uiSize, psMemHandle, psDevPAddr, ui32OSid, uiPid); + } + + return eResult; +} +#endif + +PVRSRV_ERROR PhysHeapPagesAlloc(PHYS_HEAP *psPhysHeap, size_t uiSize, + PG_HANDLE *psMemHandle, + IMG_DEV_PHYADDR *psDevPAddr, + IMG_PID uiPid) +{ + PHEAP_IMPL_FUNCS *psImplFuncs = psPhysHeap->psImplFuncs; + PVRSRV_ERROR eResult = PVRSRV_ERROR_NOT_IMPLEMENTED; + + if (psImplFuncs->pfnPagesAlloc != NULL) + { + eResult = psImplFuncs->pfnPagesAlloc(psPhysHeap, + uiSize, psMemHandle, psDevPAddr, uiPid); + } + + return eResult; +} + +void PhysHeapPagesFree(PHYS_HEAP *psPhysHeap, PG_HANDLE *psMemHandle) +{ + PHEAP_IMPL_FUNCS *psImplFuncs = psPhysHeap->psImplFuncs; + + PVR_ASSERT(psImplFuncs->pfnPagesFree != NULL); + + if (psImplFuncs->pfnPagesFree != NULL) + { + psImplFuncs->pfnPagesFree(psPhysHeap, + psMemHandle); + } +} + +PVRSRV_ERROR PhysHeapPagesMap(PHYS_HEAP *psPhysHeap, PG_HANDLE *pshMemHandle, size_t uiSize, IMG_DEV_PHYADDR *psDevPAddr, + void **pvPtr) +{ + PHEAP_IMPL_FUNCS *psImplFuncs = psPhysHeap->psImplFuncs; + PVRSRV_ERROR eResult = PVRSRV_ERROR_NOT_IMPLEMENTED; + + if (psImplFuncs->pfnPagesMap != NULL) + { + eResult = psImplFuncs->pfnPagesMap(psPhysHeap, + pshMemHandle, uiSize, psDevPAddr, pvPtr); + } + + return eResult; +} + +void PhysHeapPagesUnMap(PHYS_HEAP *psPhysHeap, PG_HANDLE *psMemHandle, void *pvPtr) +{ + PHEAP_IMPL_FUNCS *psImplFuncs = psPhysHeap->psImplFuncs; + + PVR_ASSERT(psImplFuncs->pfnPagesUnMap != NULL); + + if (psImplFuncs->pfnPagesUnMap != NULL) + { + psImplFuncs->pfnPagesUnMap(psPhysHeap, + psMemHandle, pvPtr); + } +} + +PVRSRV_ERROR PhysHeapPagesClean(PHYS_HEAP *psPhysHeap, PG_HANDLE *pshMemHandle, + IMG_UINT32 uiOffset, + IMG_UINT32 uiLength) +{ + PHEAP_IMPL_FUNCS *psImplFuncs = psPhysHeap->psImplFuncs; + PVRSRV_ERROR eResult = PVRSRV_ERROR_NOT_IMPLEMENTED; + + if (psImplFuncs->pfnPagesClean != NULL) + { + eResult = psImplFuncs->pfnPagesClean(psPhysHeap, + pshMemHandle, uiOffset, uiLength); + } + + return eResult; +} + +IMG_UINT32 PhysHeapGetPageShift(PHYS_HEAP *psPhysHeap) +{ + PHEAP_IMPL_FUNCS *psImplFuncs = psPhysHeap->psImplFuncs; + IMG_UINT32 ui32PageShift = 0; + + PVR_ASSERT(psImplFuncs->pfnGetPageShift != NULL); + + if (psImplFuncs->pfnGetPageShift != NULL) + { + ui32PageShift = psImplFuncs->pfnGetPageShift(); + } + + return ui32PageShift; +} diff --git a/drivers/gpu/drm/img-rogue/physheap.h b/drivers/gpu/drm/img-rogue/physheap.h index e1288cfa8..060c5cd0e 100644 --- a/drivers/gpu/drm/img-rogue/physheap.h +++ b/drivers/gpu/drm/img-rogue/physheap.h @@ -57,6 +57,32 @@ typedef struct _PHYS_HEAP_ PHYS_HEAP; struct _CONNECTION_DATA_; +typedef struct _PG_HANDLE_ +{ + union + { + void *pvHandle; + IMG_UINT64 ui64Handle; + }u; + /* The allocation order is log2 value of the number of pages to allocate. + * As such this is a correspondingly small value. E.g, for order 4 we + * are talking 2^4 * PAGE_SIZE contiguous allocation. + * DevPxAlloc API does not need to support orders higher than 4. + */ +#if defined(SUPPORT_GPUVIRT_VALIDATION) + IMG_BYTE uiOrder; /* Order of the corresponding allocation */ + IMG_BYTE uiOSid; /* OSid to use for allocation arena. + * Connection-specific. */ + IMG_BYTE uiPad1, + uiPad2; /* Spare */ +#else + IMG_BYTE uiOrder; /* Order of the corresponding allocation */ + IMG_BYTE uiPad1, + uiPad2, + uiPad3; /* Spare */ +#endif +} PG_HANDLE; + /*! Pointer to private implementation specific data */ typedef void *PHEAP_IMPL_DATA; @@ -90,6 +116,12 @@ typedef PVRSRV_ERROR (*PFN_GET_CPU_PADDR)(PHEAP_IMPL_DATA, IMG_CPU_PHYADDR*); @Return PVRSRV_ERROR PVRSRV_OK or error code */ /**************************************************************************/ typedef PVRSRV_ERROR (*PFN_GET_SIZE)(PHEAP_IMPL_DATA, IMG_UINT64*); +/*************************************************************************/ /*! +@Function Callback function PFN_GET_PAGE_SHIFT +@Description Get heap log2 page shift. +@Return IMG_UINT32 Log2 page shift +*/ /**************************************************************************/ +typedef IMG_UINT32 (*PFN_GET_PAGE_SHIFT)(void); /*************************************************************************/ /*! @Function Callback function PFN_GET_MEM_STATS @@ -102,6 +134,29 @@ typedef PVRSRV_ERROR (*PFN_GET_SIZE)(PHEAP_IMPL_DATA, IMG_UINT64*); */ /**************************************************************************/ typedef void (*PFN_GET_MEM_STATS)(PHEAP_IMPL_DATA, IMG_UINT64 *, IMG_UINT64 *); +#if defined(SUPPORT_GPUVIRT_VALIDATION) +typedef PVRSRV_ERROR (*PFN_PAGES_ALLOC_GPV)(PHYS_HEAP *psPhysHeap, size_t uiSize, + PG_HANDLE *psMemHandle, IMG_DEV_PHYADDR *psDevPAddr, + IMG_UINT32 ui32OSid, IMG_PID uiPid); +#endif +typedef PVRSRV_ERROR (*PFN_PAGES_ALLOC)(PHYS_HEAP *psPhysHeap, size_t uiSize, + PG_HANDLE *psMemHandle, IMG_DEV_PHYADDR *psDevPAddr, + IMG_PID uiPid); + +typedef void (*PFN_PAGES_FREE)(PHYS_HEAP *psPhysHeap, PG_HANDLE *psMemHandle); + +typedef PVRSRV_ERROR (*PFN_PAGES_MAP)(PHYS_HEAP *psPhysHeap, PG_HANDLE *pshMemHandle, + size_t uiSize, IMG_DEV_PHYADDR *psDevPAddr, + void **pvPtr); + +typedef void (*PFN_PAGES_UNMAP)(PHYS_HEAP *psPhysHeap, + PG_HANDLE *psMemHandle, void *pvPtr); + +typedef PVRSRV_ERROR (*PFN_PAGES_CLEAN)(PHYS_HEAP *psPhysHeap, + PG_HANDLE *pshMemHandle, + IMG_UINT32 uiOffset, + IMG_UINT32 uiLength); + /*************************************************************************/ /*! @Function Callback function PFN_CREATE_PMR @Description Create a PMR physical allocation and back with RAM on creation, @@ -143,27 +198,31 @@ typedef struct PHEAP_IMPL_FUNCS_TAG PFN_GET_DEV_PADDR pfnGetDevPAddr; PFN_GET_CPU_PADDR pfnGetCPUPAddr; PFN_GET_SIZE pfnGetSize; + PFN_GET_PAGE_SHIFT pfnGetPageShift; PFN_GET_MEM_STATS pfnGetPMRFactoryMemStats; PFN_CREATE_PMR pfnCreatePMR; +#if defined(SUPPORT_GPUVIRT_VALIDATION) + PFN_PAGES_ALLOC_GPV pfnPagesAllocGPV; +#endif + PFN_PAGES_ALLOC pfnPagesAlloc; + PFN_PAGES_FREE pfnPagesFree; + PFN_PAGES_MAP pfnPagesMap; + PFN_PAGES_UNMAP pfnPagesUnMap; + PFN_PAGES_CLEAN pfnPagesClean; } PHEAP_IMPL_FUNCS; /*************************************************************************/ /*! -@Function PhysHeapCreateHeapsFromConfigs -@Description Create new heaps from configs. +@Function PhysHeapCreateDeviceHeapsFromConfigs +@Description Create new heaps for a device from configs. @Input psDevNode Pointer to device node struct @Input pasConfigs Pointer to array of Heap configurations. @Input ui32NumConfigs Number of configurations in array. -@Output papsPhysHeaps Pointer to array of phys heap pointers. -@Output pui32NumHeaps Number of heaps created. Can be less than - ui32NumConfigs if error. @Return PVRSRV_ERROR PVRSRV_OK or error code */ /**************************************************************************/ PVRSRV_ERROR -PhysHeapCreateHeapsFromConfigs(PPVRSRV_DEVICE_NODE psDevNode, - PHYS_HEAP_CONFIG *pasConfigs, - IMG_UINT32 ui32NumConfigs, - PHYS_HEAP **papsPhysHeaps, - IMG_UINT32 *pui32NumHeaps); +PhysHeapCreateDeviceHeapsFromConfigs(PPVRSRV_DEVICE_NODE psDevNode, + PHYS_HEAP_CONFIG *pasConfigs, + IMG_UINT32 ui32NumConfigs); /*************************************************************************/ /*! @Function PhysHeapCreateHeapFromConfig @@ -198,6 +257,14 @@ PVRSRV_ERROR PhysHeapCreate(PPVRSRV_DEVICE_NODE psDevNode, PHEAP_IMPL_FUNCS *psImplFuncs, PHYS_HEAP **ppsPhysHeap); +/*************************************************************************/ /*! +@Function PhysHeapDestroyDeviceHeaps +@Description Destroys all heaps referenced by a device. +@Input psDevNode Pointer to a device node struct. +@Return void +*/ /**************************************************************************/ +void PhysHeapDestroyDeviceHeaps(PPVRSRV_DEVICE_NODE psDevNode); + void PhysHeapDestroy(PHYS_HEAP *psPhysHeap); PVRSRV_ERROR PhysHeapAcquire(PHYS_HEAP *psPhysHeap); @@ -281,6 +348,21 @@ PhysHeapGetMemInfo(PPVRSRV_DEVICE_NODE psDevNode, PVRSRV_PHYS_HEAP *paePhysHeapID, PHYS_HEAP_MEM_STATS_PTR paPhysHeapMemStats); +/*************************************************************************/ /*! +@Function PhysHeapGetMemInfoPkd +@Description Get phys heap memory statistics for a given physical heap ID. +@Input psDevNode Pointer to device node struct +@Input ui32PhysHeapCount Physical heap count +@Input paePhysHeapID Physical heap ID +@Output paPhysHeapMemStats Buffer that holds the memory statistics +@Return PVRSRV_ERROR PVRSRV_OK or error code +*/ /**************************************************************************/ +PVRSRV_ERROR +PhysHeapGetMemInfoPkd(PPVRSRV_DEVICE_NODE psDevNode, + IMG_UINT32 ui32PhysHeapCount, + PVRSRV_PHYS_HEAP *paePhysHeapID, + PHYS_HEAP_MEM_STATS_PKD_PTR paPhysHeapMemStats); + /*************************************************************************/ /*! @Function PhysheapGetPhysMemUsage @Description Get memory statistics for a given physical heap. @@ -331,7 +413,7 @@ PVRSRV_ERROR PhysHeapCreatePMR(PHYS_HEAP *psPhysHeap, IMG_UINT32 ui32PDumpFlags); PVRSRV_ERROR PhysHeapInit(void); -PVRSRV_ERROR PhysHeapDeinit(void); +void PhysHeapDeinit(void); /*************************************************************************/ /*! @Function PhysHeapDeviceNode @@ -357,4 +439,59 @@ IMG_BOOL PhysHeapPVRLayerAcquire(PVRSRV_PHYS_HEAP ePhysHeap); */ /**************************************************************************/ IMG_BOOL PhysHeapUserModeAlloc(PVRSRV_PHYS_HEAP ePhysHeap); +/*************************************************************************/ /*! +@Function PhysHeapMMUPxSetup +@Description Setup MMU Px allocation function pointers. +@Input psDeviceNode Pointer to device node struct +@Return PVRSRV_ERROR PVRSRV_OK on success. +*/ /**************************************************************************/ +PVRSRV_ERROR PhysHeapMMUPxSetup(PPVRSRV_DEVICE_NODE psDeviceNode); + +/*************************************************************************/ /*! +@Function PhysHeapMMUPxDeInit +@Description Deinit after PhysHeapMMUPxSetup. +@Input psDeviceNode Pointer to device node struct +*/ /**************************************************************************/ +void PhysHeapMMUPxDeInit(PPVRSRV_DEVICE_NODE psDeviceNode); + +#if defined(SUPPORT_GPUVIRT_VALIDATION) +PVRSRV_ERROR PhysHeapPagesAllocGPV(PHYS_HEAP *psPhysHeap, + size_t uiSize, + PG_HANDLE *psMemHandle, + IMG_DEV_PHYADDR *psDevPAddr, + IMG_UINT32 ui32OSid, IMG_PID uiPid); +#endif + +PVRSRV_ERROR PhysHeapPagesAlloc(PHYS_HEAP *psPhysHeap, + size_t uiSize, + PG_HANDLE *psMemHandle, + IMG_DEV_PHYADDR *psDevPAddr, + IMG_PID uiPid); + +void PhysHeapPagesFree(PHYS_HEAP *psPhysHeap, + PG_HANDLE *psMemHandle); + +PVRSRV_ERROR PhysHeapPagesMap(PHYS_HEAP *psPhysHeap, + PG_HANDLE *pshMemHandle, + size_t uiSize, + IMG_DEV_PHYADDR *psDevPAddr, + void **pvPtr); + +void PhysHeapPagesUnMap(PHYS_HEAP *psPhysHeap, + PG_HANDLE *psMemHandle, + void *pvPtr); + +PVRSRV_ERROR PhysHeapPagesClean(PHYS_HEAP *psPhysHeap, + PG_HANDLE *pshMemHandle, + IMG_UINT32 uiOffset, + IMG_UINT32 uiLength); + +/*************************************************************************/ /*! +@Function PhysHeapGetPageShift +@Description Get phys heap page shift. +@Input psPhysHeap Pointer to physical heap. +@Return IMG_UINT32 Log2 page shift +*/ /**************************************************************************/ +IMG_UINT32 PhysHeapGetPageShift(PHYS_HEAP *psPhysHeap); + #endif /* PHYSHEAP_H */ diff --git a/drivers/gpu/drm/img-rogue/physheap_config.h b/drivers/gpu/drm/img-rogue/physheap_config.h index 22599e669..9d4d786dd 100644 --- a/drivers/gpu/drm/img-rogue/physheap_config.h +++ b/drivers/gpu/drm/img-rogue/physheap_config.h @@ -88,29 +88,6 @@ typedef struct _PHYS_HEAP_FUNCTIONS_ DevPAddrToCpuPAddr pfnDevPAddrToCpuPAddr; } PHYS_HEAP_FUNCTIONS; -/*! Type conveys the class of physical heap to instantiate within Services - * for the physical pool of memory. */ -typedef enum _PHYS_HEAP_TYPE_ -{ - PHYS_HEAP_TYPE_UNKNOWN = 0, /*!< Not a valid value for any config */ - PHYS_HEAP_TYPE_UMA, /*!< Heap represents OS managed physical memory heap - i.e. system RAM. Unified Memory Architecture - physmem_osmem PMR factory */ - PHYS_HEAP_TYPE_LMA, /*!< Heap represents physical memory pool managed by - Services i.e. carve out from system RAM or local - card memory. Local Memory Architecture - physmem_lma PMR factory */ - PHYS_HEAP_TYPE_DMA, /*!< Heap represents a physical memory pool managed by - Services, alias of LMA and is only used on - VZ non-native system configurations for - a heap used for PHYS_HEAP_USAGE_FW_MAIN tagged - buffers */ -#if defined(SUPPORT_WRAP_EXTMEMOBJECT) - PHYS_HEAP_TYPE_WRAP, /*!< Heap used to group UM buffers given - to Services. Integrity OS port only. */ -#endif -} PHYS_HEAP_TYPE; - /*! Structure used to describe a physical Heap supported by a system. A * system layer module can declare multiple physical heaps for different * purposes. At a minimum a system must provide one physical heap tagged for diff --git a/drivers/gpu/drm/img-rogue/physmem.c b/drivers/gpu/drm/img-rogue/physmem.c index a8e2d9882..34c174d9d 100644 --- a/drivers/gpu/drm/img-rogue/physmem.c +++ b/drivers/gpu/drm/img-rogue/physmem.c @@ -109,11 +109,11 @@ PVRSRV_ERROR DevPhysMemAlloc(PVRSRV_DEVICE_NODE *psDevNode, #endif /* Allocate the pages */ - eError = psDevNode->sDevMMUPxSetup.pfnDevPxAlloc(psDevNode, - TRUNCATE_64BITS_TO_SIZE_T(ui32MemSize), - psMemHandle, - &sDevPhysAddr_int, - uiPid); + eError = PhysHeapPagesAlloc(psDevNode->psMMUPhysHeap, + TRUNCATE_64BITS_TO_SIZE_T(ui32MemSize), + psMemHandle, + &sDevPhysAddr_int, + uiPid); PVR_LOG_RETURN_IF_ERROR(eError, "pfnDevPxAlloc:1"); /* Check to see if the page allocator returned pages with our desired @@ -123,14 +123,14 @@ PVRSRV_ERROR DevPhysMemAlloc(PVRSRV_DEVICE_NODE *psDevNode, if (ui32Log2Align && (sDevPhysAddr_int.uiAddr & uiMask)) { /* use over allocation instead */ - psDevNode->sDevMMUPxSetup.pfnDevPxFree(psDevNode, psMemHandle); + PhysHeapPagesFree(psDevNode->psMMUPhysHeap, psMemHandle); ui32MemSize += (IMG_UINT32) uiMask; - eError = psDevNode->sDevMMUPxSetup.pfnDevPxAlloc(psDevNode, - TRUNCATE_64BITS_TO_SIZE_T(ui32MemSize), - psMemHandle, - &sDevPhysAddr_int, - uiPid); + eError = PhysHeapPagesAlloc(psDevNode->psMMUPhysHeap, + TRUNCATE_64BITS_TO_SIZE_T(ui32MemSize), + psMemHandle, + &sDevPhysAddr_int, + uiPid); PVR_LOG_RETURN_IF_ERROR(eError, "pfnDevPxAlloc:2"); sDevPhysAddr_int.uiAddr += uiMask; @@ -160,15 +160,15 @@ PVRSRV_ERROR DevPhysMemAlloc(PVRSRV_DEVICE_NODE *psDevNode, if (bInitPage) { /*Map the page to the CPU VA space */ - eError = psDevNode->sDevMMUPxSetup.pfnDevPxMap(psDevNode, - psMemHandle, - ui32MemSize, - &sDevPhysAddr_int, - &pvCpuVAddr); + eError = PhysHeapPagesMap(psDevNode->psMMUPhysHeap, + psMemHandle, + ui32MemSize, + &sDevPhysAddr_int, + &pvCpuVAddr); if (PVRSRV_OK != eError) { PVR_LOG_ERROR(eError, "DevPxMap"); - psDevNode->sDevMMUPxSetup.pfnDevPxFree(psDevNode, psMemHandle); + PhysHeapPagesFree(psDevNode->psMMUPhysHeap, psMemHandle); return eError; } @@ -176,15 +176,15 @@ PVRSRV_ERROR DevPhysMemAlloc(PVRSRV_DEVICE_NODE *psDevNode, OSDeviceMemSet(pvCpuVAddr, u8Value, ui32MemSize); /*Map the page to the CPU VA space */ - eError = psDevNode->sDevMMUPxSetup.pfnDevPxClean(psDevNode, - psMemHandle, - 0, - ui32MemSize); + eError = PhysHeapPagesClean(psDevNode->psMMUPhysHeap, + psMemHandle, + 0, + ui32MemSize); if (PVRSRV_OK != eError) { PVR_LOG_ERROR(eError, "DevPxClean"); - psDevNode->sDevMMUPxSetup.pfnDevPxUnMap(psDevNode, psMemHandle, pvCpuVAddr); - psDevNode->sDevMMUPxSetup.pfnDevPxFree(psDevNode, psMemHandle); + PhysHeapPagesUnMap(psDevNode->psMMUPhysHeap, psMemHandle, pvCpuVAddr); + PhysHeapPagesFree(psDevNode->psMMUPhysHeap, psMemHandle); return eError; } @@ -245,9 +245,9 @@ PVRSRV_ERROR DevPhysMemAlloc(PVRSRV_DEVICE_NODE *psDevNode, #endif /* Unmap the page */ - psDevNode->sDevMMUPxSetup.pfnDevPxUnMap(psDevNode, - psMemHandle, - pvCpuVAddr); + PhysHeapPagesUnMap(psDevNode->psMMUPhysHeap, + psMemHandle, + pvCpuVAddr); } return PVRSRV_OK; @@ -262,7 +262,7 @@ void DevPhysMemFree(PVRSRV_DEVICE_NODE *psDevNode, PG_HANDLE *psMemHandle; psMemHandle = hMemHandle; - psDevNode->sDevMMUPxSetup.pfnDevPxFree(psDevNode, psMemHandle); + PhysHeapPagesFree(psDevNode->psMMUPhysHeap, psMemHandle); #if defined(PDUMP) if (NULL != hPDUMPMemHandle) { @@ -742,7 +742,38 @@ PVRSRVGetHeapPhysMemUsageKM(CONNECTION_DATA *psConnection, PhysheapGetPhysMemUsage(psPhysHeap, &apPhysHeapMemStats[i].ui64TotalSize, &apPhysHeapMemStats[i].ui64FreeSize); - apPhysHeapMemStats[i].ePhysHeapID = uiHeapIndex; + i++; + } + } + return PVRSRV_OK; +} + +PVRSRV_ERROR +PVRSRVGetHeapPhysMemUsagePkdKM(CONNECTION_DATA *psConnection, + PVRSRV_DEVICE_NODE *psDevNode, + IMG_UINT32 ui32PhysHeapCount, + PHYS_HEAP_MEM_STATS_PKD *apPhysHeapMemStats) +{ + PHYS_HEAP *psPhysHeap; + IMG_UINT uiHeapIndex, i = 0; + + PVR_UNREFERENCED_PARAMETER(psConnection); + + if (ui32PhysHeapCount != psDevNode->ui32UserAllocHeapCount) + { + return PVRSRV_ERROR_INVALID_PARAMS; + } + + for (uiHeapIndex = PVRSRV_PHYS_HEAP_DEFAULT+1; (uiHeapIndex < PVRSRV_PHYS_HEAP_LAST); uiHeapIndex++) + { + psPhysHeap = psDevNode->apsPhysHeap[uiHeapIndex]; + + if (psPhysHeap && PhysHeapUserModeAlloc(uiHeapIndex)) + { + PVR_ASSERT(i < ui32PhysHeapCount); + + PhysheapGetPhysMemUsage(psPhysHeap, &apPhysHeapMemStats[i].ui64TotalSize, + &apPhysHeapMemStats[i].ui64FreeSize); i++; } @@ -764,6 +795,20 @@ PVRSRVPhysHeapGetMemInfoKM(CONNECTION_DATA *psConnection, paPhysHeapMemStats); } +PVRSRV_ERROR +PVRSRVPhysHeapGetMemInfoPkdKM(CONNECTION_DATA *psConnection, + PVRSRV_DEVICE_NODE *psDevNode, + IMG_UINT32 ui32PhysHeapCount, + PVRSRV_PHYS_HEAP *paePhysHeapID, + PHYS_HEAP_MEM_STATS_PKD *paPhysHeapMemStats) +{ + PVR_UNREFERENCED_PARAMETER(psConnection); + return PhysHeapGetMemInfoPkd(psDevNode, + ui32PhysHeapCount, + paePhysHeapID, + paPhysHeapMemStats); +} + /* 'Wrapper' function to call PMRImportPMR(), which first checks the PMR is * for the current device. This avoids the need to do this in pmr.c, which * would then need PVRSRV_DEVICE_NODE (defining this type in pmr.h causes a diff --git a/drivers/gpu/drm/img-rogue/physmem.h b/drivers/gpu/drm/img-rogue/physmem.h index 1f48b6911..ca293e9c8 100644 --- a/drivers/gpu/drm/img-rogue/physmem.h +++ b/drivers/gpu/drm/img-rogue/physmem.h @@ -274,6 +274,20 @@ PVRSRVGetHeapPhysMemUsageKM(CONNECTION_DATA *psConnection, IMG_UINT32 ui32PhysHeapCount, PHYS_HEAP_MEM_STATS *apPhysHeapMemStats); +/*************************************************************************/ /*! +@Function PVRSRVGetHeapPhysMemUsagePkdKM +@Description Get the memory usage statistics for all user accessible + physical heaps +@Input ui32PhysHeapCount Total user accessible physical heaps +@Output apPhysHeapMemStats Buffer to hold the memory statistics +@Return PVRSRV_OK if successful +*/ /**************************************************************************/ +PVRSRV_ERROR +PVRSRVGetHeapPhysMemUsagePkdKM(CONNECTION_DATA *psConnection, + PVRSRV_DEVICE_NODE *psDevNode, + IMG_UINT32 ui32PhysHeapCount, + PHYS_HEAP_MEM_STATS_PKD *apPhysHeapMemStats); + /*************************************************************************/ /*! @Function PVRSRVPhysHeapGetMemInfoKM @Description Get the memory usage statistics for a given physical heap ID @@ -289,4 +303,19 @@ PVRSRVPhysHeapGetMemInfoKM(CONNECTION_DATA *psConnection, PVRSRV_PHYS_HEAP *paePhysHeapID, PHYS_HEAP_MEM_STATS *paPhysHeapMemStats); +/*************************************************************************/ /*! +@Function PVRSRVPhysHeapGetMemInfoPkdKM +@Description Get the memory usage statistics for a given physical heap ID +@Input ui32PhysHeapCount Physical Heap count +@Input paePhysHeapID Array of Physical Heap ID's +@Output paPhysHeapMemStats Buffer to hold the memory statistics +@Return PVRSRV_OK if successful +*/ /**************************************************************************/ +PVRSRV_ERROR +PVRSRVPhysHeapGetMemInfoPkdKM(CONNECTION_DATA *psConnection, + PVRSRV_DEVICE_NODE *psDevNode, + IMG_UINT32 ui32PhysHeapCount, + PVRSRV_PHYS_HEAP *paePhysHeapID, + PHYS_HEAP_MEM_STATS_PKD *paPhysHeapMemStats); + #endif /* SRVSRV_PHYSMEM_H */ diff --git a/drivers/gpu/drm/img-rogue/physmem_dmabuf.c b/drivers/gpu/drm/img-rogue/physmem_dmabuf.c index 1813e71ba..ac157b5f4 100644 --- a/drivers/gpu/drm/img-rogue/physmem_dmabuf.c +++ b/drivers/gpu/drm/img-rogue/physmem_dmabuf.c @@ -403,8 +403,9 @@ static PVRSRV_ERROR PMRDevPhysAddrDmaBuf(PMR_IMPL_PRIVDATA pvPriv, ui32PageIndex = puiOffset[idx] >> PAGE_SHIFT; ui32InPageOffset = puiOffset[idx] - ((IMG_DEVMEM_OFFSET_T)ui32PageIndex << PAGE_SHIFT); + PVR_LOG_RETURN_IF_FALSE(ui32PageIndex < psPrivData->ui32VirtPageCount, + "puiOffset out of range", PVRSRV_ERROR_OUT_OF_RANGE); - PVR_ASSERT(ui32PageIndex < psPrivData->ui32VirtPageCount); PVR_ASSERT(ui32InPageOffset < PAGE_SIZE); psDevPAddr[idx].uiAddr = psPrivData->pasDevPhysAddr[ui32PageIndex].uiAddr + ui32InPageOffset; } @@ -553,8 +554,11 @@ PhysmemCreateNewDmaBufBackedPMR(PHYS_HEAP *psHeap, bZeroOnAlloc = PVRSRV_CHECK_ZERO_ON_ALLOC(uiFlags); bPoisonOnAlloc = PVRSRV_CHECK_POISON_ON_ALLOC(uiFlags); +#if defined(DEBUG) bPoisonOnFree = PVRSRV_CHECK_POISON_ON_FREE(uiFlags); - +#else + bPoisonOnFree = IMG_FALSE; +#endif if (bZeroOnAlloc && bPoisonOnFree) { /* Zero on Alloc and Poison on Alloc are mutually exclusive */ @@ -774,11 +778,7 @@ PhysmemExportDmaBuf(CONNECTION_DATA *psConnection, PMRRefPMR(psPMR); - eError = PMR_LogicalSize(psPMR, &uiPMRSize); - if (eError != PVRSRV_OK) - { - goto fail_pmr_ref; - } + PMR_LogicalSize(psPMR, &uiPMRSize); #if (LINUX_VERSION_CODE >= KERNEL_VERSION(4, 1, 0)) { diff --git a/drivers/gpu/drm/img-rogue/physmem_lma.c b/drivers/gpu/drm/img-rogue/physmem_lma.c index 35357cea4..4fa61ac18 100644 --- a/drivers/gpu/drm/img-rogue/physmem_lma.c +++ b/drivers/gpu/drm/img-rogue/physmem_lma.c @@ -168,6 +168,11 @@ _GetSize(PHEAP_IMPL_DATA pvImplData, return PVRSRV_OK; } +static IMG_UINT32 +_GetPageShift(void) +{ + return PVRSRV_4K_PAGE_SIZE_ALIGNSHIFT; +} static void PhysmemGetLocalRamMemStats(PHEAP_IMPL_DATA pvImplData, IMG_UINT64 *pui64TotalSize, @@ -182,7 +187,7 @@ static void PhysmemGetLocalRamMemStats(PHEAP_IMPL_DATA pvImplData, *pui64FreeSize = sRAUsageStats.ui64FreeArenaSize; } -PVRSRV_ERROR +static PVRSRV_ERROR PhysmemGetArenaLMA(PHYS_HEAP *psPhysHeap, RA_ARENA **ppsArena) { @@ -351,14 +356,308 @@ PVRSRV_ERROR LMA_HeapIteratorGetHeapStats(PHYS_HEAP_ITERATOR *psIter, return PVRSRV_OK; } + +static PVRSRV_ERROR +_LMA_DoPhyContigPagesAlloc(RA_ARENA *pArena, + size_t uiSize, + PG_HANDLE *psMemHandle, + IMG_DEV_PHYADDR *psDevPAddr, + IMG_PID uiPid) +{ + RA_BASE_T uiCardAddr = 0; + RA_LENGTH_T uiActualSize; + PVRSRV_ERROR eError; +#if defined(DEBUG) + static IMG_UINT32 ui32MaxLog2NumPages = 4; /* 16 pages => 64KB */ +#endif /* defined(DEBUG) */ + + IMG_UINT32 ui32Log2NumPages = 0; + + PVR_ASSERT(uiSize != 0); + ui32Log2NumPages = OSGetOrder(uiSize); + uiSize = (1 << ui32Log2NumPages) * OSGetPageSize(); + + eError = RA_Alloc(pArena, + uiSize, + RA_NO_IMPORT_MULTIPLIER, + 0, /* No flags */ + uiSize, + "LMA_PhyContigPagesAlloc", + &uiCardAddr, + &uiActualSize, + NULL); /* No private handle */ + + PVR_ASSERT(uiSize == uiActualSize); + + psMemHandle->u.ui64Handle = uiCardAddr; + psDevPAddr->uiAddr = (IMG_UINT64) uiCardAddr; + + if (PVRSRV_OK == eError) + { +#if defined(PVRSRV_ENABLE_PROCESS_STATS) +#if !defined(PVRSRV_ENABLE_MEMORY_STATS) + PVRSRVStatsIncrMemAllocStatAndTrack(PVRSRV_MEM_ALLOC_TYPE_ALLOC_PAGES_PT_LMA, + uiSize, + uiCardAddr, + uiPid); +#else + IMG_CPU_PHYADDR sCpuPAddr; + sCpuPAddr.uiAddr = psDevPAddr->uiAddr; + + PVRSRVStatsAddMemAllocRecord(PVRSRV_MEM_ALLOC_TYPE_ALLOC_PAGES_PT_LMA, + NULL, + sCpuPAddr, + uiSize, + NULL, + uiPid + DEBUG_MEMSTATS_VALUES); +#endif +#endif +#if defined(SUPPORT_GPUVIRT_VALIDATION) + PVR_DPF((PVR_DBG_MESSAGE, + "%s: (GPU Virtualisation) Allocated 0x" IMG_SIZE_FMTSPECX " at 0x%" IMG_UINT64_FMTSPECX ", Arena ID %u", + __func__, uiSize, psDevPAddr->uiAddr, psMemHandle->uiOSid)); +#endif + +#if defined(DEBUG) + PVR_ASSERT((ui32Log2NumPages <= ui32MaxLog2NumPages)); + if (ui32Log2NumPages > ui32MaxLog2NumPages) + { + PVR_DPF((PVR_DBG_ERROR, + "%s: ui32MaxLog2NumPages = %u, increasing to %u", __func__, + ui32MaxLog2NumPages, ui32Log2NumPages )); + ui32MaxLog2NumPages = ui32Log2NumPages; + } +#endif /* defined(DEBUG) */ + psMemHandle->uiOrder = ui32Log2NumPages; + } + + return eError; +} + +#if defined(SUPPORT_GPUVIRT_VALIDATION) +static PVRSRV_ERROR +LMA_PhyContigPagesAllocGPV(PHYS_HEAP *psPhysHeap, + size_t uiSize, + PG_HANDLE *psMemHandle, + IMG_DEV_PHYADDR *psDevPAddr, + IMG_UINT32 ui32OSid, + IMG_PID uiPid) +{ + PVRSRV_DEVICE_NODE *psDevNode = PhysHeapDeviceNode(psPhysHeap); + RA_ARENA *pArena; + IMG_UINT32 ui32Log2NumPages = 0; + PVRSRV_ERROR eError; + + PVR_ASSERT(uiSize != 0); + ui32Log2NumPages = OSGetOrder(uiSize); + uiSize = (1 << ui32Log2NumPages) * OSGetPageSize(); + + PVR_ASSERT(ui32OSid < GPUVIRT_VALIDATION_NUM_OS); + if (ui32OSid >= GPUVIRT_VALIDATION_NUM_OS) + { + PVR_DPF((PVR_DBG_ERROR, "%s: Invalid Arena index %u defaulting to 0", + __func__, ui32OSid)); + ui32OSid = 0; + } + + pArena = psDevNode->psOSidSubArena[ui32OSid]; + + if (psMemHandle->uiOSid != ui32OSid) + { + PVR_LOG(("%s: Unexpected OSid value %u - expecting %u", __func__, + psMemHandle->uiOSid, ui32OSid)); + } + + psMemHandle->uiOSid = ui32OSid; /* For Free() use */ + + eError = _LMA_DoPhyContigPagesAlloc(pArena, uiSize, psMemHandle, + psDevPAddr, uiPid); + PVR_LOG_IF_ERROR(eError, "_LMA_DoPhyContigPagesAlloc"); + + return eError; +} +#endif + +static PVRSRV_ERROR +LMA_PhyContigPagesAlloc(PHYS_HEAP *psPhysHeap, + size_t uiSize, + PG_HANDLE *psMemHandle, + IMG_DEV_PHYADDR *psDevPAddr, + IMG_PID uiPid) +{ +#if defined(SUPPORT_GPUVIRT_VALIDATION) + IMG_UINT32 ui32OSid = 0; + return LMA_PhyContigPagesAllocGPV(psPhysHeap, uiSize, psMemHandle, psDevPAddr, + ui32OSid, uiPid); +#else + PVRSRV_ERROR eError; + + RA_ARENA *pArena; + IMG_UINT32 ui32Log2NumPages = 0; + + eError = PhysmemGetArenaLMA(psPhysHeap, &pArena); + PVR_LOG_RETURN_IF_ERROR(eError, "PhysmemGetArenaLMA"); + + PVR_ASSERT(uiSize != 0); + ui32Log2NumPages = OSGetOrder(uiSize); + uiSize = (1 << ui32Log2NumPages) * OSGetPageSize(); + + eError = _LMA_DoPhyContigPagesAlloc(pArena, uiSize, psMemHandle, + psDevPAddr, uiPid); + PVR_LOG_IF_ERROR(eError, "_LMA_DoPhyContigPagesAlloc"); + + return eError; +#endif +} + +static void +LMA_PhyContigPagesFree(PHYS_HEAP *psPhysHeap, + PG_HANDLE *psMemHandle) +{ + RA_BASE_T uiCardAddr = (RA_BASE_T) psMemHandle->u.ui64Handle; + RA_ARENA *pArena; + +#if defined(SUPPORT_GPUVIRT_VALIDATION) + PVRSRV_DEVICE_NODE *psDevNode = PhysHeapDeviceNode(psPhysHeap); + IMG_UINT32 ui32OSid = psMemHandle->uiOSid; + + /* + * The Arena ID is set by the originating allocation, and maintained via + * the call stacks into this function. We have a limited range of IDs + * and if the passed value falls outside this we simply treat it as a + * 'global' arena ID of 0. This is where all default OS-specific allocations + * are created. + */ + PVR_ASSERT(ui32OSid < GPUVIRT_VALIDATION_NUM_OS); + if (ui32OSid >= GPUVIRT_VALIDATION_NUM_OS) + { + PVR_DPF((PVR_DBG_ERROR, "%s: Invalid Arena index %u PhysAddr 0x%" + IMG_UINT64_FMTSPECx " Reverting to Arena 0", __func__, + ui32OSid, uiCardAddr)); + /* + * No way of determining what we're trying to free so default to the + * global default arena index 0. + */ + ui32OSid = 0; + } + + pArena = psDevNode->psOSidSubArena[ui32OSid]; + + PVR_DPF((PVR_DBG_MESSAGE, "%s: (GPU Virtualisation) Freeing 0x%" + IMG_UINT64_FMTSPECx ", Arena %u", __func__, + uiCardAddr, ui32OSid)); + +#else + PhysmemGetArenaLMA(psPhysHeap, &pArena); +#endif + +#if defined(PVRSRV_ENABLE_PROCESS_STATS) +#if !defined(PVRSRV_ENABLE_MEMORY_STATS) + PVRSRVStatsDecrMemAllocStatAndUntrack(PVRSRV_MEM_ALLOC_TYPE_ALLOC_PAGES_PT_LMA, + (IMG_UINT64)uiCardAddr); +#else + PVRSRVStatsRemoveMemAllocRecord(PVRSRV_MEM_ALLOC_TYPE_ALLOC_PAGES_PT_LMA, + (IMG_UINT64)uiCardAddr, + OSGetCurrentClientProcessIDKM()); +#endif +#endif + + RA_Free(pArena, uiCardAddr); + psMemHandle->uiOrder = 0; +} + +static PVRSRV_ERROR +LMA_PhyContigPagesMap(PHYS_HEAP *psPhysHeap, + PG_HANDLE *psMemHandle, + size_t uiSize, IMG_DEV_PHYADDR *psDevPAddr, + void **pvPtr) +{ + IMG_CPU_PHYADDR sCpuPAddr; + IMG_UINT32 ui32NumPages = (1 << psMemHandle->uiOrder); + PVR_UNREFERENCED_PARAMETER(uiSize); + + PhysHeapDevPAddrToCpuPAddr(psPhysHeap, 1, &sCpuPAddr, psDevPAddr); + *pvPtr = OSMapPhysToLin(sCpuPAddr, + ui32NumPages * OSGetPageSize(), + PVRSRV_MEMALLOCFLAG_CPU_UNCACHED_WC); + PVR_RETURN_IF_NOMEM(*pvPtr); + +#if defined(PVRSRV_ENABLE_PROCESS_STATS) +#if !defined(PVRSRV_ENABLE_MEMORY_STATS) + PVRSRVStatsIncrMemAllocStat(PVRSRV_MEM_ALLOC_TYPE_IOREMAP_PT_LMA, + ui32NumPages * OSGetPageSize(), + OSGetCurrentClientProcessIDKM()); +#else + { + PVRSRVStatsAddMemAllocRecord(PVRSRV_MEM_ALLOC_TYPE_IOREMAP_PT_LMA, + *pvPtr, + sCpuPAddr, + ui32NumPages * OSGetPageSize(), + NULL, + OSGetCurrentClientProcessIDKM() + DEBUG_MEMSTATS_VALUES); + } +#endif +#endif + return PVRSRV_OK; +} + +static void +LMA_PhyContigPagesUnmap(PHYS_HEAP *psPhysHeap, + PG_HANDLE *psMemHandle, + void *pvPtr) +{ + IMG_UINT32 ui32NumPages = (1 << psMemHandle->uiOrder); + PVR_UNREFERENCED_PARAMETER(psPhysHeap); + +#if defined(PVRSRV_ENABLE_PROCESS_STATS) +#if !defined(PVRSRV_ENABLE_MEMORY_STATS) + PVRSRVStatsDecrMemAllocStat(PVRSRV_MEM_ALLOC_TYPE_IOREMAP_PT_LMA, + ui32NumPages * OSGetPageSize(), + OSGetCurrentClientProcessIDKM()); +#else + PVRSRVStatsRemoveMemAllocRecord(PVRSRV_MEM_ALLOC_TYPE_IOREMAP_PT_LMA, + (IMG_UINT64)(uintptr_t)pvPtr, + OSGetCurrentClientProcessIDKM()); +#endif +#endif + + OSUnMapPhysToLin(pvPtr, ui32NumPages * OSGetPageSize()); +} + +static PVRSRV_ERROR +LMA_PhyContigPagesClean(PHYS_HEAP *psPhysHeap, + PG_HANDLE *psMemHandle, + IMG_UINT32 uiOffset, + IMG_UINT32 uiLength) +{ + /* No need to flush because we map as uncached */ + PVR_UNREFERENCED_PARAMETER(psPhysHeap); + PVR_UNREFERENCED_PARAMETER(psMemHandle); + PVR_UNREFERENCED_PARAMETER(uiOffset); + PVR_UNREFERENCED_PARAMETER(uiLength); + + return PVRSRV_OK; +} + static PHEAP_IMPL_FUNCS _sPHEAPImplFuncs = { .pfnDestroyData = &_DestroyImplData, .pfnGetDevPAddr = &_GetDevPAddr, .pfnGetCPUPAddr = &_GetCPUPAddr, .pfnGetSize = &_GetSize, + .pfnGetPageShift = &_GetPageShift, .pfnGetPMRFactoryMemStats = &PhysmemGetLocalRamMemStats, .pfnCreatePMR = &PhysmemNewLocalRamBackedPMR, +#if defined(SUPPORT_GPUVIRT_VALIDATION) + .pfnPagesAllocGPV = &LMA_PhyContigPagesAllocGPV, +#endif + .pfnPagesAlloc = &LMA_PhyContigPagesAlloc, + .pfnPagesFree = &LMA_PhyContigPagesFree, + .pfnPagesMap = &LMA_PhyContigPagesMap, + .pfnPagesUnMap = &LMA_PhyContigPagesUnmap, + .pfnPagesClean = &LMA_PhyContigPagesClean, }; PVRSRV_ERROR @@ -1004,7 +1303,9 @@ PMRSysPhysAddrLocalMem(PMR_IMPL_PRIVDATA pvPriv, uiAllocIndex = puiOffset[idx] >> uiLog2AllocSize; uiInAllocOffset = puiOffset[idx] - (uiAllocIndex << uiLog2AllocSize); - PVR_ASSERT(uiAllocIndex < uiNumAllocs); + PVR_LOG_RETURN_IF_FALSE(uiAllocIndex < uiNumAllocs, + "puiOffset out of range", PVRSRV_ERROR_OUT_OF_RANGE); + PVR_ASSERT(uiInAllocOffset < (1ULL << uiLog2AllocSize)); psDevPAddr[idx].uiAddr = psLMAllocArrayData->pasDevPAddr[uiAllocIndex].uiAddr + uiInAllocOffset; @@ -1617,7 +1918,11 @@ PhysmemNewLocalRamBackedPMR(PHYS_HEAP *psPhysHeap, bOnDemand = PVRSRV_CHECK_ON_DEMAND(uiFlags) ? IMG_TRUE : IMG_FALSE; bZero = PVRSRV_CHECK_ZERO_ON_ALLOC(uiFlags) ? IMG_TRUE : IMG_FALSE; bPoisonOnAlloc = PVRSRV_CHECK_POISON_ON_ALLOC(uiFlags) ? IMG_TRUE : IMG_FALSE; +#if defined(DEBUG) bPoisonOnFree = PVRSRV_CHECK_POISON_ON_FREE(uiFlags) ? IMG_TRUE : IMG_FALSE; +#else + bPoisonOnFree = IMG_FALSE; +#endif /* Create Array structure that holds the physical pages */ eError = _AllocLMPageArray(uiChunkSize * ui32NumVirtChunks, diff --git a/drivers/gpu/drm/img-rogue/physmem_lma.h b/drivers/gpu/drm/img-rogue/physmem_lma.h index 2988730fa..51f4257b5 100644 --- a/drivers/gpu/drm/img-rogue/physmem_lma.h +++ b/drivers/gpu/drm/img-rogue/physmem_lma.h @@ -69,10 +69,6 @@ PhysmemCreateHeapLMA(PVRSRV_DEVICE_NODE *psDevNode, IMG_CHAR *pszLabel, PHYS_HEAP **ppsPhysHeap); -PVRSRV_ERROR -PhysmemGetArenaLMA(PHYS_HEAP *psPhysHeap, - RA_ARENA **ppsArena); - /* * PhysmemNewLocalRamBackedPMR * diff --git a/drivers/gpu/drm/img-rogue/physmem_osmem_linux.c b/drivers/gpu/drm/img-rogue/physmem_osmem_linux.c index 3c378fc85..abd628ed9 100644 --- a/drivers/gpu/drm/img-rogue/physmem_osmem_linux.c +++ b/drivers/gpu/drm/img-rogue/physmem_osmem_linux.c @@ -2174,7 +2174,7 @@ _CheckIfIndexInRange(IMG_UINT32 ui32Index, IMG_UINT32 *pui32Indices, IMG_UINT32 if (pui32Indices[ui32Index] >= ui32Limit) { PVR_DPF((PVR_DBG_ERROR, "%s: Given alloc index %u at %u is larger than page array %u.", - __func__, ui32Index, pui32Indices[ui32Index], ui32Limit)); + __func__, pui32Indices[ui32Index], ui32Index, ui32Limit)); return PVRSRV_ERROR_DEVICEMEM_OUT_OF_RANGE; } @@ -2187,7 +2187,7 @@ _CheckIfPageNotAllocated(IMG_UINT32 ui32Index, IMG_UINT32 *pui32Indices, struct if (ppsPageArray[pui32Indices[ui32Index]] != NULL) { PVR_DPF((PVR_DBG_ERROR, "%s: Mapping number %u at page array index %u already exists. " - "Page struct %p", __func__, ui32Index, pui32Indices[ui32Index], + "Page struct %p", __func__, pui32Indices[ui32Index], ui32Index, ppsPageArray[pui32Indices[ui32Index]])); return PVRSRV_ERROR_PMR_MAPPING_ALREADY_EXISTS; } @@ -2444,7 +2444,12 @@ e_free_pool_pages: { _FreeOSPage(0, BIT_ISSET(ui32AllocFlags, FLAG_UNSET_MEMORY_TYPE), ppsTempPageArray[i]); - ppsPageArray[puiAllocIndices[i]] = NULL; + + /* not using _CheckIfIndexInRange() to not print error message */ + if (puiAllocIndices[i] < uiDevPagesAllocated) + { + ppsPageArray[puiAllocIndices[i]] = NULL; + } } e_free_temp_array: @@ -3008,6 +3013,13 @@ PMRUnlockSysPhysAddressesOSMem(PMR_IMPL_PRIVDATA pvPriv) return eError; } +static INLINE IMG_BOOL IsOffsetValid(const PMR_OSPAGEARRAY_DATA *psOSPageArrayData, + IMG_UINT32 ui32Offset) +{ + return (ui32Offset >> psOSPageArrayData->uiLog2AllocPageSize) < + psOSPageArrayData->uiTotalNumOSPages; +} + /* Determine PA for specified offset into page array. */ static IMG_DEV_PHYADDR GetOffsetPA(const PMR_OSPAGEARRAY_DATA *psOSPageArrayData, IMG_UINT32 ui32Offset) @@ -3017,7 +3029,6 @@ static IMG_DEV_PHYADDR GetOffsetPA(const PMR_OSPAGEARRAY_DATA *psOSPageArrayData IMG_UINT32 ui32InPageOffset = ui32Offset - (ui32PageIndex << ui32Log2AllocPageSize); IMG_DEV_PHYADDR sPA; - PVR_ASSERT(ui32PageIndex < psOSPageArrayData->uiTotalNumOSPages); PVR_ASSERT(ui32InPageOffset < (1U << ui32Log2AllocPageSize)); sPA.uiAddr = page_to_phys(psOSPageArrayData->pagearray[ui32PageIndex]); @@ -3052,6 +3063,9 @@ PMRSysPhysAddrOSMem(PMR_IMPL_PRIVDATA pvPriv, { if (pbValid[uiIdx]) { + PVR_LOG_RETURN_IF_FALSE(IsOffsetValid(psOSPageArrayData, puiOffset[uiIdx]), + "puiOffset out of range", PVRSRV_ERROR_OUT_OF_RANGE); + psDevPAddr[uiIdx] = GetOffsetPA(psOSPageArrayData, puiOffset[uiIdx]); #if !defined(PVR_LINUX_PHYSMEM_USE_HIGHMEM_ONLY) @@ -3740,11 +3754,13 @@ static void _EncodeAllocationFlags(IMG_UINT32 uiLog2AllocPageSize, BIT_SET(*ui32AllocFlags, FLAG_POISON_ON_ALLOC); } +#if defined(DEBUG) /* Poison on free? */ if (PVRSRV_CHECK_POISON_ON_FREE(uiFlags)) { BIT_SET(*ui32AllocFlags, FLAG_POISON_ON_FREE); } +#endif /* Indicate whether this is an allocation with default caching attribute (i.e cached) or not */ if (PVRSRV_CHECK_CPU_UNCACHED(uiFlags) || diff --git a/drivers/gpu/drm/img-rogue/physmem_test.c b/drivers/gpu/drm/img-rogue/physmem_test.c index 1241fd325..3874594dc 100644 --- a/drivers/gpu/drm/img-rogue/physmem_test.c +++ b/drivers/gpu/drm/img-rogue/physmem_test.c @@ -159,8 +159,6 @@ PhysMemTestInit(PVRSRV_DEVICE_NODE **ppsDeviceNode, PVRSRV_DEVICE_CONFIG *psDevC eError = PVRSRVPhysMemHeapsInit(psDeviceNode, psDevConfig); PVR_LOG_GOTO_IF_ERROR(eError, "PVRSRVPhysMemHeapsInit", ErrorSysDevDeInit); - psDeviceNode->sDevMMUPxSetup.uiMMUPxLog2AllocGran = OSGetPageShift(); - *ppsDeviceNode = psDeviceNode; return PVRSRV_OK; diff --git a/drivers/gpu/drm/img-rogue/plato_drv.h b/drivers/gpu/drm/img-rogue/plato_drv.h index 9ad9c7d3f..3a0414b86 100644 --- a/drivers/gpu/drm/img-rogue/plato_drv.h +++ b/drivers/gpu/drm/img-rogue/plato_drv.h @@ -343,6 +343,8 @@ struct plato_device { /* 396 MHz (~400 MHz) on HW, around 1MHz on the emulator */ #if defined(EMULATOR) || defined(VIRTUAL_PLATFORM) #define PLATO_RGX_CORE_CLOCK_SPEED (1000000) +#define PLATO_RGX_MIN_CORE_CLOCK_SPEED (1000000) +#define PLATO_RGX_MAX_CORE_CLOCK_SPEED (1000000) #else #define PLATO_RGX_CORE_CLOCK_SPEED (396000000) diff --git a/drivers/gpu/drm/img-rogue/pmr.c b/drivers/gpu/drm/img-rogue/pmr.c index 3458c6c0f..8c4575b7b 100644 --- a/drivers/gpu/drm/img-rogue/pmr.c +++ b/drivers/gpu/drm/img-rogue/pmr.c @@ -1768,14 +1768,13 @@ IMG_BOOL PMR_IsMemLayoutFixed(PMR *psPMR) return psPMR->bNoLayoutChange; } -PVRSRV_ERROR +void PMR_LogicalSize(const PMR *psPMR, IMG_DEVMEM_SIZE_T *puiLogicalSize) { PVR_ASSERT(psPMR != NULL); *puiLogicalSize = psPMR->uiLogicalSize; - return PVRSRV_OK; } PVRSRV_ERROR @@ -1917,7 +1916,7 @@ PMR_DevPhysAddr(const PMR *psPMR, if (ui32NumOfPages > PMR_MAX_TRANSLATION_STACK_ALLOC) { puiPhysicalOffset = OSAllocMem(ui32NumOfPages * sizeof(IMG_DEVMEM_OFFSET_T)); - PVR_GOTO_IF_NOMEM(puiPhysicalOffset, eError, e0); + PVR_RETURN_IF_NOMEM(puiPhysicalOffset); } _PMRLogicalOffsetToPhysicalOffset(psPMR, @@ -1936,13 +1935,17 @@ PMR_DevPhysAddr(const PMR *psPMR, puiPhysicalOffset, pbValid, psDevAddrPtr); -#if defined(PVR_PMR_TRANSLATE_UMA_ADDRESSES) - /* Currently excluded from the default build because of performance concerns. - * We do not need this part in all systems because the GPU has the same address view of system RAM as the CPU. - * Alternatively this could be implemented as part of the PMR-factories directly */ + PVR_GOTO_IF_ERROR(eError, FreeOffsetArray); +#if defined(PVR_PMR_TRANSLATE_UMA_ADDRESSES) + /* Currently excluded from the default build because of performance + * concerns. + * We do not need this part in all systems because the GPU has the same + * address view of system RAM as the CPU. + * Alternatively this could be implemented as part of the PMR-factories + * directly */ if (PhysHeapGetType(psPMR->psPhysHeap) == PHYS_HEAP_TYPE_UMA || - PhysHeapGetType(psPMR->psPhysHeap) == PHYS_HEAP_TYPE_DMA) + PhysHeapGetType(psPMR->psPhysHeap) == PHYS_HEAP_TYPE_DMA) { IMG_UINT32 i; IMG_DEV_PHYADDR sDevPAddrCorrected; @@ -1960,17 +1963,12 @@ PMR_DevPhysAddr(const PMR *psPMR, #endif } +FreeOffsetArray: if (puiPhysicalOffset != auiPhysicalOffset) { OSFreeMem(puiPhysicalOffset); } - PVR_GOTO_IF_ERROR(eError, e0); - - return PVRSRV_OK; - -e0: - PVR_ASSERT(eError != PVRSRV_OK); return eError; } @@ -2229,7 +2227,7 @@ PMR_PDumpSymbolicAddr(const PMR *psPMR, /* Confirm that the device node's ui32InternalID matches the bound * PDump device stored* in PVRSRV_DATA. */ - if (!PDumpIsPermitted(PMR_DeviceNode(psPMR))) + if (!PDumpIsDevicePermitted(PMR_DeviceNode(psPMR))) { return PVRSRV_OK; } @@ -2287,7 +2285,7 @@ PMRPDumpLoadMemValue32(PMR *psPMR, /* Confirm that the device node's ui32InternalID matches the bound * PDump device stored* in PVRSRV_DATA. */ - if (!PDumpIsPermitted(PMR_DeviceNode(psPMR))) + if (!PDumpIsDevicePermitted(PMR_DeviceNode(psPMR))) { return PVRSRV_OK; } @@ -2451,7 +2449,7 @@ PMRPDumpLoadMemValue64(PMR *psPMR, /* Confirm that the device node's ui32InternalID matches the bound * PDump device stored in PVRSRV_DATA. */ - if (!PDumpIsPermitted(PMR_DeviceNode(psPMR))) + if (!PDumpIsDevicePermitted(PMR_DeviceNode(psPMR))) { return PVRSRV_OK; } @@ -2628,7 +2626,7 @@ PMRPDumpLoadMem(PMR *psPMR, /* Confirm that the device node's ui32InternalID matches the bound * PDump device stored* in PVRSRV_DATA. */ - if (!PDumpIsPermitted(psDevNode)) + if (!PDumpIsDevicePermitted(psDevNode)) { return PVRSRV_OK; } @@ -2788,7 +2786,7 @@ PMRPDumpSaveToFile(const PMR *psPMR, /* Confirm that the device node's ui32InternalID matches the bound * PDump device stored* in PVRSRV_DATA. */ - if (!PDumpIsPermitted(PMR_DeviceNode(psPMR))) + if (!PDumpIsDevicePermitted(PMR_DeviceNode(psPMR))) { return PVRSRV_OK; } @@ -2848,7 +2846,7 @@ PMRPDumpPol32(const PMR *psPMR, /* Confirm that the device node's ui32InternalID matches the bound * PDump device stored* in PVRSRV_DATA. */ - if (!PDumpIsPermitted(PMR_DeviceNode(psPMR))) + if (!PDumpIsDevicePermitted(PMR_DeviceNode(psPMR))) { return PVRSRV_OK; } @@ -2908,7 +2906,7 @@ PMRPDumpCheck32(const PMR *psPMR, /* Confirm that the device node's ui32InternalID matches the bound * PDump device stored* in PVRSRV_DATA. */ - if (!PDumpIsPermitted(PMR_DeviceNode(psPMR))) + if (!PDumpIsDevicePermitted(PMR_DeviceNode(psPMR))) { return PVRSRV_OK; } @@ -2969,7 +2967,7 @@ PMRPDumpCBP(const PMR *psPMR, /* Confirm that the device node's ui32InternalID matches the bound * PDump device stored* in PVRSRV_DATA. */ - if (!PDumpIsPermitted(PMR_DeviceNode(psPMR))) + if (!PDumpIsDevicePermitted(PMR_DeviceNode(psPMR))) { return PVRSRV_OK; } @@ -3410,7 +3408,7 @@ PMRWritePMPageList(/* Target PMR, offset, and length */ * buffers */ if (PVRSRV_CHECK_CPU_WRITE_COMBINE(psPageListPMR->uiFlags)) { - OSWriteMemoryBarrier(); + OSWriteMemoryBarrier(NULL); } #if !defined(NO_HARDWARE) diff --git a/drivers/gpu/drm/img-rogue/pmr.h b/drivers/gpu/drm/img-rogue/pmr.h index aff3970d4..6a1f0e844 100644 --- a/drivers/gpu/drm/img-rogue/pmr.h +++ b/drivers/gpu/drm/img-rogue/pmr.h @@ -537,7 +537,7 @@ PMR_IsSparse(const PMR *psPMR); IMG_BOOL PMR_IsUnpinned(const PMR *psPMR); -PVRSRV_ERROR +void PMR_LogicalSize(const PMR *psPMR, IMG_DEVMEM_SIZE_T *puiLogicalSize); diff --git a/drivers/gpu/drm/img-rogue/power.c b/drivers/gpu/drm/img-rogue/power.c index 03983e32e..5ad6695fc 100644 --- a/drivers/gpu/drm/img-rogue/power.c +++ b/drivers/gpu/drm/img-rogue/power.c @@ -728,15 +728,13 @@ PVRSRV_ERROR PVRSRVRegisterPowerDevice(PPVRSRV_DEVICE_NODE psDeviceNode, return PVRSRV_OK; } -PVRSRV_ERROR PVRSRVRemovePowerDevice(PPVRSRV_DEVICE_NODE psDeviceNode) +void PVRSRVRemovePowerDevice(PPVRSRV_DEVICE_NODE psDeviceNode) { if (psDeviceNode->psPowerDev) { OSFreeMem(psDeviceNode->psPowerDev); psDeviceNode->psPowerDev = NULL; } - - return PVRSRV_OK; } PVRSRV_ERROR PVRSRVGetDevicePowerState(PCPVRSRV_DEVICE_NODE psDeviceNode, @@ -797,7 +795,12 @@ PVRSRVDevicePreClockSpeedChange(PPVRSRV_DEVICE_NODE psDeviceNode, if (eError != PVRSRV_OK) { - PVR_DPF((PVR_DBG_WARNING, "%s() failed (%s) in %s()", "PVRSRVDeviceIdleRequestKM", PVRSRVGETERRORSTRING(eError), __func__)); + /* FW Can signal denied when busy with SPM or other work it can not idle */ + if (eError != PVRSRV_ERROR_DEVICE_IDLE_REQUEST_DENIED) + { + PVR_DPF((PVR_DBG_ERROR, "%s: Error (%s) from %s()", __func__, + PVRSRVGETERRORSTRING(eError), "PVRSRVDeviceIdleRequestKM")); + } if (eError != PVRSRV_ERROR_PWLOCK_RELEASED_REACQ_FAILED) { PVRSRVPowerUnlock(psDeviceNode); diff --git a/drivers/gpu/drm/img-rogue/power.h b/drivers/gpu/drm/img-rogue/power.h index 23940a0e1..333e7992e 100644 --- a/drivers/gpu/drm/img-rogue/power.h +++ b/drivers/gpu/drm/img-rogue/power.h @@ -252,10 +252,8 @@ PVRSRV_ERROR PVRSRVRegisterPowerDevice(PPVRSRV_DEVICE_NODE psDeviceNode, @Input psDeviceNode : Device node - @Return PVRSRV_ERROR - ******************************************************************************/ -PVRSRV_ERROR PVRSRVRemovePowerDevice(PPVRSRV_DEVICE_NODE psDeviceNode); +void PVRSRVRemovePowerDevice(PPVRSRV_DEVICE_NODE psDeviceNode); /*! ****************************************************************************** diff --git a/drivers/gpu/drm/img-rogue/powervr/img_drm_fourcc.h b/drivers/gpu/drm/img-rogue/powervr/img_drm_fourcc.h index 4856a8d11..5fd79a6c4 100644 --- a/drivers/gpu/drm/img-rogue/powervr/img_drm_fourcc.h +++ b/drivers/gpu/drm/img-rogue/powervr/img_drm_fourcc.h @@ -114,6 +114,9 @@ THE SOFTWARE. #define DRM_FORMAT_MOD_LINEAR fourcc_mod_code(NONE, 0) #endif +#define DRM_FORMAT_MOD_PVR_FBCDC_8x8_V1 fourcc_mod_code(PVR, 3) +#define DRM_FORMAT_MOD_PVR_FBCDC_16x4_V1 fourcc_mod_code(PVR, 9) + #define DRM_FORMAT_MOD_PVR_FBCDC_8x8_V7 fourcc_mod_code(PVR, 6) #define DRM_FORMAT_MOD_PVR_FBCDC_16x4_V7 fourcc_mod_code(PVR, 12) diff --git a/drivers/gpu/drm/img-rogue/private_data.h b/drivers/gpu/drm/img-rogue/private_data.h index 96a21cd9b..60a1fac0b 100644 --- a/drivers/gpu/drm/img-rogue/private_data.h +++ b/drivers/gpu/drm/img-rogue/private_data.h @@ -46,7 +46,14 @@ CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. #include #include "connection_server.h" +#include "pvr_drm.h" -CONNECTION_DATA *LinuxConnectionFromFile(struct file *pFile); +#define PVR_SRVKM_PRIV_DATA_IDX 0 +#define PVR_SYNC_PRIV_DATA_IDX 1 + +#define PVR_NUM_PRIV_DATA_IDXS 2 + +CONNECTION_DATA *LinuxServicesConnectionFromFile(struct file *pFile); +CONNECTION_DATA *LinuxSyncConnectionFromFile(struct file *pFile); #endif /* !defined(INCLUDED_PRIVATE_DATA_H) */ diff --git a/drivers/gpu/drm/img-rogue/process_stats.c b/drivers/gpu/drm/img-rogue/process_stats.c index df7ab2ebb..5867e2aef 100644 --- a/drivers/gpu/drm/img-rogue/process_stats.c +++ b/drivers/gpu/drm/img-rogue/process_stats.c @@ -120,7 +120,7 @@ int GlobalStatsPrintElements(OSDI_IMPL_ENTRY *psEntry, void *pvData); /* Macros for fetching stat values */ #define GET_STAT_VALUE(ptr,var) (ptr)->i32StatValue[(var)] -#define GET_GLOBAL_STAT_VALUE(idx) gsGlobalStats.ui32StatValue[idx] +#define GET_GLOBAL_STAT_VALUE(idx) gsGlobalStats.ui64StatValue[idx] #define GET_GPUMEM_GLOBAL_STAT_VALUE() \ GET_GLOBAL_STAT_VALUE(PVRSRV_DRIVER_STAT_TYPE_ALLOC_PT_MEMORY_UMA) + \ @@ -140,14 +140,14 @@ int GlobalStatsPrintElements(OSDI_IMPL_ENTRY *psEntry, void *pvData); */ #define UPDATE_MAX_VALUE(a,b) do { if ((b) > (a)) {(a) = (b);} } while (0) #define INCREASE_STAT_VALUE(ptr,var,val) do { (ptr)->i32StatValue[(var)] += (val); if ((ptr)->i32StatValue[(var)] > (ptr)->i32StatValue[(var##_MAX)]) {(ptr)->i32StatValue[(var##_MAX)] = (ptr)->i32StatValue[(var)];} } while (0) -#define INCREASE_GLOBAL_STAT_VALUE(var,idx,val) do { (var).ui32StatValue[(idx)] += (val); if ((var).ui32StatValue[(idx)] > (var).ui32StatValue[(idx##_MAX)]) {(var).ui32StatValue[(idx##_MAX)] = (var).ui32StatValue[(idx)];} } while (0) +#define INCREASE_GLOBAL_STAT_VALUE(var,idx,val) do { (var).ui64StatValue[(idx)] += (val); if ((var).ui64StatValue[(idx)] > (var).ui64StatValue[(idx##_MAX)]) {(var).ui64StatValue[(idx##_MAX)] = (var).ui64StatValue[(idx)];} } while (0) #if defined(PVRSRV_DEBUG_LINUX_MEMORY_STATS) /* Allow stats to go negative */ #define DECREASE_STAT_VALUE(ptr,var,val) do { (ptr)->i32StatValue[(var)] -= (val); } while (0) -#define DECREASE_GLOBAL_STAT_VALUE(var,idx,val) do { (var).ui32StatValue[(idx)] -= (val); } while (0) +#define DECREASE_GLOBAL_STAT_VALUE(var,idx,val) do { (var).ui64StatValue[(idx)] -= (val); } while (0) #else #define DECREASE_STAT_VALUE(ptr,var,val) do { if ((ptr)->i32StatValue[(var)] >= (val)) { (ptr)->i32StatValue[(var)] -= (val); } else { (ptr)->i32StatValue[(var)] = 0; } } while (0) -#define DECREASE_GLOBAL_STAT_VALUE(var,idx,val) do { if ((var).ui32StatValue[(idx)] >= (val)) { (var).ui32StatValue[(idx)] -= (val); } else { (var).ui32StatValue[(idx)] = 0; } } while (0) +#define DECREASE_GLOBAL_STAT_VALUE(var,idx,val) do { if ((var).ui64StatValue[(idx)] >= (val)) { (var).ui64StatValue[(idx)] -= (val); } else { (var).ui64StatValue[(idx)] = 0; } } while (0) #endif #define MAX_CACHEOP_STAT 16 #define INCREMENT_CACHEOP_STAT_IDX_WRAP(x) ((x+1) >= MAX_CACHEOP_STAT ? 0 : (x+1)) @@ -205,7 +205,6 @@ typedef struct _PVRSRV_PROCESS_STATS_ { IMG_DEVMEM_SIZE_T uiSize; IMG_UINT64 ui64ExecuteTime; IMG_BOOL bUserModeFlush; - IMG_UINT32 ui32OpSeqNum; IMG_BOOL bIsFence; IMG_PID ownerPid; } asCacheOp[MAX_CACHEOP_STAT]; @@ -412,7 +411,7 @@ static IMG_HANDLE g_hDriverProcessStats; /* Global driver-data folders */ typedef struct _GLOBAL_STATS_ { - IMG_UINT32 ui32StatValue[PVRSRV_DRIVER_STAT_TYPE_COUNT]; + IMG_UINT64 ui64StatValue[PVRSRV_DRIVER_STAT_TYPE_COUNT]; POS_LOCK hGlobalStatsLock; } GLOBAL_STATS; @@ -2313,13 +2312,14 @@ int RawProcessStatsPrintElements(OSDI_IMPL_ENTRY *psEntry, void *pvData) PVRSRV_PROCESS_STATS *psProcessStats; DIPrintf(psEntry, - "%s,%s,%s,%s,%s,%s\n", + "%s,%s,%s,%s,%s,%s,%s\n", "PID", "MemoryUsageKMalloc", // PVRSRV_PROCESS_STAT_TYPE_KMALLOC "MemoryUsageAllocPTMemoryUMA", // PVRSRV_PROCESS_STAT_TYPE_ALLOC_PAGES_PT_UMA "MemoryUsageAllocPTMemoryLMA", // PVRSRV_PROCESS_STAT_TYPE_ALLOC_PAGES_PT_LMA "MemoryUsageAllocGPUMemLMA", // PVRSRV_PROCESS_STAT_TYPE_ALLOC_LMA_PAGES - "MemoryUsageAllocGPUMemUMA"); // PVRSRV_PROCESS_STAT_TYPE_ALLOC_UMA_PAGES + "MemoryUsageAllocGPUMemUMA", // PVRSRV_PROCESS_STAT_TYPE_ALLOC_UMA_PAGES + "MemoryUsageDmaBufImport"); // PVRSRV_PROCESS_STAT_TYPE_DMA_BUF_IMPORT OSLockAcquire(g_psLinkedListLock); @@ -2330,13 +2330,14 @@ int RawProcessStatsPrintElements(OSDI_IMPL_ENTRY *psEntry, void *pvData) if (psProcessStats->pid != PVR_SYS_ALLOC_PID) { DIPrintf(psEntry, - "%d,%d,%d,%d,%d,%d\n", + "%d,%d,%d,%d,%d,%d,%d\n", psProcessStats->pid, psProcessStats->i32StatValue[PVRSRV_PROCESS_STAT_TYPE_KMALLOC], psProcessStats->i32StatValue[PVRSRV_PROCESS_STAT_TYPE_ALLOC_PAGES_PT_UMA], psProcessStats->i32StatValue[PVRSRV_PROCESS_STAT_TYPE_ALLOC_PAGES_PT_LMA], psProcessStats->i32StatValue[PVRSRV_PROCESS_STAT_TYPE_ALLOC_LMA_PAGES], - psProcessStats->i32StatValue[PVRSRV_PROCESS_STAT_TYPE_ALLOC_UMA_PAGES]); + psProcessStats->i32StatValue[PVRSRV_PROCESS_STAT_TYPE_ALLOC_UMA_PAGES], + psProcessStats->i32StatValue[PVRSRV_PROCESS_STAT_TYPE_DMA_BUF_IMPORT]); } psProcessStats = psProcessStats->psNext; @@ -2806,17 +2807,14 @@ ProcessStatsPrintElements(OSDI_IMPL_ENTRY *psEntry, #if defined(PVRSRV_ENABLE_CACHEOP_STATS) void PVRSRVStatsUpdateCacheOpStats(PVRSRV_CACHE_OP uiCacheOp, - IMG_UINT32 ui32OpSeqNum, #if defined(PVRSRV_ENABLE_GPU_MEMORY_INFO) && defined(DEBUG) IMG_DEV_VIRTADDR sDevVAddr, IMG_DEV_PHYADDR sDevPAddr, - IMG_UINT32 eFenceOpType, #endif IMG_DEVMEM_SIZE_T uiOffset, IMG_DEVMEM_SIZE_T uiSize, IMG_UINT64 ui64ExecuteTime, IMG_BOOL bUserModeFlush, - IMG_BOOL bIsFence, IMG_PID ownerPid) { IMG_PID currentPid = (ownerPid!=0)?ownerPid:OSGetCurrentClientProcessIDKM(); @@ -2848,14 +2846,11 @@ PVRSRVStatsUpdateCacheOpStats(PVRSRV_CACHE_OP uiCacheOp, #if defined(PVRSRV_ENABLE_GPU_MEMORY_INFO) && defined(DEBUG) psProcessStats->asCacheOp[Idx].sDevVAddr = sDevVAddr; psProcessStats->asCacheOp[Idx].sDevPAddr = sDevPAddr; - psProcessStats->asCacheOp[Idx].eFenceOpType = eFenceOpType; #endif psProcessStats->asCacheOp[Idx].uiOffset = uiOffset; psProcessStats->asCacheOp[Idx].uiSize = uiSize; psProcessStats->asCacheOp[Idx].bUserModeFlush = bUserModeFlush; psProcessStats->asCacheOp[Idx].ui64ExecuteTime = ui64ExecuteTime; - psProcessStats->asCacheOp[Idx].ui32OpSeqNum = ui32OpSeqNum; - psProcessStats->asCacheOp[Idx].bIsFence = bIsFence; OSLockRelease(psProcessStats->hLock); } @@ -2878,18 +2873,14 @@ CacheOpStatsPrintElements(OSDI_IMPL_ENTRY *psEntry, #if defined(PVRSRV_ENABLE_GPU_MEMORY_INFO) && defined(DEBUG) #define CACHEOP_RI_PRINTF_HEADER \ - "%-10s %-10s %-5s %-16s %-16s %-10s %-10s %-12s %-12s\n" - #define CACHEOP_RI_PRINTF_FENCE \ - "%-10s %-10s %-5s %-16s %-16s %-10s %-10s %-12llu 0x%-10x\n" + "%-10s %-10s %-5s %-16s %-16s %-10s %-10s %-12s\n" #define CACHEOP_RI_PRINTF \ - "%-10s %-10s %-5s 0x%-14llx 0x%-14llx 0x%-8llx 0x%-8llx %-12llu 0x%-10x\n" + "%-10s %-10s %-5s 0x%-14llx 0x%-14llx 0x%-8llx 0x%-8llx %-12llu\n" #else #define CACHEOP_PRINTF_HEADER \ - "%-10s %-10s %-5s %-10s %-10s %-12s %-12s\n" - #define CACHEOP_PRINTF_FENCE \ - "%-10s %-10s %-5s %-10s %-10s %-12llu 0x%-10x\n" + "%-10s %-10s %-5s %-10s %-10s %-12s\n" #define CACHEOP_PRINTF \ - "%-10s %-10s %-5s 0x%-8llx 0x%-8llx %-12llu 0x%-10x\n" + "%-10s %-10s %-5s 0x%-8llx 0x%-8llx %-12llu\n" #endif DIPrintf(psEntry, "PID %u\n", psProcessStats->pid); @@ -2910,8 +2901,7 @@ CacheOpStatsPrintElements(OSDI_IMPL_ENTRY *psEntry, #endif "Offset", "Size", - "Time (us)", - "SeqNo"); + "Time (us)"); /* Take a snapshot of write index, read backwards in buffer and wrap round at boundary */ @@ -2920,111 +2910,47 @@ CacheOpStatsPrintElements(OSDI_IMPL_ENTRY *psEntry, i32ReadIdx != i32WriteIdx; i32ReadIdx = DECREMENT_CACHEOP_STAT_IDX_WRAP(i32ReadIdx)) { - IMG_UINT64 ui64ExecuteTime; + IMG_UINT64 ui64ExecuteTime = psProcessStats->asCacheOp[i32ReadIdx].ui64ExecuteTime; + IMG_DEVMEM_SIZE_T ui64NumOfPages = psProcessStats->asCacheOp[i32ReadIdx].uiSize >> OSGetPageShift(); - if (! psProcessStats->asCacheOp[i32ReadIdx].ui32OpSeqNum) + if (ui64NumOfPages <= PMR_MAX_TRANSLATION_STACK_ALLOC) { - break; - } - - ui64ExecuteTime = psProcessStats->asCacheOp[i32ReadIdx].ui64ExecuteTime; - - if (psProcessStats->asCacheOp[i32ReadIdx].bIsFence) - { - IMG_CHAR *pszFenceType = ""; - pszCacheOpType = "Fence"; - -#if defined(PVRSRV_ENABLE_GPU_MEMORY_INFO) && defined(DEBUG) - switch (psProcessStats->asCacheOp[i32ReadIdx].eFenceOpType) - { - case RGXFWIF_DM_GP: - pszFenceType = "GP"; - break; - - case RGXFWIF_DM_TDM: - /* Also case RGXFWIF_DM_2D: */ - pszFenceType = "TDM/2D"; - break; - - case RGXFWIF_DM_GEOM: - pszFenceType = "GEOM"; - break; - - case RGXFWIF_DM_3D: - pszFenceType = "3D"; - break; - - case RGXFWIF_DM_CDM: - pszFenceType = "CDM"; - break; - - default: - PVR_ASSERT(0); - break; - } -#endif - - DIPrintf(psEntry, -#if defined(PVRSRV_ENABLE_GPU_MEMORY_INFO) && defined(DEBUG) - CACHEOP_RI_PRINTF_FENCE, -#else - CACHEOP_PRINTF_FENCE, -#endif - pszCacheOpType, - pszFenceType, - "", -#if defined(PVRSRV_ENABLE_GPU_MEMORY_INFO) && defined(DEBUG) - "", - "", -#endif - "", - "", - ui64ExecuteTime, - psProcessStats->asCacheOp[i32ReadIdx].ui32OpSeqNum); + pszFlushType = "RBF.Fast"; } else { - IMG_DEVMEM_SIZE_T ui64NumOfPages; + pszFlushType = "RBF.Slow"; + } - ui64NumOfPages = psProcessStats->asCacheOp[i32ReadIdx].uiSize >> OSGetPageShift(); - if (ui64NumOfPages <= PMR_MAX_TRANSLATION_STACK_ALLOC) - { - pszFlushType = "RBF.Fast"; - } - else - { - pszFlushType = "RBF.Slow"; - } + if (psProcessStats->asCacheOp[i32ReadIdx].bUserModeFlush) + { + pszFlushMode = "UM"; + } + else + { + pszFlushMode = "KM"; + } - if (psProcessStats->asCacheOp[i32ReadIdx].bUserModeFlush) - { - pszFlushMode = "UM"; - } - else - { - pszFlushMode = "KM"; - } + switch (psProcessStats->asCacheOp[i32ReadIdx].uiCacheOp) + { + case PVRSRV_CACHE_OP_NONE: + pszCacheOpType = "None"; + break; + case PVRSRV_CACHE_OP_CLEAN: + pszCacheOpType = "Clean"; + break; + case PVRSRV_CACHE_OP_INVALIDATE: + pszCacheOpType = "Invalidate"; + break; + case PVRSRV_CACHE_OP_FLUSH: + pszCacheOpType = "Flush"; + break; + default: + pszCacheOpType = "Unknown"; + break; + } - switch (psProcessStats->asCacheOp[i32ReadIdx].uiCacheOp) - { - case PVRSRV_CACHE_OP_NONE: - pszCacheOpType = "None"; - break; - case PVRSRV_CACHE_OP_CLEAN: - pszCacheOpType = "Clean"; - break; - case PVRSRV_CACHE_OP_INVALIDATE: - pszCacheOpType = "Invalidate"; - break; - case PVRSRV_CACHE_OP_FLUSH: - pszCacheOpType = "Flush"; - break; - default: - pszCacheOpType = "Unknown"; - break; - } - - DIPrintf(psEntry, + DIPrintf(psEntry, #if defined(PVRSRV_ENABLE_GPU_MEMORY_INFO) && defined(DEBUG) CACHEOP_RI_PRINTF, #else @@ -3039,10 +2965,9 @@ CacheOpStatsPrintElements(OSDI_IMPL_ENTRY *psEntry, #endif psProcessStats->asCacheOp[i32ReadIdx].uiOffset, psProcessStats->asCacheOp[i32ReadIdx].uiSize, - ui64ExecuteTime, - psProcessStats->asCacheOp[i32ReadIdx].ui32OpSeqNum); + ui64ExecuteTime); } - } + } /* CacheOpStatsPrintElements */ #endif @@ -3256,7 +3181,7 @@ int GlobalStatsPrintElements(OSDI_IMPL_ENTRY *psEntry, void *pvData) { if (OSStringNCompare(pszDriverStatType[ui32StatNumber], "", 1) != 0) { - DIPrintf(psEntry, "%-34s%10d\n", + DIPrintf(psEntry, "%-34s%12llu\n", pszDriverStatType[ui32StatNumber], GET_GLOBAL_STAT_VALUE(ui32StatNumber)); } diff --git a/drivers/gpu/drm/img-rogue/process_stats.h b/drivers/gpu/drm/img-rogue/process_stats.h index a34815266..400399736 100644 --- a/drivers/gpu/drm/img-rogue/process_stats.h +++ b/drivers/gpu/drm/img-rogue/process_stats.h @@ -46,6 +46,7 @@ CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. #include #include "pvrsrv_error.h" +#include "allocmem.h" #include "cache_ops.h" /* @@ -95,35 +96,6 @@ void PVRSRVStatsDeregisterProcess(IMG_HANDLE hProcessStats); * Functions for recording the statistics... */ -/* - * PVRSRV_ENABLE_PROCESS_STATS enables process statistics regarding events, - * resources and memory across all processes - * PVRSRV_ENABLE_MEMORY_STATS enables recording of Linux kernel memory - * allocations, provided that PVRSRV_ENABLE_PROCESS_STATS is enabled - * - Output can be found in: - * /(sys/kernel/debug|proc)/pvr/proc_stats/[live|retired]_pids_stats/mem_area - * PVRSRV_DEBUG_LINUX_MEMORY_STATS provides more details about memory - * statistics in conjunction with PVRSRV_ENABLE_MEMORY_STATS - * PVRSRV_DEBUG_LINUX_MEMORY_STATS_ON is defined to encompass both memory - * allocation statistics functionalities described above in a single macro - */ -#if defined(PVRSRV_ENABLE_PROCESS_STATS) && defined(PVRSRV_ENABLE_MEMORY_STATS) && defined(PVRSRV_DEBUG_LINUX_MEMORY_STATS) && defined(DEBUG) -#define PVRSRV_DEBUG_LINUX_MEMORY_STATS_ON -#endif - -/* - * When using detailed memory allocation statistics, the line number and - * file name where the allocation happened are also provided. - * When this feature is not used, these parameters are not needed. - */ -#if defined(PVRSRV_DEBUG_LINUX_MEMORY_STATS_ON) -#define DEBUG_MEMSTATS_PARAMS ,void *pvAllocFromFile, IMG_UINT32 ui32AllocFromLine -#define DEBUG_MEMSTATS_VALUES ,__FILE__, __LINE__ -#else -#define DEBUG_MEMSTATS_PARAMS -#define DEBUG_MEMSTATS_VALUES -#endif - void PVRSRVStatsAddMemAllocRecord(PVRSRV_MEM_ALLOC_TYPE eAllocType, void *pvCpuVAddr, IMG_CPU_PHYADDR sCpuPAddr, @@ -198,17 +170,14 @@ void PVRSRVStatsUpdateFreelistStats(IMG_UINT32 ui32NumGrowReqByApp, IMG_PID ownerPid); #if defined(PVRSRV_ENABLE_CACHEOP_STATS) void PVRSRVStatsUpdateCacheOpStats(PVRSRV_CACHE_OP uiCacheOp, - IMG_UINT32 ui32OpSeqNum, #if defined(PVRSRV_ENABLE_GPU_MEMORY_INFO) && defined(DEBUG) IMG_DEV_VIRTADDR sDevVAddr, IMG_DEV_PHYADDR sDevPAddr, - IMG_UINT32 eFenceOpType, #endif IMG_DEVMEM_SIZE_T uiOffset, IMG_DEVMEM_SIZE_T uiSize, IMG_UINT64 ui64ExecuteTimeMs, IMG_BOOL bUserModeFlush, - IMG_BOOL bIsFence, IMG_PID ownerPid); #endif diff --git a/drivers/gpu/drm/img-rogue/pvr_bridge_k.c b/drivers/gpu/drm/img-rogue/pvr_bridge_k.c index d42064829..7211ef025 100644 --- a/drivers/gpu/drm/img-rogue/pvr_bridge_k.c +++ b/drivers/gpu/drm/img-rogue/pvr_bridge_k.c @@ -81,7 +81,7 @@ CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. #include "common_srvcore_bridge.h" PVRSRV_ERROR InitDMABUFBridge(void); -PVRSRV_ERROR DeinitDMABUFBridge(void); +void DeinitDMABUFBridge(void); #if defined(MODULE_TEST) /************************************************************************/ @@ -253,7 +253,10 @@ PVRSRV_ERROR OSPlatformBridgeInit(void) .pfnStop = BridgeStatsDIStop, .pfnNext = BridgeStatsDINext, .pfnShow = BridgeStatsDIShow, - .pfnWrite = BridgeStatsWrite + .pfnWrite = BridgeStatsWrite, + + //Expects '0' + Null terminator + .ui32WriteLenMax = ((1U)+1U) }; eError = DICreateEntry("bridge_stats", NULL, &sIter, @@ -275,10 +278,8 @@ error_: return eError; } -PVRSRV_ERROR OSPlatformBridgeDeInit(void) +void OSPlatformBridgeDeInit(void) { - PVRSRV_ERROR eError; - #if defined(DEBUG_BRIDGE_KM) if (gpsDIBridgeStatsEntry != NULL) { @@ -286,15 +287,12 @@ PVRSRV_ERROR OSPlatformBridgeDeInit(void) } #endif - eError = DeinitDMABUFBridge(); - PVR_LOG_RETURN_IF_ERROR(eError, "DeinitDMABUFBridge"); + DeinitDMABUFBridge(); if (g_hDriverThreadEventObject != NULL) { OSEventObjectDestroy(g_hDriverThreadEventObject); g_hDriverThreadEventObject = NULL; } - - return eError; } PVRSRV_ERROR LinuxBridgeBlockClientsAccess(IMG_BOOL bShutdown) @@ -485,12 +483,12 @@ PVRSRV_BridgeDispatchKM(struct drm_device __maybe_unused *dev, void *arg, struct { struct drm_pvr_srvkm_cmd *psSrvkmCmd = (struct drm_pvr_srvkm_cmd *) arg; PVRSRV_BRIDGE_PACKAGE sBridgePackageKM = { 0 }; - CONNECTION_DATA *psConnection = LinuxConnectionFromFile(pDRMFile->filp); + CONNECTION_DATA *psConnection = LinuxServicesConnectionFromFile(pDRMFile->filp); PVRSRV_ERROR error; if (psConnection == NULL) { - PVR_DPF((PVR_DBG_ERROR, "%s: Connection is closed", __func__)); + PVR_DPF((PVR_DBG_ERROR, "Invalid connection data")); return -EFAULT; } @@ -524,7 +522,7 @@ e0: int PVRSRV_MMap(struct file *pFile, struct vm_area_struct *ps_vma) { - CONNECTION_DATA *psConnection = LinuxConnectionFromFile(pFile); + CONNECTION_DATA *psConnection = LinuxServicesConnectionFromFile(pFile); IMG_HANDLE hSecurePMRHandle = (IMG_HANDLE)((uintptr_t)ps_vma->vm_pgoff); PMR *psPMR; PVRSRV_ERROR eError; diff --git a/drivers/gpu/drm/img-rogue/pvr_buffer_sync.c b/drivers/gpu/drm/img-rogue/pvr_buffer_sync.c index 4a67d7a43..b5426d402 100644 --- a/drivers/gpu/drm/img-rogue/pvr_buffer_sync.c +++ b/drivers/gpu/drm/img-rogue/pvr_buffer_sync.c @@ -50,7 +50,6 @@ #include "pvr_drv.h" #include "pvr_fence.h" - struct pvr_buffer_sync_context { struct mutex ctx_lock; struct pvr_fence_context *fence_ctx; @@ -191,8 +190,8 @@ pvr_buffer_sync_pmrs_fence_count(u32 nr_pmrs, struct _PMR_ **pmrs, if (WARN_ON_ONCE(!resv)) continue; - resv_list = dma_resv_get_list(resv); - fence = dma_resv_get_excl(resv); + resv_list = dma_resv_shared_list(resv); + fence = dma_resv_excl_fence(resv); if (fence && (!exclusive || !resv_list || !resv_list->shared_count)) @@ -250,8 +249,8 @@ pvr_buffer_sync_check_fences_create(struct pvr_fence_context *fence_ctx, goto err_destroy_fences; } - resv_list = dma_resv_get_list(resv); - fence = dma_resv_get_excl(resv); + resv_list = dma_resv_shared_list(resv); + fence = dma_resv_excl_fence(resv); if (fence && (!exclusive || !resv_list || !resv_list->shared_count)) { diff --git a/drivers/gpu/drm/img-rogue/pvr_debug.h b/drivers/gpu/drm/img-rogue/pvr_debug.h index 003afd490..56bbb13f1 100644 --- a/drivers/gpu/drm/img-rogue/pvr_debug.h +++ b/drivers/gpu/drm/img-rogue/pvr_debug.h @@ -119,7 +119,7 @@ __noreturn void klocwork_abort(void); * them. */ #if defined(__KLOCWORK__) -#define PVR_ASSERT(x) do { if (!(x)) {klocwork_abort();} } while (0) +#define PVR_ASSERT(x) do { if (!(x)) {klocwork_abort();} } while (false) #else /* ! __KLOCWORKS__ */ #if defined(_WIN32) @@ -133,7 +133,7 @@ __noreturn void klocwork_abort(void); __debugbreak(); \ } \ MSC_SUPPRESS_4127 \ - } while (0) + } while (false) #else @@ -152,7 +152,7 @@ __noreturn void klocwork_abort(void); "Debug assertion failed!"); \ WARN_ON(1); \ } \ - } while (0) + } while (false) #else /* defined(__linux__) && defined(__KERNEL__) */ @@ -177,14 +177,14 @@ PVRSRVDebugAssertFail(const IMG_CHAR *pszFile, { \ PVRSRVDebugAssertFail(__FILE__, __LINE__, #EXPR); \ } \ - } while (0) + } while (false) #endif /* defined(__linux__) && defined(__KERNEL__) */ #endif /* defined(_WIN32) */ #endif /* defined(__KLOCWORK__) */ #if defined(__KLOCWORK__) - #define PVR_DBG_BREAK do { klocwork_abort(); } while (0) + #define PVR_DBG_BREAK do { klocwork_abort(); } while (false) #else #if defined(WIN32) #define PVR_DBG_BREAK __debugbreak() /*!< Implementation of PVR_DBG_BREAK for (non-WinCE) Win32 */ @@ -214,8 +214,8 @@ PVRSRVDebugAssertFail(const IMG_CHAR *pszFile, * macros in a special way when the code is analysed by Klocwork avoids * them. */ - #if defined(__KLOCWORK__) - #define PVR_ASSERT(EXPR) do { if (!(EXPR)) {klocwork_abort();} } while (0) + #if defined(__KLOCWORK__) && !defined(SERVICES_SC) + #define PVR_ASSERT(EXPR) do { if (!(EXPR)) {klocwork_abort();} } while (false) #else #define PVR_ASSERT(EXPR) (void)(EXPR) /*!< Null Implementation of PVR_ASSERT (does nothing) */ #endif @@ -294,21 +294,21 @@ PVRSRVDebugAssertFail(const IMG_CHAR *pszFile, PVR_DPF((PVR_DBG_ERROR, "%s() failed (%s) in %s()", _call, PVRSRVGETERRORSTRING(_rc), __func__)); \ } \ MSC_SUPPRESS_4127\ - } while (0) + } while (false) #define PVR_WARN_IF_ERROR(_rc, _call) do \ { if (unlikely(_rc != PVRSRV_OK)) { \ PVR_DPF((PVR_DBG_WARNING, "%s() failed (%s) in %s()", _call, PVRSRVGETERRORSTRING(_rc), __func__)); \ } \ MSC_SUPPRESS_4127\ - } while (0) + } while (false) #define PVR_LOG_RETURN_IF_NOMEM(_expr, _call) do \ { if (unlikely(_expr == NULL)) { \ PVR_DPF((PVR_DBG_ERROR, "%s failed (PVRSRV_ERROR_OUT_OF_MEMORY) in %s()", _call, __func__)); \ return PVRSRV_ERROR_OUT_OF_MEMORY; } \ MSC_SUPPRESS_4127\ - } while (0) + } while (false) #define PVR_LOG_GOTO_IF_NOMEM(_expr, _err, _go) do \ { if (unlikely(_expr == NULL)) { \ @@ -316,70 +316,70 @@ PVRSRVDebugAssertFail(const IMG_CHAR *pszFile, _err = PVRSRV_ERROR_OUT_OF_MEMORY; \ goto _go; } \ MSC_SUPPRESS_4127\ - } while (0) + } while (false) #define PVR_LOG_RETURN_IF_ERROR(_rc, _call) do \ { if (unlikely(_rc != PVRSRV_OK)) { \ PVR_DPF((PVR_DBG_ERROR, "%s() failed (%s) in %s()", _call, PVRSRVGETERRORSTRING(_rc), __func__)); \ return _rc; } \ MSC_SUPPRESS_4127\ - } while (0) + } while (false) #define PVR_LOG_RETURN_VOID_IF_ERROR(_rc, _call) do \ { if (unlikely(_rc != PVRSRV_OK)) { \ PVR_DPF((PVR_DBG_ERROR, "%s() failed (%s) in %s()", _call, PVRSRVGETERRORSTRING(_rc), __func__)); \ return; } \ MSC_SUPPRESS_4127\ - } while (0) + } while (false) #define PVR_LOG_GOTO_IF_ERROR(_rc, _call, _go) do \ { if (unlikely(_rc != PVRSRV_OK)) { \ PVR_DPF((PVR_DBG_ERROR, "%s() failed (%s) in %s()", _call, PVRSRVGETERRORSTRING(_rc), __func__)); \ goto _go; } \ MSC_SUPPRESS_4127\ - } while (0) + } while (false) #define PVR_LOG_GOTO_WITH_ERROR(_call, _err, _rc, _go) do \ { PVR_DPF((PVR_DBG_ERROR, "%s() failed (%s) in %s()", _call, PVRSRVGETERRORSTRING(_rc), __func__)); \ _err = _rc; \ goto _go; \ MSC_SUPPRESS_4127\ - } while (0) + } while (false) #define PVR_LOG_IF_FALSE(_expr, _msg) do \ { if (unlikely(!(_expr))) { \ PVR_DPF((PVR_DBG_ERROR, "%s in %s()", _msg, __func__)); \ } \ MSC_SUPPRESS_4127\ - } while (0) + } while (false) #define PVR_LOG_RETURN_IF_FALSE(_expr, _msg, _rc) do \ { if (unlikely(!(_expr))) { \ PVR_DPF((PVR_DBG_ERROR, "%s in %s()", _msg, __func__)); \ return _rc; } \ MSC_SUPPRESS_4127\ - } while (0) + } while (false) #define PVR_LOG_RETURN_VOID_IF_FALSE(_expr, _msg) do \ { if (unlikely(!(_expr))) { \ PVR_DPF((PVR_DBG_ERROR, "%s in %s()", _msg, __func__)); \ return; } \ MSC_SUPPRESS_4127\ - } while (0) + } while (false) #define PVR_LOG_GOTO_IF_FALSE(_expr, _msg, _go) do \ { if (unlikely(!(_expr))) { \ PVR_DPF((PVR_DBG_ERROR, "%s in %s()", _msg, __func__)); \ goto _go; } \ MSC_SUPPRESS_4127\ - } while (0) + } while (false) #define PVR_LOG_RETURN_IF_INVALID_PARAM(_expr, _param) do \ { if (unlikely(!(_expr))) { \ PVR_DPF((PVR_DBG_ERROR, "%s invalid in %s()", _param, __func__)); \ return PVRSRV_ERROR_INVALID_PARAMS; } \ MSC_SUPPRESS_4127\ - } while (0) + } while (false) #define PVR_LOG_GOTO_IF_INVALID_PARAM(_expr, _err, _go) do \ { if (unlikely(!(_expr))) { \ @@ -387,7 +387,7 @@ PVRSRVDebugAssertFail(const IMG_CHAR *pszFile, _err = PVRSRV_ERROR_INVALID_PARAMS; \ goto _go; } \ MSC_SUPPRESS_4127\ - } while (0) + } while (false) #define PVR_LOG_MSG(_lvl, _msg) \ PVR_DPF((_lvl, ("In %s() "_msg), __func__)) @@ -400,42 +400,42 @@ PVRSRVDebugAssertFail(const IMG_CHAR *pszFile, PVR_DPF((_lvl, ("In %s() "_msg), __func__, __VA_ARGS__)); \ } \ MSC_SUPPRESS_4127\ - } while (0) + } while (false) #define PVR_LOG_IF_FALSE_VA(_lvl, _expr, _msg, ...) do \ { if (unlikely(!(_expr))) { \ PVR_DPF((_lvl, ("In %s() "_msg), __func__, __VA_ARGS__)); \ } \ MSC_SUPPRESS_4127\ - } while (0) + } while (false) #define PVR_LOG_RETURN_IF_ERROR_VA(_rc, _msg, ...) do \ { if (unlikely(_rc != PVRSRV_OK)) { \ PVR_DPF((PVR_DBG_ERROR, ("In %s() "_msg), __func__, __VA_ARGS__)); \ return _rc; \ } MSC_SUPPRESS_4127\ - } while (0) + } while (false) #define PVR_LOG_GOTO_IF_ERROR_VA(_rc, _go, _msg, ...) do \ { if (unlikely(_rc != PVRSRV_OK)) { \ PVR_DPF((PVR_DBG_ERROR, ("In %s() "_msg), __func__, __VA_ARGS__)); \ goto _go; \ } MSC_SUPPRESS_4127\ - } while (0) + } while (false) #define PVR_LOG_RETURN_IF_FALSE_VA(_expr, _rc, _msg, ...) do \ { if (unlikely(!(_expr))) { \ PVR_DPF((PVR_DBG_ERROR, ("At %s: "_msg), __func__, __VA_ARGS__)); \ return _rc; \ } MSC_SUPPRESS_4127\ - } while (0) + } while (false) #define PVR_LOG_GOTO_IF_FALSE_VA(_expr, _go, _msg, ...) do \ { if (unlikely(!(_expr))) { \ PVR_DPF((PVR_DBG_ERROR, ("In %s() "_msg), __func__, __VA_ARGS__)); \ goto _go; \ } MSC_SUPPRESS_4127\ - } while (0) + } while (false) #else /* defined(PVRSRV_NEED_PVR_DPF) */ @@ -450,27 +450,27 @@ PVRSRVDebugAssertFail(const IMG_CHAR *pszFile, #define PVR_LOG_IF_ERROR_VA(_lvl, _rc, _msg, ...) (void)(_rc) #define PVR_LOG_IF_FALSE_VA(_lvl, _expr, _msg, ...) (void)(_expr) - #define PVR_LOG_RETURN_IF_NOMEM(_expr, _call) do { if (unlikely(_expr == NULL)) { return PVRSRV_ERROR_OUT_OF_MEMORY; } MSC_SUPPRESS_4127 } while (0) - #define PVR_LOG_GOTO_IF_NOMEM(_expr, _err, _go) do { if (unlikely(_expr == NULL)) { _err = PVRSRV_ERROR_OUT_OF_MEMORY; goto _go; } MSC_SUPPRESS_4127 } while (0) + #define PVR_LOG_RETURN_IF_NOMEM(_expr, _call) do { if (unlikely(_expr == NULL)) { return PVRSRV_ERROR_OUT_OF_MEMORY; } MSC_SUPPRESS_4127 } while (false) + #define PVR_LOG_GOTO_IF_NOMEM(_expr, _err, _go) do { if (unlikely(_expr == NULL)) { _err = PVRSRV_ERROR_OUT_OF_MEMORY; goto _go; } MSC_SUPPRESS_4127 } while (false) - #define PVR_LOG_RETURN_IF_ERROR(_rc, _call) do { if (unlikely(_rc != PVRSRV_OK)) { return (_rc); } MSC_SUPPRESS_4127 } while (0) - #define PVR_LOG_RETURN_IF_ERROR_VA(_rc, _msg, ...) do { if (unlikely(_rc != PVRSRV_OK)) { return (_rc); } MSC_SUPPRESS_4127 } while (0) - #define PVR_LOG_RETURN_VOID_IF_ERROR(_rc, _call) do { if (unlikely(_rc != PVRSRV_OK)) { return; } MSC_SUPPRESS_4127 } while (0) + #define PVR_LOG_RETURN_IF_ERROR(_rc, _call) do { if (unlikely(_rc != PVRSRV_OK)) { return (_rc); } MSC_SUPPRESS_4127 } while (false) + #define PVR_LOG_RETURN_IF_ERROR_VA(_rc, _msg, ...) do { if (unlikely(_rc != PVRSRV_OK)) { return (_rc); } MSC_SUPPRESS_4127 } while (false) + #define PVR_LOG_RETURN_VOID_IF_ERROR(_rc, _call) do { if (unlikely(_rc != PVRSRV_OK)) { return; } MSC_SUPPRESS_4127 } while (false) - #define PVR_LOG_GOTO_IF_ERROR(_rc, _call, _go) do { if (unlikely(_rc != PVRSRV_OK)) { goto _go; } MSC_SUPPRESS_4127 } while (0) - #define PVR_LOG_GOTO_IF_ERROR_VA(_rc, _go, _msg, ...) do { if (unlikely(_rc != PVRSRV_OK)) { goto _go; } MSC_SUPPRESS_4127 } while (0) - #define PVR_LOG_GOTO_WITH_ERROR(_call, _err, _rc, _go) do { _err = _rc; goto _go; MSC_SUPPRESS_4127 } while (0) + #define PVR_LOG_GOTO_IF_ERROR(_rc, _call, _go) do { if (unlikely(_rc != PVRSRV_OK)) { goto _go; } MSC_SUPPRESS_4127 } while (false) + #define PVR_LOG_GOTO_IF_ERROR_VA(_rc, _go, _msg, ...) do { if (unlikely(_rc != PVRSRV_OK)) { goto _go; } MSC_SUPPRESS_4127 } while (false) + #define PVR_LOG_GOTO_WITH_ERROR(_call, _err, _rc, _go) do { _err = _rc; goto _go; MSC_SUPPRESS_4127 } while (false) #define PVR_LOG_IF_FALSE(_expr, _msg) (void)(_expr) - #define PVR_LOG_RETURN_IF_FALSE(_expr, _msg, _rc) do { if (unlikely(!(_expr))) { return (_rc); } MSC_SUPPRESS_4127 } while (0) - #define PVR_LOG_RETURN_IF_FALSE_VA(_expr, _rc, _msg, ...) do { if (unlikely(!(_expr))) { return (_rc); } MSC_SUPPRESS_4127 } while (0) + #define PVR_LOG_RETURN_IF_FALSE(_expr, _msg, _rc) do { if (unlikely(!(_expr))) { return (_rc); } MSC_SUPPRESS_4127 } while (false) + #define PVR_LOG_RETURN_IF_FALSE_VA(_expr, _rc, _msg, ...) do { if (unlikely(!(_expr))) { return (_rc); } MSC_SUPPRESS_4127 } while (false) - #define PVR_LOG_RETURN_VOID_IF_FALSE(_expr, _msg) do { if (unlikely(!(_expr))) { return; } MSC_SUPPRESS_4127 } while (0) - #define PVR_LOG_GOTO_IF_FALSE(_expr, _msg, _go) do { if (unlikely(!(_expr))) { goto _go; } MSC_SUPPRESS_4127 } while (0) - #define PVR_LOG_GOTO_IF_FALSE_VA(_expr, _go, _msg, ...) do { if (unlikely(!(_expr))) { goto _go; } MSC_SUPPRESS_4127 } while (0) + #define PVR_LOG_RETURN_VOID_IF_FALSE(_expr, _msg) do { if (unlikely(!(_expr))) { return; } MSC_SUPPRESS_4127 } while (false) + #define PVR_LOG_GOTO_IF_FALSE(_expr, _msg, _go) do { if (unlikely(!(_expr))) { goto _go; } MSC_SUPPRESS_4127 } while (false) + #define PVR_LOG_GOTO_IF_FALSE_VA(_expr, _go, _msg, ...) do { if (unlikely(!(_expr))) { goto _go; } MSC_SUPPRESS_4127 } while (false) - #define PVR_LOG_RETURN_IF_INVALID_PARAM(_expr, _param) do { if (unlikely(!(_expr))) { return PVRSRV_ERROR_INVALID_PARAMS; } MSC_SUPPRESS_4127 } while (0) - #define PVR_LOG_GOTO_IF_INVALID_PARAM(_expr, _err, _go) do { if (unlikely(!(_expr))) { _err = PVRSRV_ERROR_INVALID_PARAMS; goto _go; } MSC_SUPPRESS_4127 } while (0) + #define PVR_LOG_RETURN_IF_INVALID_PARAM(_expr, _param) do { if (unlikely(!(_expr))) { return PVRSRV_ERROR_INVALID_PARAMS; } MSC_SUPPRESS_4127 } while (false) + #define PVR_LOG_GOTO_IF_INVALID_PARAM(_expr, _err, _go) do { if (unlikely(!(_expr))) { _err = PVRSRV_ERROR_INVALID_PARAMS; goto _go; } MSC_SUPPRESS_4127 } while (false) #undef PVR_DPF_FUNCTION_TRACE_ON @@ -520,8 +520,10 @@ IMG_EXPORT void IMG_CALLCONV PVRSRVDebugPrintf(IMG_UINT32 ui32DebugLevel, */ /**************************************************************************/ IMG_EXPORT void IMG_CALLCONV PVRSRVDebugPrintfDumpCCB(void); +#if !defined(DOXYGEN) #define PVR_DPF_FUNC__(lvl, message, ...) PVR_DPF((lvl, "%s: " message, __func__, ##__VA_ARGS__)) #define PVR_DPF_FUNC(x) PVR_DPF_FUNC__ x +#endif /*!defined(DOXYGEN) */ /* Note: Use only when a log message due to the error absolutely should not * be printed. Otherwise use PVR_LOG_RETURN_IF_ERROR macro. @@ -530,7 +532,7 @@ IMG_EXPORT void IMG_CALLCONV PVRSRVDebugPrintfDumpCCB(void); { if (unlikely(_rc != PVRSRV_OK)) { \ return _rc; } \ MSC_SUPPRESS_4127 \ - } while (0) + } while (false) /* Note: Use only when a log message due to the error absolutely should not * be printed. Otherwise use PVR_LOG_RETURN_IF_FALSE macro. @@ -539,7 +541,7 @@ IMG_EXPORT void IMG_CALLCONV PVRSRVDebugPrintfDumpCCB(void); { if (unlikely(!(_expr))) { \ return _rc; } \ MSC_SUPPRESS_4127 \ - } while (0) + } while (false) /* Note: Use only when a log message due to the error absolutely should not * be printed. Otherwise use PVR_LOG_RETURN_IF_INVALID_PARAM macro. @@ -548,7 +550,7 @@ IMG_EXPORT void IMG_CALLCONV PVRSRVDebugPrintfDumpCCB(void); { if (unlikely(!(_expr))) { \ return PVRSRV_ERROR_INVALID_PARAMS; } \ MSC_SUPPRESS_4127 \ - } while (0) + } while (false) /* Note: Use only when a log message due to the error absolutely should not * be printed. Otherwise use PVR_LOG_RETURN_IF_NOMEM macro. @@ -557,7 +559,7 @@ IMG_EXPORT void IMG_CALLCONV PVRSRVDebugPrintfDumpCCB(void); { if (unlikely(!(_expr))) { \ return PVRSRV_ERROR_OUT_OF_MEMORY; } \ MSC_SUPPRESS_4127 \ - } while (0) + } while (false) /* Note: Use only when a log message due to the error absolutely should not * be printed. Otherwise use PVR_LOG_GOTO_IF_NOMEM macro. @@ -567,7 +569,7 @@ IMG_EXPORT void IMG_CALLCONV PVRSRVDebugPrintfDumpCCB(void); _err = PVRSRV_ERROR_OUT_OF_MEMORY; \ goto _go; } \ MSC_SUPPRESS_4127 \ - } while (0) + } while (false) /* Note: Use only when a log message due to the error absolutely should not * be printed. Otherwise use PVR_LOG_GOTO_IF_INVALID_PARAM macro. @@ -577,7 +579,7 @@ IMG_EXPORT void IMG_CALLCONV PVRSRVDebugPrintfDumpCCB(void); _err = PVRSRV_ERROR_INVALID_PARAMS; \ goto _go; } \ MSC_SUPPRESS_4127 \ - } while (0) + } while (false) /* Note: Use only when a log message due to the error absolutely should not * be printed. Otherwise use PVR_LOG_GOTO_IF_FALSE macro. @@ -586,7 +588,7 @@ IMG_EXPORT void IMG_CALLCONV PVRSRVDebugPrintfDumpCCB(void); { if (unlikely(!(_expr))) { \ goto _go; } \ MSC_SUPPRESS_4127 \ - } while (0) + } while (false) /* Note: Use only when a log message due to the error absolutely should not * be printed. Otherwise use PVR_LOG_GOTO_IF_ERROR macro. @@ -595,7 +597,7 @@ IMG_EXPORT void IMG_CALLCONV PVRSRVDebugPrintfDumpCCB(void); { if (unlikely(_rc != PVRSRV_OK)) { \ goto _go; } \ MSC_SUPPRESS_4127\ - } while (0) + } while (false) /* Note: Use only when a log message due to the error absolutely should not * be printed. Otherwise use PVR_LOG_GOTO_WITH_ERROR macro. @@ -603,7 +605,7 @@ IMG_EXPORT void IMG_CALLCONV PVRSRVDebugPrintfDumpCCB(void); #define PVR_GOTO_WITH_ERROR(_err, _rc, _go) do \ { _err = _rc; goto _go; \ MSC_SUPPRESS_4127 \ - } while (0) + } while (false) /*! @cond Doxygen_Suppress */ #if defined(PVR_DPF_FUNCTION_TRACE_ON) @@ -615,19 +617,19 @@ IMG_EXPORT void IMG_CALLCONV PVRSRVDebugPrintfDumpCCB(void); PVR_DPF((PVR_DBG_CALLTRACE, "|-> %s:%d entered (0x%lx)", __func__, __LINE__, ((unsigned long)p1))) #define PVR_DPF_RETURN_RC(a) \ - do { int _r = (a); PVR_DPF((PVR_DBG_CALLTRACE, "<-| %s:%d returned %d", __func__, __LINE__, (_r))); return (_r); MSC_SUPPRESS_4127 } while (0) + do { int _r = (a); PVR_DPF((PVR_DBG_CALLTRACE, "<-| %s:%d returned %d", __func__, __LINE__, (_r))); return (_r); MSC_SUPPRESS_4127 } while (false) #define PVR_DPF_RETURN_RC1(a,p1) \ - do { int _r = (a); PVR_DPF((PVR_DBG_CALLTRACE, "<-| %s:%d returned %d (0x%lx)", __func__, __LINE__, (_r), ((unsigned long)p1))); return (_r); MSC_SUPPRESS_4127 } while (0) + do { int _r = (a); PVR_DPF((PVR_DBG_CALLTRACE, "<-| %s:%d returned %d (0x%lx)", __func__, __LINE__, (_r), ((unsigned long)p1))); return (_r); MSC_SUPPRESS_4127 } while (false) #define PVR_DPF_RETURN_VAL(a) \ - do { PVR_DPF((PVR_DBG_CALLTRACE, "<-| %s:%d returned with value", __func__, __LINE__)); return (a); MSC_SUPPRESS_4127 } while (0) + do { PVR_DPF((PVR_DBG_CALLTRACE, "<-| %s:%d returned with value", __func__, __LINE__)); return (a); MSC_SUPPRESS_4127 } while (false) #define PVR_DPF_RETURN_OK \ - do { PVR_DPF((PVR_DBG_CALLTRACE, "<-| %s:%d returned ok", __func__, __LINE__)); return PVRSRV_OK; MSC_SUPPRESS_4127 } while (0) + do { PVR_DPF((PVR_DBG_CALLTRACE, "<-| %s:%d returned ok", __func__, __LINE__)); return PVRSRV_OK; MSC_SUPPRESS_4127 } while (false) #define PVR_DPF_RETURN \ - do { PVR_DPF((PVR_DBG_CALLTRACE, "<-| %s:%d returned", __func__, __LINE__)); return; MSC_SUPPRESS_4127 } while (0) + do { PVR_DPF((PVR_DBG_CALLTRACE, "<-| %s:%d returned", __func__, __LINE__)); return; MSC_SUPPRESS_4127 } while (false) #if !defined(DEBUG) #error PVR DPF Function trace enabled in release build, rectify @@ -742,7 +744,7 @@ IMG_EXPORT void IMG_CALLCONV PVRSRVTrace(const IMG_CHAR* pszFormat, ... ) #define PVR_DBG_FILELINE_ARG , pszaFile, ui32Line #define PVR_DBG_FILELINE_FMT " %s:%u" #define PVR_DBG_FILELINE_UNREF() do { PVR_UNREFERENCED_PARAMETER(pszaFile); \ - PVR_UNREFERENCED_PARAMETER(ui32Line); } while (0) + PVR_UNREFERENCED_PARAMETER(ui32Line); } while (false) #else #define PVR_DBG_FILELINE #define PVR_DBG_FILELINE_PARAM @@ -840,7 +842,7 @@ IMG_EXPORT void IMG_CALLCONV PVRSRVTrace(const IMG_CHAR* pszFormat, ... ) @brief Goes to a label if expression is false. @def PVR_GOTO_IF_FALSE - @def Goes to a label if expression is false. + @brief Goes to a label if expression is false. @def PVR_GOTO_IF_ERROR @brief Goes to a label if the error code is different than PVRSRV_OK; @@ -852,6 +854,29 @@ IMG_EXPORT void IMG_CALLCONV PVRSRVTrace(const IMG_CHAR* pszFormat, ... ) @brief Prints message to a log unconditionally. This macro will print messages only if PVRSRV_NEED_PVR_LOG macro is defined. + @def PVR_LOG_MSG + @brief Prints message to a log with the given log-level. + + @def PVR_LOG_VA + @brief Prints message with var-args to a log with the given log-level. + + @def PVR_LOG_IF_ERROR_VA + @brief Prints message with var-args to a log if the error code is different than PVRSRV_OK. + + @def PVR_LOG_IF_FALSE_VA + @brief Prints message with var-args if expression is false. + + @def PVR_LOG_RETURN_IF_ERROR_VA + @brief Prints message with var-args to a log and returns the error code. + + @def PVR_LOG_GOTO_IF_ERROR_VA + @brief Prints message with var-args to a log and goes to a label if the error code is different than PVRSRV_OK. + + @def PVR_LOG_RETURN_IF_FALSE_VA + @brief Logs the error message with var-args if the expression is false and returns the error code. + + @def PVR_LOG_GOTO_IF_FALSE_VA + @brief Logs the error message with var-args and goes to a label if the expression is false. @def PVR_TRACE_EMPTY_LINE @brief Prints empty line to a log (PVRSRV_NEED_PVR_LOG must be defined). diff --git a/drivers/gpu/drm/img-rogue/pvr_debugfs.c b/drivers/gpu/drm/img-rogue/pvr_debugfs.c index 3ba43c0ef..fa6a94c64 100644 --- a/drivers/gpu/drm/img-rogue/pvr_debugfs.c +++ b/drivers/gpu/drm/img-rogue/pvr_debugfs.c @@ -112,6 +112,12 @@ typedef struct DFS_FILE /* ----- native callbacks interface ----------------------------------------- */ +static void _WriteData(void *pvNativeHandle, const void *pvData, + IMG_UINT32 uiSize) +{ + seq_write(pvNativeHandle, pvData, uiSize); +} + static void _VPrintf(void *pvNativeHandle, const IMG_CHAR *pszFmt, va_list pArgs) { @@ -141,6 +147,7 @@ static IMG_BOOL _HasOverflowed(void *pvNativeHandle) } static OSDI_IMPL_ENTRY_CB _g_sEntryCallbacks = { + .pfnWrite = _WriteData, .pfnVPrintf = _VPrintf, .pfnPuts = _Puts, .pfnHasOverflowed = _HasOverflowed, @@ -403,22 +410,29 @@ static ssize_t _Write(struct file *psFile, const char __user *pszBuffer, DFS_FILE *psDFSFile = psINode->i_private; DI_ITERATOR_CB *psIter = &psDFSFile->sEntry.sIterCb; IMG_CHAR *pcLocalBuffer; - IMG_UINT64 ui64Count = uiCount + 1, ui64Pos = *puiPos; + IMG_UINT64 ui64Count; IMG_INT64 i64Res = -EIO; + IMG_UINT64 ui64Pos = *puiPos; PVR_LOG_RETURN_IF_FALSE(psDFSFile != NULL, "psDFSFile is NULL", -EIO); PVR_LOG_RETURN_IF_FALSE(psIter->pfnWrite != NULL, "pfnWrite is NULL", -EIO); + + /* Make sure we allocate the smallest amount of needed memory*/ + ui64Count = psIter->ui32WriteLenMax; + PVR_LOG_GOTO_IF_FALSE(uiCount <= ui64Count, "uiCount too long", return_); + ui64Count = MIN(uiCount + 1, ui64Count); + _DRIVER_THREAD_ENTER(); - /* allocate buffer with one additional byte fore NUL character */ + /* allocate buffer with one additional byte for NUL character */ pcLocalBuffer = OSAllocMem(ui64Count); PVR_LOG_GOTO_IF_FALSE(pcLocalBuffer != NULL, "OSAllocMem() failed", return_); - i64Res = pvr_copy_from_user(pcLocalBuffer, pszBuffer, uiCount); + i64Res = pvr_copy_from_user(pcLocalBuffer, pszBuffer, ui64Count); PVR_LOG_GOTO_IF_FALSE(i64Res == 0, "pvr_copy_from_user() failed", free_local_buffer_); diff --git a/drivers/gpu/drm/img-rogue/pvr_dma_resv.h b/drivers/gpu/drm/img-rogue/pvr_dma_resv.h index 26f54c5bd..a51c9de84 100644 --- a/drivers/gpu/drm/img-rogue/pvr_dma_resv.h +++ b/drivers/gpu/drm/img-rogue/pvr_dma_resv.h @@ -67,4 +67,14 @@ CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. #define dma_resv_wait_timeout_rcu reservation_object_wait_timeout_rcu #endif +#if (LINUX_VERSION_CODE < KERNEL_VERSION(5, 14, 0)) + +#define dma_resv_shared_list dma_resv_get_list +#define dma_resv_excl_fence dma_resv_get_excl +#define dma_resv_wait_timeout dma_resv_wait_timeout_rcu +#define dma_resv_test_signaled dma_resv_test_signaled_rcu +#define dma_resv_get_fences dma_resv_get_fences_rcu + +#endif /* (LINUX_VERSION_CODE < KERNEL_VERSION(5, 14, 0)) */ + #endif /* __PVR_DMA_RESV_H__ */ diff --git a/drivers/gpu/drm/img-rogue/pvr_drm.c b/drivers/gpu/drm/img-rogue/pvr_drm.c index d8c9c52e6..65a8e511e 100644 --- a/drivers/gpu/drm/img-rogue/pvr_drm.c +++ b/drivers/gpu/drm/img-rogue/pvr_drm.c @@ -167,7 +167,7 @@ int pvr_drm_load(struct drm_device *ddev, unsigned long flags) drm_mode_config_init(ddev); -#if defined(SUPPORT_FWLOAD_ON_PROBE) +#if (PVRSRV_DEVICE_INIT_MODE == PVRSRV_LINUX_DEV_INIT_ON_PROBE) srv_err = PVRSRVCommonDeviceInitialise(priv->dev_node); if (srv_err != PVRSRV_OK) { err = -ENODEV; @@ -181,7 +181,7 @@ int pvr_drm_load(struct drm_device *ddev, unsigned long flags) return 0; -#if defined(SUPPORT_FWLOAD_ON_PROBE) +#if (PVRSRV_DEVICE_INIT_MODE == PVRSRV_LINUX_DEV_INIT_ON_PROBE) err_device_deinit: drm_mode_config_cleanup(ddev); PVRSRVDeviceDeinit(priv->dev_node); @@ -231,19 +231,25 @@ void pvr_drm_unload(struct drm_device *ddev) static int pvr_drm_open(struct drm_device *ddev, struct drm_file *dfile) { +#if (PVRSRV_DEVICE_INIT_MODE != PVRSRV_LINUX_DEV_INIT_ON_CONNECT) struct pvr_drm_private *priv = ddev->dev_private; int err; +#endif if (!try_module_get(THIS_MODULE)) { DRM_ERROR("failed to get module reference\n"); return -ENOENT; } - err = PVRSRVDeviceOpen(priv->dev_node, dfile); +#if (PVRSRV_DEVICE_INIT_MODE != PVRSRV_LINUX_DEV_INIT_ON_CONNECT) + err = PVRSRVDeviceServicesOpen(priv->dev_node, dfile); if (err) module_put(THIS_MODULE); return err; +#else + return 0; +#endif } static void pvr_drm_release(struct drm_device *ddev, struct drm_file *dfile) @@ -261,6 +267,8 @@ static void pvr_drm_release(struct drm_device *ddev, struct drm_file *dfile) static struct drm_ioctl_desc pvr_drm_ioctls[] = { DRM_IOCTL_DEF_DRV(PVR_SRVKM_CMD, PVRSRV_BridgeDispatchKM, DRM_RENDER_ALLOW | DRM_UNLOCKED), + DRM_IOCTL_DEF_DRV(PVR_SRVKM_INIT, drm_pvr_srvkm_init, + DRM_RENDER_ALLOW | DRM_UNLOCKED), #if defined(SUPPORT_NATIVE_FENCE_SYNC) && !defined(USE_PVRSYNC_DEVNODE) DRM_IOCTL_DEF_DRV(PVR_SYNC_RENAME_CMD, pvr_sync_rename_ioctl, DRM_RENDER_ALLOW | DRM_UNLOCKED), diff --git a/drivers/gpu/drm/img-rogue/pvr_drm.h b/drivers/gpu/drm/img-rogue/pvr_drm.h index 65c293be6..c0d00c98d 100644 --- a/drivers/gpu/drm/img-rogue/pvr_drm.h +++ b/drivers/gpu/drm/img-rogue/pvr_drm.h @@ -89,6 +89,17 @@ struct pvr_sw_timeline_advance_data { __u64 sync_pt_idx; }; +#define PVR_SRVKM_SERVICES_INIT 1 +#define PVR_SRVKM_SYNC_INIT 2 +struct drm_pvr_srvkm_init_data { + __u32 init_module; +}; + +/* Values used to configure the PVRSRV_DEVICE_INIT_MODE tunable (Linux-only) */ +#define PVRSRV_LINUX_DEV_INIT_ON_PROBE 1 +#define PVRSRV_LINUX_DEV_INIT_ON_OPEN 2 +#define PVRSRV_LINUX_DEV_INIT_ON_CONNECT 3 + /* * DRM command numbers, relative to DRM_COMMAND_BASE. * These defines must be prefixed with "DRM_". @@ -105,6 +116,9 @@ struct pvr_sw_timeline_advance_data { #define DRM_PVR_SW_SYNC_CREATE_FENCE_CMD 3 #define DRM_PVR_SW_SYNC_INC_CMD 4 +/* PVR Services Render Device Init command */ +#define DRM_PVR_SRVKM_INIT 5 + /* These defines must be prefixed with "DRM_IOCTL_". */ #define DRM_IOCTL_PVR_SRVKM_CMD \ DRM_IOWR(DRM_COMMAND_BASE + DRM_PVR_SRVKM_CMD, \ @@ -125,4 +139,8 @@ struct pvr_sw_timeline_advance_data { DRM_IOR(DRM_COMMAND_BASE + DRM_PVR_SW_SYNC_INC_CMD, \ struct pvr_sw_timeline_advance_data) +#define DRM_IOCTL_PVR_SRVKM_INIT \ + DRM_IOW(DRM_COMMAND_BASE + DRM_PVR_SRVKM_INIT, \ + struct drm_pvr_srvkm_init_data) + #endif /* defined(__PVR_DRM_H__) */ diff --git a/drivers/gpu/drm/img-rogue/pvr_fence.c b/drivers/gpu/drm/img-rogue/pvr_fence.c index 7e929f46c..e94522a64 100644 --- a/drivers/gpu/drm/img-rogue/pvr_fence.c +++ b/drivers/gpu/drm/img-rogue/pvr_fence.c @@ -660,7 +660,7 @@ const struct dma_fence_ops pvr_fence_ops = { */ struct pvr_fence * pvr_fence_create(struct pvr_fence_context *fctx, - struct _SYNC_CHECKPOINT_CONTEXT *sync_checkpoint_ctx, + struct SYNC_CHECKPOINT_CONTEXT_TAG *sync_checkpoint_ctx, int timeline_fd, const char *name) { struct pvr_fence *pvr_fence; @@ -872,7 +872,7 @@ pvr_fence_foreign_signal_sync(struct dma_fence *fence, struct dma_fence_cb *cb) struct pvr_fence * pvr_fence_create_from_fence(struct pvr_fence_context *fctx, - struct _SYNC_CHECKPOINT_CONTEXT *sync_checkpoint_ctx, + struct SYNC_CHECKPOINT_CONTEXT_TAG *sync_checkpoint_ctx, struct dma_fence *fence, PVRSRV_FENCE fence_fd, const char *name) @@ -1050,9 +1050,9 @@ pvr_fence_sw_error(struct pvr_fence *pvr_fence) int pvr_fence_get_checkpoints(struct pvr_fence **pvr_fences, u32 nr_fences, - struct _SYNC_CHECKPOINT **fence_checkpoints) + struct SYNC_CHECKPOINT_TAG **fence_checkpoints) { - struct _SYNC_CHECKPOINT **next_fence_checkpoint = fence_checkpoints; + struct SYNC_CHECKPOINT_TAG **next_fence_checkpoint = fence_checkpoints; struct pvr_fence **next_pvr_fence = pvr_fences; int fence_checkpoint_idx; @@ -1072,7 +1072,7 @@ pvr_fence_get_checkpoints(struct pvr_fence **pvr_fences, u32 nr_fences, return 0; } -struct _SYNC_CHECKPOINT * +struct SYNC_CHECKPOINT_TAG * pvr_fence_get_checkpoint(struct pvr_fence *update_fence) { return update_fence->sync_checkpoint; @@ -1111,7 +1111,7 @@ u32 pvr_fence_dump_info_on_stalled_ufos(struct pvr_fence_context *fctx, DUMPDEBUG_PRINTF_FUNC *pfnDummy = NULL; for (ufo_num = 0; ufo_num < nr_ufos; ufo_num++) { - struct _SYNC_CHECKPOINT *checkpoint = + struct SYNC_CHECKPOINT_TAG *checkpoint = pvr_fence->sync_checkpoint; const u32 fence_ufo_addr = SyncCheckpointGetFirmwareAddr(checkpoint); diff --git a/drivers/gpu/drm/img-rogue/pvr_fence.h b/drivers/gpu/drm/img-rogue/pvr_fence.h index e6ac419a7..21870ba91 100644 --- a/drivers/gpu/drm/img-rogue/pvr_fence.h +++ b/drivers/gpu/drm/img-rogue/pvr_fence.h @@ -57,8 +57,8 @@ static inline void pvr_fence_cleanup(void) #include #include -struct _SYNC_CHECKPOINT_CONTEXT; -struct _SYNC_CHECKPOINT; +struct SYNC_CHECKPOINT_CONTEXT_TAG; +struct SYNC_CHECKPOINT_TAG; /** * pvr_fence_context - PVR fence context used to create and manage PVR fences @@ -117,7 +117,7 @@ struct pvr_fence { char name[32]; struct dma_fence *fence; - struct _SYNC_CHECKPOINT *sync_checkpoint; + struct SYNC_CHECKPOINT_TAG *sync_checkpoint; struct list_head fence_head; struct list_head signal_head; @@ -163,11 +163,11 @@ void pvr_context_value_str(struct pvr_fence_context *fctx, char *str, int size); struct pvr_fence * pvr_fence_create(struct pvr_fence_context *fctx, - struct _SYNC_CHECKPOINT_CONTEXT *sync_checkpoint_ctx, + struct SYNC_CHECKPOINT_CONTEXT_TAG *sync_checkpoint_ctx, int timeline_fd, const char *name); struct pvr_fence * pvr_fence_create_from_fence(struct pvr_fence_context *fctx, - struct _SYNC_CHECKPOINT_CONTEXT *sync_checkpoint_ctx, + struct SYNC_CHECKPOINT_CONTEXT_TAG *sync_checkpoint_ctx, struct dma_fence *fence, PVRSRV_FENCE fence_fd, const char *name); @@ -176,8 +176,8 @@ int pvr_fence_sw_signal(struct pvr_fence *pvr_fence); int pvr_fence_sw_error(struct pvr_fence *pvr_fence); int pvr_fence_get_checkpoints(struct pvr_fence **pvr_fences, u32 nr_fences, - struct _SYNC_CHECKPOINT **fence_checkpoints); -struct _SYNC_CHECKPOINT * + struct SYNC_CHECKPOINT_TAG **fence_checkpoints); +struct SYNC_CHECKPOINT_TAG * pvr_fence_get_checkpoint(struct pvr_fence *update_fence); void pvr_fence_context_signal_fences_nohw(void *data); diff --git a/drivers/gpu/drm/img-rogue/pvr_gputrace.c b/drivers/gpu/drm/img-rogue/pvr_gputrace.c index 15454d5b5..3e65aa3de 100644 --- a/drivers/gpu/drm/img-rogue/pvr_gputrace.c +++ b/drivers/gpu/drm/img-rogue/pvr_gputrace.c @@ -280,10 +280,18 @@ static PVRSRV_ERROR _GpuTraceEnable(PVRSRV_RGXDEV_INFO *psRgxDevInfo) IMG_UINT64 ui64UFOFilter = psRgxDevInfo->ui64HWPerfFilter & (RGX_HWPERF_EVENT_MASK_FW_SED | RGX_HWPERF_EVENT_MASK_FW_UFO); - eError = PVRSRVRGXCtrlHWPerfKM(NULL, psRgxDevNode, - RGX_HWPERF_STREAM_ID0_FW, IMG_FALSE, - RGX_HWPERF_EVENT_MASK_HW_KICKFINISH | - ui64UFOFilter); + /* Do not call into PVRSRVRGXCtrlHWPerfKM if we're in GUEST mode. */ + if (PVRSRV_VZ_MODE_IS(GUEST)) + { + eError = PVRSRV_OK; + } + else + { + eError = PVRSRVRGXCtrlHWPerfKM(NULL, psRgxDevNode, + RGX_HWPERF_STREAM_ID0_FW, IMG_FALSE, + RGX_HWPERF_EVENT_MASK_HW_KICKFINISH | + ui64UFOFilter); + } PVR_LOG_GOTO_IF_ERROR(eError, "PVRSRVRGXCtrlHWPerfKM", err_out); } else @@ -374,10 +382,11 @@ static PVRSRV_ERROR _GpuTraceDisable(PVRSRV_RGXDEV_INFO *psRgxDevInfo, IMG_BOOL if (!psRgxDevInfo->bFirmwareInitialised) { psRgxDevInfo->ui64HWPerfFilter = RGX_HWPERF_EVENT_MASK_NONE; +#if !defined(NO_HARDWARE) PVR_DPF((PVR_DBG_WARNING, - "HWPerfFW mask has been SET to (%" IMG_UINT64_FMTSPECx ")", - psRgxDevInfo->ui64HWPerfFilter)); - + "HWPerfFW mask has been SET to (%" IMG_UINT64_FMTSPECx ")", + psRgxDevInfo->ui64HWPerfFilter)); +#endif return PVRSRV_OK; } @@ -390,9 +399,17 @@ static PVRSRV_ERROR _GpuTraceDisable(PVRSRV_RGXDEV_INFO *psRgxDevInfo, IMG_BOOL #if defined(SUPPORT_RGX) if (!bDeInit) { - eError = PVRSRVRGXCtrlHWPerfKM(NULL, psRgxDevNode, - RGX_HWPERF_STREAM_ID0_FW, IMG_FALSE, - (RGX_HWPERF_EVENT_MASK_NONE)); + /* Do not call into PVRSRVRGXCtrlHWPerfKM if we are in GUEST mode. */ + if (PVRSRV_VZ_MODE_IS(GUEST)) + { + eError = PVRSRV_OK; + } + else + { + eError = PVRSRVRGXCtrlHWPerfKM(NULL, psRgxDevNode, + RGX_HWPERF_STREAM_ID0_FW, IMG_FALSE, + (RGX_HWPERF_EVENT_MASK_NONE)); + } PVR_LOG_IF_ERROR(eError, "PVRSRVRGXCtrlHWPerfKM"); } #endif @@ -475,7 +492,9 @@ static PVRSRV_ERROR _GpuTraceSetEnabledForAllDevices(IMG_BOOL bNewValue) PVRSRV_DATA *psPVRSRVData = PVRSRVGetPVRSRVData(); PVRSRV_DEVICE_NODE *psDeviceNode; + OSWRLockAcquireRead(psPVRSRVData->hDeviceNodeListLock); psDeviceNode = psPVRSRVData->psDeviceNodeList; + /* enable/disable GPU trace on all devices */ while (psDeviceNode) { @@ -487,6 +506,8 @@ static PVRSRV_ERROR _GpuTraceSetEnabledForAllDevices(IMG_BOOL bNewValue) psDeviceNode = psDeviceNode->psNext; } + OSWRLockReleaseRead(psPVRSRVData->hDeviceNodeListLock); + PVR_DPF_RETURN_RC(eError); } @@ -501,10 +522,10 @@ PVRSRV_ERROR PVRGpuTraceSetEnabled(PVRSRV_DEVICE_NODE *psDeviceNode, static const IMG_CHAR *_HWPerfKickTypeToStr(RGX_HWPERF_KICK_TYPE eKickType) { static const IMG_CHAR *aszKickType[RGX_HWPERF_KICK_TYPE_LAST+1] = { -#if defined(HWPERF_PACKET_V2C_SIG) - "TA3D", "CDM", "RS", "SHG", "TQTDM", "SYNC", "LAST" +#if defined(RGX_FEATURE_HWPERF_VOLCANIC) + "TA3D", "CDM", "RS", "SHG", "TQTDM", "SYNC", "TA", "3D", "LAST" #else - "TA3D", "TQ2D", "TQ3D", "CDM", "RS", "VRDM", "TQTDM", "SYNC", "LAST" + "TA3D", "TQ2D", "TQ3D", "CDM", "RS", "VRDM", "TQTDM", "SYNC", "TA", "3D", "LAST" #endif }; @@ -1053,7 +1074,8 @@ void PVRGpuTraceInitAppHintCallbacks(const PVRSRV_DEVICE_NODE *psDeviceNode) void PVRGpuTraceEnableUfoCallback(void) { - PVRSRV_DEVICE_NODE *psDeviceNode = PVRSRVGetPVRSRVData()->psDeviceNodeList; + PVRSRV_DATA *psPVRSRVData = PVRSRVGetPVRSRVData(); + PVRSRV_DEVICE_NODE *psDeviceNode; #if defined(SUPPORT_RGX) PVRSRV_RGXDEV_INFO *psRgxDevInfo; PVRSRV_ERROR eError; @@ -1063,6 +1085,9 @@ void PVRGpuTraceEnableUfoCallback(void) OSLockAcquire(ghLockFTraceEventLock); if (guiUfoEventRef++ == 0) { + OSWRLockAcquireRead(psPVRSRVData->hDeviceNodeListLock); + psDeviceNode = psPVRSRVData->psDeviceNodeList; + /* make sure UFO events are enabled on all rogue devices */ while (psDeviceNode) { @@ -1090,6 +1115,8 @@ void PVRGpuTraceEnableUfoCallback(void) #endif psDeviceNode = psDeviceNode->psNext; } + + OSWRLockReleaseRead(psPVRSRVData->hDeviceNodeListLock); } OSLockRelease(ghLockFTraceEventLock); } @@ -1099,6 +1126,7 @@ void PVRGpuTraceDisableUfoCallback(void) #if defined(SUPPORT_RGX) PVRSRV_ERROR eError; #endif + PVRSRV_DATA *psPVRSRVData = PVRSRVGetPVRSRVData(); PVRSRV_DEVICE_NODE *psDeviceNode; /* We have to check if lock is valid because on driver unload @@ -1110,7 +1138,8 @@ void PVRGpuTraceDisableUfoCallback(void) if (ghLockFTraceEventLock == NULL) return; - psDeviceNode = PVRSRVGetPVRSRVData()->psDeviceNodeList; + OSWRLockAcquireRead(psPVRSRVData->hDeviceNodeListLock); + psDeviceNode = psPVRSRVData->psDeviceNodeList; /* Lock down events state, for consistent value of guiUfoEventRef */ OSLockAcquire(ghLockFTraceEventLock); @@ -1142,15 +1171,19 @@ void PVRGpuTraceDisableUfoCallback(void) psDeviceNode->sDevId.i32OsDeviceID)); } #endif + psDeviceNode = psDeviceNode->psNext; } } OSLockRelease(ghLockFTraceEventLock); + + OSWRLockReleaseRead(psPVRSRVData->hDeviceNodeListLock); } void PVRGpuTraceEnableFirmwareActivityCallback(void) { - PVRSRV_DEVICE_NODE *psDeviceNode = PVRSRVGetPVRSRVData()->psDeviceNodeList; + PVRSRV_DATA *psPVRSRVData = PVRSRVGetPVRSRVData(); + PVRSRV_DEVICE_NODE *psDeviceNode; #if defined(SUPPORT_RGX) PVRSRV_RGXDEV_INFO *psRgxDevInfo; uint64_t ui64Filter, ui64FWEventsFilter = 0; @@ -1162,6 +1195,10 @@ void PVRGpuTraceEnableFirmwareActivityCallback(void) ui64FWEventsFilter |= RGX_HWPERF_EVENT_MASK_VALUE(i); } #endif + + OSWRLockAcquireRead(psPVRSRVData->hDeviceNodeListLock); + psDeviceNode = psPVRSRVData->psDeviceNodeList; + OSLockAcquire(ghLockFTraceEventLock); /* Enable all FW events on all the devices */ while (psDeviceNode) @@ -1173,7 +1210,7 @@ void PVRGpuTraceEnableFirmwareActivityCallback(void) eError = PVRSRVRGXCtrlHWPerfKM(NULL, psDeviceNode, RGX_HWPERF_STREAM_ID0_FW, IMG_FALSE, ui64Filter); - if (eError != PVRSRV_OK) + if ((eError != PVRSRV_OK) && !PVRSRV_VZ_MODE_IS(GUEST)) { PVR_DPF((PVR_DBG_ERROR, "Could not enable HWPerf event for firmware" " task timings (%s).", PVRSRVGetErrorString(eError))); @@ -1182,10 +1219,13 @@ void PVRGpuTraceEnableFirmwareActivityCallback(void) psDeviceNode = psDeviceNode->psNext; } OSLockRelease(ghLockFTraceEventLock); + + OSWRLockReleaseRead(psPVRSRVData->hDeviceNodeListLock); } void PVRGpuTraceDisableFirmwareActivityCallback(void) { + PVRSRV_DATA *psPVRSRVData = PVRSRVGetPVRSRVData(); PVRSRV_DEVICE_NODE *psDeviceNode; #if defined(SUPPORT_RGX) IMG_UINT64 ui64FWEventsFilter = ~0; @@ -1201,7 +1241,8 @@ void PVRGpuTraceDisableFirmwareActivityCallback(void) if (ghLockFTraceEventLock == NULL) return; - psDeviceNode = PVRSRVGetPVRSRVData()->psDeviceNodeList; + OSWRLockAcquireRead(psPVRSRVData->hDeviceNodeListLock); + psDeviceNode = psPVRSRVData->psDeviceNodeList; #if defined(SUPPORT_RGX) for (i = RGX_HWPERF_FW_EVENT_RANGE_FIRST_TYPE; @@ -1220,8 +1261,9 @@ void PVRGpuTraceDisableFirmwareActivityCallback(void) PVRSRV_RGXDEV_INFO *psRgxDevInfo = psDeviceNode->pvDevice; IMG_UINT64 ui64Filter = psRgxDevInfo->ui64HWPerfFilter & ui64FWEventsFilter; - if (PVRSRVRGXCtrlHWPerfKM(NULL, psDeviceNode, RGX_HWPERF_STREAM_ID0_FW, - IMG_FALSE, ui64Filter) != PVRSRV_OK) + if ((PVRSRVRGXCtrlHWPerfKM(NULL, psDeviceNode, RGX_HWPERF_STREAM_ID0_FW, + IMG_FALSE, ui64Filter) != PVRSRV_OK) && + !PVRSRV_VZ_MODE_IS(GUEST)) { PVR_DPF((PVR_DBG_ERROR, "Could not disable HWPerf event for firmware task timings.")); } @@ -1230,6 +1272,8 @@ void PVRGpuTraceDisableFirmwareActivityCallback(void) } OSLockRelease(ghLockFTraceEventLock); + + OSWRLockReleaseRead(psPVRSRVData->hDeviceNodeListLock); } /****************************************************************************** diff --git a/drivers/gpu/drm/img-rogue/pvr_notifier.c b/drivers/gpu/drm/img-rogue/pvr_notifier.c index 625f370c7..583d4c517 100644 --- a/drivers/gpu/drm/img-rogue/pvr_notifier.c +++ b/drivers/gpu/drm/img-rogue/pvr_notifier.c @@ -535,7 +535,12 @@ PVRSRVDebugRequest(PVRSRV_DEVICE_NODE *psDevNode, PVR_DUMPDEBUG_LOG("------------[ PVR DBG: START (%s) ]------------", szVerbosityLevel); - OSDumpVersionInfo(pfnDumpDebugPrintf, pvDumpDebugFile); +#if defined(RGX_IRQ_HYPERV_HANDLER) + if (!PVRSRV_VZ_MODE_IS(GUEST)) +#endif + { + OSDumpVersionInfo(pfnDumpDebugPrintf, pvDumpDebugFile); + } PVR_DUMPDEBUG_LOG("DDK info: %s (%s) %s", PVRVERSION_STRING, PVR_BUILD_TYPE, PVR_BUILD_DIR); diff --git a/drivers/gpu/drm/img-rogue/pvr_sync_file.c b/drivers/gpu/drm/img-rogue/pvr_sync_file.c index 24e2af3df..e3656108e 100644 --- a/drivers/gpu/drm/img-rogue/pvr_sync_file.c +++ b/drivers/gpu/drm/img-rogue/pvr_sync_file.c @@ -263,6 +263,7 @@ pvr_sync_finalise_fence(PVRSRV_FENCE fence_fd, void *finalise_data) * in that fence. The OS native sync code needs to implement a function * meeting this specification. * + * Input: device Device node to use in creating a hw_fence_ctx * Input: fence_name A string to annotate the fence with (for * debug). * Input: timeline The timeline on which the new fence is to be @@ -274,7 +275,9 @@ pvr_sync_finalise_fence(PVRSRV_FENCE fence_fd, void *finalise_data) * Output: new_checkpoint_handle The PSYNC_CHECKPOINT used by the new fence. */ static enum PVRSRV_ERROR_TAG -pvr_sync_create_fence(const char *fence_name, +pvr_sync_create_fence( + struct _PVRSRV_DEVICE_NODE_ *device, + const char *fence_name, PVRSRV_TIMELINE new_fence_timeline, PSYNC_CHECKPOINT_CONTEXT psSyncCheckpointContext, PVRSRV_FENCE *new_fence, u64 *fence_uid, @@ -327,7 +330,7 @@ pvr_sync_create_fence(const char *fence_name, /* First time we use this timeline, so create a context. */ timeline->hw_fence_context = pvr_fence_context_create( - SyncCheckpointGetAssociatedDevice(psSyncCheckpointContext), + device, NativeSyncGetFenceStatusWq(), timeline->name); if (!timeline->hw_fence_context) { @@ -588,12 +591,12 @@ pvr_sync_dump_info_on_stalled_ufos(u32 nr_ufos, u32 *vaddrs) #if defined(PDUMP) static enum PVRSRV_ERROR_TAG pvr_sync_fence_get_checkpoints(PVRSRV_FENCE fence_to_pdump, u32 *nr_checkpoints, - struct _SYNC_CHECKPOINT ***checkpoint_handles) + struct SYNC_CHECKPOINT_TAG ***checkpoint_handles) { struct dma_fence **fences = NULL; struct dma_fence *fence; struct pvr_fence *pvr_fence; - struct _SYNC_CHECKPOINT **checkpoints = NULL; + struct SYNC_CHECKPOINT_TAG **checkpoints = NULL; unsigned int i, num_fences, num_used_fences = 0; enum PVRSRV_ERROR_TAG err; diff --git a/drivers/gpu/drm/img-rogue/pvr_sync_ioctl_drm.c b/drivers/gpu/drm/img-rogue/pvr_sync_ioctl_drm.c index bf782a1c5..423c8d3a7 100644 --- a/drivers/gpu/drm/img-rogue/pvr_sync_ioctl_drm.c +++ b/drivers/gpu/drm/img-rogue/pvr_sync_ioctl_drm.c @@ -84,7 +84,7 @@ pvr_sync_connection_private_data(void *connection_data) struct pvr_sync_file_data * pvr_sync_get_private_data(struct file *file) { - CONNECTION_DATA *connection_data = LinuxConnectionFromFile(file); + CONNECTION_DATA *connection_data = LinuxSyncConnectionFromFile(file); return pvr_sync_connection_private_data(connection_data); } @@ -120,9 +120,13 @@ int pvr_sync_open(void *connection_data, struct drm_file *file) return pvr_sync_open_common(connection_data, file); } -int pvr_sync_close(void *connection_data) +void pvr_sync_close(void *connection_data) { - return pvr_sync_close_common(connection_data); + int iErr = pvr_sync_close_common(connection_data); + + if (iErr < 0) + pr_err("%s: ERROR (%d) returned by pvr_sync_close_common()\n", + __func__, iErr); } diff --git a/drivers/gpu/drm/img-rogue/pvr_sync_ioctl_drm.h b/drivers/gpu/drm/img-rogue/pvr_sync_ioctl_drm.h index 98a536972..756ce4bf7 100644 --- a/drivers/gpu/drm/img-rogue/pvr_sync_ioctl_drm.h +++ b/drivers/gpu/drm/img-rogue/pvr_sync_ioctl_drm.h @@ -48,7 +48,7 @@ struct drm_device; struct drm_file; int pvr_sync_open(void *connection_data, struct drm_file *file); -int pvr_sync_close(void *connection_data); +void pvr_sync_close(void *connection_data); int pvr_sync_rename_ioctl(struct drm_device *dev, void *arg, struct drm_file *file); diff --git a/drivers/gpu/drm/img-rogue/pvrsrv.c b/drivers/gpu/drm/img-rogue/pvrsrv.c index 47edf06f5..5de014095 100644 --- a/drivers/gpu/drm/img-rogue/pvrsrv.c +++ b/drivers/gpu/drm/img-rogue/pvrsrv.c @@ -162,27 +162,11 @@ CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. /*! When unloading try a few times to free everything remaining on the list */ #define CLEANUP_THREAD_UNLOAD_RETRY 4 -#define PVRSRV_PROC_HANDLE_BASE_INIT 10 - #define PVRSRV_TL_CTLR_STREAM_SIZE 4096 static PVRSRV_DATA *gpsPVRSRVData; static IMG_UINT32 g_ui32InitFlags; -#if defined(PDUMP) -static IMG_UINT32 gPDumpDevice = PVRSRV_MAX_DEVICES; - -#if defined(__linux__) -#include - -module_param(gPDumpDevice, uint, 0644); -MODULE_PARM_DESC(gPDumpDevice, "This is the internalID of the GPU device for " - "which PDump capture will be acquired - no capture of other " - "GPU devices will occur. If not specified, the first device " - "(internalID=0) will be chosen."); -#endif /* defined(__linux__) */ -#endif /* defined(PDUMP) */ - /* mark which parts of Services were initialised */ #define INIT_DATA_ENABLE_PDUMPINIT 0x1U @@ -394,6 +378,7 @@ static void CleanupThread(void *pvData) /* Store the process id (pid) of the clean-up thread */ psPVRSRVData->cleanupThreadPid = OSGetCurrentProcessID(); + psPVRSRVData->cleanupThreadTid = OSGetCurrentThreadID(); OSAtomicWrite(&psPVRSRVData->i32NumCleanupItemsQueued, 0); OSAtomicWrite(&psPVRSRVData->i32NumCleanupItemsNotCompleted, 0); @@ -471,6 +456,16 @@ static void CleanupThread(void *pvData) PVR_DPF((CLEANUP_DPFL, "CleanupThread: thread ending... ")); } +IMG_PID PVRSRVCleanupThreadGetPid(void) +{ + return gpsPVRSRVData->cleanupThreadPid; +} + +uintptr_t PVRSRVCleanupThreadGetTid(void) +{ + return gpsPVRSRVData->cleanupThreadTid; +} + static void DevicesWatchdogThread_ForEachVaCb(PVRSRV_DEVICE_NODE *psDeviceNode, va_list va) { @@ -865,8 +860,14 @@ static void DevicesWatchdogThread(void *pvData) bTimeOut = IMG_TRUE; } + OSWRLockAcquireRead(psPVRSRVData->hDeviceNodeListLock); + List_PVRSRV_DEVICE_NODE_ForEach_va(psPVRSRVData->psDeviceNodeList, + DevicesWatchdogThread_ForEachVaCb, + &ePreviousHealthStatus, + bTimeOut); bPwrIsOn = List_PVRSRV_DEVICE_NODE_IMG_BOOL_Any(psPVRSRVData->psDeviceNodeList, PVRSRVIsDevicePowered); + OSWRLockReleaseRead(psPVRSRVData->hDeviceNodeListLock); if (bPwrIsOn || psPVRSRVData->ui32DevicesWatchdogPwrTrans) { @@ -892,11 +893,6 @@ static void DevicesWatchdogThread(void *pvData) } } - List_PVRSRV_DEVICE_NODE_ForEach_va(psPVRSRVData->psDeviceNodeList, - DevicesWatchdogThread_ForEachVaCb, - &ePreviousHealthStatus, - bTimeOut); - #endif /* defined(PVRSRV_SERVER_THREADS_INDEFINITE_SLEEP) */ } @@ -1061,6 +1057,9 @@ PVRSRVCommonDriverInit(void) /* Now it is set up, point gpsPVRSRVData to the actual data */ gpsPVRSRVData = psPVRSRVData; + eError = OSWRLockCreate(&gpsPVRSRVData->hDeviceNodeListLock); + PVR_GOTO_IF_ERROR(eError, Error); + /* Register the driver context debug table */ eError = PVRSRVRegisterDriverDbgTable(); PVR_GOTO_IF_ERROR(eError, Error); @@ -1210,19 +1209,9 @@ PVRSRVCommonDriverInit(void) PVR_LOG_GOTO_IF_ERROR(eError, "OSThreadCreatePriority:3", Error); #endif /* SUPPORT_AUTOVZ */ - gpsPVRSRVData->psProcessHandleBase_Table = HASH_Create(PVRSRV_PROC_HANDLE_BASE_INIT); - - if (gpsPVRSRVData->psProcessHandleBase_Table == NULL) - { - PVR_LOG_GOTO_WITH_ERROR("psProcessHandleBase_Table", eError, PVRSRV_ERROR_UNABLE_TO_CREATE_HASH_TABLE, Error); - } - - eError = OSLockCreate(&gpsPVRSRVData->hProcessHandleBase_Lock); - PVR_LOG_GOTO_IF_ERROR(eError, "OSLockCreate:1", Error); - #if defined(SUPPORT_RGX) eError = OSLockCreate(&gpsPVRSRVData->hHWPerfHostPeriodicThread_Lock); - PVR_LOG_GOTO_IF_ERROR(eError, "OSLockCreate:2", Error); + PVR_LOG_GOTO_IF_ERROR(eError, "OSLockCreate", Error); #endif eError = HostMemDeviceCreate(&gpsPVRSRVData->psHostMemDeviceNode); @@ -1288,15 +1277,19 @@ PVRSRVCommonDriverInit(void) #endif #if defined(PDUMP) - /* Init PDumpBoundDevice (using mod param gPDumpDevice), default to device 0 */ - if (gPDumpDevice < PVRSRV_MAX_DEVICES) - { - psPVRSRVData->ui32PDumpBoundDevice = gPDumpDevice; - } - else - { - psPVRSRVData->ui32PDumpBoundDevice = 0; - } +#if (PVRSRV_DEVICE_INIT_MODE == PVRSRV_LINUX_DEV_INIT_ON_CONNECT) + /* If initialising the device on first connection, we will + * bind PDump capture to the first device we connect to later. + */ + psPVRSRVData->ui32PDumpBoundDevice = PVRSRV_MAX_DEVICES; +#else + /* If not initialising the device on first connection, bind PDump + * capture to device 0. This is because we need to capture PDump + * during device initialisation but only want to capture PDump for + * a single device (by default, device 0). + */ + psPVRSRVData->ui32PDumpBoundDevice = 0; +#endif #endif return 0; @@ -1326,12 +1319,6 @@ PVRSRVCommonDriverDeInit(void) gpsPVRSRVData->bUnload = IMG_TRUE; - if (gpsPVRSRVData->hProcessHandleBase_Lock) - { - OSLockDestroy(gpsPVRSRVData->hProcessHandleBase_Lock); - gpsPVRSRVData->hProcessHandleBase_Lock = NULL; - } - #if defined(SUPPORT_RGX) PVRSRVDestroyHWPerfHostThread(); if (gpsPVRSRVData->hHWPerfHostPeriodicThread_Lock) @@ -1341,12 +1328,6 @@ PVRSRVCommonDriverDeInit(void) } #endif - if (gpsPVRSRVData->psProcessHandleBase_Table) - { - HASH_Delete(gpsPVRSRVData->psProcessHandleBase_Table); - gpsPVRSRVData->psProcessHandleBase_Table = NULL; - } - if (gpsPVRSRVData->hGlobalEventObject) { OSEventObjectSignal(gpsPVRSRVData->hGlobalEventObject); @@ -1509,11 +1490,9 @@ PVRSRVCommonDriverDeInit(void) (void) DevmemIntDeInit(); - eError = ServerBridgeDeInit(); - PVR_LOG_IF_ERROR(eError, "ServerBridgeDeinit"); + ServerBridgeDeInit(); - eError = PhysHeapDeinit(); - PVR_LOG_IF_ERROR(eError, "PhysHeapDeinit"); + PhysHeapDeinit(); HTB_DestroyDIEntry(); @@ -1532,152 +1511,12 @@ PVRSRVCommonDriverDeInit(void) PVRSRVUnregisterDriverDbgTable(); + OSWRLockDestroy(gpsPVRSRVData->hDeviceNodeListLock); + OSFreeMem(gpsPVRSRVData); gpsPVRSRVData = NULL; } -#if defined(SUPPORT_GPUVIRT_VALIDATION) -/*************************************************************************/ /*! -@Function CreateGpuVirtValArenas -@Description Create virtualization validation arenas -@Input psDeviceNode The device node -@Return PVRSRV_ERROR PVRSRV_OK on success -*/ /**************************************************************************/ -static PVRSRV_ERROR CreateGpuVirtValArenas(PVRSRV_DEVICE_NODE *psDeviceNode) -{ - /* aui64OSidMin and aui64OSidMax are what we program into HW registers. - The values are different from base/size of arenas. */ - IMG_UINT64 aui64OSidMin[GPUVIRT_VALIDATION_NUM_REGIONS][GPUVIRT_VALIDATION_NUM_OS]; - IMG_UINT64 aui64OSidMax[GPUVIRT_VALIDATION_NUM_REGIONS][GPUVIRT_VALIDATION_NUM_OS]; - PHYS_HEAP_CONFIG *psGPULocalHeap = FindPhysHeapConfig(psDeviceNode->psDevConfig, PHYS_HEAP_USAGE_GPU_LOCAL); - PHYS_HEAP_CONFIG *psDisplayHeap = FindPhysHeapConfig(psDeviceNode->psDevConfig, PHYS_HEAP_USAGE_DISPLAY); - IMG_UINT64 uBase; - IMG_UINT64 uSize; - IMG_UINT64 uBaseShared; - IMG_UINT64 uSizeShared; - IMG_UINT64 uSizeSharedReg; - IMG_UINT32 i; - - /* Shared region is fixed size, the remaining space is divided amongst OSes */ - uSizeShared = PVR_ALIGN(GPUVIRT_SIZEOF_SHARED, (IMG_DEVMEM_SIZE_T)OSGetPageSize()); - uSize = psGPULocalHeap->uiSize - uSizeShared; - uSize /= GPUVIRT_VALIDATION_NUM_OS; - uSize = uSize & ~((IMG_UINT64)OSGetPageSize() - 1ULL); /* Align, round down */ - - uBase = psGPULocalHeap->sCardBase.uiAddr; - uBaseShared = uBase + uSize * GPUVIRT_VALIDATION_NUM_OS; - uSizeShared = psGPULocalHeap->uiSize - (uBaseShared - uBase); - - PVR_LOG(("GPUVIRT_VALIDATION split GPU_LOCAL base: 0x%" IMG_UINT64_FMTSPECX ", size: 0x%" IMG_UINT64_FMTSPECX ".", - psGPULocalHeap->sCardBase.uiAddr, - psGPULocalHeap->uiSize)); - - /* If a display heap config exists, include the display heap in the non-secure regions */ - if (psDisplayHeap) - { - /* Only works when DISPLAY heap follows GPU_LOCAL heap. */ - PVR_LOG(("GPUVIRT_VALIDATION include DISPLAY in shared, base: 0x%" IMG_UINT64_FMTSPECX ", size: 0x%" IMG_UINT64_FMTSPECX ".", - psDisplayHeap->sCardBase.uiAddr, - psDisplayHeap->uiSize)); - - uSizeSharedReg = uSizeShared + psDisplayHeap->uiSize; - } - else - { - uSizeSharedReg = uSizeShared; - } - - PVR_ASSERT(uSize >= GPUVIRT_MIN_SIZE); - PVR_ASSERT(uSizeSharedReg >= GPUVIRT_SIZEOF_SHARED); - - for (i = 0; i < GPUVIRT_VALIDATION_NUM_OS; i++) - { - IMG_CHAR aszOSRAName[RA_MAX_NAME_LENGTH]; - - PVR_LOG(("GPUVIRT_VALIDATION create arena OS: %d, base: 0x%" IMG_UINT64_FMTSPECX ", size: 0x%" IMG_UINT64_FMTSPECX ".", i, uBase, uSize)); - - OSSNPrintf(aszOSRAName, RA_MAX_NAME_LENGTH, "GPUVIRT_OS%d", i); - - psDeviceNode->psOSidSubArena[i] = RA_Create_With_Span(aszOSRAName, - OSGetPageShift(), - 0, - uBase, - uSize); - PVR_LOG_RETURN_IF_NOMEM(psDeviceNode->psOSidSubArena[i], "RA_Create_With_Span"); - - aui64OSidMin[GPUVIRT_VAL_REGION_SECURE][i] = uBase; - - if (i == 0) - { - /* OSid0 has access to all regions */ - aui64OSidMax[GPUVIRT_VAL_REGION_SECURE][i] = psGPULocalHeap->uiSize - 1ULL; - } - else - { - aui64OSidMax[GPUVIRT_VAL_REGION_SECURE][i] = uBase + uSize - 1ULL; - } - - /* uSizeSharedReg includes display heap */ - aui64OSidMin[GPUVIRT_VAL_REGION_SHARED][i] = uBaseShared; - aui64OSidMax[GPUVIRT_VAL_REGION_SHARED][i] = uBaseShared + uSizeSharedReg - 1ULL; - - PVR_LOG(("GPUVIRT_VALIDATION HW reg regions %d: min[0]: 0x%" IMG_UINT64_FMTSPECX ", max[0]: 0x%" IMG_UINT64_FMTSPECX ", min[1]: 0x%" IMG_UINT64_FMTSPECX ", max[1]: 0x%" IMG_UINT64_FMTSPECX ",", - i, - aui64OSidMin[GPUVIRT_VAL_REGION_SECURE][i], - aui64OSidMax[GPUVIRT_VAL_REGION_SECURE][i], - aui64OSidMin[GPUVIRT_VAL_REGION_SHARED][i], - aui64OSidMax[GPUVIRT_VAL_REGION_SHARED][i])); - uBase += uSize; - } - - PVR_LOG(("GPUVIRT_VALIDATION create arena Shared, base: 0x%" IMG_UINT64_FMTSPECX ", size: 0x%" IMG_UINT64_FMTSPECX ".", uBaseShared, uSizeShared)); - - PVR_ASSERT(uSizeShared >= GPUVIRT_SIZEOF_SHARED); - - /* uSizeShared does not include display heap */ - psDeviceNode->psOSSharedArena = RA_Create_With_Span("GPUVIRT_SHARED", - OSGetPageShift(), - 0, - uBaseShared, - uSizeShared); - PVR_LOG_RETURN_IF_NOMEM(psDeviceNode->psOSSharedArena, "RA_Create_With_Span"); - - if (psDeviceNode->psDevConfig->pfnSysDevVirtInit != NULL) - { - psDeviceNode->psDevConfig->pfnSysDevVirtInit(aui64OSidMin, aui64OSidMax); - } - - return PVRSRV_OK; -} - -/* - * Counter-part to CreateGpuVirtValArenas. - */ -static void DestroyGpuVirtValArenas(PVRSRV_DEVICE_NODE *psDeviceNode) -{ - IMG_UINT32 uiCounter = 0; - - /* - * NOTE: We overload psOSidSubArena[0] into the psLocalMemArena so we must - * not free it here as it gets cleared later. - */ - for (uiCounter = 1; uiCounter < GPUVIRT_VALIDATION_NUM_OS; uiCounter++) - { - if (psDeviceNode->psOSidSubArena[uiCounter] == NULL) - { - continue; - } - RA_Delete(psDeviceNode->psOSidSubArena[uiCounter]); - } - - if (psDeviceNode->psOSSharedArena != NULL) - { - RA_Delete(psDeviceNode->psOSSharedArena); - } -} - -#endif - static void _SysDebugRequestNotify(PVRSRV_DBGREQ_HANDLE hDebugRequestHandle, IMG_UINT32 ui32VerbLevel, DUMPDEBUG_PRINTF_FUNC *pfnDumpDebugPrintf, @@ -1708,6 +1547,8 @@ static void _SysDebugRequestNotify(PVRSRV_DBGREQ_HANDLE hDebugRequestHandle, SysDebugInfo(psDeviceNode->psDevConfig, pfnDumpDebugPrintf, pvDumpDebugFile); } +#define PVRSRV_MIN_DEFAULT_LMA_PHYS_HEAP_SIZE (0x100000ULL * 32ULL) /* 32MB */ + static PVRSRV_ERROR PVRSRVValidatePhysHeapConfig(PVRSRV_DEVICE_CONFIG *psDevConfig) { IMG_UINT32 ui32FlagsAccumulate = 0; @@ -1730,6 +1571,22 @@ static PVRSRV_ERROR PVRSRVValidatePhysHeapConfig(PVRSRV_DEVICE_CONFIG *psDevConf "Phys heap config %d: duplicate usage flags.", i); ui32FlagsAccumulate |= psHeapConf->ui32UsageFlags; + + /* Output message if default heap is LMA and smaller than recommended minimum */ + if ((i == psDevConfig->eDefaultHeap) && +#if defined(__KERNEL__) + ((psHeapConf->eType == PHYS_HEAP_TYPE_LMA) || + (psHeapConf->eType == PHYS_HEAP_TYPE_DMA)) && +#else + (psHeapConf->eType == PHYS_HEAP_TYPE_LMA) && +#endif + (psHeapConf->uiSize < PVRSRV_MIN_DEFAULT_LMA_PHYS_HEAP_SIZE)) + { + PVR_DPF((PVR_DBG_ERROR, "%s: Size of default heap is 0x%" IMG_UINT64_FMTSPECX + " (recommended minimum heap size is 0x%llx)", + __func__, psHeapConf->uiSize, + PVRSRV_MIN_DEFAULT_LMA_PHYS_HEAP_SIZE)); + } } if (psDevConfig->eDefaultHeap == PVRSRV_PHYS_HEAP_GPU_LOCAL) @@ -1751,25 +1608,15 @@ static PVRSRV_ERROR PVRSRVValidatePhysHeapConfig(PVRSRV_DEVICE_CONFIG *psDevConf PVRSRV_ERROR PVRSRVPhysMemHeapsInit(PVRSRV_DEVICE_NODE *psDeviceNode, PVRSRV_DEVICE_CONFIG *psDevConfig) { PVRSRV_ERROR eError; - PHYS_HEAP *psPhysHeap; - PHYS_HEAP_TYPE eHeapType; PVRSRV_PHYS_HEAP ePhysHeap; eError = PVRSRVValidatePhysHeapConfig(psDevConfig); PVR_LOG_RETURN_IF_ERROR(eError, "PVRSRVValidatePhysHeapConfig"); - /* Register the physical memory heaps */ - psDeviceNode->papsRegisteredPhysHeaps = - OSAllocZMem(sizeof(*psDeviceNode->papsRegisteredPhysHeaps) * - psDevConfig->ui32PhysHeapCount); - PVR_RETURN_IF_NOMEM(psDeviceNode->papsRegisteredPhysHeaps); - - eError = PhysHeapCreateHeapsFromConfigs(psDeviceNode, - psDevConfig->pasPhysHeaps, - psDevConfig->ui32PhysHeapCount, - psDeviceNode->papsRegisteredPhysHeaps, - &psDeviceNode->ui32RegisteredPhysHeaps); - PVR_LOG_GOTO_IF_ERROR(eError, "PhysHeapCreateHeapsFromConfigs", ErrorDeinit); + eError = PhysHeapCreateDeviceHeapsFromConfigs(psDeviceNode, + psDevConfig->pasPhysHeaps, + psDevConfig->ui32PhysHeapCount); + PVR_LOG_GOTO_IF_ERROR(eError, "PhysHeapCreateDeviceHeapsFromConfigs", ErrorDeinit); for (ePhysHeap = PVRSRV_PHYS_HEAP_DEFAULT+1; ePhysHeap < PVRSRV_PHYS_HEAP_LAST; ePhysHeap++) { @@ -1791,48 +1638,8 @@ PVRSRV_ERROR PVRSRVPhysMemHeapsInit(PVRSRV_DEVICE_NODE *psDeviceNode, PVRSRV_DEV PVR_LOG_GOTO_IF_ERROR(eError, "PVRSRVPhysHeapCheckUsageFlags", ErrorDeinit); } - eHeapType = PhysHeapGetType(psDeviceNode->apsPhysHeap[PVRSRV_PHYS_HEAP_GPU_LOCAL]); - if (eHeapType == PHYS_HEAP_TYPE_UMA) - { - PVR_DPF((PVR_DBG_MESSAGE, "%s: GPU physical heap uses OS System memory (UMA)", __func__)); - - psDeviceNode->sDevMMUPxSetup.pfnDevPxAlloc = OSPhyContigPagesAlloc; - psDeviceNode->sDevMMUPxSetup.pfnDevPxFree = OSPhyContigPagesFree; - psDeviceNode->sDevMMUPxSetup.pfnDevPxMap = OSPhyContigPagesMap; - psDeviceNode->sDevMMUPxSetup.pfnDevPxUnMap = OSPhyContigPagesUnmap; - psDeviceNode->sDevMMUPxSetup.pfnDevPxClean = OSPhyContigPagesClean; - psDeviceNode->sDevMMUPxSetup.psPxRA = NULL; - -#if defined(SUPPORT_GPUVIRT_VALIDATION) - PVR_DPF((PVR_DBG_ERROR, "%s: Virtualisation Validation builds are currently only" - " supported on systems with local memory (LMA).", __func__)); - eError = PVRSRV_ERROR_NOT_SUPPORTED; - goto ErrorDeinit; -#endif - } - else - { - psPhysHeap = psDeviceNode->apsPhysHeap[PVRSRV_PHYS_HEAP_GPU_LOCAL]; - - PVR_DPF((PVR_DBG_MESSAGE, "%s: GPU physical heap uses local memory managed by the driver (LMA)", __func__)); - - psDeviceNode->sDevMMUPxSetup.pfnDevPxAlloc = LMA_PhyContigPagesAlloc; - psDeviceNode->sDevMMUPxSetup.pfnDevPxFree = LMA_PhyContigPagesFree; - psDeviceNode->sDevMMUPxSetup.pfnDevPxMap = LMA_PhyContigPagesMap; - psDeviceNode->sDevMMUPxSetup.pfnDevPxUnMap = LMA_PhyContigPagesUnmap; - psDeviceNode->sDevMMUPxSetup.pfnDevPxClean = LMA_PhyContigPagesClean; - -#if defined(SUPPORT_GPUVIRT_VALIDATION) - eError = CreateGpuVirtValArenas(psDeviceNode); - PVR_LOG_GOTO_IF_ERROR(eError, "CreateGpuVirtValArenas", ErrorDeinit); - - psDeviceNode->sDevMMUPxSetup.psPxRA = psDeviceNode->psOSidSubArena[0]; - psDeviceNode->sDevMMUPxSetup.pfnDevPxAllocGPV = LMA_PhyContigPagesAllocGPV; -#else - eError = PhysmemGetArenaLMA(psPhysHeap, &psDeviceNode->sDevMMUPxSetup.psPxRA); - PVR_LOG_GOTO_IF_ERROR(eError, "PhysmemGetArenaLMA", ErrorDeinit); -#endif - } + eError = PhysHeapMMUPxSetup(psDeviceNode); + PVR_LOG_GOTO_IF_ERROR(eError, "PhysHeapMMUPxSetup", ErrorDeinit); return PVRSRV_OK; @@ -1848,18 +1655,15 @@ void PVRSRVPhysMemHeapsDeinit(PVRSRV_DEVICE_NODE *psDeviceNode) PVRSRV_PHYS_HEAP ePhysHeapIdx; IMG_UINT32 i; - if (psDeviceNode->psFwMMUReservedMemArena) +#if defined(SUPPORT_AUTOVZ) + if (psDeviceNode->psFwMMUReservedPhysHeap) { - RA_Delete(psDeviceNode->psFwMMUReservedMemArena); - psDeviceNode->psFwMMUReservedMemArena = NULL; + PhysHeapDestroy(psDeviceNode->psFwMMUReservedPhysHeap); + psDeviceNode->psFwMMUReservedPhysHeap = NULL; } +#endif -#if defined(SUPPORT_GPUVIRT_VALIDATION) - /* Remove local LMA subarenas */ - DestroyGpuVirtValArenas(psDeviceNode); -#endif /* defined(SUPPORT_GPUVIRT_VALIDATION) */ - - psDeviceNode->sDevMMUPxSetup.psPxRA = NULL; + PhysHeapMMUPxDeInit(psDeviceNode); /* Release heaps */ for (ePhysHeapIdx = 0; @@ -1893,13 +1697,7 @@ void PVRSRVPhysMemHeapsDeinit(PVRSRV_DEVICE_NODE *psDeviceNode) } } - /* Unregister heaps */ - for (i = 0; i < psDeviceNode->ui32RegisteredPhysHeaps; i++) - { - PhysHeapDestroy(psDeviceNode->papsRegisteredPhysHeaps[i]); - } - - OSFreeMem(psDeviceNode->papsRegisteredPhysHeaps); + PhysHeapDestroyDeviceHeaps(psDeviceNode); } PHYS_HEAP_CONFIG* FindPhysHeapConfig(PVRSRV_DEVICE_CONFIG *psDevConfig, @@ -1978,13 +1776,23 @@ PVRSRV_ERROR PVRSRVCommonDeviceCreate(void *pvOSDevice, psDeviceNode->eDevState = PVRSRV_DEVICE_STATE_INIT; + if (psDevConfig->pfnGpuDomainPower) + { + psDeviceNode->eCurrentSysPowerState = psDevConfig->pfnGpuDomainPower(psDeviceNode); + } + else + { + /* If the System Layer doesn't provide a function to query the power state + * of the system hardware, use a default implementation that keeps track of + * the power state locally and assumes the system starting state */ + psDevConfig->pfnGpuDomainPower = PVRSRVDefaultDomainPower; + #if defined(SUPPORT_AUTOVZ) - /* AutoVz platforms should have the GPU domain powered on before startup */ - psDeviceNode->eCurrentSysPowerState = PVRSRV_SYS_POWER_STATE_ON; + psDeviceNode->eCurrentSysPowerState = PVRSRV_SYS_POWER_STATE_ON; #else - /* Assume system power is off at start of day and turned on by the time we hit RGXInitDevPart2 */ - psDeviceNode->eCurrentSysPowerState = PVRSRV_SYS_POWER_STATE_OFF; + psDeviceNode->eCurrentSysPowerState = PVRSRV_SYS_POWER_STATE_OFF; #endif + } psDeviceNode->psDevConfig = psDevConfig; psDevConfig->psDevNode = psDeviceNode; @@ -2058,8 +1866,6 @@ PVRSRV_ERROR PVRSRVCommonDeviceCreate(void *pvOSDevice, PVR_GOTO_IF_ERROR(eError, ErrorFwMMUDeinit); } - psDeviceNode->sDevMMUPxSetup.uiMMUPxLog2AllocGran = OSGetPageShift(); - eError = SyncServerInit(psDeviceNode); PVR_GOTO_IF_ERROR(eError, ErrorDeInitRgx); @@ -2077,11 +1883,9 @@ PVRSRV_ERROR PVRSRVCommonDeviceCreate(void *pvOSDevice, psDeviceNode); PVR_LOG_GOTO_IF_ERROR(eError, "PVRSRVRegisterDeviceDbgRequestNotify", ErrorRegDbgReqNotify); - psPVRSRVData->ui32RegisteredDevices++; - #if defined(SUPPORT_LINUX_DVFS) && !defined(NO_HARDWARE) eError = InitDVFS(psDeviceNode); - PVR_LOG_GOTO_IF_ERROR(eError, "InitDVFS", ErrorDecrementDeviceCount); + PVR_LOG_GOTO_IF_ERROR(eError, "InitDVFS", ErrorDVFSInitFail); #endif OSAtomicWrite(&psDeviceNode->iNumClockSpeedChanges, 0); @@ -2095,7 +1899,7 @@ PVRSRV_ERROR PVRSRVCommonDeviceCreate(void *pvOSDevice, { PVR_DPF((PVR_DBG_ERROR, "%s: Failed to create lock for PF notify list", __func__)); - goto ErrorDecrementDeviceCount; + goto ErrorPageFaultLockFailCreate; } dllist_init(&psDeviceNode->sMemoryContextPageFaultNotifyListHead); @@ -2140,11 +1944,20 @@ PVRSRV_ERROR PVRSRVCommonDeviceCreate(void *pvOSDevice, ErrorDestroyMemoryContextPageFaultNotifyListLock); /* Finally insert the device into the dev-list and set it as active */ + OSWRLockAcquireWrite(psPVRSRVData->hDeviceNodeListLock); List_PVRSRV_DEVICE_NODE_InsertTail(&psPVRSRVData->psDeviceNodeList, psDeviceNode); + psPVRSRVData->ui32RegisteredDevices++; + OSWRLockReleaseWrite(psPVRSRVData->hDeviceNodeListLock); *ppsDeviceNode = psDeviceNode; +#if defined(SUPPORT_LINUX_DVFS) && !defined(NO_HARDWARE) + /* Register the DVFS device now the device node is present in the dev-list */ + eError = RegisterDVFSDevice(psDeviceNode); + PVR_LOG_GOTO_IF_ERROR(eError, "RegisterDVFSDevice", ErrorRegisterDVFSDeviceFail); +#endif + #if defined(PVRSRV_ENABLE_PROCESS_STATS) && !defined(PVRSRV_DEBUG_LINUX_MEMORY_STATS) /* Close the process statistics */ PVRSRVStatsDeregisterProcess(hProcessStats); @@ -2156,16 +1969,28 @@ PVRSRV_ERROR PVRSRVCommonDeviceCreate(void *pvOSDevice, return PVRSRV_OK; +#if defined(SUPPORT_LINUX_DVFS) && !defined(NO_HARDWARE) +ErrorRegisterDVFSDeviceFail: + /* Remove the device from the list */ + OSWRLockAcquireWrite(psPVRSRVData->hDeviceNodeListLock); + List_PVRSRV_DEVICE_NODE_Remove(psDeviceNode); + psPVRSRVData->ui32RegisteredDevices--; + OSWRLockReleaseWrite(psPVRSRVData->hDeviceNodeListLock); +#endif + ErrorDestroyMemoryContextPageFaultNotifyListLock: OSWRLockDestroy(psDeviceNode->hMemoryContextPageFaultNotifyListLock); psDeviceNode->hMemoryContextPageFaultNotifyListLock = NULL; -ErrorDecrementDeviceCount: - psPVRSRVData->ui32RegisteredDevices--; +ErrorPageFaultLockFailCreate: #if defined(PVR_TESTING_UTILS) TUtilsDeinit(psDeviceNode); #endif +#if defined(SUPPORT_LINUX_DVFS) && !defined(NO_HARDWARE) +ErrorDVFSInitFail: +#endif + if (psDeviceNode->hDbgReqNotify) { PVRSRVUnregisterDeviceDbgRequestNotify(psDeviceNode->hDbgReqNotify); @@ -2300,6 +2125,20 @@ PVRSRV_ERROR PVRSRVCommonDeviceInitialise(PVRSRV_DEVICE_NODE *psDeviceNode) return PVRSRV_ERROR_INIT_FAILURE; } +#if defined(PDUMP) +#if (PVRSRV_DEVICE_INIT_MODE == PVRSRV_LINUX_DEV_INIT_ON_CONNECT) + { + PVRSRV_DATA *psSRVData = PVRSRVGetPVRSRVData(); + + /* If first connection, bind this and future PDump clients to use this device */ + if (psSRVData->ui32PDumpBoundDevice == PVRSRV_MAX_DEVICES) + { + psSRVData->ui32PDumpBoundDevice = psDeviceNode->sDevId.ui32InternalID; + } + } +#endif +#endif + /* Initialise Connection_Data access mechanism */ dllist_init(&psDeviceNode->sConnections); eError = OSLockCreate(&psDeviceNode->hConnectionsLock); @@ -2397,10 +2236,17 @@ PVRSRV_ERROR PVRSRVCommonDeviceDestroy(PVRSRV_DEVICE_NODE *psDeviceNode) MULTI_DEVICE_BRINGUP_DPF("PVRSRVCommonDeviceDestroy: DevId %d", psDeviceNode->sDevId.i32OsDeviceID); - psPVRSRVData->ui32RegisteredDevices--; - psDeviceNode->eDevState = PVRSRV_DEVICE_STATE_DEINIT; +#if defined(SUPPORT_LINUX_DVFS) && !defined(NO_HARDWARE) + UnregisterDVFSDevice(psDeviceNode); +#endif + + OSWRLockAcquireWrite(psPVRSRVData->hDeviceNodeListLock); + List_PVRSRV_DEVICE_NODE_Remove(psDeviceNode); + psPVRSRVData->ui32RegisteredDevices--; + OSWRLockReleaseWrite(psPVRSRVData->hDeviceNodeListLock); + #if defined(__linux__) pvr_apphint_device_unregister(psDeviceNode); #endif /* defined(__linux__) */ @@ -2529,8 +2375,6 @@ PVRSRV_ERROR PVRSRVCommonDeviceDestroy(PVRSRV_DEVICE_NODE *psDeviceNode) DevDeInitRGX(psDeviceNode); #endif - List_PVRSRV_DEVICE_NODE_Remove(psDeviceNode); - PVRSRVPhysMemHeapsDeinit(psDeviceNode); PVRSRVPowerLockDeInit(psDeviceNode); @@ -2539,8 +2383,7 @@ PVRSRV_ERROR PVRSRVCommonDeviceDestroy(PVRSRV_DEVICE_NODE *psDeviceNode) /* Release the Connection-Data lock as late as possible. */ if (psDeviceNode->hConnectionsLock) { - eError = OSLockDestroy(psDeviceNode->hConnectionsLock); - PVR_LOG_IF_ERROR(eError, "ConnectionLock destruction failed"); + OSLockDestroy(psDeviceNode->hConnectionsLock); } psDeviceNode->psDevConfig->psDevNode = NULL; @@ -2556,264 +2399,6 @@ PVRSRV_ERROR PVRSRVCommonDeviceDestroy(PVRSRV_DEVICE_NODE *psDeviceNode) return PVRSRV_OK; } -static PVRSRV_ERROR _LMA_DoPhyContigPagesAlloc(RA_ARENA *pArena, - size_t uiSize, - PG_HANDLE *psMemHandle, - IMG_DEV_PHYADDR *psDevPAddr, - IMG_PID uiPid) -{ - RA_BASE_T uiCardAddr = 0; - RA_LENGTH_T uiActualSize; - PVRSRV_ERROR eError; -#if defined(DEBUG) - static IMG_UINT32 ui32MaxLog2NumPages = 4; /* 16 pages => 64KB */ -#endif /* defined(DEBUG) */ - - IMG_UINT32 ui32Log2NumPages = 0; - - PVR_ASSERT(uiSize != 0); - ui32Log2NumPages = OSGetOrder(uiSize); - uiSize = (1 << ui32Log2NumPages) * OSGetPageSize(); - - eError = RA_Alloc(pArena, - uiSize, - RA_NO_IMPORT_MULTIPLIER, - 0, /* No flags */ - uiSize, - "LMA_PhyContigPagesAlloc", - &uiCardAddr, - &uiActualSize, - NULL); /* No private handle */ - - PVR_ASSERT(uiSize == uiActualSize); - - psMemHandle->u.ui64Handle = uiCardAddr; - psDevPAddr->uiAddr = (IMG_UINT64) uiCardAddr; - - if (PVRSRV_OK == eError) - { -#if defined(PVRSRV_ENABLE_PROCESS_STATS) -#if !defined(PVRSRV_ENABLE_MEMORY_STATS) - PVRSRVStatsIncrMemAllocStatAndTrack(PVRSRV_MEM_ALLOC_TYPE_ALLOC_PAGES_PT_LMA, - uiSize, - uiCardAddr, - uiPid); -#else - IMG_CPU_PHYADDR sCpuPAddr; - sCpuPAddr.uiAddr = psDevPAddr->uiAddr; - - PVRSRVStatsAddMemAllocRecord(PVRSRV_MEM_ALLOC_TYPE_ALLOC_PAGES_PT_LMA, - NULL, - sCpuPAddr, - uiSize, - NULL, - uiPid - DEBUG_MEMSTATS_VALUES); -#endif -#endif -#if defined(SUPPORT_GPUVIRT_VALIDATION) - PVR_DPF((PVR_DBG_MESSAGE, - "%s: (GPU Virtualisation) Allocated 0x" IMG_SIZE_FMTSPECX " at 0x%" IMG_UINT64_FMTSPECX ", Arena ID %u", - __func__, uiSize, psDevPAddr->uiAddr, psMemHandle->uiOSid)); -#endif - -#if defined(DEBUG) - PVR_ASSERT((ui32Log2NumPages <= ui32MaxLog2NumPages)); - if (ui32Log2NumPages > ui32MaxLog2NumPages) - { - PVR_DPF((PVR_DBG_ERROR, - "%s: ui32MaxLog2NumPages = %u, increasing to %u", __func__, - ui32MaxLog2NumPages, ui32Log2NumPages )); - ui32MaxLog2NumPages = ui32Log2NumPages; - } -#endif /* defined(DEBUG) */ - psMemHandle->uiOrder = ui32Log2NumPages; - } - - return eError; -} - -#if defined(SUPPORT_GPUVIRT_VALIDATION) -PVRSRV_ERROR LMA_PhyContigPagesAllocGPV(PVRSRV_DEVICE_NODE *psDevNode, size_t uiSize, - PG_HANDLE *psMemHandle, IMG_DEV_PHYADDR *psDevPAddr, - IMG_UINT32 ui32OSid, IMG_PID uiPid) -{ - RA_ARENA *pArena; - IMG_UINT32 ui32Log2NumPages = 0; - PVRSRV_ERROR eError; - - PVR_ASSERT(uiSize != 0); - ui32Log2NumPages = OSGetOrder(uiSize); - uiSize = (1 << ui32Log2NumPages) * OSGetPageSize(); - - PVR_ASSERT(ui32OSid < GPUVIRT_VALIDATION_NUM_OS); - if (ui32OSid >= GPUVIRT_VALIDATION_NUM_OS) - { - PVR_DPF((PVR_DBG_ERROR, "%s: Invalid Arena index %u defaulting to 0", - __func__, ui32OSid)); - ui32OSid = 0; - } - pArena = psDevNode->psOSidSubArena[ui32OSid]; - - if (psMemHandle->uiOSid != ui32OSid) - { - PVR_LOG(("%s: Unexpected OSid value %u - expecting %u", __func__, - psMemHandle->uiOSid, ui32OSid)); - } - - psMemHandle->uiOSid = ui32OSid; /* For Free() use */ - - eError = _LMA_DoPhyContigPagesAlloc(pArena, uiSize, psMemHandle, - psDevPAddr, uiPid); - PVR_LOG_IF_ERROR(eError, "_LMA_DoPhyContigPagesAlloc"); - - return eError; -} -#endif - -PVRSRV_ERROR LMA_PhyContigPagesAlloc(PVRSRV_DEVICE_NODE *psDevNode, size_t uiSize, - PG_HANDLE *psMemHandle, IMG_DEV_PHYADDR *psDevPAddr, - IMG_PID uiPid) -{ - PVRSRV_ERROR eError; - - RA_ARENA *pArena = psDevNode->sDevMMUPxSetup.psPxRA; - IMG_UINT32 ui32Log2NumPages = 0; - - PVR_ASSERT(uiSize != 0); - ui32Log2NumPages = OSGetOrder(uiSize); - uiSize = (1 << ui32Log2NumPages) * OSGetPageSize(); - - eError = _LMA_DoPhyContigPagesAlloc(pArena, uiSize, psMemHandle, - psDevPAddr, uiPid); - PVR_LOG_IF_ERROR(eError, "_LMA_DoPhyContigPagesAlloc"); - - return eError; -} - -void LMA_PhyContigPagesFree(PVRSRV_DEVICE_NODE *psDevNode, PG_HANDLE *psMemHandle) -{ - RA_BASE_T uiCardAddr = (RA_BASE_T) psMemHandle->u.ui64Handle; - RA_ARENA *pArena; -#if defined(SUPPORT_GPUVIRT_VALIDATION) - IMG_UINT32 ui32OSid = psMemHandle->uiOSid; - - /* - * The Arena ID is set by the originating allocation, and maintained via - * the call stacks into this function. We have a limited range of IDs - * and if the passed value falls outside this we simply treat it as a - * 'global' arena ID of 0. This is where all default OS-specific allocations - * are created. - */ - PVR_ASSERT(ui32OSid < GPUVIRT_VALIDATION_NUM_OS); - if (ui32OSid >= GPUVIRT_VALIDATION_NUM_OS) - { - PVR_DPF((PVR_DBG_ERROR, "%s: Invalid Arena index %u PhysAddr 0x%" - IMG_UINT64_FMTSPECx " Reverting to Arena 0", __func__, - ui32OSid, uiCardAddr)); - /* - * No way of determining what we're trying to free so default to the - * global default arena index 0. - */ - ui32OSid = 0; - } - - pArena = psDevNode->psOSidSubArena[ui32OSid]; - - PVR_DPF((PVR_DBG_MESSAGE, "%s: (GPU Virtualisation) Freeing 0x%" - IMG_UINT64_FMTSPECx ", Arena %u", __func__, - uiCardAddr, ui32OSid)); - -#else - pArena = psDevNode->sDevMMUPxSetup.psPxRA; -#endif - -#if defined(PVRSRV_ENABLE_PROCESS_STATS) -#if !defined(PVRSRV_ENABLE_MEMORY_STATS) - PVRSRVStatsDecrMemAllocStatAndUntrack(PVRSRV_MEM_ALLOC_TYPE_ALLOC_PAGES_PT_LMA, - (IMG_UINT64)uiCardAddr); -#else - PVRSRVStatsRemoveMemAllocRecord(PVRSRV_MEM_ALLOC_TYPE_ALLOC_PAGES_PT_LMA, - (IMG_UINT64)uiCardAddr, - OSGetCurrentClientProcessIDKM()); -#endif -#endif - - RA_Free(pArena, uiCardAddr); - psMemHandle->uiOrder = 0; -} - -PVRSRV_ERROR LMA_PhyContigPagesMap(PVRSRV_DEVICE_NODE *psDevNode, PG_HANDLE *psMemHandle, - size_t uiSize, IMG_DEV_PHYADDR *psDevPAddr, - void **pvPtr) -{ - IMG_CPU_PHYADDR sCpuPAddr; - IMG_UINT32 ui32NumPages = (1 << psMemHandle->uiOrder); - PVR_UNREFERENCED_PARAMETER(psMemHandle); - PVR_UNREFERENCED_PARAMETER(uiSize); - - PhysHeapDevPAddrToCpuPAddr(psDevNode->apsPhysHeap[PVRSRV_PHYS_HEAP_GPU_LOCAL], 1, &sCpuPAddr, psDevPAddr); - *pvPtr = OSMapPhysToLin(sCpuPAddr, - ui32NumPages * OSGetPageSize(), - PVRSRV_MEMALLOCFLAG_CPU_UNCACHED_WC); - PVR_RETURN_IF_NOMEM(*pvPtr); - -#if defined(PVRSRV_ENABLE_PROCESS_STATS) -#if !defined(PVRSRV_ENABLE_MEMORY_STATS) - PVRSRVStatsIncrMemAllocStat(PVRSRV_MEM_ALLOC_TYPE_IOREMAP_PT_LMA, - ui32NumPages * OSGetPageSize(), - OSGetCurrentClientProcessIDKM()); -#else - { - PVRSRVStatsAddMemAllocRecord(PVRSRV_MEM_ALLOC_TYPE_IOREMAP_PT_LMA, - *pvPtr, - sCpuPAddr, - ui32NumPages * OSGetPageSize(), - NULL, - OSGetCurrentClientProcessIDKM() - DEBUG_MEMSTATS_VALUES); - } -#endif -#endif - return PVRSRV_OK; -} - -void LMA_PhyContigPagesUnmap(PVRSRV_DEVICE_NODE *psDevNode, PG_HANDLE *psMemHandle, - void *pvPtr) -{ - IMG_UINT32 ui32NumPages = (1 << psMemHandle->uiOrder); - PVR_UNREFERENCED_PARAMETER(psMemHandle); - PVR_UNREFERENCED_PARAMETER(psDevNode); - -#if defined(PVRSRV_ENABLE_PROCESS_STATS) -#if !defined(PVRSRV_ENABLE_MEMORY_STATS) - PVRSRVStatsDecrMemAllocStat(PVRSRV_MEM_ALLOC_TYPE_IOREMAP_PT_LMA, - ui32NumPages * OSGetPageSize(), - OSGetCurrentClientProcessIDKM()); -#else - PVRSRVStatsRemoveMemAllocRecord(PVRSRV_MEM_ALLOC_TYPE_IOREMAP_PT_LMA, - (IMG_UINT64)(uintptr_t)pvPtr, - OSGetCurrentClientProcessIDKM()); -#endif -#endif - - OSUnMapPhysToLin(pvPtr, ui32NumPages * OSGetPageSize()); -} - -PVRSRV_ERROR LMA_PhyContigPagesClean(PVRSRV_DEVICE_NODE *psDevNode, - PG_HANDLE *psMemHandle, - IMG_UINT32 uiOffset, - IMG_UINT32 uiLength) -{ - /* No need to flush because we map as uncached */ - PVR_UNREFERENCED_PARAMETER(psDevNode); - PVR_UNREFERENCED_PARAMETER(psMemHandle); - PVR_UNREFERENCED_PARAMETER(uiOffset); - PVR_UNREFERENCED_PARAMETER(uiLength); - - return PVRSRV_OK; -} - /**************************************************************************/ /*! @Function PVRSRVDeviceFinalise @Description Performs the final parts of device initialisation. @@ -2903,7 +2488,7 @@ PVRSRV_ERROR PVRSRVDeviceFinalise(PVRSRV_DEVICE_NODE *psDeviceNode, goto ErrorExit; } - PDUMPPOWCMDSTART(); + PDUMPPOWCMDSTART(psDeviceNode); /* Force the device to idle if its default power state is off */ eError = PVRSRVDeviceIdleRequestKM(psDeviceNode, @@ -2923,7 +2508,7 @@ PVRSRV_ERROR PVRSRVDeviceFinalise(PVRSRV_DEVICE_NODE *psDeviceNode, eError = PVRSRVSetDevicePowerStateKM(psDeviceNode, PVRSRV_DEV_POWER_STATE_DEFAULT, PVRSRV_POWER_FLAGS_FORCED); - PDUMPPOWCMDEND(); + PDUMPPOWCMDEND(psDeviceNode); if (eError != PVRSRV_OK) { @@ -3246,10 +2831,13 @@ PVRSRV_ERROR PVRSRVSystemInstallDeviceLISR(void *pvOSDevice, PVRSRV_DATA *psPVRSRVData = PVRSRVGetPVRSRVData(); PVRSRV_DEVICE_NODE *psDeviceNode; + OSWRLockAcquireRead(psPVRSRVData->hDeviceNodeListLock); psDeviceNode = List_PVRSRV_DEVICE_NODE_Any_va(psPVRSRVData->psDeviceNodeList, &PVRSRVSystemInstallDeviceLISR_Match_AnyVaCb, pvOSDevice); + OSWRLockReleaseRead(psPVRSRVData->hDeviceNodeListLock); + if (!psDeviceNode) { /* Device can't be found in the list so it isn't in the system */ @@ -3287,9 +2875,10 @@ PVRSRV_ERROR PVRSRVCreateHWPerfHostThread(IMG_UINT32 ui32Timeout) if (!ui32Timeout) return PVRSRV_ERROR_INVALID_PARAMS; - if (gpsPVRSRVData->hHWPerfHostPeriodicThread_Lock) { - OSLockAcquire(gpsPVRSRVData->hHWPerfHostPeriodicThread_Lock); - } + + if (gpsPVRSRVData->hHWPerfHostPeriodicThread_Lock) { + OSLockAcquire(gpsPVRSRVData->hHWPerfHostPeriodicThread_Lock); + } /* Create only once */ if (gpsPVRSRVData->hHWPerfHostPeriodicThread == NULL) @@ -3317,9 +2906,11 @@ PVRSRV_ERROR PVRSRVCreateHWPerfHostThread(IMG_UINT32 ui32Timeout) eError = OSEventObjectSignal(gpsPVRSRVData->hHWPerfHostPeriodicEvObj); PVR_LOG_IF_ERROR(eError, "OSEventObjectSignal"); } - if (gpsPVRSRVData->hHWPerfHostPeriodicThread_Lock) { - OSLockRelease(gpsPVRSRVData->hHWPerfHostPeriodicThread_Lock); - } + + if (gpsPVRSRVData->hHWPerfHostPeriodicThread_Lock) { + OSLockRelease(gpsPVRSRVData->hHWPerfHostPeriodicThread_Lock); + } + return eError; } @@ -3327,9 +2918,9 @@ PVRSRV_ERROR PVRSRVDestroyHWPerfHostThread(void) { PVRSRV_ERROR eError = PVRSRV_OK; - if (gpsPVRSRVData->hHWPerfHostPeriodicThread_Lock) { - OSLockAcquire(gpsPVRSRVData->hHWPerfHostPeriodicThread_Lock); - } + if (gpsPVRSRVData->hHWPerfHostPeriodicThread_Lock) { + OSLockAcquire(gpsPVRSRVData->hHWPerfHostPeriodicThread_Lock); + } /* Stop and cleanup the HWPerf periodic thread */ if (gpsPVRSRVData->hHWPerfHostPeriodicThread) @@ -3360,9 +2951,10 @@ PVRSRV_ERROR PVRSRVDestroyHWPerfHostThread(void) } } - if (gpsPVRSRVData->hHWPerfHostPeriodicThread_Lock) { - OSLockRelease(gpsPVRSRVData->hHWPerfHostPeriodicThread_Lock); - } + if (gpsPVRSRVData->hHWPerfHostPeriodicThread_Lock) { + OSLockRelease(gpsPVRSRVData->hHWPerfHostPeriodicThread_Lock); + } + return eError; } #endif @@ -3379,32 +2971,42 @@ PVRSRV_DEVICE_NODE *PVRSRVGetDeviceInstance(IMG_UINT32 uiInstance) { return NULL; } + OSWRLockAcquireRead(gpsPVRSRVData->hDeviceNodeListLock); for (psDevNode = gpsPVRSRVData->psDeviceNodeList; psDevNode != NULL; psDevNode = psDevNode->psNext) { if (uiInstance == psDevNode->sDevId.ui32InternalID) { - return psDevNode; + break; } } + OSWRLockReleaseRead(gpsPVRSRVData->hDeviceNodeListLock); - return NULL; + return psDevNode; } PVRSRV_DEVICE_NODE *PVRSRVGetDeviceInstanceByOSId(IMG_INT32 i32OSInstance) { PVRSRV_DEVICE_NODE *psDevNode; + OSWRLockAcquireRead(gpsPVRSRVData->hDeviceNodeListLock); for (psDevNode = gpsPVRSRVData->psDeviceNodeList; psDevNode != NULL; psDevNode = psDevNode->psNext) { if (i32OSInstance == psDevNode->sDevId.i32OsDeviceID) { - return psDevNode; + break; } } + OSWRLockReleaseRead(gpsPVRSRVData->hDeviceNodeListLock); - return NULL; + return psDevNode; +} + +/* Default function for querying the power state of the system */ +PVRSRV_SYS_POWER_STATE PVRSRVDefaultDomainPower(PVRSRV_DEVICE_NODE *psDevNode) +{ + return psDevNode->eCurrentSysPowerState; } /***************************************************************************** End of file (pvrsrv.c) diff --git a/drivers/gpu/drm/img-rogue/pvrsrv.h b/drivers/gpu/drm/img-rogue/pvrsrv.h index 7153dc20f..97454f5ad 100644 --- a/drivers/gpu/drm/img-rogue/pvrsrv.h +++ b/drivers/gpu/drm/img-rogue/pvrsrv.h @@ -122,19 +122,16 @@ typedef struct PVRSRV_DATA_TAG PVRSRV_DRIVER_MODE eDriverMode; /*!< Driver mode (i.e. native, host or guest) */ IMG_BOOL bForceApphintDriverMode; /*!< Indicate if driver mode is forced via apphint */ DRIVER_INFO sDriverInfo; - IMG_UINT32 ui32RegisteredDevices; IMG_UINT32 ui32DPFErrorCount; /*!< Number of Fatal/Error DPFs */ + POSWR_LOCK hDeviceNodeListLock; /*!< Read-Write lock to protect the list of devices */ PVRSRV_DEVICE_NODE *psDeviceNodeList; /*!< List head of device nodes */ + IMG_UINT32 ui32RegisteredDevices; PVRSRV_DEVICE_NODE *psHostMemDeviceNode; /*!< DeviceNode to be used for device independent host based memory allocations where the DevMem framework is to be used e.g. TL */ PVRSRV_SERVICES_STATE eServicesState; /*!< global driver state */ - HASH_TABLE *psProcessHandleBase_Table; /*!< Hash table with process handle bases */ - POS_LOCK hProcessHandleBase_Lock; /*!< Lock for the process handle base table */ - PVRSRV_HANDLE_BASE *psProcessHandleBaseBeingFreed; /*!< Pointer to process handle base currently being freed */ - IMG_HANDLE hGlobalEventObject; /*!< OS Global Event Object */ IMG_UINT32 ui32GEOConsecutiveTimeouts; /*!< OS Global Event Object Timeouts */ @@ -143,6 +140,7 @@ typedef struct PVRSRV_DATA_TAG POS_SPINLOCK hCleanupThreadWorkListLock; /*!< Lock protecting the cleanup thread work list */ DLLIST_NODE sCleanupThreadWorkList; /*!< List of work for the cleanup thread */ IMG_PID cleanupThreadPid; /*!< Cleanup thread process id */ + uintptr_t cleanupThreadTid; /*!< Cleanup thread id */ ATOMIC_T i32NumCleanupItemsQueued; /*!< Number of items in cleanup thread work list */ ATOMIC_T i32NumCleanupItemsNotCompleted; /*!< Number of items dropped from cleanup thread work list after retry limit reached */ @@ -230,35 +228,6 @@ PVRSRV_DATA *PVRSRVGetPVRSRVData(void); ((IMG_UINT32)((IMG_UINT32)(_expr)&(IMG_UINT)0x7FFFFFFF)==(IMG_UINT32)0x1) ? DRIVER_MODE_GUEST : \ ((IMG_UINT32)(_expr)&(IMG_UINT32)0x7FFFFFFF)) -/*! -****************************************************************************** - - @Function LMA memory management API - -******************************************************************************/ -#if defined(SUPPORT_GPUVIRT_VALIDATION) -PVRSRV_ERROR LMA_PhyContigPagesAllocGPV(PVRSRV_DEVICE_NODE *psDevNode, size_t uiSize, - PG_HANDLE *psMemHandle, IMG_DEV_PHYADDR *psDevPAddr, - IMG_UINT32 ui32OSid, IMG_PID uiPid); -#endif -PVRSRV_ERROR LMA_PhyContigPagesAlloc(PVRSRV_DEVICE_NODE *psDevNode, size_t uiSize, - PG_HANDLE *psMemHandle, IMG_DEV_PHYADDR *psDevPAddr, - IMG_PID uiPid); - -void LMA_PhyContigPagesFree(PVRSRV_DEVICE_NODE *psDevNode, PG_HANDLE *psMemHandle); - -PVRSRV_ERROR LMA_PhyContigPagesMap(PVRSRV_DEVICE_NODE *psDevNode, PG_HANDLE *psMemHandle, - size_t uiSize, IMG_DEV_PHYADDR *psDevPAddr, - void **pvPtr); - -void LMA_PhyContigPagesUnmap(PVRSRV_DEVICE_NODE *psDevNode, PG_HANDLE *psMemHandle, - void *pvPtr); - -PVRSRV_ERROR LMA_PhyContigPagesClean(PVRSRV_DEVICE_NODE *psDevNode, - PG_HANDLE *psMemHandle, - IMG_UINT32 uiOffset, - IMG_UINT32 uiLength); - typedef struct _PHYS_HEAP_ITERATOR_ PHYS_HEAP_ITERATOR; /*! @@ -561,4 +530,13 @@ PVRSRV_DEVICE_NODE* PVRSRVGetDeviceInstance(IMG_UINT32 ui32Instance); @Return PVRSRV_DEVICE_NODE* Return a device node, or NULL if not found. */ /**************************************************************************/ PVRSRV_DEVICE_NODE *PVRSRVGetDeviceInstanceByOSId(IMG_INT32 i32OSInstance); + +/*************************************************************************/ /*! +@Function PVRSRVDefaultDomainPower +@Description Returns psDevNode->eCurrentSysPowerState +@Input PVRSRV_DEVICE_NODE* Device node +@Return PVRSRV_SYS_POWER_STATE System power state tracked internally +*/ /**************************************************************************/ +PVRSRV_SYS_POWER_STATE PVRSRVDefaultDomainPower(PVRSRV_DEVICE_NODE *psDevNode); + #endif /* PVRSRV_H */ diff --git a/drivers/gpu/drm/img-rogue/pvrsrv_bridge_init.c b/drivers/gpu/drm/img-rogue/pvrsrv_bridge_init.c index da36e245b..2ce4ae0a8 100644 --- a/drivers/gpu/drm/img-rogue/pvrsrv_bridge_init.c +++ b/drivers/gpu/drm/img-rogue/pvrsrv_bridge_init.c @@ -47,97 +47,97 @@ CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. /* These will go when full bridge gen comes in */ #if defined(PDUMP) PVRSRV_ERROR InitPDUMPCTRLBridge(void); -PVRSRV_ERROR DeinitPDUMPCTRLBridge(void); +void DeinitPDUMPCTRLBridge(void); PVRSRV_ERROR InitPDUMPBridge(void); -PVRSRV_ERROR DeinitPDUMPBridge(void); +void DeinitPDUMPBridge(void); PVRSRV_ERROR InitRGXPDUMPBridge(void); -PVRSRV_ERROR DeinitRGXPDUMPBridge(void); +void DeinitRGXPDUMPBridge(void); #endif #if defined(SUPPORT_DISPLAY_CLASS) PVRSRV_ERROR InitDCBridge(void); -PVRSRV_ERROR DeinitDCBridge(void); +void DeinitDCBridge(void); #endif PVRSRV_ERROR InitMMBridge(void); -PVRSRV_ERROR DeinitMMBridge(void); +void DeinitMMBridge(void); #if !defined(EXCLUDE_CMM_BRIDGE) PVRSRV_ERROR InitCMMBridge(void); -PVRSRV_ERROR DeinitCMMBridge(void); +void DeinitCMMBridge(void); #endif PVRSRV_ERROR InitPDUMPMMBridge(void); -PVRSRV_ERROR DeinitPDUMPMMBridge(void); +void DeinitPDUMPMMBridge(void); PVRSRV_ERROR InitSRVCOREBridge(void); -PVRSRV_ERROR DeinitSRVCOREBridge(void); +void DeinitSRVCOREBridge(void); PVRSRV_ERROR InitSYNCBridge(void); -PVRSRV_ERROR DeinitSYNCBridge(void); +void DeinitSYNCBridge(void); #if defined(SUPPORT_DMA_TRANSFER) PVRSRV_ERROR InitDMABridge(void); -PVRSRV_ERROR DeinitDMABridge(void); +void DeinitDMABridge(void); #endif #if defined(SUPPORT_RGX) PVRSRV_ERROR InitRGXTA3DBridge(void); -PVRSRV_ERROR DeinitRGXTA3DBridge(void); +void DeinitRGXTA3DBridge(void); #if defined(SUPPORT_RGXTQ_BRIDGE) PVRSRV_ERROR InitRGXTQBridge(void); -PVRSRV_ERROR DeinitRGXTQBridge(void); +void DeinitRGXTQBridge(void); #endif /* defined(SUPPORT_RGXTQ_BRIDGE) */ #if defined(SUPPORT_USC_BREAKPOINT) PVRSRV_ERROR InitRGXBREAKPOINTBridge(void); -PVRSRV_ERROR DeinitRGXBREAKPOINTBridge(void); +void DeinitRGXBREAKPOINTBridge(void); #endif PVRSRV_ERROR InitRGXFWDBGBridge(void); -PVRSRV_ERROR DeinitRGXFWDBGBridge(void); +void DeinitRGXFWDBGBridge(void); PVRSRV_ERROR InitRGXHWPERFBridge(void); -PVRSRV_ERROR DeinitRGXHWPERFBridge(void); +void DeinitRGXHWPERFBridge(void); #if !defined(EXCLUDE_RGXREGCONFIG_BRIDGE) PVRSRV_ERROR InitRGXREGCONFIGBridge(void); -PVRSRV_ERROR DeinitRGXREGCONFIGBridge(void); +void DeinitRGXREGCONFIGBridge(void); #endif PVRSRV_ERROR InitRGXKICKSYNCBridge(void); -PVRSRV_ERROR DeinitRGXKICKSYNCBridge(void); +void DeinitRGXKICKSYNCBridge(void); #endif /* SUPPORT_RGX */ PVRSRV_ERROR InitCACHEBridge(void); -PVRSRV_ERROR DeinitCACHEBridge(void); +void DeinitCACHEBridge(void); #if defined(SUPPORT_SECURE_EXPORT) PVRSRV_ERROR InitSMMBridge(void); -PVRSRV_ERROR DeinitSMMBridge(void); +void DeinitSMMBridge(void); #endif #if !defined(EXCLUDE_HTBUFFER_BRIDGE) PVRSRV_ERROR InitHTBUFFERBridge(void); -PVRSRV_ERROR DeinitHTBUFFERBridge(void); +void DeinitHTBUFFERBridge(void); #endif PVRSRV_ERROR InitPVRTLBridge(void); -PVRSRV_ERROR DeinitPVRTLBridge(void); +void DeinitPVRTLBridge(void); #if defined(PVRSRV_ENABLE_GPU_MEMORY_INFO) PVRSRV_ERROR InitRIBridge(void); -PVRSRV_ERROR DeinitRIBridge(void); +void DeinitRIBridge(void); #endif PVRSRV_ERROR InitDEVICEMEMHISTORYBridge(void); -PVRSRV_ERROR DeinitDEVICEMEMHISTORYBridge(void); +void DeinitDEVICEMEMHISTORYBridge(void); #if defined(SUPPORT_VALIDATION_BRIDGE) PVRSRV_ERROR InitVALIDATIONBridge(void); -PVRSRV_ERROR DeinitVALIDATIONBridge(void); +void DeinitVALIDATIONBridge(void); #endif #if defined(PVR_TESTING_UTILS) PVRSRV_ERROR InitTUTILSBridge(void); -PVRSRV_ERROR DeinitTUTILSBridge(void); +void DeinitTUTILSBridge(void); #endif PVRSRV_ERROR InitSYNCTRACKINGBridge(void); -PVRSRV_ERROR DeinitSYNCTRACKINGBridge(void); +void DeinitSYNCTRACKINGBridge(void); #if defined(SUPPORT_WRAP_EXTMEM) PVRSRV_ERROR InitMMEXTMEMBridge(void); -PVRSRV_ERROR DeinitMMEXTMEMBridge(void); +void DeinitMMEXTMEMBridge(void); #endif #if defined(SUPPORT_FALLBACK_FENCE_SYNC) PVRSRV_ERROR InitSYNCFALLBACKBridge(void); -PVRSRV_ERROR DeinitSYNCFALLBACKBridge(void); +void DeinitSYNCFALLBACKBridge(void); #endif PVRSRV_ERROR InitRGXTIMERQUERYBridge(void); -PVRSRV_ERROR DeinitRGXTIMERQUERYBridge(void); +void DeinitRGXTIMERQUERYBridge(void); #if defined(SUPPORT_DI_BRG_IMPL) PVRSRV_ERROR InitDIBridge(void); -PVRSRV_ERROR DeinitDIBridge(void); +void DeinitDIBridge(void); #endif PVRSRV_ERROR @@ -281,141 +281,105 @@ ServerBridgeInit(void) return eError; } -PVRSRV_ERROR -ServerBridgeDeInit(void) +void ServerBridgeDeInit(void) { - PVRSRV_ERROR eError; - - eError = OSPlatformBridgeDeInit(); - PVR_LOG_IF_ERROR(eError, "OSPlatformBridgeDeInit"); + OSPlatformBridgeDeInit(); #if defined(SUPPORT_DI_BRG_IMPL) - eError = DeinitDIBridge(); - PVR_LOG_IF_ERROR(eError, "DeinitDIBridge"); + DeinitDIBridge(); #endif #if defined(SUPPORT_FALLBACK_FENCE_SYNC) - eError = DeinitSYNCFALLBACKBridge(); - PVR_LOG_RETURN_IF_ERROR(eError, "DeinitSYNCFALLBACKBridge"); + DeinitSYNCFALLBACKBridge(); #endif #if defined(SUPPORT_WRAP_EXTMEM) - eError = DeinitMMEXTMEMBridge(); - PVR_LOG_RETURN_IF_ERROR(eError, "DeinitMMEXTMEMBridge"); + DeinitMMEXTMEMBridge(); #endif - eError = DeinitSRVCOREBridge(); - PVR_LOG_RETURN_IF_ERROR(eError, "DeinitSRVCOREBridge"); + DeinitSRVCOREBridge(); - eError = DeinitSYNCBridge(); - PVR_LOG_RETURN_IF_ERROR(eError, "DeinitSYNCBridge"); + DeinitSYNCBridge(); #if defined(PDUMP) - eError = DeinitPDUMPCTRLBridge(); - PVR_LOG_RETURN_IF_ERROR(eError, "DeinitPDUMPCTRLBridge"); + DeinitPDUMPCTRLBridge(); #endif - eError = DeinitMMBridge(); - PVR_LOG_RETURN_IF_ERROR(eError, "DeinitMMBridge"); + DeinitMMBridge(); #if !defined(EXCLUDE_CMM_BRIDGE) - eError = DeinitCMMBridge(); - PVR_LOG_RETURN_IF_ERROR(eError, "DeinitCMMBridge"); + DeinitCMMBridge(); #endif #if defined(PDUMP) - eError = DeinitPDUMPMMBridge(); - PVR_LOG_RETURN_IF_ERROR(eError, "DeinitPDUMPMMBridge"); + DeinitPDUMPMMBridge(); - eError = DeinitPDUMPBridge(); - PVR_LOG_RETURN_IF_ERROR(eError, "DeinitPDUMPBridge"); + DeinitPDUMPBridge(); #endif #if defined(PVR_TESTING_UTILS) - eError = DeinitTUTILSBridge(); - PVR_LOG_RETURN_IF_ERROR(eError, "DeinitTUTILSBridge"); + DeinitTUTILSBridge(); #endif #if defined(SUPPORT_DISPLAY_CLASS) - eError = DeinitDCBridge(); - PVR_LOG_RETURN_IF_ERROR(eError, "DeinitDCBridge"); + DeinitDCBridge(); #endif - eError = DeinitCACHEBridge(); - PVR_LOG_RETURN_IF_ERROR(eError, "DeinitCACHEBridge"); + DeinitCACHEBridge(); #if defined(SUPPORT_SECURE_EXPORT) - eError = DeinitSMMBridge(); - PVR_LOG_RETURN_IF_ERROR(eError, "DeinitSMMBridge"); + DeinitSMMBridge(); #endif #if !defined(EXCLUDE_HTBUFFER_BRIDGE) - eError = DeinitHTBUFFERBridge(); - PVR_LOG_RETURN_IF_ERROR(eError, "DeinitHTBUFFERBridge"); + DeinitHTBUFFERBridge(); #endif - eError = DeinitPVRTLBridge(); - PVR_LOG_RETURN_IF_ERROR(eError, "DeinitPVRTLBridge"); + DeinitPVRTLBridge(); #if defined(SUPPORT_VALIDATION_BRIDGE) - eError = DeinitVALIDATIONBridge(); - PVR_LOG_RETURN_IF_ERROR(eError, "DeinitVALIDATIONBridge"); + DeinitVALIDATIONBridge(); #endif #if defined(PVRSRV_ENABLE_GPU_MEMORY_INFO) - eError = DeinitRIBridge(); - PVR_LOG_RETURN_IF_ERROR(eError, "DeinitRIBridge"); + DeinitRIBridge(); #endif - eError = DeinitDEVICEMEMHISTORYBridge(); - PVR_LOG_RETURN_IF_ERROR(eError, "DeinitDEVICEMEMHISTORYBridge"); + DeinitDEVICEMEMHISTORYBridge(); - eError = DeinitSYNCTRACKINGBridge(); - PVR_LOG_RETURN_IF_ERROR(eError, "DeinitSYNCTRACKINGBridge"); + DeinitSYNCTRACKINGBridge(); #if defined(SUPPORT_DMA_TRANSFER) - eError = DeinitDMABridge(); - PVR_LOG_RETURN_IF_ERROR(eError, "DeinitDMABridge"); + DeinitDMABridge(); #endif #if defined(SUPPORT_RGX) #if defined(SUPPORT_RGXTQ_BRIDGE) - eError = DeinitRGXTQBridge(); - PVR_LOG_RETURN_IF_ERROR(eError, "DeinitRGXTQBridge"); + DeinitRGXTQBridge(); #endif /* defined(SUPPORT_RGXTQ_BRIDGE) */ - eError = DeinitRGXTA3DBridge(); - PVR_LOG_RETURN_IF_ERROR(eError, "DeinitRGXTA3DBridge"); + DeinitRGXTA3DBridge(); #if defined(SUPPORT_USC_BREAKPOINT) - eError = DeinitRGXBREAKPOINTBridge(); - PVR_LOG_RETURN_IF_ERROR(eError, "DeinitRGXBREAKPOINTBridge"); + DeinitRGXBREAKPOINTBridge(); #endif - eError = DeinitRGXFWDBGBridge(); - PVR_LOG_RETURN_IF_ERROR(eError, "DeinitRGXFWDBGBridge"); + DeinitRGXFWDBGBridge(); #if defined(PDUMP) - eError = DeinitRGXPDUMPBridge(); - PVR_LOG_RETURN_IF_ERROR(eError, "DeinitRGXPDUMPBridge"); + DeinitRGXPDUMPBridge(); #endif - eError = DeinitRGXHWPERFBridge(); - PVR_LOG_RETURN_IF_ERROR(eError, "DeinitRGXHWPERFBridge"); + DeinitRGXHWPERFBridge(); #if !defined(EXCLUDE_RGXREGCONFIG_BRIDGE) - eError = DeinitRGXREGCONFIGBridge(); - PVR_LOG_RETURN_IF_ERROR(eError, "DeinitRGXREGCONFIGBridge"); + DeinitRGXREGCONFIGBridge(); #endif - eError = DeinitRGXKICKSYNCBridge(); - PVR_LOG_RETURN_IF_ERROR(eError, "DeinitRGXKICKSYNCBridge"); + DeinitRGXKICKSYNCBridge(); - eError = DeinitRGXTIMERQUERYBridge(); - PVR_LOG_RETURN_IF_ERROR(eError, "DeinitRGXTIMERQUERYBridge"); + DeinitRGXTIMERQUERYBridge(); #endif /* SUPPORT_RGX */ - - return eError; } diff --git a/drivers/gpu/drm/img-rogue/pvrsrv_bridge_init.h b/drivers/gpu/drm/img-rogue/pvrsrv_bridge_init.h index 73a07c3ce..750c9816c 100644 --- a/drivers/gpu/drm/img-rogue/pvrsrv_bridge_init.h +++ b/drivers/gpu/drm/img-rogue/pvrsrv_bridge_init.h @@ -48,6 +48,6 @@ CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. #include "pvrsrv_error.h" PVRSRV_ERROR ServerBridgeInit(void); -PVRSRV_ERROR ServerBridgeDeInit(void); +void ServerBridgeDeInit(void); #endif /* PVRSRV_BRIDGE_INIT_H */ diff --git a/drivers/gpu/drm/img-rogue/pvrsrv_cleanup.h b/drivers/gpu/drm/img-rogue/pvrsrv_cleanup.h index 3d1b1c91a..9eb454f5e 100644 --- a/drivers/gpu/drm/img-rogue/pvrsrv_cleanup.h +++ b/drivers/gpu/drm/img-rogue/pvrsrv_cleanup.h @@ -156,4 +156,22 @@ typedef struct _PVRSRV_CLEANUP_THREAD_WORK_ */ /***************************************************************************/ void PVRSRVCleanupThreadAddWork(PVRSRV_CLEANUP_THREAD_WORK *psData); +/**************************************************************************/ /*! +@Function PVRSRVCleanupThreadGetPid + +@Description Returns Cleanup Thread's PID. + +@Return PID of the Cleanup Thread +*/ /***************************************************************************/ +IMG_PID PVRSRVCleanupThreadGetPid(void); + +/**************************************************************************/ /*! +@Function PVRSRVCleanupThreadGetTid + +@Description Returns Cleanup Thread's TID. + +@Return TID of the Cleanup Thread +*/ /***************************************************************************/ +uintptr_t PVRSRVCleanupThreadGetTid(void); + #endif /* PVRSRV_CLEANUP_H */ diff --git a/drivers/gpu/drm/img-rogue/pvrsrv_device.h b/drivers/gpu/drm/img-rogue/pvrsrv_device.h index 80df86d46..b97e015cb 100644 --- a/drivers/gpu/drm/img-rogue/pvrsrv_device.h +++ b/drivers/gpu/drm/img-rogue/pvrsrv_device.h @@ -113,6 +113,29 @@ typedef PVRSRV_ERROR PVRSRV_SYS_POWER_STATE eCurrentPowerState, PVRSRV_POWER_FLAGS ePwrFlags); +/*************************************************************************/ /*! +@Brief Callback function type PFN_SYS_GET_POWER + +@Description This function queries the SoC power registers to determine + if the power domain on which the GPU resides is powered on. + + Implementation of this callback is optional - where it is not provided, + the driver will assume the domain power state depending on driver type: + regular drivers assume it is unpowered at startup, while drivers with + AutoVz support expect the GPU domain to be powered on initially. The power + state will be then tracked internally according to the pfnPrePowerState + and pfnPostPowerState calls using a fallback function. + +@Input psDevNode Pointer to node struct of the + device being initialised + +@Return PVRSRV_SYS_POWER_STATE_ON if the respective device's hardware + domain is powered on + PVRSRV_SYS_POWER_STATE_OFF if the domain is powered off +*/ /**************************************************************************/ +typedef PVRSRV_SYS_POWER_STATE +(*PFN_SYS_GET_POWER)(struct _PVRSRV_DEVICE_NODE_ *psDevNode); + typedef void (*PFN_SYS_DEV_INTERRUPT_HANDLED)(PVRSRV_DEVICE_CONFIG *psDevConfig); @@ -272,6 +295,7 @@ struct _PVRSRV_DEVICE_CONFIG_ */ PFN_SYS_PRE_POWER pfnPrePowerState; PFN_SYS_POST_POWER pfnPostPowerState; + PFN_SYS_GET_POWER pfnGpuDomainPower; /*! Callback to obtain the clock frequency from the device (optional). */ PFN_SYS_DEV_CLK_FREQ_GET pfnClockFreqGet; diff --git a/drivers/gpu/drm/img-rogue/pvrsrv_errors.h b/drivers/gpu/drm/img-rogue/pvrsrv_errors.h index d571d6279..59b9cfe84 100644 --- a/drivers/gpu/drm/img-rogue/pvrsrv_errors.h +++ b/drivers/gpu/drm/img-rogue/pvrsrv_errors.h @@ -406,3 +406,5 @@ PVRE(PVRSRV_ERROR_TOO_MANY_SYNCS) PVRE(PVRSRV_ERROR_ION_NO_CLIENT) PVRE(PVRSRV_ERROR_ION_FAILED_TO_ALLOC) PVRE(PVRSRV_ERROR_PDUMP_CAPTURE_BOUND_TO_ANOTHER_DEVICE) +PVRE(PVRSRV_ERROR_REFCOUNT_OVERFLOW) +PVRE(PVRSRV_ERROR_OUT_OF_RANGE) diff --git a/drivers/gpu/drm/img-rogue/pvrsrv_memalloc_physheap.h b/drivers/gpu/drm/img-rogue/pvrsrv_memalloc_physheap.h index f002a1af3..1072ba857 100644 --- a/drivers/gpu/drm/img-rogue/pvrsrv_memalloc_physheap.h +++ b/drivers/gpu/drm/img-rogue/pvrsrv_memalloc_physheap.h @@ -56,41 +56,115 @@ CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. * * NOTE: Enum order important, table in physheap.c must change if order changed. */ -typedef enum -{ - /* Services client accessible heaps */ - PVRSRV_PHYS_HEAP_DEFAULT = 0, /* default phys heap for device memory allocations */ - PVRSRV_PHYS_HEAP_GPU_LOCAL = 1, /* used for buffers with more GPU access than CPU */ - PVRSRV_PHYS_HEAP_CPU_LOCAL = 2, /* used for buffers with more CPU access than GPU */ - PVRSRV_PHYS_HEAP_GPU_PRIVATE = 3, /* used for buffers that only required GPU read/write access, not visible to the CPU. */ +typedef IMG_UINT32 PVRSRV_PHYS_HEAP; +/* Services client accessible heaps */ +#define PVRSRV_PHYS_HEAP_DEFAULT 0U /* default phys heap for device memory allocations */ +#define PVRSRV_PHYS_HEAP_GPU_LOCAL 1U /* used for buffers with more GPU access than CPU */ +#define PVRSRV_PHYS_HEAP_CPU_LOCAL 2U /* used for buffers with more CPU access than GPU */ +#define PVRSRV_PHYS_HEAP_GPU_PRIVATE 3U /* used for buffers that only required GPU read/write access, not visible to the CPU. */ - /* Services internal heaps */ - PVRSRV_PHYS_HEAP_FW_MAIN = 4, /* runtime data, e.g. CCBs, sync objects */ - PVRSRV_PHYS_HEAP_EXTERNAL = 5, /* used by some PMR import/export factories where the physical memory heap is not managed by the pvrsrv driver */ - PVRSRV_PHYS_HEAP_GPU_COHERENT = 6, /* used for a cache coherent region */ - PVRSRV_PHYS_HEAP_GPU_SECURE = 7, /* used by security validation */ - PVRSRV_PHYS_HEAP_FW_CONFIG = 8, /* subheap of FW_MAIN, configuration data for FW init */ - PVRSRV_PHYS_HEAP_FW_CODE = 9, /* used by security validation or dedicated fw */ - PVRSRV_PHYS_HEAP_FW_PRIV_DATA = 10, /* internal FW data (like the stack, FW control data structures, etc.) */ - PVRSRV_PHYS_HEAP_FW_PREMAP0 = 11, /* Host OS premap fw heap */ - PVRSRV_PHYS_HEAP_FW_PREMAP1 = 12, /* Guest OS 1 premap fw heap */ - PVRSRV_PHYS_HEAP_FW_PREMAP2 = 13, /* Guest OS 2 premap fw heap */ - PVRSRV_PHYS_HEAP_FW_PREMAP3 = 14, /* Guest OS 3 premap fw heap */ - PVRSRV_PHYS_HEAP_FW_PREMAP4 = 15, /* Guest OS 4 premap fw heap */ - PVRSRV_PHYS_HEAP_FW_PREMAP5 = 16, /* Guest OS 5 premap fw heap */ - PVRSRV_PHYS_HEAP_FW_PREMAP6 = 17, /* Guest OS 6 premap fw heap */ - PVRSRV_PHYS_HEAP_FW_PREMAP7 = 18, /* Guest OS 7 premap fw heap */ - PVRSRV_PHYS_HEAP_LAST -} PVRSRV_PHYS_HEAP; +#define HEAPSTR(x) #x +static inline const IMG_CHAR *PVRSRVGetClientPhysHeapName(PVRSRV_PHYS_HEAP ePhysHeapID) +{ + switch (ePhysHeapID) + { + case PVRSRV_PHYS_HEAP_DEFAULT: + return HEAPSTR(PVRSRV_PHYS_HEAP_DEFAULT); + case PVRSRV_PHYS_HEAP_GPU_LOCAL: + return HEAPSTR(PVRSRV_PHYS_HEAP_GPU_LOCAL); + case PVRSRV_PHYS_HEAP_CPU_LOCAL: + return HEAPSTR(PVRSRV_PHYS_HEAP_CPU_LOCAL); + case PVRSRV_PHYS_HEAP_GPU_PRIVATE: + return HEAPSTR(PVRSRV_PHYS_HEAP_GPU_PRIVATE); + default: + return "Unknown Heap"; + } +} + +/* Services internal heaps */ +#define PVRSRV_PHYS_HEAP_FW_MAIN 4U /* runtime data, e.g. CCBs, sync objects */ +#define PVRSRV_PHYS_HEAP_EXTERNAL 5U /* used by some PMR import/export factories where the physical memory heap is not managed by the pvrsrv driver */ +#define PVRSRV_PHYS_HEAP_GPU_COHERENT 6U /* used for a cache coherent region */ +#define PVRSRV_PHYS_HEAP_GPU_SECURE 7U /* used by security validation */ +#define PVRSRV_PHYS_HEAP_FW_CONFIG 8U /* subheap of FW_MAIN, configuration data for FW init */ +#define PVRSRV_PHYS_HEAP_FW_CODE 9U /* used by security validation or dedicated fw */ +#define PVRSRV_PHYS_HEAP_FW_PRIV_DATA 10U /* internal FW data (like the stack, FW control data structures, etc.) */ +#define PVRSRV_PHYS_HEAP_FW_PREMAP0 11U /* Host OS premap fw heap */ +#define PVRSRV_PHYS_HEAP_FW_PREMAP1 12U /* Guest OS 1 premap fw heap */ +#define PVRSRV_PHYS_HEAP_FW_PREMAP2 13U /* Guest OS 2 premap fw heap */ +#define PVRSRV_PHYS_HEAP_FW_PREMAP3 14U /* Guest OS 3 premap fw heap */ +#define PVRSRV_PHYS_HEAP_FW_PREMAP4 15U /* Guest OS 4 premap fw heap */ +#define PVRSRV_PHYS_HEAP_FW_PREMAP5 16U /* Guest OS 5 premap fw heap */ +#define PVRSRV_PHYS_HEAP_FW_PREMAP6 17U /* Guest OS 6 premap fw heap */ +#define PVRSRV_PHYS_HEAP_FW_PREMAP7 18U /* Guest OS 7 premap fw heap */ +#define PVRSRV_PHYS_HEAP_LAST 19U static_assert(PVRSRV_PHYS_HEAP_LAST <= (0x1FU + 1U), "Ensure enum fits in memalloc flags bitfield."); -typedef struct _PHYS_HEAP_MEM_STATS_ +/*! Type conveys the class of physical heap to instantiate within Services + * for the physical pool of memory. */ +typedef enum _PHYS_HEAP_TYPE_ +{ + PHYS_HEAP_TYPE_UNKNOWN = 0, /*!< Not a valid value for any config */ + PHYS_HEAP_TYPE_UMA, /*!< Heap represents OS managed physical memory heap + i.e. system RAM. Unified Memory Architecture + physmem_osmem PMR factory */ + PHYS_HEAP_TYPE_LMA, /*!< Heap represents physical memory pool managed by + Services i.e. carve out from system RAM or local + card memory. Local Memory Architecture + physmem_lma PMR factory */ +#if defined(__KERNEL__) + PHYS_HEAP_TYPE_DMA, /*!< Heap represents a physical memory pool managed by + Services, alias of LMA and is only used on + VZ non-native system configurations for + a heap used for PHYS_HEAP_USAGE_FW_MAIN tagged + buffers */ +#if defined(SUPPORT_WRAP_EXTMEMOBJECT) + PHYS_HEAP_TYPE_WRAP, /*!< Heap used to group UM buffers given + to Services. Integrity OS port only. */ +#endif +#endif +} PHYS_HEAP_TYPE; + +/* Defines used when interpreting the ui32PhysHeapFlags in PHYS_HEAP_MEM_STATS + 0x000000000000dttt + d = is this the default heap? (1=yes, 0=no) + ttt = heap type (000 = PHYS_HEAP_TYPE_UNKNOWN, + 001 = PHYS_HEAP_TYPE_UMA, + 010 = PHYS_HEAP_TYPE_LMA, + 011 = PHYS_HEAP_TYPE_DMA) +*/ +#define PVRSRV_PHYS_HEAP_FLAGS_TYPE_MASK (0x7U << 0) +#define PVRSRV_PHYS_HEAP_FLAGS_IS_DEFAULT (0x1U << 7) + +typedef struct PHYS_HEAP_MEM_STATS_TAG { - IMG_UINT64 ePhysHeapID; IMG_UINT64 ui64TotalSize; IMG_UINT64 ui64FreeSize; + IMG_UINT32 ui32PhysHeapFlags; }PHYS_HEAP_MEM_STATS, *PHYS_HEAP_MEM_STATS_PTR; +typedef struct PHYS_HEAP_MEM_STATS_PKD_TAG +{ + IMG_UINT64 ui64TotalSize; + IMG_UINT64 ui64FreeSize; + IMG_UINT32 ui32PhysHeapFlags; + IMG_UINT32 ui32Dummy; +}PHYS_HEAP_MEM_STATS_PKD, *PHYS_HEAP_MEM_STATS_PKD_PTR; + +static inline const IMG_CHAR *PVRSRVGetClientPhysHeapTypeName(PHYS_HEAP_TYPE ePhysHeapType) +{ + switch (ePhysHeapType) + { + case PHYS_HEAP_TYPE_UMA: + return HEAPSTR(PHYS_HEAP_TYPE_UMA); + case PHYS_HEAP_TYPE_LMA: + return HEAPSTR(PHYS_HEAP_TYPE_LMA); + default: + return "Unknown Heap Type"; + } +} +#undef HEAPSTR + #endif /* PVRSRV_MEMALLOC_PHYSHEAP_H */ diff --git a/drivers/gpu/drm/img-rogue/pvrsrv_memallocflags.h b/drivers/gpu/drm/img-rogue/pvrsrv_memallocflags.h index 28a4c018f..3b87dbf49 100644 --- a/drivers/gpu/drm/img-rogue/pvrsrv_memallocflags.h +++ b/drivers/gpu/drm/img-rogue/pvrsrv_memallocflags.h @@ -58,7 +58,7 @@ CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. typedef IMG_UINT64 PVRSRV_MEMALLOCFLAGS_T; #define PVRSRV_MEMALLOCFLAGS_FMTSPEC IMG_UINT64_FMTSPECx -#if defined(__KERNEL__) || defined(SERVICES_SC) +#if defined(__KERNEL__) #include "pvrsrv_memallocflags_internal.h" #endif /* __KERNEL__ */ @@ -538,7 +538,7 @@ typedef IMG_UINT64 PVRSRV_MEMALLOCFLAGS_T; /*! Indicates the particular memory that's being allocated is sparse and the sparse regions should not be backed by dummy page -*/ + */ #define PVRSRV_MEMALLOCFLAG_SPARSE_NO_DUMMY_BACKING (1ULL << 18) /*! @@ -549,9 +549,12 @@ typedef IMG_UINT64 PVRSRV_MEMALLOCFLAGS_T; #define PVRSRV_IS_SPARSE_DUMMY_BACKING_REQUIRED(uiFlags) (((uiFlags) & PVRSRV_MEMALLOCFLAG_SPARSE_NO_DUMMY_BACKING) == 0U) /*! - Services is going to clean the cache for the allocated memory. - For performance reasons avoid usage if allocation is written to by the - CPU anyway before the next GPU kick. + Used to force Services to carry out at least one CPU cache invalidate on a + CPU cached buffer during allocation of the memory. Applicable to incoherent + systems, it must be used for buffers which are CPU cached and which will not + be 100% written to by the CPU before the GPU accesses it. For performance + reasons, avoid usage if the whole buffer that is allocated is written to by + the CPU anyway before the next GPU kick, or if the system is coherent. */ #define PVRSRV_MEMALLOCFLAG_CPU_CACHE_CLEAN (1ULL<<19) @@ -570,7 +573,7 @@ typedef IMG_UINT64 PVRSRV_MEMALLOCFLAGS_T; by zero page at the time of mapping. The zero backed page is always with read only attribute irrespective of its original attributes. -*/ + */ #define PVRSRV_MEMALLOCFLAG_SPARSE_ZERO_BACKING (1ULL << 20) #define PVRSRV_IS_SPARSE_ZERO_BACKING_REQUIRED(uiFlags) (((uiFlags) & \ PVRSRV_MEMALLOCFLAG_SPARSE_ZERO_BACKING) == PVRSRV_MEMALLOCFLAG_SPARSE_ZERO_BACKING) @@ -650,8 +653,10 @@ typedef IMG_UINT64 PVRSRV_MEMALLOCFLAGS_T; */ #define PVRSRV_CHECK_POISON_ON_ALLOC(uiFlags) (((uiFlags) & PVRSRV_MEMALLOCFLAG_POISON_ON_ALLOC) != 0U) +#if defined(DEBUG) || defined(SERVICES_SC) /*! - Causes memory to be trashed when freed, as a lazy man's security measure. + Causes memory to be trashed when freed, used when debugging only, not to be used + as a security measure. */ #define PVRSRV_MEMALLOCFLAG_POISON_ON_FREE (1ULL<<29) @@ -661,6 +666,7 @@ typedef IMG_UINT64 PVRSRV_MEMALLOCFLAGS_T; @Return True if the flag is set, false otherwise */ #define PVRSRV_CHECK_POISON_ON_FREE(uiFlags) (((uiFlags) & PVRSRV_MEMALLOCFLAG_POISON_ON_FREE) != 0U) +#endif /* DEBUG */ /*! Avoid address alignment to a CPU or GPU cache line size. @@ -822,20 +828,27 @@ typedef IMG_UINT64 PVRSRV_MEMALLOCFLAGS_T; * Trusted device mask -- Flags in the mask are allowed for trusted device * because the driver cannot access the memory */ +#if defined(DEBUG) || defined(SERVICES_SC) #define PVRSRV_MEMALLOCFLAGS_TDFWMASK ~(PVRSRV_MEMALLOCFLAG_KERNEL_CPU_MAPPABLE | \ PVRSRV_MEMALLOCFLAG_ZERO_ON_ALLOC | \ PVRSRV_MEMALLOCFLAG_POISON_ON_ALLOC | \ - PVRSRV_MEMALLOCFLAG_POISON_ON_FREE | \ + PVRSRV_MEMALLOCFLAG_POISON_ON_FREE | \ PVRSRV_MEMALLOCFLAGS_CPU_MMUFLAGSMASK | \ PVRSRV_MEMALLOCFLAG_SPARSE_NO_DUMMY_BACKING) - +#else +#define PVRSRV_MEMALLOCFLAGS_TDFWMASK ~(PVRSRV_MEMALLOCFLAG_KERNEL_CPU_MAPPABLE | \ + PVRSRV_MEMALLOCFLAG_ZERO_ON_ALLOC | \ + PVRSRV_MEMALLOCFLAG_POISON_ON_ALLOC | \ + PVRSRV_MEMALLOCFLAGS_CPU_MMUFLAGSMASK | \ + PVRSRV_MEMALLOCFLAG_SPARSE_NO_DUMMY_BACKING) +#endif /*! PMR flags mask -- for internal services use only. This is the set of flags that will be passed down and stored with the PMR, this also includes the MMU flags which the PMR has to pass down to mm_common.c at PMRMap time. */ - +#if defined(DEBUG) || defined(SERVICES_SC) #define PVRSRV_MEMALLOCFLAGS_PMRFLAGSMASK (PVRSRV_MEMALLOCFLAG_DEVICE_FLAGS_MASK | \ PVRSRV_MEMALLOCFLAG_CPU_CACHE_CLEAN | \ PVRSRV_MEMALLOCFLAG_KERNEL_CPU_MAPPABLE | \ @@ -848,8 +861,23 @@ typedef IMG_UINT64 PVRSRV_MEMALLOCFLAGS_T; PVRSRV_MEMALLOCFLAG_NO_OSPAGES_ON_ALLOC | \ PVRSRV_MEMALLOCFLAG_SPARSE_NO_DUMMY_BACKING | \ PVRSRV_MEMALLOCFLAG_SPARSE_ZERO_BACKING | \ - PVRSRV_MEMALLOCFLAG_VAL_SHARED_BUFFER | \ + PVRSRV_MEMALLOCFLAG_VAL_SHARED_BUFFER | \ PVRSRV_PHYS_HEAP_HINT_MASK) +#else +#define PVRSRV_MEMALLOCFLAGS_PMRFLAGSMASK (PVRSRV_MEMALLOCFLAG_DEVICE_FLAGS_MASK | \ + PVRSRV_MEMALLOCFLAG_CPU_CACHE_CLEAN | \ + PVRSRV_MEMALLOCFLAG_KERNEL_CPU_MAPPABLE | \ + PVRSRV_MEMALLOCFLAG_ZERO_ON_ALLOC | \ + PVRSRV_MEMALLOCFLAG_SVM_ALLOC | \ + PVRSRV_MEMALLOCFLAG_POISON_ON_ALLOC | \ + PVRSRV_MEMALLOCFLAGS_GPU_MMUFLAGSMASK | \ + PVRSRV_MEMALLOCFLAGS_CPU_MMUFLAGSMASK | \ + PVRSRV_MEMALLOCFLAG_NO_OSPAGES_ON_ALLOC | \ + PVRSRV_MEMALLOCFLAG_SPARSE_NO_DUMMY_BACKING | \ + PVRSRV_MEMALLOCFLAG_SPARSE_ZERO_BACKING | \ + PVRSRV_MEMALLOCFLAG_VAL_SHARED_BUFFER | \ + PVRSRV_PHYS_HEAP_HINT_MASK) +#endif /*! * CPU mappable mask -- Any flag set in the mask requires memory to be CPU mappable @@ -874,11 +902,18 @@ typedef IMG_UINT64 PVRSRV_MEMALLOCFLAGS_T; memory might be reused. */ +#if defined(DEBUG) || defined(SERVICES_SC) +#define PVRSRV_MEMALLOCFLAGS_RA_DIFFERENTIATION_MASK (PVRSRV_MEMALLOCFLAGS_PMRFLAGSMASK \ + & \ + ~(PVRSRV_MEMALLOCFLAG_ZERO_ON_ALLOC | \ + PVRSRV_MEMALLOCFLAG_POISON_ON_ALLOC | \ + PVRSRV_MEMALLOCFLAG_POISON_ON_FREE)) +#else #define PVRSRV_MEMALLOCFLAGS_RA_DIFFERENTIATION_MASK (PVRSRV_MEMALLOCFLAGS_PMRFLAGSMASK \ & \ ~(PVRSRV_MEMALLOCFLAG_ZERO_ON_ALLOC | \ PVRSRV_MEMALLOCFLAG_POISON_ON_ALLOC)) - +#endif /*! Flags that affect _allocation_ */ @@ -903,6 +938,7 @@ typedef IMG_UINT64 PVRSRV_MEMALLOCFLAGS_T; /*! Flags that affect _physical allocations_ in the DevMemX API */ +#if defined(DEBUG) || defined(SERVICES_SC) #define PVRSRV_MEMALLOCFLAGS_DEVMEMX_PHYSICAL_MASK (PVRSRV_MEMALLOCFLAGS_CPU_MMUFLAGSMASK | \ PVRSRV_MEMALLOCFLAG_GPU_CACHE_MODE_MASK | \ PVRSRV_MEMALLOCFLAG_CPU_READ_PERMITTED | \ @@ -912,6 +948,16 @@ typedef IMG_UINT64 PVRSRV_MEMALLOCFLAGS_T; PVRSRV_MEMALLOCFLAG_POISON_ON_ALLOC | \ PVRSRV_MEMALLOCFLAG_POISON_ON_FREE | \ PVRSRV_PHYS_HEAP_HINT_MASK) +#else +#define PVRSRV_MEMALLOCFLAGS_DEVMEMX_PHYSICAL_MASK (PVRSRV_MEMALLOCFLAGS_CPU_MMUFLAGSMASK | \ + PVRSRV_MEMALLOCFLAG_GPU_CACHE_MODE_MASK | \ + PVRSRV_MEMALLOCFLAG_CPU_READ_PERMITTED | \ + PVRSRV_MEMALLOCFLAG_CPU_WRITE_PERMITTED | \ + PVRSRV_MEMALLOCFLAG_CPU_CACHE_CLEAN | \ + PVRSRV_MEMALLOCFLAG_ZERO_ON_ALLOC | \ + PVRSRV_MEMALLOCFLAG_POISON_ON_ALLOC | \ + PVRSRV_PHYS_HEAP_HINT_MASK) +#endif /*! Flags that affect _virtual allocations_ in the DevMemX API diff --git a/drivers/gpu/drm/img-rogue/pvrsrv_tlcommon.h b/drivers/gpu/drm/img-rogue/pvrsrv_tlcommon.h index 7b5761397..28999e5d2 100644 --- a/drivers/gpu/drm/img-rogue/pvrsrv_tlcommon.h +++ b/drivers/gpu/drm/img-rogue/pvrsrv_tlcommon.h @@ -170,7 +170,7 @@ typedef IMG_UINT32 PVRSRVTL_PACKETTYPE; */ #define PVRSRVTL_SET_PACKET_DATA(len) (len) | (PVRSRVTL_PACKETTYPE_DATA << PVRSRVTL_PACKETHDR_TYPE_OFFSET) #define PVRSRVTL_SET_PACKET_PADDING(len) (len) | (PVRSRVTL_PACKETTYPE_PADDING << PVRSRVTL_PACKETHDR_TYPE_OFFSET) -#define PVRSRVTL_SET_PACKET_WRITE_FAILED (0) | (PVRSRVTL_PACKETTYPE_MOST_RECENT_WRITE_FAILED << PVRSRVTL_PACKETHDR_TYPE_OFFSET) +#define PVRSRVTL_SET_PACKET_WRITE_FAILED (0U) | (PVRSRVTL_PACKETTYPE_MOST_RECENT_WRITE_FAILED << PVRSRVTL_PACKETHDR_TYPE_OFFSET) #define PVRSRVTL_SET_PACKET_HDR(len, type) (len) | ((type) << PVRSRVTL_PACKETHDR_TYPE_OFFSET) /*! Returns the number of bytes of data in the packet. diff --git a/drivers/gpu/drm/img-rogue/pvrversion.h b/drivers/gpu/drm/img-rogue/pvrversion.h index 53db28ba8..c62b3f752 100644 --- a/drivers/gpu/drm/img-rogue/pvrversion.h +++ b/drivers/gpu/drm/img-rogue/pvrversion.h @@ -45,21 +45,21 @@ CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. #define PVRVERSION_H #define PVRVERSION_MAJ 1U -#define PVRVERSION_MIN 16U +#define PVRVERSION_MIN 17U #define PVRVERSION_FAMILY "rogueddk" -#define PVRVERSION_BRANCHNAME "1.16" -#define PVRVERSION_BUILD 6099580 +#define PVRVERSION_BRANCHNAME "1.17" +#define PVRVERSION_BUILD 6210866 #define PVRVERSION_BSCONTROL "Rogue_DDK_Linux_WS" -#define PVRVERSION_STRING "Rogue_DDK_Linux_WS rogueddk 1.16@6099580" -#define PVRVERSION_STRING_SHORT "1.16@6099580" +#define PVRVERSION_STRING "Rogue_DDK_Linux_WS rogueddk 1.17@6210866" +#define PVRVERSION_STRING_SHORT "1.17@6210866" #define COPYRIGHT_TXT "Copyright (c) Imagination Technologies Ltd. All Rights Reserved." -#define PVRVERSION_BUILD_HI 609 -#define PVRVERSION_BUILD_LO 9580 -#define PVRVERSION_STRING_NUMERIC "1.16.609.9580" +#define PVRVERSION_BUILD_HI 621 +#define PVRVERSION_BUILD_LO 866 +#define PVRVERSION_STRING_NUMERIC "1.17.621.866" #define PVRVERSION_PACK(MAJOR,MINOR) (((IMG_UINT32)((IMG_UINT32)(MAJOR) & 0xFFFFU) << 16U) | (((MINOR) & 0xFFFFU) << 0U)) #define PVRVERSION_UNPACK_MAJ(VERSION) (((VERSION) >> 16U) & 0xFFFFU) diff --git a/drivers/gpu/drm/img-rogue/ra.c b/drivers/gpu/drm/img-rogue/ra.c index 43b800369..4c2981e57 100644 --- a/drivers/gpu/drm/img-rogue/ra.c +++ b/drivers/gpu/drm/img-rogue/ra.c @@ -205,14 +205,12 @@ struct _RA_ARENA_ }; -#if defined(__KERNEL__) struct _RA_ARENA_ITERATOR_ { RA_ARENA *pArena; BT *pCurrent; IMG_BOOL bIncludeFreeSegments; }; -#endif /*************************************************************************/ /*! @Function _RequestAllocFail @@ -229,12 +227,12 @@ struct _RA_ARENA_ITERATOR_ */ /**************************************************************************/ static PVRSRV_ERROR _RequestAllocFail(RA_PERARENA_HANDLE _h, - RA_LENGTH_T _uSize, - RA_FLAGS_T _uFlags, - const IMG_CHAR *_pszAnnotation, - RA_BASE_T *_pBase, - RA_LENGTH_T *_pActualSize, - RA_PERISPAN_HANDLE *_phPriv) + RA_LENGTH_T _uSize, + RA_FLAGS_T _uFlags, + const IMG_CHAR *_pszAnnotation, + RA_BASE_T *_pBase, + RA_LENGTH_T *_pActualSize, + RA_PERISPAN_HANDLE *_phPriv) { PVR_UNREFERENCED_PARAMETER(_h); PVR_UNREFERENCED_PARAMETER(_uSize); @@ -291,10 +289,10 @@ pvr_log2(RA_LENGTH_T n) PVR_ASSERT(n != 0); /* Log2 is not defined on 0 */ - n>>=1; - while (n>0) + n >>= 1; + while (n > 0) { - n>>=1; + n >>= 1; l++; } return l; @@ -448,7 +446,7 @@ static int is_arena_valid(struct _RA_ARENA_ *arena) */ /**************************************************************************/ static INLINE void _SegmentListInsertAfter(BT *pInsertionPoint, - BT *pBT) + BT *pBT) { PVR_ASSERT(pBT != NULL); PVR_ASSERT(pInsertionPoint != NULL); @@ -732,7 +730,7 @@ _FreeListRemove(RA_ARENA *pArena, BT *pBT) */ /**************************************************************************/ static BT * _InsertResource(RA_ARENA *pArena, RA_BASE_T base, RA_LENGTH_T uSize, - RA_FLAGS_T uFlags) + RA_FLAGS_T uFlags) { BT *pBT; PVR_ASSERT(pArena!=NULL); @@ -808,7 +806,6 @@ _RemoveResourceSpan(RA_ARENA *pArena, BT *pBT) return IMG_FALSE; } - /*************************************************************************/ /*! @Function _FreeBT @Description Free a boundary tag taking care of the segment list and the @@ -880,9 +877,9 @@ _FreeBT(RA_ARENA *pArena, BT *pBT) */ static INLINE struct _BT_ *find_chunk_in_bucket(struct _BT_ * first_elt, - RA_LENGTH_T uSize, - RA_LENGTH_T uAlignment, - unsigned int nb_max_try) + RA_LENGTH_T uSize, + RA_LENGTH_T uAlignment, + unsigned int nb_max_try) { struct _BT_ *walker; @@ -907,6 +904,93 @@ struct _BT_ *find_chunk_in_bucket(struct _BT_ * first_elt, return NULL; } +/*************************************************************************/ /*! +@Function _AllocAlignSplit +@Description Given a valid BT, trim the start and end of the BT according + to alignment and size requirements. Also add the resulting + BT to the live hash table. +@Input pArena The arena. +@Input pBT The BT to trim and add to live hash table +@Input uSize The requested allocation size. +@Input uAlignment The alignment requirements of the allocation + Required uAlignment, or 0. + Must be a power of 2 if not 0 +@Output pBase Allocated, corrected, resource base + (non-optional, must not be NULL) +@Output phPriv The user references associated with + the imported segment. (optional) +@Return IMG_FALSE failure + IMG_TRUE success +*/ /**************************************************************************/ +static IMG_BOOL +_AllocAlignSplit(RA_ARENA *pArena, + BT *pBT, + RA_LENGTH_T uSize, + RA_LENGTH_T uAlignment, + RA_BASE_T *pBase, + RA_PERISPAN_HANDLE *phPriv) +{ + RA_BASE_T aligned_base; + + aligned_base = (uAlignment > 1) ? (pBT->base + uAlignment - 1) & ~(uAlignment - 1) : pBT->base; + + _FreeListRemove(pArena, pBT); + + if ((pArena->ui32PolicyFlags & RA_POLICY_NO_SPLIT_MASK) == RA_POLICY_NO_SPLIT) + { + goto nosplit; + } + + /* with uAlignment we might need to discard the front of this segment */ + if (aligned_base > pBT->base) + { + BT *pNeighbour; + pNeighbour = _SegmentSplit(pBT, (RA_LENGTH_T)(aligned_base - pBT->base)); + /* partition the buffer, create a new boundary tag */ + if (pNeighbour == NULL) + { + PVR_DPF((PVR_DBG_ERROR, "%s: Front split failed", __func__)); + /* Put pBT back in the list */ + _FreeListInsert(pArena, pBT); + return IMG_FALSE; + } + + _FreeListInsert(pArena, pBT); + pBT = pNeighbour; + } + + /* the segment might be too big, if so, discard the back of the segment */ + if (pBT->uSize > uSize) + { + BT *pNeighbour; + pNeighbour = _SegmentSplit(pBT, uSize); + /* partition the buffer, create a new boundary tag */ + if (pNeighbour == NULL) + { + PVR_DPF((PVR_DBG_ERROR, "%s: Back split failed", __func__)); + /* Put pBT back in the list */ + _FreeListInsert(pArena, pBT); + return IMG_FALSE; + } + + _FreeListInsert(pArena, pNeighbour); + } +nosplit: + pBT->type = btt_live; + + if (!HASH_Insert_Extended(pArena->pSegmentHash, &aligned_base, (uintptr_t)pBT)) + { + _FreeBT(pArena, pBT); + return IMG_FALSE; + } + + if (phPriv != NULL) + *phPriv = pBT->hPriv; + + *pBase = aligned_base; + + return IMG_TRUE; +} /*************************************************************************/ /*! @Function _AttemptAllocAligned @@ -925,18 +1009,17 @@ struct _BT_ *find_chunk_in_bucket(struct _BT_ * first_elt, */ /**************************************************************************/ static IMG_BOOL _AttemptAllocAligned(RA_ARENA *pArena, - RA_LENGTH_T uSize, - RA_FLAGS_T uFlags, - RA_LENGTH_T uAlignment, - RA_BASE_T *base, - RA_PERISPAN_HANDLE *phPriv) /* this is the "per-import" private data */ + RA_LENGTH_T uSize, + RA_FLAGS_T uFlags, + RA_LENGTH_T uAlignment, + RA_BASE_T *base, + RA_PERISPAN_HANDLE *phPriv) /* this is the "per-import" private data */ { IMG_UINT32 index_low; IMG_UINT32 index_high; IMG_UINT32 i; struct _BT_ *pBT = NULL; - RA_BASE_T aligned_base; PVR_ASSERT(pArena!=NULL); PVR_ASSERT(base != NULL); @@ -1009,88 +1092,104 @@ _AttemptAllocAligned(RA_ARENA *pArena, return IMG_FALSE; } - aligned_base = (uAlignment > 1) ? (pBT->base + uAlignment - 1) & ~(uAlignment - 1) : pBT->base; - - _FreeListRemove(pArena, pBT); - - if ((pArena->ui32PolicyFlags & RA_POLICY_NO_SPLIT_MASK) == RA_POLICY_NO_SPLIT) - { - goto nosplit; - } - - /* with uAlignment we might need to discard the front of this segment */ - if (aligned_base > pBT->base) - { - BT *pNeighbour; - pNeighbour = _SegmentSplit(pBT, (RA_LENGTH_T)(aligned_base - pBT->base)); - /* partition the buffer, create a new boundary tag */ - if (pNeighbour == NULL) - { - PVR_DPF((PVR_DBG_ERROR, "%s: Front split failed", __func__)); - /* Put pBT back in the list */ - _FreeListInsert(pArena, pBT); - return IMG_FALSE; - } - - _FreeListInsert(pArena, pBT); - pBT = pNeighbour; - } - - /* the segment might be too big, if so, discard the back of the segment */ - if (pBT->uSize > uSize) - { - BT *pNeighbour; - pNeighbour = _SegmentSplit(pBT, uSize); - /* partition the buffer, create a new boundary tag */ - if (pNeighbour == NULL) - { - PVR_DPF((PVR_DBG_ERROR, "%s: Back split failed", __func__)); - /* Put pBT back in the list */ - _FreeListInsert(pArena, pBT); - return IMG_FALSE; - } - - _FreeListInsert(pArena, pNeighbour); - } -nosplit: - pBT->type = btt_live; - - if (!HASH_Insert_Extended(pArena->pSegmentHash, &aligned_base, (uintptr_t)pBT)) - { - _FreeBT(pArena, pBT); - return IMG_FALSE; - } - - if (phPriv != NULL) - *phPriv = pBT->hPriv; - - *base = aligned_base; - - return IMG_TRUE; + return _AllocAlignSplit(pArena, pBT, uSize, uAlignment, base, phPriv); } - - /*************************************************************************/ /*! -@Function RA_Create -@Description To create a resource arena. -@Input name The name of the arena for diagnostic purposes. -@Input ulog2Quantum The arena allocation quantum. -@Input ui32LockClass the lock class level this arena uses -@Input imp_alloc A resource allocation callback or 0. -@Input imp_free A resource de-allocation callback or 0. -@Input arena_handle Handle passed to alloc and free or 0. -@Input ui32PolicyFlags Policies that govern the arena. -@Return arena handle, or NULL. +@Function _AttemptImportSpanAlloc +@Description Attempt to Import more memory and create a new span. + Function attempts to import more memory from the callback + provided at RA creation time, if successful the memory + will form a new span in the RA. +@Input pArena The arena. +@Input uRequestSize The requested allocation size. +@Input uImportMultiplier Import x-times more for future requests if + we have to import new memory. +@Input uImportFlags Flags influencing allocation policy. +@Input uAlignment The alignment requirements of the allocation + Required uAlignment, or 0. + Must be a power of 2 if not 0 +@Input pszAnnotation String to describe the allocation +@Output pImportBase Allocated import base + (non-optional, must not be NULL) +@Output pImportSize Allocated import size +@Output pImportBT Allocated import BT +@Return PVRSRV_OK - success */ /**************************************************************************/ +static PVRSRV_ERROR +_AttemptImportSpanAlloc(RA_ARENA *pArena, + RA_LENGTH_T uRequestSize, + IMG_UINT8 uImportMultiplier, + RA_FLAGS_T uImportFlags, + RA_LENGTH_T uAlignment, + const IMG_CHAR *pszAnnotation, + RA_BASE_T *pImportBase, + RA_LENGTH_T *pImportSize, + BT **pImportBT) +{ + IMG_HANDLE hPriv; + RA_FLAGS_T uFlags = (uImportFlags & PVRSRV_MEMALLOCFLAGS_RA_DIFFERENTIATION_MASK); + BT *pBT; + PVRSRV_ERROR eError; + + *pImportSize = uRequestSize; + /* + Ensure that we allocate sufficient space to meet the uAlignment + constraint + */ + if (uAlignment > pArena->uQuantum) + { + *pImportSize += (uAlignment - pArena->uQuantum); + } + + /* apply over-allocation multiplier after all alignment adjustments */ + *pImportSize *= uImportMultiplier; + + /* ensure that we import according to the quanta of this arena */ + *pImportSize = (*pImportSize + pArena->uQuantum - 1) & ~(pArena->uQuantum - 1); + + eError = pArena->pImportAlloc(pArena->pImportHandle, + *pImportSize, uImportFlags, + pszAnnotation, + pImportBase, pImportSize, + &hPriv); + if (PVRSRV_OK != eError) + { + return eError; + } + + /* If we successfully import more resource, create a span to + * represent it else free the resource we imported. + */ + pBT = _InsertResourceSpan(pArena, *pImportBase, *pImportSize, uFlags); + if (pBT == NULL) + { + /* insufficient resources to insert the newly acquired span, + so free it back again */ + pArena->pImportFree(pArena->pImportHandle, *pImportBase, hPriv); + + PVR_DPF((PVR_DBG_MESSAGE, "%s: name='%s', " + "size=0x%llx failed!", __func__, pArena->name, + (unsigned long long)uRequestSize)); + /* RA_Dump (arena); */ + + return PVRSRV_ERROR_RA_INSERT_RESOURCE_SPAN_FAILED; + } + + pBT->hPriv = hPriv; + *pImportBT = pBT; + + return eError; +} + IMG_INTERNAL RA_ARENA * RA_Create(IMG_CHAR *name, - RA_LOG2QUANTUM_T uLog2Quantum, - IMG_UINT32 ui32LockClass, - PFN_RA_ALLOC imp_alloc, - PFN_RA_FREE imp_free, - RA_PERARENA_HANDLE arena_handle, - IMG_UINT32 ui32PolicyFlags) + RA_LOG2QUANTUM_T uLog2Quantum, + IMG_UINT32 ui32LockClass, + PFN_RA_ALLOC imp_alloc, + PFN_RA_FREE imp_free, + RA_PERARENA_HANDLE arena_handle, + IMG_UINT32 ui32PolicyFlags) { RA_ARENA *pArena; PVRSRV_ERROR eError; @@ -1215,12 +1314,6 @@ return_: return NULL; } -/*************************************************************************/ /*! -@Function RA_Delete -@Description To delete a resource arena. All resources allocated from - the arena must be freed before deleting the arena. -@Input pArena The arena to delete. -*/ /**************************************************************************/ IMG_INTERNAL void RA_Delete(RA_ARENA *pArena) { @@ -1282,25 +1375,12 @@ RA_Delete(RA_ARENA *pArena) /* not nulling pointer, copy on stack */ } -/*************************************************************************/ /*! -@Function RA_Add -@Description To add a resource span to an arena. The span must not - overlap with any span previously added to the arena. -@Input pArena The arena to add a span into. -@Input base The base of the span. -@Input uSize The extent of the span. -@Input uFlags the flags of the new import -@Input hPriv a private handle associate to the span. - (reserved for user) -@Return IMG_TRUE - Success - IMG_FALSE - failure -*/ /**************************************************************************/ IMG_INTERNAL IMG_BOOL RA_Add(RA_ARENA *pArena, - RA_BASE_T base, - RA_LENGTH_T uSize, - RA_FLAGS_T uFlags, - RA_PERISPAN_HANDLE hPriv) + RA_BASE_T base, + RA_LENGTH_T uSize, + RA_FLAGS_T uFlags, + RA_PERISPAN_HANDLE hPriv) { struct _BT_* bt; PVR_ASSERT(pArena != NULL); @@ -1340,35 +1420,16 @@ RA_Add(RA_ARENA *pArena, return bt != NULL; } -/*************************************************************************/ /*! -@Function RA_Alloc -@Description To allocate resource from an arena. -@Input pArena The arena -@Input uRequestSize The size of resource segment requested. -@Input uImportMultiplier Import x-times more for future requests if - we have to import new memory. -@Input uImportFlags Flags influencing allocation policy. -@Input uAlignment The uAlignment constraint required for the - allocated segment, use 0 if uAlignment not - required, otherwise must be a power of 2. -@Input pszAnnotation String to describe the allocation -@Output base Allocated base resource -@Output pActualSize The actual size of resource segment - allocated, typically rounded up by quantum. -@Output phPriv The user reference associated with allocated - resource span. -@Return PVRSRV_OK - success -*/ /**************************************************************************/ IMG_INTERNAL PVRSRV_ERROR RA_Alloc(RA_ARENA *pArena, - RA_LENGTH_T uRequestSize, - IMG_UINT8 uImportMultiplier, - RA_FLAGS_T uImportFlags, - RA_LENGTH_T uAlignment, - const IMG_CHAR *pszAnnotation, - RA_BASE_T *base, - RA_LENGTH_T *pActualSize, - RA_PERISPAN_HANDLE *phPriv) + RA_LENGTH_T uRequestSize, + IMG_UINT8 uImportMultiplier, + RA_FLAGS_T uImportFlags, + RA_LENGTH_T uAlignment, + const IMG_CHAR *pszAnnotation, + RA_BASE_T *base, + RA_LENGTH_T *pActualSize, + RA_PERISPAN_HANDLE *phPriv) { PVRSRV_ERROR eError; IMG_BOOL bResult; @@ -1378,7 +1439,7 @@ RA_Alloc(RA_ARENA *pArena, if (pArena == NULL || uImportMultiplier == 0 || uSize == 0) { PVR_DPF((PVR_DBG_ERROR, - "%s: One of the necessary parameters is 0", __func__)); + "%s: One of the necessary parameters is 0", __func__)); return PVRSRV_ERROR_INVALID_PARAMS; } @@ -1394,10 +1455,10 @@ RA_Alloc(RA_ARENA *pArena, PVR_ASSERT((uAlignment == 0) || (uAlignment & (uAlignment - 1)) == 0); PVR_DPF((PVR_DBG_MESSAGE, - "%s: arena='%s', size=0x%llx(0x%llx), " - "alignment=0x%llx", __func__, pArena->name, - (unsigned long long)uSize, (unsigned long long)uRequestSize, - (unsigned long long)uAlignment)); + "%s: arena='%s', size=0x%llx(0x%llx), " + "alignment=0x%llx", __func__, pArena->name, + (unsigned long long)uSize, (unsigned long long)uRequestSize, + (unsigned long long)uAlignment)); /* if allocation failed then we might have an import source which can provide more resource, else we will have to fail the @@ -1405,102 +1466,68 @@ RA_Alloc(RA_ARENA *pArena, bResult = _AttemptAllocAligned(pArena, uSize, uFlags, uAlignment, base, phPriv); if (!bResult) { - IMG_HANDLE hPriv; - RA_BASE_T import_base; - RA_LENGTH_T uImportSize = uSize; + RA_BASE_T uImportBase; + RA_LENGTH_T uImportSize; + BT *pBT = NULL; - /* - Ensure that we allocate sufficient space to meet the uAlignment - constraint - */ - if (uAlignment > pArena->uQuantum) - { - uImportSize += (uAlignment - pArena->uQuantum); - } - - /* apply over-allocation multiplier after all alignment adjustments */ - uImportSize *= uImportMultiplier; - - /* ensure that we import according to the quanta of this arena */ - uImportSize = (uImportSize + pArena->uQuantum - 1) & ~(pArena->uQuantum - 1); - - eError = pArena->pImportAlloc(pArena->pImportHandle, - uImportSize, uImportFlags, - pszAnnotation, - &import_base, &uImportSize, - &hPriv); - if (PVRSRV_OK != eError) + eError = _AttemptImportSpanAlloc(pArena, + uSize, + uImportMultiplier, + uFlags, + uAlignment, + pszAnnotation, + &uImportBase, + &uImportSize, + &pBT); + if (eError != PVRSRV_OK) { OSLockRelease(pArena->hLock); return eError; } + + bResult = _AttemptAllocAligned(pArena, uSize, uFlags, uAlignment, base, phPriv); + if (!bResult) + { + PVR_DPF((PVR_DBG_ERROR, + "%s: name='%s' second alloc failed!", + __func__, pArena->name)); + + /* + On failure of _AttemptAllocAligned() depending on the exact point + of failure, the imported segment may have been used and freed, or + left untouched. If the later, we need to return it. + */ + _FreeBT(pArena, pBT); + + OSLockRelease(pArena->hLock); + return PVRSRV_ERROR_RA_ATTEMPT_ALLOC_ALIGNED_FAILED; + } else { - BT *pBT; - pBT = _InsertResourceSpan(pArena, import_base, uImportSize, uFlags); - /* successfully import more resource, create a span to - represent it and retry the allocation attempt */ - if (pBT == NULL) - { - /* insufficient resources to insert the newly acquired span, - so free it back again */ - pArena->pImportFree(pArena->pImportHandle, import_base, hPriv); - - PVR_DPF((PVR_DBG_MESSAGE, "%s: name='%s', " - "size=0x%llx failed!", __func__, pArena->name, - (unsigned long long)uSize)); - /* RA_Dump (arena); */ - - OSLockRelease(pArena->hLock); - return PVRSRV_ERROR_RA_INSERT_RESOURCE_SPAN_FAILED; - } - - pBT->hPriv = hPriv; - - bResult = _AttemptAllocAligned(pArena, uSize, uFlags, uAlignment, base, phPriv); - if (!bResult) + /* Check if the new allocation was in the span we just added... */ + if (*base < uImportBase || *base > (uImportBase + uImportSize)) { PVR_DPF((PVR_DBG_ERROR, - "%s: name='%s' second alloc failed!", - __func__, pArena->name)); + "%s: name='%s' alloc did not occur in the imported span!", + __func__, pArena->name)); /* - On failure of _AttemptAllocAligned() depending on the exact point - of failure, the imported segment may have been used and freed, or - left untouched. If the later, we need to return it. + Remove the imported span which should not be in use (if it is then + that is okay, but essentially no span should exist that is not used). */ _FreeBT(pArena, pBT); - - OSLockRelease(pArena->hLock); - return PVRSRV_ERROR_RA_ATTEMPT_ALLOC_ALIGNED_FAILED; } else { - /* Check if the new allocation was in the span we just added... */ - if (*base < import_base || *base > (import_base + uImportSize)) - { - PVR_DPF((PVR_DBG_ERROR, - "%s: name='%s' alloc did not occur in the imported span!", - __func__, pArena->name)); - - /* - Remove the imported span which should not be in use (if it is then - that is okay, but essentially no span should exist that is not used). - */ - _FreeBT(pArena, pBT); - } - else - { - pArena->ui64FreeArenaSize += uImportSize; - pArena->ui64TotalArenaSize += uImportSize; - } + pArena->ui64FreeArenaSize += uImportSize; + pArena->ui64TotalArenaSize += uImportSize; } } } PVR_DPF((PVR_DBG_MESSAGE, "%s: name='%s', size=0x%llx, " - "*base=0x%llx = %d", __func__, pArena->name, (unsigned long long)uSize, - (unsigned long long)*base, bResult)); + "*base=0x%llx = %d", __func__, pArena->name, (unsigned long long)uSize, + (unsigned long long)*base, bResult)); PVR_ASSERT(is_arena_valid(pArena)); @@ -1573,28 +1600,13 @@ static BT *RA_Find_BT_VARange(RA_ARENA *pArena, return NULL; } - -/*************************************************************************/ /*! -@Function RA_Alloc_Range -@Description To allocate requested device virtual address resource from an arena. -@Input pArena The arena -@Input uRequestSize The size of resource segment requested. -@Input uImportFlags Flags influencing allocation policy. -@Input uAlignment The uAlignment constraint required for the - allocated segment, use 0 if uAlignment not required, otherwise - must be a power of 2. -@input base Allocated base resource -@Output pActualSize The actual size of resource segment - allocated, typically rounded up by quantum. -@Return PVRSRV_OK - success -*/ /**************************************************************************/ IMG_INTERNAL PVRSRV_ERROR RA_Alloc_Range(RA_ARENA *pArena, - RA_LENGTH_T uRequestSize, - RA_FLAGS_T uImportFlags, - RA_LENGTH_T uAlignment, - RA_BASE_T base, - RA_LENGTH_T *pActualSize) + RA_LENGTH_T uRequestSize, + RA_FLAGS_T uImportFlags, + RA_LENGTH_T uAlignment, + RA_BASE_T base, + RA_LENGTH_T *pActualSize) { RA_LENGTH_T uSize = uRequestSize; BT *pBT = NULL; @@ -1602,8 +1614,8 @@ RA_Alloc_Range(RA_ARENA *pArena, if (pArena == NULL || uSize == 0) { - PVR_DPF ((PVR_DBG_ERROR, - "%s: One of the necessary parameters is 0", __func__)); + PVR_DPF((PVR_DBG_ERROR, + "%s: One of the necessary parameters is 0", __func__)); return PVRSRV_ERROR_INVALID_PARAMS; } @@ -1710,12 +1722,6 @@ unlock_: return eError; } -/*************************************************************************/ /*! -@Function RA_Free -@Description To free a resource segment. -@Input pArena The arena the segment was originally allocated from. -@Input base The base of the resource span to free. -*/ /**************************************************************************/ IMG_INTERNAL void RA_Free(RA_ARENA *pArena, RA_BASE_T base) { @@ -1733,7 +1739,7 @@ RA_Free(RA_ARENA *pArena, RA_BASE_T base) PVR_ASSERT(is_arena_valid(pArena)); PVR_DPF((PVR_DBG_MESSAGE, "%s: name='%s', base=0x%llx", __func__, pArena->name, - (unsigned long long)base)); + (unsigned long long)base)); pBT = (BT *) HASH_Remove_Extended(pArena->pSegmentHash, &base); PVR_ASSERT(pBT != NULL); @@ -1763,11 +1769,10 @@ RA_Get_Usage_Stats(RA_ARENA *pArena, PRA_USAGE_STATS psRAStats) psRAStats->ui64FreeArenaSize = pArena->ui64FreeArenaSize; } -#if defined(__KERNEL__) /* #define _DBG(...) PVR_LOG((__VA_ARGS__)) */ #define _DBG(...) -RA_ARENA_ITERATOR * +IMG_INTERNAL RA_ARENA_ITERATOR * RA_IteratorAcquire(RA_ARENA *pArena, IMG_BOOL bIncludeFreeSegments) { RA_ARENA_ITERATOR *pIter = OSAllocMem(sizeof(*pIter)); @@ -1783,7 +1788,7 @@ RA_IteratorAcquire(RA_ARENA *pArena, IMG_BOOL bIncludeFreeSegments) return pIter; } -void +IMG_INTERNAL void RA_IteratorRelease(RA_ARENA_ITERATOR *pIter) { PVR_ASSERT(pIter != NULL); @@ -1798,7 +1803,7 @@ RA_IteratorRelease(RA_ARENA_ITERATOR *pIter) OSFreeMem(pIter); } -void +IMG_INTERNAL void RA_IteratorReset(RA_ARENA_ITERATOR *pIter) { BT *pNext; @@ -1831,7 +1836,7 @@ RA_IteratorReset(RA_ARENA_ITERATOR *pIter) pIter->pCurrent = pNext; } -IMG_BOOL +IMG_INTERNAL IMG_BOOL RA_IteratorNext(RA_ARENA_ITERATOR *pIter, RA_ITERATOR_DATA *pData) { BT *pNext; @@ -1895,4 +1900,267 @@ RA_IteratorNext(RA_ARENA_ITERATOR *pIter, RA_ITERATOR_DATA *pData) return IMG_TRUE; } -#endif /* defined(__KERNEL__) */ + +IMG_INTERNAL PVRSRV_ERROR +RA_BlockDump(RA_ARENA *pArena, void (*pfnLogDump)(void*, IMG_CHAR*, ...), void *pPrivData) +{ + RA_ARENA_ITERATOR *pIter = NULL; + RA_ITERATOR_DATA sIterData; + const IMG_UINT32 uiLineWidth = 64; + + IMG_UINT32 **papRegionArray = NULL; + IMG_UINT32 uiRegionCount = 0; + + const IMG_UINT32 uiChunkSize = 32; /* 32-bit chunks */ + const IMG_UINT32 uiChunkCount = (uiLineWidth / uiChunkSize) * 2; /* This should equal 2 or a multiple of 2 */ + const IMG_UINT32 uiRegionSize = uiChunkSize * uiChunkCount; + + IMG_UINT32 uiRecognisedQuantum = 0; + + IMG_UINT32 uiLastBase = 0; + IMG_UINT32 uiLastSize = 0; + + IMG_UINT32 i; + PVRSRV_ERROR eError = PVRSRV_OK; + + /* -- papRegionArray Structure -- + * papRegionArray Indexes + * | Chunk 0 Chunk 1 Chunk 2 Chunk 3 + * v |------------|------------|------------|------------| + * [0] -> | 0000000000 | 0000000000 | 0000000000 | 0000000000 | -- | + * [1] -> | 0000000000 | 0000000000 | 0000000000 | 0000000000 | | + * [2] -> | 0000000000 | 0000000000 | 0000000000 | 0000000000 | | + * [3] -> | 0000000000 | 0000000000 | 0000000000 | 0000000000 | | Regions + * [4] -> | 0000000000 | 0000000000 | 0000000000 | 0000000000 | | + * [5] -> | 0000000000 | 0000000000 | 0000000000 | 0000000000 | | + * [6] -> | 0000000000 | 0000000000 | 0000000000 | 0000000000 | -- | + * ... + */ + + if (pArena == NULL || pfnLogDump == NULL) + { + return PVRSRV_ERROR_INVALID_PARAMS; + } + + pIter = RA_IteratorAcquire(pArena, IMG_FALSE); + PVR_LOG_RETURN_IF_NOMEM(pIter, "RA_IteratorAcquire"); + + uiRecognisedQuantum = pArena->uQuantum > 0 ? pArena->uQuantum : 4096; + + while (RA_IteratorNext(pIter, &sIterData)) + { + if (sIterData.uiAddr >= uiLastBase) + { + uiLastBase = sIterData.uiAddr; + uiLastSize = sIterData.uiSize; + } + } + + uiRegionCount = ((uiLastBase + uiLastSize) / uiRecognisedQuantum) / uiRegionSize; + if (((uiLastBase + uiLastSize) / uiRecognisedQuantum) % uiRegionSize != 0 + || uiRegionCount == 0) + { + uiRegionCount += 1; + } + + papRegionArray = OSAllocZMem(sizeof(IMG_UINT32*) * uiRegionCount); + PVR_LOG_GOTO_IF_NOMEM(papRegionArray, eError, cleanup_array); + + RA_IteratorReset(pIter); + + while (RA_IteratorNext(pIter, &sIterData)) + { + IMG_UINT32 uiAddrRegionIdx = 0; + IMG_UINT32 uiAddrRegionOffset = 0; + IMG_UINT32 uiAddrChunkIdx = 0; + IMG_UINT32 uiAddrChunkOffset = 0; + IMG_UINT32 uiAddrChunkShift; /* The bit-shift needed to fill the chunk */ + + IMG_UINT32 uiQuantisedSize; + IMG_UINT32 uiQuantisedSizeMod; + IMG_UINT32 uiAllocLastRegionIdx = 0; /* The last region that this alloc appears in */ + IMG_UINT32 uiAllocChunkSize = 0; /* The number of chunks this alloc spans */ + + IMG_INT32 iBitSetCount = 0; + IMG_INT32 iOverflowCheck = 0; + IMG_INT32 iOverflow = 0; + IMG_UINT32 uiRegionIdx = 0; + IMG_UINT32 uiChunkIdx = 0; + +#if defined(__KERNEL__) && defined(__linux__) + IMG_UINT64 uiDataDivRecQuant = sIterData.uiSize; + uiQuantisedSizeMod = do_div(uiDataDivRecQuant, uiRecognisedQuantum); + uiQuantisedSize = (IMG_UINT32)uiDataDivRecQuant; + + uiDataDivRecQuant = sIterData.uiAddr; + do_div(uiDataDivRecQuant, uiRecognisedQuantum); + uiAddrRegionOffset = do_div(uiDataDivRecQuant, uiRegionSize); + uiAddrRegionIdx = (IMG_UINT32)uiDataDivRecQuant; + + uiDataDivRecQuant = sIterData.uiAddr; + do_div(uiDataDivRecQuant, uiRecognisedQuantum); +#else + IMG_UINT64 uiDataDivRecQuant = sIterData.uiAddr / uiRecognisedQuantum; + uiAddrRegionIdx = uiDataDivRecQuant / uiRegionSize; + uiAddrRegionOffset = uiDataDivRecQuant % uiRegionSize; + + uiQuantisedSize = sIterData.uiSize / uiRecognisedQuantum; + uiQuantisedSizeMod = sIterData.uiSize % uiRecognisedQuantum; +#endif + uiAddrChunkIdx = uiAddrRegionOffset / uiChunkSize; + uiAddrChunkOffset = uiAddrRegionOffset % uiChunkSize; + uiAddrChunkShift = uiChunkSize - uiAddrChunkOffset; + uiRegionIdx = uiAddrRegionIdx; + uiChunkIdx = uiAddrChunkIdx; + + if ((uiQuantisedSize == 0) || (uiQuantisedSizeMod != 0)) + { + uiQuantisedSize += 1; + } + +#if defined(__KERNEL__) && defined(__linux__) + uiDataDivRecQuant += uiQuantisedSize - 1; + do_div(uiDataDivRecQuant, uiRegionSize); + uiAllocLastRegionIdx = (IMG_UINT32)uiDataDivRecQuant; +#else + uiAllocLastRegionIdx = + (uiDataDivRecQuant + uiQuantisedSize - 1) / uiRegionSize; +#endif + uiAllocChunkSize = (uiAddrChunkOffset + uiQuantisedSize) / uiChunkSize; + + if ((uiAddrChunkOffset + uiQuantisedSize) % uiChunkSize > 0) + { + uiAllocChunkSize += 1; + } + + iBitSetCount = uiQuantisedSize; + iOverflowCheck = uiQuantisedSize - uiAddrChunkShift; + + if (iOverflowCheck > 0) + { + iOverflow = iOverflowCheck; + iBitSetCount = uiQuantisedSize - iOverflow; + } + + /** + * Allocate memory to represent the chunks for each region the allocation + * spans. If one was already allocated before don't do it again. + */ + for (i = 0; uiAddrRegionIdx + i <= uiAllocLastRegionIdx; i++) + { + if (papRegionArray[uiAddrRegionIdx + i] == NULL) + { + papRegionArray[uiAddrRegionIdx + i] = OSAllocZMem(sizeof(IMG_UINT32) * uiChunkCount); + PVR_LOG_GOTO_IF_NOMEM(papRegionArray[uiAddrRegionIdx + i], eError, cleanup_regions); + } + } + + for (i = 0; i < uiAllocChunkSize; i++) + { + if (uiChunkIdx >= uiChunkCount) + { + uiRegionIdx++; + uiChunkIdx = 0; + } + + if ((IMG_UINT32)iBitSetCount != uiChunkSize) + { + IMG_UINT32 uiBitMask = 0; + + uiBitMask = (1U << iBitSetCount) - 1; + uiBitMask <<= (uiAddrChunkShift - iBitSetCount); + + papRegionArray[uiRegionIdx][uiChunkIdx] |= uiBitMask; + } + else + { + papRegionArray[uiRegionIdx][uiChunkIdx] |= 0xFFFFFFFF; + } + + uiChunkIdx++; + iOverflow -= uiChunkSize; + iBitSetCount = iOverflow >= 0 ? uiChunkSize : uiChunkSize + iOverflow; + if (iOverflow < 0) + { + uiAddrChunkShift = 32; + } + } + } + + RA_IteratorRelease(pIter); + + pfnLogDump(pPrivData, "~~~ '%s' Resource Arena Block Dump", pArena->name); + pfnLogDump(pPrivData, " Block Size: %uB", uiRecognisedQuantum); + pfnLogDump(pPrivData, + " Span Memory Usage: %"IMG_UINT64_FMTSPEC"B" + " Free Span Memory: %"IMG_UINT64_FMTSPEC"B", + pArena->ui64TotalArenaSize, + pArena->ui64FreeArenaSize); + pfnLogDump(pPrivData, + "==============================================================================="); + + for (i = 0; i < uiRegionCount; i++) + { + static IMG_BOOL bEmptyRegion = IMG_FALSE; + if (papRegionArray[i] != NULL) + { + IMG_CHAR pszLine[65]; + IMG_UINT32 j; + + bEmptyRegion = IMG_FALSE; + pszLine[64] = '\0'; + + for (j = 0; j < uiChunkCount; j+=2) + { + IMG_UINT8 uiBit = 0; + IMG_UINT32 k; + IMG_UINT64 uiLineAddress = + (i * uiRegionSize + (j >> 1) * uiLineWidth) * uiRecognisedQuantum; + + /** + * Move through each of the 32 bits in the chunk and check their + * value. If it is 1 we set the corresponding character to '#', + * otherwise it is set to '.' representing empty space + */ + for (k = 1 << 31; k != 0; k >>= 1) + { + pszLine[uiBit] = papRegionArray[i][j] & k ? '#' : '.'; + pszLine[32 + uiBit] = papRegionArray[i][j+1] & k ? '#' : '.'; + uiBit++; + } + + pfnLogDump(pPrivData, + "| 0x%08"IMG_UINT64_FMTSPECx" | %s", + uiLineAddress, + pszLine); + } + OSFreeMem(papRegionArray[i]); + } + else + { + /* We only print this once per gap of n regions */ + if (!bEmptyRegion) + { + pfnLogDump(pPrivData, " ...."); + bEmptyRegion = IMG_TRUE; + } + } + } + OSFreeMem(papRegionArray); + return eError; + +cleanup_regions: + for (i = 0; i < uiRegionCount; i++) + { + if (papRegionArray[i] != NULL) + { + OSFreeMem(papRegionArray[i]); + } + } + +cleanup_array: + OSFreeMem(papRegionArray); + RA_IteratorRelease(pIter); + + return eError; +} diff --git a/drivers/gpu/drm/img-rogue/ra.h b/drivers/gpu/drm/img-rogue/ra.h index ed76936e6..d306af7ed 100644 --- a/drivers/gpu/drm/img-rogue/ra.h +++ b/drivers/gpu/drm/img-rogue/ra.h @@ -53,7 +53,6 @@ CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. */ typedef struct _RA_ARENA_ RA_ARENA; //PRQA S 3313 -#if defined(__KERNEL__) /** Resource arena's iterator. * struct _RA_ARENA_ITERATOR_ deliberately opaque */ @@ -64,7 +63,6 @@ typedef struct _RA_ITERATOR_DATA_ { IMG_UINT64 uiSize; IMG_BOOL bFree; } RA_ITERATOR_DATA; -#endif /* defined(__KERNEL__) */ /** Resource arena usage statistics. * struct _RA_USAGE_STATS @@ -358,18 +356,31 @@ RA_Free(RA_ARENA *pArena, RA_BASE_T base); IMG_INTERNAL void RA_Get_Usage_Stats(RA_ARENA *pArena, PRA_USAGE_STATS psRAStats); -#if defined(__KERNEL__) -RA_ARENA_ITERATOR * +IMG_INTERNAL RA_ARENA_ITERATOR * RA_IteratorAcquire(RA_ARENA *pArena, IMG_BOOL bIncludeFreeSegments); -void +IMG_INTERNAL void RA_IteratorReset(RA_ARENA_ITERATOR *pIter); -void +IMG_INTERNAL void RA_IteratorRelease(RA_ARENA_ITERATOR *pIter); -IMG_BOOL +IMG_INTERNAL IMG_BOOL RA_IteratorNext(RA_ARENA_ITERATOR *pIter, RA_ITERATOR_DATA *pData); -#endif /* defined(__KERNEL__) */ + +/*************************************************************************/ /*! +@Function RA_BlockDump +@Description Debug dump of all memory allocations within the RA and the space + between. A '#' represents a block of memory (the arena's quantum + in size) that has been allocated whereas a '.' represents a free + block. +@Input pArena The arena to dump. +@Input pfnLogDump The dumping method. +@Input pPrivData Data to be passed into the pfnLogDump method. +*/ /**************************************************************************/ +IMG_INTERNAL PVRSRV_ERROR +RA_BlockDump(RA_ARENA *pArena, + __printf(2, 3) void (*pfnLogDump)(void*, IMG_CHAR*, ...), + void *pPrivData); #endif diff --git a/drivers/gpu/drm/img-rogue/rgx_bridge.h b/drivers/gpu/drm/img-rogue/rgx_bridge.h index 96589ca34..fa4ca1ff5 100644 --- a/drivers/gpu/drm/img-rogue/rgx_bridge.h +++ b/drivers/gpu/drm/img-rogue/rgx_bridge.h @@ -57,7 +57,9 @@ extern "C" { #include "common_rgxta3d_bridge.h" #include "common_rgxcmp_bridge.h" +#if defined(SUPPORT_FASTRENDER_DM) #include "common_rgxtq2_bridge.h" +#endif #if defined(SUPPORT_RGXTQ_BRIDGE) #include "common_rgxtq_bridge.h" #endif @@ -169,14 +171,22 @@ extern "C" { #define PVRSRV_BRIDGE_RGXKICKSYNC_DISPATCH_FIRST (PVRSRV_BRIDGE_RGXREGCONFIG_DISPATCH_LAST + 1) #define PVRSRV_BRIDGE_RGXKICKSYNC_DISPATCH_LAST (PVRSRV_BRIDGE_RGXKICKSYNC_DISPATCH_FIRST + PVRSRV_BRIDGE_RGXKICKSYNC_CMD_LAST) +/* 137: RGX TQ2 interface */ #define PVRSRV_BRIDGE_RGXTQ2 137UL +#if defined(SUPPORT_FASTRENDER_DM) #define PVRSRV_BRIDGE_RGXTQ2_DISPATCH_FIRST (PVRSRV_BRIDGE_RGXKICKSYNC_DISPATCH_LAST + 1) #define PVRSRV_BRIDGE_RGXTQ2_DISPATCH_LAST (PVRSRV_BRIDGE_RGXTQ2_DISPATCH_FIRST + PVRSRV_BRIDGE_RGXTQ2_CMD_LAST) +#else +#define PVRSRV_BRIDGE_RGXTQ2_DISPATCH_FIRST (0) +#define PVRSRV_BRIDGE_RGXTQ2_DISPATCH_LAST (PVRSRV_BRIDGE_RGXKICKSYNC_DISPATCH_LAST) +#endif +/* 138: RGX timer query interface */ #define PVRSRV_BRIDGE_RGXTIMERQUERY 138UL #define PVRSRV_BRIDGE_RGXTIMERQUERY_DISPATCH_FIRST (PVRSRV_BRIDGE_RGXTQ2_DISPATCH_LAST + 1) #define PVRSRV_BRIDGE_RGXTIMERQUERY_DISPATCH_LAST (PVRSRV_BRIDGE_RGXTIMERQUERY_DISPATCH_FIRST + PVRSRV_BRIDGE_RGXTIMERQUERY_CMD_LAST) +/* 139: RGX Ray tracing interface */ #define PVRSRV_BRIDGE_RGXRAY 139UL #if defined(SUPPORT_RGXRAY_BRIDGE) #define PVRSRV_BRIDGE_RGXRAY_DISPATCH_FIRST (PVRSRV_BRIDGE_RGXTIMERQUERY_DISPATCH_LAST + 1) diff --git a/drivers/gpu/drm/img-rogue/rgx_bridge_init.c b/drivers/gpu/drm/img-rogue/rgx_bridge_init.c index 82313f7c3..1b1f81d78 100644 --- a/drivers/gpu/drm/img-rogue/rgx_bridge_init.c +++ b/drivers/gpu/drm/img-rogue/rgx_bridge_init.c @@ -46,13 +46,15 @@ CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. #include "rgx_bridge_init.h" #include "rgxdevice.h" +#if defined(RGX_FEATURE_FASTRENDER_DM_BIT_MASK) PVRSRV_ERROR InitRGXTQ2Bridge(void); -PVRSRV_ERROR DeinitRGXTQ2Bridge(void); +void DeinitRGXTQ2Bridge(void); +#endif PVRSRV_ERROR InitRGXCMPBridge(void); -PVRSRV_ERROR DeinitRGXCMPBridge(void); +void DeinitRGXCMPBridge(void); #if defined(SUPPORT_RGXRAY_BRIDGE) PVRSRV_ERROR InitRGXRAYBridge(void); -PVRSRV_ERROR DeinitRGXRAYBridge(void); +void DeinitRGXRAYBridge(void); #endif PVRSRV_ERROR DeviceDepBridgeInit(PVRSRV_RGXDEV_INFO *psDevInfo) @@ -65,11 +67,13 @@ PVRSRV_ERROR DeviceDepBridgeInit(PVRSRV_RGXDEV_INFO *psDevInfo) PVR_LOG_RETURN_IF_ERROR(eError, "InitRGXCMPBridge"); } +#if defined(RGX_FEATURE_FASTRENDER_DM_BIT_MASK) if (RGX_IS_FEATURE_SUPPORTED(psDevInfo, FASTRENDER_DM)) { eError = InitRGXTQ2Bridge(); PVR_LOG_RETURN_IF_ERROR(eError, "InitRGXTQ2Bridge"); } +#endif #if defined(SUPPORT_RGXRAY_BRIDGE) if (RGX_IS_FEATURE_VALUE_SUPPORTED(psDevInfo, RAY_TRACING_ARCH) && @@ -83,30 +87,25 @@ PVRSRV_ERROR DeviceDepBridgeInit(PVRSRV_RGXDEV_INFO *psDevInfo) return PVRSRV_OK; } -PVRSRV_ERROR DeviceDepBridgeDeInit(PVRSRV_RGXDEV_INFO *psDevInfo) +void DeviceDepBridgeDeInit(PVRSRV_RGXDEV_INFO *psDevInfo) { - PVRSRV_ERROR eError; - if (RGX_IS_FEATURE_SUPPORTED(psDevInfo, COMPUTE)) { - eError = DeinitRGXCMPBridge(); - PVR_LOG_RETURN_IF_ERROR(eError, "DeinitRGXCMPBridge"); + DeinitRGXCMPBridge(); } +#if defined(RGX_FEATURE_FASTRENDER_DM_BIT_MASK) if (RGX_IS_FEATURE_SUPPORTED(psDevInfo, FASTRENDER_DM)) { - eError = DeinitRGXTQ2Bridge(); - PVR_LOG_RETURN_IF_ERROR(eError, "DeinitRGXTQ2Bridge"); + DeinitRGXTQ2Bridge(); } +#endif #if defined(SUPPORT_RGXRAY_BRIDGE) if (RGX_IS_FEATURE_VALUE_SUPPORTED(psDevInfo, RAY_TRACING_ARCH) && RGX_GET_FEATURE_VALUE(psDevInfo, RAY_TRACING_ARCH) > 0) { - eError = DeinitRGXRAYBridge(); - PVR_LOG_RETURN_IF_ERROR(eError, "DeinitRGXRAYBridge"); + DeinitRGXRAYBridge(); } #endif - - return PVRSRV_OK; } diff --git a/drivers/gpu/drm/img-rogue/rgx_bridge_init.h b/drivers/gpu/drm/img-rogue/rgx_bridge_init.h index ba0d2044c..10e8e72ca 100644 --- a/drivers/gpu/drm/img-rogue/rgx_bridge_init.h +++ b/drivers/gpu/drm/img-rogue/rgx_bridge_init.h @@ -50,7 +50,6 @@ CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. #include "rgxdevice.h" PVRSRV_ERROR DeviceDepBridgeInit(PVRSRV_RGXDEV_INFO *psDevInfo); -PVRSRV_ERROR DeviceDepBridgeDeInit(PVRSRV_RGXDEV_INFO *psDevInfo); +void DeviceDepBridgeDeInit(PVRSRV_RGXDEV_INFO *psDevInfo); #endif /* RGX_BRIDGE_INIT_H */ - diff --git a/drivers/gpu/drm/img-rogue/rgx_common.h b/drivers/gpu/drm/img-rogue/rgx_common.h index b20d0456e..b6ae1500a 100644 --- a/drivers/gpu/drm/img-rogue/rgx_common.h +++ b/drivers/gpu/drm/img-rogue/rgx_common.h @@ -52,20 +52,7 @@ extern "C" { /* Included to get the BVNC_KM_N defined and other feature defs */ #include "km/rgxdefs_km.h" -/*! This macro represents a mask of LSBs that must be zero on data structure - * sizes and offsets to ensure they are 8-byte granular on types shared between - * the FW and host driver */ -#define RGX_FW_ALIGNMENT_LSB (7U) - -/*! Macro to test structure size alignment */ -#define RGX_FW_STRUCT_SIZE_ASSERT(_a) \ - static_assert((sizeof(_a) & RGX_FW_ALIGNMENT_LSB) == 0U, \ - "Size of " #_a " is not properly aligned") - -/*! Macro to test structure member alignment */ -#define RGX_FW_STRUCT_OFFSET_ASSERT(_a, _b) \ - static_assert((offsetof(_a, _b) & RGX_FW_ALIGNMENT_LSB) == 0U, \ - "Offset of " #_a "." #_b " is not properly aligned") +#include "rgx_common_asserts.h" /* Virtualisation validation builds are meant to test the VZ-related hardware without a fully virtualised platform. @@ -99,25 +86,25 @@ typedef IMG_UINT32 RGXFWIF_DM; #define RGXFWIF_DM_CDM IMG_UINT32_C(4) #define RGXFWIF_DM_RAY IMG_UINT32_C(5) #define RGXFWIF_DM_GEOM2 IMG_UINT32_C(6) +#define RGXFWIF_DM_GEOM3 IMG_UINT32_C(7) +#define RGXFWIF_DM_GEOM4 IMG_UINT32_C(8) -#define RGXFWIF_DM_LAST RGXFWIF_DM_GEOM2 +#define RGXFWIF_DM_LAST RGXFWIF_DM_GEOM4 -typedef enum _RGX_KICK_TYPE_DM_ -{ - RGX_KICK_TYPE_DM_GP = 0x001, - RGX_KICK_TYPE_DM_TDM_2D = 0x002, - RGX_KICK_TYPE_DM_TA = 0x004, - RGX_KICK_TYPE_DM_3D = 0x008, - RGX_KICK_TYPE_DM_CDM = 0x010, - RGX_KICK_TYPE_DM_RTU = 0x020, - RGX_KICK_TYPE_DM_SHG = 0x040, - RGX_KICK_TYPE_DM_TQ2D = 0x080, - RGX_KICK_TYPE_DM_TQ3D = 0x100, - RGX_KICK_TYPE_DM_RAY = 0x200, - RGX_KICK_TYPE_DM_LAST = 0x400 -} RGX_KICK_TYPE_DM; +typedef IMG_UINT32 RGX_KICK_TYPE_DM; +#define RGX_KICK_TYPE_DM_GP IMG_UINT32_C(0x001) +#define RGX_KICK_TYPE_DM_TDM_2D IMG_UINT32_C(0x002) +#define RGX_KICK_TYPE_DM_TA IMG_UINT32_C(0x004) +#define RGX_KICK_TYPE_DM_3D IMG_UINT32_C(0x008) +#define RGX_KICK_TYPE_DM_CDM IMG_UINT32_C(0x010) +#define RGX_KICK_TYPE_DM_RTU IMG_UINT32_C(0x020) +#define RGX_KICK_TYPE_DM_SHG IMG_UINT32_C(0x040) +#define RGX_KICK_TYPE_DM_TQ2D IMG_UINT32_C(0x080) +#define RGX_KICK_TYPE_DM_TQ3D IMG_UINT32_C(0x100) +#define RGX_KICK_TYPE_DM_RAY IMG_UINT32_C(0x200) +#define RGX_KICK_TYPE_DM_LAST IMG_UINT32_C(0x400) -/* Maximum number of DM in use: GP, 2D/TDM, GEOM, 3D, CDM, RDM, GEOM2 */ +/* Maximum number of DM in use: GP, 2D/TDM, GEOM, 3D, CDM, RDM, GEOM2, GEOM3, GEOM4 */ #define RGXFWIF_DM_MAX (RGXFWIF_DM_LAST + 1U) /* @@ -201,10 +188,18 @@ typedef enum _RGX_KICK_TYPE_DM_ #define RGX_MAX_NUM_REGISTER_PROGRAMMER_WRITES (128U) /* FW common context priority. */ -#define RGX_CTX_PRIORITY_REALTIME (UINT32_MAX) -#define RGX_CTX_PRIORITY_HIGH (2U) -#define RGX_CTX_PRIORITY_MEDIUM (1U) -#define RGX_CTX_PRIORITY_LOW (0) +/*! + * @AddToGroup WorkloadContexts + * @{ + */ +#define RGX_CTX_PRIORITY_REALTIME (INT32_MAX) +#define RGX_CTX_PRIORITY_HIGH (2U) /*!< HIGH priority */ +#define RGX_CTX_PRIORITY_MEDIUM (1U) /*!< MEDIUM priority */ +#define RGX_CTX_PRIORITY_LOW (0) /*!< LOW priority */ +/*! + * @} End of AddToGroup WorkloadContexts + */ + /* * Use of the 32-bit context property flags mask @@ -220,6 +215,9 @@ typedef enum _RGX_KICK_TYPE_DM_ */ #define RGX_CONTEXT_FLAG_DISABLESLR (1UL << 0) /*!< Disable SLR */ +/* Bitmask of context flags allowed to be modified after context create. */ +#define RGX_CONTEXT_FLAGS_WRITEABLE_MASK (RGX_CONTEXT_FLAG_DISABLESLR) + /* List of attributes that may be set for a context */ typedef enum _RGX_CONTEXT_PROPERTY_ { diff --git a/drivers/gpu/drm/img-rogue/rgx_common_asserts.h b/drivers/gpu/drm/img-rogue/rgx_common_asserts.h new file mode 100644 index 000000000..c571cc6f0 --- /dev/null +++ b/drivers/gpu/drm/img-rogue/rgx_common_asserts.h @@ -0,0 +1,73 @@ +/*************************************************************************/ /*! +@File +@Title RGX Common Types and Defines Header +@Copyright Copyright (c) Imagination Technologies Ltd. All Rights Reserved +@Description Common types and definitions for RGX software +@License Dual MIT/GPLv2 + +The contents of this file are subject to the MIT license as set out below. + +Permission is hereby granted, free of charge, to any person obtaining a copy +of this software and associated documentation files (the "Software"), to deal +in the Software without restriction, including without limitation the rights +to use, copy, modify, merge, publish, distribute, sublicense, and/or sell +copies of the Software, and to permit persons to whom the Software is +furnished to do so, subject to the following conditions: + +The above copyright notice and this permission notice shall be included in +all copies or substantial portions of the Software. + +Alternatively, the contents of this file may be used under the terms of +the GNU General Public License Version 2 ("GPL") in which case the provisions +of GPL are applicable instead of those above. + +If you wish to allow use of your version of this file only under the terms of +GPL, and not to allow others to use your version of this file under the terms +of the MIT license, indicate your decision by deleting the provisions above +and replace them with the notice and other provisions required by GPL as set +out in the file called "GPL-COPYING" included in this distribution. If you do +not delete the provisions above, a recipient may use your version of this file +under the terms of either the MIT license or GPL. + +This License is also included in this distribution in the file called +"MIT-COPYING". + +EXCEPT AS OTHERWISE STATED IN A NEGOTIATED AGREEMENT: (A) THE SOFTWARE IS +PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING +BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR +PURPOSE AND NONINFRINGEMENT; AND (B) IN NO EVENT SHALL THE AUTHORS OR +COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER +IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN +CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +*/ /**************************************************************************/ +#ifndef RGX_COMMON_ASSERTS_H +#define RGX_COMMON_ASSERTS_H + +#if defined(__cplusplus) +extern "C" { +#endif + +/*! This macro represents a mask of LSBs that must be zero on data structure + * sizes and offsets to ensure they are 8-byte granular on types shared between + * the FW and host driver */ +#define RGX_FW_ALIGNMENT_LSB (7U) + +/*! Macro to test structure size alignment */ +#define RGX_FW_STRUCT_SIZE_ASSERT(_a) \ + static_assert((sizeof(_a) & RGX_FW_ALIGNMENT_LSB) == 0U, \ + "Size of " #_a " is not properly aligned") + +/*! Macro to test structure member alignment */ +#define RGX_FW_STRUCT_OFFSET_ASSERT(_a, _b) \ + static_assert((offsetof(_a, _b) & RGX_FW_ALIGNMENT_LSB) == 0U, \ + "Offset of " #_a "." #_b " is not properly aligned") + +#if defined(__cplusplus) +} +#endif + +#endif /* RGX_COMMON_ASSERTS_H */ + +/****************************************************************************** + End of file +******************************************************************************/ diff --git a/drivers/gpu/drm/img-rogue/rgx_compat_bvnc.h b/drivers/gpu/drm/img-rogue/rgx_compat_bvnc.h index 748a59113..c3e1333cd 100644 --- a/drivers/gpu/drm/img-rogue/rgx_compat_bvnc.h +++ b/drivers/gpu/drm/img-rogue/rgx_compat_bvnc.h @@ -110,7 +110,7 @@ CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. (bvnc) = ((L).ui64BVNC == (R).ui64BVNC); \ } \ (all) = (version) && (bvnc); \ - } while (0) + } while (false) /**************************************************************************//** diff --git a/drivers/gpu/drm/img-rogue/rgx_fwif_hwperf.h b/drivers/gpu/drm/img-rogue/rgx_fwif_hwperf.h index a75a07b55..7001092c7 100644 --- a/drivers/gpu/drm/img-rogue/rgx_fwif_hwperf.h +++ b/drivers/gpu/drm/img-rogue/rgx_fwif_hwperf.h @@ -68,6 +68,20 @@ typedef struct IMG_UINT32 aui32SelectedCountersIDs[RGX_HWPERF_MAX_CUSTOM_CNTRS]; } RGXFW_HWPERF_SELECT; +/* Structure used to hold a Direct-Addressable block's parameters for passing + * between the BG context and the IRQ context when applying a configuration + * request. RGX_FEATURE_HWPERF_OCEANIC use only. + */ +typedef struct +{ + IMG_UINT32 uiEnabled; + IMG_UINT32 uiNumCounters; + IMG_UINT32 eBlockID; + RGXFWIF_DEV_VIRTADDR psModel; + IMG_UINT32 aui32Counters[RGX_CNTBLK_COUNTERS_MAX]; +} RGXFWIF_HWPERF_DA_BLK; + + /* Structure to hold the whole configuration request details for all blocks * The block masks and counts are used to optimise reading of this data. */ typedef struct @@ -77,8 +91,8 @@ typedef struct IMG_UINT32 ui32SelectedCountersBlockMask; RGXFW_HWPERF_SELECT RGXFW_ALIGN SelCntr[RGX_HWPERF_MAX_CUSTOM_BLKS]; - IMG_UINT32 ui32EnabledBlksCount; - RGXFWIF_HWPERF_CTL_BLK RGXFW_ALIGN sBlkCfg[RGX_HWPERF_MAX_DEFINED_BLKS]; + IMG_UINT32 ui32EnabledMUXBlksCount; + RGXFWIF_HWPERF_CTL_BLK RGXFW_ALIGN sBlkCfg[RGX_HWPERF_MAX_MUX_BLKS]; } UNCACHED_ALIGN RGXFWIF_HWPERF_CTL; /* NOTE: The switch statement in this function must be kept in alignment with @@ -90,7 +104,7 @@ typedef struct #ifdef INLINE_IS_PRAGMA #pragma inline(rgxfw_hwperf_get_block_ctl) #endif -static INLINE RGXFWIF_HWPERF_CTL_BLK* rgxfw_hwperf_get_block_ctl( +static INLINE RGXFWIF_HWPERF_CTL_BLK *rgxfw_hwperf_get_block_ctl( RGX_HWPERF_CNTBLK_ID eBlockID, RGXFWIF_HWPERF_CTL *psHWPerfInitData) { IMG_UINT32 ui32Idx; @@ -221,4 +235,18 @@ static INLINE RGXFWIF_HWPERF_CTL_BLK* rgxfw_hwperf_get_block_ctl( return &psHWPerfInitData->sBlkCfg[ui32Idx]; } +/* Stub routine for rgxfw_hwperf_get_da_block_ctl() for non + * RGX_FEATURE_HWPERF_OCEANIC systems. Just return a NULL. + */ +#ifdef INLINE_IS_PRAGMA +#pragma inline(rgxfw_hwperf_get_da_block_ctl) +#endif +static INLINE RGXFWIF_HWPERF_DA_BLK* rgxfw_hwperf_get_da_block_ctl( + RGX_HWPERF_CNTBLK_ID eBlockID, RGXFWIF_HWPERF_CTL *psHWPerfInitData) +{ + PVR_UNREFERENCED_PARAMETER(eBlockID); + PVR_UNREFERENCED_PARAMETER(psHWPerfInitData); + + return NULL; +} #endif diff --git a/drivers/gpu/drm/img-rogue/rgx_fwif_km.h b/drivers/gpu/drm/img-rogue/rgx_fwif_km.h index 16f5cd489..724f6eecd 100644 --- a/drivers/gpu/drm/img-rogue/rgx_fwif_km.h +++ b/drivers/gpu/drm/img-rogue/rgx_fwif_km.h @@ -109,21 +109,21 @@ typedef struct { #define RGXFWIF_LOG_ENABLED_GROUPS_LIST_PFSPEC "%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s" /* Used in a print statement to display log group state, one per group */ -#define RGXFWIF_LOG_ENABLED_GROUPS_LIST(types) (((types) & RGXFWIF_LOG_TYPE_GROUP_MAIN) ?("main ") :("")), \ - (((types) & RGXFWIF_LOG_TYPE_GROUP_MTS) ?("mts ") :("")), \ - (((types) & RGXFWIF_LOG_TYPE_GROUP_CLEANUP) ?("cleanup ") :("")), \ - (((types) & RGXFWIF_LOG_TYPE_GROUP_CSW) ?("csw ") :("")), \ - (((types) & RGXFWIF_LOG_TYPE_GROUP_BIF) ?("bif ") :("")), \ - (((types) & RGXFWIF_LOG_TYPE_GROUP_PM) ?("pm ") :("")), \ - (((types) & RGXFWIF_LOG_TYPE_GROUP_RTD) ?("rtd ") :("")), \ - (((types) & RGXFWIF_LOG_TYPE_GROUP_SPM) ?("spm ") :("")), \ - (((types) & RGXFWIF_LOG_TYPE_GROUP_POW) ?("pow ") :("")), \ - (((types) & RGXFWIF_LOG_TYPE_GROUP_HWR) ?("hwr ") :("")), \ - (((types) & RGXFWIF_LOG_TYPE_GROUP_HWP) ?("hwp ") :("")), \ - (((types) & RGXFWIF_LOG_TYPE_GROUP_RPM) ?("rpm ") :("")), \ - (((types) & RGXFWIF_LOG_TYPE_GROUP_DMA) ?("dma ") :("")), \ - (((types) & RGXFWIF_LOG_TYPE_GROUP_MISC) ?("misc ") :("")), \ - (((types) & RGXFWIF_LOG_TYPE_GROUP_DEBUG) ?("debug ") :("")) +#define RGXFWIF_LOG_ENABLED_GROUPS_LIST(types) ((((types) & RGXFWIF_LOG_TYPE_GROUP_MAIN) != 0U) ?("main ") :("")), \ + ((((types) & RGXFWIF_LOG_TYPE_GROUP_MTS) != 0U) ?("mts ") :("")), \ + ((((types) & RGXFWIF_LOG_TYPE_GROUP_CLEANUP) != 0U) ?("cleanup ") :("")), \ + ((((types) & RGXFWIF_LOG_TYPE_GROUP_CSW) != 0U) ?("csw ") :("")), \ + ((((types) & RGXFWIF_LOG_TYPE_GROUP_BIF) != 0U) ?("bif ") :("")), \ + ((((types) & RGXFWIF_LOG_TYPE_GROUP_PM) != 0U) ?("pm ") :("")), \ + ((((types) & RGXFWIF_LOG_TYPE_GROUP_RTD) != 0U) ?("rtd ") :("")), \ + ((((types) & RGXFWIF_LOG_TYPE_GROUP_SPM) != 0U) ?("spm ") :("")), \ + ((((types) & RGXFWIF_LOG_TYPE_GROUP_POW) != 0U) ?("pow ") :("")), \ + ((((types) & RGXFWIF_LOG_TYPE_GROUP_HWR) != 0U) ?("hwr ") :("")), \ + ((((types) & RGXFWIF_LOG_TYPE_GROUP_HWP) != 0U) ?("hwp ") :("")), \ + ((((types) & RGXFWIF_LOG_TYPE_GROUP_RPM) != 0U) ?("rpm ") :("")), \ + ((((types) & RGXFWIF_LOG_TYPE_GROUP_DMA) != 0U) ?("dma ") :("")), \ + ((((types) & RGXFWIF_LOG_TYPE_GROUP_MISC) != 0U) ?("misc ") :("")), \ + ((((types) & RGXFWIF_LOG_TYPE_GROUP_DEBUG) != 0U) ?("debug ") :("")) /************************************************************************ @@ -156,20 +156,31 @@ typedef struct IMG_UINT32 ui32LineNum; } UNCACHED_ALIGN RGXFWIF_FILE_INFO_BUF; +/*! + * @Defgroup SRVAndFWTracing Services and Firmware Tracing data interface + * @Brief The document groups/lists the data structures and the interfaces related to Services and Firmware Tracing + * @{ + */ + +/*! + * @Brief Firmware trace buffer details + */ typedef struct { - IMG_UINT32 ui32TracePointer; + IMG_UINT32 ui32TracePointer; /*!< Trace pointer (write index into Trace Buffer)*/ #if defined(RGX_FIRMWARE) - IMG_UINT32 *pui32RGXFWIfTraceBuffer; /* To be used by firmware for writing into trace buffer */ + IMG_UINT32 *pui32RGXFWIfTraceBuffer; /*!< Trace buffer address (FW address), to be used by firmware for writing into trace buffer */ #else - RGXFWIF_DEV_VIRTADDR pui32RGXFWIfTraceBuffer; + RGXFWIF_DEV_VIRTADDR pui32RGXFWIfTraceBuffer; /*!< Trace buffer address (FW address)*/ #endif - IMG_PUINT32 pui32TraceBuffer; /* To be used by host when reading from trace buffer */ + IMG_PUINT32 pui32TraceBuffer; /*!< Trace buffer address (Host address), to be used by host when reading from trace buffer */ - RGXFWIF_FILE_INFO_BUF sAssertBuf; + RGXFWIF_FILE_INFO_BUF sAssertBuf; } UNCACHED_ALIGN RGXFWIF_TRACEBUF_SPACE; +/*! @} End of Defgroup SRVAndFWTracing */ + #define RGXFWIF_FWFAULTINFO_MAX (8U) /* Total number of FW fault logs stored */ typedef struct @@ -229,14 +240,12 @@ typedef IMG_UINT32 RGXFWIF_HWR_STATEFLAGS; #define RGXFWIF_DM_STATE_GPU_ECC_HWR (IMG_UINT32_C(0x1) << 10) /*!< DM was forced into HWR due to an uncorrected GPU ECC error */ /* Firmware's connection state */ -typedef enum -{ - RGXFW_CONNECTION_FW_OFFLINE = 0, /*!< Firmware is offline */ - RGXFW_CONNECTION_FW_READY, /*!< Firmware is initialised */ - RGXFW_CONNECTION_FW_ACTIVE, /*!< Firmware connection is fully established */ - RGXFW_CONNECTION_FW_OFFLOADING, /*!< Firmware is clearing up connection data */ - RGXFW_CONNECTION_FW_STATE_COUNT -} RGXFWIF_CONNECTION_FW_STATE; +typedef IMG_UINT32 RGXFWIF_CONNECTION_FW_STATE; +#define RGXFW_CONNECTION_FW_OFFLINE 0U /*!< Firmware is offline */ +#define RGXFW_CONNECTION_FW_READY 1U /*!< Firmware is initialised */ +#define RGXFW_CONNECTION_FW_ACTIVE 2U /*!< Firmware connection is fully established */ +#define RGXFW_CONNECTION_FW_OFFLOADING 3U /*!< Firmware is clearing up connection data */ +#define RGXFW_CONNECTION_FW_STATE_COUNT 4U /* OS' connection state */ typedef enum @@ -259,7 +268,7 @@ typedef struct typedef IMG_UINT32 RGXFWIF_HWR_RECOVERYFLAGS; #if defined(PVRSRV_STALLED_CCB_ACTION) -#define PVR_SLR_LOG_ENTRIES 10 +#define PVR_SLR_LOG_ENTRIES 10U #define PVR_SLR_LOG_STRLEN 30 /*!< MAX_CLIENT_CCB_NAME not visible to this header */ typedef struct @@ -271,14 +280,17 @@ typedef struct } UNCACHED_ALIGN RGXFWIF_SLR_ENTRY; #endif -/* firmware trace control data */ +/*! + * @InGroup SRVAndFWTracing + * @Brief Firmware trace control data + */ typedef struct { - IMG_UINT32 ui32LogType; - RGXFWIF_TRACEBUF_SPACE sTraceBuf[RGXFW_THREAD_NUM]; - IMG_UINT32 ui32TraceBufSizeInDWords; /*!< Member initialised only when sTraceBuf is actually allocated - * (in RGXTraceBufferInitOnDemandResources) */ - IMG_UINT32 ui32TracebufFlags; /*!< Compatibility and other flags */ + IMG_UINT32 ui32LogType; /*!< FW trace log group configuration */ + RGXFWIF_TRACEBUF_SPACE sTraceBuf[RGXFW_THREAD_NUM]; /*!< FW Trace buffer */ + IMG_UINT32 ui32TraceBufSizeInDWords; /*!< FW Trace buffer size in dwords, Member initialised only when sTraceBuf is actually allocated + (in RGXTraceBufferInitOnDemandResources) */ + IMG_UINT32 ui32TracebufFlags; /*!< Compatibility and other flags */ } UNCACHED_ALIGN RGXFWIF_TRACEBUF; /*! @Brief Firmware system data shared with the Host driver */ @@ -320,6 +332,7 @@ typedef struct RGXFWIF_HWR_STATEFLAGS ui32HWRStateFlags; /*!< Firmware's Current HWR state */ RGXFWIF_HWR_RECOVERYFLAGS aui32HWRRecoveryFlags[RGXFWIF_DM_MAX]; /*!< Each DM's HWR state */ IMG_UINT32 ui32FwSysDataFlags; /*!< Compatibility and other flags */ + IMG_UINT32 ui32McConfig; /*!< Identify whether MC config is P-P or P-S */ } UNCACHED_ALIGN RGXFWIF_SYSDATA; /*! @@ -533,18 +546,13 @@ typedef struct #define RGXFWIF_INICFG_FBCDC_V3_1_EN (IMG_UINT32_C(0x1) << 6) #define RGXFWIF_INICFG_CHECK_MLIST_EN (IMG_UINT32_C(0x1) << 7) #define RGXFWIF_INICFG_DISABLE_CLKGATING_EN (IMG_UINT32_C(0x1) << 8) -#define RGXFWIF_INICFG_POLL_COUNTERS_EN (IMG_UINT32_C(0x1) << 9) -#define RGXFWIF_INICFG_VDM_CTX_STORE_MODE_SHIFT (10) -#define RGXFWIF_INICFG_VDM_CTX_STORE_MODE_INDEX ((IMG_UINT32)RGX_CR_VDM_CONTEXT_STORE_MODE_MODE_INDEX << RGXFWIF_INICFG_VDM_CTX_STORE_MODE_SHIFT) -#define RGXFWIF_INICFG_VDM_CTX_STORE_MODE_INSTANCE ((IMG_UINT32)RGX_CR_VDM_CONTEXT_STORE_MODE_MODE_INSTANCE << RGXFWIF_INICFG_VDM_CTX_STORE_MODE_SHIFT) -#define RGXFWIF_INICFG_VDM_CTX_STORE_MODE_LIST ((IMG_UINT32)RGX_CR_VDM_CONTEXT_STORE_MODE_MODE_LIST << RGXFWIF_INICFG_VDM_CTX_STORE_MODE_SHIFT) -#define RGXFWIF_INICFG_VDM_CTX_STORE_MODE_MASK (RGXFWIF_INICFG_VDM_CTX_STORE_MODE_INDEX |\ - RGXFWIF_INICFG_VDM_CTX_STORE_MODE_INSTANCE |\ - RGXFWIF_INICFG_VDM_CTX_STORE_MODE_LIST) +/* 9 unused */ +/* 10 unused */ +/* 11 unused */ #define RGXFWIF_INICFG_REGCONFIG_EN (IMG_UINT32_C(0x1) << 12) #define RGXFWIF_INICFG_ASSERT_ON_OUTOFMEMORY (IMG_UINT32_C(0x1) << 13) #define RGXFWIF_INICFG_HWP_DISABLE_FILTER (IMG_UINT32_C(0x1) << 14) -#define RGXFWIF_INICFG_CUSTOM_PERF_TIMER_EN (IMG_UINT32_C(0x1) << 15) +/* 15 unused */ #define RGXFWIF_INICFG_CTXSWITCH_PROFILE_SHIFT (16) #define RGXFWIF_INICFG_CTXSWITCH_PROFILE_FAST (RGXFWIF_CTXSWITCH_PROFILE_FAST_EN << RGXFWIF_INICFG_CTXSWITCH_PROFILE_SHIFT) #define RGXFWIF_INICFG_CTXSWITCH_PROFILE_MEDIUM (RGXFWIF_CTXSWITCH_PROFILE_MEDIUM_EN << RGXFWIF_INICFG_CTXSWITCH_PROFILE_SHIFT) @@ -575,7 +583,12 @@ typedef struct /* Extended Flag definitions affecting the firmware globally */ #define RGXFWIF_INICFG_EXT_TFBC_CONTROL_SHIFT (0) -#define RGXFWIF_INICFG_EXT_TFBC_CONTROL_MASK (IMG_UINT32_C(0x7F)) /* RGX_CR_TFBC_COMPRESSION_CONTROL_MASKFULL */ +/* [7] YUV10 override + * [6:4] Quality + * [3] Quality enable + * [2:1] Compression scheme + * [0] Lossy group */ +#define RGXFWIF_INICFG_EXT_TFBC_CONTROL_MASK (IMG_UINT32_C(0xFF)) /* RGX_CR_TFBC_COMPRESSION_CONTROL_MASKFULL */ #define RGXFWIF_INICFG_EXT_ALL (RGXFWIF_INICFG_EXT_TFBC_CONTROL_MASK) #define RGXFWIF_INICFG_SYS_CTXSWITCH_CLRMSK ~(RGXFWIF_INICFG_CTXSWITCH_MODE_RAND | \ @@ -599,7 +612,7 @@ typedef struct #define RGXFWIF_INICFG_OS_LOW_PRIO_CS_3D (IMG_UINT32_C(0x1) << 6) #define RGXFWIF_INICFG_OS_LOW_PRIO_CS_CDM (IMG_UINT32_C(0x1) << 7) -#define RGXFWIF_INICFG_OS_ALL (0xFF) +#define RGXFWIF_INICFG_OS_ALL (0xFFU) #define RGXFWIF_INICFG_OS_CTXSWITCH_DM_ALL (RGXFWIF_INICFG_OS_CTXSWITCH_GEOM_EN | \ RGXFWIF_INICFG_OS_CTXSWITCH_3D_EN | \ @@ -617,12 +630,10 @@ typedef struct #define RGXFWIF_FILTCFG_TRUNCATE_INT (IMG_UINT32_C(0x1) << 2) #define RGXFWIF_FILTCFG_NEW_FILTER_MODE (IMG_UINT32_C(0x1) << 1) -typedef enum -{ - RGX_ACTIVEPM_FORCE_OFF = 0, - RGX_ACTIVEPM_FORCE_ON = 1, - RGX_ACTIVEPM_DEFAULT = 2 -} RGX_ACTIVEPM_CONF; +typedef IMG_UINT32 RGX_ACTIVEPM_CONF; +#define RGX_ACTIVEPM_FORCE_OFF 0U +#define RGX_ACTIVEPM_FORCE_ON 1U +#define RGX_ACTIVEPM_DEFAULT 2U typedef enum { @@ -675,6 +686,7 @@ typedef RGXFWIF_DEV_VIRTADDR PRGXFWIF_GPU_UTIL_FWCB; typedef RGXFWIF_DEV_VIRTADDR PRGXFWIF_REG_CFG; typedef RGXFWIF_DEV_VIRTADDR PRGXFWIF_HWPERF_CTL; typedef RGXFWIF_DEV_VIRTADDR PRGX_HWPERF_CONFIG_MUX_CNTBLK; +typedef RGXFWIF_DEV_VIRTADDR PRGX_HWPERF_CONFIG_CNTBLK; typedef RGXFWIF_DEV_VIRTADDR PRGX_HWPERF_SELECT_CUSTOM_CNTRS; typedef RGXFWIF_DEV_VIRTADDR PRGXFWIF_CCB_CTL; typedef RGXFWIF_DEV_VIRTADDR PRGXFWIF_CCB; @@ -701,7 +713,7 @@ typedef RGXFWIF_DEV_VIRTADDR PRGXFWIF_RF_CMD; /*! * This number is used to represent unallocated page catalog base register */ -#define RGXFW_BIF_INVALID_PCREG 0xFFFFFFFFU +#define RGXFW_BIF_INVALID_PCSET 0xFFFFFFFFU /*! Firmware memory context. @@ -709,7 +721,7 @@ typedef RGXFWIF_DEV_VIRTADDR PRGXFWIF_RF_CMD; typedef struct { IMG_DEV_PHYADDR RGXFW_ALIGN sPCDevPAddr; /*!< device physical address of context's page catalogue */ - IMG_UINT32 uiPageCatBaseRegID; /*!< associated page catalog base register (RGXFW_BIF_INVALID_PCREG == unallocated) */ + IMG_UINT32 uiPageCatBaseRegSet; /*!< associated page catalog base register (RGXFW_BIF_INVALID_PCSET == unallocated) */ IMG_UINT32 uiBreakpointAddr; /*!< breakpoint address */ IMG_UINT32 uiBPHandlerAddr; /*!< breakpoint handler address */ IMG_UINT32 uiBreakpointCtl; /*!< DM and enable control for BP */ @@ -728,6 +740,7 @@ typedef struct #define RGXFWIF_CONTEXT_FLAGS_NEED_RESUME (0x00000001U) #define RGXFWIF_CONTEXT_FLAGS_MC_NEED_RESUME_MASKFULL (0x000000FFU) #define RGXFWIF_CONTEXT_FLAGS_TDM_HEADER_STALE (0x00000100U) +#define RGXFWIF_CONTEXT_FLAGS_LAST_KICK_SECURE (0x00000200U) /*! * @InGroup ContextSwitching @@ -738,11 +751,14 @@ typedef struct /* FW-accessible TA state which must be written out to memory on context store */ IMG_UINT64 RGXFW_ALIGN uTAReg_VDM_CALL_STACK_POINTER; /*!< VDM control stream stack pointer, to store in mid-TA */ IMG_UINT64 RGXFW_ALIGN uTAReg_VDM_CALL_STACK_POINTER_Init; /*!< Initial value of VDM control stream stack pointer (in case is 'lost' due to a lock-up) */ - IMG_UINT64 RGXFW_ALIGN uTAReg_VBS_SO_PRIM0; - IMG_UINT64 RGXFW_ALIGN uTAReg_VBS_SO_PRIM1; - IMG_UINT64 RGXFW_ALIGN uTAReg_VBS_SO_PRIM2; - IMG_UINT64 RGXFW_ALIGN uTAReg_VBS_SO_PRIM3; + IMG_UINT32 uTAReg_VBS_SO_PRIM[4]; IMG_UINT16 ui16TACurrentIdx; +} UNCACHED_ALIGN RGXFWIF_TACTX_STATE_PER_GEOM; + +typedef struct +{ + /* FW-accessible TA state which must be written out to memory on context store */ + RGXFWIF_TACTX_STATE_PER_GEOM asGeomCore[RGX_NUM_GEOM_CORES]; } UNCACHED_ALIGN RGXFWIF_TACTX_STATE; /*! @@ -761,7 +777,7 @@ typedef struct IMG_UINT32 au3DReg_ISP_STORE[]; /*!< ISP state (per-pipe) */ } UNCACHED_ALIGN RGXFWIF_3DCTX_STATE; -static_assert(sizeof(RGXFWIF_3DCTX_STATE) <= 16, +static_assert(sizeof(RGXFWIF_3DCTX_STATE) <= 16U, "Size of structure RGXFWIF_3DCTX_STATE exceeds maximum expected size."); #define RGXFWIF_CTX_USING_BUFFER_A (0) @@ -788,7 +804,7 @@ typedef struct RGXFWIF_FWCOMMONCONTEXT_ /* Flags e.g. for context switching */ IMG_UINT32 ui32FWComCtxFlags; - IMG_UINT32 ui32Priority; /*!< Priority level */ + IMG_INT32 i32Priority; /*!< Priority level */ IMG_UINT32 ui32PrioritySeqNum; /* Framework state */ @@ -823,7 +839,7 @@ typedef struct RGXFWIF_FWCOMMONCONTEXT_ } UNCACHED_ALIGN RGXFWIF_FWCOMMONCONTEXT; -static_assert(sizeof(RGXFWIF_FWCOMMONCONTEXT) <= 256, +static_assert(sizeof(RGXFWIF_FWCOMMONCONTEXT) <= 256U, "Size of structure RGXFWIF_FWCOMMONCONTEXT exceeds maximum expected size."); typedef IMG_UINT64 RGXFWIF_TRP_CHECKSUM_TQ[RGX_TRP_MAX_NUM_CORES][1]; @@ -846,6 +862,10 @@ typedef struct IMG_UINT32 ui32FwRenderCtxFlags; /*!< Compatibility and other flags */ +#if defined(SUPPORT_TRP) + RGXFWIF_TRP_CHECKSUM_3D aui64TRPChecksums3D; + RGXFWIF_TRP_CHECKSUM_GEOM aui64TRPChecksumsGeom; +#endif } UNCACHED_ALIGN RGXFWIF_FWRENDERCONTEXT; /*! @@ -935,7 +955,11 @@ typedef struct #if !defined(RGX_FEATURE_SLC_VIVT) #define RGXFWIF_MMUCACHEDATA_FLAGS_PMTLB (0x10U) /* can't use PM_TLB0 bit from BIFPM_CTRL reg because it collides with PT bit from BIF_CTRL reg */ +#if !defined(RGX_FEATURE_XE_ARCHITECTURE) || (RGX_FEATURE_XE_ARCHITECTURE < 2) #define RGXFWIF_MMUCACHEDATA_FLAGS_TLB (RGXFWIF_MMUCACHEDATA_FLAGS_PMTLB | 0x8U) /* BIF_CTRL_INVAL_TLB1_EN */ +#else +#define RGXFWIF_MMUCACHEDATA_FLAGS_TLB (RGXFWIF_MMUCACHEDATA_FLAGS_PMTLB) +#endif #define RGXFWIF_MMUCACHEDATA_FLAGS_CTX_ALL (0x0U) /* not used */ #else /* RGX_FEATURE_SLC_VIVT */ @@ -1106,6 +1130,12 @@ typedef struct PRGX_HWPERF_CONFIG_MUX_CNTBLK sBlockConfigs; /*!< Address of the RGX_HWPERF_CONFIG_MUX_CNTBLK array */ } RGXFWIF_HWPERF_CONFIG_ENABLE_BLKS; +typedef struct +{ + IMG_UINT32 ui32NumBlocks; /*!< Number of RGX_HWPERF_CONFIG_CNTBLK in the array */ + PRGX_HWPERF_CONFIG_CNTBLK sBlockConfigs; /*!< Address of the RGX_HWPERF_CONFIG_CNTBLK array */ +} RGXFWIF_HWPERF_CONFIG_DA_BLKS; + /*! * @Brief Command data for \ref RGXFWIF_KCCB_CMD_CORECLKSPEEDCHANGE type command */ @@ -1151,6 +1181,13 @@ typedef struct IMG_UINT32 ui32RegAddr; IMG_UINT64 RGXFW_ALIGN ui64RegVal; } RGXFWIF_RGXREG_DATA; + +typedef struct +{ + IMG_UINT64 ui64BaseAddress; + PRGXFWIF_FWCOMMONCONTEXT psContext; + IMG_UINT32 ui32Size; +} RGXFWIF_GPUMAP_DATA; #endif /*! @@ -1340,6 +1377,10 @@ typedef enum RGXFWIF_KCCB_CMD_COUNTER_DUMP = 216U | RGX_CMD_MAGIC_DWORD_SHIFTED, /*!< Controls counter dumping in the FW */ RGXFWIF_KCCB_CMD_HWPERF_CONFIG_ENABLE_BLKS = 217U | RGX_CMD_MAGIC_DWORD_SHIFTED, /*!< Configure, clear and enable multiple HWPerf blocks */ RGXFWIF_KCCB_CMD_HWPERF_SELECT_CUSTOM_CNTRS = 218U | RGX_CMD_MAGIC_DWORD_SHIFTED, /*!< Configure the custom counters for HWPerf */ +#if defined(SUPPORT_VALIDATION) + RGXFWIF_KCCB_CMD_GPUMAP = 219U | RGX_CMD_MAGIC_DWORD_SHIFTED, /*!< Request a FW GPU mapping which is written into by the FW with a pattern */ +#endif + RGXFWIF_KCCB_CMD_HWPERF_CONFIG_BLKS = 220U | RGX_CMD_MAGIC_DWORD_SHIFTED, /*!< Configure directly addressable counters for HWPerf */ } RGXFWIF_KCCB_CMD_TYPE; #define RGXFWIF_LAST_ALLOWED_GUEST_KCCB_CMD (RGXFWIF_KCCB_CMD_REGCONFIG - 1) @@ -1366,7 +1407,8 @@ typedef struct RGXFWIF_HWPERF_CTRL sHWPerfCtrl; /*!< Data for HWPerf control command */ RGXFWIF_HWPERF_CONFIG_ENABLE_BLKS sHWPerfCfgEnableBlks; /*!< Data for HWPerf configure, clear and enable performance counter block command */ RGXFWIF_HWPERF_CTRL_BLKS sHWPerfCtrlBlks; /*!< Data for HWPerf enable or disable performance counter block commands */ - RGXFWIF_HWPERF_SELECT_CUSTOM_CNTRS sHWPerfSelectCstmCntrs; /*!< Data for HWPerf configure the custom counters to read */ + RGXFWIF_HWPERF_SELECT_CUSTOM_CNTRS sHWPerfSelectCstmCntrs; /*!< Data for HWPerf configure the custom counters to read */ + RGXFWIF_HWPERF_CONFIG_DA_BLKS sHWPerfCfgDABlks; /*!< Data for HWPerf configure Directly Addressable blocks */ RGXFWIF_CORECLKSPEEDCHANGE_DATA sCoreClkSpeedChangeData;/*!< Data for core clock speed change */ RGXFWIF_ZSBUFFER_BACKING_DATA sZSBufferBackingData; /*!< Feedback for Z/S Buffer backing/unbacking */ RGXFWIF_FREELIST_GS_DATA sFreeListGSData; /*!< Feedback for Freelist grow/shrink */ @@ -1381,6 +1423,7 @@ typedef struct RGXFWIF_KCCB_CMD_FORCE_UPDATE_DATA sForceUpdateData; /*!< Data for signalling all unmet fences for a given CCB */ #if defined(SUPPORT_VALIDATION) RGXFWIF_RGXREG_DATA sFwRgxData; /*!< Data for reading off an RGX register */ + RGXFWIF_GPUMAP_DATA sGPUMapData; /*!< Data for requesting a FW GPU mapping which is written into by the FW with a pattern */ #endif } UNCACHED_ALIGN uCmdData; } UNCACHED_ALIGN RGXFWIF_KCCB_CMD; @@ -1664,7 +1707,7 @@ typedef struct /*! @Brief Command data for \ref RGXFWIF_CCB_CMD_TYPE_PRIORITY type client CCB command */ typedef struct { - IMG_UINT32 ui32Priority; /*!< Priority level */ + IMG_INT32 i32Priority; /*!< Priority level */ } RGXFWIF_CMD_PRIORITY; /*! @} End of ClientCCBTypes */ @@ -1721,7 +1764,7 @@ typedef struct do { \ (name).ui32LayoutVersion = RGXFWIF_COMPCHECKS_LAYOUT_VERSION; \ (name).ui64BVNC = 0; \ - } while (0) + } while (false) typedef struct { @@ -1831,8 +1874,6 @@ typedef enum FW_PERF_CONF_NONE = 0, FW_PERF_CONF_ICACHE = 1, FW_PERF_CONF_DCACHE = 2, - FW_PERF_CONF_POLLS = 3, - FW_PERF_CONF_CUSTOM_TIMER = 4, FW_PERF_CONF_JTLB_INSTR = 5, FW_PERF_CONF_INSTRUCTIONS = 6 } FW_PERF_CONF; @@ -1915,6 +1956,9 @@ typedef struct IMG_DEV_VIRTADDR RGXFW_ALIGN sPDSExecBase; /*!< PDS execution base */ IMG_DEV_VIRTADDR RGXFW_ALIGN sUSCExecBase; /*!< USC execution base */ + IMG_DEV_VIRTADDR RGXFW_ALIGN sFBCDCStateTableBase; /*!< FBCDC bindless texture state table base */ + IMG_DEV_VIRTADDR RGXFW_ALIGN sFBCDCLargeStateTableBase; + IMG_DEV_VIRTADDR RGXFW_ALIGN sTextureHeapBase; /*!< Texture state base */ IMG_UINT64 RGXFW_ALIGN ui64HWPerfFilter; /*! Event filter for Firmware events */ @@ -2002,10 +2046,11 @@ typedef struct /* Value to write into RGX_CR_TFBC_COMPRESSION_CONTROL */ IMG_UINT32 ui32TFBCCompressionControl; -} UNCACHED_ALIGN RGXFWIF_SYSINIT; +#if defined(SUPPORT_AUTOVZ) + IMG_UINT32 ui32VzWdgPeriod; +#endif -static_assert(sizeof(RGXFWIF_SYSINIT) <= 792, - "Size of structure RGXFW_SYSINIT exceeds maximum expected size."); +} UNCACHED_ALIGN RGXFWIF_SYSINIT; #if defined(SUPPORT_GPUVIRT_VALIDATION) #define RGXFWIF_KICK_TEST_ENABLED_BIT 0x1 @@ -2134,67 +2179,33 @@ typedef struct IMG_UINT32 ui32RTACtlFlags; /* Compatibility and other flags */ } UNCACHED_ALIGN RGXFWIF_RTA_CTL; -/*! @Brief Firmware Freelist holding usage state of the Parameter Buffers */ +/*! + * @InGroup RenderTarget + * @Brief Firmware Freelist holding usage state of the Parameter Buffers + */ typedef struct { - IMG_DEV_VIRTADDR RGXFW_ALIGN psFreeListDevVAddr; - IMG_UINT64 RGXFW_ALIGN ui64CurrentDevVAddr; - IMG_UINT32 ui32CurrentStackTop; - IMG_UINT32 ui32MaxPages; - IMG_UINT32 ui32GrowPages; - IMG_UINT32 ui32CurrentPages; /* HW pages */ - IMG_UINT32 ui32AllocatedPageCount; - IMG_UINT32 ui32AllocatedMMUPageCount; + IMG_DEV_VIRTADDR RGXFW_ALIGN psFreeListDevVAddr; /*!< Freelist page table base */ + IMG_UINT64 RGXFW_ALIGN ui64CurrentDevVAddr;/*!< Freelist page table entry for current free page */ + IMG_UINT32 ui32CurrentStackTop; /*!< Freelist current free page */ + IMG_UINT32 ui32MaxPages; /*!< Max no. of pages can be added to the freelist */ + IMG_UINT32 ui32GrowPages; /*!< No pages to add in each freelist grow */ + IMG_UINT32 ui32CurrentPages; /*!< Total no. of pages made available to the PM HW */ + IMG_UINT32 ui32AllocatedPageCount; /*!< No. of pages allocated by PM HW */ + IMG_UINT32 ui32AllocatedMMUPageCount; /*!< No. of pages allocated for GPU MMU for PM*/ #if defined(SUPPORT_SHADOW_FREELISTS) - IMG_UINT32 ui32HWRCounter; + IMG_UINT32 ui32HWRCounter; PRGXFWIF_FWMEMCONTEXT psFWMemContext; #endif - IMG_UINT32 ui32FreeListID; - IMG_BOOL bGrowPending; - IMG_UINT32 ui32ReadyPages; /* Pages that should be used only when OOM is reached */ - IMG_UINT32 ui32FreelistFlags; /* Compatibility and other flags */ + IMG_UINT32 ui32FreeListID; /*!< Unique Freelist ID */ + IMG_BOOL bGrowPending; /*!< Freelist grow is pending */ + IMG_UINT32 ui32ReadyPages; /*!< Reserved pages to be used only on PM OOM event */ + IMG_UINT32 ui32FreelistFlags; /*!< Compatibility and other flags */ +#if defined(SUPPORT_AGP) + IMG_UINT32 ui32PmGlobalPb; /*!< PM Global PB on which Freelist is loaded */ +#endif } UNCACHED_ALIGN RGXFWIF_FREELIST; -/*! - ****************************************************************************** - * Parameter Management (PM) control data for RGX - *****************************************************************************/ - -/* Used only by Firmware but defined here for similarity with Volcanic where it's required for SW TRP */ - -typedef enum -{ - RGXFW_SPM_STATE_NONE = 0, - RGXFW_SPM_STATE_PR_BLOCKED, - RGXFW_SPM_STATE_WAIT_FOR_GROW, - RGXFW_SPM_STATE_WAIT_FOR_HW, - RGXFW_SPM_STATE_PR_RUNNING, - RGXFW_SPM_STATE_PR_AVOIDED, - RGXFW_SPM_STATE_PR_EXECUTED, -} RGXFW_SPM_STATE; - -/*! - ****************************************************************************** - * @Brief RGX firmware SPM Control Data: - * This structure holds all the internal SPM control Data of the firmware. - *****************************************************************************/ -typedef struct -{ - RGXFW_SPM_STATE eSPMState; /*!< Current state of TA OOM event */ - RGXFWIF_UFO sPartialRenderTA3DFence; /*!< TA/3D fence object holding the value to let through the 3D partial command */ -#if defined(RGX_FIRMWARE) - RGXFWIF_FWCOMMONCONTEXT *ps3dContext; /*!< Pointer to the 3D Context holding the partial render */ - RGXFWIF_PRBUFFER *apsPRBuffer[RGXFWIF_PRBUFFER_MAXSUPPORTED]; /*!< Array of pointers to PR Buffers which may be used if partial render is needed */ -#else - RGXFWIF_DEV_VIRTADDR ps3dContext; /*!< Pointer to the 3D Context holding the partial render */ - RGXFWIF_DEV_VIRTADDR apsPRBuffer[RGXFWIF_PRBUFFER_MAXSUPPORTED]; /*!< Array of pointers to PR Buffers which may be used if partial render is needed */ -#endif - IMG_UINT32 ui32CmdOffset; /*!< CCCB offset of the command holding the partial render */ - bool b3DMemFreeDetected; /*!< Indicates if a 3D Memory Free has been detected, which resolves OOM */ -} RGXFW_ALIGN_DCACHEL RGXFW_SPMCTL; - -static_assert(sizeof(RGXFW_SPMCTL) <= 64, - "Size of structure RGXFW_SPMCTL exceeds maximum expected size."); /*! ****************************************************************************** * HWRTData @@ -2202,12 +2213,19 @@ static_assert(sizeof(RGXFW_SPMCTL) <= 64, /* HWRTData flags */ /* Deprecated flags 1:0 */ -#define HWRTDATA_HAS_LAST_TA (1U << 2) -#define HWRTDATA_PARTIAL_RENDERED (1U << 3) -#define HWRTDATA_DISABLE_TILE_REORDERING (1U << 4) -#define HWRTDATA_NEED_BRN65101_BLIT (1U << 5) -#define HWRTDATA_FIRST_BRN65101_STRIP (1U << 6) -#define HWRTDATA_NEED_BRN67182_2ND_RENDER (1U << 7) +#define HWRTDATA_HAS_LAST_TA (1UL << 2) +#define HWRTDATA_PARTIAL_RENDERED (1UL << 3) +#define HWRTDATA_DISABLE_TILE_REORDERING (1UL << 4) +#define HWRTDATA_NEED_BRN65101_BLIT (1UL << 5) +#define HWRTDATA_FIRST_BRN65101_STRIP (1UL << 6) +#define HWRTDATA_NEED_BRN67182_2ND_RENDER (1UL << 7) +#if defined(SUPPORT_AGP) +#define HWRTDATA_GLOBAL_PB_NUMBER_BIT0 (1UL << 8) +#if defined(SUPPORT_AGP4) +#define HWRTDATA_GLOBAL_PB_NUMBER_BIT1 (1UL << 9) +#endif +#define HWRTDATA_GEOM_NEEDS_RESUME (1UL << 10) +#endif typedef enum { @@ -2251,51 +2269,55 @@ typedef struct IMG_UINT32 ui32ISPMtileSize; } UNCACHED_ALIGN RGXFWIF_HWRTDATA_COMMON; -/*! @Brief Firmware Render Target data i.e. HWRTDATA used to hold the PM context */ +/*! + * @InGroup RenderTarget + * @Brief Firmware Render Target data i.e. HWRTDATA used to hold the PM context + */ typedef struct { - IMG_DEV_VIRTADDR RGXFW_ALIGN psPMMListDevVAddr; /*!< MList Data Store */ + IMG_DEV_VIRTADDR RGXFW_ALIGN psPMMListDevVAddr; /*!< MList Data Store */ - IMG_UINT64 RGXFW_ALIGN ui64VCECatBase[4]; - IMG_UINT64 RGXFW_ALIGN ui64VCELastCatBase[4]; - IMG_UINT64 RGXFW_ALIGN ui64TECatBase[4]; - IMG_UINT64 RGXFW_ALIGN ui64TELastCatBase[4]; - IMG_UINT64 RGXFW_ALIGN ui64AlistCatBase; - IMG_UINT64 RGXFW_ALIGN ui64AlistLastCatBase; + IMG_UINT64 RGXFW_ALIGN ui64VCECatBase[4]; /*!< VCE Page Catalogue base */ + IMG_UINT64 RGXFW_ALIGN ui64VCELastCatBase[4]; + IMG_UINT64 RGXFW_ALIGN ui64TECatBase[4]; /*!< TE Page Catalogue base */ + IMG_UINT64 RGXFW_ALIGN ui64TELastCatBase[4]; + IMG_UINT64 RGXFW_ALIGN ui64AlistCatBase; /*!< Alist Page Catalogue base */ + IMG_UINT64 RGXFW_ALIGN ui64AlistLastCatBase; - IMG_UINT64 RGXFW_ALIGN ui64PMAListStackPointer; - IMG_UINT32 ui32PMMListStackPointer; + IMG_UINT64 RGXFW_ALIGN ui64PMAListStackPointer; /*!< Freelist page table entry for current Mlist page */ + IMG_UINT32 ui32PMMListStackPointer; /*!< Current Mlist page */ - RGXFWIF_DEV_VIRTADDR sHWRTDataCommonFwAddr; + RGXFWIF_DEV_VIRTADDR sHWRTDataCommonFwAddr; /*!< Render target dimension dependent data */ - IMG_UINT32 ui32HWRTDataFlags; - RGXFWIF_RTDATA_STATE eState; + IMG_UINT32 ui32HWRTDataFlags; + RGXFWIF_RTDATA_STATE eState; /*!< Current workload processing state of HWRTDATA */ - PRGXFWIF_FREELIST RGXFW_ALIGN apsFreeLists[RGXFW_MAX_FREELISTS]; - IMG_UINT32 aui32FreeListHWRSnapshot[RGXFW_MAX_FREELISTS]; + PRGXFWIF_FREELIST RGXFW_ALIGN apsFreeLists[RGXFW_MAX_FREELISTS]; /*!< Freelist to use */ + IMG_UINT32 aui32FreeListHWRSnapshot[RGXFW_MAX_FREELISTS]; - IMG_DEV_VIRTADDR RGXFW_ALIGN psVHeapTableDevVAddr; + IMG_DEV_VIRTADDR RGXFW_ALIGN psVHeapTableDevVAddr; /*!< VHeap table base */ - RGXFWIF_CLEANUP_CTL sCleanupState; + RGXFWIF_CLEANUP_CTL sCleanupState; /*!< Render target clean up state */ - RGXFWIF_RTA_CTL sRTACtl; + RGXFWIF_RTA_CTL sRTACtl; /*!< Render target array data */ - IMG_DEV_VIRTADDR RGXFW_ALIGN sTailPtrsDevVAddr; - IMG_DEV_VIRTADDR RGXFW_ALIGN sMacrotileArrayDevVAddr; - IMG_DEV_VIRTADDR RGXFW_ALIGN sRgnHeaderDevVAddr; - IMG_DEV_VIRTADDR RGXFW_ALIGN sRTCDevVAddr; + IMG_DEV_VIRTADDR RGXFW_ALIGN sTailPtrsDevVAddr; /*!< Tail pointers base */ + IMG_DEV_VIRTADDR RGXFW_ALIGN sMacrotileArrayDevVAddr; /*!< Macrotiling array base */ + IMG_DEV_VIRTADDR RGXFW_ALIGN sRgnHeaderDevVAddr; /*!< Region headers base */ + IMG_DEV_VIRTADDR RGXFW_ALIGN sRTCDevVAddr; /*!< Render target cache base */ #if defined(RGX_FIRMWARE) - struct RGXFWIF_FWCOMMONCONTEXT_* RGXFW_ALIGN psOwnerGeom; + struct RGXFWIF_FWCOMMONCONTEXT_* RGXFW_ALIGN psOwnerGeom; #else - RGXFWIF_DEV_VIRTADDR RGXFW_ALIGN pui32OwnerGeomNotUsedByHost; + RGXFWIF_DEV_VIRTADDR RGXFW_ALIGN pui32OwnerGeomNotUsedByHost; #endif #if defined(SUPPORT_TRP) - IMG_UINT32 ui32KickFlagsCopy; - IMG_UINT32 ui32TRPState; - RGXFWIF_TRP_CHECKSUM_3D aui64TRPChecksums3D; - RGXFWIF_TRP_CHECKSUM_GEOM aui64TRPChecksumsGeom; - IMG_UINT32 ui32TEPageCopy; - IMG_UINT32 ui32VCEPageCopy; + IMG_UINT32 ui32KickFlagsCopy; + IMG_UINT32 ui32TRPState; + IMG_UINT32 ui32TEPageCopy; + IMG_UINT32 ui32VCEPageCopy; +#endif +#if defined(SUPPORT_AGP) + IMG_BOOL bTACachesNeedZeroing; #endif } UNCACHED_ALIGN RGXFWIF_HWRTDATA; diff --git a/drivers/gpu/drm/img-rogue/rgx_fwif_resetframework.h b/drivers/gpu/drm/img-rogue/rgx_fwif_resetframework.h index 84575635f..e60bafd84 100644 --- a/drivers/gpu/drm/img-rogue/rgx_fwif_resetframework.h +++ b/drivers/gpu/drm/img-rogue/rgx_fwif_resetframework.h @@ -48,21 +48,17 @@ CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. typedef struct { -#if defined(RGX_FEATURE_CDM_USER_MODE_QUEUE) - IMG_UINT64 uCDMReg_CDM_CB_QUEUE; - IMG_UINT64 uCDMReg_CDM_CB_BASE; - IMG_UINT64 uCDMReg_CDM_CB; -#else - IMG_UINT64 uCDMReg_CDM_CTRL_STREAM_BASE; -#endif + union + { + IMG_UINT64 uCDMReg_CDM_CB_BASE; // defined(RGX_FEATURE_CDM_USER_MODE_QUEUE) + IMG_UINT64 uCDMReg_CDM_CTRL_STREAM_BASE; // !defined(RGX_FEATURE_CDM_USER_MODE_QUEUE) + }; + IMG_UINT64 uCDMReg_CDM_CB_QUEUE; // !defined(RGX_FEATURE_CDM_USER_MODE_QUEUE) + IMG_UINT64 uCDMReg_CDM_CB; // !defined(RGX_FEATURE_CDM_USER_MODE_QUEUE) } RGXFWIF_RF_REGISTERS; -#define RGXFWIF_RF_FLAG_ENABLE 0x00000001U /*!< enables the reset framework in the firmware */ - typedef struct { - IMG_UINT32 ui32Flags; - /* THIS MUST BE THE LAST MEMBER OF THE CONTAINING STRUCTURE */ RGXFWIF_RF_REGISTERS RGXFW_ALIGN sFWRegisters; diff --git a/drivers/gpu/drm/img-rogue/rgx_fwif_sf.h b/drivers/gpu/drm/img-rogue/rgx_fwif_sf.h index 9cb64d898..9238cf8ca 100644 --- a/drivers/gpu/drm/img-rogue/rgx_fwif_sf.h +++ b/drivers/gpu/drm/img-rogue/rgx_fwif_sf.h @@ -71,6 +71,10 @@ CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. X(RGXFW_GROUP_DMA,DMA) \ X(RGXFW_GROUP_DBG,DBG) +/*! + * @InGroup SRVAndFWTracing + * @Brief FW Trace log groups(GID) list + */ enum RGXFW_LOG_SFGROUPS { #define X(A,B) A, RGXFW_LOG_SFGROUPLIST @@ -284,7 +288,7 @@ X(181, RGXFW_GROUP_MAIN, RGXFW_SF_MAIN_SIGNAL_UPDATE, "Signal update, Snoop Filt X(182, RGXFW_GROUP_MAIN, RGXFW_SF_MAIN_DEV_SERIES8_DEPRECATED, "WARNING: Skipping FW KCCB Cmd type %d which is not yet supported on Series8.", 1) \ X(183, RGXFW_GROUP_MAIN, RGXFW_SF_MAIN_INCONSISTENT_MMU_FLAGS, "MMU context cache data NULL, but cache flags=0x%x (sync counter=%u, update value=%u) OSId=%u", 4) \ X(184, RGXFW_GROUP_MAIN, RGXFW_SF_MAIN_SLC_FLUSH, "SLC range based flush: Context=%u VAddr=0x%02x%08x, Size=0x%08x, Invalidate=%d", 5) \ -X(185, RGXFW_GROUP_MAIN, RGXFW_SF_MAIN_FBSC_INVAL, "FBSC invalidate for Context [0x%08x]: Entry mask 0x%08x%08x.", 3) \ +X(185, RGXFW_GROUP_MAIN, RGXFW_SF_MAIN_FBSC_INVAL, "FBSC invalidate for Context Set [0x%08x]: Entry mask 0x%08x%08x.", 3) \ X(186, RGXFW_GROUP_MAIN, RGXFW_SF_MAIN_TDM_BRN66284_UPDATE, "TDM context switch check: Roff %u was not valid for kick starting at %u, moving back to %u", 3) \ X(187, RGXFW_GROUP_MAIN, RGXFW_SF_MAIN_SPFILTER_UPDATES, "Signal updates: FIFO: %u, Signals: 0x%08x", 2) \ X(188, RGXFW_GROUP_MAIN, RGXFW_SF_MAIN_INVALID_FBSC_CMD, "Invalid FBSC cmd: FWCtx 0x%08x, MemCtx 0x%08x", 2) \ @@ -318,8 +322,8 @@ X(215, RGXFW_GROUP_MAIN, RGXFW_SF_MAIN_USC_TASKS_RANGE, "DM%d USC tasks range li X(216, RGXFW_GROUP_MAIN, RGXFW_SF_MAIN_GPU_ECC_FAULT, "ECC fault GPU=0x%08x", 1) \ X(217, RGXFW_GROUP_MAIN, RGXFW_SF_MAIN_GPU_SAFETY_RESET, "GPU Hardware units reset to prevent transient faults.", 0) \ X(218, RGXFW_GROUP_MAIN, RGXFW_SF_MAIN_ABORTCMD, "Kick Abort cmd: FWCtx 0x%08.8x @ %d", 2) \ -X(219, RGXFW_GROUP_MAIN, RGXFW_SF_MAIN_KICK_RAY, "Kick Ray: FWCtx 0x%08.8x @ %d. (PID:%d, prio:%d, frame:%d, ext:0x%08x, int:0x%08x)", 7)\ -X(220, RGXFW_GROUP_MAIN, RGXFW_SF_MAIN_RAY_FINISHED, "Ray finished", 0) \ +X(219, RGXFW_GROUP_MAIN, RGXFW_SF_MAIN_KICK_RAY_DEPRECATED, "Kick Ray: FWCtx 0x%08.8x @ %d. (PID:%d, prio:%d, frame:%d, ext:0x%08x, int:0x%08x)", 7)\ +X(220, RGXFW_GROUP_MAIN, RGXFW_SF_MAIN_RAY_FINISHED_DEPRECATED, "Ray finished", 0) \ X(221, RGXFW_GROUP_MAIN, RGXFW_SF_MAIN_FWDATA_INIT_STATUS, "State of firmware's private data at boot time: %d (0 = uninitialised, 1 = initialised); Fw State Flags = 0x%08X", 2) \ X(222, RGXFW_GROUP_MAIN, RGXFW_SF_MAIN_CFI_TIMEOUT, "CFI Timeout detected (%d increasing to %d)", 2) \ X(223, RGXFW_GROUP_MAIN, RGXFW_SF_MAIN_CFI_TIMEOUT_FBM, "CFI Timeout detected for FBM (%d increasing to %d)", 2) \ @@ -327,6 +331,17 @@ X(224, RGXFW_GROUP_MAIN, RGXFW_SF_MAIN_GEOM_OOM_DISALLOWED, "Geom OOM event not X(225, RGXFW_GROUP_MAIN, RGXFW_SF_MAIN_OS_PRIORITY_CHANGE, "Changing OSid %d's priority from %u to %u; Isolation = %u (0 = off; 1 = on)", 4) \ X(226, RGXFW_GROUP_MAIN, RGXFW_SF_MAIN_SKIP_ALREADY_RUN_GEOM, "Skipping already executed TA FWCtx 0x%08.8x @ %d", 2) \ X(227, RGXFW_GROUP_MAIN, RGXFW_SF_MAIN_ATTEMPT_TO_RUN_AHEAD_GEOM, "Attempt to execute TA FWCtx 0x%08.8x @ %d ahead of time on other GEOM", 2) \ +X(228, RGXFW_GROUP_MAIN, RGXFW_SF_MAIN_KICK_TDM_DEPRECATED2, "Kick TDM: Kick ID %u FWCtx 0x%08.8x @ %d. (PID:%d, prio:%d, frame:%d, ext:0x%08x, int:0x%08x)", 8) \ +X(229, RGXFW_GROUP_MAIN, RGXFW_SF_MAIN_KICK_TA_PIPELINE, "Kick TA: Kick ID %u FWCtx 0x%08.8x @ %d, RTD 0x%08x, First kick:%d, Last kick:%d, CSW resume:%d. (PID:%d, prio:%d, frame:%d, ext:0x%08x, int:0x%08x)", 12) \ +X(230, RGXFW_GROUP_MAIN, RGXFW_SF_MAIN_KICK_3D_PIPELINE, "Kick 3D: Kick ID %u FWCtx 0x%08.8x @ %d, RTD 0x%08x, Partial render:%d, CSW resume:%d. (PID:%d, prio:%d, frame:%d, ext:0x%08x, int:0x%08x)", 11) \ +X(231, RGXFW_GROUP_MAIN, RGXFW_SF_MAIN_KICK_COMPUTE_PIPELINE, "Kick Compute: Kick ID %u FWCtx 0x%08.8x @ %d. (PID:%d, prio:%d, ext:0x%08x, int:0x%08x)", 7) \ +X(232, RGXFW_GROUP_MAIN, RGXFW_SF_MAIN_TDM_FINISHED_PIPELINE, "TDM finished: Kick ID %u ", 1) \ +X(233, RGXFW_GROUP_MAIN, RGXFW_SF_MAIN_TA_FINISHED_PIPELINE, "TA finished: Kick ID %u ", 1) \ +X(234, RGXFW_GROUP_MAIN, RGXFW_SF_MAIN_3D_FINISHED_PIPELINE, "3D finished: Kick ID %u , HWRTData0State=%x, HWRTData1State=%x", 3) \ +X(235, RGXFW_GROUP_MAIN, RGXFW_SF_MAIN_COMPUTE_FINISHED_PIPELINE, "Compute finished: Kick ID %u ", 1) \ +X(236, RGXFW_GROUP_MAIN, RGXFW_SF_MAIN_KICK_TDM_PIPELINE, "Kick TDM: Kick ID %u FWCtx 0x%08.8x @ %d, Base 0x%08x%08x. (PID:%d, prio:%d, frame:%d, ext:0x%08x, int:0x%08x)", 10) \ +X(237, RGXFW_GROUP_MAIN, RGXFW_SF_MAIN_KICK_RAY_PIPELINE, "Kick Ray: Kick ID %u FWCtx 0x%08.8x @ %d. (PID:%d, prio:%d, frame:%d, ext:0x%08x, int:0x%08x)", 8)\ +X(238, RGXFW_GROUP_MAIN, RGXFW_SF_MAIN_RAY_FINISHED_PIPELINE, "Ray finished: Kick ID %u ", 1) \ \ X( 1, RGXFW_GROUP_MTS, RGXFW_SF_MTS_BG_KICK_DEPRECATED, "Bg Task DM = %u, counted = %d", 2) \ X( 2, RGXFW_GROUP_MTS, RGXFW_SF_MTS_BG_COMPLETE_DEPRECATED, "Bg Task complete DM = %u", 1) \ @@ -348,6 +363,7 @@ X( 17, RGXFW_GROUP_MTS, RGXFW_SF_MTS_KCCBCMD_RTN_VALUE, "KCCB Slot %u: Return va X( 18, RGXFW_GROUP_MTS, RGXFW_SF_MTS_BG_KICK, "Bg Task OSid = %u", 1) \ X( 19, RGXFW_GROUP_MTS, RGXFW_SF_MTS_KCCBCMD_EXEC, "KCCB Slot %u: Cmd=0x%08x, OSid=%u", 3) \ X( 20, RGXFW_GROUP_MTS, RGXFW_SF_MTS_IRQ_KICK, "Irq Task (EVENT_STATUS=0x%08x)", 1) \ +X( 21, RGXFW_GROUP_MTS, RGXFW_SF_MTS_VZ_SIDEBAND, "VZ sideband test, kicked with OSid=%u from MTS, OSid for test=%u", 2) \ \ X( 1, RGXFW_GROUP_CLEANUP, RGXFW_SF_CLEANUP_FWCTX_CLEANUP, "FwCommonContext [0x%08x] cleaned", 1) \ X( 2, RGXFW_GROUP_CLEANUP, RGXFW_SF_CLEANUP_FWCTX_BUSY, "FwCommonContext [0x%08x] is busy: ReadOffset = %d, WriteOffset = %d", 3) \ @@ -425,9 +441,9 @@ X( 54, RGXFW_GROUP_CSW, RGXFW_SF_CSW_RDM_RESUME, "RDM FWCtx 0x%08.8x resume", 1) \ X( 1, RGXFW_GROUP_BIF, RGXFW_SF_BIF_ACTIVATE_BIFREQ_DEPRECATED, "Activate MemCtx=0x%08x BIFreq=%d secure=%d", 3) \ X( 2, RGXFW_GROUP_BIF, RGXFW_SF_BIF_DEACTIVATE, "Deactivate MemCtx=0x%08x", 1) \ -X( 3, RGXFW_GROUP_BIF, RGXFW_SF_BIF_PCREG_ALLOC, "Alloc PC reg %d", 1) \ -X( 4, RGXFW_GROUP_BIF, RGXFW_SF_BIF_PCREG_GRAB, "Grab reg %d refcount now %d", 2) \ -X( 5, RGXFW_GROUP_BIF, RGXFW_SF_BIF_PCREG_UNGRAB, "Ungrab reg %d refcount now %d", 2) \ +X( 3, RGXFW_GROUP_BIF, RGXFW_SF_BIF_PCREG_ALLOC_DEPRECATED, "Alloc PC reg %d", 1) \ +X( 4, RGXFW_GROUP_BIF, RGXFW_SF_BIF_PCSET_GRAB, "Grab reg set %d refcount now %d", 2) \ +X( 5, RGXFW_GROUP_BIF, RGXFW_SF_BIF_PCSET_UNGRAB, "Ungrab reg set %d refcount now %d", 2) \ X( 6, RGXFW_GROUP_BIF, RGXFW_SF_BIF_SETUP_REG_BIFREQ_DEPRECATED, "Setup reg=%d BIFreq=%d, expect=0x%08x%08x, actual=0x%08x%08x", 6) \ X( 7, RGXFW_GROUP_BIF, RGXFW_SF_BIF_TRUST_DEPRECATED, "Trust enabled:%d, for BIFreq=%d", 2) \ X( 8, RGXFW_GROUP_BIF, RGXFW_SF_BIF_TILECFG_DEPRECATED, "BIF Tiling Cfg %d base 0x%08x%08x len 0x%08x%08x enable %d stride %d --> 0x%08x%08x", 9) \ @@ -437,10 +453,12 @@ X( 11, RGXFW_GROUP_BIF, RGXFW_SF_BIF_OSIDx, "ui32OSid = %u, Catbase = %u, Reg Ad X( 12, RGXFW_GROUP_BIF, RGXFW_SF_BIF_MAP_GPU_MEMORY_BIFREQ_DEPRECATED, "Map GPU memory DevVAddr 0x%x%08x, Size %u, Context ID %u, BIFREQ %u", 5) \ X( 13, RGXFW_GROUP_BIF, RGXFW_SF_BIF_UNMAP_GPU_MEMORY, "Unmap GPU memory (event status 0x%x)", 1) \ X( 14, RGXFW_GROUP_BIF, RGXFW_SF_BIF_ACTIVATE_DM, "Activate MemCtx=0x%08x DM=%d secure=%d", 3) \ -X( 15, RGXFW_GROUP_BIF, RGXFW_SF_BIF_SETUP_REG_DM, "Setup reg=%d DM=%d, expect=0x%08x%08x, actual=0x%08x%08x", 6) \ +X( 15, RGXFW_GROUP_BIF, RGXFW_SF_BIF_SETUP_REG_DM_DEPRECATED, "Setup reg=%d DM=%d, expect=0x%08x%08x, actual=0x%08x%08x", 6) \ X( 16, RGXFW_GROUP_BIF, RGXFW_SF_BIF_MAP_GPU_MEMORY, "Map GPU memory DevVAddr 0x%x%08x, Size %u, Context ID %u", 4) \ X( 17, RGXFW_GROUP_BIF, RGXFW_SF_BIF_TRUST_DM, "Trust enabled:%d, for DM=%d", 2) \ X( 18, RGXFW_GROUP_BIF, RGXFW_SF_BIF_MAP_GPU_MEMORY_DM, "Map GPU memory DevVAddr 0x%x%08x, Size %u, Context ID %u, DM %u", 5) \ +X( 19, RGXFW_GROUP_BIF, RGXFW_SF_BIF_SETUP_REG_DM, "Setup register set=%d DM=%d, PC address=0x%08x%08x, OSid=%u, NewPCRegRequired=%d", 6) \ +X( 20, RGXFW_GROUP_BIF, RGXFW_SF_BIF_PCSET_ALLOC, "Alloc PC set %d as register range [%u - %u]", 3) \ \ X( 1, RGXFW_GROUP_MISC, RGXFW_SF_MISC_GPIO_WRITE, "GPIO write 0x%02x", 1) \ X( 2, RGXFW_GROUP_MISC, RGXFW_SF_MISC_GPIO_READ, "GPIO read 0x%02x", 1) \ @@ -505,6 +523,8 @@ X( 28, RGXFW_GROUP_PM, RGXFW_SF_PM_3D_TIMEOUT, "3D Timeout Now for FWCtx 0x%08.8 X( 29, RGXFW_GROUP_PM, RGXFW_SF_PM_RECYCLE, "GEOM PM Recycle for FWCtx 0x%08.8x", 1) \ X( 30, RGXFW_GROUP_PM, RGXFW_SF_PM_PRIMARY_CONFIG, "PM running primary config (Core %d)", 1) \ X( 31, RGXFW_GROUP_PM, RGXFW_SF_PM_SECONDARY_CONFIG, "PM running secondary config (Core %d)", 1) \ +X( 32, RGXFW_GROUP_PM, RGXFW_SF_PM_TERTIARY_CONFIG, "PM running tertiary config (Core %d)", 1) \ +X( 33, RGXFW_GROUP_PM, RGXFW_SF_PM_QUATERNARY_CONFIG, "PM running quaternary config (Core %d)", 1) \ \ X( 1, RGXFW_GROUP_RPM, RGXFW_SF_RPM_GLL_DYNAMIC_STATUS_DEPRECATED, "Global link list dynamic page count: vertex 0x%x, varying 0x%x, node 0x%x", 3) \ X( 2, RGXFW_GROUP_RPM, RGXFW_SF_RPM_GLL_STATIC_STATUS_DEPRECATED, "Global link list static page count: vertex 0x%x, varying 0x%x, node 0x%x", 3) \ @@ -628,6 +648,7 @@ X( 54, RGXFW_GROUP_SPM, RGXFW_SF_SPM_ACK_GROW_UPDATE, "Received grow update, FL X( 66, RGXFW_GROUP_SPM, RGXFW_SF_SPM_OOM_TACMD, "OOM TA/3D PR Check: [0x%08.8x] is 0x%08.8x requires 0x%08.8x", 3) \ X( 67, RGXFW_GROUP_SPM, RGXFW_SF_SPM_RESUMED_TA, "OOM: Resumed TA with ready pages, FL addr: 0x%02x%08x, current pages: %u", 3) \ X( 68, RGXFW_GROUP_SPM, RGXFW_SF_SPM_PR_DEADLOCK_UNBLOCKED, "OOM TA/3D PR deadlock unblocked reordering DM%d runlist head from Context 0x%08x to 0x%08x", 3) \ +X( 69, RGXFW_GROUP_SPM, RGXFW_SF_SPM_STATE_PR_FORCEFREE, "SPM State = PR force free", 0) \ \ X( 1, RGXFW_GROUP_POW, RGXFW_SF_POW_CHECK_DEPRECATED, "Check Pow state DM%d int: 0x%x, ext: 0x%x, pow flags: 0x%x", 4) \ X( 2, RGXFW_GROUP_POW, RGXFW_SF_POW_GPU_IDLE, "GPU idle (might be powered down). Pow state int: 0x%x, ext: 0x%x, flags: 0x%x", 3) \ @@ -697,6 +718,10 @@ X( 66, RGXFW_GROUP_POW, RGXFW_SF_POW_POWMON_PERF_MODE, "PPA block started in per X( 67, RGXFW_GROUP_POW, RGXFW_SF_POW_POWMON_RESET, "Reset PPA block state %u (1=reset, 0=recalculate).", 1) \ X( 68, RGXFW_GROUP_POW, RGXFW_SF_POW_POWCTRL_ABORT_WITH_CORE, "Power controller returned ABORT for Core-%d last request so retrying.", 1) \ X( 69, RGXFW_GROUP_POW, RGXFW_SF_POW_HWREQ64BIT, "HW Request On(1)/Off(0): %d, Units: 0x%08x%08x", 3) \ +X( 70, RGXFW_GROUP_POW, RGXFW_SF_POW_SPU_RAC_POW_STATE_CHANGE_REQ, "Request to change SPU power state mask from 0x%x to 0x%x and RAC from 0x%x to 0x%x. Pow flags: 0x%x", 5) \ +X( 71, RGXFW_GROUP_POW, RGXFW_SF_POW_SPU_RAC_POW_STATE_CHANGE, "Changing SPU power state mask from 0x%x to 0x%x and RAC from 0x%x to 0x%x", 4) \ +X( 72, RGXFW_GROUP_POW, RGXFW_SF_POW_REQUESTEDOFF_RAC, "RAC pending? %d, RAC Active? %d", 2) \ +X( 73, RGXFW_GROUP_POW, RGXFW_SF_POW_INIOFF_RAC, "Initiate powoff query for RAC.", 0) \ \ X( 1, RGXFW_GROUP_HWR, RGXFW_SF_HWR_LOCKUP_DEPRECATED, "Lockup detected on DM%d, FWCtx: 0x%08.8x", 2) \ X( 2, RGXFW_GROUP_HWR, RGXFW_SF_HWR_RESET_FW_DEPRECATED, "Reset fw state for DM%d, FWCtx: 0x%08.8x, MemCtx: 0x%08.8x", 3) \ @@ -786,14 +811,15 @@ X( 85, RGXFW_GROUP_HWR, RGXFW_SF_HWR_FULL_CHECK, "Full Signature Check result fo X( 86, RGXFW_GROUP_HWR, RGXFW_SF_HWR_USC_SLOTS_CHECK, "USC Slots result for Core%u, DM%u is HWRNeeded=%u USCSlotsUsedByDM=%d", 4) \ X( 87, RGXFW_GROUP_HWR, RGXFW_SF_HWR_WATCHDOG_CHECK, "USC Watchdog result for Core%u DM%u is HWRNeeded=%u Status=%u USCs={0x%x} with HWRChecksToGo=%u", 6) \ X( 88, RGXFW_GROUP_HWR, RGXFW_SF_HWR_MMU_RISCV_FAULT, "RISC-V MMU page fault detected (FWCORE MMU Status 0x%08x Req Status 0x%08x%08x)", 3) \ -X( 89, RGXFW_GROUP_HWR, RGXFW_SF_HWR_HWR_FAULT_POLL_BIF_TEXAS1_PFS_DEPRECATED, "After FW fault was raised, TEXAS1_PFS poll failed on core %d with value 0x%08x", 2) \ -X( 90, RGXFW_GROUP_HWR, RGXFW_SF_HWR_HWR_FAULT_POLL_BIF_PFS, "After FW fault was raised, BIF_PFS poll failed on core %d with value 0x%08x", 2) \ -X( 91, RGXFW_GROUP_HWR, RGXFW_SF_HWR_HWR_FAULT_POLL_SET_ABORT_PM_STATUS, "After FW fault was raised, MMU_ABORT_PM_STATUS set poll failed on core %d with value 0x%08x", 2) \ -X( 92, RGXFW_GROUP_HWR, RGXFW_SF_HWR_HWR_FAULT_POLL_UNSET_ABORT_PM_STATUS, "After FW fault was raised, MMU_ABORT_PM_STATUS unset poll failed on core %d with value 0x%08x", 2) \ -X( 93, RGXFW_GROUP_HWR, RGXFW_SF_HWR_HWR_FAULT_POLL_SLC_INVAL, "After FW fault was raised, MMU_CTRL_INVAL poll (all but fw) failed on core %d with value 0x%08x", 2) \ -X( 94, RGXFW_GROUP_HWR, RGXFW_SF_HWR_HWR_FAULT_POLL_SLCMMU_INVAL, "After FW fault was raised, MMU_CTRL_INVAL poll (all) failed on core %d with value 0x%08x", 2) \ -X( 95, RGXFW_GROUP_HWR, RGXFW_SF_HWR_HWR_FAULT_POLL_BIF_TEXAS_PFS, "After FW fault was raised, TEXAS%d_PFS poll failed on core %d with value 0x%08x", 3) \ +X( 89, RGXFW_GROUP_HWR, RGXFW_SF_HWR_HWR_FAULT_POLL_BIF_TEXAS1_PFS_DEPRECATED, "TEXAS1_PFS poll failed on core %d with value 0x%08x", 2) \ +X( 90, RGXFW_GROUP_HWR, RGXFW_SF_HWR_HWR_FAULT_POLL_BIF_PFS, "BIF_PFS poll failed on core %d with value 0x%08x", 2) \ +X( 91, RGXFW_GROUP_HWR, RGXFW_SF_HWR_HWR_FAULT_POLL_SET_ABORT_PM_STATUS, "MMU_ABORT_PM_STATUS set poll failed on core %d with value 0x%08x", 2) \ +X( 92, RGXFW_GROUP_HWR, RGXFW_SF_HWR_HWR_FAULT_POLL_UNSET_ABORT_PM_STATUS, "MMU_ABORT_PM_STATUS unset poll failed on core %d with value 0x%08x", 2) \ +X( 93, RGXFW_GROUP_HWR, RGXFW_SF_HWR_HWR_FAULT_POLL_SLC_INVAL, "MMU_CTRL_INVAL poll (all but fw) failed on core %d with value 0x%08x", 2) \ +X( 94, RGXFW_GROUP_HWR, RGXFW_SF_HWR_HWR_FAULT_POLL_SLCMMU_INVAL, "MMU_CTRL_INVAL poll (all) failed on core %d with value 0x%08x", 2) \ +X( 95, RGXFW_GROUP_HWR, RGXFW_SF_HWR_HWR_FAULT_POLL_BIF_TEXAS_PFS, "TEXAS%d_PFS poll failed on core %d with value 0x%08x", 3) \ X( 96, RGXFW_GROUP_HWR, RGXFW_SF_HWR_EXTRA_CHECK, "Extra Registers Check result for Core%u, DM%u is HWRNeeded=%u", 3) \ +X( 97, RGXFW_GROUP_HWR, RGXFW_SF_HWR_WRITE_TO_GPU_READONLY_ADDR, "FW attempted to write to read-only GPU address 0x%08x", 1) \ \ X( 1, RGXFW_GROUP_HWP, RGXFW_SF_HWP_I_CFGBLK, "Block 0x%x mapped to Config Idx %u", 2) \ X( 2, RGXFW_GROUP_HWP, RGXFW_SF_HWP_I_OMTBLK, "Block 0x%x omitted from event - not enabled in HW", 1) \ diff --git a/drivers/gpu/drm/img-rogue/rgx_fwif_shared.h b/drivers/gpu/drm/img-rogue/rgx_fwif_shared.h index 3d47224e6..13844ad4e 100644 --- a/drivers/gpu/drm/img-rogue/rgx_fwif_shared.h +++ b/drivers/gpu/drm/img-rogue/rgx_fwif_shared.h @@ -51,7 +51,17 @@ CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. #include "powervr/mem_types.h" /* Indicates the number of RTDATAs per RTDATASET */ -#define RGXMKIF_NUM_RTDATAS 2U +#if defined(SUPPORT_AGP) +#define RGXMKIF_NUM_RTDATAS 4U +#define RGXMKIF_NUM_GEOMDATAS 4U +#define RGXMKIF_NUM_RTDATA_FREELISTS 12U /* RGXMKIF_NUM_RTDATAS * RGXFW_MAX_FREELISTS */ +#define RGX_NUM_GEOM_CORES (2U) +#else +#define RGXMKIF_NUM_RTDATAS 2U +#define RGXMKIF_NUM_GEOMDATAS 1U +#define RGXMKIF_NUM_RTDATA_FREELISTS 2U /* RGXMKIF_NUM_RTDATAS * RGXFW_MAX_FREELISTS */ +#define RGX_NUM_GEOM_CORES (1U) +#endif /* Maximum number of UFOs in a CCB command. * The number is based on having 32 sync prims (as originally), plus 32 sync @@ -121,13 +131,17 @@ typedef enum RGXFWIF_PRBUFFER_UNBACKING_PENDING, }RGXFWIF_PRBUFFER_STATE; +/*! + * @InGroup RenderTarget + * @Brief OnDemand Z/S/MSAA Buffers + */ typedef struct { - IMG_UINT32 ui32BufferID; /*!< Buffer ID*/ - IMG_BOOL bOnDemand; /*!< Needs On-demand Z/S/MSAA Buffer allocation */ - RGXFWIF_PRBUFFER_STATE eState; /*!< Z/S/MSAA -Buffer state */ - RGXFWIF_CLEANUP_CTL sCleanupState; /*!< Cleanup state */ - IMG_UINT32 ui32PRBufferFlags; /*!< Compatibility and other flags */ + IMG_UINT32 ui32BufferID; /*!< Buffer ID*/ + IMG_BOOL bOnDemand; /*!< Needs On-demand Z/S/MSAA Buffer allocation */ + RGXFWIF_PRBUFFER_STATE eState; /*!< Z/S/MSAA -Buffer state */ + RGXFWIF_CLEANUP_CTL sCleanupState; /*!< Cleanup state */ + IMG_UINT32 ui32PRBufferFlags; /*!< Compatibility and other flags */ } UNCACHED_ALIGN RGXFWIF_PRBUFFER; /* @@ -188,7 +202,15 @@ typedef struct * Points to commands not ready, i.e. * fence dependencies are not met. */ IMG_UINT32 ui32WrapMask; /*!< Offset wrapping mask, total capacity - * in bytes of the CCB-1 */ + in bytes of the CCB-1 */ +#if defined(SUPPORT_AGP) + IMG_UINT32 ui32ReadOffset2; +#if defined(SUPPORT_AGP4) + IMG_UINT32 ui32ReadOffset3; + IMG_UINT32 ui32ReadOffset4; +#endif +#endif + } UNCACHED_ALIGN RGXFWIF_CCCB_CTL; @@ -196,7 +218,13 @@ typedef IMG_UINT32 RGXFW_FREELIST_TYPE; #define RGXFW_LOCAL_FREELIST IMG_UINT32_C(0) #define RGXFW_GLOBAL_FREELIST IMG_UINT32_C(1) +#if defined(SUPPORT_AGP) +#define RGXFW_GLOBAL2_FREELIST IMG_UINT32_C(2) +#define RGXFW_MAX_FREELISTS (RGXFW_GLOBAL2_FREELIST + 1U) +#else #define RGXFW_MAX_FREELISTS (RGXFW_GLOBAL_FREELIST + 1U) +#endif +#define RGXFW_MAX_HWFREELISTS (2U) /*! * @Defgroup ContextSwitching Context switching data interface @@ -256,7 +284,7 @@ typedef struct */ typedef struct { - RGXFWIF_TAREGISTERS_CSWITCH RGXFW_ALIGN sCtxSwitch_Regs; /*!< Geom registers for ctx switch */ + RGXFWIF_TAREGISTERS_CSWITCH RGXFW_ALIGN asCtxSwitch_GeomRegs[RGX_NUM_GEOM_CORES]; /*!< Geom registers for ctx switch */ } RGXFWIF_STATIC_RENDERCONTEXT_STATE; #define RGXFWIF_STATIC_RENDERCONTEXT_SIZE sizeof(RGXFWIF_STATIC_RENDERCONTEXT_STATE) diff --git a/drivers/gpu/drm/img-rogue/rgx_heap_firmware.h b/drivers/gpu/drm/img-rogue/rgx_heap_firmware.h index 36150640d..db2b90b9f 100644 --- a/drivers/gpu/drm/img-rogue/rgx_heap_firmware.h +++ b/drivers/gpu/drm/img-rogue/rgx_heap_firmware.h @@ -57,7 +57,7 @@ CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. * of the map / unmap functions must take into consideration * the entire range (i.e. main and config heap). */ -#define RGX_FIRMWARE_NUMBER_OF_FW_HEAPS (2) +#define RGX_FIRMWARE_NUMBER_OF_FW_HEAPS (IMG_UINT32_C(2)) #define RGX_FIRMWARE_HEAP_SHIFT RGX_FW_HEAP_SHIFT #define RGX_FIRMWARE_RAW_HEAP_BASE (0xE1C0000000ULL) #define RGX_FIRMWARE_RAW_HEAP_SIZE (IMG_UINT32_C(1) << RGX_FIRMWARE_HEAP_SHIFT) @@ -73,9 +73,9 @@ CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. * 1st PMR: RGXFWIF_CONNECTION_CTL * 2nd PMR: RGXFWIF_OSINIT * 3rd PMR: RGXFWIF_SYSINIT */ -#define RGX_FIRMWARE_CONFIG_HEAP_SIZE (3*RGX_FIRMWARE_CONFIG_HEAP_ALLOC_GRANULARITY) +#define RGX_FIRMWARE_CONFIG_HEAP_SIZE (IMG_UINT32_C(3)*RGX_FIRMWARE_CONFIG_HEAP_ALLOC_GRANULARITY) -#define RGX_FIRMWARE_META_MAIN_HEAP_SIZE (RGX_FIRMWARE_RAW_HEAP_SIZE - RGX_FIRMWARE_CONFIG_HEAP_SIZE) +#define RGX_FIRMWARE_DEFAULT_MAIN_HEAP_SIZE (RGX_FIRMWARE_RAW_HEAP_SIZE - RGX_FIRMWARE_CONFIG_HEAP_SIZE) /* * MIPS FW needs space in the Main heap to map GPU memory. * This space is taken from the MAIN heap, to avoid creating a new heap. @@ -83,36 +83,30 @@ CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. #define RGX_FIRMWARE_MIPS_GPU_MAP_RESERVED_SIZE_NORMAL (IMG_UINT32_C(0x100000)) /* 1MB */ #define RGX_FIRMWARE_MIPS_GPU_MAP_RESERVED_SIZE_BRN65101 (IMG_UINT32_C(0x400000)) /* 4MB */ -#define RGX_FIRMWARE_MIPS_MAIN_HEAP_SIZE_NORMAL (RGX_FIRMWARE_RAW_HEAP_SIZE - RGX_FIRMWARE_CONFIG_HEAP_SIZE - \ - RGX_FIRMWARE_MIPS_GPU_MAP_RESERVED_SIZE_NORMAL) +#define RGX_FIRMWARE_HOST_MIPS_MAIN_HEAP_SIZE_NORMAL (RGX_FIRMWARE_RAW_HEAP_SIZE - RGX_FIRMWARE_CONFIG_HEAP_SIZE - \ + RGX_FIRMWARE_MIPS_GPU_MAP_RESERVED_SIZE_NORMAL) -#define RGX_FIRMWARE_MIPS_MAIN_HEAP_SIZE_BRN65101 (RGX_FIRMWARE_RAW_HEAP_SIZE - RGX_FIRMWARE_CONFIG_HEAP_SIZE - \ - RGX_FIRMWARE_MIPS_GPU_MAP_RESERVED_SIZE_BRN65101) +#define RGX_FIRMWARE_HOST_MIPS_MAIN_HEAP_SIZE_BRN65101 (RGX_FIRMWARE_RAW_HEAP_SIZE - RGX_FIRMWARE_CONFIG_HEAP_SIZE - \ + RGX_FIRMWARE_MIPS_GPU_MAP_RESERVED_SIZE_BRN65101) #if !defined(__KERNEL__) #if defined(FIX_HW_BRN_65101) #define RGX_FIRMWARE_MIPS_GPU_MAP_RESERVED_SIZE RGX_FIRMWARE_MIPS_GPU_MAP_RESERVED_SIZE_BRN65101 -#define RGX_FIRMWARE_MIPS_MAIN_HEAP_SIZE RGX_FIRMWARE_MIPS_MAIN_HEAP_SIZE_BRN65101 +#define RGX_FIRMWARE_HOST_MIPS_MAIN_HEAP_SIZE RGX_FIRMWARE_HOST_MIPS_MAIN_HEAP_SIZE_BRN65101 #include "img_defs.h" static_assert((RGX_FIRMWARE_RAW_HEAP_SIZE) >= IMG_UINT32_C(0x800000), "MIPS GPU map size cannot be increased due to BRN65101 with a small FW heap"); #else #define RGX_FIRMWARE_MIPS_GPU_MAP_RESERVED_SIZE RGX_FIRMWARE_MIPS_GPU_MAP_RESERVED_SIZE_NORMAL -#define RGX_FIRMWARE_MIPS_MAIN_HEAP_SIZE RGX_FIRMWARE_MIPS_MAIN_HEAP_SIZE_NORMAL +#define RGX_FIRMWARE_HOST_MIPS_MAIN_HEAP_SIZE RGX_FIRMWARE_HOST_MIPS_MAIN_HEAP_SIZE_NORMAL #endif #endif /* !defined(__KERNEL__) */ -/* Host sub-heap order: MAIN + CONFIG */ -#define RGX_FIRMWARE_HOST_MAIN_HEAP_BASE RGX_FIRMWARE_RAW_HEAP_BASE -#define RGX_FIRMWARE_HOST_CONFIG_HEAP_BASE (RGX_FIRMWARE_HOST_MAIN_HEAP_BASE + \ - RGX_FIRMWARE_RAW_HEAP_SIZE - \ - RGX_FIRMWARE_CONFIG_HEAP_SIZE) - -/* Guest sub-heap order: CONFIG + MAIN */ -#define RGX_FIRMWARE_GUEST_CONFIG_HEAP_BASE RGX_FIRMWARE_RAW_HEAP_BASE -#define RGX_FIRMWARE_GUEST_MAIN_HEAP_BASE (RGX_FIRMWARE_GUEST_CONFIG_HEAP_BASE + \ - RGX_FIRMWARE_CONFIG_HEAP_SIZE) +#define RGX_FIRMWARE_MAIN_HEAP_BASE RGX_FIRMWARE_RAW_HEAP_BASE +#define RGX_FIRMWARE_CONFIG_HEAP_BASE (RGX_FIRMWARE_MAIN_HEAP_BASE + \ + RGX_FIRMWARE_RAW_HEAP_SIZE - \ + RGX_FIRMWARE_CONFIG_HEAP_SIZE) /* * The maximum configurable size via RGX_FW_HEAP_SHIFT is 32MiB (1<<25) and diff --git a/drivers/gpu/drm/img-rogue/rgx_heaps.h b/drivers/gpu/drm/img-rogue/rgx_heaps.h index 4c7e53582..e41e4002b 100644 --- a/drivers/gpu/drm/img-rogue/rgx_heaps.h +++ b/drivers/gpu/drm/img-rogue/rgx_heaps.h @@ -54,6 +54,7 @@ CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. #define RGX_VK_CAPT_REPLAY_HEAP_IDENT "Vulkan Capture Replay" /*!< RGX Vulkan capture replay buffer Heap Identifier */ #define RGX_SIGNALS_HEAP_IDENT "Signals" /*!< Signals Heap Identifier */ #define RGX_FBCDC_HEAP_IDENT "FBCDC" /*!< RGX FBCDC State Table Heap Identifier */ +#define RGX_FBCDC_LARGE_HEAP_IDENT "Large FBCDC" /*!< RGX Large FBCDC State Table Heap Identifier */ #define RGX_CMP_MISSION_RMW_HEAP_IDENT "Compute Mission RMW" /*!< Compute Mission RMW Heap Identifier */ #define RGX_CMP_SAFETY_RMW_HEAP_IDENT "Compute Safety RMW" /*!< Compute Safety RMW Heap Identifier */ #define RGX_TEXTURE_STATE_HEAP_IDENT "Texture State" /*!< Texture State Heap Identifier */ diff --git a/drivers/gpu/drm/img-rogue/rgx_hwperf.h b/drivers/gpu/drm/img-rogue/rgx_hwperf.h index e8d159c15..fa711b0b6 100644 --- a/drivers/gpu/drm/img-rogue/rgx_hwperf.h +++ b/drivers/gpu/drm/img-rogue/rgx_hwperf.h @@ -60,6 +60,7 @@ extern "C" { #include "img_defs.h" #include "rgx_common.h" +#include "rgx_hwperf_common.h" #include "pvrsrv_tlcommon.h" #include "pvrsrv_sync_km.h" @@ -141,404 +142,8 @@ static_assert(RGX_FEATURE_NUM_CLUSTERS <= 16U, "Cluster count too large for HWPe /*! The number of counters supported in each non-mux counter block */ #define RGX_HWPERF_MAX_CUSTOM_CNTRS 8U -/*! The number of non-mux counter blocks supported */ -#if defined(SUPPORT_VALIDATION) -#define RGX_CNTBLK_COUNTERS_MAX 64U -#else -#define RGX_CNTBLK_COUNTERS_MAX 12U -#endif - -/****************************************************************************** - * Packet Event Type Enumerations - *****************************************************************************/ - -/*! Type used to encode the event that generated the packet. - * NOTE: When this type is updated the corresponding hwperfbin2json tool - * source needs to be updated as well. The RGX_HWPERF_EVENT_MASK_* macros will - * also need updating when adding new types. - * - * @par - * The event type values are incrementing integers for use as a shift ordinal - * in the event filtering process at the point events are generated. - * This scheme thus implies a limit of 63 event types. - */ - -typedef IMG_UINT32 RGX_HWPERF_EVENT_TYPE; - -#define RGX_HWPERF_INVALID 0x00U /*!< Invalid. Reserved value. */ - -/*! FW types 0x01..0x06 */ -#define RGX_HWPERF_FW_EVENT_RANGE_FIRST_TYPE 0x01U - -#define RGX_HWPERF_FW_BGSTART 0x01U /*!< Background task processing start */ -#define RGX_HWPERF_FW_BGEND 0x02U /*!< Background task end */ -#define RGX_HWPERF_FW_IRQSTART 0x03U /*!< IRQ task processing start */ - -#define RGX_HWPERF_FW_IRQEND 0x04U /*!< IRQ task end */ -#define RGX_HWPERF_FW_DBGSTART 0x05U /*!< Debug event start */ -#define RGX_HWPERF_FW_DBGEND 0x06U /*!< Debug event end */ - -#define RGX_HWPERF_FW_EVENT_RANGE_LAST_TYPE 0x06U - -/*! HW types 0x07..0x19 */ -#define RGX_HWPERF_HW_EVENT_RANGE0_FIRST_TYPE 0x07U - -#define RGX_HWPERF_HW_PMOOM_TAPAUSE 0x07U /*!< TA Pause at PM Out of Memory */ - -#define RGX_HWPERF_HW_TAKICK 0x08U /*!< TA task started */ -#define RGX_HWPERF_HW_TAFINISHED 0x09U /*!< TA task finished */ -#define RGX_HWPERF_HW_3DTQKICK 0x0AU /*!< 3D TQ started */ -#define RGX_HWPERF_HW_3DKICK 0x0BU /*!< 3D task started */ -#define RGX_HWPERF_HW_3DFINISHED 0x0CU /*!< 3D task finished */ -#define RGX_HWPERF_HW_CDMKICK 0x0DU /*!< CDM task started */ -#define RGX_HWPERF_HW_CDMFINISHED 0x0EU /*!< CDM task finished */ -#define RGX_HWPERF_HW_TLAKICK 0x0FU /*!< TLA task started */ -#define RGX_HWPERF_HW_TLAFINISHED 0x10U /*!< TLS task finished */ -#define RGX_HWPERF_HW_3DSPMKICK 0x11U /*!< 3D SPM task started */ -#define RGX_HWPERF_HW_PERIODIC 0x12U /*!< Periodic event with updated HW counters */ -#define RGX_HWPERF_HW_RTUKICK 0x13U /*!< Reserved, future use */ -#define RGX_HWPERF_HW_RTUFINISHED 0x14U /*!< Reserved, future use */ -#define RGX_HWPERF_HW_SHGKICK 0x15U /*!< Reserved, future use */ -#define RGX_HWPERF_HW_SHGFINISHED 0x16U /*!< Reserved, future use */ -#define RGX_HWPERF_HW_3DTQFINISHED 0x17U /*!< 3D TQ finished */ -#define RGX_HWPERF_HW_3DSPMFINISHED 0x18U /*!< 3D SPM task finished */ - -#define RGX_HWPERF_HW_PMOOM_TARESUME 0x19U /*!< TA Resume after PM Out of Memory */ - -/*! HW_EVENT_RANGE0 used up. Use next empty range below to add new hardware events */ -#define RGX_HWPERF_HW_EVENT_RANGE0_LAST_TYPE 0x19U - -/*! other types 0x1A..0x1F */ -#define RGX_HWPERF_CLKS_CHG 0x1AU /*!< Clock speed change in GPU */ -#define RGX_HWPERF_GPU_STATE_CHG 0x1BU /*!< GPU work state change */ - -/*! power types 0x20..0x27 */ -#define RGX_HWPERF_PWR_EST_RANGE_FIRST_TYPE 0x20U -#define RGX_HWPERF_PWR_EST_REQUEST 0x20U /*!< Power estimate requested (via GPIO) */ -#define RGX_HWPERF_PWR_EST_READY 0x21U /*!< Power estimate inputs ready */ -#define RGX_HWPERF_PWR_EST_RESULT 0x22U /*!< Power estimate result calculated */ -#define RGX_HWPERF_PWR_EST_RANGE_LAST_TYPE 0x22U - -#define RGX_HWPERF_PWR_CHG 0x23U /*!< Power state change */ - -/*! HW_EVENT_RANGE1 0x28..0x2F, for accommodating new hardware events */ -#define RGX_HWPERF_HW_EVENT_RANGE1_FIRST_TYPE 0x28U - -#define RGX_HWPERF_HW_TDMKICK 0x28U /*!< TDM task started */ -#define RGX_HWPERF_HW_TDMFINISHED 0x29U /*!< TDM task finished */ -#define RGX_HWPERF_HW_NULLKICK 0x2AU /*!< NULL event */ - -#define RGX_HWPERF_HW_EVENT_RANGE1_LAST_TYPE 0x2AU - -/*! context switch types 0x30..0x31 */ -#define RGX_HWPERF_CSW_START 0x30U /*!< HW context store started */ -#define RGX_HWPERF_CSW_FINISHED 0x31U /*!< HW context store finished */ - -/*! DVFS events */ -#define RGX_HWPERF_DVFS 0x32U /*!< Dynamic voltage/frequency scaling events */ - -/*! firmware misc 0x38..0x39 */ -#define RGX_HWPERF_UFO 0x38U /*!< FW UFO Check / Update */ -#define RGX_HWPERF_FWACT 0x39U /*!< FW Activity notification */ - -/*! last */ -#define RGX_HWPERF_LAST_TYPE 0x3BU - -/*! This enumeration must have a value that is a power of two as it is - * used in masks and a filter bit field (currently 64 bits long). - */ -#define RGX_HWPERF_MAX_TYPE 0x40U - -static_assert(RGX_HWPERF_LAST_TYPE < RGX_HWPERF_MAX_TYPE, "Too many HWPerf event types"); - -/*! Macro used to check if an event type ID is present in the known set of hardware type events */ -#define HWPERF_PACKET_IS_HW_TYPE(_etype) (((_etype) >= RGX_HWPERF_HW_EVENT_RANGE0_FIRST_TYPE && (_etype) <= RGX_HWPERF_HW_EVENT_RANGE0_LAST_TYPE) || \ - ((_etype) >= RGX_HWPERF_HW_EVENT_RANGE1_FIRST_TYPE && (_etype) <= RGX_HWPERF_HW_EVENT_RANGE1_LAST_TYPE)) - -/*! Macro used to check if an event type ID is present in the known set of firmware type events */ -#define HWPERF_PACKET_IS_FW_TYPE(_etype) \ - ((_etype) >= RGX_HWPERF_FW_EVENT_RANGE_FIRST_TYPE && \ - (_etype) <= RGX_HWPERF_FW_EVENT_RANGE_LAST_TYPE) - - -typedef enum { - RGX_HWPERF_HOST_INVALID = 0x00, /*!< Invalid, do not use. */ - RGX_HWPERF_HOST_ENQ = 0x01, /*!< ``0x01`` Kernel driver has queued GPU work. - See RGX_HWPERF_HOST_ENQ_DATA */ - RGX_HWPERF_HOST_UFO = 0x02, /*!< ``0x02`` UFO updated by the driver. - See RGX_HWPERF_HOST_UFO_DATA */ - RGX_HWPERF_HOST_ALLOC = 0x03, /*!< ``0x03`` Resource allocated. - See RGX_HWPERF_HOST_ALLOC_DATA */ - RGX_HWPERF_HOST_CLK_SYNC = 0x04, /*!< ``0x04`` GPU / Host clocks correlation data. - See RGX_HWPERF_HOST_CLK_SYNC_DATA */ - RGX_HWPERF_HOST_FREE = 0x05, /*!< ``0x05`` Resource freed, - See RGX_HWPERF_HOST_FREE_DATA */ - RGX_HWPERF_HOST_MODIFY = 0x06, /*!< ``0x06`` Resource modified / updated. - See RGX_HWPERF_HOST_MODIFY_DATA */ - RGX_HWPERF_HOST_DEV_INFO = 0x07, /*!< ``0x07`` Device Health status. - See RGX_HWPERF_HOST_DEV_INFO_DATA */ - RGX_HWPERF_HOST_INFO = 0x08, /*!< ``0x08`` Device memory usage information. - See RGX_HWPERF_HOST_INFO_DATA */ - RGX_HWPERF_HOST_SYNC_FENCE_WAIT = 0x09, /*!< ``0x09`` Wait for sync event. - See RGX_HWPERF_HOST_SYNC_FENCE_WAIT_DATA */ - RGX_HWPERF_HOST_SYNC_SW_TL_ADVANCE = 0x0A, /*!< ``0x0A`` Software timeline advanced. - See RGX_HWPERF_HOST_SYNC_SW_TL_ADV_DATA */ - - /*! last */ - RGX_HWPERF_HOST_LAST_TYPE, - - /*! This enumeration must have a value that is a power of two as it is - * used in masks and a filter bit field (currently 32 bits long). - */ - RGX_HWPERF_HOST_MAX_TYPE = 0x20 -} RGX_HWPERF_HOST_EVENT_TYPE; - -/*!< The event type values are incrementing integers for use as a shift ordinal - * in the event filtering process at the point events are generated. - * This scheme thus implies a limit of 31 event types. - */ -static_assert(RGX_HWPERF_HOST_LAST_TYPE < RGX_HWPERF_HOST_MAX_TYPE, "Too many HWPerf host event types"); - - -/****************************************************************************** - * Packet Header Format Version 2 Types - *****************************************************************************/ - -/*! Major version number of the protocol in operation - */ -#define RGX_HWPERF_V2_FORMAT 2 - -/*! Signature ASCII pattern 'HWP2' found in the first word of a HWPerfV2 packet - */ -#define HWPERF_PACKET_V2_SIG 0x48575032 - -/*! Signature ASCII pattern 'HWPA' found in the first word of a HWPerfV2a packet - */ -#define HWPERF_PACKET_V2A_SIG 0x48575041 - -/*! Signature ASCII pattern 'HWPB' found in the first word of a HWPerfV2b packet - */ -#define HWPERF_PACKET_V2B_SIG 0x48575042 - -#define HWPERF_PACKET_ISVALID(_ptr) (((_ptr) == HWPERF_PACKET_V2_SIG) || ((_ptr) == HWPERF_PACKET_V2A_SIG)|| ((_ptr) == HWPERF_PACKET_V2B_SIG)) -/*!< Checks that the packet signature is one of the supported versions */ - -/*! Type defines the HWPerf packet header common to all events. */ -typedef struct -{ - IMG_UINT32 ui32Sig; /*!< Always the value HWPERF_PACKET_SIG */ - IMG_UINT32 ui32Size; /*!< Overall packet size in bytes */ - IMG_UINT32 eTypeId; /*!< Event type information field */ - IMG_UINT32 ui32Ordinal; /*!< Sequential number of the packet */ - IMG_UINT64 ui64Timestamp; /*!< Event timestamp */ -} RGX_HWPERF_V2_PACKET_HDR, *RGX_PHWPERF_V2_PACKET_HDR; - -#ifndef __CHECKER__ -RGX_FW_STRUCT_OFFSET_ASSERT(RGX_HWPERF_V2_PACKET_HDR, ui64Timestamp); - -RGX_FW_STRUCT_SIZE_ASSERT(RGX_HWPERF_V2_PACKET_HDR); -#endif - - -/*! Mask for use with the IMG_UINT32 ui32Size header field */ -#define RGX_HWPERF_SIZE_MASK 0xFFFFU - -/*! This macro defines an upper limit to which the size of the largest variable - * length HWPerf packet must fall within, currently 3KB. This constant may be - * used to allocate a buffer to hold one packet. - * This upper limit is policed by packet producing code. - */ -#define RGX_HWPERF_MAX_PACKET_SIZE 0xC00U - -/*! Defines an upper limit to the size of a variable length packet payload. - */ -#define RGX_HWPERF_MAX_PAYLOAD_SIZE ((IMG_UINT32)(RGX_HWPERF_MAX_PACKET_SIZE-\ - sizeof(RGX_HWPERF_V2_PACKET_HDR))) - -/*! Macro which takes a structure name and provides the packet size for - * a fixed size payload packet, rounded up to 8 bytes to align packets - * for 64 bit architectures. */ -#define RGX_HWPERF_MAKE_SIZE_FIXED(_struct) ((IMG_UINT32)(RGX_HWPERF_SIZE_MASK&(sizeof(RGX_HWPERF_V2_PACKET_HDR)+PVR_ALIGN(sizeof(_struct), PVRSRVTL_PACKET_ALIGNMENT)))) - -/*! Macro which takes the number of bytes written in the data payload of a - * packet for a variable size payload packet, rounded up to 8 bytes to - * align packets for 64 bit architectures. */ -#define RGX_HWPERF_MAKE_SIZE_VARIABLE(_size) ((IMG_UINT32)(RGX_HWPERF_SIZE_MASK&(sizeof(RGX_HWPERF_V2_PACKET_HDR)+PVR_ALIGN((_size), PVRSRVTL_PACKET_ALIGNMENT)))) - -/*! Macro to obtain the size of the packet */ -#define RGX_HWPERF_GET_SIZE(_packet_addr) ((IMG_UINT16)(((_packet_addr)->ui32Size) & RGX_HWPERF_SIZE_MASK)) - -/*! Macro to obtain the size of the packet data */ -#define RGX_HWPERF_GET_DATA_SIZE(_packet_addr) (RGX_HWPERF_GET_SIZE(_packet_addr) - sizeof(RGX_HWPERF_V2_PACKET_HDR)) - -/*! Masks for use with the IMG_UINT32 eTypeId header field */ -#define RGX_HWPERF_TYPEID_MASK 0x0007FFFFU -#define RGX_HWPERF_TYPEID_EVENT_MASK 0x00007FFFU -#define RGX_HWPERF_TYPEID_THREAD_MASK 0x00008000U -#define RGX_HWPERF_TYPEID_STREAM_MASK 0x00070000U -#define RGX_HWPERF_TYPEID_META_DMA_MASK 0x00080000U -#define RGX_HWPERF_TYPEID_M_CORE_MASK 0x00100000U -#define RGX_HWPERF_TYPEID_OSID_MASK 0x07000000U - -/*! Meta thread macros for encoding the ID into the type field of a packet */ -#define RGX_HWPERF_META_THREAD_SHIFT 15U -#define RGX_HWPERF_META_THREAD_ID0 0x0U /*!< Meta Thread 0 ID */ -#define RGX_HWPERF_META_THREAD_ID1 0x1U /*!< Meta Thread 1 ID */ -/*! Obsolete, kept for source compatibility */ -#define RGX_HWPERF_META_THREAD_MASK 0x1U -/*! Stream ID macros for encoding the ID into the type field of a packet */ -#define RGX_HWPERF_STREAM_SHIFT 16U -/*! Meta DMA macro for encoding how the packet was generated into the type field of a packet */ -#define RGX_HWPERF_META_DMA_SHIFT 19U -/*! Bit-shift macro used for encoding multi-core data into the type field of a packet */ -#define RGX_HWPERF_M_CORE_SHIFT 20U -/*! OSID bit-shift macro used for encoding OSID into type field of a packet */ -#define RGX_HWPERF_OSID_SHIFT 24U -typedef enum { - RGX_HWPERF_STREAM_ID0_FW, /*!< Events from the Firmware/GPU */ - RGX_HWPERF_STREAM_ID1_HOST, /*!< Events from the Server host driver component */ - RGX_HWPERF_STREAM_ID2_CLIENT, /*!< Events from the Client host driver component */ - RGX_HWPERF_STREAM_ID_LAST, -} RGX_HWPERF_STREAM_ID; - -/* Checks if all stream IDs can fit under RGX_HWPERF_TYPEID_STREAM_MASK. */ -static_assert(((IMG_UINT32)RGX_HWPERF_STREAM_ID_LAST - 1U) < (RGX_HWPERF_TYPEID_STREAM_MASK >> RGX_HWPERF_STREAM_SHIFT), - "Too many HWPerf stream IDs."); - -/*! Compile-time value used to seed the Multi-Core (MC) bit in the typeID field. - * Only set by RGX_FIRMWARE builds. - */ -#if defined(RGX_FIRMWARE) -# if defined(RGX_FEATURE_GPU_MULTICORE_SUPPORT) -#define RGX_HWPERF_M_CORE_VALUE 1U /*!< 1 => Multi-core supported */ -# else -#define RGX_HWPERF_M_CORE_VALUE 0U /*!< 0 => Multi-core not supported */ -# endif -#else -#define RGX_HWPERF_M_CORE_VALUE 0U /*!< 0 => Multi-core not supported */ -#endif - -/*! Macros used to set the packet type and encode meta thread ID (0|1), - * HWPerf stream ID, multi-core capability and OSID within the typeID */ -#define RGX_HWPERF_MAKE_TYPEID(_stream, _type, _thread, _metadma, _osid)\ - ((IMG_UINT32) ((RGX_HWPERF_TYPEID_STREAM_MASK&((IMG_UINT32)(_stream) << RGX_HWPERF_STREAM_SHIFT)) | \ - (RGX_HWPERF_TYPEID_THREAD_MASK & ((IMG_UINT32)(_thread) << RGX_HWPERF_META_THREAD_SHIFT)) | \ - (RGX_HWPERF_TYPEID_EVENT_MASK & (IMG_UINT32)(_type)) | \ - (RGX_HWPERF_TYPEID_META_DMA_MASK & ((IMG_UINT32)(_metadma) << RGX_HWPERF_META_DMA_SHIFT)) | \ - (RGX_HWPERF_TYPEID_OSID_MASK & ((IMG_UINT32)(_osid) << RGX_HWPERF_OSID_SHIFT)) | \ - (RGX_HWPERF_TYPEID_M_CORE_MASK & ((IMG_UINT32)(RGX_HWPERF_M_CORE_VALUE) << RGX_HWPERF_M_CORE_SHIFT)))) - -/*! Obtains the event type that generated the packet */ -#define RGX_HWPERF_GET_TYPE(_packet_addr) (((_packet_addr)->eTypeId) & RGX_HWPERF_TYPEID_EVENT_MASK) - -/*! Obtains the META Thread number that generated the packet */ -#define RGX_HWPERF_GET_THREAD_ID(_packet_addr) (((((_packet_addr)->eTypeId) & RGX_HWPERF_TYPEID_THREAD_MASK) >> RGX_HWPERF_META_THREAD_SHIFT)) - -/*! Determines if the packet generated contains multi-core data */ -#define RGX_HWPERF_GET_M_CORE(_packet_addr) (((_packet_addr)->eTypeId & RGX_HWPERF_TYPEID_M_CORE_MASK) >> RGX_HWPERF_M_CORE_SHIFT) - -/*! Obtains the guest OSID which resulted in packet generation */ -#define RGX_HWPERF_GET_OSID(_packet_addr) (((_packet_addr)->eTypeId & RGX_HWPERF_TYPEID_OSID_MASK) >> RGX_HWPERF_OSID_SHIFT) - -/*! Obtain stream id */ -#define RGX_HWPERF_GET_STREAM_ID(_packet_addr) (((((_packet_addr)->eTypeId) & RGX_HWPERF_TYPEID_STREAM_MASK) >> RGX_HWPERF_STREAM_SHIFT)) - -/*! Obtain information about how the packet was generated, which might affect payload total size */ -#define RGX_HWPERF_GET_META_DMA_INFO(_packet_addr) (((((_packet_addr)->eTypeId) & RGX_HWPERF_TYPEID_META_DMA_MASK) >> RGX_HWPERF_META_DMA_SHIFT)) - -/*! Obtains a typed pointer to a packet given a buffer address */ -#define RGX_HWPERF_GET_PACKET(_buffer_addr) ((RGX_HWPERF_V2_PACKET_HDR *)(void *) (_buffer_addr)) -/*! Obtains a typed pointer to a data structure given a packet address */ -#define RGX_HWPERF_GET_PACKET_DATA_BYTES(_packet_addr) (IMG_OFFSET_ADDR((_packet_addr), sizeof(RGX_HWPERF_V2_PACKET_HDR))) -/*! Obtains a typed pointer to the next packet given a packet address */ -#define RGX_HWPERF_GET_NEXT_PACKET(_packet_addr) ((RGX_HWPERF_V2_PACKET_HDR *) (IMG_OFFSET_ADDR((_packet_addr), RGX_HWPERF_SIZE_MASK&((_packet_addr)->ui32Size)))) - -/*! Obtains a typed pointer to a packet header given the packet data address */ -#define RGX_HWPERF_GET_PACKET_HEADER(_packet_addr) ((RGX_HWPERF_V2_PACKET_HDR *) (IMG_OFFSET_ADDR((_packet_addr), -(IMG_INT32)sizeof(RGX_HWPERF_V2_PACKET_HDR)))) - - -/****************************************************************************** - * Other Common Defines - *****************************************************************************/ - -/*! This macro is not a real array size, but indicates the array has a variable - * length only known at run-time but always contains at least 1 element. The - * final size of the array is deduced from the size field of a packet header. - */ -#define RGX_HWPERF_ONE_OR_MORE_ELEMENTS 1U - -/*! This macro is not a real array size, but indicates the array is optional - * and if present has a variable length only known at run-time. The final - * size of the array is deduced from the size field of a packet header. */ -#define RGX_HWPERF_ZERO_OR_MORE_ELEMENTS 1U - - -/*! Masks for use with the IMG_UINT32 ui32BlkInfo field */ -#define RGX_HWPERF_BLKINFO_BLKCOUNT_MASK 0xFFFF0000U -#define RGX_HWPERF_BLKINFO_BLKOFFSET_MASK 0x0000FFFFU - -/*! Shift for the NumBlocks and counter block offset field in ui32BlkInfo */ -#define RGX_HWPERF_BLKINFO_BLKCOUNT_SHIFT 16U -#define RGX_HWPERF_BLKINFO_BLKOFFSET_SHIFT 0U - -/*! Macro used to set the block info word as a combination of two 16-bit integers */ -#define RGX_HWPERF_MAKE_BLKINFO(_numblks, _blkoffset) ((IMG_UINT32) ((RGX_HWPERF_BLKINFO_BLKCOUNT_MASK&((_numblks) << RGX_HWPERF_BLKINFO_BLKCOUNT_SHIFT)) | (RGX_HWPERF_BLKINFO_BLKOFFSET_MASK&((_blkoffset) << RGX_HWPERF_BLKINFO_BLKOFFSET_SHIFT)))) - -/*! Macro used to obtain the number of counter blocks present in the packet */ -#define RGX_HWPERF_GET_BLKCOUNT(_blkinfo) (((_blkinfo) & RGX_HWPERF_BLKINFO_BLKCOUNT_MASK) >> RGX_HWPERF_BLKINFO_BLKCOUNT_SHIFT) - -/*! Obtains the offset of the counter block stream in the packet */ -#define RGX_HWPERF_GET_BLKOFFSET(_blkinfo) (((_blkinfo) & RGX_HWPERF_BLKINFO_BLKOFFSET_MASK) >> RGX_HWPERF_BLKINFO_BLKOFFSET_SHIFT) - -/*! This macro gets the number of blocks depending on the packet version */ -#define RGX_HWPERF_GET_NUMBLKS(_sig, _packet_data, _numblocks) \ - do { \ - if (HWPERF_PACKET_V2B_SIG == (_sig)) \ - { \ - (_numblocks) = RGX_HWPERF_GET_BLKCOUNT((_packet_data)->ui32BlkInfo);\ - } \ - else \ - { \ - IMG_UINT32 ui32VersionOffset = (((_sig) == HWPERF_PACKET_V2_SIG) ? 1 : 3);\ - (_numblocks) = *(IMG_UINT16 *)(IMG_OFFSET_ADDR(&(_packet_data)->ui32WorkTarget, ui32VersionOffset)); \ - } \ - } while (0) - -/*! This macro gets the counter stream pointer depending on the packet version */ -#define RGX_HWPERF_GET_CNTSTRM(_sig, _hw_packet_data, _cntstream_ptr) \ -{ \ - if (HWPERF_PACKET_V2B_SIG == (_sig)) \ - { \ - (_cntstream_ptr) = (IMG_UINT32 *)(IMG_OFFSET_ADDR((_hw_packet_data), RGX_HWPERF_GET_BLKOFFSET((_hw_packet_data)->ui32BlkInfo))); \ - } \ - else \ - { \ - IMG_UINT32 ui32BlkStreamOffsetInWords = (((_sig) == HWPERF_PACKET_V2_SIG) ? 6 : 8); \ - (_cntstream_ptr) = (IMG_UINT32 *)(IMG_OFFSET_ADDR_DW((_hw_packet_data), ui32BlkStreamOffsetInWords)); \ - } \ -} - -/*! Masks for use with the RGX_HWPERF_UFO_EV eEvType field */ -#define RGX_HWPERF_UFO_STREAMSIZE_MASK 0xFFFF0000U -#define RGX_HWPERF_UFO_STREAMOFFSET_MASK 0x0000FFFFU - -/*! Shift for the UFO count and data stream fields */ -#define RGX_HWPERF_UFO_STREAMSIZE_SHIFT 16U -#define RGX_HWPERF_UFO_STREAMOFFSET_SHIFT 0U - -/*! Macro used to set UFO stream info word as a combination of two 16-bit integers */ -#define RGX_HWPERF_MAKE_UFOPKTINFO(_ssize, _soff) \ - ((IMG_UINT32) ((RGX_HWPERF_UFO_STREAMSIZE_MASK&((_ssize) << RGX_HWPERF_UFO_STREAMSIZE_SHIFT)) | \ - (RGX_HWPERF_UFO_STREAMOFFSET_MASK&((_soff) << RGX_HWPERF_UFO_STREAMOFFSET_SHIFT)))) - -/*! Macro used to obtain UFO count*/ -#define RGX_HWPERF_GET_UFO_STREAMSIZE(_streaminfo) \ - (((_streaminfo) & RGX_HWPERF_UFO_STREAMSIZE_MASK) >> RGX_HWPERF_UFO_STREAMSIZE_SHIFT) - -/*! Obtains the offset of the UFO stream in the packet */ -#define RGX_HWPERF_GET_UFO_STREAMOFFSET(_streaminfo) \ - (((_streaminfo) & RGX_HWPERF_UFO_STREAMOFFSET_MASK) >> RGX_HWPERF_UFO_STREAMOFFSET_SHIFT) - +/*! The number of directly-addressable counters allowed in non-mux counter blocks */ +#define RGX_CNTBLK_COUNTERS_MAX ((IMG_UINT32)PVRSRV_HWPERF_COUNTERS_PERBLK + 0U) /****************************************************************************** @@ -565,18 +170,20 @@ typedef enum { RGX_HWPERF_DM_INVALID = 0x1FFFFFFF } RGX_HWPERF_DM; -/*! Enum containing bit position for 32bit feature flags used in hwperf and api */ -typedef enum { - RGX_HWPERF_FEATURE_PERFBUS_FLAG = 0x001, - RGX_HWPERF_FEATURE_S7_TOP_INFRASTRUCTURE_FLAG = 0x002, - RGX_HWPERF_FEATURE_XT_TOP_INFRASTRUCTURE_FLAG = 0x004, - RGX_HWPERF_FEATURE_PERF_COUNTER_BATCH_FLAG = 0x008, - RGX_HWPERF_FEATURE_ROGUEXE_FLAG = 0x010, - RGX_HWPERF_FEATURE_DUST_POWER_ISLAND_S7_FLAG = 0x020, - RGX_HWPERF_FEATURE_PBE2_IN_XE_FLAG = 0x040, - RGX_HWPERF_FEATURE_WORKLOAD_ESTIMATION = 0x080, - RGX_HWPERF_FEATURE_MULTICORE_FLAG = 0x100 -} RGX_HWPERF_FEATURE_FLAGS; +/*! Define containing bit position for 32bit feature flags used in hwperf and api */ +typedef IMG_UINT32 RGX_HWPERF_FEATURE_FLAGS; +#define RGX_HWPERF_FEATURE_PERFBUS_FLAG 0x0001U +#define RGX_HWPERF_FEATURE_S7_TOP_INFRASTRUCTURE_FLAG 0x0002U +#define RGX_HWPERF_FEATURE_XT_TOP_INFRASTRUCTURE_FLAG 0x0004U +#define RGX_HWPERF_FEATURE_PERF_COUNTER_BATCH_FLAG 0x0008U +#define RGX_HWPERF_FEATURE_ROGUEXE_FLAG 0x0010U +#define RGX_HWPERF_FEATURE_DUST_POWER_ISLAND_S7_FLAG 0x0020U +#define RGX_HWPERF_FEATURE_PBE2_IN_XE_FLAG 0x0040U +#define RGX_HWPERF_FEATURE_WORKLOAD_ESTIMATION 0x0080U +#define RGX_HWPERF_FEATURE_MULTICORE_FLAG 0x0100U +#define RGX_HWPERF_FEATURE_VOLCANIC_FLAG 0x0800U +#define RGX_HWPERF_FEATURE_ROGUE_FLAG 0x1000U +#define RGX_HWPERF_FEATURE_OCEANIC_FLAG 0x2000U /*! This structure holds the data of a firmware packet. */ typedef struct @@ -606,11 +213,14 @@ typedef struct IMG_UINT32 ui32WorkCtx; /*!< Work context: Render Context for TA/3D; RayTracing Context for RTU/SHG; 0x0 otherwise */ IMG_UINT32 ui32CtxPriority; /*!< Context priority */ IMG_UINT32 ui32GPUIdMask; /*!< GPU IDs active within this event */ - IMG_UINT32 aui32CountBlksStream[RGX_HWPERF_ZERO_OR_MORE_ELEMENTS]; /*!< Counter data */ - IMG_UINT32 ui32Padding2; /*!< Reserved. To ensure correct alignment */ + IMG_UINT32 ui32KickInfo; /*!< <31..8> Reserved <7..0> GPU Pipeline DM kick ID, 0 if not using Pipeline DMs */ + IMG_UINT32 ui32Padding; /*!< Reserved. To ensure correct alignment */ + IMG_UINT32 aui32CountBlksStream[RGX_HWPERF_ZERO_OR_MORE_ELEMENTS]; /*!< Optional variable length Counter data */ + IMG_UINT32 ui32Padding2; /*!< Reserved. To ensure correct alignment (not written in the packet) */ } RGX_HWPERF_HW_DATA; RGX_FW_STRUCT_SIZE_ASSERT(RGX_HWPERF_HW_DATA); +RGX_FW_STRUCT_OFFSET_ASSERT(RGX_HWPERF_HW_DATA, aui32CountBlksStream); typedef struct { @@ -914,6 +524,26 @@ typedef struct RGX_FW_STRUCT_SIZE_ASSERT(RGX_HWPERF_BVNC); +/*! Performance Counter Configuration data element. */ +typedef struct +{ + IMG_UINT32 ui32BlockID; /*!< Counter Block ID. See RGX_HWPERF_CNTBLK_ID */ + IMG_UINT32 ui32NumCounters; /*!< Number of counters configured */ + IMG_UINT32 ui32CounterVals[RGX_CNTBLK_COUNTERS_MAX]; /*!< Counters configured (ui32NumCounters worth of entries) */ +} RGX_HWPERF_COUNTER_CFG_DATA_EL; + +RGX_FW_STRUCT_SIZE_ASSERT(RGX_HWPERF_COUNTER_CFG_DATA_EL); + +/*! Performance Counter Configuration data. */ +typedef struct +{ + IMG_UINT32 ui32EnabledBlocks; /*!< Number of Enabled Blocks. */ + RGX_HWPERF_COUNTER_CFG_DATA_EL uData; /*!< Start of variable length data. See RGX_HWPERF_COUNTER_CFG_DATA_EL */ + IMG_UINT32 ui32Padding; /*!< reserved */ +} RGX_HWPERF_COUNTER_CFG; + +RGX_FW_STRUCT_SIZE_ASSERT(RGX_HWPERF_COUNTER_CFG); + /*! Sub-event's data. */ typedef union { @@ -930,7 +560,7 @@ typedef union IMG_UINT32 ui32EvMaskLo; /*!< Low order 32 bits of Filter Mask */ IMG_UINT32 ui32EvMaskHi; /*!< High order 32 bits of Filter Mask */ } sEvMsk; /*!< HW Filter Mask */ - + RGX_HWPERF_COUNTER_CFG sPCC; /*!< Performance Counter Config. See RGX_HWPERF_COUNTER_CFG */ } RGX_HWPERF_FWACT_DETAIL; RGX_FW_STRUCT_SIZE_ASSERT(RGX_HWPERF_FWACT_DETAIL); @@ -1456,6 +1086,49 @@ typedef struct static_assert((sizeof(RGX_HWPERF_HOST_SYNC_SW_TL_ADV_DATA) & (PVRSRVTL_PACKET_ALIGNMENT-1U)) == 0U, "sizeof(RGX_HWPERF_HOST_SYNC_SW_TL_ADV_DATA) must be a multiple PVRSRVTL_PACKET_ALIGNMENT"); +typedef enum +{ + RGX_HWPERF_HOST_CLIENT_INFO_TYPE_INVALID = 0, /*!< Invalid */ + RGX_HWPERF_HOST_CLIENT_INFO_TYPE_PROCESS_NAME, /*!< Process Name */ + + RGX_HWPERF_HOST_CLIENT_INFO_TYPE_LAST, /*!< Do not use */ +} RGX_HWPERF_HOST_CLIENT_INFO_TYPE; + +typedef struct +{ + IMG_PID uiClientPID; /*!< Client process identifier */ + IMG_UINT32 ui32Length; /*!< Number of bytes present in ``acName`` */ + IMG_CHAR acName[RGX_HWPERF_ONE_OR_MORE_ELEMENTS]; /*!< Process name string, null terminated */ +} RGX_HWPERF_HOST_CLIENT_PROC_NAME; + +#define RGX_HWPERF_HOST_CLIENT_PROC_NAME_SIZE(ui32NameLen) \ + ((IMG_UINT32)(offsetof(RGX_HWPERF_HOST_CLIENT_PROC_NAME, acName) + (ui32NameLen))) + +typedef union +{ + struct + { + IMG_UINT32 ui32Count; /*!< Number of elements in ``asProcNames`` */ + RGX_HWPERF_HOST_CLIENT_PROC_NAME asProcNames[RGX_HWPERF_ONE_OR_MORE_ELEMENTS]; + } sProcName; +} RGX_HWPERF_HOST_CLIENT_INFO_DETAIL; + +typedef struct +{ + IMG_UINT32 uiReserved1; /*!< Reserved. Align structure size to 8 bytes */ + RGX_HWPERF_HOST_CLIENT_INFO_TYPE eType; + /*!< Type of the subevent, see + RGX_HWPERF_HOST_CLIENT_INFO_TYPE */ + RGX_HWPERF_HOST_CLIENT_INFO_DETAIL uDetail; + /*!< Union of structures. Size of data + varies with union member that is present, + check ``eType`` value to decode */ + +} RGX_HWPERF_HOST_CLIENT_INFO_DATA; + +static_assert((sizeof(RGX_HWPERF_HOST_CLIENT_INFO_DATA) & (PVRSRVTL_PACKET_ALIGNMENT-1U)) == 0U, + "sizeof(RGX_HWPERF_HOST_CLIENT_INFO_DATA) must be a multiple PVRSRVTL_PACKET_ALIGNMENT"); + typedef enum { RGX_HWPERF_RESOURCE_CAPTURE_TYPE_NONE, @@ -1581,6 +1254,9 @@ typedef union events ``0x09`` (Host) */ RGX_HWPERF_HOST_SYNC_SW_TL_ADV_DATA sSWTLADV; /*!< Host SW-timeline advance data, events ``0x0A`` (Host) */ + RGX_HWPERF_HOST_CLIENT_INFO_DATA sHClientInfo; /*!< Host client info, + events ``0x0B`` (Host) */ + } RGX_HWPERF_V2_PACKET_DATA, *RGX_PHWPERF_V2_PACKET_DATA; RGX_FW_STRUCT_SIZE_ASSERT(RGX_HWPERF_V2_PACKET_DATA); @@ -1612,7 +1288,11 @@ typedef IMG_UINT32 RGX_HWPERF_CNTBLK_ID; #define RGX_CNTBLK_ID_HUB 0x0002U /*!< Non-cluster grouping cores */ #define RGX_CNTBLK_ID_TORNADO 0x0003U /*!< XT cores */ #define RGX_CNTBLK_ID_JONES 0x0004U /*!< S7 cores */ +#if defined(RGX_FEATURE_HWPERF_OCEANIC) +#define RGX_CNTBLK_ID_DIRECT_LAST 0x0003U /*!< Indirect blocks start from here */ +#else #define RGX_CNTBLK_ID_DIRECT_LAST 0x0005U /*!< Indirect blocks start from here */ +#endif /* defined(RGX_FEATURE_HWPERF_OCEANIC) */ #define RGX_CNTBLK_ID_BF_DEPRECATED 0x0005U /*!< Doppler unit (DEPRECATED) */ #define RGX_CNTBLK_ID_BT_DEPRECATED 0x0006U /*!< Doppler unit (DEPRECATED) */ @@ -1747,6 +1427,19 @@ typedef IMG_UINT32 RGX_HWPERF_CNTBLK_ID; /*! The number of layout blocks defined with configurable multiplexed * performance counters, hence excludes custom counter blocks. */ +#if defined(RGX_FEATURE_HWPERF_OCEANIC) +#define RGX_HWPERF_MAX_MUX_BLKS (\ + (IMG_UINT32)RGX_CNTBLK_ID_DIRECT_LAST +\ + RGX_CNTBLK_INDIRECT_COUNT(PBE, 0) ) + +#define RGX_HWPERF_MAX_DA_BLKS (\ + (IMG_UINT32)RGX_CNTBLK_INDIRECT_COUNT(TPU_MCU, 0)+\ + RGX_CNTBLK_INDIRECT_COUNT(USC, 0) ) + +#define RGX_HWPERF_MAX_DEFINED_BLKS (\ + (IMG_UINT32)RGX_HWPERF_MAX_MUX_BLKS +\ + RGX_HWPERF_MAX_DA_BLKS ) +#else #define RGX_HWPERF_MAX_DEFINED_BLKS (\ (IMG_UINT32)RGX_CNTBLK_ID_DIRECT_LAST +\ RGX_CNTBLK_INDIRECT_COUNT(TPU_MCU, 7)+\ @@ -1755,12 +1448,15 @@ typedef IMG_UINT32 RGX_HWPERF_CNTBLK_ID; RGX_CNTBLK_INDIRECT_COUNT(RASTER, 3)+\ RGX_CNTBLK_INDIRECT_COUNT(BLACKPEARL, 3)+\ RGX_CNTBLK_INDIRECT_COUNT(PBE, 15) ) +#define RGX_HWPERF_MAX_MUX_BLKS (\ + RGX_HWPERF_MAX_DEFINED_BLKS ) +#endif static_assert( ((RGX_CNTBLK_ID_DIRECT_LAST + ((RGX_CNTBLK_ID_LAST & RGX_CNTBLK_ID_GROUP_MASK) >> RGX_CNTBLK_ID_GROUP_SHIFT)) <= RGX_HWPERF_MAX_BVNC_BLOCK_LEN), "RGX_HWPERF_MAX_BVNC_BLOCK_LEN insufficient"); -#define RGX_HWPERF_EVENT_MASK_VALUE(e) (IMG_UINT64_C(1) << (e)) +#define RGX_HWPERF_EVENT_MASK_VALUE(e) (IMG_UINT64_C(1) << (IMG_UINT32)(e)) #define RGX_CUSTOM_FW_CNTRS \ X(TA_LOCAL_FL_SIZE, 0x0, RGX_HWPERF_EVENT_MASK_VALUE(RGX_HWPERF_HW_TAKICK) | \ diff --git a/drivers/gpu/drm/img-rogue/rgx_hwperf_common.h b/drivers/gpu/drm/img-rogue/rgx_hwperf_common.h new file mode 100644 index 000000000..0635a5157 --- /dev/null +++ b/drivers/gpu/drm/img-rogue/rgx_hwperf_common.h @@ -0,0 +1,482 @@ +/*************************************************************************/ /*! +@File +@Title RGX HWPerf and Debug Types and Defines Header +@Copyright Copyright (c) Imagination Technologies Ltd. All Rights Reserved +@Description Common data types definitions for hardware performance API +@License Dual MIT/GPLv2 + +The contents of this file are subject to the MIT license as set out below. + +Permission is hereby granted, free of charge, to any person obtaining a copy +of this software and associated documentation files (the "Software"), to deal +in the Software without restriction, including without limitation the rights +to use, copy, modify, merge, publish, distribute, sublicense, and/or sell +copies of the Software, and to permit persons to whom the Software is +furnished to do so, subject to the following conditions: + +The above copyright notice and this permission notice shall be included in +all copies or substantial portions of the Software. + +Alternatively, the contents of this file may be used under the terms of +the GNU General Public License Version 2 ("GPL") in which case the provisions +of GPL are applicable instead of those above. + +If you wish to allow use of your version of this file only under the terms of +GPL, and not to allow others to use your version of this file under the terms +of the MIT license, indicate your decision by deleting the provisions above +and replace them with the notice and other provisions required by GPL as set +out in the file called "GPL-COPYING" included in this distribution. If you do +not delete the provisions above, a recipient may use your version of this file +under the terms of either the MIT license or GPL. + +This License is also included in this distribution in the file called +"MIT-COPYING". + +EXCEPT AS OTHERWISE STATED IN A NEGOTIATED AGREEMENT: (A) THE SOFTWARE IS +PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING +BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR +PURPOSE AND NONINFRINGEMENT; AND (B) IN NO EVENT SHALL THE AUTHORS OR +COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER +IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN +CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +*/ /**************************************************************************/ +#ifndef RGX_HWPERF_COMMON_H_ +#define RGX_HWPERF_COMMON_H_ + +#if defined(__cplusplus) +extern "C" { +#endif + +/* These structures are used on both GPU and CPU and must be a size that is a + * multiple of 64 bits, 8 bytes to allow the FW to write 8 byte quantities at + * 8 byte aligned addresses. RGX_FW_STRUCT_*_ASSERT() is used to check this. + */ + +/****************************************************************************** + * Includes and Defines + *****************************************************************************/ + +#include "img_types.h" +#include "img_defs.h" + +#include "rgx_common_asserts.h" +#include "pvrsrv_tlcommon.h" + + +/****************************************************************************** + * Packet Event Type Enumerations + *****************************************************************************/ + +/*! Type used to encode the event that generated the packet. + * NOTE: When this type is updated the corresponding hwperfbin2json tool + * source needs to be updated as well. The RGX_HWPERF_EVENT_MASK_* macros will + * also need updating when adding new types. + * + * @par + * The event type values are incrementing integers for use as a shift ordinal + * in the event filtering process at the point events are generated. + * This scheme thus implies a limit of 63 event types. + */ + +typedef IMG_UINT32 RGX_HWPERF_EVENT_TYPE; + +#define RGX_HWPERF_INVALID 0x00U /*!< Invalid. Reserved value. */ + +/*! FW types 0x01..0x06 */ +#define RGX_HWPERF_FW_EVENT_RANGE_FIRST_TYPE 0x01U + +#define RGX_HWPERF_FW_BGSTART 0x01U /*!< Background task processing start */ +#define RGX_HWPERF_FW_BGEND 0x02U /*!< Background task end */ +#define RGX_HWPERF_FW_IRQSTART 0x03U /*!< IRQ task processing start */ + +#define RGX_HWPERF_FW_IRQEND 0x04U /*!< IRQ task end */ +#define RGX_HWPERF_FW_DBGSTART 0x05U /*!< Debug event start */ +#define RGX_HWPERF_FW_DBGEND 0x06U /*!< Debug event end */ + +#define RGX_HWPERF_FW_EVENT_RANGE_LAST_TYPE 0x06U + +/*! HW types 0x07..0x19 */ +#define RGX_HWPERF_HW_EVENT_RANGE0_FIRST_TYPE 0x07U + +#define RGX_HWPERF_HW_PMOOM_TAPAUSE 0x07U /*!< TA Pause at PM Out of Memory */ + +#define RGX_HWPERF_HW_TAKICK 0x08U /*!< TA task started */ +#define RGX_HWPERF_HW_TAFINISHED 0x09U /*!< TA task finished */ +#define RGX_HWPERF_HW_3DTQKICK 0x0AU /*!< 3D TQ started */ +#define RGX_HWPERF_HW_3DKICK 0x0BU /*!< 3D task started */ +#define RGX_HWPERF_HW_3DFINISHED 0x0CU /*!< 3D task finished */ +#define RGX_HWPERF_HW_CDMKICK 0x0DU /*!< CDM task started */ +#define RGX_HWPERF_HW_CDMFINISHED 0x0EU /*!< CDM task finished */ +#define RGX_HWPERF_HW_TLAKICK 0x0FU /*!< TLA task started */ +#define RGX_HWPERF_HW_TLAFINISHED 0x10U /*!< TLS task finished */ +#define RGX_HWPERF_HW_3DSPMKICK 0x11U /*!< 3D SPM task started */ +#define RGX_HWPERF_HW_PERIODIC 0x12U /*!< Periodic event with updated HW counters */ +#define RGX_HWPERF_HW_RTUKICK 0x13U /*!< Reserved, future use */ +#define RGX_HWPERF_HW_RTUFINISHED 0x14U /*!< Reserved, future use */ +#define RGX_HWPERF_HW_SHGKICK 0x15U /*!< Reserved, future use */ +#define RGX_HWPERF_HW_SHGFINISHED 0x16U /*!< Reserved, future use */ +#define RGX_HWPERF_HW_3DTQFINISHED 0x17U /*!< 3D TQ finished */ +#define RGX_HWPERF_HW_3DSPMFINISHED 0x18U /*!< 3D SPM task finished */ + +#define RGX_HWPERF_HW_PMOOM_TARESUME 0x19U /*!< TA Resume after PM Out of Memory */ + +/*! HW_EVENT_RANGE0 used up. Use next empty range below to add new hardware events */ +#define RGX_HWPERF_HW_EVENT_RANGE0_LAST_TYPE 0x19U + +/*! other types 0x1A..0x1F */ +#define RGX_HWPERF_CLKS_CHG 0x1AU /*!< Clock speed change in GPU */ +#define RGX_HWPERF_GPU_STATE_CHG 0x1BU /*!< GPU work state change */ + +/*! power types 0x20..0x27 */ +#define RGX_HWPERF_PWR_EST_RANGE_FIRST_TYPE 0x20U +#define RGX_HWPERF_PWR_EST_REQUEST 0x20U /*!< Power estimate requested (via GPIO) */ +#define RGX_HWPERF_PWR_EST_READY 0x21U /*!< Power estimate inputs ready */ +#define RGX_HWPERF_PWR_EST_RESULT 0x22U /*!< Power estimate result calculated */ +#define RGX_HWPERF_PWR_EST_RANGE_LAST_TYPE 0x22U + +#define RGX_HWPERF_PWR_CHG 0x23U /*!< Power state change */ + +/*! HW_EVENT_RANGE1 0x28..0x2F, for accommodating new hardware events */ +#define RGX_HWPERF_HW_EVENT_RANGE1_FIRST_TYPE 0x28U + +#define RGX_HWPERF_HW_TDMKICK 0x28U /*!< TDM task started */ +#define RGX_HWPERF_HW_TDMFINISHED 0x29U /*!< TDM task finished */ +#define RGX_HWPERF_HW_NULLKICK 0x2AU /*!< NULL event */ + +#define RGX_HWPERF_HW_EVENT_RANGE1_LAST_TYPE 0x2AU + +/*! context switch types 0x30..0x31 */ +#define RGX_HWPERF_CSW_START 0x30U /*!< HW context store started */ +#define RGX_HWPERF_CSW_FINISHED 0x31U /*!< HW context store finished */ + +/*! DVFS events */ +#define RGX_HWPERF_DVFS 0x32U /*!< Dynamic voltage/frequency scaling events */ + +/*! firmware misc 0x38..0x39 */ +#define RGX_HWPERF_UFO 0x38U /*!< FW UFO Check / Update */ +#define RGX_HWPERF_FWACT 0x39U /*!< FW Activity notification */ + +/*! last */ +#define RGX_HWPERF_LAST_TYPE 0x3BU + +/*! This enumeration must have a value that is a power of two as it is + * used in masks and a filter bit field (currently 64 bits long). + */ +#define RGX_HWPERF_MAX_TYPE 0x40U + +static_assert(RGX_HWPERF_LAST_TYPE < RGX_HWPERF_MAX_TYPE, "Too many HWPerf event types"); + +/*! Macro used to check if an event type ID is present in the known set of hardware type events */ +#define HWPERF_PACKET_IS_HW_TYPE(_etype) (((_etype) >= RGX_HWPERF_HW_EVENT_RANGE0_FIRST_TYPE && (_etype) <= RGX_HWPERF_HW_EVENT_RANGE0_LAST_TYPE) || \ + ((_etype) >= RGX_HWPERF_HW_EVENT_RANGE1_FIRST_TYPE && (_etype) <= RGX_HWPERF_HW_EVENT_RANGE1_LAST_TYPE)) + +/*! Macro used to check if an event type ID is present in the known set of firmware type events */ +#define HWPERF_PACKET_IS_FW_TYPE(_etype) \ + ((_etype) >= RGX_HWPERF_FW_EVENT_RANGE_FIRST_TYPE && \ + (_etype) <= RGX_HWPERF_FW_EVENT_RANGE_LAST_TYPE) + + +typedef enum { + RGX_HWPERF_HOST_INVALID = 0x00, /*!< Invalid, do not use. */ + RGX_HWPERF_HOST_ENQ = 0x01, /*!< ``0x01`` Kernel driver has queued GPU work. + See RGX_HWPERF_HOST_ENQ_DATA */ + RGX_HWPERF_HOST_UFO = 0x02, /*!< ``0x02`` UFO updated by the driver. + See RGX_HWPERF_HOST_UFO_DATA */ + RGX_HWPERF_HOST_ALLOC = 0x03, /*!< ``0x03`` Resource allocated. + See RGX_HWPERF_HOST_ALLOC_DATA */ + RGX_HWPERF_HOST_CLK_SYNC = 0x04, /*!< ``0x04`` GPU / Host clocks correlation data. + See RGX_HWPERF_HOST_CLK_SYNC_DATA */ + RGX_HWPERF_HOST_FREE = 0x05, /*!< ``0x05`` Resource freed, + See RGX_HWPERF_HOST_FREE_DATA */ + RGX_HWPERF_HOST_MODIFY = 0x06, /*!< ``0x06`` Resource modified / updated. + See RGX_HWPERF_HOST_MODIFY_DATA */ + RGX_HWPERF_HOST_DEV_INFO = 0x07, /*!< ``0x07`` Device Health status. + See RGX_HWPERF_HOST_DEV_INFO_DATA */ + RGX_HWPERF_HOST_INFO = 0x08, /*!< ``0x08`` Device memory usage information. + See RGX_HWPERF_HOST_INFO_DATA */ + RGX_HWPERF_HOST_SYNC_FENCE_WAIT = 0x09, /*!< ``0x09`` Wait for sync event. + See RGX_HWPERF_HOST_SYNC_FENCE_WAIT_DATA */ + RGX_HWPERF_HOST_SYNC_SW_TL_ADVANCE = 0x0A, /*!< ``0x0A`` Software timeline advanced. + See RGX_HWPERF_HOST_SYNC_SW_TL_ADV_DATA */ + RGX_HWPERF_HOST_CLIENT_INFO = 0x0B, /*!< ``0x0B`` Additional client info. + See RGX_HWPERF_HOST_CLIENT_INFO_DATA */ + + /*! last */ + RGX_HWPERF_HOST_LAST_TYPE, + + /*! This enumeration must have a value that is a power of two as it is + * used in masks and a filter bit field (currently 32 bits long). + */ + RGX_HWPERF_HOST_MAX_TYPE = 0x20 +} RGX_HWPERF_HOST_EVENT_TYPE; + +/*!< The event type values are incrementing integers for use as a shift ordinal + * in the event filtering process at the point events are generated. + * This scheme thus implies a limit of 31 event types. + */ +static_assert(RGX_HWPERF_HOST_LAST_TYPE < RGX_HWPERF_HOST_MAX_TYPE, "Too many HWPerf host event types"); + + +/****************************************************************************** + * Packet Header Format Version 2 Types + *****************************************************************************/ + +/*! Major version number of the protocol in operation + */ +#define RGX_HWPERF_V2_FORMAT 2 + +/*! Signature ASCII pattern 'HWP2' found in the first word of a HWPerfV2 packet + */ +#define HWPERF_PACKET_V2_SIG 0x48575032 + +/*! Signature ASCII pattern 'HWPA' found in the first word of a HWPerfV2a packet + */ +#define HWPERF_PACKET_V2A_SIG 0x48575041 + +/*! Signature ASCII pattern 'HWPB' found in the first word of a HWPerfV2b packet + */ +#define HWPERF_PACKET_V2B_SIG 0x48575042 + +/*! Signature ASCII pattern 'HWPC' found in the first word of a HWPerfV2c packet + */ +#define HWPERF_PACKET_V2C_SIG 0x48575043 + +#define HWPERF_PACKET_ISVALID(_val) (((_val) == HWPERF_PACKET_V2_SIG) || ((_val) == HWPERF_PACKET_V2A_SIG) || ((_val) == HWPERF_PACKET_V2B_SIG) || ((_val) == HWPERF_PACKET_V2C_SIG)) +/*!< Checks that the packet signature is one of the supported versions */ + +/*! Type defines the HWPerf packet header common to all events. */ +typedef struct +{ + IMG_UINT32 ui32Sig; /*!< Always the value HWPERF_PACKET_SIG */ + IMG_UINT32 ui32Size; /*!< Overall packet size in bytes */ + IMG_UINT32 eTypeId; /*!< Event type information field */ + IMG_UINT32 ui32Ordinal; /*!< Sequential number of the packet */ + IMG_UINT64 ui64Timestamp; /*!< Event timestamp */ +} RGX_HWPERF_V2_PACKET_HDR, *RGX_PHWPERF_V2_PACKET_HDR; + +RGX_FW_STRUCT_OFFSET_ASSERT(RGX_HWPERF_V2_PACKET_HDR, ui64Timestamp); + +RGX_FW_STRUCT_SIZE_ASSERT(RGX_HWPERF_V2_PACKET_HDR); + + +/*! Mask for use with the IMG_UINT32 ui32Size header field */ +#define RGX_HWPERF_SIZE_MASK 0xFFFFU + +/*! This macro defines an upper limit to which the size of the largest variable + * length HWPerf packet must fall within, currently 3KB. This constant may be + * used to allocate a buffer to hold one packet. + * This upper limit is policed by packet producing code. + */ +#define RGX_HWPERF_MAX_PACKET_SIZE 0xC00U + +/*! Defines an upper limit to the size of a variable length packet payload. + */ +#define RGX_HWPERF_MAX_PAYLOAD_SIZE ((IMG_UINT32)(RGX_HWPERF_MAX_PACKET_SIZE-\ + sizeof(RGX_HWPERF_V2_PACKET_HDR))) + +/*! Macro which takes a structure name and provides the packet size for + * a fixed size payload packet, rounded up to 8 bytes to align packets + * for 64 bit architectures. */ +#define RGX_HWPERF_MAKE_SIZE_FIXED(_struct) ((IMG_UINT32)(RGX_HWPERF_SIZE_MASK&(sizeof(RGX_HWPERF_V2_PACKET_HDR)+PVR_ALIGN(sizeof(_struct), PVRSRVTL_PACKET_ALIGNMENT)))) + +/*! Macro which takes the number of bytes written in the data payload of a + * packet for a variable size payload packet, rounded up to 8 bytes to + * align packets for 64 bit architectures. */ +#define RGX_HWPERF_MAKE_SIZE_VARIABLE(_size) ((IMG_UINT32)(RGX_HWPERF_SIZE_MASK&((IMG_UINT32)sizeof(RGX_HWPERF_V2_PACKET_HDR)+PVR_ALIGN((_size), PVRSRVTL_PACKET_ALIGNMENT)))) + +/*! Macro to obtain the size of the packet */ +#define RGX_HWPERF_GET_SIZE(_packet_addr) ((IMG_UINT16)(((_packet_addr)->ui32Size) & RGX_HWPERF_SIZE_MASK)) + +/*! Macro to obtain the size of the packet data */ +#define RGX_HWPERF_GET_DATA_SIZE(_packet_addr) (RGX_HWPERF_GET_SIZE(_packet_addr) - sizeof(RGX_HWPERF_V2_PACKET_HDR)) + +/*! Masks for use with the IMG_UINT32 eTypeId header field */ +#define RGX_HWPERF_TYPEID_MASK 0x0007FFFFU +#define RGX_HWPERF_TYPEID_EVENT_MASK 0x00007FFFU +#define RGX_HWPERF_TYPEID_THREAD_MASK 0x00008000U +#define RGX_HWPERF_TYPEID_STREAM_MASK 0x00070000U +#define RGX_HWPERF_TYPEID_META_DMA_MASK 0x00080000U +#define RGX_HWPERF_TYPEID_M_CORE_MASK 0x00100000U +#define RGX_HWPERF_TYPEID_OSID_MASK 0x07000000U + +/*! Meta thread macros for encoding the ID into the type field of a packet */ +#define RGX_HWPERF_META_THREAD_SHIFT 15U +#define RGX_HWPERF_META_THREAD_ID0 0x0U /*!< Meta Thread 0 ID */ +#define RGX_HWPERF_META_THREAD_ID1 0x1U /*!< Meta Thread 1 ID */ +/*! Obsolete, kept for source compatibility */ +#define RGX_HWPERF_META_THREAD_MASK 0x1U +/*! Stream ID macros for encoding the ID into the type field of a packet */ +#define RGX_HWPERF_STREAM_SHIFT 16U +/*! Meta DMA macro for encoding how the packet was generated into the type field of a packet */ +#define RGX_HWPERF_META_DMA_SHIFT 19U +/*! Bit-shift macro used for encoding multi-core data into the type field of a packet */ +#define RGX_HWPERF_M_CORE_SHIFT 20U +/*! OSID bit-shift macro used for encoding OSID into type field of a packet */ +#define RGX_HWPERF_OSID_SHIFT 24U +typedef enum { + RGX_HWPERF_STREAM_ID0_FW, /*!< Events from the Firmware/GPU */ + RGX_HWPERF_STREAM_ID1_HOST, /*!< Events from the Server host driver component */ + RGX_HWPERF_STREAM_ID2_CLIENT, /*!< Events from the Client host driver component */ + RGX_HWPERF_STREAM_ID_LAST, +} RGX_HWPERF_STREAM_ID; + +/* Checks if all stream IDs can fit under RGX_HWPERF_TYPEID_STREAM_MASK. */ +static_assert(((IMG_UINT32)RGX_HWPERF_STREAM_ID_LAST - 1U) < (RGX_HWPERF_TYPEID_STREAM_MASK >> RGX_HWPERF_STREAM_SHIFT), + "Too many HWPerf stream IDs."); + +/*! Compile-time value used to seed the Multi-Core (MC) bit in the typeID field. + * Only set by RGX_FIRMWARE builds. + */ +#if defined(RGX_FIRMWARE) +# if defined(RGX_FEATURE_GPU_MULTICORE_SUPPORT) +#define RGX_HWPERF_M_CORE_VALUE 1U /*!< 1 => Multi-core supported */ +# else +#define RGX_HWPERF_M_CORE_VALUE 0U /*!< 0 => Multi-core not supported */ +# endif +#else +#define RGX_HWPERF_M_CORE_VALUE 0U /*!< 0 => Multi-core not supported */ +#endif + +/*! Macros used to set the packet type and encode meta thread ID (0|1), + * HWPerf stream ID, multi-core capability and OSID within the typeID */ +#define RGX_HWPERF_MAKE_TYPEID(_stream, _type, _thread, _metadma, _osid)\ + ((IMG_UINT32) ((RGX_HWPERF_TYPEID_STREAM_MASK&((IMG_UINT32)(_stream) << RGX_HWPERF_STREAM_SHIFT)) | \ + (RGX_HWPERF_TYPEID_THREAD_MASK & ((IMG_UINT32)(_thread) << RGX_HWPERF_META_THREAD_SHIFT)) | \ + (RGX_HWPERF_TYPEID_EVENT_MASK & (IMG_UINT32)(_type)) | \ + (RGX_HWPERF_TYPEID_META_DMA_MASK & ((IMG_UINT32)(_metadma) << RGX_HWPERF_META_DMA_SHIFT)) | \ + (RGX_HWPERF_TYPEID_OSID_MASK & ((IMG_UINT32)(_osid) << RGX_HWPERF_OSID_SHIFT)) | \ + (RGX_HWPERF_TYPEID_M_CORE_MASK & ((IMG_UINT32)(RGX_HWPERF_M_CORE_VALUE) << RGX_HWPERF_M_CORE_SHIFT)))) + +/*! Obtains the event type that generated the packet */ +#define RGX_HWPERF_GET_TYPE(_packet_addr) (((_packet_addr)->eTypeId) & RGX_HWPERF_TYPEID_EVENT_MASK) + +/*! Obtains the META Thread number that generated the packet */ +#define RGX_HWPERF_GET_THREAD_ID(_packet_addr) (((((_packet_addr)->eTypeId) & RGX_HWPERF_TYPEID_THREAD_MASK) >> RGX_HWPERF_META_THREAD_SHIFT)) + +/*! Determines if the packet generated contains multi-core data */ +#define RGX_HWPERF_GET_M_CORE(_packet_addr) (((_packet_addr)->eTypeId & RGX_HWPERF_TYPEID_M_CORE_MASK) >> RGX_HWPERF_M_CORE_SHIFT) + +/*! Obtains the guest OSID which resulted in packet generation */ +#define RGX_HWPERF_GET_OSID(_packet_addr) (((_packet_addr)->eTypeId & RGX_HWPERF_TYPEID_OSID_MASK) >> RGX_HWPERF_OSID_SHIFT) + +/*! Obtain stream id */ +#define RGX_HWPERF_GET_STREAM_ID(_packet_addr) (((((_packet_addr)->eTypeId) & RGX_HWPERF_TYPEID_STREAM_MASK) >> RGX_HWPERF_STREAM_SHIFT)) + +/*! Obtain information about how the packet was generated, which might affect payload total size */ +#define RGX_HWPERF_GET_META_DMA_INFO(_packet_addr) (((((_packet_addr)->eTypeId) & RGX_HWPERF_TYPEID_META_DMA_MASK) >> RGX_HWPERF_META_DMA_SHIFT)) + +/*! Obtains a typed pointer to a packet given a buffer address */ +#define RGX_HWPERF_GET_PACKET(_buffer_addr) ((RGX_HWPERF_V2_PACKET_HDR *)(void *) (_buffer_addr)) +/*! Obtains a typed pointer to a data structure given a packet address */ +#define RGX_HWPERF_GET_PACKET_DATA_BYTES(_packet_addr) (IMG_OFFSET_ADDR((_packet_addr), sizeof(RGX_HWPERF_V2_PACKET_HDR))) +/*! Obtains a typed pointer to the next packet given a packet address */ +#define RGX_HWPERF_GET_NEXT_PACKET(_packet_addr) ((RGX_HWPERF_V2_PACKET_HDR *) (IMG_OFFSET_ADDR((_packet_addr), RGX_HWPERF_SIZE_MASK&((_packet_addr)->ui32Size)))) + +/*! Obtains a typed pointer to a packet header given the packet data address */ +#define RGX_HWPERF_GET_PACKET_HEADER(_packet_addr) ((RGX_HWPERF_V2_PACKET_HDR *) (IMG_OFFSET_ADDR((_packet_addr), -(IMG_INT32)sizeof(RGX_HWPERF_V2_PACKET_HDR)))) + + +/****************************************************************************** + * Other Common Defines + *****************************************************************************/ + +/*! This macro is not a real array size, but indicates the array has a variable + * length only known at run-time but always contains at least 1 element. The + * final size of the array is deduced from the size field of a packet header. + */ +#define RGX_HWPERF_ONE_OR_MORE_ELEMENTS 1U + +/*! This macro is not a real array size, but indicates the array is optional + * and if present has a variable length only known at run-time. The final + * size of the array is deduced from the size field of a packet header. */ +#define RGX_HWPERF_ZERO_OR_MORE_ELEMENTS 1U + + +/*! Masks for use with the IMG_UINT32 ui32BlkInfo field */ +#define RGX_HWPERF_BLKINFO_BLKCOUNT_MASK 0xFFFF0000U +#define RGX_HWPERF_BLKINFO_BLKOFFSET_MASK 0x0000FFFFU + +/*! Shift for the NumBlocks and counter block offset field in ui32BlkInfo */ +#define RGX_HWPERF_BLKINFO_BLKCOUNT_SHIFT 16U +#define RGX_HWPERF_BLKINFO_BLKOFFSET_SHIFT 0U + +/*! Macro used to set the block info word as a combination of two 16-bit integers */ +#define RGX_HWPERF_MAKE_BLKINFO(_numblks, _blkoffset) ((IMG_UINT32) ((RGX_HWPERF_BLKINFO_BLKCOUNT_MASK&((_numblks) << RGX_HWPERF_BLKINFO_BLKCOUNT_SHIFT)) | (RGX_HWPERF_BLKINFO_BLKOFFSET_MASK&((_blkoffset) << RGX_HWPERF_BLKINFO_BLKOFFSET_SHIFT)))) + +/*! Macro used to obtain the number of counter blocks present in the packet */ +#define RGX_HWPERF_GET_BLKCOUNT(_blkinfo) (((_blkinfo) & RGX_HWPERF_BLKINFO_BLKCOUNT_MASK) >> RGX_HWPERF_BLKINFO_BLKCOUNT_SHIFT) + +/*! Obtains the offset of the counter block stream in the packet */ +#define RGX_HWPERF_GET_BLKOFFSET(_blkinfo) (((_blkinfo) & RGX_HWPERF_BLKINFO_BLKOFFSET_MASK) >> RGX_HWPERF_BLKINFO_BLKOFFSET_SHIFT) + +/*! This macro gets the number of blocks depending on the packet version */ +#define RGX_HWPERF_GET_NUMBLKS(_sig, _packet_data, _numblocks) \ + do { \ + if (HWPERF_PACKET_V2B_SIG == (_sig) || HWPERF_PACKET_V2C_SIG == (_sig)) \ + { \ + (_numblocks) = RGX_HWPERF_GET_BLKCOUNT((_packet_data)->ui32BlkInfo);\ + } \ + else \ + { \ + IMG_UINT32 ui32VersionOffset = (((_sig) == HWPERF_PACKET_V2_SIG) ? 1 : 3);\ + (_numblocks) = *(IMG_UINT16 *)(IMG_OFFSET_ADDR(&(_packet_data)->ui32WorkTarget, ui32VersionOffset)); \ + } \ + } while (0) + +/*! This macro gets the counter stream pointer depending on the packet version */ +#define RGX_HWPERF_GET_CNTSTRM(_sig, _hw_packet_data, _cntstream_ptr) \ +{ \ + if (HWPERF_PACKET_V2B_SIG == (_sig) || HWPERF_PACKET_V2C_SIG == (_sig)) \ + { \ + (_cntstream_ptr) = (IMG_UINT32 *)(IMG_OFFSET_ADDR((_hw_packet_data), RGX_HWPERF_GET_BLKOFFSET((_hw_packet_data)->ui32BlkInfo))); \ + } \ + else \ + { \ + IMG_UINT32 ui32BlkStreamOffsetInWords = (((_sig) == HWPERF_PACKET_V2_SIG) ? 6 : 8); \ + (_cntstream_ptr) = (IMG_UINT32 *)(IMG_OFFSET_ADDR_DW((_hw_packet_data), ui32BlkStreamOffsetInWords)); \ + } \ +} + +/*! Masks for use with the IMG_UINT32 ui32KickInfo field */ +#define RGX_HWPERF_KICKINFO_KICKID_MASK 0x000000FFU + +/*! Shift for the Kick ID field in ui32KickInfo */ +#define RGX_HWPERF_KICKINFO_KICKID_SHIFT 0U + +/*! Macro used to set the kick info field. */ +#define RGX_HWPERF_MAKE_KICKINFO(_kickid) ((IMG_UINT32) (RGX_HWPERF_KICKINFO_KICKID_MASK&((_kickid) << RGX_HWPERF_KICKINFO_KICKID_SHIFT))) + +/*! Macro used to obtain the Kick ID if present in the packet */ +#define RGX_HWPERF_GET_KICKID(_kickinfo) (((_kickinfo) & RGX_HWPERF_KICKINFO_KICKID_MASK) >> RGX_HWPERF_KICKINFO_KICKID_SHIFT) + +/*! Masks for use with the RGX_HWPERF_UFO_EV eEvType field */ +#define RGX_HWPERF_UFO_STREAMSIZE_MASK 0xFFFF0000U +#define RGX_HWPERF_UFO_STREAMOFFSET_MASK 0x0000FFFFU + +/*! Shift for the UFO count and data stream fields */ +#define RGX_HWPERF_UFO_STREAMSIZE_SHIFT 16U +#define RGX_HWPERF_UFO_STREAMOFFSET_SHIFT 0U + +/*! Macro used to set UFO stream info word as a combination of two 16-bit integers */ +#define RGX_HWPERF_MAKE_UFOPKTINFO(_ssize, _soff) \ + ((IMG_UINT32) ((RGX_HWPERF_UFO_STREAMSIZE_MASK&((_ssize) << RGX_HWPERF_UFO_STREAMSIZE_SHIFT)) | \ + (RGX_HWPERF_UFO_STREAMOFFSET_MASK&((_soff) << RGX_HWPERF_UFO_STREAMOFFSET_SHIFT)))) + +/*! Macro used to obtain UFO count*/ +#define RGX_HWPERF_GET_UFO_STREAMSIZE(_streaminfo) \ + (((_streaminfo) & RGX_HWPERF_UFO_STREAMSIZE_MASK) >> RGX_HWPERF_UFO_STREAMSIZE_SHIFT) + +/*! Obtains the offset of the UFO stream in the packet */ +#define RGX_HWPERF_GET_UFO_STREAMOFFSET(_streaminfo) \ + (((_streaminfo) & RGX_HWPERF_UFO_STREAMOFFSET_MASK) >> RGX_HWPERF_UFO_STREAMOFFSET_SHIFT) + + +#if defined(__cplusplus) +} +#endif + +#endif /* RGX_HWPERF_COMMON_H_ */ + +/****************************************************************************** + End of file +******************************************************************************/ diff --git a/drivers/gpu/drm/img-rogue/rgx_hwperf_table.c b/drivers/gpu/drm/img-rogue/rgx_hwperf_table.c index 472dd57e4..268ba6520 100644 --- a/drivers/gpu/drm/img-rogue/rgx_hwperf_table.c +++ b/drivers/gpu/drm/img-rogue/rgx_hwperf_table.c @@ -158,12 +158,9 @@ static bool rgxfw_hwperf_pow_st_indirect(RGX_HWPERF_CNTBLK_ID eBlkType, IMG_UINT # define rgxfw_hwperf_pow_st_direct ((void*)NULL) # define rgxfw_hwperf_pow_st_indirect ((void*)NULL) -# define rgxfw_hwperf_pow_st_gandalf ((void*)NULL) #endif /* !defined(RGX_FIRMWARE) || !defined(RGX_FEATURE_PERFBUS) */ -# define rgxfw_hwperf_pow_st_gandalf ((void*)NULL) - /***************************************************************************** RGXFW_HWPERF_CNTBLK_TYPE_MODEL struct PFNs pfnIsBlkPowered() end *****************************************************************************/ diff --git a/drivers/gpu/drm/img-rogue/rgx_meta.h b/drivers/gpu/drm/img-rogue/rgx_meta.h index e88d21308..bdff11ffb 100644 --- a/drivers/gpu/drm/img-rogue/rgx_meta.h +++ b/drivers/gpu/drm/img-rogue/rgx_meta.h @@ -74,7 +74,7 @@ CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. #define META_CR_PERF_COUNT_THR_SHIFT (24) #define META_CR_PERF_COUNT_THR_MASK (0x0F000000) #define META_CR_PERF_COUNT_THR_0 (IMG_UINT32_C(0x1) << META_CR_PERF_COUNT_THR_SHIFT) -#define META_CR_PERF_COUNT_THR_1 (IMG_UINT32_C(0x2) << META_CR_PERF_COUNT_THR_1) +#define META_CR_PERF_COUNT_THR_1 (IMG_UINT32_C(0x2) << META_CR_PERF_COUNT_THR_SHIFT) #define META_CR_TxVECINT_BHALT (0x04820500) #define META_CR_PERF_ICORE0 (0x0480FFD0) @@ -248,11 +248,11 @@ typedef struct * The interface has been kept the same to simplify the code changes. * The bifdm argument is ignored (no longer relevant) in S7 and volcanic. */ -#define RGXFW_SEGMMU_OUTADDR_TOP_VIVT_SLC(pers, slc_policy, mmu_ctx) ((((IMG_UINT64) ((pers) & 0x3)) << 52) | \ - (((IMG_UINT64) ((mmu_ctx) & 0xFF)) << 44) | \ - (((IMG_UINT64) ((slc_policy) & 0x1)) << 40)) -#define RGXFW_SEGMMU_OUTADDR_TOP_VIVT_SLC_CACHED(mmu_ctx) RGXFW_SEGMMU_OUTADDR_TOP_VIVT_SLC(0x3, 0x0, mmu_ctx) -#define RGXFW_SEGMMU_OUTADDR_TOP_VIVT_SLC_UNCACHED(mmu_ctx) RGXFW_SEGMMU_OUTADDR_TOP_VIVT_SLC(0x0, 0x1, mmu_ctx) +#define RGXFW_SEGMMU_OUTADDR_TOP_VIVT_SLC(pers, slc_policy, mmu_ctx) ((((IMG_UINT64) ((pers) & 0x3U)) << 52) | \ + (((IMG_UINT64) ((mmu_ctx) & 0xFFU)) << 44) | \ + (((IMG_UINT64) ((slc_policy) & 0x1U)) << 40)) +#define RGXFW_SEGMMU_OUTADDR_TOP_VIVT_SLC_CACHED(mmu_ctx) RGXFW_SEGMMU_OUTADDR_TOP_VIVT_SLC(0x3U, 0x0U, mmu_ctx) +#define RGXFW_SEGMMU_OUTADDR_TOP_VIVT_SLC_UNCACHED(mmu_ctx) RGXFW_SEGMMU_OUTADDR_TOP_VIVT_SLC(0x0U, 0x1U, mmu_ctx) /* To configure the Page Catalog and BIF-DM fed into the BIF for Garten * accesses through this segment diff --git a/drivers/gpu/drm/img-rogue/rgx_mips.h b/drivers/gpu/drm/img-rogue/rgx_mips.h index d3947127f..c2f381882 100644 --- a/drivers/gpu/drm/img-rogue/rgx_mips.h +++ b/drivers/gpu/drm/img-rogue/rgx_mips.h @@ -72,7 +72,7 @@ CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. /* Total number of TLB entries */ #define RGXMIPSFW_NUMBER_OF_TLB_ENTRIES (16) /* "Uncached" caching policy */ -#define RGXMIPSFW_UNCACHED_CACHE_POLICY (0X00000002) +#define RGXMIPSFW_UNCACHED_CACHE_POLICY (0X00000002U) /* "Write-back write-allocate" caching policy */ #define RGXMIPSFW_WRITEBACK_CACHE_POLICY (0X00000003) /* "Write-through no write-allocate" caching policy */ @@ -91,11 +91,11 @@ CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. #define RGXMIPSFW_ENTRYLO_READ_INHIBIT_SHIFT (31U) #define RGXMIPSFW_ENTRYLO_READ_INHIBIT_CLRMSK (0X7FFFFFFF) -#define RGXMIPSFW_ENTRYLO_READ_INHIBIT_EN (0X80000000) +#define RGXMIPSFW_ENTRYLO_READ_INHIBIT_EN (0X80000000U) #define RGXMIPSFW_ENTRYLO_EXEC_INHIBIT_SHIFT (30U) #define RGXMIPSFW_ENTRYLO_EXEC_INHIBIT_CLRMSK (0XBFFFFFFF) -#define RGXMIPSFW_ENTRYLO_EXEC_INHIBIT_EN (0X40000000) +#define RGXMIPSFW_ENTRYLO_EXEC_INHIBIT_EN (0X40000000U) /* Page Frame Number */ #define RGXMIPSFW_ENTRYLO_PFN_SHIFT (6) @@ -104,25 +104,25 @@ CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. #define RGXMIPSFW_ENTRYLO_PFN_MASK (0x03FFFFC0) #define RGXMIPSFW_ENTRYLO_PFN_SIZE (20) /* Mask used for the MIPS Page Table in case of physical bus on more than 32 bit */ -#define RGXMIPSFW_ENTRYLO_PFN_MASK_ABOVE_32BIT (0x3FFFFFC0) +#define RGXMIPSFW_ENTRYLO_PFN_MASK_ABOVE_32BIT (0x3FFFFFC0U) #define RGXMIPSFW_ENTRYLO_PFN_SIZE_ABOVE_32BIT (24) #define RGXMIPSFW_ADDR_TO_ENTRYLO_PFN_RSHIFT (RGXMIPSFW_ENTRYLO_PFN_ALIGNSHIFT - \ RGXMIPSFW_ENTRYLO_PFN_SHIFT) #define RGXMIPSFW_ENTRYLO_CACHE_POLICY_SHIFT (3U) -#define RGXMIPSFW_ENTRYLO_CACHE_POLICY_CLRMSK (0XFFFFFFC7) +#define RGXMIPSFW_ENTRYLO_CACHE_POLICY_CLRMSK (0XFFFFFFC7U) #define RGXMIPSFW_ENTRYLO_DIRTY_SHIFT (2U) #define RGXMIPSFW_ENTRYLO_DIRTY_CLRMSK (0XFFFFFFFB) -#define RGXMIPSFW_ENTRYLO_DIRTY_EN (0X00000004) +#define RGXMIPSFW_ENTRYLO_DIRTY_EN (0X00000004U) #define RGXMIPSFW_ENTRYLO_VALID_SHIFT (1U) #define RGXMIPSFW_ENTRYLO_VALID_CLRMSK (0XFFFFFFFD) -#define RGXMIPSFW_ENTRYLO_VALID_EN (0X00000002) +#define RGXMIPSFW_ENTRYLO_VALID_EN (0X00000002U) #define RGXMIPSFW_ENTRYLO_GLOBAL_SHIFT (0U) #define RGXMIPSFW_ENTRYLO_GLOBAL_CLRMSK (0XFFFFFFFE) -#define RGXMIPSFW_ENTRYLO_GLOBAL_EN (0X00000001) +#define RGXMIPSFW_ENTRYLO_GLOBAL_EN (0X00000001U) #define RGXMIPSFW_ENTRYLO_DVG (RGXMIPSFW_ENTRYLO_DIRTY_EN | \ RGXMIPSFW_ENTRYLO_VALID_EN | \ @@ -158,14 +158,14 @@ CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. */ #define RGXMIPSFW_TRAMPOLINE_LOG2_NUMPAGES (2) -#define RGXMIPSFW_TRAMPOLINE_NUMPAGES (1 << RGXMIPSFW_TRAMPOLINE_LOG2_NUMPAGES) +#define RGXMIPSFW_TRAMPOLINE_NUMPAGES (1U << RGXMIPSFW_TRAMPOLINE_LOG2_NUMPAGES) #define RGXMIPSFW_TRAMPOLINE_SIZE (RGXMIPSFW_TRAMPOLINE_NUMPAGES << RGXMIPSFW_LOG2_PAGE_SIZE_4K) #define RGXMIPSFW_TRAMPOLINE_LOG2_SEGMENT_SIZE (RGXMIPSFW_TRAMPOLINE_LOG2_NUMPAGES + RGXMIPSFW_LOG2_PAGE_SIZE_4K) #define RGXMIPSFW_TRAMPOLINE_TARGET_PHYS_ADDR (RGXMIPSFW_BOOT_REMAP_PHYS_ADDR_IN) #define RGXMIPSFW_TRAMPOLINE_OFFSET(a) (a - RGXMIPSFW_BOOT_REMAP_PHYS_ADDR_IN) -#define RGXMIPSFW_SENSITIVE_ADDR(a) (RGXMIPSFW_BOOT_REMAP_PHYS_ADDR_IN == (~((1UL << RGXMIPSFW_TRAMPOLINE_LOG2_SEGMENT_SIZE)-1) & a)) +#define RGXMIPSFW_SENSITIVE_ADDR(a) (RGXMIPSFW_BOOT_REMAP_PHYS_ADDR_IN == (~((1UL << RGXMIPSFW_TRAMPOLINE_LOG2_SEGMENT_SIZE)-1U) & a)) /* * Firmware virtual layout and remap configuration @@ -183,20 +183,20 @@ CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. /* Boot remap setup */ #define RGXMIPSFW_BOOT_REMAP_VIRTUAL_BASE (0xBFC00000) -#define RGXMIPSFW_BOOT_REMAP_PHYS_ADDR_IN (0x1FC00000) +#define RGXMIPSFW_BOOT_REMAP_PHYS_ADDR_IN (0x1FC00000U) #define RGXMIPSFW_BOOT_REMAP_LOG2_SEGMENT_SIZE (12) #define RGXMIPSFW_BOOT_NMI_CODE_VIRTUAL_BASE (RGXMIPSFW_BOOT_REMAP_VIRTUAL_BASE) /* Data remap setup */ #define RGXMIPSFW_DATA_REMAP_VIRTUAL_BASE (0xBFC01000) #define RGXMIPSFW_DATA_CACHED_REMAP_VIRTUAL_BASE (0x9FC01000) -#define RGXMIPSFW_DATA_REMAP_PHYS_ADDR_IN (0x1FC01000) +#define RGXMIPSFW_DATA_REMAP_PHYS_ADDR_IN (0x1FC01000U) #define RGXMIPSFW_DATA_REMAP_LOG2_SEGMENT_SIZE (12) #define RGXMIPSFW_BOOT_NMI_DATA_VIRTUAL_BASE (RGXMIPSFW_DATA_REMAP_VIRTUAL_BASE) /* Code remap setup */ #define RGXMIPSFW_CODE_REMAP_VIRTUAL_BASE (0x9FC02000) -#define RGXMIPSFW_CODE_REMAP_PHYS_ADDR_IN (0x1FC02000) +#define RGXMIPSFW_CODE_REMAP_PHYS_ADDR_IN (0x1FC02000U) #define RGXMIPSFW_CODE_REMAP_LOG2_SEGMENT_SIZE (12) #define RGXMIPSFW_EXCEPTIONS_VIRTUAL_BASE (RGXMIPSFW_CODE_REMAP_VIRTUAL_BASE) @@ -211,7 +211,7 @@ CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. */ /* Bootloader configuration offset (where RGXMIPSFW_BOOT_DATA lives) * within the bootloader/NMI data page */ -#define RGXMIPSFW_BOOTLDR_CONF_OFFSET (0x0) +#define RGXMIPSFW_BOOTLDR_CONF_OFFSET (0x0U) /* @@ -292,10 +292,10 @@ typedef struct #define RGXMIPSFW_C0_NBHWIRQ 8 /* Macros to decode C0_Cause register */ -#define RGXMIPSFW_C0_CAUSE_EXCCODE(CAUSE) (((CAUSE) & 0x7c) >> 2) +#define RGXMIPSFW_C0_CAUSE_EXCCODE(CAUSE) (((CAUSE) & 0x7cU) >> 2U) #define RGXMIPSFW_C0_CAUSE_EXCCODE_FWERROR 9 /* Use only when Coprocessor Unusable exception */ -#define RGXMIPSFW_C0_CAUSE_UNUSABLE_UNIT(CAUSE) (((CAUSE) >> 28) & 0x3) +#define RGXMIPSFW_C0_CAUSE_UNUSABLE_UNIT(CAUSE) (((CAUSE) >> 28U) & 0x3U) #define RGXMIPSFW_C0_CAUSE_PENDING_HWIRQ(CAUSE) (((CAUSE) & 0x3fc00) >> 10) #define RGXMIPSFW_C0_CAUSE_FDCIPENDING (1UL << 21) #define RGXMIPSFW_C0_CAUSE_IV (1UL << 23) @@ -305,7 +305,7 @@ typedef struct #define RGXMIPSFW_C0_CAUSE_BRANCH_DELAY (1UL << 31) /* Macros to decode C0_Debug register */ -#define RGXMIPSFW_C0_DEBUG_EXCCODE(DEBUG) (((DEBUG) >> 10) & 0x1f) +#define RGXMIPSFW_C0_DEBUG_EXCCODE(DEBUG) (((DEBUG) >> 10U) & 0x1fU) #define RGXMIPSFW_C0_DEBUG_DSS (1UL << 0) #define RGXMIPSFW_C0_DEBUG_DBP (1UL << 1) #define RGXMIPSFW_C0_DEBUG_DDBL (1UL << 2) @@ -325,7 +325,7 @@ typedef struct /* Macros to decode TLB entries */ #define RGXMIPSFW_TLB_GET_MASK(PAGE_MASK) (((PAGE_MASK) >> 13) & 0XFFFFU) -#define RGXMIPSFW_TLB_GET_PAGE_SIZE(PAGE_MASK) ((((PAGE_MASK) | 0x1FFF) + 1) >> 11) /* page size in KB */ +#define RGXMIPSFW_TLB_GET_PAGE_SIZE(PAGE_MASK) ((((PAGE_MASK) | 0x1FFFU) + 1U) >> 11U) /* page size in KB */ #define RGXMIPSFW_TLB_GET_PAGE_MASK(PAGE_SIZE) ((((PAGE_SIZE) << 11) - 1) & ~0x7FF) /* page size in KB */ #define RGXMIPSFW_TLB_GET_VPN2(ENTRY_HI) ((ENTRY_HI) >> 13) #define RGXMIPSFW_TLB_GET_COHERENCY(ENTRY_LO) (((ENTRY_LO) >> 3) & 0x7U) diff --git a/drivers/gpu/drm/img-rogue/rgx_riscv.h b/drivers/gpu/drm/img-rogue/rgx_riscv.h index 1ce9ab569..e5be2a562 100644 --- a/drivers/gpu/drm/img-rogue/rgx_riscv.h +++ b/drivers/gpu/drm/img-rogue/rgx_riscv.h @@ -76,7 +76,7 @@ CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. #define RGXRISCVFW_COREMEM_REGION IMG_UINT32_C(0x8) #define RGXRISCVFW_COREMEM_MAX_SIZE IMG_UINT32_C(0x10000000) /* 256 MB */ #define RGXRISCVFW_COREMEM_BASE (RGXRISCVFW_GET_REGION_BASE(RGXRISCVFW_COREMEM_REGION)) -#define RGXRISCVFW_COREMEM_END (RGXRISCVFW_COREMEM_BASE + RGXRISCVFW_COREMEM_MAX_SIZE - 1) +#define RGXRISCVFW_COREMEM_END (RGXRISCVFW_COREMEM_BASE + RGXRISCVFW_COREMEM_MAX_SIZE - 1U) /* diff --git a/drivers/gpu/drm/img-rogue/rgxbreakpoint.c b/drivers/gpu/drm/img-rogue/rgxbreakpoint.c index 168d070cd..bd147dc62 100644 --- a/drivers/gpu/drm/img-rogue/rgxbreakpoint.c +++ b/drivers/gpu/drm/img-rogue/rgxbreakpoint.c @@ -91,7 +91,6 @@ PVRSRV_ERROR PVRSRVRGXSetBreakpointKM(CONNECTION_DATA * psConnection, eError = RGXScheduleCommandAndGetKCCBSlot(psDevInfo, eFWDataMaster, &sBPCmd, - 0, PDUMP_FLAGS_CONTINUOUS, &ui32kCCBCommandSlot); PVR_LOG_GOTO_IF_ERROR(eError, "RGXScheduleCommandAndGetKCCBSlot", unlock); @@ -138,7 +137,6 @@ PVRSRV_ERROR PVRSRVRGXClearBreakpointKM(CONNECTION_DATA * psConnection, eError = RGXScheduleCommandAndGetKCCBSlot(psDevInfo, psDevInfo->eBPDM, &sBPCmd, - 0, PDUMP_FLAGS_CONTINUOUS, &ui32kCCBCommandSlot); PVR_LOG_GOTO_IF_ERROR(eError, "RGXScheduleCommandAndGetKCCBSlot", unlock); @@ -188,7 +186,6 @@ PVRSRV_ERROR PVRSRVRGXEnableBreakpointKM(CONNECTION_DATA * psConnection, eError = RGXScheduleCommandAndGetKCCBSlot(psDevInfo, psDevInfo->eBPDM, &sBPCmd, - 0, PDUMP_FLAGS_CONTINUOUS, &ui32kCCBCommandSlot); PVR_LOG_GOTO_IF_ERROR(eError, "RGXScheduleCommandAndGetKCCBSlot", unlock); @@ -236,7 +233,6 @@ PVRSRV_ERROR PVRSRVRGXDisableBreakpointKM(CONNECTION_DATA * psConnection, eError = RGXScheduleCommandAndGetKCCBSlot(psDevInfo, psDevInfo->eBPDM, &sBPCmd, - 0, PDUMP_FLAGS_CONTINUOUS, &ui32kCCBCommandSlot); PVR_LOG_GOTO_IF_ERROR(eError, "RGXScheduleCommandAndGetKCCBSlot", unlock); @@ -275,7 +271,6 @@ PVRSRV_ERROR PVRSRVRGXOverallocateBPRegistersKM(CONNECTION_DATA * psConnectio eError = RGXScheduleCommandAndGetKCCBSlot(psDeviceNode->pvDevice, RGXFWIF_DM_GP, &sBPCmd, - 0, PDUMP_FLAGS_CONTINUOUS, &ui32kCCBCommandSlot); PVR_LOG_GOTO_IF_ERROR(eError, "RGXScheduleCommandAndGetKCCBSlot", unlock); diff --git a/drivers/gpu/drm/img-rogue/rgxbvnc.c b/drivers/gpu/drm/img-rogue/rgxbvnc.c index 20eff3e83..6c29beef2 100644 --- a/drivers/gpu/drm/img-rogue/rgxbvnc.c +++ b/drivers/gpu/drm/img-rogue/rgxbvnc.c @@ -57,7 +57,7 @@ CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. static IMG_UINT64* _RGXSearchBVNCTable( IMG_UINT64 *pui64Array, IMG_UINT uiEnd, IMG_UINT64 ui64SearchValue, - IMG_UINT uiRowCount) + IMG_UINT uiColCount) { IMG_UINT uiStart = 0, index; IMG_UINT64 value, *pui64Ptr = NULL; @@ -65,7 +65,7 @@ static IMG_UINT64* _RGXSearchBVNCTable( IMG_UINT64 *pui64Array, while (uiStart < uiEnd) { index = (uiStart + uiEnd)/2; - pui64Ptr = pui64Array + (index * uiRowCount); + pui64Ptr = pui64Array + (index * uiColCount); value = *(pui64Ptr); if (value == ui64SearchValue) @@ -104,23 +104,29 @@ static void _RGXBvncDumpParsedConfig(PVRSRV_DEVICE_NODE *psDeviceNode) PVR_LOG_DUMP_FEATURE_VALUE(psDevInfo, "NC: ", NUM_CLUSTERS); PVR_LOG_DUMP_FEATURE_VALUE(psDevInfo, "CSF: ", CDM_CONTROL_STREAM_FORMAT); PVR_LOG_DUMP_FEATURE_VALUE(psDevInfo, "FBCDCA: ", FBCDC_ARCHITECTURE); +#if defined(RGX_FEATURE_META_MAX_VALUE_IDX) + PVR_LOG_DUMP_FEATURE_VALUE(psDevInfo, "META: ", META); PVR_LOG_DUMP_FEATURE_VALUE(psDevInfo, "MCMB: ", META_COREMEM_BANKS); PVR_LOG_DUMP_FEATURE_VALUE(psDevInfo, "MCMS: ", META_COREMEM_SIZE); PVR_LOG_DUMP_FEATURE_VALUE(psDevInfo, "MDMACnt: ", META_DMA_CHANNEL_COUNT); +#endif PVR_LOG_DUMP_FEATURE_VALUE(psDevInfo, "NIIP: ", NUM_ISP_IPP_PIPES); #if defined(RGX_FEATURE_NUM_ISP_PER_SPU_MAX_VALUE_IDX) PVR_LOG_DUMP_FEATURE_VALUE(psDevInfo, "NIPS: ", NUM_ISP_PER_SPU); +#endif +#if defined(RGX_FEATURE_PBE_PER_SPU_MAX_VALUE_IDX) PVR_LOG_DUMP_FEATURE_VALUE(psDevInfo, "PPS: ", PBE_PER_SPU); PVR_LOG_DUMP_FEATURE_VALUE(psDevInfo, "NSPU: ", NUM_SPU); #endif PVR_LOG_DUMP_FEATURE_VALUE(psDevInfo, "PBW: ", PHYS_BUS_WIDTH); +#if defined(RGX_FEATURE_SCALABLE_TE_ARCH_MAX_VALUE_IDX) PVR_LOG_DUMP_FEATURE_VALUE(psDevInfo, "STEArch: ", SCALABLE_TE_ARCH); PVR_LOG_DUMP_FEATURE_VALUE(psDevInfo, "SVCEA: ", SCALABLE_VCE); +#endif PVR_LOG_DUMP_FEATURE_VALUE(psDevInfo, "SLCBanks: ", SLC_BANKS); PVR_LOG_DUMP_FEATURE_VALUE(psDevInfo, "SLCCLS: ", SLC_CACHE_LINE_SIZE_BITS); PVR_LOG(("SLCSize: %d", psDevInfo->sDevFeatureCfg.ui32SLCSizeInBytes)); PVR_LOG_DUMP_FEATURE_VALUE(psDevInfo, "VASB: ", VIRTUAL_ADDRESS_SPACE_BITS); - PVR_LOG_DUMP_FEATURE_VALUE(psDevInfo, "META: ", META); PVR_LOG_DUMP_FEATURE_VALUE(psDevInfo, "NOSIDS: ", NUM_OSIDS); #if defined(FEATURE_NO_VALUES_NAMES_MAX_IDX) @@ -206,7 +212,6 @@ static void _RGXBvncParseFeatureValues(PVRSRV_RGXDEV_INFO *psDevInfo, IMG_UINT64 #if defined(RGX_FEATURE_POWER_ISLAND_VERSION_MAX_VALUE_IDX) /* Code path for Volcanic */ - /* Get the max number of DMs */ psDevInfo->sDevFeatureCfg.ui32MAXDMCount = RGXFWIF_DM_CDM+1; if (RGX_IS_FEATURE_VALUE_SUPPORTED(psDevInfo, RAY_TRACING_ARCH) && RGX_GET_FEATURE_VALUE(psDevInfo, RAY_TRACING_ARCH) > 1) @@ -215,22 +220,24 @@ static void _RGXBvncParseFeatureValues(PVRSRV_RGXDEV_INFO *psDevInfo, IMG_UINT64 } #if defined(SUPPORT_AGP) psDevInfo->sDevFeatureCfg.ui32MAXDMCount = MAX(psDevInfo->sDevFeatureCfg.ui32MAXDMCount, RGXFWIF_DM_GEOM2+1); +#if defined(SUPPORT_AGP4) + psDevInfo->sDevFeatureCfg.ui32MAXDMCount = MAX(psDevInfo->sDevFeatureCfg.ui32MAXDMCount, RGXFWIF_DM_GEOM4+1); +#endif #endif /* Get the max number of dusts in the core */ if (RGX_IS_FEATURE_VALUE_SUPPORTED(psDevInfo, NUM_CLUSTERS)) { - RGX_LAYER_PARAMS sParams; - - OSCachedMemSet(&sParams, 0, sizeof(RGX_LAYER_PARAMS)); - sParams.psDevInfo = psDevInfo; + RGX_LAYER_PARAMS sParams = {.psDevInfo = psDevInfo}; if (RGX_DEVICE_GET_FEATURE_VALUE(&sParams, POWER_ISLAND_VERSION) == 1) { + /* per SPU power island */ psDevInfo->sDevFeatureCfg.ui32MAXPowUnitCount = MAX(1, (RGX_GET_FEATURE_VALUE(psDevInfo, NUM_CLUSTERS) / 2)); } - else if (RGX_DEVICE_GET_FEATURE_VALUE(&sParams, POWER_ISLAND_VERSION) == 2) + else if (RGX_DEVICE_GET_FEATURE_VALUE(&sParams, POWER_ISLAND_VERSION) >= 2) { + /* per Cluster power island */ psDevInfo->sDevFeatureCfg.ui32MAXPowUnitCount = RGX_GET_FEATURE_VALUE(psDevInfo, NUM_CLUSTERS); } else @@ -240,6 +247,19 @@ static void _RGXBvncParseFeatureValues(PVRSRV_RGXDEV_INFO *psDevInfo, IMG_UINT64 PVR_DPF((PVR_DBG_ERROR, "%s: Power island feature version not found!", __func__)); PVR_ASSERT(0); } + + if (RGX_IS_FEATURE_VALUE_SUPPORTED(psDevInfo, RAY_TRACING_ARCH) && + RGX_GET_FEATURE_VALUE(psDevInfo, RAY_TRACING_ARCH) > 1) + { + if (RGX_IS_FEATURE_SUPPORTED(psDevInfo, RT_RAC_PER_SPU)) + { + psDevInfo->sDevFeatureCfg.ui32MAXRACCount = RGX_GET_FEATURE_VALUE(psDevInfo, NUM_SPU); + } + else + { + psDevInfo->sDevFeatureCfg.ui32MAXRACCount = 1; + } + } } else { @@ -248,13 +268,21 @@ static void _RGXBvncParseFeatureValues(PVRSRV_RGXDEV_INFO *psDevInfo, IMG_UINT64 PVR_DPF((PVR_DBG_ERROR, "%s: Number of clusters feature value missing!", __func__)); PVR_ASSERT(0); } -#else - /* Code path for Rogue */ +#else /* defined(RGX_FEATURE_POWER_ISLAND_VERSION_MAX_VALUE_IDX) */ + /* Code path for Rogue and Oceanic */ + psDevInfo->sDevFeatureCfg.ui32MAXDMCount = RGXFWIF_DM_CDM+1; +#if defined(SUPPORT_AGP) + psDevInfo->sDevFeatureCfg.ui32MAXDMCount = MAX(psDevInfo->sDevFeatureCfg.ui32MAXDMCount, RGXFWIF_DM_GEOM2+1); +#endif + + /* Meta feature not present in oceanic */ +#if defined(RGX_FEATURE_META_MAX_VALUE_IDX) if (RGX_IS_FEATURE_SUPPORTED(psDevInfo, MIPS)) { psDevInfo->sDevFeatureCfg.ui32FeaturesValues[RGX_FEATURE_META_IDX] = RGX_FEATURE_VALUE_DISABLED; } +#endif /* Get the max number of dusts in the core */ if (RGX_IS_FEATURE_VALUE_SUPPORTED(psDevInfo, NUM_CLUSTERS)) @@ -268,13 +296,16 @@ static void _RGXBvncParseFeatureValues(PVRSRV_RGXDEV_INFO *psDevInfo, IMG_UINT64 PVR_DPF((PVR_DBG_ERROR, "%s: Number of clusters feature value missing!", __func__)); PVR_ASSERT(0); } -#endif +#endif /* defined(RGX_FEATURE_POWER_ISLAND_VERSION_MAX_VALUE_IDX) */ + /* Meta feature not present in oceanic */ +#if defined(RGX_FEATURE_META_COREMEM_SIZE_MAX_VALUE_IDX) /* Transform the META coremem size info in bytes */ if (RGX_IS_FEATURE_VALUE_SUPPORTED(psDevInfo, META_COREMEM_SIZE)) { psDevInfo->sDevFeatureCfg.ui32FeaturesValues[RGX_FEATURE_META_COREMEM_SIZE_IDX] *= 1024; } +#endif } static void _RGXBvncAcquireAppHint(IMG_CHAR *pszBVNC, const IMG_UINT32 ui32RGXDevCount) @@ -398,8 +429,8 @@ static IMG_UINT32 _RGXBvncReadSLCSize(PVRSRV_DEVICE_NODE *psDeviceNode) PVRSRV_RGXDEV_INFO *psDevInfo = psDeviceNode->pvDevice; IMG_UINT64 ui64SLCSize = 0ULL; -#if defined(RGX_CR_CORE_ID__PBVNC) - /* Rogue hardware */ +#if defined(RGX_CR_SLC_SIZE_IN_KB) + /* Rogue and Oceanic hardware */ if (RGX_IS_FEATURE_SUPPORTED(psDevInfo, SLC_SIZE_CONFIGURABLE)) { ui64SLCSize = OSReadHWReg64(psDevInfo->pvRegsBaseKM, RGX_CR_SLC_SIZE_IN_KB); diff --git a/drivers/gpu/drm/img-rogue/rgxccb.c b/drivers/gpu/drm/img-rogue/rgxccb.c index ece085de6..7a76f8023 100644 --- a/drivers/gpu/drm/img-rogue/rgxccb.c +++ b/drivers/gpu/drm/img-rogue/rgxccb.c @@ -297,6 +297,10 @@ static void RGXCCBPDumpFastForwardCCB(RGX_CLIENT_CCB *psClientCCB, IMG_UINT32 ui psCCBCtl->ui32WriteOffset = psClientCCB->ui32HostWriteOffset; #if defined(SUPPORT_AGP) psCCBCtl->ui32ReadOffset2 = psClientCCB->ui32HostWriteOffset; +#if defined(SUPPORT_AGP4) + psCCBCtl->ui32ReadOffset3 = psClientCCB->ui32HostWriteOffset; + psCCBCtl->ui32ReadOffset4 = psClientCCB->ui32HostWriteOffset; +#endif #endif PDUMPCOMMENTWITHFLAGS(psDevInfo->psDeviceNode, @@ -1585,7 +1589,8 @@ PVRSRV_ERROR RGXSetCCBFlags(RGX_CLIENT_CCB *psClientCCB, return PVRSRV_OK; } -void RGXCmdHelperInitCmdCCB_CommandSize(IMG_UINT64 ui64FBSCEntryMask, +void RGXCmdHelperInitCmdCCB_CommandSize(PVRSRV_RGXDEV_INFO *psDevInfo, + IMG_UINT64 ui64FBSCEntryMask, IMG_UINT32 ui32ClientFenceCount, IMG_UINT32 ui32ClientUpdateCount, IMG_UINT32 ui32CmdSize, @@ -1594,6 +1599,8 @@ void RGXCmdHelperInitCmdCCB_CommandSize(IMG_UINT64 ui64FBSCEntryMask, PRGXFWIF_UFO_ADDR *ppRMWUFOAddr, RGX_CCB_CMD_HELPER_DATA *psCmdHelperData) { + PVRSRV_DEVICE_NODE *psDeviceNode = psDevInfo->psDeviceNode; + IMG_BOOL bCacheInval = IMG_TRUE; /* Init the generated data members */ psCmdHelperData->ui32FBSCInvalCmdSize = 0; psCmdHelperData->ui64FBSCEntryMask = 0; @@ -1603,14 +1610,32 @@ void RGXCmdHelperInitCmdCCB_CommandSize(IMG_UINT64 ui64FBSCEntryMask, psCmdHelperData->ui32PostTimeStampCmdSize = 0; psCmdHelperData->ui32RMWUFOCmdSize = 0; - /* Total FBSC invalidate command size (header plus command data) */ + /* Only compile if RGX_FEATURE_PDS_INSTRUCTION_CACHE_AUTO_INVALIDATE is defined to avoid + * compilation errors on rogue cores. + */ +#if defined(RGX_FEATURE_PDS_INSTRUCTION_CACHE_AUTO_INVALIDATE) + bCacheInval = !(PVRSRV_IS_FEATURE_SUPPORTED(psDeviceNode, PDS_INSTRUCTION_CACHE_AUTO_INVALIDATE) && + PVRSRV_IS_FEATURE_SUPPORTED(psDeviceNode, USC_INSTRUCTION_CACHE_AUTO_INVALIDATE) && + PVRSRV_IS_FEATURE_SUPPORTED(psDeviceNode, TDM_SLC_MMU_AUTO_CACHE_OPS) && + PVRSRV_IS_FEATURE_SUPPORTED(psDeviceNode, GEOM_SLC_MMU_AUTO_CACHE_OPS) && + PVRSRV_IS_FEATURE_SUPPORTED(psDeviceNode, FRAG_SLC_MMU_AUTO_CACHE_OPS) && + PVRSRV_IS_FEATURE_SUPPORTED(psDeviceNode, COMPUTE_SLC_MMU_AUTO_CACHE_OPS)) || + RGX_IS_BRN_SUPPORTED(psDevInfo, 71960) || + RGX_IS_BRN_SUPPORTED(psDevInfo, 72143); +#else + PVR_UNREFERENCED_PARAMETER(psDeviceNode); +#endif - if (ui64FBSCEntryMask != 0) + /* Total FBSC invalidate command size (header plus command data) */ + if (bCacheInval) { - psCmdHelperData->ui32FBSCInvalCmdSize = - RGX_CCB_FWALLOC_ALIGN(sizeof(psCmdHelperData->ui64FBSCEntryMask) + - sizeof(RGXFWIF_CCB_CMD_HEADER)); - psCmdHelperData->ui64FBSCEntryMask = ui64FBSCEntryMask; + if (ui64FBSCEntryMask != 0) + { + psCmdHelperData->ui32FBSCInvalCmdSize = + RGX_CCB_FWALLOC_ALIGN(sizeof(psCmdHelperData->ui64FBSCEntryMask) + + sizeof(RGXFWIF_CCB_CMD_HEADER)); + psCmdHelperData->ui64FBSCEntryMask = ui64FBSCEntryMask; + } } /* total DM command size (header plus command data) */ @@ -1739,7 +1764,8 @@ void RGXCmdHelperInitCmdCCB_OtherData(RGX_CLIENT_CCB *psClientCCB, /* Work out how much space this command will require */ -void RGXCmdHelperInitCmdCCB(RGX_CLIENT_CCB *psClientCCB, +void RGXCmdHelperInitCmdCCB(PVRSRV_RGXDEV_INFO *psDevInfo, + RGX_CLIENT_CCB *psClientCCB, IMG_UINT64 ui64FBSCEntryMask, IMG_UINT32 ui32ClientFenceCount, PRGXFWIF_UFO_ADDR *pauiFenceUFOAddress, @@ -1761,7 +1787,8 @@ void RGXCmdHelperInitCmdCCB(RGX_CLIENT_CCB *psClientCCB, IMG_BOOL bCCBStateOpen, RGX_CCB_CMD_HELPER_DATA *psCmdHelperData) { - RGXCmdHelperInitCmdCCB_CommandSize(ui64FBSCEntryMask, + RGXCmdHelperInitCmdCCB_CommandSize(psDevInfo, + ui64FBSCEntryMask, ui32ClientFenceCount, ui32ClientUpdateCount, ui32CmdSize, @@ -2435,7 +2462,7 @@ void DumpCCB(PVRSRV_RGXDEV_INFO *psDevInfo, psClientCCBCtrl = psCurrentClientCCB->psClientCCBCtrl; pvClientCCBBuff = psCurrentClientCCB->pvClientCCB; ui32EndOffset = psCurrentClientCCB->ui32HostWriteOffset; - OSMemoryBarrier(); + OSMemoryBarrier(NULL); ui32Offset = psClientCCBCtrl->ui32ReadOffset; ui32DepOffset = psClientCCBCtrl->ui32DepOffset; /* NB. Use psCurrentClientCCB->ui32Size as basis for wrap mask (rather @@ -2598,7 +2625,7 @@ void DumpStalledCCBCommand(PRGXFWIF_FWCOMMONCONTEXT sFWCommonContext, PVR_DUMPDEBUG_LOG(" Addr:0x%08x Value=0x%08x",psUFOPtr[jj].puiAddrUFO.ui32Addr, psUFOPtr[jj].ui32Value); #else ui32Val = 0; - RGXReadWithSP(psDevInfo, psUFOPtr[jj].puiAddrUFO.ui32Addr, &ui32Val); + RGXReadFWModuleAddr(psDevInfo, psUFOPtr[jj].puiAddrUFO.ui32Addr, &ui32Val); PVR_DUMPDEBUG_LOG(" Addr:0x%08x Value(Host)=0x%08x Value(FW)=0x%08x", psUFOPtr[jj].puiAddrUFO.ui32Addr, psUFOPtr[jj].ui32Value, ui32Val); @@ -2629,7 +2656,7 @@ void DumpStalledCCBCommand(PRGXFWIF_FWCOMMONCONTEXT sFWCommonContext, PVR_DUMPDEBUG_LOG(" Addr:0x%08x Value=0x%08x",psUFOPtr[jj].puiAddrUFO.ui32Addr, psUFOPtr[jj].ui32Value); #else ui32Val = 0; - RGXReadWithSP(psDevInfo, psUFOPtr[jj].puiAddrUFO.ui32Addr, &ui32Val); + RGXReadFWModuleAddr(psDevInfo, psUFOPtr[jj].puiAddrUFO.ui32Addr, &ui32Val); PVR_DUMPDEBUG_LOG(" Addr:0x%08x Value(Host)=0x%08x Value(FW)=0x%08x", psUFOPtr[jj].puiAddrUFO.ui32Addr, psUFOPtr[jj].ui32Value, @@ -2696,7 +2723,7 @@ void DumpStalledContextInfo(PVRSRV_RGXDEV_INFO *psDevInfo) } psDevInfo->psRGXFWIfFwOsData->ui32ForcedUpdatesRequested++; /* flush write buffers for psRGXFWIfFwOsData */ - OSWriteMemoryBarrier(); + OSWriteMemoryBarrier(&psDevInfo->psRGXFWIfFwOsData->sSLRLog[psDevInfo->psRGXFWIfFwOsData->ui8SLRLogWp]); #endif PVR_LOG(("Fence found on context 0x%x '%s' @ %d has %d UFOs", FWCommonContextGetFWAddress(psStalledClientCCB->psServerCommonContext).ui32Addr, @@ -2762,7 +2789,6 @@ void DumpStalledContextInfo(PVRSRV_RGXDEV_INFO *psDevInfo) RGXScheduleCommand(FWCommonContextGetRGXDevInfo(psStalledClientCCB->psServerCommonContext), RGXFWIF_DM_GP, &sSignalFencesCmd, - 0, PDUMP_FLAGS_CONTINUOUS); } } diff --git a/drivers/gpu/drm/img-rogue/rgxccb.h b/drivers/gpu/drm/img-rogue/rgxccb.h index ee9542f77..0dddee171 100644 --- a/drivers/gpu/drm/img-rogue/rgxccb.h +++ b/drivers/gpu/drm/img-rogue/rgxccb.h @@ -269,7 +269,8 @@ IMG_UINT32 RGXGetWrapMaskCCB(RGX_CLIENT_CCB *psClientCCB); PVRSRV_ERROR RGXSetCCBFlags(RGX_CLIENT_CCB *psClientCCB, IMG_UINT32 ui32Flags); -void RGXCmdHelperInitCmdCCB_CommandSize(IMG_UINT64 ui64FBSCEntryMask, +void RGXCmdHelperInitCmdCCB_CommandSize(PVRSRV_RGXDEV_INFO *psDevInfo, + IMG_UINT64 ui64FBSCEntryMask, IMG_UINT32 ui32ClientFenceCount, IMG_UINT32 ui32ClientUpdateCount, IMG_UINT32 ui32CmdSize, @@ -299,7 +300,8 @@ void RGXCmdHelperInitCmdCCB_OtherData(RGX_CLIENT_CCB *psClientCCB, IMG_BOOL bCCBStateOpen, RGX_CCB_CMD_HELPER_DATA *psCmdHelperData); -void RGXCmdHelperInitCmdCCB(RGX_CLIENT_CCB *psClientCCB, +void RGXCmdHelperInitCmdCCB(PVRSRV_RGXDEV_INFO *psDevInfo, + RGX_CLIENT_CCB *psClientCCB, IMG_UINT64 ui64FBSCEntryMask, IMG_UINT32 ui32ClientFenceCount, PRGXFWIF_UFO_ADDR *pauiFenceUFOAddress, diff --git a/drivers/gpu/drm/img-rogue/rgxcompute.c b/drivers/gpu/drm/img-rogue/rgxcompute.c index 71e573e8c..952940f6f 100644 --- a/drivers/gpu/drm/img-rogue/rgxcompute.c +++ b/drivers/gpu/drm/img-rogue/rgxcompute.c @@ -402,7 +402,6 @@ PVRSRV_ERROR PVRSRVRGXDestroyComputeContextKM(RGX_SERVER_COMPUTE_CONTEXT *psComp PVRSRV_ERROR PVRSRVRGXKickCDMKM(RGX_SERVER_COMPUTE_CONTEXT *psComputeContext, - IMG_UINT32 ui32ClientCacheOpSeqNum, IMG_UINT32 ui32ClientUpdateCount, SYNC_PRIMITIVE_BLOCK **pauiClientUpdateUFODevVarBlock, IMG_UINT32 *paui32ClientUpdateSyncOffset, @@ -834,7 +833,8 @@ PVRSRV_ERROR PVRSRVRGXKickCDMKM(RGX_SERVER_COMPUTE_CONTEXT *psComputeContext, &pPostAddr, &pRMWUFOAddr); - RGXCmdHelperInitCmdCCB(psClientCCB, + RGXCmdHelperInitCmdCCB(psDevInfo, + psClientCCB, 0, ui32IntClientFenceCount, pauiIntFenceUFOAddress, @@ -959,7 +959,6 @@ PVRSRV_ERROR PVRSRVRGXKickCDMKM(RGX_SERVER_COMPUTE_CONTEXT *psComputeContext, eError2 = RGXScheduleCommand(psComputeContext->psDeviceNode->pvDevice, RGXFWIF_DM_CDM, &sCmpKCCBCmd, - ui32ClientCacheOpSeqNum, ui32PDumpFlags); if (eError2 != PVRSRV_ERROR_RETRY) { @@ -1112,7 +1111,6 @@ PVRSRV_ERROR PVRSRVRGXFlushComputeDataKM(RGX_SERVER_COMPUTE_CONTEXT *psComputeCo eError = RGXScheduleCommandAndGetKCCBSlot(psDevInfo, RGXFWIF_DM_CDM, &sFlushCmd, - 0, PDUMP_FLAGS_CONTINUOUS, &ui32kCCBCommandSlot); /* Iterate if we hit a PVRSRV_ERROR_KERNEL_CCB_FULL error */ @@ -1185,7 +1183,6 @@ PVRSRV_ERROR PVRSRVRGXNotifyComputeWriteOffsetUpdateKM(RGX_SERVER_COMPUTE_CONTEX eError = RGXScheduleCommand(psComputeContext->psDeviceNode->pvDevice, RGXFWIF_DM_CDM, &sKCCBCmd, - 0, PDUMP_FLAGS_NONE); if (eError != PVRSRV_ERROR_RETRY) { @@ -1245,17 +1242,18 @@ PVRSRV_ERROR PVRSRVRGXSetComputeContextPropertyKM(RGX_SERVER_COMPUTE_CONTEXT *ps IMG_UINT64 ui64Input, IMG_UINT64 *pui64Output) { - PVRSRV_ERROR eError; + PVRSRV_ERROR eError = PVRSRV_OK; switch (eContextProperty) { case RGX_CONTEXT_PROPERTY_FLAGS: { + IMG_UINT32 ui32ContextFlags = (IMG_UINT32)ui64Input; + OSLockAcquire(psComputeContext->hLock); eError = FWCommonContextSetFlags(psComputeContext->psServerCommonContext, - (IMG_UINT32)ui64Input); + ui32ContextFlags); OSLockRelease(psComputeContext->hLock); - PVR_LOG_IF_ERROR(eError, "FWCommonContextSetFlags"); break; } diff --git a/drivers/gpu/drm/img-rogue/rgxcompute.h b/drivers/gpu/drm/img-rogue/rgxcompute.h index ebe2c3faa..0ac6e4a34 100644 --- a/drivers/gpu/drm/img-rogue/rgxcompute.h +++ b/drivers/gpu/drm/img-rogue/rgxcompute.h @@ -102,7 +102,6 @@ PVRSRV_ERROR PVRSRVRGXDestroyComputeContextKM(RGX_SERVER_COMPUTE_CONTEXT *psComp @Return PVRSRV_ERROR ******************************************************************************/ PVRSRV_ERROR PVRSRVRGXKickCDMKM(RGX_SERVER_COMPUTE_CONTEXT *psComputeContext, - IMG_UINT32 ui32ClientCacheOpSeqNum, IMG_UINT32 ui32ClientUpdateCount, SYNC_PRIMITIVE_BLOCK **pauiClientUpdateUFODevVarBlock, IMG_UINT32 *paui32ClientUpdateSyncOffset, diff --git a/drivers/gpu/drm/img-rogue/rgxdebug.c b/drivers/gpu/drm/img-rogue/rgxdebug.c index 57690b9df..f69484723 100644 --- a/drivers/gpu/drm/img-rogue/rgxdebug.c +++ b/drivers/gpu/drm/img-rogue/rgxdebug.c @@ -94,7 +94,7 @@ CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. #define DD_SUMMARY_INDENT "" #define DD_NORMAL_INDENT " " -#define RGX_DEBUG_STR_SIZE (150U) +#define RGX_DEBUG_STR_SIZE (150U) #define MAX_FW_DESCRIPTION_LENGTH (500U) #define RGX_CR_BIF_CAT_BASE0 (0x1200U) @@ -177,9 +177,6 @@ static const IMG_FLAGS2DESC asCswOpts2Description[] = {RGXFWIF_INICFG_CTXSWITCH_PROFILE_NODELAY, " No Delay CSW profile;"}, {RGXFWIF_INICFG_CTXSWITCH_MODE_RAND, " Random Csw enabled;"}, {RGXFWIF_INICFG_CTXSWITCH_SRESET_EN, " SoftReset;"}, - {RGXFWIF_INICFG_VDM_CTX_STORE_MODE_INDEX, " VDM CS INDEX mode;"}, - {RGXFWIF_INICFG_VDM_CTX_STORE_MODE_INSTANCE, " VDM CS INSTANCE mode;"}, - {RGXFWIF_INICFG_VDM_CTX_STORE_MODE_LIST, " VDM CS LIST mode;"}, }; static const IMG_FLAGS2DESC asMisc2Description[] = @@ -189,11 +186,9 @@ static const IMG_FLAGS2DESC asMisc2Description[] = {RGXFWIF_INICFG_FBCDC_V3_1_EN, " FBCDCv3.1;"}, {RGXFWIF_INICFG_CHECK_MLIST_EN, " Check MList;"}, {RGXFWIF_INICFG_DISABLE_CLKGATING_EN, " ClockGating Off;"}, - {RGXFWIF_INICFG_POLL_COUNTERS_EN, " Poll Counters;"}, {RGXFWIF_INICFG_REGCONFIG_EN, " Register Config;"}, {RGXFWIF_INICFG_ASSERT_ON_OUTOFMEMORY, " Assert on OOM;"}, {RGXFWIF_INICFG_HWP_DISABLE_FILTER, " HWP Filter Off;"}, - {RGXFWIF_INICFG_CUSTOM_PERF_TIMER_EN, " Custom PerfTimer;"}, {RGXFWIF_INICFG_DM_KILL_MODE_RAND_EN, " CDM Random kill;"}, {RGXFWIF_INICFG_DISABLE_DM_OVERLAP, " DM Overlap Off;"}, {RGXFWIF_INICFG_ASSERT_ON_HWR_TRIGGER, " Assert on HWR;"}, @@ -246,6 +241,39 @@ static const IMG_FLAGS2DESC asDmState2Description[] = {RGXFWIF_DM_STATE_GPU_ECC_HWR, " GPU ECC hwr;"}, }; +const IMG_CHAR * const gapszMipsPermissionPTFlags[4] = +{ + " ", + "XI ", + "RI ", + "RIXI" +}; + +const IMG_CHAR * const gapszMipsCoherencyPTFlags[8] = +{ + "C", + "C", + " ", + "C", + "C", + "C", + "C", + " " +}; + +const IMG_CHAR * const gapszMipsDirtyGlobalValidPTFlags[8] = +{ + " ", + " G", + " V ", + " VG", + "D ", + "D G", + "DV ", + "DVG" +}; + +#if !defined(SUPPORT_TRUSTED_DEVICE) #if !defined(NO_HARDWARE) /* Translation of MIPS exception encoding */ typedef struct _MIPS_EXCEPTION_ENCODING_ @@ -304,6 +332,7 @@ static IMG_CHAR const *_GetMIPSExcString(IMG_UINT32 ui32ExcCode) return apsMIPSExcCodes[ui32ExcCode].pszStr; } #endif +#endif /* !defined(SUPPORT_TRUSTED_DEVICE) */ typedef struct _RGXMIPSFW_C0_DEBUG_TBL_ENTRY_ { @@ -311,6 +340,7 @@ typedef struct _RGXMIPSFW_C0_DEBUG_TBL_ENTRY_ const IMG_CHAR * pszExplanation; } RGXMIPSFW_C0_DEBUG_TBL_ENTRY; +#if !defined(SUPPORT_TRUSTED_DEVICE) #if !defined(NO_HARDWARE) static const RGXMIPSFW_C0_DEBUG_TBL_ENTRY sMIPS_C0_DebugTable[] = { @@ -331,6 +361,7 @@ static const RGXMIPSFW_C0_DEBUG_TBL_ENTRY sMIPS_C0_DebugTable[] = { (IMG_UINT32)RGXMIPSFW_C0_DEBUG_DBD, "Debug exception occurred in branch delay slot" } }; #endif +#endif /* !defined(SUPPORT_TRUSTED_DEVICE) */ static const IMG_CHAR * const apszFwOsStateName[RGXFW_CONNECTION_FW_STATE_COUNT] = { @@ -358,7 +389,7 @@ RGXPollMetaRegThroughSP(PVRSRV_RGXDEV_INFO *psDevInfo, IMG_UINT32 ui32RegOffset, do { - eError = RGXReadWithSP(psDevInfo, ui32RegOffset, &ui32RegValue); + eError = RGXReadFWModuleAddr(psDevInfo, ui32RegOffset, &ui32RegValue); if (eError != PVRSRV_OK) { return eError; @@ -381,9 +412,9 @@ RGXReadMetaCoreReg(PVRSRV_RGXDEV_INFO *psDevInfo, IMG_UINT32 ui32RegAddr, IMG_UI PVR_LOG_RETURN_IF_ERROR(eError, "RGXPollMetaRegThroughSP"); /* Set the reg we are interested in reading */ - eError = RGXWriteWithSP(psDevInfo, META_CR_TXUXXRXRQ_OFFSET, + eError = RGXWriteFWModuleAddr(psDevInfo, META_CR_TXUXXRXRQ_OFFSET, ui32RegAddr | META_CR_TXUXXRXRQ_RDnWR_BIT); - PVR_LOG_RETURN_IF_ERROR(eError, "RGXWriteWithSP"); + PVR_LOG_RETURN_IF_ERROR(eError, "RGXWriteFWModuleAddr"); /* Core Read Done? */ eError = RGXPollMetaRegThroughSP(psDevInfo, @@ -393,30 +424,7 @@ RGXReadMetaCoreReg(PVRSRV_RGXDEV_INFO *psDevInfo, IMG_UINT32 ui32RegAddr, IMG_UI PVR_LOG_RETURN_IF_ERROR(eError, "RGXPollMetaRegThroughSP"); /* Read the value */ - return RGXReadWithSP(psDevInfo, META_CR_TXUXXRXDT_OFFSET, pui32RegVal); -} - -PVRSRV_ERROR -RGXReadWithSP(PVRSRV_RGXDEV_INFO *psDevInfo, IMG_UINT32 ui32FWAddr, IMG_UINT32 *pui32Value) -{ - PVRSRV_ERROR eError = RGXReadMETAAddr(psDevInfo, ui32FWAddr, pui32Value); - if (eError != PVRSRV_OK) - { - PVR_DPF((PVR_DBG_ERROR, "%s: %s", __func__, PVRSRVGetErrorString(eError))); - } - - return eError; -} - -PVRSRV_ERROR -RGXWriteWithSP(PVRSRV_RGXDEV_INFO *psDevInfo, IMG_UINT32 ui32FWAddr, IMG_UINT32 ui32Value) -{ - PVRSRV_ERROR eError = RGXWriteMETAAddr(psDevInfo, ui32FWAddr, ui32Value); - if (eError != PVRSRV_OK) - { - PVR_DPF((PVR_DBG_ERROR, "%s: %s", __func__, PVRSRVGetErrorString(eError))); - } - return eError; + return RGXReadFWModuleAddr(psDevInfo, META_CR_TXUXXRXDT_OFFSET, pui32RegVal); } #if !defined(NO_HARDWARE) && !defined(SUPPORT_TRUSTED_DEVICE) @@ -435,22 +443,19 @@ static PVRSRV_ERROR _ValidateWithFWModule(DUMPDEBUG_PRINTF_FUNC *pfnDumpDebugPri IMG_UINT32 *pui32FWCode = (IMG_PUINT32) ((IMG_PBYTE)pvHostCodeAddr + ui32StartOffset); IMG_UINT32 i; +#if defined(EMULATOR) + if (RGX_IS_FEATURE_SUPPORTED(psDevInfo, RISCV_FW_PROCESSOR)) + { + return PVRSRV_OK; + } +#endif + ui32MaxLen -= ui32StartOffset; ui32MaxLen /= sizeof(IMG_UINT32); /* Byte -> 32 bit words */ for (i = 0; i < ui32MaxLen; i++) { - if (RGX_IS_FEATURE_VALUE_SUPPORTED(psDevInfo, META)) - { - eError = RGXReadMETAAddr(psDevInfo, ui32FWCodeDevVAAddr, &ui32Value); - } -#if !defined(EMULATOR) - else if (RGX_IS_FEATURE_SUPPORTED(psDevInfo, RISCV_FW_PROCESSOR)) - { - eError = RGXRiscvReadMem(psDevInfo, ui32FWCodeDevVAAddr, &ui32Value); - } -#endif - + eError = RGXReadFWModuleAddr(psDevInfo, ui32FWCodeDevVAAddr, &ui32Value); if (eError != PVRSRV_OK) { PVR_DPF((PVR_DBG_ERROR, "%s: %s", __func__, PVRSRVGetErrorString(eError))); @@ -694,7 +699,16 @@ PVRSRV_ERROR ValidateFWOnLoad(PVRSRV_RGXDEV_INFO *psDevInfo) return eError; } - sFWAddr.ui32Addr = RGXFW_BOOTLDR_META_ADDR; + if (RGX_IS_FEATURE_VALUE_SUPPORTED(psDevInfo, META)) + { + sFWAddr.ui32Addr = RGXFW_BOOTLDR_META_ADDR; + } + else + { + PVR_ASSERT(RGX_IS_FEATURE_SUPPORTED(psDevInfo, RISCV_FW_PROCESSOR)); + sFWAddr.ui32Addr = RGXRISCVFW_BOOTLDR_CODE_BASE; + }; + eError = _ValidateWithFWModule(NULL, NULL, psDevInfo, &sFWAddr, pbCodeMemoryPointer, psDevInfo->ui32FWCodeSizeInBytes, "FW code", 0); if (eError != PVRSRV_OK) { @@ -709,7 +723,15 @@ PVRSRV_ERROR ValidateFWOnLoad(PVRSRV_RGXDEV_INFO *psDevInfo) goto releaseFWCoreCodeMapping; } - sFWAddr.ui32Addr = RGXGetFWImageSectionAddress(NULL, META_COREMEM_CODE); + if (RGX_IS_FEATURE_VALUE_SUPPORTED(psDevInfo, META)) + { + sFWAddr.ui32Addr = RGXGetFWImageSectionAddress(NULL, META_COREMEM_CODE); + } + else + { + PVR_ASSERT(RGX_IS_FEATURE_SUPPORTED(psDevInfo, RISCV_FW_PROCESSOR)); + sFWAddr.ui32Addr = RGXGetFWImageSectionAddress(NULL, RISCV_COREMEM_CODE); + } eError = _ValidateWithFWModule(NULL, NULL, psDevInfo, &sFWAddr, pbCodeMemoryPointer, psDevInfo->ui32FWCorememCodeSizeInBytes, "FW coremem code", 0); @@ -812,17 +834,17 @@ static void _RGXDecodeBIFReqTagsXE(PVRSRV_RGXDEV_INFO *psDevInfo, switch (ui32TagID) { /* MMU tags */ - case RGX_MH_TAG_ENCODING_MH_TAG_MMU_PT: - case RGX_MH_TAG_ENCODING_MH_TAG_MMU_PD: - case RGX_MH_TAG_ENCODING_MH_TAG_MMU_PC: - case RGX_MH_TAG_ENCODING_MH_TAG_MMU_PM: + case RGX_MH_TAG_ENCODING_MH_TAG_MMU: + case RGX_MH_TAG_ENCODING_MH_TAG_CPU_MMU: + case RGX_MH_TAG_ENCODING_MH_TAG_CPU_IFU: + case RGX_MH_TAG_ENCODING_MH_TAG_CPU_LSU: { switch (ui32TagID) { - case RGX_MH_TAG_ENCODING_MH_TAG_MMU_PT: pszTagID = "MMU PT"; break; - case RGX_MH_TAG_ENCODING_MH_TAG_MMU_PD: pszTagID = "MMU PD"; break; - case RGX_MH_TAG_ENCODING_MH_TAG_MMU_PC: pszTagID = "MMU PC"; break; - case RGX_MH_TAG_ENCODING_MH_TAG_MMU_PM: pszTagID = "MMU PM"; break; + case RGX_MH_TAG_ENCODING_MH_TAG_MMU: pszTagID = "MMU"; break; + case RGX_MH_TAG_ENCODING_MH_TAG_CPU_MMU: pszTagID = "CPU MMU"; break; + case RGX_MH_TAG_ENCODING_MH_TAG_CPU_IFU: pszTagID = "CPU IFU"; break; + case RGX_MH_TAG_ENCODING_MH_TAG_CPU_LSU: pszTagID = "CPU LSU"; break; } switch (ui32TagSB) { @@ -1604,7 +1626,7 @@ static const IMG_CHAR* _RGXDecodeMMULevel(IMG_UINT32 ui32MMULevel) ******************************************************************************/ static void _RGXDecodeMMUReqTags(PVRSRV_RGXDEV_INFO *psDevInfo, - IMG_UINT32 ui32TagID, + IMG_UINT32 ui32TagID, IMG_UINT32 ui32TagSB, IMG_BOOL bRead, IMG_CHAR **ppszTagID, @@ -2031,6 +2053,7 @@ static void _RGXDecodeMMUReqTags(PVRSRV_RGXDEV_INFO *psDevInfo, *ppszTagSB = pszTagSB; } + static void ConvertOSTimestampToSAndNS(IMG_UINT64 ui64OSTimer, IMG_UINT64 *pui64Seconds, IMG_UINT64 *pui64Nanoseconds) @@ -2050,6 +2073,7 @@ typedef enum _DEVICEMEM_HISTORY_QUERY_INDEX_ DEVICEMEM_HISTORY_QUERY_INDEX_COUNT, } DEVICEMEM_HISTORY_QUERY_INDEX; + /*! ******************************************************************************* @@ -2240,7 +2264,6 @@ static IMG_BOOL _GetDevicememHistoryData(IMG_PID uiPID, IMG_DEV_VIRTADDR sFaultD DEVICEMEM_HISTORY_QUERY_OUT asQueryOut[DEVICEMEM_HISTORY_QUERY_INDEX_COUNT], IMG_UINT32 ui32PageSizeBytes) { - IMG_UINT32 i; DEVICEMEM_HISTORY_QUERY_IN sQueryIn; IMG_BOOL bAnyHits = IMG_FALSE; @@ -2258,39 +2281,38 @@ static IMG_BOOL _GetDevicememHistoryData(IMG_PID uiPID, IMG_DEV_VIRTADDR sFaultD sQueryIn.uiPID = uiPID; } - /* query the DevicememHistory about the preceding / faulting / next page */ - - for (i = DEVICEMEM_HISTORY_QUERY_INDEX_PRECEDING; i < DEVICEMEM_HISTORY_QUERY_INDEX_COUNT; i++) + /* Query the DevicememHistory for all allocations in the previous page... */ + sQueryIn.sDevVAddr.uiAddr = (sFaultDevVAddr.uiAddr & ~(IMG_UINT64)(ui32PageSizeBytes - 1)) - ui32PageSizeBytes; + if (DevicememHistoryQuery(&sQueryIn, &asQueryOut[DEVICEMEM_HISTORY_QUERY_INDEX_PRECEDING], + ui32PageSizeBytes, IMG_TRUE)) { - IMG_BOOL bHits; + bAnyHits = IMG_TRUE; + } - switch (i) - { - case DEVICEMEM_HISTORY_QUERY_INDEX_PRECEDING: - sQueryIn.sDevVAddr.uiAddr = (sFaultDevVAddr.uiAddr & ~(IMG_UINT64)(ui32PageSizeBytes - 1)) - 1; - break; - case DEVICEMEM_HISTORY_QUERY_INDEX_FAULTED: - sQueryIn.sDevVAddr = sFaultDevVAddr; - break; - case DEVICEMEM_HISTORY_QUERY_INDEX_NEXT: - sQueryIn.sDevVAddr.uiAddr = (sFaultDevVAddr.uiAddr & ~(IMG_UINT64)(ui32PageSizeBytes - 1)) + ui32PageSizeBytes; - break; - } - - /* First try matching any record at the exact address... */ - bHits = DevicememHistoryQuery(&sQueryIn, &asQueryOut[i], ui32PageSizeBytes, IMG_FALSE); - if (!bHits) - { - /* If not matched then try matching any record in the same page... */ - bHits = DevicememHistoryQuery(&sQueryIn, &asQueryOut[i], ui32PageSizeBytes, IMG_TRUE); - } - - if (bHits) + /* Query the DevicememHistory for any record at the exact address... */ + sQueryIn.sDevVAddr = sFaultDevVAddr; + if (DevicememHistoryQuery(&sQueryIn, &asQueryOut[DEVICEMEM_HISTORY_QUERY_INDEX_FAULTED], + ui32PageSizeBytes, IMG_FALSE)) + { + bAnyHits = IMG_TRUE; + } + else + { + /* If not matched then try matching any record in the faulting page... */ + if (DevicememHistoryQuery(&sQueryIn, &asQueryOut[DEVICEMEM_HISTORY_QUERY_INDEX_FAULTED], + ui32PageSizeBytes, IMG_TRUE)) { bAnyHits = IMG_TRUE; } } + /* Query the DevicememHistory for all allocations in the next page... */ + sQueryIn.sDevVAddr.uiAddr = (sFaultDevVAddr.uiAddr & ~(IMG_UINT64)(ui32PageSizeBytes - 1)) + ui32PageSizeBytes; + if (DevicememHistoryQuery(&sQueryIn, &asQueryOut[DEVICEMEM_HISTORY_QUERY_INDEX_NEXT], + ui32PageSizeBytes, IMG_TRUE)) + { + bAnyHits = IMG_TRUE; + } return bAnyHits; } @@ -2412,7 +2434,7 @@ static void _PrintFaultInfo(DUMPDEBUG_PRINTF_FUNC *pfnDumpDebugPrintf, { for (i = DEVICEMEM_HISTORY_QUERY_INDEX_PRECEDING; i < DEVICEMEM_HISTORY_QUERY_INDEX_COUNT; i++) { - const IMG_CHAR *pszWhich; + const IMG_CHAR *pszWhich = NULL; switch (i) { @@ -2820,6 +2842,7 @@ static_assert((RGX_CR_MMU_FAULT_STATUS_TYPE_SHIFT == RGX_CR_MMU_FAULT_STATUS_MET +#if !defined(SUPPORT_TRUSTED_DEVICE) #if !defined(NO_HARDWARE) static PVRSRV_ERROR _RGXMipsExtraDebug(PVRSRV_RGXDEV_INFO *psDevInfo, RGX_MIPS_STATE *psMIPSState) { @@ -2854,8 +2877,9 @@ static PVRSRV_ERROR _RGXMipsExtraDebug(PVRSRV_RGXDEV_INFO *psDevInfo, RGX_MIPS_S /* Make sure the synchronisation flag is set to 0 */ pui32SyncFlag = &pui32NMIMemoryPointer[RGXMIPSFW_NMI_SYNC_FLAG_OFFSET]; *pui32SyncFlag = 0; - OSWriteMemoryBarrier(); - (void) *pui32SyncFlag; + + /* Readback performed as a part of memory barrier */ + OSWriteMemoryBarrier(pui32SyncFlag); /* Enable NMI issuing in the MIPS wrapper */ OSWriteHWReg64(pvRegsBaseKM, @@ -2902,8 +2926,9 @@ static PVRSRV_ERROR _RGXMipsExtraDebug(PVRSRV_RGXDEV_INFO *psDevInfo, RGX_MIPS_S /* Allow the firmware to proceed */ *pui32SyncFlag = 1; - OSWriteMemoryBarrier(); - (void) *pui32SyncFlag; + + /* Readback performed as a part of memory barrier */ + OSWriteMemoryBarrier(pui32SyncFlag); /* Wait for the FW to have finished the NMI routine */ ui32RegRead = OSReadHWReg32(pvRegsBaseKM, @@ -3138,38 +3163,6 @@ static inline void _RGXMipsDumpTLBEntry(DUMPDEBUG_PRINTF_FUNC *pfnDumpDebugPrint IMG_UINT64 ui64Remap0AddrOut = 0, ui64Remap1AddrOut = 0; IMG_UINT32 ui32Remap0AddrIn = 0, ui32Remap1AddrIn = 0; - static const IMG_CHAR * const apszPermissionInhibit[4] = - { - "", - "XI", - "RI", - "RIXI" - }; - - static const IMG_CHAR * const apszCoherencyTLB[8] = - { - "C", - "C", - " ", - "C", - "C", - "C", - "C", - " " - }; - - static const IMG_CHAR * const apszDirtyGlobalValid[8] = - { - " ", - " G", - " V ", - " VG", - "D ", - "D G", - "DV ", - "DVG" - }; - if (bDumpRemapEntries) { /* RemapAddrIn is always 4k aligned and on 32 bit */ @@ -3196,13 +3189,13 @@ static inline void _RGXMipsDumpTLBEntry(DUMPDEBUG_PRINTF_FUNC *pfnDumpDebugPrint psTLBEntry->ui32TLBHi, RGXMIPSFW_TLB_GET_PAGE_SIZE(psTLBEntry->ui32TLBPageMask), ui64PA0, - apszPermissionInhibit[RGXMIPSFW_TLB_GET_INHIBIT(psTLBEntry->ui32TLBLo0)], - apszDirtyGlobalValid[RGXMIPSFW_TLB_GET_DGV(psTLBEntry->ui32TLBLo0)], - apszCoherencyTLB[RGXMIPSFW_TLB_GET_COHERENCY(psTLBEntry->ui32TLBLo0)], + gapszMipsPermissionPTFlags[RGXMIPSFW_TLB_GET_INHIBIT(psTLBEntry->ui32TLBLo0)], + gapszMipsDirtyGlobalValidPTFlags[RGXMIPSFW_TLB_GET_DGV(psTLBEntry->ui32TLBLo0)], + gapszMipsCoherencyPTFlags[RGXMIPSFW_TLB_GET_COHERENCY(psTLBEntry->ui32TLBLo0)], ui64PA1, - apszPermissionInhibit[RGXMIPSFW_TLB_GET_INHIBIT(psTLBEntry->ui32TLBLo1)], - apszDirtyGlobalValid[RGXMIPSFW_TLB_GET_DGV(psTLBEntry->ui32TLBLo1)], - apszCoherencyTLB[RGXMIPSFW_TLB_GET_COHERENCY(psTLBEntry->ui32TLBLo1)]); + gapszMipsPermissionPTFlags[RGXMIPSFW_TLB_GET_INHIBIT(psTLBEntry->ui32TLBLo1)], + gapszMipsDirtyGlobalValidPTFlags[RGXMIPSFW_TLB_GET_DGV(psTLBEntry->ui32TLBLo1)], + gapszMipsCoherencyPTFlags[RGXMIPSFW_TLB_GET_COHERENCY(psTLBEntry->ui32TLBLo1)]); if (bDumpRemapEntries) { @@ -3221,6 +3214,7 @@ static inline void _RGXMipsDumpTLBEntry(DUMPDEBUG_PRINTF_FUNC *pfnDumpDebugPrint } #endif /* !defined(NO_HARDWARE) */ +#endif /* !defined(SUPPORT_TRUSTED_DEVICE) */ static inline IMG_CHAR const *_GetRISCVException(IMG_UINT32 ui32Mcause) { @@ -3245,8 +3239,11 @@ static inline IMG_CHAR const *_GetRISCVException(IMG_UINT32 ui32Mcause) Appends flags strings to a null-terminated string buffer - each flag description string starts with a space. */ -static void _Flags2Description(IMG_CHAR *psDesc, IMG_UINT32 ui32DescSize, const IMG_FLAGS2DESC *psConvTable, - IMG_UINT32 ui32TableSize, IMG_UINT32 ui32Flags) +static void _Flags2Description(IMG_CHAR *psDesc, + IMG_UINT32 ui32DescSize, + const IMG_FLAGS2DESC *psConvTable, + IMG_UINT32 ui32TableSize, + IMG_UINT32 ui32Flags) { IMG_UINT32 ui32Idx; @@ -3404,11 +3401,11 @@ static void _RGXDumpFWHWRInfo(DUMPDEBUG_PRINTF_FUNC *pfnDumpDebugPrintf, const RGXFWIF_HWRINFOBUF *psHWRInfoBuf, PVRSRV_RGXDEV_INFO *psDevInfo) { - IMG_BOOL bAnyLocked = IMG_FALSE; - IMG_UINT32 dm, i; - IMG_UINT32 ui32LineSize; - IMG_CHAR *pszLine, *pszTemp; - const IMG_CHAR *apszDmNames[RGXFWIF_DM_MAX] = {"GP", "TDM", "TA", "3D", "CDM", "RAY"}; + IMG_BOOL bAnyLocked = IMG_FALSE; + IMG_UINT32 dm, i; + IMG_UINT32 ui32LineSize; + IMG_CHAR *pszLine, *pszTemp; + const IMG_CHAR *apszDmNames[RGXFWIF_DM_MAX] = {"GP", "TDM", "TA", "3D", "CDM", "RAY", "TA2", "TA3", "TA4"}; const IMG_CHAR szMsgHeader[] = "Number of HWR: "; const IMG_CHAR szMsgFalse[] = "FALSE("; IMG_CHAR *pszLockupType = ""; @@ -3422,7 +3419,7 @@ static void _RGXDumpFWHWRInfo(DUMPDEBUG_PRINTF_FUNC *pfnDumpDebugPrintf, apszDmNames[RGXFWIF_DM_TDM] = "2D"; } - for (dm = 0; dm < RGXFWIF_DM_MAX; dm++) + for (dm = 0; dm < psDevInfo->sDevFeatureCfg.ui32MAXDMCount; dm++) { if (psHWRInfoBuf->aui32HwrDmLockedUpCount[dm] || psHWRInfoBuf->aui32HwrDmOverranCount[dm]) @@ -3442,7 +3439,7 @@ static void _RGXDumpFWHWRInfo(DUMPDEBUG_PRINTF_FUNC *pfnDumpDebugPrintf, { IMG_BOOL bAnyHWROccured = IMG_FALSE; - for (dm = 0; dm < RGXFWIF_DM_MAX; dm++) + for (dm = 0; dm < psDevInfo->sDevFeatureCfg.ui32MAXDMCount; dm++) { if (psHWRInfoBuf->aui32HwrDmRecoveredCount[dm] != 0 || psHWRInfoBuf->aui32HwrDmLockedUpCount[dm] != 0 || @@ -3461,12 +3458,12 @@ static void _RGXDumpFWHWRInfo(DUMPDEBUG_PRINTF_FUNC *pfnDumpDebugPrintf, ui32LineSize = sizeof(IMG_CHAR) * ( ui32MsgHeaderCharCount + - (RGXFWIF_DM_MAX * ( 4/*DM name + left parenthesis*/ + + (psDevInfo->sDevFeatureCfg.ui32MAXDMCount*( 4/*DM name + left parenthesis*/ + 10/*UINT32 max num of digits*/ + 1/*slash*/ + 10/*UINT32 max num of digits*/ + 3/*right parenthesis + comma + space*/)) + - ui32MsgFalseCharCount + 1 + (RGXFWIF_DM_MAX*6) + 1 + ui32MsgFalseCharCount + 1 + (psDevInfo->sDevFeatureCfg.ui32MAXDMCount*6) + 1 /* 'FALSE(' + ')' + (UINT16 max num + comma) per DM + \0 */ ); @@ -3483,7 +3480,7 @@ static void _RGXDumpFWHWRInfo(DUMPDEBUG_PRINTF_FUNC *pfnDumpDebugPrintf, OSStringLCopy(pszLine, szMsgHeader, ui32LineSize); pszTemp = pszLine + ui32MsgHeaderCharCount; - for (dm = 0; dm < RGXFWIF_DM_MAX; dm++) + for (dm = 0; dm < psDevInfo->sDevFeatureCfg.ui32MAXDMCount; dm++) { pszTemp += OSSNPrintf(pszTemp, 4 + 10 + 1 + 10 + 1 + 10 + 1 + 1 + 1 + 1 @@ -3498,11 +3495,11 @@ static void _RGXDumpFWHWRInfo(DUMPDEBUG_PRINTF_FUNC *pfnDumpDebugPrintf, OSStringLCat(pszLine, szMsgFalse, ui32LineSize); pszTemp += ui32MsgFalseCharCount; - for (dm = 0; dm < RGXFWIF_DM_MAX; dm++) + for (dm = 0; dm < psDevInfo->sDevFeatureCfg.ui32MAXDMCount; dm++) { pszTemp += OSSNPrintf(pszTemp, 10 + 1 + 1 /* UINT32 max num + comma + \0 */, - (dm < RGXFWIF_DM_MAX-1 ? "%u," : "%u)"), + (dm < psDevInfo->sDevFeatureCfg.ui32MAXDMCount-1 ? "%u," : "%u)"), psHWRInfoBuf->aui32HwrDmFalseDetectCount[dm]); } @@ -3511,7 +3508,7 @@ static void _RGXDumpFWHWRInfo(DUMPDEBUG_PRINTF_FUNC *pfnDumpDebugPrintf, OSFreeMem(pszLine); /* Print out per HWR info */ - for (dm = 0; dm < RGXFWIF_DM_MAX; dm++) + for (dm = 0; dm < psDevInfo->sDevFeatureCfg.ui32MAXDMCount; dm++) { if (dm == RGXFWIF_DM_GP) { @@ -3601,7 +3598,7 @@ static void _RGXDumpFWHWRInfo(DUMPDEBUG_PRINTF_FUNC *pfnDumpDebugPrintf, /* There's currently no time correlation for the Guest OSes on the Firmware so there's no point printing OS Timestamps on Guests */ if (!PVRSRV_VZ_MODE_IS(GUEST)) { - PVR_DUMPDEBUG_LOG(" %s CRTimer = 0x%012"IMG_UINT64_FMTSPECx", OSTimer = %" IMG_UINT64_FMTSPEC ".%09" IMG_UINT64_FMTSPEC ", CyclesElapsed = %" IMG_INT64_FMTSPECd, + PVR_DUMPDEBUG_LOG(" %s CRTimer = 0x%012"IMG_UINT64_FMTSPECX", OSTimer = %" IMG_UINT64_FMTSPEC ".%09" IMG_UINT64_FMTSPEC ", CyclesElapsed = %" IMG_INT64_FMTSPECd, aui8RecoveryNum, psHWRInfo->ui64CRTimer, ui64Seconds, @@ -3610,7 +3607,7 @@ static void _RGXDumpFWHWRInfo(DUMPDEBUG_PRINTF_FUNC *pfnDumpDebugPrintf, } else { - PVR_DUMPDEBUG_LOG(" %s CRTimer = 0x%012"IMG_UINT64_FMTSPECx", CyclesElapsed = %" IMG_INT64_FMTSPECd, + PVR_DUMPDEBUG_LOG(" %s CRTimer = 0x%012"IMG_UINT64_FMTSPECX", CyclesElapsed = %" IMG_INT64_FMTSPECd, aui8RecoveryNum, psHWRInfo->ui64CRTimer, (psHWRInfo->ui64CRTimer-psHWRInfo->ui64CRTimeOfKick)*256); @@ -3726,6 +3723,7 @@ static void _RGXDumpFWHWRInfo(DUMPDEBUG_PRINTF_FUNC *pfnDumpDebugPrintf, } } break; + case RGX_HWRTYPE_MMUMETAFAULT: { if (RGX_IS_FEATURE_SUPPORTED(psDevInfo, S7_TOP_INFRASTRUCTURE)) @@ -3745,7 +3743,6 @@ static void _RGXDumpFWHWRInfo(DUMPDEBUG_PRINTF_FUNC *pfnDumpDebugPrintf, } break; - case RGX_HWRTYPE_POLLFAILURE: { PVR_DUMPDEBUG_LOG(" T%u polling %s (reg:0x%08X mask:0x%08X last:0x%08X)", @@ -4103,6 +4100,7 @@ void RGXDumpRGXDebugSummary(DUMPDEBUG_PRINTF_FUNC *pfnDumpDebugPrintf, #endif /* (RGX_NUM_OS_SUPPORTED > 1) */ #if defined(RGX_VZ_STATIC_CARVEOUT_FW_HEAPS) || (defined(RGX_NUM_OS_SUPPORTED) && (RGX_NUM_OS_SUPPORTED > 1)) + if (!PVRSRV_VZ_MODE_IS(NATIVE)) { RGXFWIF_CONNECTION_FW_STATE eFwState = KM_GET_FW_CONNECTION(psDevInfo); RGXFWIF_CONNECTION_OS_STATE eOsState = KM_GET_OS_CONNECTION(psDevInfo); @@ -4140,6 +4138,7 @@ void RGXDumpRGXDebugSummary(DUMPDEBUG_PRINTF_FUNC *pfnDumpDebugPrintf, } sHwrStateDescription[0] = '\0'; + _Flags2Description(sHwrStateDescription, RGX_DEBUG_STR_SIZE, asHwrState2Description, ARRAY_SIZE(asHwrState2Description), psFwSysData->ui32HWRStateFlags); @@ -4189,16 +4188,17 @@ void RGXDumpRGXDebugSummary(DUMPDEBUG_PRINTF_FUNC *pfnDumpDebugPrintf, for (ui32OSid = 0; ui32OSid < RGX_NUM_OS_SUPPORTED; ui32OSid++) { RGXFWIF_OS_RUNTIME_FLAGS sFwRunFlags = psFwSysData->asOsRuntimeFlagsMirror[ui32OSid]; - IMG_BOOL bMTSEnabled = IMG_FALSE; + IMG_BOOL bMTSEnabled = IMG_FALSE; #if !defined(NO_HARDWARE) - if (bRGXPoweredON) - { - bMTSEnabled = (!RGX_IS_FEATURE_SUPPORTED(psDevInfo, GPU_VIRTUALISATION)) ? IMG_TRUE : - ((OSReadHWReg32(psDevInfo->pvRegsBaseKM, RGX_CR_MTS_SCHEDULE_ENABLE) & BIT(ui32OSid)) != 0); - } + if (bRGXPoweredON) + { + bMTSEnabled = (!RGX_IS_FEATURE_SUPPORTED(psDevInfo, GPU_VIRTUALISATION)) ? IMG_TRUE : + ((OSReadHWReg32(psDevInfo->pvRegsBaseKM, RGX_CR_MTS_SCHEDULE_ENABLE) & BIT(ui32OSid)) != 0); + } #endif + PVR_DUMPDEBUG_LOG("RGX FW OS %u - State: %s; Freelists: %s%s; Priority: %d;%s %s", ui32OSid, apszFwOsStateName[sFwRunFlags.bfOsState], (sFwRunFlags.bfFLOk) ? "Ok" : "Not Ok", @@ -4210,6 +4210,7 @@ void RGXDumpRGXDebugSummary(DUMPDEBUG_PRINTF_FUNC *pfnDumpDebugPrintf, bOsIsolationEnabled |= sFwRunFlags.bfIsolatedOS; } + #if defined(PVR_ENABLE_PHR) { IMG_CHAR sPHRConfigDescription[RGX_DEBUG_STR_SIZE]; @@ -4223,6 +4224,14 @@ void RGXDumpRGXDebugSummary(DUMPDEBUG_PRINTF_FUNC *pfnDumpDebugPrintf, } #endif + if (bRGXPoweredON && RGX_IS_FEATURE_SUPPORTED(psDevInfo, GPU_MULTICORE_SUPPORT)) + { + if (OSReadHWReg32(psDevInfo->pvRegsBaseKM, RGX_CR_MULTICORE_SYSTEM) > 1U) + { + PVR_DUMPDEBUG_LOG("RGX MC Configuration: 0x%X (1:primary, 0:secondary)", psFwSysData->ui32McConfig); + } + } + if (bOsIsolationEnabled) { PVR_DUMPDEBUG_LOG("RGX Hard Context Switch deadline: %u ms", psDevInfo->psRGXFWIfRuntimeCfg->ui32HCSDeadlineMS); @@ -4533,9 +4542,12 @@ void RGXDumpFirmwareTrace(DUMPDEBUG_PRINTF_FUNC *pfnDumpDebugPrintf, /* Print the decoded log for each thread... */ for (tid = 0; tid < RGXFW_THREAD_NUM; tid++) { - IMG_UINT32 *pui32TraceBuf = psRGXFWIfTraceBufCtl->sTraceBuf[tid].pui32TraceBuffer; - IMG_UINT32 ui32TracePtr = psRGXFWIfTraceBufCtl->sTraceBuf[tid].ui32TracePointer; - IMG_UINT32 ui32Count = 0; + volatile IMG_UINT32 *pui32FWWrapCount = &(psRGXFWIfTraceBufCtl->sTraceBuf[tid].sAssertBuf.ui32LineNum); + volatile IMG_UINT32 *pui32FWTracePtr = &(psRGXFWIfTraceBufCtl->sTraceBuf[tid].ui32TracePointer); + IMG_UINT32 *pui32TraceBuf = psRGXFWIfTraceBufCtl->sTraceBuf[tid].pui32TraceBuffer; + IMG_UINT32 ui32HostWrapCount = *pui32FWWrapCount; + IMG_UINT32 ui32HostTracePtr = *pui32FWTracePtr; + IMG_UINT32 ui32Count = 0; if (pui32TraceBuf == NULL) { @@ -4550,7 +4562,7 @@ void RGXDumpFirmwareTrace(DUMPDEBUG_PRINTF_FUNC *pfnDumpDebugPrintf, /* Find the first valid log ID, skipping whitespace... */ do { - ui32Data = pui32TraceBuf[ui32TracePtr]; + ui32Data = pui32TraceBuf[ui32HostTracePtr]; ui32DataToId = idToStringID(ui32Data, SFs); /* If an unrecognized id is found it may be inconsistent data or a firmware trace error. */ @@ -4560,7 +4572,12 @@ void RGXDumpFirmwareTrace(DUMPDEBUG_PRINTF_FUNC *pfnDumpDebugPrintf, } /* Update the trace pointer... */ - ui32TracePtr = (ui32TracePtr + 1) % ui32TraceBufSizeInDWords; + ui32HostTracePtr++; + if (ui32HostTracePtr >= ui32TraceBufSizeInDWords) + { + ui32HostTracePtr = 0; + ui32HostWrapCount++; + } ui32Count++; } while ((RGXFW_SF_LAST == ui32DataToId) && ui32Count < ui32TraceBufSizeInDWords); @@ -4582,8 +4599,8 @@ void RGXDumpFirmwareTrace(DUMPDEBUG_PRINTF_FUNC *pfnDumpDebugPrintf, break; } - ui64Timestamp = (IMG_UINT64)(pui32TraceBuf[(ui32TracePtr + 0) % ui32TraceBufSizeInDWords]) << 32 | - (IMG_UINT64)(pui32TraceBuf[(ui32TracePtr + 1) % ui32TraceBufSizeInDWords]); + ui64Timestamp = (IMG_UINT64)(pui32TraceBuf[(ui32HostTracePtr + 0) % ui32TraceBufSizeInDWords]) << 32 | + (IMG_UINT64)(pui32TraceBuf[(ui32HostTracePtr + 1) % ui32TraceBufSizeInDWords]); ui16DebugInfo = (IMG_UINT16) ((ui64Timestamp & ~RGXFWT_TIMESTAMP_DEBUG_INFO_CLRMSK) >> RGXFWT_TIMESTAMP_DEBUG_INFO_SHIFT); ui64Timestamp = (ui64Timestamp & ~RGXFWT_TIMESTAMP_TIME_CLRMSK) >> RGXFWT_TIMESTAMP_TIME_SHIFT; @@ -4606,30 +4623,45 @@ void RGXDumpFirmwareTrace(DUMPDEBUG_PRINTF_FUNC *pfnDumpDebugPrintf, } PVR_DUMPDEBUG_LOG(szBuffer, ui64Timestamp, tid, groups[RGXFW_SF_GID(ui32Data)], - pui32TraceBuf[(ui32TracePtr + 2) % ui32TraceBufSizeInDWords], - pui32TraceBuf[(ui32TracePtr + 3) % ui32TraceBufSizeInDWords], - pui32TraceBuf[(ui32TracePtr + 4) % ui32TraceBufSizeInDWords], - pui32TraceBuf[(ui32TracePtr + 5) % ui32TraceBufSizeInDWords], - pui32TraceBuf[(ui32TracePtr + 6) % ui32TraceBufSizeInDWords], - pui32TraceBuf[(ui32TracePtr + 7) % ui32TraceBufSizeInDWords], - pui32TraceBuf[(ui32TracePtr + 8) % ui32TraceBufSizeInDWords], - pui32TraceBuf[(ui32TracePtr + 9) % ui32TraceBufSizeInDWords], - pui32TraceBuf[(ui32TracePtr + 10) % ui32TraceBufSizeInDWords], - pui32TraceBuf[(ui32TracePtr + 11) % ui32TraceBufSizeInDWords], - pui32TraceBuf[(ui32TracePtr + 12) % ui32TraceBufSizeInDWords], - pui32TraceBuf[(ui32TracePtr + 13) % ui32TraceBufSizeInDWords], - pui32TraceBuf[(ui32TracePtr + 14) % ui32TraceBufSizeInDWords], - pui32TraceBuf[(ui32TracePtr + 15) % ui32TraceBufSizeInDWords], - pui32TraceBuf[(ui32TracePtr + 16) % ui32TraceBufSizeInDWords], - pui32TraceBuf[(ui32TracePtr + 17) % ui32TraceBufSizeInDWords], - pui32TraceBuf[(ui32TracePtr + 18) % ui32TraceBufSizeInDWords], - pui32TraceBuf[(ui32TracePtr + 19) % ui32TraceBufSizeInDWords], - pui32TraceBuf[(ui32TracePtr + 20) % ui32TraceBufSizeInDWords], - pui32TraceBuf[(ui32TracePtr + 21) % ui32TraceBufSizeInDWords]); + pui32TraceBuf[(ui32HostTracePtr + 2) % ui32TraceBufSizeInDWords], + pui32TraceBuf[(ui32HostTracePtr + 3) % ui32TraceBufSizeInDWords], + pui32TraceBuf[(ui32HostTracePtr + 4) % ui32TraceBufSizeInDWords], + pui32TraceBuf[(ui32HostTracePtr + 5) % ui32TraceBufSizeInDWords], + pui32TraceBuf[(ui32HostTracePtr + 6) % ui32TraceBufSizeInDWords], + pui32TraceBuf[(ui32HostTracePtr + 7) % ui32TraceBufSizeInDWords], + pui32TraceBuf[(ui32HostTracePtr + 8) % ui32TraceBufSizeInDWords], + pui32TraceBuf[(ui32HostTracePtr + 9) % ui32TraceBufSizeInDWords], + pui32TraceBuf[(ui32HostTracePtr + 10) % ui32TraceBufSizeInDWords], + pui32TraceBuf[(ui32HostTracePtr + 11) % ui32TraceBufSizeInDWords], + pui32TraceBuf[(ui32HostTracePtr + 12) % ui32TraceBufSizeInDWords], + pui32TraceBuf[(ui32HostTracePtr + 13) % ui32TraceBufSizeInDWords], + pui32TraceBuf[(ui32HostTracePtr + 14) % ui32TraceBufSizeInDWords], + pui32TraceBuf[(ui32HostTracePtr + 15) % ui32TraceBufSizeInDWords], + pui32TraceBuf[(ui32HostTracePtr + 16) % ui32TraceBufSizeInDWords], + pui32TraceBuf[(ui32HostTracePtr + 17) % ui32TraceBufSizeInDWords], + pui32TraceBuf[(ui32HostTracePtr + 18) % ui32TraceBufSizeInDWords], + pui32TraceBuf[(ui32HostTracePtr + 19) % ui32TraceBufSizeInDWords], + pui32TraceBuf[(ui32HostTracePtr + 20) % ui32TraceBufSizeInDWords], + pui32TraceBuf[(ui32HostTracePtr + 21) % ui32TraceBufSizeInDWords]); /* Update the trace pointer... */ - ui32TracePtr = (ui32TracePtr + 2 + RGXFW_SF_PARAMNUM(ui32Data)) % ui32TraceBufSizeInDWords; - ui32Count = (ui32Count + 2 + RGXFW_SF_PARAMNUM(ui32Data)); + ui32HostTracePtr = ui32HostTracePtr + 2 + RGXFW_SF_PARAMNUM(ui32Data); + if (ui32HostTracePtr >= ui32TraceBufSizeInDWords) + { + ui32HostTracePtr = ui32HostTracePtr % ui32TraceBufSizeInDWords; + ui32HostWrapCount++; + } + ui32Count = (ui32Count + 2 + RGXFW_SF_PARAMNUM(ui32Data)); + + /* Has the FW trace buffer overtaken the host pointer during the last line printed??? */ + if ((*pui32FWWrapCount > ui32HostWrapCount) || + ((*pui32FWWrapCount == ui32HostWrapCount) && (*pui32FWTracePtr > ui32HostTracePtr))) + { + /* Move forward to the oldest entry again... */ + PVR_DUMPDEBUG_LOG(". . ."); + ui32HostWrapCount = *pui32FWWrapCount; + ui32HostTracePtr = *pui32FWTracePtr; + } } } } @@ -4740,6 +4772,7 @@ static const IMG_CHAR* _RGXGetDebugDevPowerStateString(PVRSRV_DEV_POWER_STATE eP #define DDLOG64_DPX(R) PVR_DUMPDEBUG_LOG(REG64_FMTSPEC, #R, OSReadHWReg64(pvRegsBaseKM, DPX_CR_##R)); #define DDLOGVAL32(S,V) PVR_DUMPDEBUG_LOG(REG32_FMTSPEC, S, V); +#if !defined(SUPPORT_TRUSTED_DEVICE) #if !defined(NO_HARDWARE) static void RGXDumpMIPSState(DUMPDEBUG_PRINTF_FUNC *pfnDumpDebugPrintf, void *pvDumpDebugFile, @@ -4841,6 +4874,7 @@ static void RGXDumpMIPSState(DUMPDEBUG_PRINTF_FUNC *pfnDumpDebugPrintf, PVR_DUMPDEBUG_LOG("--------------------------------"); } #endif +#endif /* !defined(SUPPORT_TRUSTED_DEVICE) */ static PVRSRV_ERROR RGXDumpRISCVState(DUMPDEBUG_PRINTF_FUNC *pfnDumpDebugPrintf, void *pvDumpDebugFile, @@ -4851,11 +4885,6 @@ static PVRSRV_ERROR RGXDumpRISCVState(DUMPDEBUG_PRINTF_FUNC *pfnDumpDebugPrintf, const IMG_CHAR *pszException; PVRSRV_ERROR eError; -#if defined(NO_HARDWARE) - /* OSReadHWReg variants don't use params passed in NoHW builds */ - PVR_UNREFERENCED_PARAMETER(pvRegsBaseKM); -#endif - DDLOG64(FWCORE_MEM_CAT_BASE0); DDLOG64(FWCORE_MEM_CAT_BASE1); DDLOG64(FWCORE_MEM_CAT_BASE2); @@ -4945,11 +4974,6 @@ PVRSRV_ERROR RGXDumpRGXRegisters(DUMPDEBUG_PRINTF_FUNC *pfnDumpDebugPrintf, /* Check if firmware perf was set at Init time */ bFirmwarePerf = (psDevInfo->psRGXFWIfSysInit->eFirmwarePerf != FW_PERF_CONF_NONE); -#if defined(NO_HARDWARE) - /* OSReadHWReg variants don't use params passed in NoHW builds */ - PVR_UNREFERENCED_PARAMETER(pvRegsBaseKM); -#endif - if (RGX_IS_FEATURE_SUPPORTED(psDevInfo, PBVNC_COREID_REG)) { DDLOG64(CORE_ID); @@ -5174,16 +5198,16 @@ PVRSRV_ERROR RGXDumpRGXRegisters(DUMPDEBUG_PRINTF_FUNC *pfnDumpDebugPrintf, /* Forcing bit 6 of MslvCtrl1 to 0 to avoid internal reg read going through the core */ OSWriteHWReg32(psDevInfo->pvRegsBaseKM, RGX_CR_META_SP_MSLVCTRL1, 0x0); - eError = RGXReadWithSP(psDevInfo, META_CR_T0ENABLE_OFFSET, &ui32RegVal); - PVR_LOG_GOTO_IF_ERROR(eError, "RGXReadWithSP", _METASPError); + eError = RGXReadFWModuleAddr(psDevInfo, META_CR_T0ENABLE_OFFSET, &ui32RegVal); + PVR_LOG_GOTO_IF_ERROR(eError, "RGXReadFWModuleAddr", _METASPError); DDLOGVAL32("T0 TXENABLE", ui32RegVal); if (ui32RegVal & META_CR_TXENABLE_ENABLE_BIT) { bIsT0Enabled = IMG_TRUE; } - eError = RGXReadWithSP(psDevInfo, META_CR_T0STATUS_OFFSET, &ui32RegVal); - PVR_LOG_GOTO_IF_ERROR(eError, "RGXReadWithSP", _METASPError); + eError = RGXReadFWModuleAddr(psDevInfo, META_CR_T0STATUS_OFFSET, &ui32RegVal); + PVR_LOG_GOTO_IF_ERROR(eError, "RGXReadFWModuleAddr", _METASPError); DDLOGVAL32("T0 TXSTATUS", ui32RegVal); /* check for FW fault */ @@ -5192,8 +5216,8 @@ PVRSRV_ERROR RGXDumpRGXRegisters(DUMPDEBUG_PRINTF_FUNC *pfnDumpDebugPrintf, bIsFWFaulted = IMG_TRUE; } - eError = RGXReadWithSP(psDevInfo, META_CR_T0DEFR_OFFSET, &ui32RegVal); - PVR_LOG_GOTO_IF_ERROR(eError, "RGXReadWithSP", _METASPError); + eError = RGXReadFWModuleAddr(psDevInfo, META_CR_T0DEFR_OFFSET, &ui32RegVal); + PVR_LOG_GOTO_IF_ERROR(eError, "RGXReadFWModuleAddr", _METASPError); DDLOGVAL32("T0 TXDEFR", ui32RegVal); eError = RGXReadMetaCoreReg(psDevInfo, META_CR_THR0_PC, &ui32RegVal); @@ -5210,16 +5234,16 @@ PVRSRV_ERROR RGXDumpRGXRegisters(DUMPDEBUG_PRINTF_FUNC *pfnDumpDebugPrintf, if ((ui32Meta == MTP218) || (ui32Meta == MTP219)) { - eError = RGXReadWithSP(psDevInfo, META_CR_T1ENABLE_OFFSET, &ui32RegVal); - PVR_LOG_GOTO_IF_ERROR(eError, "RGXReadWithSP", _METASPError); + eError = RGXReadFWModuleAddr(psDevInfo, META_CR_T1ENABLE_OFFSET, &ui32RegVal); + PVR_LOG_GOTO_IF_ERROR(eError, "RGXReadFWModuleAddr", _METASPError); DDLOGVAL32("T1 TXENABLE", ui32RegVal); - eError = RGXReadWithSP(psDevInfo, META_CR_T1STATUS_OFFSET, &ui32RegVal); - PVR_LOG_GOTO_IF_ERROR(eError, "RGXReadWithSP", _METASPError); + eError = RGXReadFWModuleAddr(psDevInfo, META_CR_T1STATUS_OFFSET, &ui32RegVal); + PVR_LOG_GOTO_IF_ERROR(eError, "RGXReadFWModuleAddr", _METASPError); DDLOGVAL32("T1 TXSTATUS", ui32RegVal); - eError = RGXReadWithSP(psDevInfo, META_CR_T1DEFR_OFFSET, &ui32RegVal); - PVR_LOG_GOTO_IF_ERROR(eError, "RGXReadWithSP", _METASPError); + eError = RGXReadFWModuleAddr(psDevInfo, META_CR_T1DEFR_OFFSET, &ui32RegVal); + PVR_LOG_GOTO_IF_ERROR(eError, "RGXReadFWModuleAddr", _METASPError); DDLOGVAL32("T1 TXDEFR", ui32RegVal); eError = RGXReadMetaCoreReg(psDevInfo, META_CR_THR1_PC, &ui32RegVal); @@ -5237,12 +5261,12 @@ PVRSRV_ERROR RGXDumpRGXRegisters(DUMPDEBUG_PRINTF_FUNC *pfnDumpDebugPrintf, if (bFirmwarePerf) { - eError = RGXReadWithSP(psDevInfo, META_CR_PERF_COUNT0, &ui32RegVal); - PVR_LOG_GOTO_IF_ERROR(eError, "RGXReadWithSP", _METASPError); + eError = RGXReadFWModuleAddr(psDevInfo, META_CR_PERF_COUNT0, &ui32RegVal); + PVR_LOG_GOTO_IF_ERROR(eError, "RGXReadFWModuleAddr", _METASPError); DDLOGVAL32("PERF_COUNT0", ui32RegVal); - eError = RGXReadWithSP(psDevInfo, META_CR_PERF_COUNT1, &ui32RegVal); - PVR_LOG_GOTO_IF_ERROR(eError, "RGXReadWithSP", _METASPError); + eError = RGXReadFWModuleAddr(psDevInfo, META_CR_PERF_COUNT1, &ui32RegVal); + PVR_LOG_GOTO_IF_ERROR(eError, "RGXReadFWModuleAddr", _METASPError); DDLOGVAL32("PERF_COUNT1", ui32RegVal); } @@ -5275,7 +5299,9 @@ PVRSRV_ERROR RGXDumpRGXRegisters(DUMPDEBUG_PRINTF_FUNC *pfnDumpDebugPrintf, DDLOG64(MIPS_WRAPPER_CONFIG); DDLOG32(MIPS_EXCEPTION_STATUS); -#if !defined(NO_HARDWARE) +#if defined(SUPPORT_TRUSTED_DEVICE) + PVR_DUMPDEBUG_LOG("MIPS extra debug not available with SUPPORT_TRUSTED_DEVICE."); +#elif !defined(NO_HARDWARE) RGXDumpMIPSState(pfnDumpDebugPrintf, pvDumpDebugFile, psDevInfo); #endif } diff --git a/drivers/gpu/drm/img-rogue/rgxdebug.h b/drivers/gpu/drm/img-rogue/rgxdebug.h index afe081880..f163997ac 100644 --- a/drivers/gpu/drm/img-rogue/rgxdebug.h +++ b/drivers/gpu/drm/img-rogue/rgxdebug.h @@ -105,6 +105,9 @@ static inline void RGXDEBUG_PRINT_IRQ_COUNT(PVRSRV_RGXDEV_INFO* psRgxDevInfo) #endif /* PVRSRV_NEED_PVR_DPF */ } +extern const IMG_CHAR * const gapszMipsPermissionPTFlags[4]; +extern const IMG_CHAR * const gapszMipsCoherencyPTFlags[8]; +extern const IMG_CHAR * const gapszMipsDirtyGlobalValidPTFlags[8]; /*! ******************************************************************************* @@ -153,42 +156,6 @@ void RGXDumpPowerMonitoring(DUMPDEBUG_PRINTF_FUNC *pfnDumpDebugPrintf, PVRSRV_RGXDEV_INFO *psDevInfo); #endif -/*! -******************************************************************************* - - @Function RGXReadWithSP - - @Description - - Reads data from a memory location (FW memory map) using the META Slave Port - - @Input psDevInfo - Pointer to RGX DevInfo to be used while reading - @Input ui32FWAddr - 32 bit FW address - @Input pui32Value - When the read is successful, value at above FW address - is returned at this location - - @Return PVRSRV_ERROR PVRSRV_OK if read success, error code otherwise. -******************************************************************************/ -PVRSRV_ERROR RGXReadWithSP(PVRSRV_RGXDEV_INFO *psDevInfo, IMG_UINT32 ui32FWAddr, IMG_UINT32 *pui32Value); - -/*! -******************************************************************************* - - @Function RGXWriteWithSP - - @Description - - Writes data to a memory location (FW memory map) using the META Slave Port - - @Input psDevInfo - Pointer to RGX DevInfo to be used while writing - @Input ui32FWAddr - 32 bit FW address - - @Input ui32Value - 32 bit Value to write - - @Return PVRSRV_ERROR PVRSRV_OK if write success, error code otherwise. -******************************************************************************/ -PVRSRV_ERROR RGXWriteWithSP(PVRSRV_RGXDEV_INFO *psDevInfo, IMG_UINT32 ui32FWAddr, IMG_UINT32 ui32Value); - #if defined(SUPPORT_FW_VIEW_EXTRA_DEBUG) /*! ******************************************************************************* @@ -196,8 +163,8 @@ PVRSRV_ERROR RGXWriteWithSP(PVRSRV_RGXDEV_INFO *psDevInfo, IMG_UINT32 ui32FWAddr @Function ValidateFWOnLoad @Description Compare the Firmware image as seen from the CPU point of view - against the same memory area as seen from the META point of view - after first power up. + against the same memory area as seen from the firmware point + of view after first power up. @Input psDevInfo - Device Info diff --git a/drivers/gpu/drm/img-rogue/rgxdevice.h b/drivers/gpu/drm/img-rogue/rgxdevice.h index 585452f8b..4ebbd2915 100644 --- a/drivers/gpu/drm/img-rogue/rgxdevice.h +++ b/drivers/gpu/drm/img-rogue/rgxdevice.h @@ -198,6 +198,7 @@ typedef struct _PVRSRV_DEVICE_FEATURE_CONFIG_ IMG_UINT32 ui32N; IMG_UINT32 ui32C; IMG_UINT32 ui32FeaturesValues[RGX_FEATURE_WITH_VALUES_MAX_IDX]; + IMG_UINT32 ui32MAXDMCount; IMG_UINT32 ui32MAXDustCount; IMG_UINT32 ui32SLCSizeInBytes; IMG_PCHAR pszBVNCString; @@ -517,6 +518,7 @@ typedef struct _PVRSRV_RGXDEV_INFO_ DEVMEM_MEMDESC *psRGXFWIfConnectionCtlMemDesc; RGXFWIF_CONNECTION_CTL *psRGXFWIfConnectionCtl; + DEVMEM_MEMDESC *psRGXFWHeapGuardPageReserveMemDesc; DEVMEM_MEMDESC *psRGXFWIfSysInitMemDesc; RGXFWIF_SYSINIT *psRGXFWIfSysInit; @@ -729,6 +731,15 @@ typedef struct _PVRSRV_RGXDEV_INFO_ IMG_UINT32 ui32FirmwareGcovSize; #endif +#if defined(SUPPORT_VALIDATION) && defined(SUPPORT_SOC_TIMER) + struct + { + IMG_UINT64 ui64timerGray; + IMG_UINT64 ui64timerBinary; + IMG_UINT64 *pui64uscTimers; + } sRGXTimerValues; +#endif + #if defined(SUPPORT_VALIDATION) struct { diff --git a/drivers/gpu/drm/img-rogue/rgxfwdbg.c b/drivers/gpu/drm/img-rogue/rgxfwdbg.c index 9126258ec..1e7a51f5f 100644 --- a/drivers/gpu/drm/img-rogue/rgxfwdbg.c +++ b/drivers/gpu/drm/img-rogue/rgxfwdbg.c @@ -111,7 +111,7 @@ PVRSRVRGXFWDebugSetFWLogKM( * before requesting the FW to read it */ psDevInfo->psRGXFWIfTraceBufCtl->ui32LogType = ui32RGXFWLogType; - OSMemoryBarrier(); + OSMemoryBarrier(&psDevInfo->psRGXFWIfTraceBufCtl->ui32LogType); /* Allocate firmware trace buffer resource(s) if not already done */ if (RGXTraceBufferIsInitRequired(psDevInfo)) @@ -139,7 +139,7 @@ PVRSRVRGXFWDebugSetFWLogKM( "%s: Failed to allocate resource on-demand. Reverting to old value", __func__)); psDevInfo->psRGXFWIfTraceBufCtl->ui32LogType = ui32OldRGXFWLogTpe; - OSMemoryBarrier(); + OSMemoryBarrier(&psDevInfo->psRGXFWIfTraceBufCtl->ui32LogType); OSLockRelease(psDevInfo->hRGXFWIfBufInitLock); diff --git a/drivers/gpu/drm/img-rogue/rgxfwimageutils.c b/drivers/gpu/drm/img-rogue/rgxfwimageutils.c index 8ab32e40d..0a9813bea 100644 --- a/drivers/gpu/drm/img-rogue/rgxfwimageutils.c +++ b/drivers/gpu/drm/img-rogue/rgxfwimageutils.c @@ -177,6 +177,7 @@ found: @Return void ******************************************************************************/ +#if defined(RGX_FEATURE_META_MAX_VALUE_IDX) static void RGXFWConfigureSegID(const void *hPrivate, IMG_UINT64 ui64SegOutAddr, IMG_UINT32 ui32SegBase, @@ -217,6 +218,7 @@ static void RGXFWConfigureSegID(const void *hPrivate, *ppui32BootConf = pui32BootConf; } +#endif /*! ******************************************************************************* @@ -233,6 +235,7 @@ static void RGXFWConfigureSegID(const void *hPrivate, @Return void ******************************************************************************/ +#if defined(RGX_FEATURE_META_MAX_VALUE_IDX) static void RGXFWConfigureSegMMU(const void *hPrivate, IMG_DEV_VIRTADDR *psFWCodeDevVAddrBase, IMG_DEV_VIRTADDR *psFWDataDevVAddrBase, @@ -282,6 +285,7 @@ static void RGXFWConfigureSegMMU(const void *hPrivate, } } } +#endif /*! ******************************************************************************* @@ -297,6 +301,7 @@ static void RGXFWConfigureSegMMU(const void *hPrivate, @Return void ******************************************************************************/ +#if defined(RGX_FEATURE_META_MAX_VALUE_IDX) static void RGXFWConfigureMetaCaches(const void *hPrivate, IMG_UINT32 ui32NumThreads, IMG_UINT32 **ppui32BootConf) @@ -413,6 +418,7 @@ static void RGXFWConfigureMetaCaches(const void *hPrivate, *ppui32BootConf = pui32BootConf; } +#endif /*! ******************************************************************************* @@ -895,16 +901,23 @@ PVRSRV_ERROR RGXProcessFWImage(const void *hPrivate, { PVRSRV_ERROR eError = PVRSRV_OK; IMG_BOOL bMIPS = IMG_FALSE; +#if defined(RGX_FEATURE_RISCV_FW_PROCESSOR_BIT_MASK) IMG_BOOL bRISCV = RGX_DEVICE_HAS_FEATURE(hPrivate, RISCV_FW_PROCESSOR); +#endif IMG_BOOL bMETA; #if defined(RGX_FEATURE_MIPS_BIT_MASK) bMIPS = (IMG_BOOL)RGX_DEVICE_HAS_FEATURE(hPrivate, MIPS); #endif +#if defined(RGX_FEATURE_RISCV_FW_PROCESSOR_BIT_MASK) bMETA = (IMG_BOOL)(!bMIPS && !bRISCV); +#else + bMETA = !bMIPS; +#endif if (bMETA) { +#if defined(RGX_FEATURE_META_MAX_VALUE_IDX) IMG_UINT32 *pui32BootConf = NULL; /* Skip bootloader configuration if a pointer to the FW code * allocation is not available @@ -974,17 +987,20 @@ PVRSRV_ERROR RGXProcessFWImage(const void *hPrivate, *pui32BootConf++ = 0; } +#if defined(RGX_FEATURE_META_DMA_BIT_MASK) if (RGX_DEVICE_HAS_FEATURE(hPrivate, META_DMA)) { *pui32BootConf++ = (IMG_UINT32) (puFWParams->sMeta.sFWCorememCodeDevVAddr.uiAddr >> 32); *pui32BootConf++ = (IMG_UINT32) puFWParams->sMeta.sFWCorememCodeDevVAddr.uiAddr; } else +#endif { *pui32BootConf++ = 0; *pui32BootConf++ = 0; } } +#endif /* defined(RGX_FEATURE_META_MAX_VALUE_IDX) */ } #if defined(RGXMIPSFW_MAX_NUM_PAGETABLE_PAGES) else if (bMIPS) diff --git a/drivers/gpu/drm/img-rogue/rgxfwutils.c b/drivers/gpu/drm/img-rogue/rgxfwutils.c index 6d50a3f57..2e98cd205 100644 --- a/drivers/gpu/drm/img-rogue/rgxfwutils.c +++ b/drivers/gpu/drm/img-rogue/rgxfwutils.c @@ -82,6 +82,8 @@ CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. #include "dc_server.h" #endif #include "rgxmem.h" +#include "rgxmmudefs_km.h" +#include "rgxmipsmmuinit.h" #include "rgxta3d.h" #include "rgxkicksync.h" #include "rgxutils.h" @@ -118,6 +120,10 @@ CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. #include "rgxpdvfs.h" #endif +#if defined(SUPPORT_VALIDATION) && defined(SUPPORT_SOC_TIMER) +#include "rgxsoctimer.h" +#endif + #include "vz_vmm_pvz.h" #include "rgx_heaps.h" @@ -154,7 +160,7 @@ const IMG_UINT32 gaui32FwOsIrqCntRegAddr[RGXFW_MAX_NUM_OS] = {IRQ_COUNTER_STORAG */ #if defined(FPGA) || defined(EMULATOR) || defined(VIRTUAL_PLATFORM) || defined(PDUMP) #define RGXFWIF_MAX_WORKLOAD_DEADLINE_MS (480000) -#define RGXFWIF_MAX_CDM_WORKLOAD_DEADLINE_MS (90000) +#define RGXFWIF_MAX_CDM_WORKLOAD_DEADLINE_MS (1000000) #else #define RGXFWIF_MAX_WORKLOAD_DEADLINE_MS (40000) #define RGXFWIF_MAX_CDM_WORKLOAD_DEADLINE_MS (90000) @@ -187,6 +193,7 @@ static_assert(sizeof(IMG_PID) == sizeof(IMG_UINT32), static void RGXFreeFwOsData(PVRSRV_RGXDEV_INFO *psDevInfo); static void RGXFreeFwSysData(PVRSRV_RGXDEV_INFO *psDevInfo); +#if defined(RGX_FEATURE_SLC_VIVT_BIT_MASK) static PVRSRV_ERROR _AllocateSLC3Fence(PVRSRV_RGXDEV_INFO* psDevInfo, RGXFWIF_SYSINIT* psFwSysInit) { PVRSRV_ERROR eError; @@ -233,16 +240,21 @@ static void _FreeSLC3Fence(PVRSRV_RGXDEV_INFO* psDevInfo) DevmemFree(psSLC3FenceMemDesc); } } +#endif static void __MTSScheduleWrite(PVRSRV_RGXDEV_INFO *psDevInfo, IMG_UINT32 ui32Value) { /* ensure memory is flushed before kicking MTS */ - OSWriteMemoryBarrier(); + OSWriteMemoryBarrier(NULL); OSWriteHWReg32(psDevInfo->pvRegsBaseKM, RGX_CR_MTS_SCHEDULE, ui32Value); /* ensure the MTS kick goes through before continuing */ - OSMemoryBarrier(); +#if !defined(NO_HARDWARE) && !defined(INTEGRITY_OS) + OSWriteMemoryBarrier((IMG_BYTE*) psDevInfo->pvRegsBaseKM + RGX_CR_MTS_SCHEDULE); +#else + OSWriteMemoryBarrier(NULL); +#endif } /*************************************************************************/ /*! @@ -606,7 +618,7 @@ static PVRSRV_ERROR RGXFWSetupAlignChecks(PVRSRV_DEVICE_NODE *psDeviceNode, *paui32AlignChecks = 0; } - OSWriteMemoryBarrier(); + OSWriteMemoryBarrier(paui32AlignChecks); DevmemPDumpLoadMem(psDevInfo->psRGXFWAlignChecksMemDesc, 0, @@ -643,6 +655,7 @@ PVRSRV_ERROR RGXSetFirmwareAddress(RGXFWIF_DEV_VIRTADDR *ppDest, psDeviceNode = (PVRSRV_DEVICE_NODE *) DevmemGetConnection(psSrc); psDevInfo = (PVRSRV_RGXDEV_INFO *)psDeviceNode->pvDevice; +#if defined(RGX_FEATURE_META_MAX_VALUE_IDX) if (RGX_IS_FEATURE_VALUE_SUPPORTED(psDevInfo, META)) { IMG_UINT32 ui32Offset; @@ -687,7 +700,9 @@ PVRSRV_ERROR RGXSetFirmwareAddress(RGXFWIF_DEV_VIRTADDR *ppDest, } ppDest->ui32Addr = ui32Offset; } - else if (RGX_IS_FEATURE_SUPPORTED(psDevInfo, MIPS)) + else +#endif + if (RGX_IS_FEATURE_SUPPORTED(psDevInfo, MIPS)) { eError = DevmemAcquireDevVirtAddr(psSrc, &psDevVirtAddr); PVR_GOTO_IF_ERROR(eError, failDevVAAcquire); @@ -743,8 +758,10 @@ PVRSRV_ERROR RGXSetFirmwareAddress(RGXFWIF_DEV_VIRTADDR *ppDest, return PVRSRV_OK; +#if defined(RGX_FEATURE_META_MAX_VALUE_IDX) failDevCacheMode: DevmemReleaseDevVirtAddr(psSrc); +#endif failDevVAAcquire: return eError; } @@ -789,7 +806,7 @@ struct _RGX_SERVER_COMMON_CONTEXT_ { DLLIST_NODE sListNode; RGX_CONTEXT_RESET_REASON eLastResetReason; IMG_UINT32 ui32LastResetJobRef; - IMG_UINT32 ui32Priority; + IMG_INT32 i32Priority; RGX_CCB_REQUESTOR_TYPE eRequestor; }; @@ -797,16 +814,16 @@ struct _RGX_SERVER_COMMON_CONTEXT_ { @Function _CheckPriority @Description Check if priority is allowed for requestor type @Input psDevInfo pointer to DevInfo struct -@Input ui32Priority Requested priority +@Input i32Priority Requested priority @Input eRequestor Requestor type specifying data master @Return PVRSRV_ERROR PVRSRV_OK on success */ /**************************************************************************/ static PVRSRV_ERROR _CheckPriority(PVRSRV_RGXDEV_INFO *psDevInfo, - IMG_UINT32 ui32Priority, + IMG_INT32 i32Priority, RGX_CCB_REQUESTOR_TYPE eRequestor) { /* Only one context allowed with real time priority (highest priority) */ - if (ui32Priority == RGX_CTX_PRIORITY_REALTIME) + if (i32Priority == RGX_CTX_PRIORITY_REALTIME) { DLLIST_NODE *psNode, *psNext; @@ -815,7 +832,7 @@ static PVRSRV_ERROR _CheckPriority(PVRSRV_RGXDEV_INFO *psDevInfo, RGX_SERVER_COMMON_CONTEXT *psThisContext = IMG_CONTAINER_OF(psNode, RGX_SERVER_COMMON_CONTEXT, sListNode); - if (psThisContext->ui32Priority == RGX_CTX_PRIORITY_REALTIME && + if (psThisContext->i32Priority == RGX_CTX_PRIORITY_REALTIME && psThisContext->eRequestor == eRequestor) { PVR_LOG(("Only one context with real time priority allowed")); @@ -850,6 +867,7 @@ PVRSRV_ERROR FWCommonContextAllocate(CONNECTION_DATA *psConnection, RGXFWIF_FWCOMMONCONTEXT *psFWCommonContext; IMG_UINT32 ui32FWCommonContextOffset; IMG_UINT8 *pui8Ptr; + IMG_INT32 i32Priority = (IMG_INT32)ui32Priority; PVRSRV_ERROR eError; /* @@ -953,6 +971,7 @@ PVRSRV_ERROR FWCommonContextAllocate(CONNECTION_DATA *psConnection, 0, RFW_FWADDR_FLAG_NONE); PVR_LOG_GOTO_IF_ERROR(eError, "RGXSetFirmwareAddress:2", fail_cccbctrlfwaddr); +#if defined(RGX_FEATURE_META_DMA_CHANNEL_COUNT_MAX_VALUE_IDX) if (RGX_IS_FEATURE_SUPPORTED(psDevInfo, META_DMA)) { RGXSetMetaDMAAddress(&psFWCommonContext->sCCBMetaDMAAddr, @@ -960,6 +979,7 @@ PVRSRV_ERROR FWCommonContextAllocate(CONNECTION_DATA *psConnection, &psFWCommonContext->psCCB, 0); } +#endif /* Set the memory context device address */ psServerCommonContext->psFWMemContextMemDesc = psFWMemContextMemDesc; @@ -985,13 +1005,13 @@ PVRSRV_ERROR FWCommonContextAllocate(CONNECTION_DATA *psConnection, psFWCommonContext->psRFCmd.ui32Addr = 0; } - eError = _CheckPriority(psDevInfo, ui32Priority, eRGXCCBRequestor); + eError = _CheckPriority(psDevInfo, i32Priority, eRGXCCBRequestor); PVR_LOG_GOTO_IF_ERROR(eError, "_CheckPriority", fail_checkpriority); - psServerCommonContext->ui32Priority = ui32Priority; + psServerCommonContext->i32Priority = i32Priority; psServerCommonContext->eRequestor = eRGXCCBRequestor; - psFWCommonContext->ui32Priority = ui32Priority; + psFWCommonContext->i32Priority = i32Priority; psFWCommonContext->ui32PrioritySeqNum = 0; psFWCommonContext->ui32MaxDeadlineMS = MIN(ui32MaxDeadlineMS, (eDM == RGXFWIF_DM_CDM ? @@ -1202,8 +1222,21 @@ PVRSRV_ERROR RGXGetFWCommonContextAddrFromServerMMUCtx(PVRSRV_RGXDEV_INFO *psDev PVRSRV_ERROR FWCommonContextSetFlags(RGX_SERVER_COMMON_CONTEXT *psServerCommonContext, IMG_UINT32 ui32ContextFlags) { - return RGXSetCCBFlags(psServerCommonContext->psClientCCB, - ui32ContextFlags); + PVRSRV_ERROR eError = PVRSRV_OK; + + if (BITMASK_ANY(ui32ContextFlags, ~RGX_CONTEXT_FLAGS_WRITEABLE_MASK)) + { + PVR_DPF((PVR_DBG_ERROR, "%s: Context flag(s) invalid or not writeable (%d)", + __func__, ui32ContextFlags)); + eError = PVRSRV_ERROR_INVALID_PARAMS; + } + else + { + RGXSetCCBFlags(psServerCommonContext->psClientCCB, + ui32ContextFlags); + } + + return eError; } /*! @@ -1438,7 +1471,7 @@ static PVRSRV_ERROR RGXSetupFaultReadRegister(PVRSRV_DEVICE_NODE *psDeviceNode, } } - OSWriteMemoryBarrier(); + OSWriteMemoryBarrier(pui32MemoryVirtAddr); DevmemReleaseCpuVirtAddr(psDevInfo->psRGXFaultAddressMemDesc); @@ -1623,7 +1656,7 @@ PVRSRV_ERROR RGXTBIBufferInitOnDemandResources(PVRSRV_RGXDEV_INFO *psDevInfo) } /* flush write buffers for psFW_SFs */ - OSWriteMemoryBarrier(); + OSWriteMemoryBarrier(psFW_SFs); /* Set size of TBI buffer */ psDevInfo->ui32FWIfTBIBufferSize = ui32FWTBIBufsize; @@ -1888,27 +1921,12 @@ static void RGXPDumpLoadFWInitData(PVRSRV_RGXDEV_INFO *psDevInfo, "( Check MList: 0x%08x)", RGXFWIF_INICFG_CHECK_MLIST_EN); PDUMPCOMMENT(psDevInfo->psDeviceNode, "( Disable Auto Clock Gating: 0x%08x)", RGXFWIF_INICFG_DISABLE_CLKGATING_EN); - PDUMPCOMMENT(psDevInfo->psDeviceNode, - "( Enable HWPerf Polling Perf Counter: 0x%08x)", RGXFWIF_INICFG_POLL_COUNTERS_EN); - - if (RGX_IS_FEATURE_SUPPORTED(psDevInfo, VDM_OBJECT_LEVEL_LLS)) - { - PDUMPCOMMENT(psDevInfo->psDeviceNode, - "( Ctx Switch Object mode Index: 0x%08x)", RGXFWIF_INICFG_VDM_CTX_STORE_MODE_INDEX); - PDUMPCOMMENT(psDevInfo->psDeviceNode, - "( Ctx Switch Object mode Instance: 0x%08x)", RGXFWIF_INICFG_VDM_CTX_STORE_MODE_INSTANCE); - PDUMPCOMMENT(psDevInfo->psDeviceNode, - "( Ctx Switch Object mode List: 0x%08x)", RGXFWIF_INICFG_VDM_CTX_STORE_MODE_LIST); - } - PDUMPCOMMENT(psDevInfo->psDeviceNode, "( Enable register configuration: 0x%08x)", RGXFWIF_INICFG_REGCONFIG_EN); PDUMPCOMMENT(psDevInfo->psDeviceNode, "( Assert on TA Out-of-Memory: 0x%08x)", RGXFWIF_INICFG_ASSERT_ON_OUTOFMEMORY); PDUMPCOMMENT(psDevInfo->psDeviceNode, "( Disable HWPerf custom counter filter: 0x%08x)", RGXFWIF_INICFG_HWP_DISABLE_FILTER); - PDUMPCOMMENT(psDevInfo->psDeviceNode, - "( Enable HWPerf custom performance timer: 0x%08x)", RGXFWIF_INICFG_CUSTOM_PERF_TIMER_EN); PDUMPCOMMENT(psDevInfo->psDeviceNode, "( Enable Ctx Switch profile mode: 0x%08x (none=b'000, fast=b'001, medium=b'010, slow=b'011, nodelay=b'100))", RGXFWIF_INICFG_CTXSWITCH_PROFILE_MASK); PDUMPCOMMENT(psDevInfo->psDeviceNode, @@ -2064,11 +2082,13 @@ static void RGXPDumpLoadFWInitData(PVRSRV_RGXDEV_INFO *psDevInfo, PDUMPCOMMENT(psDevInfo->psDeviceNode, "( HWP Group Enable: 0x%08x)", RGXFWIF_LOG_TYPE_GROUP_HWP); +#if defined(RGX_FEATURE_META_DMA_CHANNEL_COUNT_MAX_VALUE_IDX) if (RGX_IS_FEATURE_SUPPORTED(psDevInfo, META_DMA)) { PDUMPCOMMENT(psDevInfo->psDeviceNode, "( DMA Group Enable: 0x%08x)", RGXFWIF_LOG_TYPE_GROUP_DMA); } +#endif PDUMPCOMMENT(psDevInfo->psDeviceNode, "( MISC Group Enable: 0x%08x)", RGXFWIF_LOG_TYPE_GROUP_MISC); @@ -2127,11 +2147,38 @@ static void RGXPDumpLoadFWInitData(PVRSRV_RGXDEV_INFO *psDevInfo, } #endif /* defined(PDUMP) */ +/*! +******************************************************************************* + @Function RGXSetupFwGuardPage + + @Description Allocate a Guard Page at the start of a Guest's Main Heap + + @Input psDevceNode + + @Return PVRSRV_ERROR +******************************************************************************/ +static PVRSRV_ERROR RGXSetupFwGuardPage(PVRSRV_RGXDEV_INFO *psDevInfo) +{ + PVRSRV_ERROR eError; + + eError = RGXSetupFwAllocation(psDevInfo, + (RGX_FWSHAREDMEM_GPU_ONLY_ALLOCFLAGS | + PVRSRV_MEMALLOCFLAG_PHYS_HEAP_HINT(FW_MAIN)), + OSGetPageSize(), + "FwGuardPage", + &psDevInfo->psRGXFWHeapGuardPageReserveMemDesc, + NULL, + NULL, + RFW_FWADDR_FLAG_NONE); + + return eError; +} + /*! ******************************************************************************* @Function RGXSetupFwSysData - @Description Setups all system-wide firmware related data + @Description Sets up all system-wide firmware related data @Input psDevInfo @@ -2176,6 +2223,10 @@ static PVRSRV_ERROR RGXSetupFwSysData(PVRSRV_DEVICE_NODE *psDeviceNode, eError = RGXSetupFaultReadRegister(psDeviceNode, psFwSysInitScratch); PVR_LOG_GOTO_IF_ERROR(eError, "Fault read register setup", fail); +#if defined(SUPPORT_AUTOVZ) + psFwSysInitScratch->ui32VzWdgPeriod = PVR_AUTOVZ_WDG_PERIOD_MS; +#endif + /* RD Power Island */ { RGX_DATA *psRGXData = (RGX_DATA*) psDeviceNode->psDevConfig->hDevData; @@ -2343,6 +2394,7 @@ static PVRSRV_ERROR RGXSetupFwSysData(PVRSRV_DEVICE_NODE *psDeviceNode, switch (ui32EnablePollOnChecksumErrorStatus) { + case 0: /* no checking */ break; case 3: psDevInfo->ui32ValidationFlags |= RGX_VAL_KZ_SIG_CHECK_NOERR_EN; break; case 4: psDevInfo->ui32ValidationFlags |= RGX_VAL_KZ_SIG_CHECK_ERR_EN; break; default: @@ -2384,6 +2436,10 @@ static PVRSRV_ERROR RGXSetupFwSysData(PVRSRV_DEVICE_NODE *psDeviceNode, PVR_LOG_GOTO_IF_ERROR(eError, "3D Signature check setup", fail); psDevInfo->ui32Sig3DChecksSize = ui32SignatureChecksBufSize; + psDevInfo->psRGXFWSigTDM2DChecksMemDesc = NULL; + psDevInfo->ui32SigTDM2DChecksSize = 0; + +#if defined(RGX_FEATURE_TDM_PDS_CHECKSUM_BIT_MASK) if (RGX_IS_FEATURE_SUPPORTED(psDevInfo, TDM_PDS_CHECKSUM)) { /* Buffer allocated only when feature present because, all known TDM @@ -2395,11 +2451,6 @@ static PVRSRV_ERROR RGXSetupFwSysData(PVRSRV_DEVICE_NODE *psDeviceNode, PVR_LOG_GOTO_IF_ERROR(eError, "TDM Signature check setup", fail); psDevInfo->ui32SigTDM2DChecksSize = ui32SignatureChecksBufSize; } - else - { - psDevInfo->psRGXFWSigTDM2DChecksMemDesc = NULL; - psDevInfo->ui32SigTDM2DChecksSize = 0; - } #endif if (!bEnableSignatureChecks) @@ -2408,6 +2459,7 @@ static PVRSRV_ERROR RGXSetupFwSysData(PVRSRV_DEVICE_NODE *psDeviceNode, psFwSysInitScratch->asSigBufCtl[RGXFWIF_DM_GEOM].sBuffer.ui32Addr = 0x0; psFwSysInitScratch->asSigBufCtl[RGXFWIF_DM_3D].sBuffer.ui32Addr = 0x0; } +#endif /* defined(PDUMP) */ eError = RGXFWSetupAlignChecks(psDeviceNode, &psFwSysInitScratch->sAlignChecks); @@ -2415,30 +2467,35 @@ static PVRSRV_ERROR RGXSetupFwSysData(PVRSRV_DEVICE_NODE *psDeviceNode, psFwSysInitScratch->ui32FilterFlags = ui32FilterFlags; + /* Fill the remaining bits of fw the init data */ + psFwSysInitScratch->sPDSExecBase.uiAddr = RGX_PDSCODEDATA_HEAP_BASE; + psFwSysInitScratch->sUSCExecBase.uiAddr = RGX_USCCODE_HEAP_BASE; + psFwSysInitScratch->sFBCDCStateTableBase.uiAddr = RGX_FBCDC_HEAP_BASE; + psFwSysInitScratch->sFBCDCLargeStateTableBase.uiAddr = RGX_FBCDC_LARGE_HEAP_BASE; + psFwSysInitScratch->sTextureHeapBase.uiAddr = RGX_TEXTURE_STATE_HEAP_BASE; + +#if defined(FIX_HW_BRN_65273_BIT_MASK) if (RGX_IS_BRN_SUPPORTED(psDevInfo, 65273)) { /* Fill the remaining bits of fw the init data */ psFwSysInitScratch->sPDSExecBase.uiAddr = RGX_PDSCODEDATA_BRN_65273_HEAP_BASE; psFwSysInitScratch->sUSCExecBase.uiAddr = RGX_USCCODE_BRN_65273_HEAP_BASE; } - else - { - /* Fill the remaining bits of fw the init data */ - psFwSysInitScratch->sPDSExecBase.uiAddr = RGX_PDSCODEDATA_HEAP_BASE; - psFwSysInitScratch->sUSCExecBase.uiAddr = RGX_USCCODE_HEAP_BASE; - } +#endif +#if defined(RGX_FEATURE_S7_TOP_INFRASTRUCTURE_BIT_MASK) if (RGX_IS_FEATURE_SUPPORTED(psDevInfo, S7_TOP_INFRASTRUCTURE)) { psFwSysInitScratch->ui32JonesDisableMask = ui32JonesDisableMask; } - +#endif +#if defined(RGX_FEATURE_SLC_VIVT_BIT_MASK) if (RGX_IS_FEATURE_SUPPORTED(psDevInfo, SLC_VIVT)) { eError = _AllocateSLC3Fence(psDevInfo, psFwSysInitScratch); PVR_LOG_GOTO_IF_ERROR(eError, "SLC3Fence memory allocation", fail); } - +#endif #if defined(SUPPORT_PDVFS) /* Core clock rate */ eError = RGXSetupFwAllocation(psDevInfo, @@ -2703,11 +2760,13 @@ static PVRSRV_ERROR RGXSetupFwSysData(PVRSRV_DEVICE_NODE *psDeviceNode, } #endif /* SUPPORT_SECURITY_VALIDATION */ +#if defined(RGX_FEATURE_TFBC_LOSSY_37_PERCENT_BIT_MASK) if (RGX_IS_FEATURE_SUPPORTED(psDevInfo, TFBC_LOSSY_37_PERCENT) || RGX_IS_FEATURE_SUPPORTED(psDevInfo, TFBC_DELTA_CORRELATION)) { psFwSysInitScratch->ui32TFBCCompressionControl = (ui32ConfigFlagsExt & RGXFWIF_INICFG_EXT_TFBC_CONTROL_MASK) >> RGXFWIF_INICFG_EXT_TFBC_CONTROL_SHIFT; } +#endif /* Initialize FW started flag */ psFwSysInitScratch->bFirmwareStarted = IMG_FALSE; @@ -2731,14 +2790,21 @@ static PVRSRV_ERROR RGXSetupFwSysData(PVRSRV_DEVICE_NODE *psDeviceNode, psRuntimeCfg->ui32WdgPeriodUs = RGXFW_SAFETY_WATCHDOG_PERIOD_IN_US; psRuntimeCfg->ui32HCSDeadlineMS = RGX_HCS_DEFAULT_DEADLINE_MS; - for (ui32OSIndex = 0; ui32OSIndex < RGX_NUM_OS_SUPPORTED; ui32OSIndex++) + if (PVRSRV_VZ_MODE_IS(NATIVE)) { - const IMG_INT32 ai32DefaultOsPriority[RGXFW_MAX_NUM_OS] = - {RGX_OSID_0_DEFAULT_PRIORITY, RGX_OSID_1_DEFAULT_PRIORITY, RGX_OSID_2_DEFAULT_PRIORITY, RGX_OSID_3_DEFAULT_PRIORITY, - RGX_OSID_4_DEFAULT_PRIORITY, RGX_OSID_5_DEFAULT_PRIORITY, RGX_OSID_6_DEFAULT_PRIORITY, RGX_OSID_7_DEFAULT_PRIORITY}; + psRuntimeCfg->aui32OSidPriority[RGXFW_HOST_OS] = 0; + } + else + { + for (ui32OSIndex = 0; ui32OSIndex < RGX_NUM_OS_SUPPORTED; ui32OSIndex++) + { + const IMG_INT32 ai32DefaultOsPriority[RGXFW_MAX_NUM_OS] = + {RGX_OSID_0_DEFAULT_PRIORITY, RGX_OSID_1_DEFAULT_PRIORITY, RGX_OSID_2_DEFAULT_PRIORITY, RGX_OSID_3_DEFAULT_PRIORITY, + RGX_OSID_4_DEFAULT_PRIORITY, RGX_OSID_5_DEFAULT_PRIORITY, RGX_OSID_6_DEFAULT_PRIORITY, RGX_OSID_7_DEFAULT_PRIORITY}; - /* Set up initial priorities between different OSes */ - psRuntimeCfg->aui32OSidPriority[ui32OSIndex] = (IMG_UINT32)ai32DefaultOsPriority[ui32OSIndex]; + /* Set up initial priorities between different OSes */ + psRuntimeCfg->aui32OSidPriority[ui32OSIndex] = (IMG_UINT32)ai32DefaultOsPriority[ui32OSIndex]; + } } #if defined(PVR_ENABLE_PHR) && defined(PDUMP) @@ -2751,22 +2817,22 @@ static PVRSRV_ERROR RGXSetupFwSysData(PVRSRV_DEVICE_NODE *psDeviceNode, psRuntimeCfg->ui32DefaultDustsNumInit = psDevInfo->sDevFeatureCfg.ui32MAXDustCount; /* flush write buffers for psDevInfo->psRGXFWIfRuntimeCfg */ - OSWriteMemoryBarrier(); + OSWriteMemoryBarrier(psDevInfo->psRGXFWIfRuntimeCfg); /* Setup FW coremem data */ if (psDevInfo->psRGXFWIfCorememDataStoreMemDesc) { - IMG_BOOL bMetaDMA = RGX_IS_FEATURE_SUPPORTED(psDevInfo, META_DMA); - psFwSysInitScratch->sCorememDataStore.pbyFWAddr = psDevInfo->sFWCorememDataStoreFWAddr; - if (bMetaDMA) +#if defined(RGX_FEATURE_META_DMA_CHANNEL_COUNT_MAX_VALUE_IDX) + if (RGX_IS_FEATURE_SUPPORTED(psDevInfo, META_DMA)) { RGXSetMetaDMAAddress(&psFwSysInitScratch->sCorememDataStore, psDevInfo->psRGXFWIfCorememDataStoreMemDesc, &psFwSysInitScratch->sCorememDataStore.pbyFWAddr, 0); } +#endif } psDevInfo->psRGXFWIfFwSysData->ui32ConfigFlags = ui32ConfigFlags & RGXFWIF_INICFG_ALL; @@ -2831,6 +2897,12 @@ static PVRSRV_ERROR RGXSetupFwOsData(PVRSRV_DEVICE_NODE *psDeviceNode, OSCachedMemSet(&sFwOsInitScratch, 0, sizeof(RGXFWIF_OSINIT)); + if (PVRSRV_VZ_MODE_IS(GUEST)) + { + eError = RGXSetupFwGuardPage(psDevInfo); + PVR_LOG_GOTO_IF_ERROR(eError, "Setting up firmware heap guard pages", fail); + } + /* Memory tracking the connection state should be non-volatile and * is not cleared on allocation to prevent loss of pre-reset information */ eError = RGXSetupFwAllocation(psDevInfo, @@ -2935,7 +3007,7 @@ static PVRSRV_ERROR RGXSetupFwOsData(PVRSRV_DEVICE_NODE *psDeviceNode, PVR_LOG_GOTO_IF_ERROR(eError, "Get Sync Prim FW address", fail); /* flush write buffers for psRGXFWIfFwOsData */ - OSWriteMemoryBarrier(); + OSWriteMemoryBarrier(psDevInfo->psRGXFWIfFwOsData); sFwOsInitScratch.ui32HWRDebugDumpLimit = ui32HWRDebugDumpLimit; @@ -2975,7 +3047,7 @@ fail: ******************************************************************************* @Function RGXSetupFirmware - @Description Setups all firmware related data + @Description Sets up all firmware related data @Input psDevInfo @@ -3063,12 +3135,14 @@ static void RGXFreeFwSysData(PVRSRV_RGXDEV_INFO *psDevInfo) } #if defined(PDUMP) +#if defined(RGX_FEATURE_TDM_PDS_CHECKSUM_BIT_MASK) if (RGX_IS_FEATURE_SUPPORTED(psDevInfo, TDM_PDS_CHECKSUM) && psDevInfo->psRGXFWSigTDM2DChecksMemDesc) { DevmemFwUnmapAndFree(psDevInfo, psDevInfo->psRGXFWSigTDM2DChecksMemDesc); psDevInfo->psRGXFWSigTDM2DChecksMemDesc = NULL; } +#endif if (psDevInfo->psRGXFWSigTAChecksMemDesc) { @@ -3188,11 +3262,12 @@ static void RGXFreeFwSysData(PVRSRV_RGXDEV_INFO *psDevInfo) } #endif +#if defined(RGX_FEATURE_SLC_VIVT_BIT_MASK) if (RGX_IS_FEATURE_SUPPORTED(psDevInfo, SLC_VIVT)) { _FreeSLC3Fence(psDevInfo); } - +#endif #if defined(SUPPORT_PDVFS) if (psDevInfo->psRGXFWIFCoreClkRateMemDesc) { @@ -3314,6 +3389,11 @@ static void RGXFreeFwOsData(PVRSRV_RGXDEV_INFO *psDevInfo) psDevInfo->hTimerQueryLock = NULL; } #endif + + if (psDevInfo->psRGXFWHeapGuardPageReserveMemDesc) + { + DevmemFwUnmapAndFree(psDevInfo, psDevInfo->psRGXFWHeapGuardPageReserveMemDesc); + } } /*! @@ -3552,6 +3632,10 @@ static IMG_UINT32 RGXGetCmdMemCopySize(RGXFWIF_KCCB_CMD_TYPE eCmdType) { return offsetof(RGXFWIF_KCCB_CMD, uCmdData) + sizeof(RGXFWIF_HWPERF_CONFIG_ENABLE_BLKS); } + case RGXFWIF_KCCB_CMD_HWPERF_CONFIG_BLKS: + { + return offsetof(RGXFWIF_KCCB_CMD, uCmdData) + sizeof(RGXFWIF_HWPERF_CONFIG_DA_BLKS); + } case RGXFWIF_KCCB_CMD_HWPERF_CTRL_BLKS: { return offsetof(RGXFWIF_KCCB_CMD, uCmdData) + sizeof(RGXFWIF_HWPERF_CTRL_BLKS); @@ -3575,6 +3659,10 @@ static IMG_UINT32 RGXGetCmdMemCopySize(RGXFWIF_KCCB_CMD_TYPE eCmdType) { return offsetof(RGXFWIF_KCCB_CMD, uCmdData) + sizeof(RGXFWIF_RGXREG_DATA); } + case RGXFWIF_KCCB_CMD_GPUMAP: + { + return offsetof(RGXFWIF_KCCB_CMD, uCmdData) + sizeof(RGXFWIF_GPUMAP_DATA); + } #endif default: { @@ -3634,7 +3722,7 @@ static PVRSRV_ERROR RGXSendCommandRaw(PVRSRV_RGXDEV_INFO *psDevInfo, #if !defined(PDUMP) PVR_UNREFERENCED_PARAMETER(uiPDumpFlags); #else - IMG_BOOL bContCaptureOn = PDumpCheckFlagsWrite(psDeviceNode, PDUMP_FLAGS_CONTINUOUS); /* client connected or in pdump init phase */ + IMG_BOOL bContCaptureOn = PDumpCheckFlagsWrite(psDeviceNode, PDUMP_FLAGS_CONTINUOUS | PDUMP_FLAGS_POWER); /* client connected or in pdump init phase */ IMG_BOOL bPDumpEnabled = PDumpCheckFlagsWrite(psDeviceNode, uiPDumpFlags); /* Are we in capture range or continuous and not in a power transition */ if (bContCaptureOn) @@ -3672,7 +3760,8 @@ static PVRSRV_ERROR RGXSendCommandRaw(PVRSRV_RGXDEV_INFO *psDevInfo, #if defined(SUPPORT_AUTOVZ) if (!((KM_FW_CONNECTION_IS(READY, psDevInfo) && KM_OS_CONNECTION_IS(READY, psDevInfo)) || - (KM_FW_CONNECTION_IS(ACTIVE, psDevInfo) && KM_OS_CONNECTION_IS(ACTIVE, psDevInfo)))) + (KM_FW_CONNECTION_IS(ACTIVE, psDevInfo) && KM_OS_CONNECTION_IS(ACTIVE, psDevInfo))) && + !PVRSRV_VZ_MODE_IS(NATIVE)) { PVR_DPF((PVR_DBG_ERROR, "%s: The firmware-driver connection is invalid:" "driver state = %u / firmware state = %u;" @@ -3706,9 +3795,8 @@ static PVRSRV_ERROR RGXSendCommandRaw(PVRSRV_RGXDEV_INFO *psDevInfo, PVR_LOG_RETURN_IF_FALSE(ui32CmdMemCopySize !=0, "RGXGetCmdMemCopySize failed", PVRSRV_ERROR_INVALID_CCB_COMMAND); /* Copy the command into the CCB */ - OSCachedMemCopy(&pui8KCCB[ui32OldWriteOffset * psKCCBCtl->ui32CmdSize], + OSCachedMemCopyWMB(&pui8KCCB[ui32OldWriteOffset * psKCCBCtl->ui32CmdSize], psKCCBCmd, ui32CmdMemCopySize); - OSWriteMemoryBarrier(); /* If non-NULL pui32CmdKCCBSlot passed-in, return the kCCB slot in which the command was enqueued */ if (pui32CmdKCCBSlot) @@ -3731,14 +3819,10 @@ static PVRSRV_ERROR RGXSendCommandRaw(PVRSRV_RGXDEV_INFO *psDevInfo, __func__, psDevInfo, ui32OldWriteOffset, RGXFWIF_KCCB_RTN_SLOT_NO_RESPONSE, psKCCBCmd->eCmdType)); } - /* ensure kCCB data is written before the offsets */ - OSWriteMemoryBarrier(); - /* Move past the current command */ psKCCBCtl->ui32WriteOffset = ui32NewWriteOffset; - /* Force a read-back to memory to avoid posted writes on certain buses */ - (void) psKCCBCtl->ui32WriteOffset; + OSWriteMemoryBarrier(&psKCCBCtl->ui32WriteOffset); #if defined(PDUMP) if (bContCaptureOn) @@ -4003,9 +4087,8 @@ PVRSRV_ERROR RGXSendCommandAndGetKCCBSlot(PVRSRV_RGXDEV_INFO *psDevInfo, /* Let the caller retry. Otherwise if we deferred the command and returned OK, * the caller can end up looking in a stale CCB slot. */ - PVR_DPF((PVR_DBG_ERROR, "%s: Couldn't flush the deferred queue for a command (Type:%d) " - "that needed the kCCB command slot number! Returning kCCB FULL", - __func__, psKCCBCmd->eCmdType)); + PVR_DPF((PVR_DBG_WARNING, "%s: Couldn't flush the deferred queue for a command (Type:%d) " + "- will be retried", __func__, psKCCBCmd->eCmdType)); } } @@ -4033,11 +4116,11 @@ PVRSRV_ERROR RGXSendCommandWithPowLockAndGetKCCBSlot(PVRSRV_RGXDEV_INFO *psDevIn goto _PVRSRVPowerLock_Exit; } - PDUMPPOWCMDSTART(); + PDUMPPOWCMDSTART(psDeviceNode); eError = PVRSRVSetDevicePowerStateKM(psDeviceNode, PVRSRV_DEV_POWER_STATE_ON, PVRSRV_POWER_FLAGS_NONE); - PDUMPPOWCMDEND(); + PDUMPPOWCMDEND(psDeviceNode); if (eError != PVRSRV_OK) { @@ -4100,7 +4183,6 @@ PVRSRV_ERROR RGXScheduleRgxRegCommand(PVRSRV_RGXDEV_INFO *psDevInfo, eError = RGXScheduleCommandAndGetKCCBSlot(psDevInfo, RGXFWIF_DM_GP, &sRgxRegsCmd, - 0, PDUMP_FLAGS_CONTINUOUS, &ui32kCCBCommandSlot); PVR_LOG_RETURN_IF_ERROR(eError, "RGXScheduleCommandAndGetKCCBSlot"); @@ -4161,12 +4243,12 @@ static void RGX_MISRHandler_ScheduleProcessQueues(void *pvData) } } - PDUMPPOWCMDSTART(); + PDUMPPOWCMDSTART(psDeviceNode); /* wake up the GPU */ eError = PVRSRVSetDevicePowerStateKM(psDeviceNode, PVRSRV_DEV_POWER_STATE_ON, PVRSRV_POWER_FLAGS_NONE); - PDUMPPOWCMDEND(); + PDUMPPOWCMDEND(psDeviceNode); if (eError != PVRSRV_OK) { @@ -4195,7 +4277,6 @@ PVRSRV_ERROR RGXInstallProcessQueuesMISR(IMG_HANDLE *phMISR, PVRSRV_DEVICE_NODE PVRSRV_ERROR RGXScheduleCommandAndGetKCCBSlot(PVRSRV_RGXDEV_INFO *psDevInfo, RGXFWIF_DM eKCCBType, RGXFWIF_KCCB_CMD *psKCCBCmd, - IMG_UINT32 ui32CacheOpFence, IMG_UINT32 ui32PDumpFlags, IMG_UINT32 *pui32CmdKCCBSlot) { @@ -4213,9 +4294,6 @@ PVRSRV_ERROR RGXScheduleCommandAndGetKCCBSlot(PVRSRV_RGXDEV_INFO *psDevInfo, return PVRSRV_ERROR_INVALID_DEVICE; } - eError = CacheOpFence(psDevInfo->psDeviceNode, eKCCBType, ui32CacheOpFence); - if (unlikely(eError != PVRSRV_OK)) goto RGXScheduleCommand_exit; - #if defined(SUPPORT_VALIDATION) /* For validation, force the core to different dust count states with each kick */ if ((eKCCBType == RGXFWIF_DM_GEOM) || (eKCCBType == RGXFWIF_DM_CDM)) @@ -4251,13 +4329,23 @@ PVRSRV_ERROR RGXScheduleCommandAndGetKCCBSlot(PVRSRV_RGXDEV_INFO *psDevInfo, } else if (psDevInfo->ui32ECCRAMErrInjModule == RGXKM_ECC_ERR_INJ_TPU) { +#if defined(RGX_FEATURE_MAX_TPU_PER_SPU) + PVR_LOG(("ECC RAM Error Inject Swift TPU")); + ui64ECCRegVal = RGX_CR_ECC_RAM_ERR_INJ_SWIFT_EN; +#else PVR_LOG(("ECC RAM Error Inject TPU MCU L0")); ui64ECCRegVal = RGX_CR_ECC_RAM_ERR_INJ_TPU_MCU_L0_EN; +#endif } else if (psDevInfo->ui32ECCRAMErrInjModule == RGXKM_ECC_ERR_INJ_RASCAL) { +#if defined(RGX_CR_ECC_RAM_ERR_INJ_RASCAL_EN) PVR_LOG(("ECC RAM Error Inject RASCAL")); ui64ECCRegVal = RGX_CR_ECC_RAM_ERR_INJ_RASCAL_EN; +#else + PVR_LOG(("ECC RAM Error Inject USC")); + ui64ECCRegVal = RGX_CR_ECC_RAM_ERR_INJ_USC_EN; +#endif } else if (psDevInfo->ui32ECCRAMErrInjModule == RGXKM_ECC_ERR_INJ_MARS) { @@ -4268,11 +4356,11 @@ PVRSRV_ERROR RGXScheduleCommandAndGetKCCBSlot(PVRSRV_RGXDEV_INFO *psDevInfo, { } - OSWriteMemoryBarrier(); + OSWriteMemoryBarrier(NULL); OSWriteHWReg64(psDevInfo->pvRegsBaseKM, RGX_CR_ECC_RAM_ERR_INJ, ui64ECCRegVal); PDUMPCOMMENT(psDevInfo->psDeviceNode, "Write reg ECC_RAM_ERR_INJ"); PDUMPREG64(psDevInfo->psDeviceNode, RGX_PDUMPREG_NAME, RGX_CR_ECC_RAM_ERR_INJ, ui64ECCRegVal, PDUMP_FLAGS_CONTINUOUS); - OSWriteMemoryBarrier(); + OSWriteMemoryBarrier(NULL); } } #endif @@ -4303,11 +4391,11 @@ PVRSRV_ERROR RGXScheduleCommandAndGetKCCBSlot(PVRSRV_RGXDEV_INFO *psDevInfo, } /* Ensure device is powered up before sending any commands */ - PDUMPPOWCMDSTART(); + PDUMPPOWCMDSTART(psDevInfo->psDeviceNode); eError = PVRSRVSetDevicePowerStateKM(psDevInfo->psDeviceNode, PVRSRV_DEV_POWER_STATE_ON, PVRSRV_POWER_FLAGS_NONE); - PDUMPPOWCMDEND(); + PDUMPPOWCMDEND(psDevInfo->psDeviceNode); if (unlikely(eError != PVRSRV_OK)) { PVR_DPF((PVR_DBG_WARNING, "%s: failed to transition RGX to ON (%s)", @@ -4337,9 +4425,10 @@ void RGXCheckFirmwareCCB(PVRSRV_RGXDEV_INFO *psDevInfo) IMG_UINT8 *psFWCCB = psDevInfo->psFirmwareCCB; #if defined(RGX_NUM_OS_SUPPORTED) && (RGX_NUM_OS_SUPPORTED > 1) - PVR_LOG_RETURN_VOID_IF_FALSE((KM_FW_CONNECTION_IS(ACTIVE, psDevInfo) && + PVR_LOG_RETURN_VOID_IF_FALSE(PVRSRV_VZ_MODE_IS(NATIVE) || + (KM_FW_CONNECTION_IS(ACTIVE, psDevInfo) && KM_OS_CONNECTION_IS(ACTIVE, psDevInfo)), - "FW-KM connection is down"); + "FW-KM connection is down"); #endif while (psFWCCBCtl->ui32ReadOffset != psFWCCBCtl->ui32WriteOffset) @@ -4702,6 +4791,28 @@ void RGXCheckFirmwareCCB(PVRSRV_RGXDEV_INFO *psDevInfo) complete(&psDevInfo->sFwRegs.sRegComp); break; } +#if defined(SUPPORT_SOC_TIMER) + case RGXFWIF_FWCCB_CMD_SAMPLE_TIMERS: + { + if (psDevInfo->psRGXFWIfFwSysData->ui32ConfigFlags & RGXFWIF_INICFG_VALIDATE_SOCUSC_TIMER) + { + PVRSRV_ERROR eSOCtimerErr = RGXValidateSOCUSCTimer(psDevInfo, + PDUMP_NONE, + psFwCCBCmd->uCmdData.sCmdTimers.ui64timerGray, + psFwCCBCmd->uCmdData.sCmdTimers.ui64timerBinary, + psFwCCBCmd->uCmdData.sCmdTimers.aui64uscTimers); + if (PVRSRV_OK == eSOCtimerErr) + { + PVR_DPF((PVR_DBG_WARNING, "SoC or USC Timers have increased over time")); + } + else + { + PVR_DPF((PVR_DBG_WARNING, "SoC or USC Timers have NOT increased over time")); + } + } + break; + } +#endif #endif default: { @@ -4882,7 +4993,7 @@ PVRSRV_ERROR RGXStateFlagCtrl(PVRSRV_RGXDEV_INFO *psDevInfo, *pui32ConfigState = psSysData->ui32ConfigFlags; } - OSMemoryBarrier(); + OSMemoryBarrier(&psSysData->ui32ConfigFlags); eError = PVRSRVPowerLock(psDeviceNode); PVR_LOG_RETURN_IF_ERROR(eError, "PVRSRVPowerLock"); @@ -4942,10 +5053,19 @@ PVRSRV_ERROR RGXScheduleCleanupCommand(PVRSRV_RGXDEV_INFO *psDevInfo, eError = RGXScheduleCommandAndGetKCCBSlot(psDevInfo, eDM, psKCCBCmd, - 0, ui32PDumpFlags, &ui32kCCBCommandSlot); - PVR_LOG_GOTO_IF_ERROR(eError, "RGXScheduleCommandAndGetKCCBSlot", fail_command); + if (eError != PVRSRV_OK) + { + /* If caller may retry, fail with no error message */ + if ((eError != PVRSRV_ERROR_RETRY) && + (eError != PVRSRV_ERROR_KERNEL_CCB_FULL)) + { + PVR_DPF((PVR_DBG_ERROR ,"RGXScheduleCommandAndGetKCCBSlot() failed (%s) in %s()", + PVRSRVGETERRORSTRING(eError), __func__)); + } + goto fail_command; + } /* Wait for command kCCB slot to be updated by FW */ PDUMPCOMMENTWITHFLAGS(psDevInfo->psDeviceNode, ui32PDumpFlags, @@ -5097,11 +5217,16 @@ PVRSRV_ERROR RGXFWRequestHWRTDataCleanUp(PVRSRV_DEVICE_NODE *psDeviceNode, RGXFWIF_CLEANUP_HWRTDATA, PDUMP_FLAGS_NONE); - if ((eError != PVRSRV_OK) && (eError != PVRSRV_ERROR_RETRY)) + if (eError != PVRSRV_OK) { - PVR_DPF((PVR_DBG_ERROR, - "%s: Failed to schedule a HWRTData cleanup with error (%u)", - __func__, eError)); + /* If caller may retry, fail with no error message */ + if ((eError != PVRSRV_ERROR_RETRY) && + (eError != PVRSRV_ERROR_KERNEL_CCB_FULL)) + { + PVR_DPF((PVR_DBG_ERROR, + "%s: Failed to schedule a HWRTData cleanup with error (%u)", + __func__, eError)); + } } return eError; @@ -5128,11 +5253,16 @@ PVRSRV_ERROR RGXFWRequestFreeListCleanUp(PVRSRV_RGXDEV_INFO *psDevInfo, RGXFWIF_CLEANUP_FREELIST, PDUMP_FLAGS_NONE); - if ((eError != PVRSRV_OK) && (eError != PVRSRV_ERROR_RETRY)) + if (eError != PVRSRV_OK) { - PVR_DPF((PVR_DBG_ERROR, - "%s: Failed to schedule a memory context cleanup with error (%u)", - __func__, eError)); + /* If caller may retry, fail with no error message */ + if ((eError != PVRSRV_ERROR_RETRY) && + (eError != PVRSRV_ERROR_KERNEL_CCB_FULL)) + { + PVR_DPF((PVR_DBG_ERROR, + "%s: Failed to schedule a memory context cleanup with error (%u)", + __func__, eError)); + } } return eError; @@ -5175,7 +5305,16 @@ PVRSRV_ERROR RGXFWSetHCSDeadline(PVRSRV_RGXDEV_INFO *psDevInfo, PVRSRV_VZ_RET_IF_MODE(GUEST, PVRSRV_ERROR_NOT_SUPPORTED); psDevInfo->psRGXFWIfRuntimeCfg->ui32HCSDeadlineMS = ui32HCSDeadlineMs; - OSWriteMemoryBarrier(); + OSWriteMemoryBarrier(&psDevInfo->psRGXFWIfRuntimeCfg->ui32HCSDeadlineMS); + +#if defined(PDUMP) + PDUMPCOMMENT(psDevInfo->psDeviceNode, + "Updating the Hard Context Switching deadline inside RGXFWIfRuntimeCfg"); + DevmemPDumpLoadMemValue32(psDevInfo->psRGXFWIfRuntimeCfgMemDesc, + offsetof(RGXFWIF_RUNTIME_CFG, ui32HCSDeadlineMS), + ui32HCSDeadlineMs, + PDUMP_FLAGS_CONTINUOUS); +#endif return PVRSRV_OK; } @@ -5189,7 +5328,6 @@ PVRSRV_ERROR RGXFWHealthCheckCmd(PVRSRV_RGXDEV_INFO *psDevInfo) return RGXScheduleCommand(psDevInfo, RGXFWIF_DM_GP, &sCmpKCCBCmd, - 0, PDUMP_FLAGS_CONTINUOUS); } @@ -5266,7 +5404,6 @@ PVRSRV_ERROR RGXFWSetFwOsState(PVRSRV_RGXDEV_INFO *psDevInfo, IMG_UINT32 ui32OSi eError = RGXScheduleCommand(psDevInfo, RGXFWIF_DM_GP, &sOSOnlineStateCmd, - 0, PDUMP_FLAGS_CONTINUOUS); if (eError != PVRSRV_ERROR_RETRY) break; @@ -5287,7 +5424,6 @@ PVRSRV_ERROR RGXFWSetFwOsState(PVRSRV_RGXDEV_INFO *psDevInfo, IMG_UINT32 ui32OSi eError = RGXScheduleCommandAndGetKCCBSlot(psDevInfo, RGXFWIF_DM_GP, &sOSOnlineStateCmd, - 0, PDUMP_FLAGS_CONTINUOUS, &ui32kCCBCommandSlot); if (unlikely(eError == PVRSRV_ERROR_RETRY)) continue; @@ -5298,7 +5434,7 @@ PVRSRV_ERROR RGXFWSetFwOsState(PVRSRV_RGXDEV_INFO *psDevInfo, IMG_UINT32 ui32OSi PVR_LOG_GOTO_IF_ERROR(eError, "RGXWaitForKCCBSlotUpdate", return_); /* read the OS state */ - OSMemoryBarrier(); + OSMemoryBarrier(NULL); /* check if FW finished offloading the OSID and is stopped */ if (psFwRunFlags->bfOsState == RGXFW_CONNECTION_FW_OFFLINE) { @@ -5334,13 +5470,22 @@ PVRSRV_ERROR RGXFWChangeOSidPriority(PVRSRV_RGXDEV_INFO *psDevInfo, sOSidPriorityCmd.eCmdType = RGXFWIF_KCCB_CMD_OSID_PRIORITY_CHANGE; psDevInfo->psRGXFWIfRuntimeCfg->aui32OSidPriority[ui32OSid] = ui32Priority; + OSWriteMemoryBarrier(&psDevInfo->psRGXFWIfRuntimeCfg->aui32OSidPriority[ui32OSid]); + +#if defined(PDUMP) + PDUMPCOMMENT(psDevInfo->psDeviceNode, + "Updating the priority of OSID%u inside RGXFWIfRuntimeCfg", ui32OSid); + DevmemPDumpLoadMemValue32(psDevInfo->psRGXFWIfRuntimeCfgMemDesc, + offsetof(RGXFWIF_RUNTIME_CFG, aui32OSidPriority) + (ui32OSid * sizeof(ui32Priority)), + ui32Priority , + PDUMP_FLAGS_CONTINUOUS); +#endif LOOP_UNTIL_TIMEOUT(MAX_HW_TIME_US) { eError = RGXScheduleCommand(psDevInfo, RGXFWIF_DM_GP, &sOSidPriorityCmd, - 0, PDUMP_FLAGS_CONTINUOUS); if (eError != PVRSRV_ERROR_RETRY) { @@ -5364,9 +5509,10 @@ PVRSRV_ERROR ContextSetPriority(RGX_SERVER_COMMON_CONTEXT *psContext, RGXFWIF_CCB_CMD_HEADER *psCmdHeader; RGXFWIF_CMD_PRIORITY *psCmd; PVRSRV_ERROR eError; + IMG_INT32 i32Priority = (IMG_INT32)ui32Priority; RGX_CLIENT_CCB *psClientCCB = FWCommonContextGetClientCCB(psContext); - eError = _CheckPriority(psDevInfo, ui32Priority, psContext->eRequestor); + eError = _CheckPriority(psDevInfo, i32Priority, psContext->eRequestor); PVR_LOG_GOTO_IF_ERROR(eError, "_CheckPriority", fail_checkpriority); /* @@ -5396,7 +5542,7 @@ PVRSRV_ERROR ContextSetPriority(RGX_SERVER_COMMON_CONTEXT *psContext, pui8CmdPtr += sizeof(*psCmdHeader); psCmd = (RGXFWIF_CMD_PRIORITY *) pui8CmdPtr; - psCmd->ui32Priority = ui32Priority; + psCmd->i32Priority = i32Priority; pui8CmdPtr += sizeof(*psCmd); /* @@ -5432,7 +5578,6 @@ PVRSRV_ERROR ContextSetPriority(RGX_SERVER_COMMON_CONTEXT *psContext, eError = RGXScheduleCommand(psDevInfo, eDM, &sPriorityCmd, - 0, PDUMP_FLAGS_CONTINUOUS); if (eError != PVRSRV_ERROR_RETRY) { @@ -5450,7 +5595,7 @@ PVRSRV_ERROR ContextSetPriority(RGX_SERVER_COMMON_CONTEXT *psContext, goto fail_cmdacquire; } - psContext->ui32Priority = ui32Priority; + psContext->i32Priority = i32Priority; return PVRSRV_OK; @@ -5471,14 +5616,22 @@ PVRSRV_ERROR RGXFWConfigPHR(PVRSRV_RGXDEV_INFO *psDevInfo, sCfgPHRCmd.eCmdType = RGXFWIF_KCCB_CMD_PHR_CFG; psDevInfo->psRGXFWIfRuntimeCfg->ui32PHRMode = ui32PHRMode; - OSWriteMemoryBarrier(); + OSWriteMemoryBarrier(&psDevInfo->psRGXFWIfRuntimeCfg->ui32PHRMode); + +#if defined(PDUMP) + PDUMPCOMMENT(psDevInfo->psDeviceNode, + "Updating the Periodic Hardware Reset Mode inside RGXFWIfRuntimeCfg"); + DevmemPDumpLoadMemValue32(psDevInfo->psRGXFWIfRuntimeCfgMemDesc, + offsetof(RGXFWIF_RUNTIME_CFG, ui32PHRMode), + ui32PHRMode, + PDUMP_FLAGS_CONTINUOUS); +#endif LOOP_UNTIL_TIMEOUT(MAX_HW_TIME_US) { eError = RGXScheduleCommand(psDevInfo, RGXFWIF_DM_GP, &sCfgPHRCmd, - 0, PDUMP_FLAGS_CONTINUOUS); if (eError != PVRSRV_ERROR_RETRY) { @@ -5500,14 +5653,22 @@ PVRSRV_ERROR RGXFWConfigWdg(PVRSRV_RGXDEV_INFO *psDevInfo, sCfgWdgCmd.eCmdType = RGXFWIF_KCCB_CMD_WDG_CFG; psDevInfo->psRGXFWIfRuntimeCfg->ui32WdgPeriodUs = ui32WdgPeriodUs; - OSWriteMemoryBarrier(); + OSWriteMemoryBarrier(&psDevInfo->psRGXFWIfRuntimeCfg->ui32WdgPeriodUs); + +#if defined(PDUMP) + PDUMPCOMMENT(psDevInfo->psDeviceNode, + "Updating the firmware watchdog period inside RGXFWIfRuntimeCfg"); + DevmemPDumpLoadMemValue32(psDevInfo->psRGXFWIfRuntimeCfgMemDesc, + offsetof(RGXFWIF_RUNTIME_CFG, ui32WdgPeriodUs), + ui32WdgPeriodUs, + PDUMP_FLAGS_CONTINUOUS); +#endif LOOP_UNTIL_TIMEOUT(MAX_HW_TIME_US) { eError = RGXScheduleCommand(psDevInfo, RGXFWIF_DM_GP, &sCfgWdgCmd, - 0, PDUMP_FLAGS_CONTINUOUS); if (eError != PVRSRV_ERROR_RETRY) { @@ -5519,72 +5680,7 @@ PVRSRV_ERROR RGXFWConfigWdg(PVRSRV_RGXDEV_INFO *psDevInfo, return eError; } -/* - RGXReadMETAAddr -*/ -PVRSRV_ERROR RGXReadMETAAddr(PVRSRV_RGXDEV_INFO *psDevInfo, IMG_UINT32 ui32METAAddr, IMG_UINT32 *pui32Value) -{ - IMG_UINT8 __iomem *pui8RegBase = psDevInfo->pvRegsBaseKM; - IMG_UINT32 ui32Value; - /* Wait for Slave Port to be Ready */ - if (PVRSRVPollForValueKM(psDevInfo->psDeviceNode, - (IMG_UINT32 __iomem *) (pui8RegBase + RGX_CR_META_SP_MSLVCTRL1), - RGX_CR_META_SP_MSLVCTRL1_READY_EN|RGX_CR_META_SP_MSLVCTRL1_GBLPORT_IDLE_EN, - RGX_CR_META_SP_MSLVCTRL1_READY_EN|RGX_CR_META_SP_MSLVCTRL1_GBLPORT_IDLE_EN, - POLL_FLAG_LOG_ERROR) != PVRSRV_OK) - { - return PVRSRV_ERROR_TIMEOUT; - } - - /* Issue the Read */ - OSWriteHWReg32( - psDevInfo->pvRegsBaseKM, - RGX_CR_META_SP_MSLVCTRL0, - ui32METAAddr | RGX_CR_META_SP_MSLVCTRL0_RD_EN); - (void) OSReadHWReg32(psDevInfo->pvRegsBaseKM, RGX_CR_META_SP_MSLVCTRL0); - - /* Wait for Slave Port to be Ready: read complete */ - if (PVRSRVPollForValueKM(psDevInfo->psDeviceNode, - (IMG_UINT32 __iomem *) (pui8RegBase + RGX_CR_META_SP_MSLVCTRL1), - RGX_CR_META_SP_MSLVCTRL1_READY_EN|RGX_CR_META_SP_MSLVCTRL1_GBLPORT_IDLE_EN, - RGX_CR_META_SP_MSLVCTRL1_READY_EN|RGX_CR_META_SP_MSLVCTRL1_GBLPORT_IDLE_EN, - POLL_FLAG_LOG_ERROR) != PVRSRV_OK) - { - return PVRSRV_ERROR_TIMEOUT; - } - - /* Read the value */ - ui32Value = OSReadHWReg32(psDevInfo->pvRegsBaseKM, RGX_CR_META_SP_MSLVDATAX); - - *pui32Value = ui32Value; - - return PVRSRV_OK; -} - -/* - RGXWriteMETAAddr -*/ -PVRSRV_ERROR RGXWriteMETAAddr(PVRSRV_RGXDEV_INFO *psDevInfo, IMG_UINT32 ui32METAAddr, IMG_UINT32 ui32Value) -{ - IMG_UINT8 __iomem *pui8RegBase = psDevInfo->pvRegsBaseKM; - - /* Wait for Slave Port to be Ready */ - if (PVRSRVPollForValueKM(psDevInfo->psDeviceNode, - (IMG_UINT32 __iomem *)(pui8RegBase + RGX_CR_META_SP_MSLVCTRL1), - RGX_CR_META_SP_MSLVCTRL1_READY_EN|RGX_CR_META_SP_MSLVCTRL1_GBLPORT_IDLE_EN, - RGX_CR_META_SP_MSLVCTRL1_READY_EN|RGX_CR_META_SP_MSLVCTRL1_GBLPORT_IDLE_EN, - POLL_FLAG_LOG_ERROR) != PVRSRV_OK) - { - return PVRSRV_ERROR_TIMEOUT; - } - - /* Issue the Write */ - OSWriteHWReg32(psDevInfo->pvRegsBaseKM, RGX_CR_META_SP_MSLVCTRL0, ui32METAAddr); - OSWriteHWReg32(psDevInfo->pvRegsBaseKM, RGX_CR_META_SP_MSLVDATAT, ui32Value); - - return PVRSRV_OK; -} void RGXCheckForStalledClientContexts(PVRSRV_RGXDEV_INFO *psDevInfo, IMG_BOOL bIgnorePrevious) { @@ -6638,11 +6734,6 @@ static RGXRISCVFW_ABSTRACT_CMD_ERR RGXRiscvCheckAbstractCmdError(PVRSRV_RGXDEV_I #else void __iomem *pvRegsBaseKM = psDevInfo->pvRegsBaseKM; - /* The following line is necessary to avoid a compiler error, despite the - * variable actually being used below. - */ - PVR_UNREFERENCED_PARAMETER(pvRegsBaseKM); - /* Check error status */ eCmdErr = (OSReadHWReg32(pvRegsBaseKM, RGX_CR_FWCORE_DMI_ABSTRACTCS) & ~RGX_CR_FWCORE_DMI_ABSTRACTCS_CMDERR_CLRMSK) @@ -6863,7 +6954,7 @@ PVRSRV_ERROR RGXRiscvWriteReg(PVRSRV_RGXDEV_INFO *psDevInfo, @Return RGXRISCVFW_SYSBUS_ERR ******************************************************************************/ -static RGXRISCVFW_SYSBUS_ERR RGXRiscvCheckSysBusError(PVRSRV_RGXDEV_INFO *psDevInfo) +static __maybe_unused RGXRISCVFW_SYSBUS_ERR RGXRiscvCheckSysBusError(PVRSRV_RGXDEV_INFO *psDevInfo) { RGXRISCVFW_SYSBUS_ERR eSBError; @@ -6880,11 +6971,6 @@ static RGXRISCVFW_SYSBUS_ERR RGXRiscvCheckSysBusError(PVRSRV_RGXDEV_INFO *psDevI #else void __iomem *pvRegsBaseKM = psDevInfo->pvRegsBaseKM; - /* The following line is necessary to avoid a compiler error, despite the - * variable actually being used below. - */ - PVR_UNREFERENCED_PARAMETER(pvRegsBaseKM); - eSBError = (OSReadHWReg32(pvRegsBaseKM, RGX_CR_FWCORE_DMI_SBCS) & ~RGX_CR_FWCORE_DMI_SBCS_SBERROR_CLRMSK) >> RGX_CR_FWCORE_DMI_SBCS_SBERROR_SHIFT; @@ -6902,6 +6988,7 @@ static RGXRISCVFW_SYSBUS_ERR RGXRiscvCheckSysBusError(PVRSRV_RGXDEV_INFO *psDevI return eSBError; } +#if defined(RGX_FEATURE_RISCV_FW_PROCESSOR_BIT_MASK) && !defined(EMULATOR) /*! ******************************************************************************* @Function RGXRiscvReadAbstractMem @@ -6964,6 +7051,7 @@ RGXRiscvReadAbstractMem(PVRSRV_RGXDEV_INFO *psDevInfo, IMG_UINT32 ui32Addr, IMG_ return PVRSRV_OK; #endif } +#endif /* !defined(EMULATOR) */ /*! ******************************************************************************* @@ -7028,6 +7116,7 @@ RGXRiscvPollAbstractMem(PVRSRV_RGXDEV_INFO *psDevInfo, IMG_UINT32 ui32Addr, IMG_ #endif } +#if defined(RGX_FEATURE_RISCV_FW_PROCESSOR_BIT_MASK) && !defined(EMULATOR) /*! ******************************************************************************* @Function RGXRiscvReadSysBusMem @@ -7089,6 +7178,7 @@ RGXRiscvReadSysBusMem(PVRSRV_RGXDEV_INFO *psDevInfo, IMG_UINT32 ui32Addr, IMG_UI return PVRSRV_OK; #endif } +#endif /* !defined(EMULATOR) */ /*! ******************************************************************************* @@ -7154,6 +7244,7 @@ RGXRiscvPollSysBusMem(PVRSRV_RGXDEV_INFO *psDevInfo, IMG_UINT32 ui32Addr, IMG_UI #endif } +#if defined(RGX_FEATURE_RISCV_FW_PROCESSOR_BIT_MASK) && !defined(EMULATOR) /*! ******************************************************************************* @Function RGXRiscvReadMem @@ -7167,7 +7258,7 @@ RGXRiscvPollSysBusMem(PVRSRV_RGXDEV_INFO *psDevInfo, IMG_UINT32 ui32Addr, IMG_UI @Return PVRSRV_ERROR ******************************************************************************/ -PVRSRV_ERROR RGXRiscvReadMem(PVRSRV_RGXDEV_INFO *psDevInfo, +static PVRSRV_ERROR RGXRiscvReadMem(PVRSRV_RGXDEV_INFO *psDevInfo, IMG_UINT32 ui32Addr, IMG_UINT32 *pui32Value) { @@ -7178,6 +7269,7 @@ PVRSRV_ERROR RGXRiscvReadMem(PVRSRV_RGXDEV_INFO *psDevInfo, return RGXRiscvReadSysBusMem(psDevInfo, ui32Addr, pui32Value); } +#endif /* !defined(EMULATOR) */ /*! ******************************************************************************* @@ -7203,6 +7295,7 @@ PVRSRV_ERROR RGXRiscvPollMem(PVRSRV_RGXDEV_INFO *psDevInfo, return RGXRiscvPollSysBusMem(psDevInfo, ui32Addr, ui32Value); } +#if defined(RGX_FEATURE_RISCV_FW_PROCESSOR_BIT_MASK) && !defined(EMULATOR) /*! ******************************************************************************* @Function RGXRiscvWriteAbstractMem @@ -7363,7 +7456,7 @@ RGXRiscvWriteSysBusMem(PVRSRV_RGXDEV_INFO *psDevInfo, IMG_UINT32 ui32Addr, IMG_U @Return PVRSRV_ERROR ******************************************************************************/ -PVRSRV_ERROR RGXRiscvWriteMem(PVRSRV_RGXDEV_INFO *psDevInfo, +static PVRSRV_ERROR RGXRiscvWriteMem(PVRSRV_RGXDEV_INFO *psDevInfo, IMG_UINT32 ui32Addr, IMG_UINT32 ui32Value) { @@ -7374,6 +7467,7 @@ PVRSRV_ERROR RGXRiscvWriteMem(PVRSRV_RGXDEV_INFO *psDevInfo, return RGXRiscvWriteSysBusMem(psDevInfo, ui32Addr, ui32Value); } +#endif /* !defined(EMULATOR) */ /*! ******************************************************************************* @@ -7495,6 +7589,237 @@ dmiop_update: #endif } +#if defined(RGX_FEATURE_META_MAX_VALUE_IDX) +/* + RGXReadMETAAddr +*/ +static PVRSRV_ERROR RGXReadMETAAddr(PVRSRV_RGXDEV_INFO *psDevInfo, IMG_UINT32 ui32METAAddr, IMG_UINT32 *pui32Value) +{ + IMG_UINT8 __iomem *pui8RegBase = psDevInfo->pvRegsBaseKM; + IMG_UINT32 ui32Value; + + /* Wait for Slave Port to be Ready */ + if (PVRSRVPollForValueKM(psDevInfo->psDeviceNode, + (IMG_UINT32 __iomem *) (pui8RegBase + RGX_CR_META_SP_MSLVCTRL1), + RGX_CR_META_SP_MSLVCTRL1_READY_EN|RGX_CR_META_SP_MSLVCTRL1_GBLPORT_IDLE_EN, + RGX_CR_META_SP_MSLVCTRL1_READY_EN|RGX_CR_META_SP_MSLVCTRL1_GBLPORT_IDLE_EN, + POLL_FLAG_LOG_ERROR) != PVRSRV_OK) + { + return PVRSRV_ERROR_TIMEOUT; + } + + /* Issue the Read */ + OSWriteHWReg32( + psDevInfo->pvRegsBaseKM, + RGX_CR_META_SP_MSLVCTRL0, + ui32METAAddr | RGX_CR_META_SP_MSLVCTRL0_RD_EN); + (void) OSReadHWReg32(psDevInfo->pvRegsBaseKM, RGX_CR_META_SP_MSLVCTRL0); + + /* Wait for Slave Port to be Ready: read complete */ + if (PVRSRVPollForValueKM(psDevInfo->psDeviceNode, + (IMG_UINT32 __iomem *) (pui8RegBase + RGX_CR_META_SP_MSLVCTRL1), + RGX_CR_META_SP_MSLVCTRL1_READY_EN|RGX_CR_META_SP_MSLVCTRL1_GBLPORT_IDLE_EN, + RGX_CR_META_SP_MSLVCTRL1_READY_EN|RGX_CR_META_SP_MSLVCTRL1_GBLPORT_IDLE_EN, + POLL_FLAG_LOG_ERROR) != PVRSRV_OK) + { + return PVRSRV_ERROR_TIMEOUT; + } + + /* Read the value */ + ui32Value = OSReadHWReg32(psDevInfo->pvRegsBaseKM, RGX_CR_META_SP_MSLVDATAX); + + *pui32Value = ui32Value; + + return PVRSRV_OK; +} + +/* + RGXWriteMETAAddr +*/ +static PVRSRV_ERROR RGXWriteMETAAddr(PVRSRV_RGXDEV_INFO *psDevInfo, IMG_UINT32 ui32METAAddr, IMG_UINT32 ui32Value) +{ + IMG_UINT8 __iomem *pui8RegBase = psDevInfo->pvRegsBaseKM; + + /* Wait for Slave Port to be Ready */ + if (PVRSRVPollForValueKM(psDevInfo->psDeviceNode, + (IMG_UINT32 __iomem *)(pui8RegBase + RGX_CR_META_SP_MSLVCTRL1), + RGX_CR_META_SP_MSLVCTRL1_READY_EN|RGX_CR_META_SP_MSLVCTRL1_GBLPORT_IDLE_EN, + RGX_CR_META_SP_MSLVCTRL1_READY_EN|RGX_CR_META_SP_MSLVCTRL1_GBLPORT_IDLE_EN, + POLL_FLAG_LOG_ERROR) != PVRSRV_OK) + { + return PVRSRV_ERROR_TIMEOUT; + } + + /* Issue the Write */ + OSWriteHWReg32(psDevInfo->pvRegsBaseKM, RGX_CR_META_SP_MSLVCTRL0, ui32METAAddr); + OSWriteHWReg32(psDevInfo->pvRegsBaseKM, RGX_CR_META_SP_MSLVDATAT, ui32Value); + + return PVRSRV_OK; +} +#endif + +PVRSRV_ERROR RGXReadFWModuleAddr(PVRSRV_RGXDEV_INFO *psDevInfo, IMG_UINT32 ui32FWAddr, IMG_UINT32 *pui32Value) +{ +#if defined(RGX_FEATURE_META_MAX_VALUE_IDX) + if (RGX_IS_FEATURE_VALUE_SUPPORTED(psDevInfo, META)) + { + return RGXReadMETAAddr(psDevInfo, ui32FWAddr, pui32Value); + } +#endif + +#if defined(RGX_FEATURE_RISCV_FW_PROCESSOR_BIT_MASK) && !defined(EMULATOR) + if (RGX_IS_FEATURE_SUPPORTED(psDevInfo, RISCV_FW_PROCESSOR)) + { + return RGXRiscvReadMem(psDevInfo, ui32FWAddr, pui32Value); + } +#endif + + return PVRSRV_ERROR_NOT_SUPPORTED; +} + +PVRSRV_ERROR RGXWriteFWModuleAddr(PVRSRV_RGXDEV_INFO *psDevInfo, IMG_UINT32 ui32FWAddr, IMG_UINT32 ui32Value) +{ +#if defined(RGX_FEATURE_META_MAX_VALUE_IDX) + if (RGX_IS_FEATURE_VALUE_SUPPORTED(psDevInfo, META)) + { + return RGXWriteMETAAddr(psDevInfo, ui32FWAddr, ui32Value); + } +#endif + +#if defined(RGX_FEATURE_RISCV_FW_PROCESSOR_BIT_MASK) && !defined(EMULATOR) + if (RGX_IS_FEATURE_SUPPORTED(psDevInfo, RISCV_FW_PROCESSOR)) + { + return RGXRiscvWriteMem(psDevInfo, ui32FWAddr, ui32Value); + } +#endif + + return PVRSRV_ERROR_NOT_SUPPORTED; +} + +PVRSRV_ERROR RGXGetFwMapping(PVRSRV_RGXDEV_INFO *psDevInfo, + IMG_UINT32 ui32FwVA, + IMG_CPU_PHYADDR *psCpuPA, + IMG_DEV_PHYADDR *psDevPA, + IMG_UINT64 *pui64RawPTE) +{ + PVRSRV_ERROR eError = PVRSRV_OK; + IMG_CPU_PHYADDR sCpuPA = {0U}; + IMG_DEV_PHYADDR sDevPA = {0U}; + IMG_UINT64 ui64RawPTE = 0U; + MMU_FAULT_DATA sFaultData = {0U}; + MMU_CONTEXT *psFwMMUCtx = psDevInfo->psKernelMMUCtx; + IMG_UINT32 ui32FwHeapBase = (IMG_UINT32) (RGX_FIRMWARE_RAW_HEAP_BASE & UINT_MAX); + IMG_UINT32 ui32FwHeapEnd = ui32FwHeapBase + (RGX_NUM_OS_SUPPORTED * RGX_FIRMWARE_RAW_HEAP_SIZE); + IMG_UINT32 ui32OSID = (ui32FwVA - ui32FwHeapBase) / RGX_FIRMWARE_RAW_HEAP_SIZE; + IMG_UINT32 ui32HeapId; + PHYS_HEAP *psPhysHeap; + + /* MIPS uses the same page size as the OS, while others default to 4K pages */ + IMG_UINT32 ui32FwPageSize = RGX_IS_FEATURE_SUPPORTED(psDevInfo, MIPS) ? + OSGetPageSize() : BIT(RGX_MMUCTRL_PAGE_4KB_RANGE_SHIFT); + IMG_UINT32 ui32PageOffset = (ui32FwVA & (ui32FwPageSize - 1)); + + PVR_LOG_GOTO_IF_INVALID_PARAM((ui32OSID < RGX_NUM_OS_SUPPORTED), + eError, ErrorExit); + + PVR_LOG_GOTO_IF_INVALID_PARAM(((psCpuPA != NULL) || + (psDevPA != NULL) || + (pui64RawPTE != NULL)), + eError, ErrorExit); + + PVR_LOG_GOTO_IF_INVALID_PARAM(((ui32FwVA >= ui32FwHeapBase) && + (ui32FwVA < ui32FwHeapEnd)), + eError, ErrorExit); + + ui32HeapId = (ui32OSID == RGXFW_HOST_OS) ? + PVRSRV_PHYS_HEAP_FW_MAIN : (PVRSRV_PHYS_HEAP_FW_PREMAP0 + ui32OSID); + psPhysHeap = psDevInfo->psDeviceNode->apsPhysHeap[ui32HeapId]; + + if (RGX_IS_FEATURE_SUPPORTED(psDevInfo, MIPS)) + { + /* MIPS is equipped with a dedicated MMU */ + RGXMipsCheckFaultAddress(psFwMMUCtx, ui32FwVA, &sFaultData); + } + else + { + IMG_UINT64 ui64FwDataBaseMask; + IMG_DEV_VIRTADDR sDevVAddr; + +#if defined(RGX_FEATURE_META_MAX_VALUE_IDX) + if (RGX_IS_FEATURE_VALUE_SUPPORTED(psDevInfo, META)) + { + ui64FwDataBaseMask = ~(RGXFW_SEGMMU_DATA_META_CACHE_MASK | + RGXFW_SEGMMU_DATA_VIVT_SLC_CACHE_MASK | + RGXFW_SEGMMU_DATA_BASE_ADDRESS); + } + else +#endif +#if defined(RGX_FEATURE_RISCV_FW_PROCESSOR_BIT_MASK) && !defined(EMULATOR) + if (RGX_IS_FEATURE_SUPPORTED(psDevInfo, RISCV_FW_PROCESSOR)) + { + ui64FwDataBaseMask = ~(RGXRISCVFW_GET_REGION_BASE(0xF)); + } + else +#endif + { + PVR_LOG_GOTO_WITH_ERROR("RGXGetFwMapping", eError, PVRSRV_ERROR_NOT_IMPLEMENTED, ErrorExit); + } + + sDevVAddr.uiAddr = (ui32FwVA & ui64FwDataBaseMask) | RGX_FIRMWARE_RAW_HEAP_BASE; + + /* Fw CPU shares a subset of the GPU's VA space */ + MMU_CheckFaultAddress(psFwMMUCtx, &sDevVAddr, &sFaultData); + } + + ui64RawPTE = sFaultData.sLevelData[MMU_LEVEL_1].ui64Address; + + if (eError == PVRSRV_OK) + { + IMG_BOOL bValidPage = (RGX_IS_FEATURE_SUPPORTED(psDevInfo, MIPS)) ? + BITMASK_HAS(ui64RawPTE, RGXMIPSFW_TLB_VALID) : + BITMASK_HAS(ui64RawPTE, RGX_MMUCTRL_PT_DATA_VALID_EN); + if (!bValidPage) + { + /* don't report invalid pages */ + eError = PVRSRV_ERROR_DEVICEMEM_NO_MAPPING; + } + else + { + sDevPA.uiAddr = ui32PageOffset + ((RGX_IS_FEATURE_SUPPORTED(psDevInfo, MIPS)) ? + RGXMIPSFW_TLB_GET_PA(ui64RawPTE) : + (ui64RawPTE & ~RGX_MMUCTRL_PT_DATA_PAGE_CLRMSK)); + + /* Only the Host's Firmware heap is present in the Host's CPU IPA space */ + if (ui32OSID == RGXFW_HOST_OS) + { + PhysHeapDevPAddrToCpuPAddr(psPhysHeap, 1, &sCpuPA, &sDevPA); + } + else + { + sCpuPA.uiAddr = 0U; + } + } + } + + if (psCpuPA != NULL) + { + *psCpuPA = sCpuPA; + } + + if (psDevPA != NULL) + { + *psDevPA = sDevPA; + } + + if (pui64RawPTE != NULL) + { + *pui64RawPTE = ui64RawPTE; + } + +ErrorExit: + return eError; +} + /****************************************************************************** End of file (rgxfwutils.c) ******************************************************************************/ diff --git a/drivers/gpu/drm/img-rogue/rgxfwutils.h b/drivers/gpu/drm/img-rogue/rgxfwutils.h index eb4253ea3..d69f92f8a 100644 --- a/drivers/gpu/drm/img-rogue/rgxfwutils.h +++ b/drivers/gpu/drm/img-rogue/rgxfwutils.h @@ -141,9 +141,15 @@ static INLINE PVRSRV_ERROR DevmemFwAllocate(PVRSRV_RGXDEV_INFO *psDevInfo, PVR_DPF_RETURN_RC(eError); } +#define MIPS_CACHE_LINE_SIZE_IN_BYTES 16 uiAlign = (psFwHeap == psDevInfo->psFirmwareConfigHeap) ? (RGX_FIRMWARE_CONFIG_HEAP_ALLOC_GRANULARITY) : - (GET_ROGUE_CACHE_LINE_SIZE(RGX_GET_FEATURE_VALUE(psDevInfo, SLC_CACHE_LINE_SIZE_BITS))); +/* + * Aligning fw based allocations for MIPS based rogue cores at cache line boundary(16 bytes) instead of SLC(64 bytes) + * to have more compact memory with less wastage and hopefully save some tlb misses. + */ + (RGX_IS_FEATURE_SUPPORTED(psDevInfo, MIPS) ? MIPS_CACHE_LINE_SIZE_IN_BYTES + : GET_ROGUE_CACHE_LINE_SIZE(RGX_GET_FEATURE_VALUE(psDevInfo, SLC_CACHE_LINE_SIZE_BITS))); eError = DevmemAllocateAndMap(psFwHeap, uiSize, @@ -559,7 +565,7 @@ PVRSRV_ERROR RGXGetFWCommonContextAddrFromServerMMUCtx(PVRSRV_RGXDEV_INFO *psDev PRGXFWIF_FWCOMMONCONTEXT *psFWCommonContextFWAddr); PVRSRV_ERROR FWCommonContextSetFlags(RGX_SERVER_COMMON_CONTEXT *psServerCommonContext, - IMG_UINT32 ui32ContextFlags); + IMG_UINT32 ui32ContextFlags); /*! ******************************************************************************* @Function RGXScheduleProcessQueuesKM @@ -669,7 +675,6 @@ PVRSRV_ERROR RGXSendCommandAndGetKCCBSlot(PVRSRV_RGXDEV_INFO *psDevInfo, @Input psDevInfo Device Info @Input eDM To which DM the cmd is sent. @Input psKCCBCmd The cmd to send. -@Input ui32CacheOpFence Pending cache op. fence value. @Input ui32PDumpFlags PDump flags @Output pui32CmdKCCBSlot When non-NULL: - Pointer on return contains the kCCB slot @@ -681,11 +686,10 @@ PVRSRV_ERROR RGXSendCommandAndGetKCCBSlot(PVRSRV_RGXDEV_INFO *psDevInfo, PVRSRV_ERROR RGXScheduleCommandAndGetKCCBSlot(PVRSRV_RGXDEV_INFO *psDevInfo, RGXFWIF_DM eKCCBType, RGXFWIF_KCCB_CMD *psKCCBCmd, - IMG_UINT32 ui32CacheOpFence, IMG_UINT32 ui32PDumpFlags, IMG_UINT32 *pui32CmdKCCBSlot); -#define RGXScheduleCommand(psDevInfo, eKCCBType, psKCCBCmd, ui32CacheOpFence, ui32PDumpFlags) \ - RGXScheduleCommandAndGetKCCBSlot(psDevInfo, eKCCBType, psKCCBCmd, ui32CacheOpFence, ui32PDumpFlags, NULL) +#define RGXScheduleCommand(psDevInfo, eKCCBType, psKCCBCmd, ui32PDumpFlags) \ + RGXScheduleCommandAndGetKCCBSlot(psDevInfo, eKCCBType, psKCCBCmd, ui32PDumpFlags, NULL) /*************************************************************************/ /*! @Function RGXWaitForKCCBSlotUpdate @@ -958,42 +962,6 @@ PVRSRV_ERROR RGXFWConfigPHR(PVRSRV_RGXDEV_INFO *psDevInfo, ******************************************************************************/ PVRSRV_ERROR RGXFWConfigWdg(PVRSRV_RGXDEV_INFO *psDevInfo, IMG_UINT32 ui32WdgPeriod); -/*! -******************************************************************************* -@Function RGXReadMETAAddr - -@Description Reads a value at given address in META memory space - (it can be either a memory location or a META register) - -@Input psDevInfo pointer to device info -@Input ui32METAAddr address in META memory space - -@Output pui32Value value - -@Return PVRSRV_ERROR -******************************************************************************/ - -PVRSRV_ERROR RGXReadMETAAddr(PVRSRV_RGXDEV_INFO *psDevInfo, - IMG_UINT32 ui32METAAddr, - IMG_UINT32 *pui32Value); - -/*! -******************************************************************************* -@Function RGXWriteMETAAddr - -@Description Write a value to the given address in META memory space - (it can be either a memory location or a META register) - -@Input psDevInfo pointer to device info -@Input ui32METAAddr address in META memory space -@Input ui32Value Value to write to address in META memory space - -@Return PVRSRV_ERROR -******************************************************************************/ - -PVRSRV_ERROR RGXWriteMETAAddr(PVRSRV_RGXDEV_INFO *psDevInfo, - IMG_UINT32 ui32METAAddr, - IMG_UINT32 ui32Value); /*! ******************************************************************************* @@ -1254,23 +1222,6 @@ PVRSRV_ERROR RGXRiscvWriteReg(PVRSRV_RGXDEV_INFO *psDevInfo, IMG_UINT32 ui32RegAddr, IMG_UINT32 ui32Value); -/*! -******************************************************************************* -@Function RGXRiscvReadMem - -@Description Read a value at the given address in RISC-V memory space - -@Input psDevInfo Pointer to device info -@Input ui32Addr Address in RISC-V memory space - -@Output pui32Value Read value - -@Return PVRSRV_ERROR -******************************************************************************/ -PVRSRV_ERROR RGXRiscvReadMem(PVRSRV_RGXDEV_INFO *psDevInfo, - IMG_UINT32 ui32Addr, - IMG_UINT32 *pui32Value); - /*! ******************************************************************************* @Function RGXRiscvPollMem @@ -1287,22 +1238,6 @@ PVRSRV_ERROR RGXRiscvPollMem(PVRSRV_RGXDEV_INFO *psDevInfo, IMG_UINT32 ui32Addr, IMG_UINT32 ui32Value); -/*! -******************************************************************************* -@Function RGXRiscvWriteMem - -@Description Write a value to the given address in RISC-V memory space - -@Input psDevInfo Pointer to device info -@Input ui32Addr Address in RISC-V memory space -@Input ui32Value Write value - -@Return PVRSRV_ERROR -******************************************************************************/ -PVRSRV_ERROR RGXRiscvWriteMem(PVRSRV_RGXDEV_INFO *psDevInfo, - IMG_UINT32 ui32MemAddr, - IMG_UINT32 ui32Value); - /*! ******************************************************************************* @Function RGXRiscvDmiOp @@ -1322,6 +1257,61 @@ PVRSRV_ERROR RGXRiscvWriteMem(PVRSRV_RGXDEV_INFO *psDevInfo, PVRSRV_ERROR RGXRiscvDmiOp(PVRSRV_RGXDEV_INFO *psDevInfo, IMG_UINT64 *pui64DMI); +/*! +******************************************************************************* +@Function RGXReadFWModuleAddr + +@Description Read a value at the given address in META or RISCV memory space + +@Input psDevInfo Pointer to device info +@Input ui32Addr Address in META or RISCV memory space + +@Output pui32Value Read value + +@Return PVRSRV_ERROR +******************************************************************************/ +PVRSRV_ERROR RGXReadFWModuleAddr(PVRSRV_RGXDEV_INFO *psDevInfo, + IMG_UINT32 ui32Addr, + IMG_UINT32 *pui32Value); + +/*! +******************************************************************************* +@Function RGXWriteFWModuleAddr + +@Description Write a value to the given address in META or RISC memory space + +@Input psDevInfo Pointer to device info +@Input ui32Addr Address in RISC-V memory space +@Input ui32Value Write value + +@Return PVRSRV_ERROR +******************************************************************************/ +PVRSRV_ERROR RGXWriteFWModuleAddr(PVRSRV_RGXDEV_INFO *psDevInfo, + IMG_UINT32 ui32MemAddr, + IMG_UINT32 ui32Value); + +/*! +******************************************************************************* +@Function RGXGetFwMapping + +@Description Retrieve any of the CPU Physical Address, Device Physical + Address or the raw value of the page table entry associated + with the firmware virtual address given. + +@Input psDevInfo Pointer to device info +@Input ui32FwVA The Fw VA that needs decoding +@Output psCpuPA Pointer to the resulting CPU PA +@Output psDevPA Pointer to the resulting Dev PA +@Output pui64RawPTE Pointer to the raw Page Table Entry value + +@Return PVRSRV_ERROR +******************************************************************************/ +PVRSRV_ERROR RGXGetFwMapping(PVRSRV_RGXDEV_INFO *psDevInfo, + IMG_UINT32 ui32FwVA, + IMG_CPU_PHYADDR *psCpuPA, + IMG_DEV_PHYADDR *psDevPA, + IMG_UINT64 *pui64RawPTE); + #if defined(SUPPORT_AUTOVZ_HW_REGS) && !defined(SUPPORT_AUTOVZ) #error "VZ build configuration error: use of OS scratch registers supported only in AutoVz drivers." #endif diff --git a/drivers/gpu/drm/img-rogue/rgxheapconfig.h b/drivers/gpu/drm/img-rogue/rgxheapconfig.h index 2c24cad1d..abb63084a 100644 --- a/drivers/gpu/drm/img-rogue/rgxheapconfig.h +++ b/drivers/gpu/drm/img-rogue/rgxheapconfig.h @@ -231,8 +231,13 @@ CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. #define RGX_FBCDC_HEAP_BASE IMG_UINT64_C(0xEC00000000) #define RGX_FBCDC_HEAP_SIZE RGX_HEAP_SIZE_2MiB -/* 0xEC_0020_0000 - 0xED_FFFF_FFFF **/ - /* 945 GiB to 952 GiB, size of 7 GiB : RESERVED VOLCANIC **/ +/* 0xEC_4000_0000 - 0xEC_401F_FFFF **/ + /* 945 GiB to 946 GiB, size 2 MiB : FBCDC_LARGE_HEAP **/ + #define RGX_FBCDC_LARGE_HEAP_BASE IMG_UINT64_C(0xEC40000000) + #define RGX_FBCDC_LARGE_HEAP_SIZE RGX_HEAP_SIZE_2MiB + +/* 0xEC_8000_0000 - 0xED_FFFF_FFFF **/ + /* 946 GiB to 952 GiB, size of 6 GiB : RESERVED VOLCANIC **/ /* 0xEE_0000_0000 - 0xEE_3FFF_FFFF **/ /* 952 GiB to 953 GiB, size of 1 GiB : CMP_MISSION_RMW_HEAP **/ diff --git a/drivers/gpu/drm/img-rogue/rgxhwperf.c b/drivers/gpu/drm/img-rogue/rgxhwperf.c index 1552fa255..a6e2dd420 100644 --- a/drivers/gpu/drm/img-rogue/rgxhwperf.c +++ b/drivers/gpu/drm/img-rogue/rgxhwperf.c @@ -121,52 +121,6 @@ RGXSuspendHWPerfL2DataCopy(PVRSRV_RGXDEV_INFO* psDeviceInfo, } } -/*************************************************************************/ /*! -@Function RGXHWPerfIsInitRequired - -@Description Returns true if the HWperf firmware buffer (L1 buffer) and host - driver TL buffer (L2 buffer) are not already allocated. Caller - must possess hHWPerfLock lock before calling this - function so the state tested is not inconsistent. - -@Input psRgxDevInfo RGX Device Info, on which init requirement is - checked. - -@Return IMG_BOOL Whether initialization (allocation) is required - */ /**************************************************************************/ -static INLINE IMG_BOOL RGXHWPerfIsInitRequired(PVRSRV_RGXDEV_INFO *psRgxDevInfo) -{ - PVR_ASSERT(OSLockIsLocked(psRgxDevInfo->hHWPerfLock)); - -#if !defined(NO_HARDWARE) - /* Both L1 and L2 buffers are required (for HWPerf functioning) on driver - * built for actual hardware (TC, EMU, etc.) - */ - if (psRgxDevInfo->hHWPerfStream == (IMG_HANDLE) NULL) - { - /* The allocation API (RGXHWPerfInitOnDemandResources) allocates - * device memory for both L1 and L2 without any checks. Hence, - * either both should be allocated or both be NULL. - * - * In-case this changes in future (for e.g. a situation where one - * of the 2 buffers is already allocated and other is required), - * add required checks before allocation calls to avoid memory leaks. - */ - PVR_ASSERT(psRgxDevInfo->psRGXFWIfHWPerfBufMemDesc == NULL); - return IMG_TRUE; - } - PVR_ASSERT(psRgxDevInfo->psRGXFWIfHWPerfBufMemDesc != NULL); -#else - /* On a NO-HW driver L2 is not allocated. So, no point in checking its - * allocation */ - if (psRgxDevInfo->psRGXFWIfHWPerfBufMemDesc == NULL) - { - return IMG_TRUE; - } -#endif - return IMG_FALSE; -} - /****************************************************************************** * RGX HW Performance Profiling Server API(s) *****************************************************************************/ @@ -188,7 +142,14 @@ static IMG_BOOL RGXServerFeatureFlagsToHWPerfFlagsAddBlock( number of blocks and counters) but PVRScopeServices expects the latter (plus the number of blocks and counters). The conversion could always be moved to PVRScopeServices, but it's less code this way. */ psBlock->ui16BlockID = (ui16BlockID & RGX_CNTBLK_ID_GROUP_MASK) ? (ui16BlockID | RGX_CNTBLK_ID_UNIT_ALL_MASK) : ui16BlockID; - psBlock->ui16NumCounters = ui16NumCounters; + if ((ui16BlockID & RGX_CNTBLK_ID_DA_MASK) == RGX_CNTBLK_ID_DA_MASK) + { + psBlock->ui16NumCounters = RGX_CNTBLK_COUNTERS_MAX; + } + else + { + psBlock->ui16NumCounters = ui16NumCounters; + } psBlock->ui16NumBlocks = ui16NumBlocks; *pui16Count = ui16Count + 1; @@ -219,26 +180,34 @@ PVRSRV_ERROR RGXServerFeatureFlagsToHWPerfFlags(PVRSRV_RGXDEV_INFO *psDevInfo, R { psBVNC->ui32BvncKmFeatureFlags |= RGX_HWPERF_FEATURE_PERFBUS_FLAG; } +#if defined(RGX_FEATURE_S7_TOP_INFRASTRUCTURE_BIT_MASK) if (RGX_IS_FEATURE_SUPPORTED(psDevInfo, S7_TOP_INFRASTRUCTURE)) { psBVNC->ui32BvncKmFeatureFlags |= RGX_HWPERF_FEATURE_S7_TOP_INFRASTRUCTURE_FLAG; } +#endif +#if defined(RGX_FEATURE_XT_TOP_INFRASTRUCTURE_BIT_MASK) if (RGX_IS_FEATURE_SUPPORTED(psDevInfo, XT_TOP_INFRASTRUCTURE)) { psBVNC->ui32BvncKmFeatureFlags |= RGX_HWPERF_FEATURE_XT_TOP_INFRASTRUCTURE_FLAG; } +#endif +#if defined(RGX_FEATURE_PERF_COUNTER_BATCH_BIT_MASK) if (RGX_IS_FEATURE_SUPPORTED(psDevInfo, PERF_COUNTER_BATCH)) { psBVNC->ui32BvncKmFeatureFlags |= RGX_HWPERF_FEATURE_PERF_COUNTER_BATCH_FLAG; } +#endif if (RGX_IS_FEATURE_SUPPORTED(psDevInfo, ROGUEXE)) { psBVNC->ui32BvncKmFeatureFlags |= RGX_HWPERF_FEATURE_ROGUEXE_FLAG; } +#if defined(RGX_FEATURE_DUST_POWER_ISLAND_S7_BIT_MASK) if (RGX_IS_FEATURE_SUPPORTED(psDevInfo, DUST_POWER_ISLAND_S7)) { psBVNC->ui32BvncKmFeatureFlags |= RGX_HWPERF_FEATURE_DUST_POWER_ISLAND_S7_FLAG; } +#endif if (RGX_IS_FEATURE_SUPPORTED(psDevInfo, PBE2_IN_XE)) { psBVNC->ui32BvncKmFeatureFlags |= RGX_HWPERF_FEATURE_PBE2_IN_XE_FLAG; @@ -360,7 +329,6 @@ PVRSRV_ERROR PVRSRVRGXConfigMuxHWPerfCountersKM( eError = RGXScheduleCommandAndGetKCCBSlot(psDevice, RGXFWIF_DM_GP, &sKccbCmd, - 0, PDUMP_FLAGS_CONTINUOUS, &ui32kCCBCommandSlot); PVR_LOG_GOTO_IF_ERROR(eError, "RGXScheduleCommandAndGetKCCBSlot", fail2); @@ -463,7 +431,6 @@ PVRSRV_ERROR PVRSRVRGXConfigCustomCountersKM( eError = RGXScheduleCommandAndGetKCCBSlot(psDevice, RGXFWIF_DM_GP, &sKccbCmd, - 0, PDUMP_FLAGS_CONTINUOUS, &ui32kCCBCommandSlot); PVR_LOG_GOTO_IF_ERROR(eError, "RGXScheduleCommandAndGetKCCBSlot", fail3); @@ -517,30 +484,93 @@ PVRSRV_ERROR PVRSRVRGXConfigureHWPerfBlocksKM( IMG_UINT32 ui32ArrayLen, RGX_HWPERF_CONFIG_CNTBLK * psBlockConfigs) { - IMG_INT i; + PVRSRV_ERROR eError = PVRSRV_OK; + RGXFWIF_KCCB_CMD sKccbCmd; + DEVMEM_MEMDESC *psFwBlkConfigsMemDesc; + RGX_HWPERF_CONFIG_CNTBLK *psFwArray; + IMG_UINT32 ui32kCCBCommandSlot; + PVRSRV_RGXDEV_INFO *psDevice; - PVR_UNREFERENCED_PARAMETER(psConnection); - PVR_UNREFERENCED_PARAMETER(psDeviceNode); + PVR_LOG_RETURN_IF_FALSE(psDeviceNode != NULL, "psDeviceNode is NULL", + PVRSRV_ERROR_INVALID_PARAMS); - PVR_DPF((PVR_DBG_WARNING, "%s: ui32CtrlWord = %u", __func__, ui32CtrlWord)); - PVR_DPF((PVR_DBG_WARNING, "%s: ui32ArrayLen = %u", __func__, ui32ArrayLen)); - for (i = 0; i < ui32ArrayLen; i++) - { - IMG_INT j; + psDevice = psDeviceNode->pvDevice; - PVR_DPF((PVR_DBG_WARNING, "%s: psBlockConfigs[%d].ui16BlockID = 0x%x", - __func__, i, psBlockConfigs[i].ui16BlockID)); - PVR_DPF((PVR_DBG_WARNING, "%s: psBlockConfigs[%d].ui16NumCounters = %u", - __func__, i, psBlockConfigs[i].ui16NumCounters)); + PVR_UNREFERENCED_PARAMETER(ui32CtrlWord); - for (j = 0; j < psBlockConfigs[i].ui16NumCounters; j++) - { - PVR_DPF((PVR_DBG_WARNING, "%s: psBlockConfigs[%d].ui16Counters[%d] = 0x%x", - __func__, i, j, psBlockConfigs[i].ui16Counters[j])); - } - } + PVRSRV_VZ_RET_IF_MODE(GUEST, PVRSRV_ERROR_NOT_SUPPORTED); - return PVRSRV_ERROR_NOT_IMPLEMENTED; + PVR_LOG_RETURN_IF_FALSE(ui32ArrayLen > 0, "ui32ArrayLen is 0", + PVRSRV_ERROR_INVALID_PARAMS); + PVR_LOG_RETURN_IF_FALSE(psBlockConfigs != NULL, "psBlockConfigs is NULL", + PVRSRV_ERROR_INVALID_PARAMS); + + PVR_DPF_ENTERED; + + /* Fill in the command structure with the parameters needed */ + sKccbCmd.eCmdType = RGXFWIF_KCCB_CMD_HWPERF_CONFIG_BLKS; + sKccbCmd.uCmdData.sHWPerfCfgDABlks.ui32NumBlocks = ui32ArrayLen; + + /* used for passing counters config to the Firmware, write-only for the CPU */ + eError = DevmemFwAllocate(psDevice, + sizeof(RGX_HWPERF_CONFIG_CNTBLK) * ui32ArrayLen, + PVRSRV_MEMALLOCFLAG_DEVICE_FLAG(PMMETA_PROTECT) | + PVRSRV_MEMALLOCFLAG_GPU_READABLE | + PVRSRV_MEMALLOCFLAG_GPU_UNCACHED | + PVRSRV_MEMALLOCFLAG_CPU_WRITEABLE | + PVRSRV_MEMALLOCFLAG_CPU_UNCACHED_WC | + PVRSRV_MEMALLOCFLAG_KERNEL_CPU_MAPPABLE | + PVRSRV_MEMALLOCFLAG_PHYS_HEAP_HINT(FW_MAIN), + "FwHWPerfCountersDAConfigBlock", + &psFwBlkConfigsMemDesc); + PVR_LOG_RETURN_IF_ERROR(eError, "DevmemFwAllocate"); + + eError = RGXSetFirmwareAddress(&sKccbCmd.uCmdData.sHWPerfCfgDABlks.sBlockConfigs, + psFwBlkConfigsMemDesc, 0, RFW_FWADDR_FLAG_NONE); + PVR_LOG_GOTO_IF_ERROR(eError, "RGXSetFirmwareAddress", fail1); + + eError = DevmemAcquireCpuVirtAddr(psFwBlkConfigsMemDesc, (void **)&psFwArray); + PVR_LOG_GOTO_IF_ERROR(eError, "DevMemAcquireCpuVirtAddr", fail2); + + OSCachedMemCopyWMB(psFwArray, psBlockConfigs, sizeof(RGX_HWPERF_CONFIG_CNTBLK)*ui32ArrayLen); + DevmemPDumpLoadMem(psFwBlkConfigsMemDesc, + 0, + sizeof(RGX_HWPERF_CONFIG_CNTBLK)*ui32ArrayLen, + PDUMP_FLAGS_CONTINUOUS); + + /* Ask the FW to carry out the HWPerf configuration command. */ + eError = RGXScheduleCommandAndGetKCCBSlot(psDevice, + RGXFWIF_DM_GP, + &sKccbCmd, + PDUMP_FLAGS_CONTINUOUS, + &ui32kCCBCommandSlot); + + PVR_LOG_GOTO_IF_ERROR(eError, "RGXScheduleCommandAndGetKCCBSlot", fail2); + + /* Wait for FW to complete */ + eError = RGXWaitForKCCBSlotUpdate(psDevice, ui32kCCBCommandSlot, PDUMP_FLAGS_CONTINUOUS); + PVR_LOG_GOTO_IF_ERROR(eError, "RGXWaitForKCCBSlotUpdate", fail3); + + /* Release temporary memory used for block configuration. */ + RGXUnsetFirmwareAddress(psFwBlkConfigsMemDesc); + DevmemReleaseCpuVirtAddr(psFwBlkConfigsMemDesc); + DevmemFwUnmapAndFree(psDevice, psFwBlkConfigsMemDesc); + + PVR_DPF((PVR_DBG_WARNING, "HWPerf %d counter blocks configured and ENABLED", + ui32ArrayLen)); + + PVR_DPF_RETURN_OK; + +fail3: + DevmemReleaseCpuVirtAddr(psFwBlkConfigsMemDesc); + +fail2: + RGXUnsetFirmwareAddress(psFwBlkConfigsMemDesc); + +fail1: + DevmemFwUnmapAndFree(psDevice, psFwBlkConfigsMemDesc); + + PVR_DPF_RETURN_RC (eError); } /****************************************************************************** diff --git a/drivers/gpu/drm/img-rogue/rgxhwperf_common.c b/drivers/gpu/drm/img-rogue/rgxhwperf_common.c index 9c910bbd7..e2b472d51 100644 --- a/drivers/gpu/drm/img-rogue/rgxhwperf_common.c +++ b/drivers/gpu/drm/img-rogue/rgxhwperf_common.c @@ -321,7 +321,7 @@ static IMG_UINT32 RGXHWPerfDataStore(PVRSRV_RGXDEV_INFO *psDevInfo) * indexes of the FW buffer */ ui32SrcRIdx = psFwSysData->ui32HWPerfRIdx; ui32SrcWIdx = psFwSysData->ui32HWPerfWIdx; - OSMemoryBarrier(); + OSMemoryBarrier(NULL); ui32SrcWrapCount = psFwSysData->ui32HWPerfWrapCount; #if defined(HWPERF_MISR_FUNC_DEBUG) || defined(EMULATOR) @@ -649,7 +649,6 @@ static void _HWPerfFWOnReaderOpenCB(void *pvArg) eError = RGXScheduleCommandAndGetKCCBSlot(psDevNode->pvDevice, RGXFWIF_DM_GP, &sKccbCmd, - 0, PDUMP_FLAGS_CONTINUOUS, &ui32kCCBCommandSlot); if (eError != PVRSRV_OK) @@ -741,7 +740,7 @@ PVRSRV_ERROR RGXHWPerfInitOnDemandResources(PVRSRV_RGXDEV_INFO* psRgxDevInfo) #endif /* flush write buffers for psRgxDevInfo->psRGXFWIfRuntimeCfg */ - OSWriteMemoryBarrier(); + OSWriteMemoryBarrier(&psRgxDevInfo->psRGXFWIfRuntimeCfg->sHWPerfBuf.ui32Addr); eError = DevmemAcquireCpuVirtAddr(psRgxDevInfo->psRGXFWIfHWPerfBufMemDesc, (void**)&psRgxDevInfo->psRGXFWIfHWPerfBuf); @@ -918,7 +917,7 @@ static PVRSRV_ERROR RGXHWPerfCtrlFwBuffer(const PVRSRV_DEVICE_NODE *psDeviceNode } } -#if defined(RGX_FEATURE_HWPERF_VOLCANIC) && defined(SUPPORT_POWMON_COMPONENT) +#if defined(RGX_FEATURE_HWPERF_VOLCANIC) && defined(SUPPORT_POWMON_COMPONENT) && defined(SUPPORT_POWER_VALIDATION_VIA_DEBUGFS) if (RGXPowmonBufferIsInitRequired(psDeviceNode->pvDevice)) { /* Allocate power monitoring log buffer if enabled */ @@ -949,7 +948,6 @@ static PVRSRV_ERROR RGXHWPerfCtrlFwBuffer(const PVRSRV_DEVICE_NODE *psDeviceNode eError = RGXScheduleCommandAndGetKCCBSlot(psDevice, RGXFWIF_DM_GP, &sKccbCmd, - 0, IMG_TRUE, &ui32kCCBCommandSlot); if (eError != PVRSRV_OK) @@ -1338,6 +1336,10 @@ error: return eError; } +#define RGX_HWPERF_HOST_CLIENT_INFO_PROC_NAME_BASE_SIZE \ + ((IMG_UINT32)(offsetof(RGX_HWPERF_HOST_CLIENT_INFO_DATA, uDetail) + \ + sizeof(((RGX_HWPERF_HOST_CLIENT_INFO_DETAIL*)0)->sProcName.ui32Count))) + static void _HWPerfHostOnConnectCB(void *pvArg) { PVRSRV_RGXDEV_INFO* psDevice; @@ -1355,6 +1357,65 @@ static void _HWPerfHostOnConnectCB(void *pvArg) eError = PVRSRVCreateHWPerfHostThread(PVRSRV_APPHINT_HWPERFHOSTTHREADTIMEOUTINMS); PVR_LOG_IF_ERROR(eError, "PVRSRVCreateHWPerfHostThread"); } + + if (RGXHWPerfHostIsEventEnabled(psDevice, RGX_HWPERF_HOST_CLIENT_INFO)) + { + // GCC throws -Werror=frame-larger-than error if the frame size is > 1024 bytes, + // so use a heap allocation - is there an alternate solution? + IMG_BYTE *pbPktPayload = (IMG_BYTE*)OSAllocMem(RGX_HWPERF_MAX_PAYLOAD_SIZE); + + if (pbPktPayload) + { + RGX_HWPERF_HOST_CLIENT_INFO_DATA *psHostClientInfo; + RGX_HWPERF_HOST_CLIENT_PROC_NAME *psProcName; + IMG_UINT32 ui32TotalPayloadSize, ui32NameLen, ui32ProcNamePktSize; + DLLIST_NODE *pNode, *pNext; + + psHostClientInfo = IMG_OFFSET_ADDR(pbPktPayload,0); + psHostClientInfo->eType = RGX_HWPERF_HOST_CLIENT_INFO_TYPE_PROCESS_NAME; + psHostClientInfo->uDetail.sProcName.ui32Count = 0U; + psProcName = psHostClientInfo->uDetail.sProcName.asProcNames; + ui32TotalPayloadSize = RGX_HWPERF_HOST_CLIENT_INFO_PROC_NAME_BASE_SIZE; + + OSLockAcquire(psDevice->psDeviceNode->hConnectionsLock); + + // Announce current client connections to the reader + dllist_foreach_node(&psDevice->psDeviceNode->sConnections, pNode, pNext) + { + CONNECTION_DATA *psData = IMG_CONTAINER_OF(pNode, CONNECTION_DATA, sConnectionListNode); + + ui32NameLen = OSStringLength(psData->pszProcName) + 1U; + ui32ProcNamePktSize = RGX_HWPERF_HOST_CLIENT_PROC_NAME_SIZE(ui32NameLen); + + // Unlikely case where we have too much data to fit into a single hwperf packet + if (ui32ProcNamePktSize + ui32TotalPayloadSize > RGX_HWPERF_MAX_PAYLOAD_SIZE) + { + RGXHWPerfHostPostRaw(psDevice, RGX_HWPERF_HOST_CLIENT_INFO, pbPktPayload, ui32TotalPayloadSize); + + psHostClientInfo->uDetail.sProcName.ui32Count = 0U; + psProcName = psHostClientInfo->uDetail.sProcName.asProcNames; + ui32TotalPayloadSize = RGX_HWPERF_HOST_CLIENT_INFO_PROC_NAME_BASE_SIZE; + } + + // Setup packet data + psHostClientInfo->uDetail.sProcName.ui32Count++; + psProcName->uiClientPID = psData->pid; + psProcName->ui32Length = ui32NameLen; + (void)OSStringLCopy(psProcName->acName, psData->pszProcName, ui32NameLen); + + psProcName = (RGX_HWPERF_HOST_CLIENT_PROC_NAME*)IMG_OFFSET_ADDR(psProcName, ui32ProcNamePktSize); + ui32TotalPayloadSize += ui32ProcNamePktSize; + } + + OSLockRelease(psDevice->psDeviceNode->hConnectionsLock); + RGXHWPerfHostPostRaw(psDevice, RGX_HWPERF_HOST_CLIENT_INFO, pbPktPayload, ui32TotalPayloadSize); + OSFreeMem(pbPktPayload); + } + else + { + PVR_DPF((PVR_DBG_ERROR, "%s: OUT OF MEMORY. Could not allocate memory for RGX_HWPERF_HOST_CLIENT_INFO_DATA packet.", __func__)); + } + } } /* Avoiding a holder struct using fields below, as a struct gets along padding, @@ -1879,6 +1940,37 @@ static inline void _SetupHostEnqPacketData(IMG_UINT8 *pui8Dest, psData->ui32CycleEstimate = ui32CycleEstimate; } +void RGXHWPerfHostPostRaw(PVRSRV_RGXDEV_INFO *psRgxDevInfo, + RGX_HWPERF_HOST_EVENT_TYPE eEvType, + IMG_BYTE *pbPayload, + IMG_UINT32 ui32PayloadSize) +{ + IMG_UINT8 *pui8Dest; + IMG_UINT32 ui32PktSize; + IMG_UINT32 ui32Ordinal; + IMG_UINT64 ui64Timestamp; + + PVR_ASSERT(ui32PayloadSize <= RGX_HWPERF_MAX_PAYLOAD_SIZE); + + _GetHWPerfHostPacketSpecifics(psRgxDevInfo, &ui32Ordinal, &ui64Timestamp, NULL, IMG_TRUE); + _PostFunctionPrologue(psRgxDevInfo, ui32Ordinal); + + ui32PktSize = RGX_HWPERF_MAKE_SIZE_VARIABLE(ui32PayloadSize); + pui8Dest = _ReserveHWPerfStream(psRgxDevInfo, ui32PktSize); + + if (pui8Dest == NULL) + { + goto cleanup; + } + + _SetupHostPacketHeader(psRgxDevInfo, pui8Dest, eEvType, ui32PktSize, ui32Ordinal, ui64Timestamp); + OSDeviceMemCopy((IMG_UINT8*)IMG_OFFSET_ADDR(pui8Dest, sizeof(RGX_HWPERF_V2_PACKET_HDR)), pbPayload, ui32PayloadSize); + _CommitHWPerfStream(psRgxDevInfo, ui32PktSize); + +cleanup: + _PostFunctionEpilogue(psRgxDevInfo, ui32Ordinal); +} + void RGXHWPerfHostPostEnqEvent(PVRSRV_RGXDEV_INFO *psRgxDevInfo, RGX_HWPERF_KICK_TYPE eEnqType, IMG_UINT32 ui32Pid, @@ -2790,6 +2882,45 @@ cleanup: } +void RGXHWPerfHostPostClientInfoProcName(PVRSRV_RGXDEV_INFO *psRgxDevInfo, + IMG_PID uiPID, + const IMG_CHAR *psName) +{ + RGX_HWPERF_HOST_CLIENT_INFO_DATA* psPkt; + IMG_UINT8 *pui8Dest; + IMG_UINT32 ui32Size; + IMG_UINT32 ui32NameLen; + IMG_UINT32 ui32Ordinal; + IMG_UINT64 ui64Timestamp; + + _GetHWPerfHostPacketSpecifics(psRgxDevInfo, &ui32Ordinal, &ui64Timestamp, NULL, IMG_TRUE); + _PostFunctionPrologue(psRgxDevInfo, ui32Ordinal); + + ui32NameLen = OSStringLength(psName) + 1U; + ui32Size = RGX_HWPERF_MAKE_SIZE_VARIABLE(RGX_HWPERF_HOST_CLIENT_INFO_PROC_NAME_BASE_SIZE + + RGX_HWPERF_HOST_CLIENT_PROC_NAME_SIZE(ui32NameLen)); + + if ((pui8Dest = _ReserveHWPerfStream(psRgxDevInfo, ui32Size)) == NULL) + { + goto cleanup; + } + + _SetupHostPacketHeader(psRgxDevInfo, pui8Dest, RGX_HWPERF_HOST_CLIENT_INFO, + ui32Size, ui32Ordinal, ui64Timestamp); + + psPkt = (RGX_HWPERF_HOST_CLIENT_INFO_DATA*)IMG_OFFSET_ADDR(pui8Dest, sizeof(RGX_HWPERF_V2_PACKET_HDR)); + psPkt->eType = RGX_HWPERF_HOST_CLIENT_INFO_TYPE_PROCESS_NAME; + psPkt->uDetail.sProcName.ui32Count = 1U; + psPkt->uDetail.sProcName.asProcNames[0].uiClientPID = uiPID; + psPkt->uDetail.sProcName.asProcNames[0].ui32Length = ui32NameLen; + (void)OSStringLCopy(psPkt->uDetail.sProcName.asProcNames[0].acName, psName, ui32NameLen); + + _CommitHWPerfStream(psRgxDevInfo, ui32Size); + +cleanup: + _PostFunctionEpilogue(psRgxDevInfo, ui32Ordinal); +} + /****************************************************************************** * Currently only implemented on Linux. Feature can be enabled to provide * an interface to 3rd-party kernel modules that wish to access the @@ -2844,7 +2975,9 @@ PVRSRV_ERROR RGXHWPerfLazyConnect(RGX_HWPERF_CONNECTION** ppsHWPerfConnection) /* early save the return pointer to aid clean-up if failure occurs */ *ppsHWPerfConnection = psHWPerfConnection; + OSWRLockAcquireRead(psPVRSRVData->hDeviceNodeListLock); psDeviceNode = psPVRSRVData->psDeviceNodeList; + while (psDeviceNode) { if (psDeviceNode->eDevState != PVRSRV_DEVICE_STATE_ACTIVE) @@ -2860,6 +2993,7 @@ PVRSRV_ERROR RGXHWPerfLazyConnect(RGX_HWPERF_CONNECTION** ppsHWPerfConnection) psNewHWPerfDevice = OSAllocMem(sizeof(*psNewHWPerfDevice)); if (!psNewHWPerfDevice) { + OSWRLockReleaseRead(psPVRSRVData->hDeviceNodeListLock); return PVRSRV_ERROR_OUT_OF_MEMORY; } /* Insert node at head of the list */ @@ -2871,11 +3005,13 @@ PVRSRV_ERROR RGXHWPerfLazyConnect(RGX_HWPERF_CONNECTION** ppsHWPerfConnection) psNewHWPerfDevice->hDevData = (IMG_HANDLE)psDevData; if (!psDevData) { + OSWRLockReleaseRead(psPVRSRVData->hDeviceNodeListLock); return PVRSRV_ERROR_OUT_OF_MEMORY; } if (OSSNPrintf(psNewHWPerfDevice->pszName, sizeof(psNewHWPerfDevice->pszName), - "hwperf_device_%d", psDeviceNode->sDevId.i32OsDeviceID) < 0) + "hwperf_device_%d", psDeviceNode->sDevId.i32OsDeviceID) < 0) { + OSWRLockReleaseRead(psPVRSRVData->hDeviceNodeListLock); PVR_DPF((PVR_DBG_ERROR, "%s: Failed to form HWPerf device name for device %d", __func__, @@ -2892,6 +3028,8 @@ PVRSRV_ERROR RGXHWPerfLazyConnect(RGX_HWPERF_CONNECTION** ppsHWPerfConnection) bFWActive = IMG_TRUE; } + OSWRLockReleaseRead(psPVRSRVData->hDeviceNodeListLock); + if (!bFWActive) { return PVRSRV_ERROR_NOT_READY; @@ -3092,7 +3230,6 @@ PVRSRV_ERROR PVRSRVRGXControlHWPerfBlocksKM( eError = RGXScheduleCommandAndGetKCCBSlot(psDevice, RGXFWIF_DM_GP, &sKccbCmd, - 0, PDUMP_FLAGS_CONTINUOUS, &ui32kCCBCommandSlot); PVR_LOG_RETURN_IF_ERROR(eError, "RGXScheduleCommandAndGetKCCBSlot"); diff --git a/drivers/gpu/drm/img-rogue/rgxhwperf_common.h b/drivers/gpu/drm/img-rogue/rgxhwperf_common.h index 91d0a0d4e..76957c35e 100644 --- a/drivers/gpu/drm/img-rogue/rgxhwperf_common.h +++ b/drivers/gpu/drm/img-rogue/rgxhwperf_common.h @@ -109,6 +109,11 @@ void RGXHWPerfHostDeInit(PVRSRV_RGXDEV_INFO *psRgxDevInfo); void RGXHWPerfHostSetEventFilter(PVRSRV_RGXDEV_INFO *psRgxDevInfo, IMG_UINT32 ui32Filter); +void RGXHWPerfHostPostRaw(PVRSRV_RGXDEV_INFO *psRgxDevInfo, + RGX_HWPERF_HOST_EVENT_TYPE eEvType, + IMG_BYTE *pbPayload, + IMG_UINT32 ui32PayloadSize); + void RGXHWPerfHostPostEnqEvent(PVRSRV_RGXDEV_INFO *psRgxDevInfo, RGX_HWPERF_KICK_TYPE eEnqType, IMG_UINT32 ui32Pid, @@ -169,6 +174,10 @@ void RGXHWPerfHostPostSWTimelineAdv(PVRSRV_RGXDEV_INFO *psRgxDevInfo, PVRSRV_TIMELINE hSWTimeline, IMG_UINT64 ui64SyncPtIndex); +void RGXHWPerfHostPostClientInfoProcName(PVRSRV_RGXDEV_INFO *psRgxDevInfo, + IMG_PID uiPID, + const IMG_CHAR *psName); + IMG_BOOL RGXHWPerfHostIsEventEnabled(PVRSRV_RGXDEV_INFO *psRgxDevInfo, RGX_HWPERF_HOST_EVENT_TYPE eEvent); #define _RGX_HWPERF_HOST_FILTER(CTX, EV) \ @@ -466,6 +475,20 @@ do { \ RGXHWPerfHostPostSWTimelineAdv((I), (PID), (SW_TL), (SPI)); \ } \ } while (0) + +/** + * @param D Device Node pointer + * @param PID Process ID that the following timeline belongs to + * @param N Null terminated string containing the process name + */ +#define RGXSRV_HWPERF_HOST_CLIENT_INFO_PROCESS_NAME(D, PID, N) \ +do { \ + if (RGXHWPerfHostIsEventEnabled(_RGX_DEVICE_INFO_FROM_NODE(D), RGX_HWPERF_HOST_CLIENT_INFO)) \ + { \ + RGXHWPerfHostPostClientInfoProcName(_RGX_DEVICE_INFO_FROM_NODE(D), (PID), (N)); \ + } \ +} while (0) + #else #define RGXSRV_HWPERF_ENQ(C, P, X, E, I, K, CF, UF, UT, CHKUID, UPDUID, D, CE) @@ -482,6 +505,7 @@ do { \ #define RGXSRV_HWPERF_HOST_INFO(I, T) #define RGXSRV_HWPERF_SYNC_FENCE_WAIT(I, T, PID, F, D) #define RGXSRV_HWPERF_SYNC_SW_TL_ADV(I, PID, SW_TL, SPI) +#define RGXSRV_HWPERF_HOST_CLIENT_INFO_PROCESS_NAME(D, PID, N) #endif diff --git a/drivers/gpu/drm/img-rogue/rgxinit.c b/drivers/gpu/drm/img-rogue/rgxinit.c index 27e162ac1..dd572a5c6 100644 --- a/drivers/gpu/drm/img-rogue/rgxinit.c +++ b/drivers/gpu/drm/img-rogue/rgxinit.c @@ -119,6 +119,10 @@ CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. #include "rgxpdvfs.h" #endif +#if defined(SUPPORT_VALIDATION) && defined(SUPPORT_SOC_TIMER) +#include "rgxsoctimer.h" +#endif + #if defined(PDUMP) && defined(SUPPORT_SECURITY_VALIDATION) #include "pdump_physmem.h" #endif @@ -128,24 +132,13 @@ static PVRSRV_ERROR RGXDevVersionString(PVRSRV_DEVICE_NODE *psDeviceNode, IMG_CH static PVRSRV_ERROR RGXDevClockSpeed(PVRSRV_DEVICE_NODE *psDeviceNode, IMG_PUINT32 pui32RGXClockSpeed); static PVRSRV_ERROR RGXSoftReset(PVRSRV_DEVICE_NODE *psDeviceNode, IMG_UINT64 ui64ResetValue1, IMG_UINT64 ui64ResetValue2); static PVRSRV_ERROR RGXPhysMemDeviceHeapsInit(PVRSRV_DEVICE_NODE *psDeviceNode); +static void DevPart2DeInitRGX(PVRSRV_DEVICE_NODE *psDeviceNode); #if (RGX_NUM_OS_SUPPORTED > 1) static PVRSRV_ERROR RGXInitFwRawHeap(DEVMEM_HEAP_BLUEPRINT *psDevMemHeap, IMG_UINT32 ui32OSid); static void RGXDeInitFwRawHeap(DEVMEM_HEAP_BLUEPRINT *psDevMemHeap); #endif -#if defined(SUPPORT_AUTOVZ) -#define RGX_FW_MMU_RESERVED_MEM_SETUP(devnode) (MMU_PX_SETUP) { \ - LMA_PhyContigPagesAlloc, \ - LMA_PhyContigPagesFree, \ - LMA_PhyContigPagesMap, \ - LMA_PhyContigPagesUnmap, \ - LMA_PhyContigPagesClean, \ - OSGetPageShift(), \ - (devnode)->psFwMMUReservedMemArena \ - } -#endif - /* Services internal heap identification used in this file only */ #define RGX_FIRMWARE_MAIN_HEAP_IDENT "FwMain" /*!< RGX Main Firmware Heap identifier */ #define RGX_FIRMWARE_CONFIG_HEAP_IDENT "FwConfig" /*!< RGX Config firmware Heap identifier */ @@ -228,7 +221,6 @@ static INLINE IMG_UINT32 RGXHostSafetyEvents(PVRSRV_RGXDEV_INFO *psDevInfo) else { IMG_UINT32 ui32SafetyEventStatus = OSReadHWReg32(psDevInfo->pvRegsBaseKM, RGX_CR_SAFETY_EVENT_STATUS__ROGUEXE); - return (ui32SafetyEventStatus & psDevInfo->ui32HostSafetyEventMask); } } @@ -423,6 +415,7 @@ static inline IMG_BOOL RGXAckHwIrq(PVRSRV_RGXDEV_INFO *psDevInfo, } } +#if defined(RGX_FEATURE_META_MAX_VALUE_IDX) static IMG_BOOL RGXAckIrqMETA(PVRSRV_RGXDEV_INFO *psDevInfo) { return RGXAckHwIrq(psDevInfo, @@ -431,6 +424,7 @@ static IMG_BOOL RGXAckIrqMETA(PVRSRV_RGXDEV_INFO *psDevInfo) RGX_CR_META_SP_MSLVIRQSTATUS, RGX_CR_META_SP_MSLVIRQSTATUS_TRIGVECT2_CLRMSK); } +#endif static IMG_BOOL RGXAckIrqMIPS(PVRSRV_RGXDEV_INFO *psDevInfo) { @@ -672,7 +666,7 @@ static PVRSRV_ERROR RGXGetGpuUtilStats(PVRSRV_DEVICE_NODE *psDeviceNode, /***** (3) Compute return stats *****/ /* Update temp counters to account for the time since the last update to the shared ones */ - OSMemoryBarrier(); /* Ensure the current time is read after the loop above */ + OSMemoryBarrier(NULL); /* Ensure the current time is read after the loop above */ ui64TimeNow = RGXFWIF_GPU_UTIL_GET_TIME(RGXTimeCorrGetClockns64(psDeviceNode)); ui64LastTime = RGXFWIF_GPU_UTIL_GET_TIME(ui64LastWord); ui64LastPeriod = RGXFWIF_GPU_UTIL_GET_PERIOD(ui64TimeNow, ui64LastTime); @@ -950,6 +944,7 @@ static PVRSRV_ERROR RGXSetPowerParams(PVRSRV_RGXDEV_INFO *psDevInfo, #if defined(PDUMP) psDevInfo->sLayerParams.ui32PdumpFlags = PDUMP_FLAGS_CONTINUOUS; #endif +#if defined(RGX_FEATURE_META_MAX_VALUE_IDX) || defined(RGX_FEATURE_RISCV_FW_PROCESSOR_BIT_MASK) if (RGX_IS_FEATURE_VALUE_SUPPORTED(psDevInfo, META) || RGX_IS_FEATURE_SUPPORTED(psDevInfo, RISCV_FW_PROCESSOR)) { @@ -990,6 +985,7 @@ static PVRSRV_ERROR RGXSetPowerParams(PVRSRV_RGXDEV_INFO *psDevInfo, psDevInfo->sLayerParams.sPCAddr = sKernelMMUCtxPCAddr; } else +#endif { PMR *psFWCodePMR = (PMR *)(psDevInfo->psRGXFWCodeMemDesc->psImport->hPMR); PMR *psFWDataPMR = (PMR *)(psDevInfo->psRGXFWDataMemDesc->psImport->hPMR); @@ -1074,12 +1070,19 @@ static PVRSRV_ERROR RGXSetPowerParams(PVRSRV_RGXDEV_INFO *psDevInfo, { PVRSRV_TD_POWER_PARAMS sTDPowerParams; - if (RGX_IS_FEATURE_VALUE_SUPPORTED(psDevInfo, META) || - RGX_IS_FEATURE_SUPPORTED(psDevInfo, RISCV_FW_PROCESSOR)) +#if defined(RGX_FEATURE_META_MAX_VALUE_IDX) + if (RGX_IS_FEATURE_VALUE_SUPPORTED(psDevInfo, META)) { sTDPowerParams.sPCAddr = psDevInfo->sLayerParams.sPCAddr; } - else if (RGX_IS_FEATURE_SUPPORTED(psDevInfo, MIPS)) +#endif +#if defined(RGX_FEATURE_RISCV_FW_PROCESSOR_BIT_MASK) + if (RGX_IS_FEATURE_SUPPORTED(psDevInfo, RISCV_FW_PROCESSOR)) + { + sTDPowerParams.sPCAddr = psDevInfo->sLayerParams.sPCAddr; + } +#endif + if (RGX_IS_FEATURE_SUPPORTED(psDevInfo, MIPS)) { sTDPowerParams.sGPURegAddr = psDevInfo->sLayerParams.sGPURegAddr; sTDPowerParams.sBootRemapAddr = psDevInfo->sLayerParams.sBootRemapAddr; @@ -1105,11 +1108,13 @@ static PVRSRV_ERROR RGXSetPowerParams(PVRSRV_RGXDEV_INFO *psDevInfo, */ static IMG_BOOL RGXSystemHasFBCDCVersion31(PVRSRV_DEVICE_NODE *psDeviceNode) { - PVRSRV_RGXDEV_INFO *psDevInfo = psDeviceNode->pvDevice; #if defined(SUPPORT_VALIDATION) IMG_UINT32 ui32FBCDCVersionOverride = 0; #endif +#if defined(FIX_HW_ERN_66622_BIT_MASK) + PVRSRV_RGXDEV_INFO *psDevInfo = psDeviceNode->pvDevice; + if (RGX_IS_ERN_SUPPORTED(psDevInfo, 66622)) { #if defined(SUPPORT_VALIDATION) @@ -1140,6 +1145,7 @@ static IMG_BOOL RGXSystemHasFBCDCVersion31(PVRSRV_DEVICE_NODE *psDeviceNode) } } else +#endif { #if defined(SUPPORT_VALIDATION) @@ -1436,18 +1442,22 @@ PVRSRV_ERROR RGXInitDevPart2(PVRSRV_DEVICE_NODE *psDeviceNode, else { /* native and host drivers must clear the unique GPU physical interrupt */ - if (RGX_IS_FEATURE_VALUE_SUPPORTED(psDevInfo, META)) - { - psDevInfo->pfnRGXAckIrq = RGXAckIrqMETA; - } - else if (RGX_IS_FEATURE_SUPPORTED(psDevInfo, MIPS)) + if (RGX_IS_FEATURE_SUPPORTED(psDevInfo, MIPS)) { psDevInfo->pfnRGXAckIrq = RGXAckIrqMIPS; } +#if defined(RGX_FEATURE_META_MAX_VALUE_IDX) + else if (RGX_IS_FEATURE_VALUE_SUPPORTED(psDevInfo, META)) + { + psDevInfo->pfnRGXAckIrq = RGXAckIrqMETA; + } +#endif +#if defined(RGX_FEATURE_RISCV_FW_PROCESSOR_BIT_MASK) else if (RGX_IS_FEATURE_SUPPORTED(psDevInfo, RISCV_FW_PROCESSOR)) { psDevInfo->pfnRGXAckIrq = RGXAckIrqDedicated; } +#endif else { PVR_DPF((PVR_DBG_ERROR, "%s: GPU IRQ clearing mechanism not implemented " @@ -1510,7 +1520,9 @@ PVRSRV_ERROR RGXInitDevPart2(PVRSRV_DEVICE_NODE *psDeviceNode, } #endif +#if defined(RGX_FEATURE_COMPUTE_ONLY_BIT_MASK) if (!RGX_IS_FEATURE_SUPPORTED(psDevInfo, COMPUTE_ONLY)) +#endif { eError = PVRSRVTQLoadShaders(psDeviceNode); PVR_LOG_GOTO_IF_ERROR(eError, "PVRSRVTQLoadShaders", ErrorExit); @@ -1521,31 +1533,15 @@ PVRSRV_ERROR RGXInitDevPart2(PVRSRV_DEVICE_NODE *psDeviceNode, return PVRSRV_OK; ErrorExit: -#if !defined(NO_HARDWARE) - if (psDevInfo->pvLISRData != NULL) - { - (void) SysUninstallDeviceLISR(psDevInfo->pvLISRData); - } - if (psDevInfo->pvMISRData != NULL) - { - (void) OSUninstallMISR(psDevInfo->pvMISRData); - } - if (psDevInfo->hProcessQueuesMISR != NULL) - { - (void) OSUninstallMISR(psDevInfo->hProcessQueuesMISR); - } - if (psDevInfo->pvAPMISRData != NULL) - { - (void) OSUninstallMISR(psDevInfo->pvAPMISRData); - } -#endif /* !defined(NO_HARDWARE) */ + DevPart2DeInitRGX(psDeviceNode); return eError; } #define VZ_RGX_FW_FILENAME_SUFFIX ".vz" +#define RGX_64K_FW_FILENAME_SUFFIX ".64k" #define RGX_FW_FILENAME_MAX_SIZE ((sizeof(RGX_FW_FILENAME)+ \ - RGX_BVNC_STR_SIZE_MAX+sizeof(VZ_RGX_FW_FILENAME_SUFFIX))) + RGX_BVNC_STR_SIZE_MAX+sizeof(VZ_RGX_FW_FILENAME_SUFFIX) + sizeof(RGX_64K_FW_FILENAME_SUFFIX))) static void _GetFWFileName(PVRSRV_DEVICE_NODE *psDeviceNode, IMG_CHAR *pszFWFilenameStr, @@ -1555,19 +1551,24 @@ static void _GetFWFileName(PVRSRV_DEVICE_NODE *psDeviceNode, const IMG_CHAR * const pszFWFilenameSuffix = PVRSRV_VZ_MODE_IS(NATIVE) ? "" : VZ_RGX_FW_FILENAME_SUFFIX; + const IMG_CHAR * const pszFWFilenameSuffix2 = + ((OSGetPageSize() == RGX_MMU_PAGE_SIZE_64KB) && + RGX_IS_FEATURE_SUPPORTED(psDevInfo, MIPS)) + ? RGX_64K_FW_FILENAME_SUFFIX : ""; + OSSNPrintf(pszFWFilenameStr, RGX_FW_FILENAME_MAX_SIZE, - "%s." RGX_BVNC_STR_FMTSPEC "%s", + "%s." RGX_BVNC_STR_FMTSPEC "%s%s", RGX_FW_FILENAME, psDevInfo->sDevFeatureCfg.ui32B, psDevInfo->sDevFeatureCfg.ui32V, psDevInfo->sDevFeatureCfg.ui32N, psDevInfo->sDevFeatureCfg.ui32C, - pszFWFilenameSuffix); + pszFWFilenameSuffix, pszFWFilenameSuffix2); OSSNPrintf(pszFWpFilenameStr, RGX_FW_FILENAME_MAX_SIZE, - "%s." RGX_BVNC_STRP_FMTSPEC "%s", + "%s." RGX_BVNC_STRP_FMTSPEC "%s%s", RGX_FW_FILENAME, psDevInfo->sDevFeatureCfg.ui32B, psDevInfo->sDevFeatureCfg.ui32V, psDevInfo->sDevFeatureCfg.ui32N, psDevInfo->sDevFeatureCfg.ui32C, - pszFWFilenameSuffix); + pszFWFilenameSuffix, pszFWFilenameSuffix2); } PVRSRV_ERROR RGXLoadAndGetFWData(PVRSRV_DEVICE_NODE *psDeviceNode, @@ -1629,16 +1630,16 @@ PVRSRV_ERROR RGXInitCreateFWKernelMemoryContext(PVRSRV_DEVICE_NODE *psDeviceNode PVRSRV_ERROR eError; #if defined(SUPPORT_AUTOVZ) - MMU_PX_SETUP sDefaultPxSetup = psDeviceNode->sDevMMUPxSetup; + PHYS_HEAP *psDefaultPhysHeap = psDeviceNode->psMMUPhysHeap; if (PVRSRV_VZ_MODE_IS(HOST) && (!psDeviceNode->bAutoVzFwIsUp)) { - /* Temporarily swap the MMU Px methods and default LMA region of GPU physheap to - * allow the page tables of all memory mapped by the FwKernel context to be placed + /* Temporarily swap the MMU and default GPU physheap to allow the page + * tables of all memory mapped by the FwKernel context to be placed * in a dedicated memory carveout. This should allow the firmware mappings to * persist after a Host kernel crash or driver reset. */ - psDeviceNode->sDevMMUPxSetup = RGX_FW_MMU_RESERVED_MEM_SETUP(psDeviceNode); + psDeviceNode->psMMUPhysHeap = psDeviceNode->psFwMMUReservedPhysHeap; } #endif @@ -1725,7 +1726,7 @@ PVRSRV_ERROR RGXInitCreateFWKernelMemoryContext(PVRSRV_DEVICE_NODE *psDeviceNode #if defined(SUPPORT_AUTOVZ) /* restore default Px setup */ - psDeviceNode->sDevMMUPxSetup = sDefaultPxSetup; + psDeviceNode->psMMUPhysHeap = psDefaultPhysHeap; #endif } #else @@ -1766,9 +1767,9 @@ void RGXDeInitDestroyFWKernelMemoryContext(PVRSRV_DEVICE_NODE *psDeviceNode) if (PVRSRV_VZ_MODE_IS(HOST)) { #if defined(SUPPORT_AUTOVZ) - MMU_PX_SETUP sDefaultPxSetup = psDeviceNode->sDevMMUPxSetup; + PHYS_HEAP *psDefaultPhysHeap = psDeviceNode->psMMUPhysHeap; - psDeviceNode->sDevMMUPxSetup = RGX_FW_MMU_RESERVED_MEM_SETUP(psDeviceNode); + psDeviceNode->psMMUPhysHeap = psDeviceNode->psFwMMUReservedPhysHeap; if (!psDeviceNode->bAutoVzFwIsUp) #endif @@ -1781,7 +1782,7 @@ void RGXDeInitDestroyFWKernelMemoryContext(PVRSRV_DEVICE_NODE *psDeviceNode) } } #if defined(SUPPORT_AUTOVZ) - psDeviceNode->sDevMMUPxSetup = sDefaultPxSetup; + psDeviceNode->psMMUPhysHeap = psDefaultPhysHeap; #endif } #else @@ -2302,11 +2303,12 @@ static PVRSRV_ERROR RGXDevInitCompatCheck_BVNC_HWAgainstDriver(PVRSRV_RGXDEV_INF psDevInfo->sDevFeatureCfg.ui32N, psDevInfo->sDevFeatureCfg.ui32C); +#if defined(FIX_HW_BRN_38344_BIT_MASK) if (RGX_IS_BRN_SUPPORTED(psDevInfo, 38344) && (psDevInfo->sDevFeatureCfg.ui32C >= 10)) { ui64MaskBVNC &= ~RGX_BVNC_PACK_MASK_C; } - +#endif if (ui64MaskBVNC != (RGX_BVNC_PACK_MASK_B | RGX_BVNC_PACK_MASK_V | RGX_BVNC_PACK_MASK_N | RGX_BVNC_PACK_MASK_C)) { PVR_LOG(("Compatibility checks: Ignoring fields: '%s%s%s%s' of HW BVNC.", @@ -2489,7 +2491,9 @@ static PVRSRV_ERROR RGXDevInitCompatCheck_FWProcessorVersion_AgainstDriver(PVRSR ui32FWCoreIDValue = RGXMIPSFW_CORE_ID_VALUE; pcRGXFW_PROCESSOR = RGXFW_PROCESSOR_MIPS; } - else if (RGX_IS_FEATURE_VALUE_SUPPORTED(psDevInfo, META)) + else +#if defined(RGX_FEATURE_META_MAX_VALUE_IDX) + if (RGX_IS_FEATURE_VALUE_SUPPORTED(psDevInfo, META)) { switch (RGX_GET_FEATURE_VALUE(psDevInfo, META)) { @@ -2503,12 +2507,16 @@ static PVRSRV_ERROR RGXDevInitCompatCheck_FWProcessorVersion_AgainstDriver(PVRSR } pcRGXFW_PROCESSOR = RGXFW_PROCESSOR_META; } - else if (RGX_IS_FEATURE_SUPPORTED(psDevInfo, RISCV_FW_PROCESSOR)) + else +#endif +#if defined(RGX_FEATURE_RISCV_FW_PROCESSOR_BIT_MASK) + if (RGX_IS_FEATURE_SUPPORTED(psDevInfo, RISCV_FW_PROCESSOR)) { ui32FWCoreIDValue = RGXRISCVFW_CORE_ID_VALUE; pcRGXFW_PROCESSOR = RGXFW_PROCESSOR_RISCV; } else +#endif { PVR_DPF((PVR_DBG_ERROR, "%s: Undefined FW_CORE_ID_VALUE", __func__)); PVR_ASSERT(0); @@ -2597,10 +2605,11 @@ static PVRSRV_ERROR RGXDevInitCompatCheck(PVRSRV_DEVICE_NODE *psDeviceNode) ui32RegValue = 0; +#if defined(RGX_FEATURE_META_MAX_VALUE_IDX) if ((!PVRSRV_VZ_MODE_IS(GUEST)) && RGX_IS_FEATURE_VALUE_SUPPORTED(psDevInfo, META)) { - eError = RGXReadMETAAddr(psDevInfo, META_CR_T0ENABLE_OFFSET, &ui32RegValue); + eError = RGXReadFWModuleAddr(psDevInfo, META_CR_T0ENABLE_OFFSET, &ui32RegValue); if (eError != PVRSRV_OK) { @@ -2618,6 +2627,7 @@ static PVRSRV_ERROR RGXDevInitCompatCheck(PVRSRV_DEVICE_NODE *psDeviceNode) goto chk_exit; } } +#endif if (!*((volatile IMG_BOOL *)&psDevInfo->psRGXFWIfOsInit->sRGXCompChecks.bUpdated)) { @@ -2712,19 +2722,23 @@ static PVRSRV_ERROR RGXSoftReset(PVRSRV_DEVICE_NODE *psDeviceNode, /* the device info */ psDevInfo = psDeviceNode->pvDevice; +#if defined(RGX_CR_SOFT_RESET__PBE2_XE__MASKFULL) if (RGX_IS_FEATURE_SUPPORTED(psDevInfo, PBE2_IN_XE)) { ui64SoftResetMask = RGX_CR_SOFT_RESET__PBE2_XE__MASKFULL; }else +#endif { ui64SoftResetMask = RGX_CR_SOFT_RESET_MASKFULL; } +#if defined(RGX_CR_SOFT_RESET2_MASKFULL) if ((RGX_IS_FEATURE_SUPPORTED(psDevInfo, S7_TOP_INFRASTRUCTURE)) && ((ui64ResetValue2 & RGX_CR_SOFT_RESET2_MASKFULL) != ui64ResetValue2)) { bSoftReset = IMG_TRUE; } +#endif if (((ui64ResetValue1 & ui64SoftResetMask) != ui64ResetValue1) || bSoftReset) { @@ -2734,32 +2748,39 @@ static PVRSRV_ERROR RGXSoftReset(PVRSRV_DEVICE_NODE *psDeviceNode, /* Set in soft-reset */ OSWriteHWReg64(psDevInfo->pvRegsBaseKM, RGX_CR_SOFT_RESET, ui64ResetValue1); +#if defined(RGX_FEATURE_S7_TOP_INFRASTRUCTURE_BIT_MASK) if (RGX_IS_FEATURE_SUPPORTED(psDevInfo, S7_TOP_INFRASTRUCTURE)) { OSWriteHWReg64(psDevInfo->pvRegsBaseKM, RGX_CR_SOFT_RESET2, ui64ResetValue2); } - +#endif /* Read soft-reset to fence previous write in order to clear the SOCIF pipeline */ (void) OSReadHWReg64(psDevInfo->pvRegsBaseKM, RGX_CR_SOFT_RESET); +#if defined(RGX_FEATURE_S7_TOP_INFRASTRUCTURE_BIT_MASK) if (RGX_IS_FEATURE_SUPPORTED(psDevInfo, S7_TOP_INFRASTRUCTURE)) { (void) OSReadHWReg64(psDevInfo->pvRegsBaseKM, RGX_CR_SOFT_RESET2); } +#endif /* Take the modules out of reset... */ OSWriteHWReg64(psDevInfo->pvRegsBaseKM, RGX_CR_SOFT_RESET, 0); +#if defined(RGX_FEATURE_S7_TOP_INFRASTRUCTURE_BIT_MASK) if (RGX_IS_FEATURE_SUPPORTED(psDevInfo, S7_TOP_INFRASTRUCTURE)) { OSWriteHWReg64(psDevInfo->pvRegsBaseKM, RGX_CR_SOFT_RESET2, 0); } +#endif /* ...and fence again */ (void) OSReadHWReg64(psDevInfo->pvRegsBaseKM, RGX_CR_SOFT_RESET); +#if defined(RGX_FEATURE_S7_TOP_INFRASTRUCTURE_BIT_MASK) if (RGX_IS_FEATURE_SUPPORTED(psDevInfo, S7_TOP_INFRASTRUCTURE)) { (void) OSReadHWReg64(psDevInfo->pvRegsBaseKM, RGX_CR_SOFT_RESET2); } +#endif return PVRSRV_OK; } @@ -3255,6 +3276,7 @@ PVRSRV_ERROR RGXFWTraceSetLogType(const PVRSRV_DEVICE_NODE *psDeviceNode, return eResult; } +#if defined(DEBUG) static PVRSRV_ERROR RGXQueryFWPoisonOnFree(const PVRSRV_DEVICE_NODE *psDeviceNode, const void *psPrivate, @@ -3280,6 +3302,7 @@ PVRSRV_ERROR RGXSetFWPoisonOnFree(const PVRSRV_DEVICE_NODE *psDeviceNode, return PVRSRV_OK; } +#endif /* * RGXInitFirmware @@ -3304,10 +3327,12 @@ RGXInitFirmware(PVRSRV_DEVICE_NODE *psDeviceNode, IMG_UINT32 ui32FwOsCfgFlags) { PVRSRV_ERROR eError; + PVRSRV_RGXDEV_INFO *psDevInfo = (PVRSRV_RGXDEV_INFO *)psDeviceNode->pvDevice; +#if defined(DEBUG) void *pvAppHintState = NULL; IMG_UINT32 ui32AppHintDefault; - PVRSRV_RGXDEV_INFO *psDevInfo = (PVRSRV_RGXDEV_INFO *)psDeviceNode->pvDevice; IMG_BOOL bEnableFWPoisonOnFree = IMG_FALSE; +#endif eError = RGXSetupFirmware(psDeviceNode, bEnableSignatureChecks, @@ -3348,6 +3373,7 @@ RGXInitFirmware(PVRSRV_DEVICE_NODE *psDeviceNode, NULL); } +#if defined(DEBUG) OSCreateKMAppHintState(&pvAppHintState); ui32AppHintDefault = PVRSRV_APPHINT_ENABLEFWPOISONONFREE; @@ -3368,6 +3394,9 @@ RGXInitFirmware(PVRSRV_DEVICE_NODE *psDeviceNode, psDevInfo->uiFWPoisonOnFreeFlag = bEnableFWPoisonOnFree ? PVRSRV_MEMALLOCFLAG_POISON_ON_FREE : 0ULL; +#else + psDevInfo->uiFWPoisonOnFreeFlag = 0ULL; +#endif psDevInfo->ui32ClockSource = PVRSRV_APPHINT_TIMECORRCLOCK; psDevInfo->ui32LastClockSource = PVRSRV_APPHINT_TIMECORRCLOCK; @@ -3512,6 +3541,101 @@ static void RGXFreeUFOBlock(PVRSRV_DEVICE_NODE *psDeviceNode, DevmemFwUnmapAndFree(psDevInfo, psMemDesc); } +static void DevPart2DeInitRGX(PVRSRV_DEVICE_NODE *psDeviceNode) +{ + PVRSRV_RGXDEV_INFO *psDevInfo = (PVRSRV_RGXDEV_INFO*)psDeviceNode->pvDevice; + + psDevInfo->bDevInit2Done = IMG_FALSE; + +#if defined(RGX_FEATURE_COMPUTE_ONLY_BIT_MASK) + if (!RGX_IS_FEATURE_SUPPORTED(psDevInfo, COMPUTE_ONLY)) +#endif + { + if ((psDevInfo->hTQUSCSharedMem != NULL) && + (psDevInfo->hTQCLISharedMem != NULL)) + { + PVRSRVTQUnloadShaders(psDeviceNode); + } + } + +#if !defined(NO_HARDWARE) + if (psDevInfo->pvLISRData != NULL) + { + (void) SysUninstallDeviceLISR(psDevInfo->pvLISRData); + } + if (psDevInfo->pvMISRData != NULL) + { + (void) OSUninstallMISR(psDevInfo->pvMISRData); + } + if (psDevInfo->hProcessQueuesMISR != NULL) + { + (void) OSUninstallMISR(psDevInfo->hProcessQueuesMISR); + } + if (psDevInfo->pvAPMISRData != NULL) + { + (void) OSUninstallMISR(psDevInfo->pvAPMISRData); + } + if (psDeviceNode->hCmdCompNotify != NULL) + { + /* Cancel notifications to this device */ + PVRSRVUnregisterCmdCompleteNotify(psDeviceNode->hCmdCompNotify); + psDeviceNode->hCmdCompNotify = NULL; + } +#endif /* !NO_HARDWARE */ + + /* Remove the device from the power manager */ + PVRSRVRemovePowerDevice(psDeviceNode); + + psDevInfo->pfnGetGpuUtilStats = NULL; + if (psDevInfo->hGPUUtilLock != NULL) + { + OSLockDestroy(psDevInfo->hGPUUtilLock); + } + + if (RGX_IS_FEATURE_SUPPORTED(psDevInfo, MIPS) && + (psDevInfo->hNMILock != NULL)) + { + OSLockDestroy(psDevInfo->hNMILock); + } + + if ((GetInfoPageDebugFlagsKM() & DEBUG_FEATURE_PAGE_FAULT_DEBUG_ENABLED) && + (psDevInfo->hMMUCtxUnregLock != NULL)) + { + OSLockDestroy(psDevInfo->hMMUCtxUnregLock); + } + + if (psDevInfo->hDebugFaultInfoLock != NULL) + { + OSLockDestroy(psDevInfo->hDebugFaultInfoLock); + } + + /* De-init Freelists/ZBuffers... */ + if (psDevInfo->hLockFreeList != NULL) + { + OSLockDestroy(psDevInfo->hLockFreeList); + } + + if (psDevInfo->hLockZSBuffer != NULL) + { + OSLockDestroy(psDevInfo->hLockZSBuffer); + } + +#if defined(SUPPORT_WORKLOAD_ESTIMATION) + /* De-init work estimation lock */ + if (psDevInfo->hWorkEstLock != NULL) + { + OSLockDestroy(psDevInfo->hWorkEstLock); + } +#endif + + /* Free DVFS Table */ + if (psDevInfo->psGpuDVFSTable != NULL) + { + OSFreeMem(psDevInfo->psGpuDVFSTable); + psDevInfo->psGpuDVFSTable = NULL; + } +} + /* DevDeInitRGX */ @@ -3534,8 +3658,7 @@ PVRSRV_ERROR DevDeInitRGX(PVRSRV_DEVICE_NODE *psDeviceNode) KM_SET_OS_CONNECTION(OFFLINE, psDevInfo); } - eError = DeviceDepBridgeDeInit(psDevInfo); - PVR_LOG_IF_ERROR(eError, "DeviceDepBridgeDeInit"); + DeviceDepBridgeDeInit(psDevInfo); #if defined(PDUMP) DevmemIntFreeDefBackingPage(psDeviceNode, @@ -3606,82 +3729,30 @@ PVRSRV_ERROR DevDeInitRGX(PVRSRV_DEVICE_NODE *psDeviceNode) RGXDebugDeinit(psDevInfo); - /* - * De-initialise in reverse order, so stage 2 init is undone first. - */ + /* De-initialise in reverse order, so stage 2 init is undone first. */ if (psDevInfo->bDevInit2Done) { - psDevInfo->bDevInit2Done = IMG_FALSE; + DevPart2DeInitRGX(psDeviceNode); + } - if (!RGX_IS_FEATURE_SUPPORTED(psDevInfo, COMPUTE_ONLY)) - { - eError = PVRSRVTQUnloadShaders(psDeviceNode); - if (eError != PVRSRV_OK) - { - return eError; - } - } - -#if !defined(NO_HARDWARE) - (void) SysUninstallDeviceLISR(psDevInfo->pvLISRData); - (void) OSUninstallMISR(psDevInfo->pvMISRData); - /* Cancel notifications to this device */ - PVRSRVUnregisterCmdCompleteNotify(psDeviceNode->hCmdCompNotify); - psDeviceNode->hCmdCompNotify = NULL; - (void) OSUninstallMISR(psDevInfo->hProcessQueuesMISR); - if (psDevInfo->pvAPMISRData != NULL) - { - (void) OSUninstallMISR(psDevInfo->pvAPMISRData); - } -#endif /* !NO_HARDWARE */ - - /* Remove the device from the power manager */ - eError = PVRSRVRemovePowerDevice(psDeviceNode); - if (eError != PVRSRV_OK) - { - return eError; - } - - psDevInfo->pfnGetGpuUtilStats = NULL; - OSLockDestroy(psDevInfo->hGPUUtilLock); - - /* Free DVFS Table */ - if (psDevInfo->psGpuDVFSTable != NULL) - { - OSFreeMem(psDevInfo->psGpuDVFSTable); - psDevInfo->psGpuDVFSTable = NULL; - } - - /* De-init Freelists/ZBuffers... */ - OSLockDestroy(psDevInfo->hLockFreeList); - OSLockDestroy(psDevInfo->hLockZSBuffer); - -#if defined(SUPPORT_WORKLOAD_ESTIMATION) - /* De-init work estimation lock */ - OSLockDestroy(psDevInfo->hWorkEstLock); -#endif + /* Unregister MMU related stuff */ + eError = RGXMMUInit_Unregister(psDeviceNode); + if (eError != PVRSRV_OK) + { + PVR_DPF((PVR_DBG_ERROR, + "DevDeInitRGX: Failed RGXMMUInit_Unregister (0x%x)", + eError)); + } + if (RGX_IS_FEATURE_SUPPORTED(psDevInfo, MIPS)) + { /* Unregister MMU related stuff */ - eError = RGXMMUInit_Unregister(psDeviceNode); + eError = RGXMipsMMUInit_Unregister(psDeviceNode); if (eError != PVRSRV_OK) { PVR_DPF((PVR_DBG_ERROR, - "DevDeInitRGX: Failed RGXMMUInit_Unregister (0x%x)", + "DevDeInitRGX: Failed RGXMipsMMUInit_Unregister (0x%x)", eError)); - return eError; - } - - if (RGX_IS_FEATURE_SUPPORTED(psDevInfo, MIPS)) - { - /* Unregister MMU related stuff */ - eError = RGXMipsMMUInit_Unregister(psDeviceNode); - if (eError != PVRSRV_OK) - { - PVR_DPF((PVR_DBG_ERROR, - "DevDeInitRGX: Failed RGXMipsMMUInit_Unregister (0x%x)", - eError)); - return eError; - } } } @@ -3798,24 +3869,6 @@ PVRSRV_ERROR DevDeInitRGX(PVRSRV_DEVICE_NODE *psDeviceNode) OSSpinLockDestroy(psDevInfo->hLockKCCBDeferredCommandsList); OSWRLockDestroy(psDevInfo->hCommonCtxtListLock); - if ((psDevInfo->hNMILock != NULL) && (RGX_IS_FEATURE_SUPPORTED(psDevInfo, MIPS))) - { - OSLockDestroy(psDevInfo->hNMILock); - } - - if (psDevInfo->hDebugFaultInfoLock != NULL) - { - OSLockDestroy(psDevInfo->hDebugFaultInfoLock); - } - - if (GetInfoPageDebugFlagsKM() & DEBUG_FEATURE_PAGE_FAULT_DEBUG_ENABLED) - { - if (psDevInfo->hMMUCtxUnregLock != NULL) - { - OSLockDestroy(psDevInfo->hMMUCtxUnregLock); - } - } - /* Free device BVNC string */ if (NULL != psDevInfo->sDevFeatureCfg.pszBVNCString) { @@ -3920,6 +3973,7 @@ struct RGX_HEAP_INFO_TAG static IMG_BOOL BRN65273IsPresent(PVRSRV_RGXDEV_INFO *psDevInfo, const RGX_HEAP_INFO *pksHeapInfo) { +#if defined(FIX_HW_BRN_65273_BIT_MASK) if (RGX_IS_BRN_SUPPORTED(psDevInfo, 65273)) { return (((pksHeapInfo->ui32HeapInstanceFlags & HEAP_INST_VALUE_MASK) == HEAP_INST_BRN_ALT_VALUE) || @@ -3927,6 +3981,9 @@ static IMG_BOOL BRN65273IsPresent(PVRSRV_RGXDEV_INFO *psDevInfo, const RGX_HEAP_ IMG_TRUE : IMG_FALSE; } else +#else + PVR_UNREFERENCED_PARAMETER(psDevInfo); +#endif { return ((pksHeapInfo->ui32HeapInstanceFlags & HEAP_INST_VALUE_MASK) == HEAP_INST_DEFAULT_VALUE) ? IMG_TRUE : IMG_FALSE; } @@ -3936,6 +3993,7 @@ static IMG_BOOL BRN63142IsPresent(PVRSRV_RGXDEV_INFO *psDevInfo, const RGX_HEAP_ { PVR_UNREFERENCED_PARAMETER(pksHeapInfo); +#if defined(FIX_HW_BRN_63142_BIT_MASK) if (RGX_IS_BRN_SUPPORTED(psDevInfo, 63142)) { PVR_ASSERT((pksHeapInfo->ui64HeapBase & IMG_UINT64_C(0x3FFFFFFFF)) + @@ -3943,16 +4001,35 @@ static IMG_BOOL BRN63142IsPresent(PVRSRV_RGXDEV_INFO *psDevInfo, const RGX_HEAP_ return IMG_TRUE; } +#else + PVR_UNREFERENCED_PARAMETER(psDevInfo); +#endif return IMG_FALSE; } -static IMG_BOOL ArchIsOceanicCore(PVRSRV_RGXDEV_INFO *psDevInfo, const RGX_HEAP_INFO *pksHeapInfo) +static IMG_BOOL FBCDescriptorIsPresent(PVRSRV_RGXDEV_INFO *psDevInfo, const RGX_HEAP_INFO *pksHeapInfo) { PVR_UNREFERENCED_PARAMETER(pksHeapInfo); - PVR_UNREFERENCED_PARAMETER(psDevInfo); - return IMG_TRUE; + if (RGX_GET_FEATURE_VALUE(psDevInfo, FBC_MAX_DEFAULT_DESCRIPTORS)) + { + return IMG_TRUE; + } + + return IMG_FALSE; +} + +static IMG_BOOL FBCLargeDescriptorIsPresent(PVRSRV_RGXDEV_INFO *psDevInfo, const RGX_HEAP_INFO *pksHeapInfo) +{ + PVR_UNREFERENCED_PARAMETER(pksHeapInfo); + + if (RGX_GET_FEATURE_VALUE(psDevInfo, FBC_MAX_LARGE_DESCRIPTORS)) + { + return IMG_TRUE; + } + + return IMG_FALSE; } static IMG_BOOL TextureStateIsPresent(PVRSRV_RGXDEV_INFO *psDevInfo, const RGX_HEAP_INFO *pksHeapInfo) @@ -3973,63 +4050,47 @@ static IMG_BOOL SignalSnoopingIsPresent(PVRSRV_RGXDEV_INFO *psDevInfo, const RGX { PVR_UNREFERENCED_PARAMETER(pksHeapInfo); +#if defined(RGX_FEATURE_SIGNAL_SNOOPING_BIT_MASK) if (RGX_IS_FEATURE_SUPPORTED(psDevInfo, SIGNAL_SNOOPING)) { return IMG_TRUE; } +#else + PVR_UNREFERENCED_PARAMETER(psDevInfo); +#endif return IMG_FALSE; } -/* FW Feature Present function prototypes */ - static IMG_BOOL FWBRN65101IsPresent(PVRSRV_RGXDEV_INFO *psDevInfo, const RGX_HEAP_INFO *pksHeapInfo) { /* Used to determine the correct table row to instantiate as a heap by checking * the Heap size and base at run time VS the current table instance */ - IMG_UINT64 ui64FWCPUTypeAndBRN; - IMG_UINT64 ui64VZTypeBase; + IMG_UINT64 ui64MainSubHeapSize; - /* Check if the FW CPU is of MIPS type, if not then assume META for now */ - if (RGX_IS_FEATURE_SUPPORTED(psDevInfo, MIPS)) + /* MIPS Firmware must reserve some space in its Host/Native heap for GPU memory mappings */ + if (RGX_IS_FEATURE_SUPPORTED(psDevInfo, MIPS) && (!PVRSRV_VZ_MODE_IS(GUEST))) { +#if defined(FIX_HW_BRN_65101_BIT_MASK) if (RGX_IS_BRN_SUPPORTED(psDevInfo, 65101)) { - ui64FWCPUTypeAndBRN = RGX_FIRMWARE_MIPS_MAIN_HEAP_SIZE_BRN65101; + ui64MainSubHeapSize = RGX_FIRMWARE_HOST_MIPS_MAIN_HEAP_SIZE_BRN65101; } else +#endif { - ui64FWCPUTypeAndBRN = RGX_FIRMWARE_MIPS_MAIN_HEAP_SIZE_NORMAL; + ui64MainSubHeapSize = RGX_FIRMWARE_HOST_MIPS_MAIN_HEAP_SIZE_NORMAL; } } else { - ui64FWCPUTypeAndBRN = RGX_FIRMWARE_META_MAIN_HEAP_SIZE; - } - - /* Check if the FW CPU is RISC-V, if not then we have determined by elimination - * that the FW type is META - */ - if (RGX_IS_FEATURE_SUPPORTED(psDevInfo, RISCV_FW_PROCESSOR)) - { - /* We currently use the META config in this case */ - ui64FWCPUTypeAndBRN = RGX_FIRMWARE_META_MAIN_HEAP_SIZE; - } - - /* Check VZ Type */ - if (PVRSRV_VZ_MODE_IS(GUEST)) - { - ui64VZTypeBase = RGX_FIRMWARE_GUEST_MAIN_HEAP_BASE; - } - else - { - ui64VZTypeBase = RGX_FIRMWARE_HOST_MAIN_HEAP_BASE; + ui64MainSubHeapSize = RGX_FIRMWARE_DEFAULT_MAIN_HEAP_SIZE; } /* Determine if we should include this entry based upon previous checks */ - return (pksHeapInfo->uiHeapLength == ui64FWCPUTypeAndBRN && - pksHeapInfo->ui64HeapBase == ui64VZTypeBase) ? + return (pksHeapInfo->uiHeapLength == ui64MainSubHeapSize && + pksHeapInfo->ui64HeapBase == RGX_FIRMWARE_MAIN_HEAP_BASE) ? IMG_TRUE : IMG_FALSE; } @@ -4038,62 +4099,48 @@ static IMG_BOOL FWVZConfigPresent(PVRSRV_RGXDEV_INFO* psDevInfo, const RGX_HEAP_ /* Used to determine the correct table row to instantiate as a heap by checking * the Heap base at run time VS the current table instance */ - IMG_UINT64 ui64VZTypeBase; - - /* Check VZ Type */ - if (PVRSRV_VZ_MODE_IS(GUEST)) - { - ui64VZTypeBase = RGX_FIRMWARE_GUEST_CONFIG_HEAP_BASE; - } - else - { - ui64VZTypeBase = RGX_FIRMWARE_HOST_CONFIG_HEAP_BASE; - } /* Determine if we should include this entry based upon previous checks */ - return (pksHeapInfo->ui64HeapBase == ui64VZTypeBase) ? IMG_TRUE : IMG_FALSE; + return (pksHeapInfo->ui64HeapBase == RGX_FIRMWARE_CONFIG_HEAP_BASE) ? IMG_TRUE : IMG_FALSE; } /* Blueprint array. note: not all heaps are available to clients*/ static const RGX_HEAP_INFO gasRGXHeapLayoutApp[] = { - /* Name HeapBase HeapLength HeapReservedRegionLength Log2ImportAlignment pfnPresent HeapInstanceFlags */ - {RGX_GENERAL_SVM_HEAP_IDENT, RGX_GENERAL_SVM_HEAP_BASE, RGX_GENERAL_SVM_HEAP_SIZE, 0, 0, NULL, HEAP_INST_DEFAULT_VALUE }, - {RGX_GENERAL_HEAP_IDENT, RGX_GENERAL_HEAP_BASE, RGX_GENERAL_HEAP_SIZE, (1 * DEVMEM_HEAP_RESERVED_SIZE_GRANULARITY), 0, BRN65273IsPresent, HEAP_INST_DEFAULT_VALUE }, - {RGX_GENERAL_HEAP_IDENT, RGX_GENERAL_BRN_65273_HEAP_BASE, RGX_GENERAL_BRN_65273_HEAP_SIZE, (1 * DEVMEM_HEAP_RESERVED_SIZE_GRANULARITY), 0, BRN65273IsPresent, HEAP_INST_BRN_ALT_VALUE }, - {RGX_GENERAL_NON4K_HEAP_IDENT, RGX_GENERAL_NON4K_HEAP_BASE, RGX_GENERAL_NON4K_HEAP_SIZE, 0, 0, BRN65273IsPresent, HEAP_INST_DEFAULT_VALUE | HEAP_INST_NON4K_FLAG }, - {RGX_GENERAL_NON4K_HEAP_IDENT, RGX_GENERAL_NON4K_BRN_65273_HEAP_BASE, RGX_GENERAL_NON4K_BRN_65273_HEAP_SIZE, 0, 0, BRN65273IsPresent, HEAP_INST_BRN_ALT_VALUE | HEAP_INST_NON4K_FLAG }, - {RGX_PDSCODEDATA_HEAP_IDENT, RGX_PDSCODEDATA_HEAP_BASE, RGX_PDSCODEDATA_HEAP_SIZE, (1 * DEVMEM_HEAP_RESERVED_SIZE_GRANULARITY), 0, BRN65273IsPresent, HEAP_INST_DEFAULT_VALUE }, - {RGX_PDSCODEDATA_HEAP_IDENT, RGX_PDSCODEDATA_BRN_65273_HEAP_BASE, RGX_PDSCODEDATA_BRN_65273_HEAP_SIZE, (1 * DEVMEM_HEAP_RESERVED_SIZE_GRANULARITY), 0, BRN65273IsPresent, HEAP_INST_BRN_ALT_VALUE }, - {RGX_RGNHDR_BRN_63142_HEAP_IDENT, RGX_RGNHDR_BRN_63142_HEAP_BASE, RGX_RGNHDR_BRN_63142_HEAP_SIZE, 0, 0, BRN63142IsPresent, HEAP_INST_BRN_DEP_VALUE }, - {RGX_USCCODE_HEAP_IDENT, RGX_USCCODE_HEAP_BASE, RGX_USCCODE_HEAP_SIZE, (1 * DEVMEM_HEAP_RESERVED_SIZE_GRANULARITY), 0, BRN65273IsPresent, HEAP_INST_DEFAULT_VALUE }, - {RGX_USCCODE_HEAP_IDENT, RGX_USCCODE_BRN_65273_HEAP_BASE, RGX_USCCODE_BRN_65273_HEAP_SIZE, (1 * DEVMEM_HEAP_RESERVED_SIZE_GRANULARITY), 0, BRN65273IsPresent, HEAP_INST_BRN_ALT_VALUE }, - {RGX_TQ3DPARAMETERS_HEAP_IDENT, RGX_TQ3DPARAMETERS_HEAP_BASE, RGX_TQ3DPARAMETERS_HEAP_SIZE, 0, 0, BRN65273IsPresent, HEAP_INST_DEFAULT_VALUE }, - {RGX_TQ3DPARAMETERS_HEAP_IDENT, RGX_TQ3DPARAMETERS_BRN_65273_HEAP_BASE, RGX_TQ3DPARAMETERS_BRN_65273_HEAP_SIZE, 0, 0, BRN65273IsPresent, HEAP_INST_BRN_ALT_VALUE }, - {RGX_VK_CAPT_REPLAY_HEAP_IDENT, RGX_VK_CAPT_REPLAY_HEAP_BASE, RGX_VK_CAPT_REPLAY_HEAP_SIZE, 0, 0, NULL, HEAP_INST_DEFAULT_VALUE }, - {RGX_SIGNALS_HEAP_IDENT, RGX_SIGNALS_HEAP_BASE, RGX_SIGNALS_HEAP_SIZE, 0, 0, SignalSnoopingIsPresent, HEAP_INST_FEAT_DEP_VALUE}, - {RGX_FBCDC_HEAP_IDENT, RGX_FBCDC_HEAP_BASE, RGX_FBCDC_HEAP_SIZE, 0, 0, ArchIsOceanicCore, HEAP_INST_FEAT_DEP_VALUE}, - {RGX_CMP_MISSION_RMW_HEAP_IDENT, RGX_CMP_MISSION_RMW_HEAP_BASE, RGX_CMP_MISSION_RMW_HEAP_SIZE, 0, 0, NULL, HEAP_INST_DEFAULT_VALUE }, - {RGX_CMP_SAFETY_RMW_HEAP_IDENT, RGX_CMP_SAFETY_RMW_HEAP_BASE, RGX_CMP_SAFETY_RMW_HEAP_SIZE, 0, 0, NULL, HEAP_INST_DEFAULT_VALUE }, - {RGX_TEXTURE_STATE_HEAP_IDENT, RGX_TEXTURE_STATE_HEAP_BASE, RGX_TEXTURE_STATE_HEAP_SIZE, 0, 0, TextureStateIsPresent, HEAP_INST_FEAT_DEP_VALUE}, - {RGX_VISIBILITY_TEST_HEAP_IDENT, RGX_VISIBILITY_TEST_HEAP_BASE, RGX_VISIBILITY_TEST_HEAP_SIZE, 0, 0, BRN65273IsPresent, HEAP_INST_DEFAULT_VALUE }, - {RGX_VISIBILITY_TEST_HEAP_IDENT, RGX_VISIBILITY_TEST_BRN_65273_HEAP_BASE, RGX_VISIBILITY_TEST_BRN_65273_HEAP_SIZE, 0, 0, BRN65273IsPresent, HEAP_INST_BRN_ALT_VALUE }, - {RGX_MMU_INIA_BRN_65273_HEAP_IDENT, RGX_MMU_INIA_BRN_65273_HEAP_BASE, RGX_MMU_INIA_BRN_65273_HEAP_SIZE, 0, 0, BRN65273IsPresent, HEAP_INST_BRN_DEP_VALUE }, - {RGX_MMU_INIB_BRN_65273_HEAP_IDENT, RGX_MMU_INIB_BRN_65273_HEAP_BASE, RGX_MMU_INIB_BRN_65273_HEAP_SIZE, 0, 0, BRN65273IsPresent, HEAP_INST_BRN_DEP_VALUE } + /* Name HeapBase HeapLength HeapReservedRegionLength Log2ImportAlignment pfnPresent HeapInstanceFlags */ + {RGX_GENERAL_SVM_HEAP_IDENT, RGX_GENERAL_SVM_HEAP_BASE, RGX_GENERAL_SVM_HEAP_SIZE, 0, 0, NULL, HEAP_INST_DEFAULT_VALUE }, + {RGX_GENERAL_HEAP_IDENT, RGX_GENERAL_HEAP_BASE, RGX_GENERAL_HEAP_SIZE, (1 * DEVMEM_HEAP_RESERVED_SIZE_GRANULARITY), 0, BRN65273IsPresent, HEAP_INST_DEFAULT_VALUE }, + {RGX_GENERAL_HEAP_IDENT, RGX_GENERAL_BRN_65273_HEAP_BASE, RGX_GENERAL_BRN_65273_HEAP_SIZE, (1 * DEVMEM_HEAP_RESERVED_SIZE_GRANULARITY), 0, BRN65273IsPresent, HEAP_INST_BRN_ALT_VALUE }, + {RGX_GENERAL_NON4K_HEAP_IDENT, RGX_GENERAL_NON4K_HEAP_BASE, RGX_GENERAL_NON4K_HEAP_SIZE, 0, 0, BRN65273IsPresent, HEAP_INST_DEFAULT_VALUE | HEAP_INST_NON4K_FLAG }, + {RGX_GENERAL_NON4K_HEAP_IDENT, RGX_GENERAL_NON4K_BRN_65273_HEAP_BASE, RGX_GENERAL_NON4K_BRN_65273_HEAP_SIZE, 0, 0, BRN65273IsPresent, HEAP_INST_BRN_ALT_VALUE | HEAP_INST_NON4K_FLAG }, + {RGX_PDSCODEDATA_HEAP_IDENT, RGX_PDSCODEDATA_HEAP_BASE, RGX_PDSCODEDATA_HEAP_SIZE, (1 * DEVMEM_HEAP_RESERVED_SIZE_GRANULARITY), 0, BRN65273IsPresent, HEAP_INST_DEFAULT_VALUE }, + {RGX_PDSCODEDATA_HEAP_IDENT, RGX_PDSCODEDATA_BRN_65273_HEAP_BASE, RGX_PDSCODEDATA_BRN_65273_HEAP_SIZE, (1 * DEVMEM_HEAP_RESERVED_SIZE_GRANULARITY), 0, BRN65273IsPresent, HEAP_INST_BRN_ALT_VALUE }, + {RGX_RGNHDR_BRN_63142_HEAP_IDENT, RGX_RGNHDR_BRN_63142_HEAP_BASE, RGX_RGNHDR_BRN_63142_HEAP_SIZE, 0, 0, BRN63142IsPresent, HEAP_INST_BRN_DEP_VALUE }, + {RGX_USCCODE_HEAP_IDENT, RGX_USCCODE_HEAP_BASE, RGX_USCCODE_HEAP_SIZE, (1 * DEVMEM_HEAP_RESERVED_SIZE_GRANULARITY), 0, BRN65273IsPresent, HEAP_INST_DEFAULT_VALUE }, + {RGX_USCCODE_HEAP_IDENT, RGX_USCCODE_BRN_65273_HEAP_BASE, RGX_USCCODE_BRN_65273_HEAP_SIZE, (1 * DEVMEM_HEAP_RESERVED_SIZE_GRANULARITY), 0, BRN65273IsPresent, HEAP_INST_BRN_ALT_VALUE }, + {RGX_TQ3DPARAMETERS_HEAP_IDENT, RGX_TQ3DPARAMETERS_HEAP_BASE, RGX_TQ3DPARAMETERS_HEAP_SIZE, 0, 0, BRN65273IsPresent, HEAP_INST_DEFAULT_VALUE }, + {RGX_TQ3DPARAMETERS_HEAP_IDENT, RGX_TQ3DPARAMETERS_BRN_65273_HEAP_BASE, RGX_TQ3DPARAMETERS_BRN_65273_HEAP_SIZE, 0, 0, BRN65273IsPresent, HEAP_INST_BRN_ALT_VALUE }, + {RGX_VK_CAPT_REPLAY_HEAP_IDENT, RGX_VK_CAPT_REPLAY_HEAP_BASE, RGX_VK_CAPT_REPLAY_HEAP_SIZE, 0, 0, NULL, HEAP_INST_DEFAULT_VALUE }, + {RGX_SIGNALS_HEAP_IDENT, RGX_SIGNALS_HEAP_BASE, RGX_SIGNALS_HEAP_SIZE, 0, 0, SignalSnoopingIsPresent, HEAP_INST_FEAT_DEP_VALUE}, + {RGX_FBCDC_HEAP_IDENT, RGX_FBCDC_HEAP_BASE, RGX_FBCDC_HEAP_SIZE, 0, 0, FBCDescriptorIsPresent, HEAP_INST_FEAT_DEP_VALUE}, + {RGX_FBCDC_LARGE_HEAP_IDENT, RGX_FBCDC_LARGE_HEAP_BASE, RGX_FBCDC_LARGE_HEAP_SIZE, 0, 0, FBCLargeDescriptorIsPresent, HEAP_INST_FEAT_DEP_VALUE}, + {RGX_CMP_MISSION_RMW_HEAP_IDENT, RGX_CMP_MISSION_RMW_HEAP_BASE, RGX_CMP_MISSION_RMW_HEAP_SIZE, 0, 0, NULL, HEAP_INST_DEFAULT_VALUE }, + {RGX_CMP_SAFETY_RMW_HEAP_IDENT, RGX_CMP_SAFETY_RMW_HEAP_BASE, RGX_CMP_SAFETY_RMW_HEAP_SIZE, 0, 0, NULL, HEAP_INST_DEFAULT_VALUE }, + {RGX_TEXTURE_STATE_HEAP_IDENT, RGX_TEXTURE_STATE_HEAP_BASE, RGX_TEXTURE_STATE_HEAP_SIZE, 0, 0, TextureStateIsPresent, HEAP_INST_FEAT_DEP_VALUE}, + {RGX_VISIBILITY_TEST_HEAP_IDENT, RGX_VISIBILITY_TEST_HEAP_BASE, RGX_VISIBILITY_TEST_HEAP_SIZE, 0, 0, BRN65273IsPresent, HEAP_INST_DEFAULT_VALUE }, + {RGX_VISIBILITY_TEST_HEAP_IDENT, RGX_VISIBILITY_TEST_BRN_65273_HEAP_BASE, RGX_VISIBILITY_TEST_BRN_65273_HEAP_SIZE, 0, 0, BRN65273IsPresent, HEAP_INST_BRN_ALT_VALUE }, + {RGX_MMU_INIA_BRN_65273_HEAP_IDENT, RGX_MMU_INIA_BRN_65273_HEAP_BASE, RGX_MMU_INIA_BRN_65273_HEAP_SIZE, 0, 0, BRN65273IsPresent, HEAP_INST_BRN_DEP_VALUE }, + {RGX_MMU_INIB_BRN_65273_HEAP_IDENT, RGX_MMU_INIB_BRN_65273_HEAP_BASE, RGX_MMU_INIB_BRN_65273_HEAP_SIZE, 0, 0, BRN65273IsPresent, HEAP_INST_BRN_DEP_VALUE } }; static const RGX_HEAP_INFO gasRGXHeapLayoutFW[] = { /* Name HeapBase HeapLength HeapReservedRegionLength Log2ImportAlignment pfnIsHeapPresent HeapInstanceFlags*/ - {RGX_FIRMWARE_CONFIG_HEAP_IDENT, RGX_FIRMWARE_GUEST_CONFIG_HEAP_BASE, RGX_FIRMWARE_CONFIG_HEAP_SIZE, 0, 0, FWVZConfigPresent, HEAP_INST_DEFAULT_VALUE}, - {RGX_FIRMWARE_MAIN_HEAP_IDENT, RGX_FIRMWARE_GUEST_MAIN_HEAP_BASE, RGX_FIRMWARE_MIPS_MAIN_HEAP_SIZE_NORMAL, 0, 0, FWBRN65101IsPresent, HEAP_INST_DEFAULT_VALUE}, - {RGX_FIRMWARE_MAIN_HEAP_IDENT, RGX_FIRMWARE_GUEST_MAIN_HEAP_BASE, RGX_FIRMWARE_MIPS_MAIN_HEAP_SIZE_BRN65101, 0, 0, FWBRN65101IsPresent, HEAP_INST_BRN_ALT_VALUE}, - {RGX_FIRMWARE_MAIN_HEAP_IDENT, RGX_FIRMWARE_GUEST_MAIN_HEAP_BASE, RGX_FIRMWARE_META_MAIN_HEAP_SIZE, 0, 0, FWBRN65101IsPresent, HEAP_INST_DEFAULT_VALUE}, - {RGX_FIRMWARE_MAIN_HEAP_IDENT, RGX_FIRMWARE_HOST_MAIN_HEAP_BASE, RGX_FIRMWARE_MIPS_MAIN_HEAP_SIZE_NORMAL, 0, 0, FWBRN65101IsPresent, HEAP_INST_DEFAULT_VALUE}, - {RGX_FIRMWARE_MAIN_HEAP_IDENT, RGX_FIRMWARE_HOST_MAIN_HEAP_BASE, RGX_FIRMWARE_MIPS_MAIN_HEAP_SIZE_BRN65101, 0, 0, FWBRN65101IsPresent, HEAP_INST_BRN_ALT_VALUE}, - {RGX_FIRMWARE_MAIN_HEAP_IDENT, RGX_FIRMWARE_HOST_MAIN_HEAP_BASE, RGX_FIRMWARE_META_MAIN_HEAP_SIZE, 0, 0, FWBRN65101IsPresent, HEAP_INST_DEFAULT_VALUE}, - {RGX_FIRMWARE_CONFIG_HEAP_IDENT, RGX_FIRMWARE_HOST_CONFIG_HEAP_BASE, RGX_FIRMWARE_CONFIG_HEAP_SIZE, 0, 0, FWVZConfigPresent, HEAP_INST_DEFAULT_VALUE} + {RGX_FIRMWARE_MAIN_HEAP_IDENT, RGX_FIRMWARE_MAIN_HEAP_BASE, RGX_FIRMWARE_DEFAULT_MAIN_HEAP_SIZE, 0, 0, FWBRN65101IsPresent, HEAP_INST_DEFAULT_VALUE}, + {RGX_FIRMWARE_MAIN_HEAP_IDENT, RGX_FIRMWARE_MAIN_HEAP_BASE, RGX_FIRMWARE_HOST_MIPS_MAIN_HEAP_SIZE_NORMAL, 0, 0, FWBRN65101IsPresent, HEAP_INST_DEFAULT_VALUE}, + {RGX_FIRMWARE_MAIN_HEAP_IDENT, RGX_FIRMWARE_MAIN_HEAP_BASE, RGX_FIRMWARE_HOST_MIPS_MAIN_HEAP_SIZE_BRN65101, 0, 0, FWBRN65101IsPresent, HEAP_INST_BRN_ALT_VALUE}, + {RGX_FIRMWARE_CONFIG_HEAP_IDENT, RGX_FIRMWARE_CONFIG_HEAP_BASE, RGX_FIRMWARE_CONFIG_HEAP_SIZE, 0, 0, FWVZConfigPresent, HEAP_INST_DEFAULT_VALUE}, }; /* Generic counting method. */ @@ -4304,9 +4351,6 @@ static void RGXDeInitHeaps(DEVICE_MEMORY_INFO *psDevMemoryInfo) static PVRSRV_ERROR RGXPhysMemDeviceHeapsInit(PVRSRV_DEVICE_NODE *psDeviceNode) { PVRSRV_ERROR eError = PVRSRV_OK; - IMG_UINT64 uPhysheapSize; - IMG_CPU_PHYADDR sCpuPAddr; - IMG_DEV_PHYADDR sDevPAddr; PVRSRV_RGXDEV_INFO *psDevInfo = (PVRSRV_RGXDEV_INFO *)psDeviceNode->pvDevice; PHYS_HEAP_CONFIG *psFwMainConfig = FindPhysHeapConfig(psDeviceNode->psDevConfig, PHYS_HEAP_USAGE_FW_MAIN); @@ -4340,53 +4384,34 @@ static PVRSRV_ERROR RGXPhysMemDeviceHeapsInit(PVRSRV_DEVICE_NODE *psDeviceNode) } else /* PHYS_HEAP_TYPE_LMA or PHYS_HEAP_TYPE_DMA */ { - IMG_UINT64 uRawHeapBase; - RA_BASE_T uFwCfgSubHeapBase, uFwMainSubHeapBase; - const IMG_UINT64 ui64ExpectedHeapSize = RGX_FIRMWARE_RAW_HEAP_SIZE; - const RA_LENGTH_T uFwCfgSubHeapSize = RGX_FIRMWARE_CONFIG_HEAP_SIZE; - RA_LENGTH_T uFwMainSubHeapSize; + IMG_UINT64 uFwMainSubHeapSize; PHYS_HEAP_CONFIG sFwHeapConfig; - if (RGX_IS_FEATURE_SUPPORTED(psDevInfo, MIPS)) + /* MIPS Firmware must reserve some space in its Host/Native heap for GPU memory mappings */ + if (RGX_IS_FEATURE_SUPPORTED(psDevInfo, MIPS) && (!PVRSRV_VZ_MODE_IS(GUEST))) { +#if defined(FIX_HW_BRN_65101_BIT_MASK) if (RGX_IS_BRN_SUPPORTED(psDevInfo, 65101)) { - uFwMainSubHeapSize = RGX_FIRMWARE_MIPS_MAIN_HEAP_SIZE_BRN65101; + uFwMainSubHeapSize = RGX_FIRMWARE_HOST_MIPS_MAIN_HEAP_SIZE_BRN65101; } else +#endif { - uFwMainSubHeapSize = RGX_FIRMWARE_MIPS_MAIN_HEAP_SIZE_NORMAL; + uFwMainSubHeapSize = RGX_FIRMWARE_HOST_MIPS_MAIN_HEAP_SIZE_NORMAL; } } else { - uFwMainSubHeapSize = RGX_FIRMWARE_META_MAIN_HEAP_SIZE; + uFwMainSubHeapSize = RGX_FIRMWARE_DEFAULT_MAIN_HEAP_SIZE; } PVR_DPF((PVR_DBG_MESSAGE, "%s: Firmware physical heap uses local memory managed by the driver (LMA)", __func__)); - sCpuPAddr = psFwMainConfig->sStartAddr; - sDevPAddr = psFwMainConfig->sCardBase; - uPhysheapSize = psFwMainConfig->uiSize; - - PVR_LOG_GOTO_IF_FALSE(uPhysheapSize >= ui64ExpectedHeapSize, + PVR_LOG_GOTO_IF_FALSE(psFwMainConfig->uiSize >= RGX_FIRMWARE_RAW_HEAP_SIZE, "Invalid firmware physical heap size.", ErrorDeinit); /* Now we construct RAs to manage the FW heaps */ - uRawHeapBase = sDevPAddr.uiAddr; - - if (PVRSRV_VZ_MODE_IS(GUEST)) - { - /* Guest subheap layout: Config + Main */ - uFwCfgSubHeapBase = uRawHeapBase; - uFwMainSubHeapBase = uFwCfgSubHeapBase + uFwCfgSubHeapSize; - } - else - { - /* Native/Host subheap layout: Main + (optional MIPS reserved range) + Config */ - uFwMainSubHeapBase = uRawHeapBase; - uFwCfgSubHeapBase = uRawHeapBase + RGX_FIRMWARE_RAW_HEAP_SIZE - uFwCfgSubHeapSize; - } #if defined(SUPPORT_AUTOVZ) if (PVRSRV_VZ_MODE_IS(HOST)) @@ -4394,28 +4419,31 @@ static PVRSRV_ERROR RGXPhysMemDeviceHeapsInit(PVRSRV_DEVICE_NODE *psDeviceNode) /* 1 Mb can hold the maximum amount of page tables for the memory shared between the firmware and all KM drivers: * MAX(RAW_HEAP_SIZE) = 32 Mb; MAX(NUMBER_OS) = 8; Total shared memory = 256 Mb; * MMU objects required: 65536 PTEs; 16 PDEs; 1 PCE; */ - RA_LENGTH_T uMaxFwMmuPageTableSize = 1 * 1024 * 1024; + IMG_UINT64 uMaxFwMmuPageTableSize = 1 * 1024 * 1024; + + sFwHeapConfig = *psFwMainConfig; /* By default the firmware MMU's page tables are allocated from the same carveout memory as the firmware heap. * If a different base address is specified for this reserved range, use the overriding define instead. */ #if defined(PVR_AUTOVZ_OVERRIDE_FW_MMU_CARVEOUT_BASE_ADDR) - RA_BASE_T uFwMmuReservedMemStart = PVR_AUTOVZ_OVERRIDE_FW_MMU_CARVEOUT_BASE_ADDR; + sFwHeapConfig.sStartAddr.uiAddr = PVR_AUTOVZ_OVERRIDE_FW_MMU_CARVEOUT_BASE_ADDR; + sFwHeapConfig.sCardBase.uiAddr = PVR_AUTOVZ_OVERRIDE_FW_MMU_CARVEOUT_BASE_ADDR; #else - RA_BASE_T uFwMmuReservedMemStart = uRawHeapBase + (RGX_FIRMWARE_RAW_HEAP_SIZE * RGX_NUM_OS_SUPPORTED); + sFwHeapConfig.sStartAddr.uiAddr += RGX_FIRMWARE_RAW_HEAP_SIZE * RGX_NUM_OS_SUPPORTED; + sFwHeapConfig.sCardBase.uiAddr += RGX_FIRMWARE_RAW_HEAP_SIZE * RGX_NUM_OS_SUPPORTED; #endif - psDeviceNode->psFwMMUReservedMemArena = RA_Create_With_Span("Fw MMU Mem 0", - OSGetPageShift(), - 0, - uFwMmuReservedMemStart, - uMaxFwMmuPageTableSize); - PVR_LOG_GOTO_IF_NOMEM(psDeviceNode->psFwMMUReservedMemArena, eError, ErrorDeinit); + sFwHeapConfig.uiSize = uMaxFwMmuPageTableSize; + sFwHeapConfig.ui32UsageFlags = 0; + + eError = PhysmemCreateHeapLMA(psDeviceNode, &sFwHeapConfig, "Fw MMU subheap", + &psDeviceNode->psFwMMUReservedPhysHeap); + PVR_LOG_GOTO_IF_ERROR(eError, "PhysmemCreateHeapLMA:MMU", ErrorDeinit); } #endif + /* Subheap layout: Main + (optional MIPS reserved range) + Config */ sFwHeapConfig = *psFwMainConfig; - sFwHeapConfig.sStartAddr.uiAddr = sCpuPAddr.uiAddr + (uFwMainSubHeapBase - uRawHeapBase); - sFwHeapConfig.sCardBase.uiAddr = uFwMainSubHeapBase; sFwHeapConfig.uiSize = uFwMainSubHeapSize; sFwHeapConfig.ui32UsageFlags = PHYS_HEAP_USAGE_FW_MAIN; @@ -4423,9 +4451,9 @@ static PVRSRV_ERROR RGXPhysMemDeviceHeapsInit(PVRSRV_DEVICE_NODE *psDeviceNode) PVR_LOG_GOTO_IF_ERROR(eError, "PhysmemCreateHeapLMA:MAIN", ErrorDeinit); sFwHeapConfig = *psFwMainConfig; - sFwHeapConfig.sStartAddr.uiAddr = sCpuPAddr.uiAddr + (uFwCfgSubHeapBase - uRawHeapBase); - sFwHeapConfig.sCardBase.uiAddr = uFwCfgSubHeapBase; - sFwHeapConfig.uiSize = uFwCfgSubHeapSize; + sFwHeapConfig.sStartAddr.uiAddr += RGX_FIRMWARE_RAW_HEAP_SIZE - RGX_FIRMWARE_CONFIG_HEAP_SIZE; + sFwHeapConfig.sCardBase.uiAddr += RGX_FIRMWARE_RAW_HEAP_SIZE - RGX_FIRMWARE_CONFIG_HEAP_SIZE; + sFwHeapConfig.uiSize = RGX_FIRMWARE_CONFIG_HEAP_SIZE; sFwHeapConfig.ui32UsageFlags = PHYS_HEAP_USAGE_FW_CONFIG; eError = PhysmemCreateHeapLMA(psDeviceNode, &sFwHeapConfig, "Fw Cfg subheap", &psDeviceNode->psFWCfgPhysHeap); @@ -4805,6 +4833,24 @@ PVRSRV_ERROR RGXRegisterDevice(PVRSRV_DEVICE_NODE *psDeviceNode) * the answer CCB command carrying an RGX Register read value */ init_completion(&psDevInfo->sFwRegs.sRegComp); psDevInfo->sFwRegs.ui64RegVal = 0; + +#if defined(SUPPORT_SOC_TIMER) + { + IMG_BOOL ui32AppHintDefault = IMG_FALSE; + IMG_BOOL bInitSocTimer; + void *pvAppHintState = NULL; + + OSCreateKMAppHintState(&pvAppHintState); + OSGetKMAppHintBOOL(APPHINT_NO_DEVICE, pvAppHintState, ValidateSOCUSCTimer, &ui32AppHintDefault, &bInitSocTimer); + OSFreeKMAppHintState(pvAppHintState); + + if (bInitSocTimer) + { + eError = RGXInitSOCUSCTimer(psDeviceNode); + PVR_LOG_GOTO_IF_ERROR(eError, "RGXInitSOCUSCTimer", ErrorDeInitHWPerfHost); + } + } +#endif #endif /* Register callback for dumping debug info */ @@ -4820,10 +4866,12 @@ PVRSRV_ERROR RGXRegisterDevice(PVRSRV_DEVICE_NODE *psDeviceNode) /* The device shared-virtual-memory heap address-space size is stored here for faster look-up without having to walk the device heap configuration structures during client device connection (i.e. this size is relative to a zero-based offset) */ +#if defined(FIX_HW_BRN_65273_BIT_MASK) if (RGX_IS_BRN_SUPPORTED(psDevInfo, 65273)) { psDeviceNode->ui64GeneralSVMHeapTopVA = 0; }else +#endif { psDeviceNode->ui64GeneralSVMHeapTopVA = RGX_GENERAL_SVM_HEAP_BASE + RGX_GENERAL_SVM_HEAP_SIZE; } @@ -4856,7 +4904,7 @@ PVRSRV_ERROR RGXRegisterDevice(PVRSRV_DEVICE_NODE *psDeviceNode) #if defined(SUPPORT_POWER_SAMPLING_VIA_DEBUGFS) ErrorDeInitDeviceDepBridge: - DeviceDepBridgeDeInit(psDevInfo->sDevFeatureCfg.ui64Features); + DeviceDepBridgeDeInit(psDevInfo); #endif ErrorDeInitHWPerfHost: diff --git a/drivers/gpu/drm/img-rogue/rgxkicksync.c b/drivers/gpu/drm/img-rogue/rgxkicksync.c index 2ce26854b..73f1b783f 100644 --- a/drivers/gpu/drm/img-rogue/rgxkicksync.c +++ b/drivers/gpu/drm/img-rogue/rgxkicksync.c @@ -200,18 +200,19 @@ PVRSRV_ERROR PVRSRVRGXSetKickSyncContextPropertyKM(RGX_SERVER_KICKSYNC_CONTEXT * IMG_UINT64 ui64Input, IMG_UINT64 *pui64Output) { - PVRSRV_ERROR eError; + PVRSRV_ERROR eError = PVRSRV_OK; switch (eContextProperty) { case RGX_CONTEXT_PROPERTY_FLAGS: { + IMG_UINT32 ui32ContextFlags = (IMG_UINT32)ui64Input; + OSLockAcquire(psKickSyncContext->hLock); eError = FWCommonContextSetFlags(psKickSyncContext->psServerCommonContext, - (IMG_UINT32)ui64Input); + ui32ContextFlags); OSLockRelease(psKickSyncContext->hLock); - PVR_LOG_IF_ERROR(eError, "FWCommonContextSetFlags"); break; } @@ -272,7 +273,6 @@ IMG_UINT32 CheckForStalledClientKickSyncCtxt(PVRSRV_RGXDEV_INFO *psDevInfo) } PVRSRV_ERROR PVRSRVRGXKickSyncKM(RGX_SERVER_KICKSYNC_CONTEXT * psKickSyncContext, - IMG_UINT32 ui32ClientCacheOpSeqNum, IMG_UINT32 ui32ClientUpdateCount, SYNC_PRIMITIVE_BLOCK ** pauiClientUpdateUFODevVarBlock, IMG_UINT32 * paui32ClientUpdateOffset, @@ -594,7 +594,8 @@ PVRSRV_ERROR PVRSRVRGXKickSyncKM(RGX_SERVER_KICKSYNC_CONTEXT * psKickSyncContext } #endif - RGXCmdHelperInitCmdCCB(psClientCCB, + RGXCmdHelperInitCmdCCB(psDevInfo, + psClientCCB, 0, /* empty ui64FBSCEntryMask */ ui32ClientFenceCount, pauiClientFenceUFOAddress, @@ -676,7 +677,6 @@ PVRSRV_ERROR PVRSRVRGXKickSyncKM(RGX_SERVER_KICKSYNC_CONTEXT * psKickSyncContext eError2 = RGXScheduleCommand(psKickSyncContext->psDeviceNode->pvDevice, RGXFWIF_DM_GP, & sKickSyncKCCBCmd, - ui32ClientCacheOpSeqNum, PDUMP_FLAGS_NONE); if (eError2 != PVRSRV_ERROR_RETRY) { diff --git a/drivers/gpu/drm/img-rogue/rgxkicksync.h b/drivers/gpu/drm/img-rogue/rgxkicksync.h index b968520bb..57b49a03d 100644 --- a/drivers/gpu/drm/img-rogue/rgxkicksync.h +++ b/drivers/gpu/drm/img-rogue/rgxkicksync.h @@ -110,7 +110,6 @@ PVRSRV_ERROR PVRSRVRGXSetKickSyncContextPropertyKM(RGX_SERVER_KICKSYNC_CONTEXT * */ /**************************************************************************/ PVRSRV_ERROR PVRSRVRGXKickSyncKM(RGX_SERVER_KICKSYNC_CONTEXT * psKicksyncContext, - IMG_UINT32 ui32ClientCacheOpSeqNum, IMG_UINT32 ui32ClientUpdateCount, SYNC_PRIMITIVE_BLOCK ** pauiClientUpdateUFODevVarBlock, IMG_UINT32 * paui32ClientUpdateDevVarOffset, diff --git a/drivers/gpu/drm/img-rogue/rgxlayer_impl.c b/drivers/gpu/drm/img-rogue/rgxlayer_impl.c index 5b89a4bfc..6c421badd 100644 --- a/drivers/gpu/drm/img-rogue/rgxlayer_impl.c +++ b/drivers/gpu/drm/img-rogue/rgxlayer_impl.c @@ -118,6 +118,7 @@ IMG_UINT32 RGXGetOSPageSize(const void *hPrivate) IMG_UINT32 RGXGetFWCorememSize(const void *hPrivate) { +#if defined(RGX_FEATURE_META_COREMEM_SIZE_MAX_VALUE_IDX) RGX_LAYER_PARAMS *psParams; PVRSRV_RGXDEV_INFO *psDevInfo; IMG_UINT32 ui32CorememSize = 0; @@ -133,6 +134,11 @@ IMG_UINT32 RGXGetFWCorememSize(const void *hPrivate) } return ui32CorememSize; +#else + PVR_UNREFERENCED_PARAMETER(hPrivate); + + return 0U; +#endif } void RGXWriteReg32(const void *hPrivate, IMG_UINT32 ui32RegAddr, IMG_UINT32 ui32RegValue) @@ -726,6 +732,7 @@ IMG_BOOL RGXDoFWSlaveBoot(const void *hPrivate) return PVRSRVSystemSnoopingOfCPUCache(psDevConfig); } +#if defined(RGX_FEATURE_META_MAX_VALUE_IDX) static PVRSRV_ERROR RGXWriteMetaRegThroughSP(const void *hPrivate, IMG_UINT32 ui32RegAddr, IMG_UINT32 ui32RegValue) { PVRSRV_ERROR eError = PVRSRV_OK; @@ -743,6 +750,7 @@ static PVRSRV_ERROR RGXWriteMetaRegThroughSP(const void *hPrivate, IMG_UINT32 ui return eError; } +#endif /* * The fabric coherency test is performed when platform supports fabric coherency @@ -755,17 +763,18 @@ static PVRSRV_ERROR RGXWriteMetaRegThroughSP(const void *hPrivate, IMG_UINT32 ui */ PVRSRV_ERROR RGXFabricCoherencyTest(const void *hPrivate) { +#if defined(RGX_FEATURE_META_MAX_VALUE_IDX) PVRSRV_RGXDEV_INFO *psDevInfo; IMG_UINT32 *pui32FabricCohTestBufferCpuVA; DEVMEM_MEMDESC *psFabricCohTestBufferMemDesc; RGXFWIF_DEV_VIRTADDR sFabricCohTestBufferDevVA; IMG_DEVMEM_SIZE_T uiFabricCohTestBlockSize = sizeof(IMG_UINT64); IMG_DEVMEM_ALIGN_T uiFabricCohTestBlockAlign = sizeof(IMG_UINT64); - IMG_UINT64 ui64SegOutAddrTopCached = 0; - IMG_UINT64 ui64SegOutAddrTopUncached = 0; IMG_UINT32 ui32SLCCTRL = 0; IMG_UINT32 ui32OddEven; - IMG_BOOL bFeatureS7; +#if defined(RGX_FEATURE_S7_TOP_INFRASTRUCTURE_BIT_MASK) + IMG_BOOL bFeatureS7 = RGX_DEVICE_HAS_FEATURE(hPrivate, S7_TOP_INFRASTRUCTURE); +#endif IMG_UINT32 ui32TestType; IMG_UINT32 ui32OddEvenSeed = 1; PVRSRV_ERROR eError = PVRSRV_OK; @@ -780,18 +789,17 @@ PVRSRV_ERROR RGXFabricCoherencyTest(const void *hPrivate) PVR_LOG(("Starting fabric coherency test .....")); - bFeatureS7 = RGX_DEVICE_HAS_FEATURE(hPrivate, S7_TOP_INFRASTRUCTURE); - +#if defined(RGX_FEATURE_S7_TOP_INFRASTRUCTURE_BIT_MASK) if (bFeatureS7) { - ui64SegOutAddrTopCached = RGXFW_SEGMMU_OUTADDR_TOP_VIVT_SLC_CACHED(MMU_CONTEXT_MAPPING_FWIF); - ui64SegOutAddrTopUncached = RGXFW_SEGMMU_OUTADDR_TOP_VIVT_SLC_UNCACHED(MMU_CONTEXT_MAPPING_FWIF); + IMG_UINT64 ui64SegOutAddrTopUncached = RGXFW_SEGMMU_OUTADDR_TOP_VIVT_SLC_UNCACHED(MMU_CONTEXT_MAPPING_FWIF); /* Configure META to use SLC force-linefill for the bootloader segment */ RGXWriteMetaRegThroughSP(hPrivate, META_CR_MMCU_SEGMENTn_OUTA1(6), (ui64SegOutAddrTopUncached | RGXFW_BOOTLDR_DEVV_ADDR) >> 32); } else +#endif { /* Bypass the SLC when IO coherency is enabled */ ui32SLCCTRL = RGXReadReg32(hPrivate, RGX_CR_SLC_CTRL_BYPASS); @@ -951,11 +959,11 @@ PVRSRV_ERROR RGXFabricCoherencyTest(const void *hPrivate) } /* Write the value using the RGX slave-port interface */ - eError = RGXWriteMETAAddr(psDevInfo, ui32FWAddr, ui32FWValue); + eError = RGXWriteFWModuleAddr(psDevInfo, ui32FWAddr, ui32FWValue); if (eError != PVRSRV_OK) { PVR_DPF((PVR_DBG_ERROR, - "RGXWriteMETAAddr error: %s, exiting", + "RGXWriteFWModuleAddr error: %s, exiting", PVRSRVGetErrorString(eError))); bExit = IMG_TRUE; continue; @@ -963,11 +971,11 @@ PVRSRV_ERROR RGXFabricCoherencyTest(const void *hPrivate) /* Read back value using RGX slave-port interface, this is used as a sort of memory barrier for the above write */ - eError = RGXReadMETAAddr(psDevInfo, ui32FWAddr, &ui32FWValue2); + eError = RGXReadFWModuleAddr(psDevInfo, ui32FWAddr, &ui32FWValue2); if (eError != PVRSRV_OK) { PVR_DPF((PVR_DBG_ERROR, - "RGXReadMETAAddr error: %s, exiting", + "RGXReadFWModuleAddr error: %s, exiting", PVRSRVGetErrorString(eError))); bExit = IMG_TRUE; continue; @@ -1013,7 +1021,7 @@ PVRSRV_ERROR RGXFabricCoherencyTest(const void *hPrivate) pui32FabricCohTestBufferCpuVA[i] = i + ui32OddEvenSeed; /* Flush possible cpu store-buffer(ing) on LMA */ - OSWriteMemoryBarrier(); + OSWriteMemoryBarrier(&pui32FabricCohTestBufferCpuVA[i]); switch (ui32TestType) { @@ -1031,11 +1039,11 @@ PVRSRV_ERROR RGXFabricCoherencyTest(const void *hPrivate) } /* Read back value using RGX slave-port interface */ - eError = RGXReadMETAAddr(psDevInfo, ui32FWAddr, &ui32FWValue); + eError = RGXReadFWModuleAddr(psDevInfo, ui32FWAddr, &ui32FWValue); if (eError != PVRSRV_OK) { PVR_DPF((PVR_DBG_ERROR, - "RGXReadWithSP error: %s, exiting", + "RGXReadFWModuleAddr error: %s, exiting", PVRSRVGetErrorString(eError))); bExit = IMG_TRUE; continue; @@ -1135,13 +1143,16 @@ e1: DevmemFwUnmapAndFree(psDevInfo, psFabricCohTestBufferMemDesc); e0: +#if defined(RGX_FEATURE_S7_TOP_INFRASTRUCTURE_BIT_MASK) if (bFeatureS7) { /* Restore bootloader segment settings */ + IMG_UINT64 ui64SegOutAddrTopCached = RGXFW_SEGMMU_OUTADDR_TOP_VIVT_SLC_CACHED(MMU_CONTEXT_MAPPING_FWIF); RGXWriteMetaRegThroughSP(hPrivate, META_CR_MMCU_SEGMENTn_OUTA1(6), (ui64SegOutAddrTopCached | RGXFW_BOOTLDR_DEVV_ADDR) >> 32); } else +#endif { /* Restore SLC bypass settings */ RGXWriteReg32(hPrivate, RGX_CR_SLC_CTRL_BYPASS, ui32SLCCTRL); @@ -1160,6 +1171,11 @@ e0: } return eError; +#else + PVR_UNREFERENCED_PARAMETER(hPrivate); + + return PVRSRV_OK; +#endif } IMG_INT32 RGXDeviceGetFeatureValue(const void *hPrivate, IMG_UINT64 ui64Feature) diff --git a/drivers/gpu/drm/img-rogue/rgxmem.c b/drivers/gpu/drm/img-rogue/rgxmem.c index b32d65b24..de38b1cec 100644 --- a/drivers/gpu/drm/img-rogue/rgxmem.c +++ b/drivers/gpu/drm/img-rogue/rgxmem.c @@ -223,7 +223,9 @@ void RGXMMUCacheInvalidate(PVRSRV_DEVICE_NODE *psDeviceNode, case MMU_LEVEL_1: ui32NewCacheFlags = RGXFWIF_MMUCACHEDATA_FLAGS_PT; +#if defined(RGX_FEATURE_SLC_VIVT_BIT_MASK) if (!(RGX_IS_FEATURE_SUPPORTED(psDevInfo, SLC_VIVT))) +#endif { ui32NewCacheFlags |= RGXFWIF_MMUCACHEDATA_FLAGS_TLB; } @@ -236,11 +238,13 @@ void RGXMMUCacheInvalidate(PVRSRV_DEVICE_NODE *psDeviceNode, break; } +#if defined(RGX_FEATURE_SLC_VIVT_BIT_MASK) if (RGX_IS_FEATURE_SUPPORTED(psDevInfo, SLC_VIVT)) { MMU_AppendCacheFlags(psMMUContext, ui32NewCacheFlags); } else +#endif { MMU_AppendCacheFlags(psDevInfo->psKernelMMUCtx, ui32NewCacheFlags); } @@ -310,7 +314,7 @@ PVRSRV_ERROR RGXMMUCacheInvalidateKick(PVRSRV_DEVICE_NODE *psDeviceNode, { PVRSRV_ERROR eError; IMG_UINT32 ui32FWCacheFlags; - + PVRSRV_RGXDEV_INFO *psDevInfo = (PVRSRV_RGXDEV_INFO *)psDeviceNode->pvDevice; eError = PVRSRVPowerLock(psDeviceNode); if (eError != PVRSRV_OK) { @@ -328,15 +332,16 @@ PVRSRV_ERROR RGXMMUCacheInvalidateKick(PVRSRV_DEVICE_NODE *psDeviceNode, } /* Ensure device is powered up before sending cache command */ - PDUMPPOWCMDSTART(); + PDUMPPOWCMDSTART(psDeviceNode); eError = PVRSRVSetDevicePowerStateKM(psDeviceNode, PVRSRV_DEV_POWER_STATE_ON, PVRSRV_POWER_FLAGS_NONE); - PDUMPPOWCMDEND(); + PDUMPPOWCMDEND(psDeviceNode); if (eError != PVRSRV_OK) { PVR_DPF((PVR_DBG_WARNING, "%s: failed to transition RGX to ON (%s)", __func__, PVRSRVGetErrorString(eError))); + MMU_AppendCacheFlags(psDevInfo->psKernelMMUCtx, ui32FWCacheFlags); goto _PowerUnlockAndReturnErr; } @@ -345,6 +350,9 @@ PVRSRV_ERROR RGXMMUCacheInvalidateKick(PVRSRV_DEVICE_NODE *psDeviceNode, if (eError != PVRSRV_OK) { /* failed to submit cache operations, return failure */ + PVR_DPF((PVR_DBG_WARNING, "%s: failed to submit cache command (%s)", + __func__, PVRSRVGetErrorString(eError))); + MMU_AppendCacheFlags(psDevInfo->psKernelMMUCtx, ui32FWCacheFlags); goto _PowerUnlockAndReturnErr; } @@ -583,7 +591,7 @@ PVRSRV_ERROR RGXRegisterMemoryContext(PVRSRV_DEVICE_NODE *psDeviceNode, /* * Set default values for the rest of the structure. */ - psFWMemContext->uiPageCatBaseRegID = RGXFW_BIF_INVALID_PCREG; + psFWMemContext->uiPageCatBaseRegSet = RGXFW_BIF_INVALID_PCSET; psFWMemContext->uiBreakpointAddr = 0; psFWMemContext->uiBPHandlerAddr = 0; psFWMemContext->uiBreakpointCtl = 0; diff --git a/drivers/gpu/drm/img-rogue/rgxmipsmmuinit.c b/drivers/gpu/drm/img-rogue/rgxmipsmmuinit.c index f6e782bb9..0e6c0ab05 100644 --- a/drivers/gpu/drm/img-rogue/rgxmipsmmuinit.c +++ b/drivers/gpu/drm/img-rogue/rgxmipsmmuinit.c @@ -1006,3 +1006,40 @@ static PVRSRV_ERROR RGXGetPageSizeFromPDE8(IMG_UINT64 ui64PDE, IMG_UINT32 *pui32 PVR_DPF((PVR_DBG_ERROR, "PDE not supported on MIPS")); return PVRSRV_ERROR_MMU_INVALID_PAGE_SIZE_FOR_DEVICE; } + +void RGXMipsCheckFaultAddress(MMU_CONTEXT *psFwMMUCtx, + IMG_UINT32 ui32FwVA, + MMU_FAULT_DATA *psOutFaultData) +{ + IMG_UINT32 *pui32PageTable = NULL; + PVRSRV_ERROR eError = MMU_AcquireCPUBaseAddr(psFwMMUCtx, (void**) &pui32PageTable); + MMU_LEVEL_DATA *psMMULevelData; + IMG_UINT32 ui32FwHeapBase = (IMG_UINT32) (RGX_FIRMWARE_RAW_HEAP_BASE & UINT_MAX); + IMG_UINT32 ui32PageSize = OSGetPageSize(); + + /* MIPS Firmware CPU must use the same page size as the Host */ + IMG_UINT32 ui32PTEIndex = ((ui32FwVA & ~(ui32PageSize - 1)) - ui32FwHeapBase) / ui32PageSize; + + psOutFaultData->eTopLevel = MMU_LEVEL_1; + psOutFaultData->eType = MMU_FAULT_TYPE_NON_PM; + + psMMULevelData = &psOutFaultData->sLevelData[MMU_LEVEL_1]; + psMMULevelData->uiBytesPerEntry = 1 << RGXMIPSFW_LOG2_PTE_ENTRY_SIZE; + psMMULevelData->ui32Index = ui32PTEIndex; + psMMULevelData->ui32NumOfEntries = RGX_FIRMWARE_RAW_HEAP_SIZE / ui32PageSize; + + if ((eError == PVRSRV_OK) && (pui32PageTable != NULL)) + { + psMMULevelData->ui64Address = pui32PageTable[ui32PTEIndex]; + } + else + { + psMMULevelData->ui64Address = 0U; + } + + psMMULevelData->psDebugStr = BITMASK_HAS(psMMULevelData->ui64Address, + RGXMIPSFW_TLB_VALID) ? + ("valid") : ("not valid"); +} + + diff --git a/drivers/gpu/drm/img-rogue/rgxmipsmmuinit.h b/drivers/gpu/drm/img-rogue/rgxmipsmmuinit.h index 7129bc4ee..b2b39402c 100644 --- a/drivers/gpu/drm/img-rogue/rgxmipsmmuinit.h +++ b/drivers/gpu/drm/img-rogue/rgxmipsmmuinit.h @@ -90,5 +90,8 @@ Page Table entry # PVRSRV_ERROR RGXMipsMMUInit_Register(PVRSRV_DEVICE_NODE *psDeviceNode); PVRSRV_ERROR RGXMipsMMUInit_Unregister(PVRSRV_DEVICE_NODE *psDeviceNode); +void RGXMipsCheckFaultAddress(MMU_CONTEXT *psFwMMUCtx, + IMG_UINT32 ui32FwVA, + MMU_FAULT_DATA *psOutFaultData); #endif /* #ifndef SRVKM_RGXMIPSMMUINIT_H */ diff --git a/drivers/gpu/drm/img-rogue/rgxpower.c b/drivers/gpu/drm/img-rogue/rgxpower.c index d3e664ba7..1a2a09ed4 100644 --- a/drivers/gpu/drm/img-rogue/rgxpower.c +++ b/drivers/gpu/drm/img-rogue/rgxpower.c @@ -580,17 +580,22 @@ static INLINE void RGXCheckFWBootStage(PVRSRV_RGXDEV_INFO *psDevInfo) { FW_BOOT_STAGE eStage; +#if defined(RGX_FEATURE_META_MAX_VALUE_IDX) if (RGX_IS_FEATURE_VALUE_SUPPORTED(psDevInfo, META)) { /* Boot stage temporarily stored to the register below */ eStage = OSReadHWReg32(psDevInfo->pvRegsBaseKM, RGX_FW_BOOT_STAGE_REGISTER); } - else if (RGX_IS_FEATURE_SUPPORTED(psDevInfo, RISCV_FW_PROCESSOR)) + else +#endif +#if defined(RGX_FEATURE_RISCV_FW_PROCESSOR_BIT_MASK) + if (RGX_IS_FEATURE_SUPPORTED(psDevInfo, RISCV_FW_PROCESSOR)) { eStage = OSReadHWReg32(psDevInfo->pvRegsBaseKM, RGX_CR_SCRATCH14); } else +#endif { IMG_BYTE *pbBootData; @@ -659,42 +664,12 @@ static INLINE PVRSRV_ERROR RGXDoStart(PVRSRV_DEVICE_NODE *psDeviceNode) #if defined(NO_HARDWARE) && defined(PDUMP) #if 0 -#include "rgxtbdefs.h" +#include "emu_cr_defs.h" #else - -/* - Register RGX_TB_SYSTEM_STATUS -*/ -#define RGX_TB_SYSTEM_STATUS (0x00E0U) -#define RGX_TB_SYSTEM_STATUS_MASKFULL (IMG_UINT64_C(0x00000000030100FF)) -/* -directly indicates the status of power_abort flag from the power management controller (RGX_PRCM) -*/ -#define RGX_TB_SYSTEM_STATUS_HOST_POWER_EVENT_ABORT_SHIFT (25U) -#define RGX_TB_SYSTEM_STATUS_HOST_POWER_EVENT_ABORT_CLRMSK (IMG_UINT64_C(0XFFFFFFFFFDFFFFFF)) -#define RGX_TB_SYSTEM_STATUS_HOST_POWER_EVENT_ABORT_EN (IMG_UINT64_C(0X0000000002000000)) -/* -directly indicates the status of power_complete flag from the power management controller (RGX_PRCM) -*/ -#define RGX_TB_SYSTEM_STATUS_HOST_POWER_EVENT_COMPLETE_SHIFT (24U) -#define RGX_TB_SYSTEM_STATUS_HOST_POWER_EVENT_COMPLETE_CLRMSK (IMG_UINT64_C(0XFFFFFFFFFEFFFFFF)) -#define RGX_TB_SYSTEM_STATUS_HOST_POWER_EVENT_COMPLETE_EN (IMG_UINT64_C(0X0000000001000000)) -/* -directly indicates the status of GPU's hmmu_irq -*/ -#define RGX_TB_SYSTEM_STATUS_HMMU_IRQ_SHIFT (16U) -#define RGX_TB_SYSTEM_STATUS_HMMU_IRQ_CLRMSK (IMG_UINT64_C(0XFFFFFFFFFFFEFFFF)) -#define RGX_TB_SYSTEM_STATUS_HMMU_IRQ_EN (IMG_UINT64_C(0X0000000000010000)) -/* -directly indicates the status of GPU's irq per OS_ID -*/ -#define RGX_TB_SYSTEM_STATUS_IRQ_SHIFT (1U) -#define RGX_TB_SYSTEM_STATUS_IRQ_CLRMSK (IMG_UINT64_C(0XFFFFFFFFFFFFFE01)) -/* -old deprecated single irq -*/ -#define RGX_TB_SYSTEM_STATUS_OLD_IRQ_SHIFT (0U) -#define RGX_TB_SYSTEM_STATUS_OLD_IRQ_CLRMSK (IMG_UINT64_C(0XFFFFFFFFFFFFFFFE)) +#define EMU_CR_SYSTEM_IRQ_STATUS (0x00E0U) +/* IRQ is officially defined [8 .. 0] but here we split out the old deprecated single irq. */ +#define EMU_CR_SYSTEM_IRQ_STATUS_IRQ_CLRMSK (IMG_UINT64_C(0XFFFFFFFFFFFFFE01)) +#define EMU_CR_SYSTEM_IRQ_STATUS_OLD_IRQ_CLRMSK (IMG_UINT64_C(0XFFFFFFFFFFFFFFFE)) #endif static PVRSRV_ERROR @@ -714,9 +689,9 @@ _ValidateIrqs(PVRSRV_RGXDEV_INFO *psDevInfo) "Poll for TB irq status to be set (irqs signalled)..."); PDUMPREGPOL(psDevInfo->psDeviceNode, RGX_TB_PDUMPREG_NAME, - RGX_TB_SYSTEM_STATUS, - ~RGX_TB_SYSTEM_STATUS_IRQ_CLRMSK, - ~RGX_TB_SYSTEM_STATUS_IRQ_CLRMSK, + EMU_CR_SYSTEM_IRQ_STATUS, + ~EMU_CR_SYSTEM_IRQ_STATUS_IRQ_CLRMSK, + ~EMU_CR_SYSTEM_IRQ_STATUS_IRQ_CLRMSK, ui32PDumpFlags, PDUMP_POLL_OPERATOR_EQUAL); @@ -780,12 +755,7 @@ static PVRSRV_ERROR RGXVirtualisationPowerupSidebandTest(PVRSRV_DEVICE_NODE *ps PVR_DPF((PVR_DBG_MESSAGE, "Testing per-os kick registers:")); - /* Need to get the maximum supported OSid value from the per-device info. - * This can change according to how much memory is physically present and - * what the carve-out mapping looks like (provided by the module load-time - * parameters). - */ - ui32OsRegBanksMapped = MIN(ui32OsRegBanksMapped, psDeviceNode->ui32NumOSId); + ui32OsRegBanksMapped = MIN(ui32OsRegBanksMapped, GPUVIRT_VALIDATION_NUM_OS); if (ui32OsRegBanksMapped != RGXFW_MAX_NUM_OS) { @@ -800,9 +770,16 @@ static PVRSRV_ERROR RGXVirtualisationPowerupSidebandTest(PVRSRV_DEVICE_NODE *ps { /* set Test field */ psFwSysInit->ui32OSKickTest = (ui32OSid << RGXFWIF_KICK_TEST_OSID_SHIFT) | RGXFWIF_KICK_TEST_ENABLED_BIT; + +#if defined(PDUMP) + DevmemPDumpLoadMem(psDevInfo->psRGXFWIfSysInitMemDesc, + offsetof(RGXFWIF_SYSINIT, ui32OSKickTest), + sizeof(psFwSysInit->ui32OSKickTest), + PDUMP_FLAGS_CONTINUOUS); +#endif + /* Force a read-back to memory to avoid posted writes on certain buses */ - (void) psFwSysInit->ui32OSKickTest; - OSWriteMemoryBarrier(); + OSWriteMemoryBarrier(&psFwSysInit->ui32OSKickTest); /* kick register */ ui32ScheduleRegister = RGX_CR_MTS_SCHEDULE + (ui32OSid * RGX_VIRTUALISATION_REG_SIZE_PER_OS); @@ -810,7 +787,21 @@ static PVRSRV_ERROR RGXVirtualisationPowerupSidebandTest(PVRSRV_DEVICE_NODE *ps ui32OSid, ui32ScheduleRegister)); OSWriteHWReg32(psDevInfo->pvRegsBaseKM, ui32ScheduleRegister, ui32KickType); - OSMemoryBarrier(); + OSMemoryBarrier((IMG_BYTE*) psDevInfo->pvRegsBaseKM + ui32ScheduleRegister); + +#if defined(PDUMP) + PDUMPCOMMENTWITHFLAGS(psDevInfo->psDeviceNode, PDUMP_FLAGS_CONTINUOUS, "VZ sideband test, kicking MTS register %u", ui32OSid); + + PDUMPREG32(psDeviceNode, RGX_PDUMPREG_NAME, + ui32ScheduleRegister, ui32KickType, PDUMP_FLAGS_CONTINUOUS); + + DevmemPDumpDevmemPol32(psDevInfo->psRGXFWIfSysInitMemDesc, + offsetof(RGXFWIF_SYSINIT, ui32OSKickTest), + 0, + 0xFFFFFFFF, + PDUMP_POLL_OPERATOR_EQUAL, + PDUMP_FLAGS_CONTINUOUS); +#endif /* Wait test enable bit to be unset */ if (PVRSRVPollForValueKM(psDeviceNode, @@ -909,13 +900,13 @@ static void RGXRiscvDebugModuleTest(PVRSRV_RGXDEV_INFO *psDevInfo) ui32Tmp = *pui32FWCode; /* Write FW code at address (bootloader) */ - RGXRiscvWriteMem(psDevInfo, RGXRISCVFW_BOOTLDR_CODE_BASE, SCRATCH_VALUE); + RGXWriteFWModuleAddr(psDevInfo, RGXRISCVFW_BOOTLDR_CODE_BASE, SCRATCH_VALUE); /* Read FW code at address (bootloader + 4) (compare against value read from Host) */ RGXRiscvPollMem(psDevInfo, RGXRISCVFW_BOOTLDR_CODE_BASE + 4, *(pui32FWCode + 1)); /* Read FW code at address (bootloader) (compare against previously written value) */ RGXRiscvPollMem(psDevInfo, RGXRISCVFW_BOOTLDR_CODE_BASE, SCRATCH_VALUE); /* Restore FW code at address (bootloader) */ - RGXRiscvWriteMem(psDevInfo, RGXRISCVFW_BOOTLDR_CODE_BASE, ui32Tmp); + RGXWriteFWModuleAddr(psDevInfo, RGXRISCVFW_BOOTLDR_CODE_BASE, ui32Tmp); DevmemReleaseCpuVirtAddr(psDevInfo->psRGXFWCodeMemDesc); } @@ -934,7 +925,7 @@ static void RGXRiscvDebugModuleTest(PVRSRV_RGXDEV_INFO *psDevInfo) /* Read SCRATCH0 */ RGXRiscvPollMem(psDevInfo, RGXRISCVFW_SOCIF_BASE | RGX_CR_SCRATCH0, SCRATCH_VALUE); /* Write SCRATCH0 */ - RGXRiscvWriteMem(psDevInfo, RGXRISCVFW_SOCIF_BASE | RGX_CR_SCRATCH0, ~SCRATCH_VALUE); + RGXWriteFWModuleAddr(psDevInfo, RGXRISCVFW_SOCIF_BASE | RGX_CR_SCRATCH0, ~SCRATCH_VALUE); /* Read SCRATCH0 from the Host */ PDUMPREGPOL(psDevInfo->psDeviceNode, RGX_PDUMPREG_NAME, RGX_CR_SCRATCH0, ~SCRATCH_VALUE, 0xFFFFFFFFU, @@ -978,7 +969,7 @@ PVRSRV_ERROR RGXPostPowerState(IMG_HANDLE hDevHandle, return eError; } - OSMemoryBarrier(); + OSMemoryBarrier(NULL); /* * Check whether the FW has started by polling on bFirmwareStarted flag @@ -1130,17 +1121,14 @@ PVRSRV_ERROR RGXPostClockSpeedChange(IMG_HANDLE hDevHandle, sCOREClkSpeedChangeCmd.eCmdType = RGXFWIF_KCCB_CMD_CORECLKSPEEDCHANGE; sCOREClkSpeedChangeCmd.uCmdData.sCoreClkSpeedChangeData.ui32NewClockSpeed = ui32NewClockSpeed; - /* Ensure the new clock speed is written to memory before requesting the FW to read it */ - OSMemoryBarrier(); - PDUMPCOMMENT(psDeviceNode, "Scheduling CORE clock speed change command"); - PDUMPPOWCMDSTART(); + PDUMPPOWCMDSTART(psDeviceNode); eError = RGXSendCommandAndGetKCCBSlot(psDeviceNode->pvDevice, &sCOREClkSpeedChangeCmd, PDUMP_FLAGS_NONE, &ui32CmdKCCBSlot); - PDUMPPOWCMDEND(); + PDUMPPOWCMDEND(psDeviceNode); if (eError != PVRSRV_OK) { @@ -1197,7 +1185,7 @@ PVRSRV_ERROR RGXDustCountChange(IMG_HANDLE hDevHandle, } psRuntimeCfg->ui32DefaultDustsNumInit = ui32NumberOfDusts; - OSWriteMemoryBarrier(); + OSWriteMemoryBarrier(&psRuntimeCfg->ui32DefaultDustsNumInit); #if !defined(NO_HARDWARE) { @@ -1305,7 +1293,7 @@ PVRSRV_ERROR RGXAPMLatencyChange(IMG_HANDLE hDevHandle, */ psRuntimeCfg->ui32ActivePMLatencyms = ui32ActivePMLatencyms; psRuntimeCfg->bActivePMLatencyPersistant = bActivePMLatencyPersistant; - OSWriteMemoryBarrier(); + OSWriteMemoryBarrier(&psRuntimeCfg->bActivePMLatencyPersistant); eError = PVRSRVGetDevicePowerState(psDeviceNode, &ePowerState); @@ -1380,11 +1368,11 @@ PVRSRV_ERROR RGXActivePowerRequest(IMG_HANDLE hDevHandle) SetFirmwareHandshakeIdleTime(RGXReadHWTimerReg(psDevInfo)-psFwSysData->ui64StartIdleTime); #endif - PDUMPPOWCMDSTART(); + PDUMPPOWCMDSTART(psDeviceNode); eError = PVRSRVSetDevicePowerStateKM(psDeviceNode, PVRSRV_DEV_POWER_STATE_OFF, PVRSRV_POWER_FLAGS_NONE); - PDUMPPOWCMDEND(); + PDUMPPOWCMDEND(psDeviceNode); if (eError == PVRSRV_OK) { diff --git a/drivers/gpu/drm/img-rogue/rgxregconfig.c b/drivers/gpu/drm/img-rogue/rgxregconfig.c index 917af615f..ef39bea25 100644 --- a/drivers/gpu/drm/img-rogue/rgxregconfig.c +++ b/drivers/gpu/drm/img-rogue/rgxregconfig.c @@ -136,7 +136,6 @@ PVRSRV_ERROR PVRSRVRGXAddRegConfigKM(CONNECTION_DATA * psConnection, eError = RGXScheduleCommand(psDeviceNode->pvDevice, RGXFWIF_DM_GP, &sRegCfgCmd, - 0, PDUMP_FLAGS_CONTINUOUS); if (eError != PVRSRV_OK) { @@ -193,7 +192,6 @@ PVRSRV_ERROR PVRSRVRGXClearRegConfigKM(CONNECTION_DATA * psConnection, eError = RGXScheduleCommand(psDeviceNode->pvDevice, RGXFWIF_DM_GP, &sRegCfgCmd, - 0, PDUMP_FLAGS_CONTINUOUS); if (eError != PVRSRV_OK) { @@ -243,7 +241,6 @@ PVRSRV_ERROR PVRSRVRGXEnableRegConfigKM(CONNECTION_DATA * psConnection, eError = RGXScheduleCommand(psDeviceNode->pvDevice, RGXFWIF_DM_GP, &sRegCfgCmd, - 0, PDUMP_FLAGS_CONTINUOUS); if (eError != PVRSRV_OK) { @@ -291,7 +288,6 @@ PVRSRV_ERROR PVRSRVRGXDisableRegConfigKM(CONNECTION_DATA * psConnection, eError = RGXScheduleCommand(psDeviceNode->pvDevice, RGXFWIF_DM_GP, &sRegCfgCmd, - 0, PDUMP_FLAGS_CONTINUOUS); if (eError != PVRSRV_OK) { diff --git a/drivers/gpu/drm/img-rogue/rgxshader.c b/drivers/gpu/drm/img-rogue/rgxshader.c index 5aa61f064..407c0fbd5 100644 --- a/drivers/gpu/drm/img-rogue/rgxshader.c +++ b/drivers/gpu/drm/img-rogue/rgxshader.c @@ -293,23 +293,10 @@ PVRSRVTQAcquireShaders(PVRSRV_DEVICE_NODE * psDeviceNode, *ppsCLIPMRMem = psDevInfo->hTQCLISharedMem; } -PVRSRV_ERROR -PVRSRVTQUnloadShaders(PVRSRV_DEVICE_NODE * psDeviceNode) +void PVRSRVTQUnloadShaders(PVRSRV_DEVICE_NODE * psDeviceNode) { PVRSRV_RGXDEV_INFO *psDevInfo = psDeviceNode->pvDevice; - PVRSRV_ERROR eError; - eError = PMRUnrefPMR(psDevInfo->hTQUSCSharedMem); - if (eError != PVRSRV_OK) - { - return eError; - } - - eError = PMRUnrefPMR(psDevInfo->hTQCLISharedMem); - if (eError != PVRSRV_OK) - { - return eError; - } - - return PVRSRV_OK; + (void) PMRUnrefPMR(psDevInfo->hTQUSCSharedMem); + (void) PMRUnrefPMR(psDevInfo->hTQCLISharedMem); } diff --git a/drivers/gpu/drm/img-rogue/rgxshader.h b/drivers/gpu/drm/img-rogue/rgxshader.h index 20db8ddd8..7676ede51 100644 --- a/drivers/gpu/drm/img-rogue/rgxshader.h +++ b/drivers/gpu/drm/img-rogue/rgxshader.h @@ -77,9 +77,7 @@ PVRSRVTQAcquireShaders(PVRSRV_DEVICE_NODE *psDeviceNode, @Function PVRSRVTQUnLoadShaders @Description Unref PMR memory. @Input psDeviceNode Device node -@Return PVRSRV_ERROR Returns PVRSRV_OK on success. */ /**************************************************************************/ -PVRSRV_ERROR -PVRSRVTQUnloadShaders(PVRSRV_DEVICE_NODE *psDeviceNode); +void PVRSRVTQUnloadShaders(PVRSRV_DEVICE_NODE *psDeviceNode); #endif /* RGXSHADER_H */ diff --git a/drivers/gpu/drm/img-rogue/rgxsrvinit.c b/drivers/gpu/drm/img-rogue/rgxsrvinit.c index 6221d0f5f..851054a7c 100644 --- a/drivers/gpu/drm/img-rogue/rgxsrvinit.c +++ b/drivers/gpu/drm/img-rogue/rgxsrvinit.c @@ -170,6 +170,7 @@ typedef struct _RGX_SRVINIT_APPHINTS_ IMG_BOOL bAssertOnOutOfMem; #if defined(SUPPORT_VALIDATION) IMG_BOOL bValidateIrq; + IMG_BOOL bValidateSOCUSCTimer; #endif IMG_BOOL bAssertOnHWRTrigger; #if defined(SUPPORT_VALIDATION) @@ -177,6 +178,7 @@ typedef struct _RGX_SRVINIT_APPHINTS_ IMG_UINT32 ui32FBCDCVersionOverride; IMG_UINT32 ui32TFBCCompressionControlGroup; IMG_UINT32 ui32TFBCCompressionControlScheme; + IMG_BOOL bTFBCCompressionControlYUVFormat; #endif IMG_BOOL bCheckMlist; IMG_BOOL bDisableClockGating; @@ -191,7 +193,7 @@ typedef struct _RGX_SRVINIT_APPHINTS_ IMG_BOOL bZeroFreelist; IMG_UINT32 ui32EnableFWContextSwitch; IMG_UINT32 ui32FWContextSwitchProfile; - IMG_UINT32 ui32VDMContextSwitchMode; + IMG_UINT32 ui32HWPerfFWBufSize; IMG_UINT32 ui32HWPerfHostBufSize; IMG_UINT32 ui32HWPerfFilter0; @@ -231,32 +233,41 @@ static INLINE void GetApphints(PVRSRV_RGXDEV_INFO *psDevInfo, RGX_SRVINIT_APPHIN void *pvParamState = SrvInitParamOpen(); IMG_UINT32 ui32ParamTemp; IMG_BOOL bS7TopInfra = IMG_FALSE, bE42290 = IMG_FALSE, bTPUFiltermodeCtrl = IMG_FALSE; - IMG_BOOL bE42606 = IMG_FALSE, bAXIACELite = IMG_FALSE; + IMG_BOOL bE42606 = IMG_FALSE; +#if defined(EMULATOR) + IMG_BOOL bAXIACELite = IMG_FALSE; +#endif +#if defined(RGX_FEATURE_S7_TOP_INFRASTRUCTURE_BIT_MASK) if (RGX_IS_FEATURE_SUPPORTED(psDevInfo, S7_TOP_INFRASTRUCTURE)) { bS7TopInfra = IMG_TRUE; } - +#endif +#if defined(RGX_FEATURE_TPU_FILTERING_MODE_CONTROL_BIT_MASK) if (RGX_IS_FEATURE_SUPPORTED(psDevInfo, TPU_FILTERING_MODE_CONTROL)) { bTPUFiltermodeCtrl = IMG_TRUE; } - +#endif +#if defined(HW_ERN_42290_BIT_MASK) if (RGX_IS_ERN_SUPPORTED(psDevInfo, 42290)) { bE42290 = IMG_TRUE; } - +#endif +#if defined(HW_ERN_42606_BIT_MASK) if (RGX_IS_ERN_SUPPORTED(psDevInfo, 42606)) { bE42606 = IMG_TRUE; } - +#endif +#if defined(HW_FEATURE_AXI_ACELITE_BIT_MASK) && defined(EMULATOR) if (RGX_IS_FEATURE_SUPPORTED(psDevInfo, AXI_ACELITE)) { bAXIACELite = IMG_TRUE; } +#endif /* * NB AppHints initialised to a default value via SrvInitParamInit* macros above @@ -278,13 +289,13 @@ static INLINE void GetApphints(PVRSRV_RGXDEV_INFO *psDevInfo, RGX_SRVINIT_APPHIN SrvInitParamGetBOOL(INITPARAM_NO_DEVICE, pvParamState, EnableRandomContextSwitch, psHints->bEnableRandomCsw); SrvInitParamGetBOOL(INITPARAM_NO_DEVICE, pvParamState, EnableSoftResetContextSwitch, psHints->bEnableSoftResetCsw); SrvInitParamGetUINT32(INITPARAM_NO_DEVICE, pvParamState, EnableFWContextSwitch, psHints->ui32EnableFWContextSwitch); - SrvInitParamGetUINT32(INITPARAM_NO_DEVICE, pvParamState, VDMContextSwitchMode, psHints->ui32VDMContextSwitchMode); SrvInitParamGetUINT32(INITPARAM_NO_DEVICE, pvParamState, EnableRDPowerIsland, ui32ParamTemp); psHints->eRGXRDPowerIslandConf = ui32ParamTemp; SrvInitParamGetUINT32(INITPARAM_NO_DEVICE, pvParamState, FirmwarePerf, ui32ParamTemp); psHints->eFirmwarePerf = ui32ParamTemp; SrvInitParamGetUINT32(INITPARAM_NO_DEVICE, pvParamState, FWContextSwitchProfile, psHints->ui32FWContextSwitchProfile); - SrvInitParamGetBOOL(INITPARAM_NO_DEVICE, pvParamState, HWPerfDisableCustomCounterFilter, psHints->bHWPerfDisableCustomCounterFilter); + SrvInitParamGetBOOL(INITPARAM_NO_DEVICE, pvParamState, + HWPerfDisableCustomCounterFilter, psHints->bHWPerfDisableCustomCounterFilter); SrvInitParamGetUINT32(INITPARAM_NO_DEVICE, pvParamState, HWPerfHostBufSizeInKB, psHints->ui32HWPerfHostBufSize); SrvInitParamGetUINT32(INITPARAM_NO_DEVICE, pvParamState, HWPerfFWBufSizeInKB, psHints->ui32HWPerfFWBufSize); SrvInitParamGetUINT32(psDevInfo->psDeviceNode, pvParamState, KernelCCBSizeLog2, psHints->ui32KCCBSizeLog2); @@ -381,9 +392,11 @@ static INLINE void GetApphints(PVRSRV_RGXDEV_INFO *psDevInfo, RGX_SRVINIT_APPHIN SrvInitParamGetUINT32(INITPARAM_NO_DEVICE, pvParamState, TPUTrilinearFracMaskCDM, psHints->aui32TPUTrilinearFracMask[RGXFWIF_TPU_DM_CDM]); SrvInitParamGetUINT32(INITPARAM_NO_DEVICE, pvParamState, TPUTrilinearFracMaskTDM, psHints->aui32TPUTrilinearFracMask[RGXFWIF_TPU_DM_TDM]); SrvInitParamGetBOOL(INITPARAM_NO_DEVICE, pvParamState, ValidateIrq, psHints->bValidateIrq); + SrvInitParamGetBOOL(INITPARAM_NO_DEVICE, pvParamState, ValidateSOCUSCTimer, psHints->bValidateSOCUSCTimer); SrvInitParamGetUINT32(INITPARAM_NO_DEVICE, pvParamState, FBCDCVersionOverride, psHints->ui32FBCDCVersionOverride); SrvInitParamGetUINT32(INITPARAM_NO_DEVICE, pvParamState, TFBCCompressionControlGroup, psHints->ui32TFBCCompressionControlGroup); SrvInitParamGetUINT32(INITPARAM_NO_DEVICE, pvParamState, TFBCCompressionControlScheme, psHints->ui32TFBCCompressionControlScheme); + SrvInitParamGetUINT32(INITPARAM_NO_DEVICE, pvParamState, TFBCCompressionControlYUVFormat, psHints->bTFBCCompressionControlYUVFormat); #endif /* @@ -435,7 +448,9 @@ static INLINE void GetFWConfigFlags(PVRSRV_DEVICE_NODE *psDeviceNode, IMG_UINT32 *pui32FWConfigFlagsExt, IMG_UINT32 *pui32FwOsCfgFlags) { +#if defined(SUPPORT_VALIDATION) PVRSRV_RGXDEV_INFO *psDevInfo = psDeviceNode->pvDevice; +#endif IMG_UINT32 ui32FWConfigFlags = 0; IMG_UINT32 ui32FWConfigFlagsExt = 0; @@ -457,9 +472,6 @@ static INLINE void GetFWConfigFlags(PVRSRV_DEVICE_NODE *psDeviceNode, ui32FWConfigFlags |= psHints->bEnableSoftResetCsw ? RGXFWIF_INICFG_CTXSWITCH_SRESET_EN : 0; ui32FWConfigFlags |= (psHints->ui32HWPerfFilter0 != 0 || psHints->ui32HWPerfFilter1 != 0) ? RGXFWIF_INICFG_HWPERF_EN : 0; ui32FWConfigFlags |= psHints->bHWPerfDisableCustomCounterFilter ? RGXFWIF_INICFG_HWP_DISABLE_FILTER : 0; - ui32FWConfigFlags |= (psHints->eFirmwarePerf == FW_PERF_CONF_CUSTOM_TIMER) ? RGXFWIF_INICFG_CUSTOM_PERF_TIMER_EN : 0; - ui32FWConfigFlags |= (psHints->eFirmwarePerf == FW_PERF_CONF_POLLS) ? RGXFWIF_INICFG_POLL_COUNTERS_EN : 0; - ui32FWConfigFlags |= (psHints->ui32VDMContextSwitchMode << RGXFWIF_INICFG_VDM_CTX_STORE_MODE_SHIFT) & RGXFWIF_INICFG_VDM_CTX_STORE_MODE_MASK; ui32FWConfigFlags |= (psHints->ui32FWContextSwitchProfile << RGXFWIF_INICFG_CTXSWITCH_PROFILE_SHIFT) & RGXFWIF_INICFG_CTXSWITCH_PROFILE_MASK; #if defined(SUPPORT_VALIDATION) @@ -478,17 +490,29 @@ static INLINE void GetFWConfigFlags(PVRSRV_DEVICE_NODE *psDeviceNode, } #if defined(SUPPORT_VALIDATION) - if (RGX_IS_FEATURE_SUPPORTED(psDevInfo, TFBC_LOSSY_37_PERCENT) || RGX_IS_FEATURE_SUPPORTED(psDevInfo, TFBC_DELTA_CORRELATION)) + ui32FWConfigFlags |= psHints->bValidateSOCUSCTimer ? RGXFWIF_INICFG_VALIDATE_SOCUSC_TIMER : 0; + + if ((ui32FWConfigFlags & RGXFWIF_INICFG_VALIDATE_SOCUSC_TIMER) && + ((psHints->eRGXActivePMConf != 0) || (psHints->eRGXRDPowerIslandConf != 0))) + { + psHints->eRGXActivePMConf = 0; + psHints->eRGXRDPowerIslandConf = 0; + PVR_DPF((PVR_DBG_WARNING, "SoC/USC Timer test needs to run with both EnableAPM and EnableRDPowerIsland disabled.\n" + "Overriding current value for both with new value 0.")); + } + + if (RGX_IS_FEATURE_SUPPORTED(psDevInfo, TFBC_LOSSY_37_PERCENT) || + RGX_IS_FEATURE_SUPPORTED(psDevInfo, TFBC_DELTA_CORRELATION) || + RGX_IS_FEATURE_SUPPORTED(psDevInfo, TFBC_NATIVE_YUV10)) { ui32FWConfigFlagsExt |= ((((psHints->ui32TFBCCompressionControlGroup << RGX_CR_TFBC_COMPRESSION_CONTROL_GROUP_CONTROL_SHIFT) & ~RGX_CR_TFBC_COMPRESSION_CONTROL_GROUP_CONTROL_CLRMSK) | ((psHints->ui32TFBCCompressionControlScheme << RGX_CR_TFBC_COMPRESSION_CONTROL_SCHEME_SHIFT) & - ~RGX_CR_TFBC_COMPRESSION_CONTROL_SCHEME_CLRMSK)) + ~RGX_CR_TFBC_COMPRESSION_CONTROL_SCHEME_CLRMSK) | + ((psHints->bTFBCCompressionControlYUVFormat) ? RGX_CR_TFBC_COMPRESSION_CONTROL_YUV10_OVERRIDE_EN : 0)) << RGXFWIF_INICFG_EXT_TFBC_CONTROL_SHIFT) & RGXFWIF_INICFG_EXT_TFBC_CONTROL_MASK; } -#else - PVR_UNREFERENCED_PARAMETER(psDevInfo); #endif } @@ -593,11 +617,14 @@ static PVRSRV_ERROR RGXTDProcessFWImage(PVRSRV_DEVICE_NODE *psDeviceNode, sTDFWParams.pvFirmware = OSFirmwareData(psRGXFW); sTDFWParams.ui32FirmwareSize = OSFirmwareSize(psRGXFW); +#if defined(RGX_FEATURE_META_IDX) if (RGX_IS_FEATURE_VALUE_SUPPORTED(psDevInfo, META)) { sTDFWParams.uFWP.sMeta = puFWParams->sMeta; } - else if (RGX_IS_FEATURE_SUPPORTED(psDevInfo, MIPS)) + else +#endif + if (RGX_IS_FEATURE_SUPPORTED(psDevInfo, MIPS)) { sTDFWParams.uFWP.sMips = puFWParams->sMips; @@ -743,8 +770,13 @@ static PVRSRV_ERROR InitFirmware(PVRSRV_DEVICE_NODE *psDeviceNode, PVRSRV_RGXDEV_INFO *psDevInfo = (PVRSRV_RGXDEV_INFO *)psDeviceNode->pvDevice; #if defined(SUPPORT_TRUSTED_DEVICE) && !defined(NO_HARDWARE) && !defined(SUPPORT_SECURITY_VALIDATION) - IMG_BOOL bUseSecureFWData = RGX_IS_FEATURE_VALUE_SUPPORTED(psDevInfo, META) || + IMG_BOOL bUseSecureFWData = +#if defined(RGX_FEATURE_META_IDX) + RGX_IS_FEATURE_VALUE_SUPPORTED(psDevInfo, META) || +#endif +#if defined(RGX_FEATURE_RISCV_FW_PROCESSOR_BIT_MASK) RGX_IS_FEATURE_SUPPORTED(psDevInfo, RISCV_FW_PROCESSOR) || +#endif (RGX_IS_FEATURE_SUPPORTED(psDevInfo, MIPS) && RGX_GET_FEATURE_VALUE(psDevInfo, PHYS_BUS_WIDTH) > 32); #endif @@ -784,7 +816,7 @@ static PVRSRV_ERROR InitFirmware(PVRSRV_DEVICE_NODE *psDeviceNode, psDevInfo->ui32FWCodeSizeInBytes = uiFWCodeAllocSize; -#if defined(SUPPORT_TRUSTED_DEVICE) +#if defined(SUPPORT_TRUSTED_DEVICE) && defined(RGX_FEATURE_META_DMA_BIT_MASK) /* Disable META core memory allocation unless the META DMA is available */ if (!RGX_DEVICE_HAS_FEATURE(&sLayerParams, META_DMA)) { @@ -875,7 +907,9 @@ static PVRSRV_ERROR InitFirmware(PVRSRV_DEVICE_NODE *psDeviceNode, goto release_fw_allocations; } } - else if (RGX_IS_FEATURE_VALUE_SUPPORTED(psDevInfo, META)) + else +#if defined(RGX_FEATURE_META_MAX_VALUE_IDX) + if (RGX_IS_FEATURE_VALUE_SUPPORTED(psDevInfo, META)) { uFWParams.sMeta.sFWCodeDevVAddr = psDevInfo->sFWCodeDevVAddrBase; uFWParams.sMeta.sFWDataDevVAddr = psDevInfo->sFWDataDevVAddrBase; @@ -891,6 +925,7 @@ static PVRSRV_ERROR InitFirmware(PVRSRV_DEVICE_NODE *psDeviceNode, #endif } else +#endif { uFWParams.sRISCV.sFWCorememCodeDevVAddr = psDevInfo->sFWCorememCodeDevVAddrBase; uFWParams.sRISCV.sFWCorememCodeFWAddr = psDevInfo->sFWCorememCodeFWAddr; @@ -1051,6 +1086,7 @@ static void InitialiseHWPerfCounters(PVRSRV_DEVICE_NODE *psDeviceNode, RGXFWIF_HWPERF_CTL *psHWPerfInitDataInt) { RGXFWIF_HWPERF_CTL_BLK *psHWPerfInitBlkData; + RGXFWIF_HWPERF_DA_BLK *psHWPerfInitDABlkData; IMG_UINT32 ui32CntBlkModelLen; const RGXFW_HWPERF_CNTBLK_TYPE_MODEL *asCntBlkTypeModel; const RGXFW_HWPERF_CNTBLK_TYPE_MODEL* psBlkTypeDesc; @@ -1058,8 +1094,15 @@ static void InitialiseHWPerfCounters(PVRSRV_DEVICE_NODE *psDeviceNode, RGX_HWPERF_CNTBLK_RT_INFO sCntBlkRtInfo; ui32CntBlkModelLen = RGXGetHWPerfBlockConfig(&asCntBlkTypeModel); + + PDUMPCOMMENTWITHFLAGS(psDeviceNode, PDUMP_FLAGS_CONTINUOUS, + "HWPerf Counter Config starts here."); + for (ui32BlkCfgIdx = 0; ui32BlkCfgIdx < ui32CntBlkModelLen; ui32BlkCfgIdx++) { + IMG_UINT32 uiUnit; + IMG_BOOL bDirect; + /* Exit early if this core does not have any of these counter blocks * due to core type/BVNC features.... */ psBlkTypeDesc = &asCntBlkTypeModel[ui32BlkCfgIdx]; @@ -1071,64 +1114,130 @@ static void InitialiseHWPerfCounters(PVRSRV_DEVICE_NODE *psDeviceNode, /* Program all counters in one block so those already on may * be configured off and vice-a-versa. */ for (ui32BlockID = psBlkTypeDesc->ui32CntBlkIdBase; - ui32BlockID < psBlkTypeDesc->ui32CntBlkIdBase+sCntBlkRtInfo.ui32NumUnits; - ui32BlockID++) + ui32BlockID < psBlkTypeDesc->ui32CntBlkIdBase+sCntBlkRtInfo.ui32NumUnits; + ui32BlockID++) { - PDUMPCOMMENTWITHFLAGS(psDeviceNode, PDUMP_FLAGS_CONTINUOUS, "Unit %d Block : %s", ui32BlockID-psBlkTypeDesc->ui32CntBlkIdBase, psBlkTypeDesc->pszBlockNameComment); + /* Get the block configure store to update from the global store of * block configuration. This is used to remember the configuration - * between configurations and core power on in APM */ - psHWPerfInitBlkData = rgxfw_hwperf_get_block_ctl(ui32BlockID, psHWPerfInitDataInt); - /* Assert to check for HWPerf block mis-configuration */ - PVR_ASSERT(psHWPerfInitBlkData); + * between configurations and core power on in APM. + * For RGX_FEATURE_HWPERF_OCEANIC layout we have a different + * structure type to decode the HWPerf block. This is indicated by + * the RGX_CNTBLK_ID_DA_MASK bit being set in the block-ID value. */ - psHWPerfInitBlkData->bValid = IMG_TRUE; - PDUMPCOMMENTWITHFLAGS(psDeviceNode, PDUMP_FLAGS_CONTINUOUS, + bDirect = (psBlkTypeDesc->ui32IndirectReg == 0U); + uiUnit = ui32BlockID - psBlkTypeDesc->ui32CntBlkIdBase; + + if ((ui32BlockID & RGX_CNTBLK_ID_DA_MASK) == RGX_CNTBLK_ID_DA_MASK) + { + psHWPerfInitDABlkData = rgxfw_hwperf_get_da_block_ctl(ui32BlockID, psHWPerfInitDataInt); + + PVR_ASSERT(psHWPerfInitDABlkData); + + psHWPerfInitDABlkData->eBlockID = ui32BlockID; + PDUMPCOMMENTWITHFLAGS(psDeviceNode, PDUMP_FLAGS_CONTINUOUS, + "eBlockID: The Block ID for the layout block. See RGX_HWPERF_CNTBLK_ID for further information."); + DevmemPDumpLoadMemValue32(psHWPerfDataMemDesc, + (size_t)&(psHWPerfInitDABlkData->eBlockID) - (size_t)(psHWPerfInitDataInt), + psHWPerfInitDABlkData->eBlockID, + PDUMP_FLAGS_CONTINUOUS); + + psHWPerfInitDABlkData->uiEnabled = 0U; + PDUMPCOMMENTWITHFLAGS(psDeviceNode, PDUMP_FLAGS_CONTINUOUS, + "uiEnabled: Set to 0x1 if the block needs to be enabled during playback."); + DevmemPDumpLoadMemValue32(psHWPerfDataMemDesc, + (size_t)&(psHWPerfInitDABlkData->uiEnabled) - (size_t)(psHWPerfInitDataInt), + psHWPerfInitDABlkData->uiEnabled, + PDUMP_FLAGS_CONTINUOUS); + + psHWPerfInitDABlkData->uiNumCounters = 0U; + PDUMPCOMMENTWITHFLAGS(psDeviceNode, PDUMP_FLAGS_CONTINUOUS, + "uiNumCounters (X): Specifies the number of valid counters" + " [0..%d] which follow.", RGX_CNTBLK_COUNTERS_MAX); + DevmemPDumpLoadMemValue32(psHWPerfDataMemDesc, + (size_t)&(psHWPerfInitDABlkData->uiNumCounters) - (size_t)(psHWPerfInitDataInt), + psHWPerfInitDABlkData->uiNumCounters, + PDUMP_FLAGS_CONTINUOUS); + + for (ui32CounterIdx = 0; ui32CounterIdx < RGX_CNTBLK_COUNTERS_MAX; ui32CounterIdx++) + { + psHWPerfInitDABlkData->aui32Counters[ui32CounterIdx] = IMG_UINT32_C(0x00000000); + + if (bDirect) + { + PDUMPCOMMENTWITHFLAGS(psDeviceNode, PDUMP_FLAGS_CONTINUOUS, + "%s_COUNTER_%d", + psBlkTypeDesc->pszBlockNameComment, + ui32CounterIdx); + } + else + { + PDUMPCOMMENTWITHFLAGS(psDeviceNode, PDUMP_FLAGS_CONTINUOUS, + "%s%d_COUNTER_%d", + psBlkTypeDesc->pszBlockNameComment, + uiUnit, ui32CounterIdx); + } + + DevmemPDumpLoadMemValue32(psHWPerfDataMemDesc, + (size_t)&(psHWPerfInitDABlkData->aui32Counters[ui32CounterIdx]) - (size_t)(psHWPerfInitDataInt), + psHWPerfInitDABlkData->aui32Counters[ui32CounterIdx], + PDUMP_FLAGS_CONTINUOUS); + } + } + else + { + psHWPerfInitBlkData = rgxfw_hwperf_get_block_ctl(ui32BlockID, psHWPerfInitDataInt); + /* Assert to check for HWPerf block mis-configuration */ + PVR_ASSERT(psHWPerfInitBlkData); + + psHWPerfInitBlkData->bValid = IMG_TRUE; + PDUMPCOMMENTWITHFLAGS(psDeviceNode, PDUMP_FLAGS_CONTINUOUS, "bValid: This specifies if the layout block is valid for the given BVNC."); - DevmemPDumpLoadMemValue32(psHWPerfDataMemDesc, + DevmemPDumpLoadMemValue32(psHWPerfDataMemDesc, (size_t)&(psHWPerfInitBlkData->bValid) - (size_t)(psHWPerfInitDataInt), psHWPerfInitBlkData->bValid, PDUMP_FLAGS_CONTINUOUS); - psHWPerfInitBlkData->bEnabled = IMG_FALSE; - PDUMPCOMMENTWITHFLAGS(psDeviceNode, PDUMP_FLAGS_CONTINUOUS, + psHWPerfInitBlkData->bEnabled = IMG_FALSE; + PDUMPCOMMENTWITHFLAGS(psDeviceNode, PDUMP_FLAGS_CONTINUOUS, "bEnabled: Set to 0x1 if the block needs to be enabled during playback."); - DevmemPDumpLoadMemValue32(psHWPerfDataMemDesc, + DevmemPDumpLoadMemValue32(psHWPerfDataMemDesc, (size_t)&(psHWPerfInitBlkData->bEnabled) - (size_t)(psHWPerfInitDataInt), psHWPerfInitBlkData->bEnabled, PDUMP_FLAGS_CONTINUOUS); - psHWPerfInitBlkData->eBlockID = ui32BlockID; - PDUMPCOMMENTWITHFLAGS(psDeviceNode, PDUMP_FLAGS_CONTINUOUS, + psHWPerfInitBlkData->eBlockID = ui32BlockID; + PDUMPCOMMENTWITHFLAGS(psDeviceNode, PDUMP_FLAGS_CONTINUOUS, "eBlockID: The Block ID for the layout block. See RGX_HWPERF_CNTBLK_ID for further information."); - DevmemPDumpLoadMemValue32(psHWPerfDataMemDesc, + DevmemPDumpLoadMemValue32(psHWPerfDataMemDesc, (size_t)&(psHWPerfInitBlkData->eBlockID) - (size_t)(psHWPerfInitDataInt), psHWPerfInitBlkData->eBlockID, PDUMP_FLAGS_CONTINUOUS); - psHWPerfInitBlkData->uiCounterMask = 0x00; - PDUMPCOMMENTWITHFLAGS(psDeviceNode, PDUMP_FLAGS_CONTINUOUS, + psHWPerfInitBlkData->uiCounterMask = 0x00; + PDUMPCOMMENTWITHFLAGS(psDeviceNode, PDUMP_FLAGS_CONTINUOUS, "uiCounterMask: Bitmask for selecting the counters that need to be configured. (Bit 0 - counter0, bit 1 - counter1 and so on.)"); - DevmemPDumpLoadMemValue32(psHWPerfDataMemDesc, + DevmemPDumpLoadMemValue32(psHWPerfDataMemDesc, (size_t)&(psHWPerfInitBlkData->uiCounterMask) - (size_t)(psHWPerfInitDataInt), psHWPerfInitBlkData->uiCounterMask, PDUMP_FLAGS_CONTINUOUS); - for (ui32CounterIdx = RGX_CNTBLK_COUNTER0_ID; ui32CounterIdx < psBlkTypeDesc->ui8NumCounters; ui32CounterIdx++) - { - psHWPerfInitBlkData->aui64CounterCfg[ui32CounterIdx] = IMG_UINT64_C(0x0000000000000000); + for (ui32CounterIdx = RGX_CNTBLK_COUNTER0_ID; ui32CounterIdx < psBlkTypeDesc->ui8NumCounters; ui32CounterIdx++) + { + psHWPerfInitBlkData->aui64CounterCfg[ui32CounterIdx] = IMG_UINT64_C(0x0000000000000000); - PDUMPCOMMENTWITHFLAGS(psDeviceNode, PDUMP_FLAGS_CONTINUOUS, + PDUMPCOMMENTWITHFLAGS(psDeviceNode, PDUMP_FLAGS_CONTINUOUS, "%s_COUNTER_%d", psBlkTypeDesc->pszBlockNameComment, ui32CounterIdx); - DevmemPDumpLoadMemValue64(psHWPerfDataMemDesc, + DevmemPDumpLoadMemValue64(psHWPerfDataMemDesc, (size_t)&(psHWPerfInitBlkData->aui64CounterCfg[ui32CounterIdx]) - (size_t)(psHWPerfInitDataInt), psHWPerfInitBlkData->aui64CounterCfg[ui32CounterIdx], PDUMP_FLAGS_CONTINUOUS); + } } } } @@ -1316,7 +1425,7 @@ PVRSRV_ERROR RGXInit(PVRSRV_DEVICE_NODE *psDeviceNode) RGX_SRVINIT_APPHINTS sApphints = {0}; IMG_UINT32 ui32FWConfigFlags, ui32FWConfigFlagsExt, ui32FwOsCfgFlags; IMG_UINT32 ui32DeviceFlags; - IMG_BOOL bPowerDown = (psDeviceNode->eCurrentSysPowerState == PVRSRV_SYS_POWER_STATE_OFF); + IMG_BOOL bPowerDown = (psDeviceNode->eCurrentSysPowerState == PVRSRV_SYS_POWER_STATE_OFF); PVRSRV_RGXDEV_INFO *psDevInfo = (PVRSRV_RGXDEV_INFO *)psDeviceNode->pvDevice; RGX_LAYER_PARAMS sLayerParams; @@ -1343,7 +1452,6 @@ PVRSRV_ERROR RGXInit(PVRSRV_DEVICE_NODE *psDeviceNode) psDevInfo->sDevFeatureCfg.ui32N, psDevInfo->sDevFeatureCfg.ui32C); - /* Power-up the device as required to read the registers */ if (bPowerDown) { @@ -1419,11 +1527,15 @@ PVRSRV_ERROR RGXInit(PVRSRV_DEVICE_NODE *psDeviceNode) } /* Set which HW Safety Events will be handled by the driver */ +#if defined(RGX_FEATURE_WATCHDOG_TIMER_BIT_MASK) psDevInfo->ui32HostSafetyEventMask |= RGX_IS_FEATURE_SUPPORTED(psDevInfo, WATCHDOG_TIMER) ? RGX_CR_SAFETY_EVENT_STATUS__ROGUEXE__WATCHDOG_TIMEOUT_EN : 0; +#endif +#if defined(RGX_FEATURE_ECC_RAMS_MAX_VALUE_IDX) psDevInfo->ui32HostSafetyEventMask |= (RGX_DEVICE_HAS_FEATURE_VALUE(&sLayerParams, ECC_RAMS) && (RGX_DEVICE_GET_FEATURE_VALUE(&sLayerParams, ECC_RAMS) > 0)) ? RGX_CR_SAFETY_EVENT_STATUS__ROGUEXE__FAULT_FW_EN : 0; +#endif /* Services initialisation parameters */ _ParseHTBAppHints(psDeviceNode); diff --git a/drivers/gpu/drm/img-rogue/rgxstartstop.c b/drivers/gpu/drm/img-rogue/rgxstartstop.c index 105cefbba..2d213e354 100644 --- a/drivers/gpu/drm/img-rogue/rgxstartstop.c +++ b/drivers/gpu/drm/img-rogue/rgxstartstop.c @@ -76,6 +76,7 @@ static void RGXEnableClocks(const void *hPrivate) RGXCommentLog(hPrivate, "RGX clock: use default (automatic clock gating)"); } +#if defined(RGX_FEATURE_META_MAX_VALUE_IDX) static PVRSRV_ERROR RGXWriteMetaRegThroughSP(const void *hPrivate, IMG_UINT32 ui32RegAddr, IMG_UINT32 ui32RegValue) { PVRSRV_ERROR eError = PVRSRV_OK; @@ -224,7 +225,7 @@ static void RGXInitMetaProcWrapper(const void *hPrivate) RGXCommentLog(hPrivate, "RGXStart: Configure META wrapper"); RGXWriteReg64(hPrivate, RGX_CR_MTS_GARTEN_WRAPPER_CONFIG, ui64GartenConfig); } - +#endif /*! ******************************************************************************* @@ -295,6 +296,7 @@ static void RGXInitMipsProcWrapper(const void *hPrivate) ~RGX_CR_MIPS_ADDR_REMAP1_CONFIG2_ADDR_OUT_CLRMSK, ui64RemapSettings); +#if defined(FIX_HW_BRN_63553_BIT_MASK) if (RGX_DEVICE_HAS_BRN(hPrivate, 63553)) { IMG_BOOL bPhysBusAbove32Bit = RGXGetDevicePhysBusWidth(hPrivate) > 32; @@ -312,6 +314,7 @@ static void RGXInitMipsProcWrapper(const void *hPrivate) ui64RemapSettings); } } +#endif /* * Data remap setup @@ -407,6 +410,7 @@ static void RGXInitMipsProcWrapper(const void *hPrivate) } +#if defined(RGX_FEATURE_RISCV_FW_PROCESSOR_BIT_MASK) /*! ******************************************************************************* @@ -452,6 +456,7 @@ static void RGXInitRiscvProcWrapper(const void *hPrivate) RGXCommentLog(hPrivate, "RGXStart: Set GARTEN_IDLE type to RISCV"); RGXWriteReg64(hPrivate, RGX_CR_MTS_GARTEN_WRAPPER_CONFIG, RGX_CR_MTS_GARTEN_WRAPPER_CONFIG_IDLE_CTRL_META); } +#endif /*! @@ -468,6 +473,7 @@ static void RGXInitRiscvProcWrapper(const void *hPrivate) ******************************************************************************/ static void __RGXInitSLC(const void *hPrivate) { +#if defined(RGX_FEATURE_S7_CACHE_HIERARCHY_BIT_MASK) if (RGX_DEVICE_HAS_FEATURE(hPrivate, S7_CACHE_HIERARCHY)) { IMG_UINT32 ui32Reg; @@ -536,6 +542,7 @@ static void __RGXInitSLC(const void *hPrivate) } } else +#endif { IMG_UINT32 ui32Reg; IMG_UINT32 ui32RegVal; @@ -547,6 +554,7 @@ static void __RGXInitSLC(const void *hPrivate) ui32Reg = RGX_CR_SLC_CTRL_BYPASS; ui64RegVal = 0; +#if defined(RGX_CR_SLC_CTRL_BYPASS_REQ_IPF_OBJ_EN) if ((RGX_DEVICE_GET_FEATURE_VALUE(hPrivate, SLC_SIZE_IN_KILOBYTES) == 8) || RGX_DEVICE_HAS_BRN(hPrivate, 61450)) { @@ -554,6 +562,7 @@ static void __RGXInitSLC(const void *hPrivate) ui64RegVal |= (IMG_UINT64) RGX_CR_SLC_CTRL_BYPASS_REQ_IPF_OBJ_EN | (IMG_UINT64) RGX_CR_SLC_CTRL_BYPASS_REQ_IPF_CPF_EN; } +#endif if (ui64RegVal != 0) { @@ -567,9 +576,13 @@ static void __RGXInitSLC(const void *hPrivate) * 32bits (RGX_CR_SLC_CTRL_MISC_SCRAMBLE_BITS) unchanged from the HW default. */ ui32Reg = RGX_CR_SLC_CTRL_MISC; - ui32RegVal = (RGXReadReg32(hPrivate, ui32Reg) & RGX_CR_SLC_CTRL_MISC_ENABLE_PSG_HAZARD_CHECK_EN) | - RGX_CR_SLC_CTRL_MISC_ADDR_DECODE_MODE_PVR_HASH1; + ui32RegVal = RGX_CR_SLC_CTRL_MISC_ADDR_DECODE_MODE_PVR_HASH1; +#if !defined(RGX_FEATURE_XE_ARCHITECTURE) || (RGX_FEATURE_XE_ARCHITECTURE == 1) + ui32RegVal |= RGXReadReg32(hPrivate, ui32Reg) & RGX_CR_SLC_CTRL_MISC_ENABLE_PSG_HAZARD_CHECK_EN; +#endif + +#if defined(FIX_HW_BRN_60084_BIT_MASK) if (RGX_DEVICE_HAS_BRN(hPrivate, 60084)) { #if !defined(SOC_FEATURE_STRICT_SAME_ADDRESS_WRITE_ORDERING) @@ -581,11 +594,15 @@ static void __RGXInitSLC(const void *hPrivate) } #endif } +#endif + +#if !defined(RGX_FEATURE_XE_ARCHITECTURE) || (RGX_FEATURE_XE_ARCHITECTURE == 1) /* Bypass burst combiner if SLC line size is smaller than 1024 bits */ if (RGXGetDeviceCacheLineSize(hPrivate) < 1024) { ui32RegVal |= RGX_CR_SLC_CTRL_MISC_BYPASS_BURST_COMBINER_EN; } +#endif RGXWriteReg32(hPrivate, ui32Reg, ui32RegVal); } @@ -620,6 +637,7 @@ static void RGXInitBIF(const void *hPrivate) */ RGXCommentLog(hPrivate, "RGX firmware MMU Page Catalogue"); +#if defined(RGX_FEATURE_SLC_VIVT_BIT_MASK) if (!RGX_DEVICE_HAS_FEATURE(hPrivate, SLC_VIVT)) { /* Write the cat-base address */ @@ -632,6 +650,7 @@ static void RGXInitBIF(const void *hPrivate) << RGX_CR_BIF_CAT_BASE0_ADDR_SHIFT) & ~RGX_CR_BIF_CAT_BASE0_ADDR_CLRMSK); +#if defined(RGX_FEATURE_RISCV_FW_PROCESSOR_BIT_MASK) if (RGX_DEVICE_HAS_FEATURE(hPrivate, RISCV_FW_PROCESSOR)) { /* Keep catbase registers in sync */ @@ -644,6 +663,7 @@ static void RGXInitBIF(const void *hPrivate) << RGX_CR_FWCORE_MEM_CAT_BASE0_ADDR_SHIFT) & ~RGX_CR_FWCORE_MEM_CAT_BASE0_ADDR_CLRMSK); } +#endif /* * Trusted Firmware boot @@ -654,7 +674,9 @@ static void RGXInitBIF(const void *hPrivate) #endif } else +#endif /* defined(RGX_FEATURE_SLC_VIVT_BIT_MASK) */ { +#if defined(RGX_CR_MMU_CBASE_MAPPING) // FIXME_OCEANIC IMG_UINT32 uiPCAddr; uiPCAddr = (((sPCAddr.uiAddr >> RGX_CR_MMU_CBASE_MAPPING_BASE_ADDR_ALIGNSHIFT) << RGX_CR_MMU_CBASE_MAPPING_BASE_ADDR_SHIFT) @@ -681,6 +703,7 @@ static void RGXInitBIF(const void *hPrivate) RGX_CR_MMU_CBASE_MAPPING_BASE_ADDR_ALIGNSHIFT, RGX_CR_MMU_CBASE_MAPPING_BASE_ADDR_SHIFT, uiPCAddr); +#endif #endif } } @@ -726,18 +749,22 @@ static void RGXAXIACELiteInit(const void *hPrivate) (2U << RGX_CR_AXI_ACE_LITE_CONFIGURATION_ARCACHE_COHERENT_SHIFT) | (2U << RGX_CR_AXI_ACE_LITE_CONFIGURATION_ARCACHE_CACHE_MAINTENANCE_SHIFT); +#if defined(FIX_HW_BRN_42321_BIT_MASK) if (RGX_DEVICE_HAS_BRN(hPrivate, 42321)) { ui64RegVal |= (((IMG_UINT64) 1) << RGX_CR_AXI_ACE_LITE_CONFIGURATION_DISABLE_COHERENT_WRITELINEUNIQUE_SHIFT); } +#endif +#if defined(FIX_HW_BRN_68186_BIT_MASK) if (RGX_DEVICE_HAS_BRN(hPrivate, 68186)) { /* default value for reg_enable_fence_out is zero. Force to 1 to allow core_clk < mem_clk */ ui64RegVal |= (IMG_UINT64)1 << RGX_CR_AXI_ACE_LITE_CONFIGURATION_ENABLE_FENCE_OUT_SHIFT; } +#endif -#if defined(SUPPORT_TRUSTED_DEVICE) +#if defined(SUPPORT_TRUSTED_DEVICE) && defined(RGX_FEATURE_SLC_VIVT_BIT_MASK) if (RGX_DEVICE_HAS_FEATURE(hPrivate, SLC_VIVT)) { RGXCommentLog(hPrivate, "OSID 0 and 1 are trusted"); @@ -753,28 +780,27 @@ static void RGXAXIACELiteInit(const void *hPrivate) PVRSRV_ERROR RGXStart(const void *hPrivate) { PVRSRV_ERROR eError = PVRSRV_OK; - IMG_BOOL bDoFWSlaveBoot; - IMG_CHAR *pcRGXFW_PROCESSOR; - IMG_BOOL bMetaFW; + IMG_CHAR *pcRGXFW_PROCESSOR = RGXFW_PROCESSOR_MIPS; +#if defined(RGX_FEATURE_META_MAX_VALUE_IDX) + IMG_BOOL bDoFWSlaveBoot = IMG_FALSE; + IMG_BOOL bMetaFW = IMG_FALSE; +#endif - if (RGX_DEVICE_HAS_FEATURE(hPrivate, MIPS)) - { - pcRGXFW_PROCESSOR = RGXFW_PROCESSOR_MIPS; - bMetaFW = IMG_FALSE; - bDoFWSlaveBoot = IMG_FALSE; - } - else if (RGX_DEVICE_HAS_FEATURE(hPrivate, RISCV_FW_PROCESSOR)) +#if defined(RGX_FEATURE_RISCV_FW_PROCESSOR_BIT_MASK) + if (RGX_DEVICE_HAS_FEATURE(hPrivate, RISCV_FW_PROCESSOR)) { pcRGXFW_PROCESSOR = RGXFW_PROCESSOR_RISCV; - bMetaFW = IMG_FALSE; - bDoFWSlaveBoot = IMG_FALSE; } else +#endif +#if defined(RGX_FEATURE_META_MAX_VALUE_IDX) + if (RGX_DEVICE_HAS_FEATURE_VALUE(hPrivate, META)) { pcRGXFW_PROCESSOR = RGXFW_PROCESSOR_META; bMetaFW = IMG_TRUE; bDoFWSlaveBoot = RGXDoFWSlaveBoot(hPrivate); } +#endif if (RGX_DEVICE_HAS_FEATURE(hPrivate, SYS_BUS_SECURE_RESET)) { @@ -795,6 +821,7 @@ PVRSRV_ERROR RGXStart(const void *hPrivate) #define RGX_CR_SOFT_RESET_ALL (RGX_CR_SOFT_RESET_MASKFULL) #endif +#if defined(RGX_S7_SOFT_RESET_DUSTS) if (RGX_DEVICE_HAS_FEATURE(hPrivate, S7_TOP_INFRASTRUCTURE)) { /* Set RGX in soft-reset */ @@ -826,6 +853,7 @@ PVRSRV_ERROR RGXStart(const void *hPrivate) (void) RGXReadReg64(hPrivate, RGX_CR_SOFT_RESET); } else +#endif { /* Set RGX in soft-reset */ RGXCommentLog(hPrivate, "RGXStart: soft reset everything"); @@ -842,7 +870,12 @@ PVRSRV_ERROR RGXStart(const void *hPrivate) /* Take everything out of reset but the FW processor */ RGXCommentLog(hPrivate, "RGXStart: Take everything out of reset but %s", pcRGXFW_PROCESSOR); + +#if defined(RGX_FEATURE_XE_ARCHITECTURE) && (RGX_FEATURE_XE_ARCHITECTURE > 1) + RGXWriteReg64(hPrivate, RGX_CR_SOFT_RESET, RGX_CR_SOFT_RESET_CPU_EN); +#else RGXWriteReg64(hPrivate, RGX_CR_SOFT_RESET, RGX_CR_SOFT_RESET_GARTEN_EN); +#endif (void) RGXReadReg64(hPrivate, RGX_CR_SOFT_RESET); } @@ -864,6 +897,7 @@ PVRSRV_ERROR RGXStart(const void *hPrivate) RGX_CR_SAFETY_EVENT_ENABLE__ROGUEXE__MASKFULL); } +#if defined(RGX_FEATURE_META_MAX_VALUE_IDX) if (bMetaFW) { if (bDoFWSlaveBoot) @@ -880,19 +914,25 @@ PVRSRV_ERROR RGXStart(const void *hPrivate) RGXWriteReg32(hPrivate, RGX_CR_META_BOOT, RGX_CR_META_BOOT_MODE_EN); } } +#endif /* * Initialise Firmware wrapper */ - if (bMetaFW) - { - RGXInitMetaProcWrapper(hPrivate); - } - else if (RGX_DEVICE_HAS_FEATURE(hPrivate, RISCV_FW_PROCESSOR)) +#if defined(RGX_FEATURE_RISCV_FW_PROCESSOR_BIT_MASK) + if (RGX_DEVICE_HAS_FEATURE(hPrivate, RISCV_FW_PROCESSOR)) { RGXInitRiscvProcWrapper(hPrivate); } else +#endif +#if defined(RGX_FEATURE_META_MAX_VALUE_IDX) + if (bMetaFW) + { + RGXInitMetaProcWrapper(hPrivate); + } + else +#endif { RGXInitMipsProcWrapper(hPrivate); } @@ -919,6 +959,7 @@ PVRSRV_ERROR RGXStart(const void *hPrivate) /* ... and afterwards */ RGXWaitCycles(hPrivate, 32, 3); +#if defined(RGX_FEATURE_META_MAX_VALUE_IDX) if (bMetaFW && bDoFWSlaveBoot) { eError = RGXFabricCoherencyTest(hPrivate); @@ -929,9 +970,11 @@ PVRSRV_ERROR RGXStart(const void *hPrivate) if (eError != PVRSRV_OK) return eError; } else +#endif { RGXCommentLog(hPrivate, "RGXStart: RGX Firmware Master boot Start"); +#if defined(RGX_FEATURE_RISCV_FW_PROCESSOR_BIT_MASK) if (RGX_DEVICE_HAS_FEATURE(hPrivate, RISCV_FW_PROCESSOR)) { /* Bring Debug Module out of reset */ @@ -941,6 +984,7 @@ PVRSRV_ERROR RGXStart(const void *hPrivate) RGXWriteReg32(hPrivate, RGX_CR_FWCORE_BOOT, 1); RGXWaitCycles(hPrivate, 32, 3); } +#endif } #if defined(SUPPORT_TRUSTED_DEVICE) && !defined(SUPPORT_SECURITY_VALIDATION) @@ -954,10 +998,12 @@ PVRSRV_ERROR RGXStart(const void *hPrivate) PVRSRV_ERROR RGXStop(const void *hPrivate) { +#if defined(RGX_FEATURE_META_MAX_VALUE_IDX) || defined(RGX_FEATURE_RISCV_FW_PROCESSOR_BIT_MASK) IMG_BOOL bMipsFW = RGX_DEVICE_HAS_FEATURE(hPrivate, MIPS); IMG_BOOL bRiscvFW = RGX_DEVICE_HAS_FEATURE(hPrivate, RISCV_FW_PROCESSOR); IMG_BOOL bMetaFW = !bMipsFW && !bRiscvFW; - PVRSRV_ERROR eError; +#endif + PVRSRV_ERROR eError = PVRSRV_OK; RGX_LAYER_PARAMS *psParams; PVRSRV_RGXDEV_INFO *psDevInfo; PVR_ASSERT(hPrivate != NULL); @@ -969,25 +1015,29 @@ PVRSRV_ERROR RGXStop(const void *hPrivate) /* Wait for Sidekick/Jones to signal IDLE except for the Garten Wrapper * For LAYOUT_MARS = 1, SIDEKICK would have been powered down by FW */ +#if !defined(RGX_FEATURE_XE_ARCHITECTURE) || (RGX_FEATURE_XE_ARCHITECTURE == 1) if (!(PVRSRV_GET_DEVICE_FEATURE_VALUE(psDevInfo->psDeviceNode, LAYOUT_MARS) > 0)) { - if (!RGX_DEVICE_HAS_FEATURE(hPrivate, S7_TOP_INFRASTRUCTURE)) - { - eError = RGXPollReg32(hPrivate, - RGX_CR_SIDEKICK_IDLE, - RGX_CR_SIDEKICK_IDLE_MASKFULL^(RGX_CR_SIDEKICK_IDLE_GARTEN_EN|RGX_CR_SIDEKICK_IDLE_SOCIF_EN|RGX_CR_SIDEKICK_IDLE_HOSTIF_EN), - RGX_CR_SIDEKICK_IDLE_MASKFULL^(RGX_CR_SIDEKICK_IDLE_GARTEN_EN|RGX_CR_SIDEKICK_IDLE_SOCIF_EN|RGX_CR_SIDEKICK_IDLE_HOSTIF_EN)); - } - else +#if defined(RGX_FEATURE_S7_TOP_INFRASTRUCTURE_BIT_MASK) + if (RGX_DEVICE_HAS_FEATURE(hPrivate, S7_TOP_INFRASTRUCTURE)) { eError = RGXPollReg32(hPrivate, RGX_CR_JONES_IDLE, RGX_CR_JONES_IDLE_MASKFULL^(RGX_CR_JONES_IDLE_GARTEN_EN|RGX_CR_JONES_IDLE_SOCIF_EN|RGX_CR_JONES_IDLE_HOSTIF_EN), RGX_CR_JONES_IDLE_MASKFULL^(RGX_CR_JONES_IDLE_GARTEN_EN|RGX_CR_JONES_IDLE_SOCIF_EN|RGX_CR_JONES_IDLE_HOSTIF_EN)); } + else +#endif + { + eError = RGXPollReg32(hPrivate, + RGX_CR_SIDEKICK_IDLE, + RGX_CR_SIDEKICK_IDLE_MASKFULL^(RGX_CR_SIDEKICK_IDLE_GARTEN_EN|RGX_CR_SIDEKICK_IDLE_SOCIF_EN|RGX_CR_SIDEKICK_IDLE_HOSTIF_EN), + RGX_CR_SIDEKICK_IDLE_MASKFULL^(RGX_CR_SIDEKICK_IDLE_GARTEN_EN|RGX_CR_SIDEKICK_IDLE_SOCIF_EN|RGX_CR_SIDEKICK_IDLE_HOSTIF_EN)); + } if (eError != PVRSRV_OK) return eError; } +#endif if (!(PVRSRV_GET_DEVICE_FEATURE_VALUE(psDevInfo->psDeviceNode, LAYOUT_MARS) > 0)) { @@ -996,20 +1046,22 @@ PVRSRV_ERROR RGXStop(const void *hPrivate) * Wait for SLC to signal IDLE * For LAYOUT_MARS = 1, SLC would have been powered down by FW */ - if (!RGX_DEVICE_HAS_FEATURE(hPrivate, S7_TOP_INFRASTRUCTURE)) - { - eError = RGXPollReg32(hPrivate, - RGX_CR_SLC_IDLE, - RGX_CR_SLC_IDLE_MASKFULL, - RGX_CR_SLC_IDLE_MASKFULL); - } - else +#if defined(RGX_FEATURE_S7_TOP_INFRASTRUCTURE_BIT_MASK) + if (RGX_DEVICE_HAS_FEATURE(hPrivate, S7_TOP_INFRASTRUCTURE)) { eError = RGXPollReg32(hPrivate, RGX_CR_SLC3_IDLE, RGX_CR_SLC3_IDLE_MASKFULL, RGX_CR_SLC3_IDLE_MASKFULL); } + else +#endif + { + eError = RGXPollReg32(hPrivate, + RGX_CR_SLC_IDLE, + RGX_CR_SLC_IDLE_MASKFULL, + RGX_CR_SLC_IDLE_MASKFULL); + } #endif /* SUPPORT_SHARED_SLC */ if (eError != PVRSRV_OK) return eError; } @@ -1023,6 +1075,7 @@ PVRSRV_ERROR RGXStop(const void *hPrivate) RGX_CR_MTS_BGCTX_THREAD0_DM_ASSOC, RGX_CR_MTS_BGCTX_THREAD0_DM_ASSOC_DM_ASSOC_CLRMSK & RGX_CR_MTS_BGCTX_THREAD0_DM_ASSOC_MASKFULL); +#if defined(RGX_CR_MTS_INTCTX_THREAD1_DM_ASSOC) // FIXME_OCEANIC RGXWriteReg32(hPrivate, RGX_CR_MTS_INTCTX_THREAD1_DM_ASSOC, RGX_CR_MTS_INTCTX_THREAD1_DM_ASSOC_DM_ASSOC_CLRMSK @@ -1031,9 +1084,9 @@ PVRSRV_ERROR RGXStop(const void *hPrivate) RGX_CR_MTS_BGCTX_THREAD1_DM_ASSOC, RGX_CR_MTS_BGCTX_THREAD1_DM_ASSOC_DM_ASSOC_CLRMSK & RGX_CR_MTS_BGCTX_THREAD1_DM_ASSOC_MASKFULL); +#endif - -#if defined(PDUMP) +#if defined(PDUMP) && defined(RGX_FEATURE_META_MAX_VALUE_IDX) if (bMetaFW) { /* Disabling threads is only required for pdumps to stop the fw gracefully */ @@ -1066,7 +1119,7 @@ PVRSRV_ERROR RGXStop(const void *hPrivate) } #endif - +#if !defined(RGX_FEATURE_XE_ARCHITECTURE) || (RGX_FEATURE_XE_ARCHITECTURE == 1) /* Extra Idle checks */ eError = RGXPollReg32(hPrivate, RGX_CR_BIF_STATUS_MMU, @@ -1079,9 +1132,12 @@ PVRSRV_ERROR RGXStop(const void *hPrivate) 0, RGX_CR_BIFPM_STATUS_MMU_MASKFULL); if (eError != PVRSRV_OK) return eError; +#endif +#if defined(RGX_FEATURE_S7_TOP_INFRASTRUCTURE_BIT_MASK) if (!RGX_DEVICE_HAS_FEATURE(hPrivate, S7_TOP_INFRASTRUCTURE) && !RGX_DEVICE_HAS_FEATURE(hPrivate, XT_TOP_INFRASTRUCTURE)) +#endif { eError = RGXPollReg32(hPrivate, RGX_CR_BIF_READS_EXT_STATUS, @@ -1090,12 +1146,13 @@ PVRSRV_ERROR RGXStop(const void *hPrivate) if (eError != PVRSRV_OK) return eError; } - +#if !defined(RGX_FEATURE_XE_ARCHITECTURE) || (RGX_FEATURE_XE_ARCHITECTURE == 1) eError = RGXPollReg32(hPrivate, RGX_CR_BIFPM_READS_EXT_STATUS, 0, RGX_CR_BIFPM_READS_EXT_STATUS_MASKFULL); if (eError != PVRSRV_OK) return eError; +#endif { IMG_UINT64 ui64SLCMask = RGX_CR_SLC_STATUS1_MASKFULL; @@ -1106,6 +1163,7 @@ PVRSRV_ERROR RGXStop(const void *hPrivate) if (eError != PVRSRV_OK) return eError; } +#if !defined(RGX_FEATURE_XE_ARCHITECTURE) || (RGX_FEATURE_XE_ARCHITECTURE == 1) if (4 == RGXGetDeviceSLCBanks(hPrivate)) { eError = RGXPollReg64(hPrivate, @@ -1114,6 +1172,7 @@ PVRSRV_ERROR RGXStop(const void *hPrivate) RGX_CR_SLC_STATUS2_MASKFULL); if (eError != PVRSRV_OK) return eError; } +#endif if (!(PVRSRV_GET_DEVICE_FEATURE_VALUE(psDevInfo->psDeviceNode, LAYOUT_MARS) > 0)) { @@ -1122,20 +1181,22 @@ PVRSRV_ERROR RGXStop(const void *hPrivate) * Wait for SLC to signal IDLE * For LAYOUT_MARS = 1, SLC would have been powered down by FW */ - if (!RGX_DEVICE_HAS_FEATURE(hPrivate, S7_TOP_INFRASTRUCTURE)) - { - eError = RGXPollReg32(hPrivate, - RGX_CR_SLC_IDLE, - RGX_CR_SLC_IDLE_MASKFULL, - RGX_CR_SLC_IDLE_MASKFULL); - } - else +#if defined(RGX_FEATURE_S7_TOP_INFRASTRUCTURE_BIT_MASK) + if (RGX_DEVICE_HAS_FEATURE(hPrivate, S7_TOP_INFRASTRUCTURE)) { eError = RGXPollReg32(hPrivate, RGX_CR_SLC3_IDLE, RGX_CR_SLC3_IDLE_MASKFULL, RGX_CR_SLC3_IDLE_MASKFULL); } + else +#endif + { + eError = RGXPollReg32(hPrivate, + RGX_CR_SLC_IDLE, + RGX_CR_SLC_IDLE_MASKFULL, + RGX_CR_SLC_IDLE_MASKFULL); + } #endif /* SUPPORT_SHARED_SLC */ if (eError != PVRSRV_OK) return eError; } @@ -1143,17 +1204,13 @@ PVRSRV_ERROR RGXStop(const void *hPrivate) /* Wait for Sidekick/Jones to signal IDLE except for the Garten Wrapper * For LAYOUT_MARS = 1, SIDEKICK would have been powered down by FW */ +#if !defined(RGX_FEATURE_XE_ARCHITECTURE) || (RGX_FEATURE_XE_ARCHITECTURE == 1) if (!(PVRSRV_GET_DEVICE_FEATURE_VALUE(psDevInfo->psDeviceNode, LAYOUT_MARS) > 0)) { - if (!RGX_DEVICE_HAS_FEATURE(hPrivate, S7_TOP_INFRASTRUCTURE)) - { - eError = RGXPollReg32(hPrivate, - RGX_CR_SIDEKICK_IDLE, - RGX_CR_SIDEKICK_IDLE_MASKFULL^(RGX_CR_SIDEKICK_IDLE_GARTEN_EN|RGX_CR_SIDEKICK_IDLE_SOCIF_EN|RGX_CR_SIDEKICK_IDLE_HOSTIF_EN), - RGX_CR_SIDEKICK_IDLE_MASKFULL^(RGX_CR_SIDEKICK_IDLE_GARTEN_EN|RGX_CR_SIDEKICK_IDLE_SOCIF_EN|RGX_CR_SIDEKICK_IDLE_HOSTIF_EN)); - } - else +#if defined(RGX_FEATURE_S7_TOP_INFRASTRUCTURE_BIT_MASK) + if (RGX_DEVICE_HAS_FEATURE(hPrivate, S7_TOP_INFRASTRUCTURE)) { +#if defined(RGX_FEATURE_FASTRENDER_DM_BIT_MASK) if (!RGX_DEVICE_HAS_FEATURE(hPrivate, FASTRENDER_DM)) { eError = RGXPollReg32(hPrivate, @@ -1161,11 +1218,22 @@ PVRSRV_ERROR RGXStop(const void *hPrivate) RGX_CR_JONES_IDLE_MASKFULL^(RGX_CR_JONES_IDLE_GARTEN_EN|RGX_CR_JONES_IDLE_SOCIF_EN|RGX_CR_JONES_IDLE_HOSTIF_EN), RGX_CR_JONES_IDLE_MASKFULL^(RGX_CR_JONES_IDLE_GARTEN_EN|RGX_CR_JONES_IDLE_SOCIF_EN|RGX_CR_JONES_IDLE_HOSTIF_EN)); } +#endif + } + else +#endif + { + eError = RGXPollReg32(hPrivate, + RGX_CR_SIDEKICK_IDLE, + RGX_CR_SIDEKICK_IDLE_MASKFULL^(RGX_CR_SIDEKICK_IDLE_GARTEN_EN|RGX_CR_SIDEKICK_IDLE_SOCIF_EN|RGX_CR_SIDEKICK_IDLE_HOSTIF_EN), + RGX_CR_SIDEKICK_IDLE_MASKFULL^(RGX_CR_SIDEKICK_IDLE_GARTEN_EN|RGX_CR_SIDEKICK_IDLE_SOCIF_EN|RGX_CR_SIDEKICK_IDLE_HOSTIF_EN)); } if (eError != PVRSRV_OK) return eError; } +#endif +#if defined(RGX_FEATURE_META_MAX_VALUE_IDX) if (bMetaFW) { IMG_UINT32 ui32RegValue; @@ -1199,6 +1267,7 @@ PVRSRV_ERROR RGXStop(const void *hPrivate) } } else +#endif { if (PVRSRV_GET_DEVICE_FEATURE_VALUE(psDevInfo->psDeviceNode, LAYOUT_MARS) > 0) { @@ -1212,6 +1281,7 @@ PVRSRV_ERROR RGXStop(const void *hPrivate) RGX_CR_MARS_IDLE_CPU_EN | RGX_CR_MARS_IDLE_MH_SYSARB0_EN); if (eError != PVRSRV_OK) return eError; } +#if !defined(RGX_FEATURE_XE_ARCHITECTURE) || (RGX_FEATURE_XE_ARCHITECTURE == 1) else { eError = RGXPollReg32(hPrivate, @@ -1220,6 +1290,7 @@ PVRSRV_ERROR RGXStop(const void *hPrivate) RGX_CR_SIDEKICK_IDLE_GARTEN_EN); if (eError != PVRSRV_OK) return eError; } +#endif } return eError; diff --git a/drivers/gpu/drm/img-rogue/rgxta3d.c b/drivers/gpu/drm/img-rogue/rgxta3d.c index 397f7e27b..3b43babaf 100644 --- a/drivers/gpu/drm/img-rogue/rgxta3d.c +++ b/drivers/gpu/drm/img-rogue/rgxta3d.c @@ -653,11 +653,7 @@ PVRSRV_ERROR RGXGrowFreeList(RGX_FREELIST *psFreeList, /* Copy only the newly added memory */ OSCachedMemCopy(pFLMapAddr + ui32FLMaxSize + ui32CopyOffset, pFLMapAddr + ui32CopyOffset , uiLength); - - if (PVRSRV_CHECK_CPU_WRITE_COMBINE(PMR_Flags(psFreeList->psFreeListPMR))) - { - OSWriteMemoryBarrier(); - } + OSWriteMemoryBarrier(pFLMapAddr); #if defined(PDUMP) PDUMPCOMMENT(psFreeList->psDevInfo->psDeviceNode, "Initialize shadow freelist"); @@ -675,11 +671,6 @@ PVRSRV_ERROR RGXGrowFreeList(RGX_FREELIST *psFreeList, ":SYSMEM:$1", PDUMP_FLAGS_CONTINUOUS); } - - if (PVRSRV_CHECK_CPU_WRITE_COMBINE(PMR_Flags(psFreeList->psFreeListPMR))) - { - OSWriteMemoryBarrier(); - } } #endif @@ -954,7 +945,6 @@ void RGXProcessRequestGrow(PVRSRV_RGXDEV_INFO *psDevInfo, eError = RGXScheduleCommand(psDevInfo, RGXFWIF_DM_3D, &s3DCCBCmd, - 0, PDUMP_FLAGS_NONE); if (eError != PVRSRV_ERROR_RETRY) { @@ -1264,7 +1254,6 @@ void RGXProcessRequestFreelistsReconstruction(PVRSRV_RGXDEV_INFO *psDevInfo, eError = RGXScheduleCommand(psDevInfo, RGXFWIF_DM_GEOM, &sTACCBCmd, - 0, PDUMP_FLAGS_NONE); if (eError != PVRSRV_ERROR_RETRY) { @@ -1531,14 +1520,14 @@ static void RGXDestroyHWRTData_aux(RGX_KM_HW_RT_DATASET *psKMHWRTDataSet) /* Create set of HWRTData(s) and bind it with a shared FW HWRTDataCommon */ PVRSRV_ERROR RGXCreateHWRTDataSet(CONNECTION_DATA *psConnection, PVRSRV_DEVICE_NODE *psDeviceNode, - IMG_DEV_VIRTADDR psVHeapTableDevVAddr, + IMG_DEV_VIRTADDR asVHeapTableDevVAddr[RGXMKIF_NUM_GEOMDATAS], IMG_DEV_VIRTADDR asPMMListDevVAddr[RGXMKIF_NUM_RTDATAS], - RGX_FREELIST *apsFreeLists[RGXFW_MAX_FREELISTS], + RGX_FREELIST *apsFreeLists[RGXMKIF_NUM_RTDATA_FREELISTS], IMG_UINT32 ui32ScreenPixelMax, IMG_UINT64 ui64MultiSampleCtl, IMG_UINT64 ui64FlippedMultiSampleCtl, IMG_UINT32 ui32TPCStride, - IMG_DEV_VIRTADDR sTailPtrsDevVAddr, + IMG_DEV_VIRTADDR asTailPtrsDevVAddr[RGXMKIF_NUM_GEOMDATAS], IMG_UINT32 ui32TPCSize, IMG_UINT32 ui32TEScreen, IMG_UINT32 ui32TEAA, @@ -1553,7 +1542,7 @@ PVRSRV_ERROR RGXCreateHWRTDataSet(CONNECTION_DATA *psConnection, IMG_UINT32 ui32ISPMergeScaleY, IMG_DEV_VIRTADDR asMacrotileArrayDevVAddr[RGXMKIF_NUM_RTDATAS], IMG_DEV_VIRTADDR asRgnHeaderDevVAddr[RGXMKIF_NUM_RTDATAS], - IMG_DEV_VIRTADDR sRTCDevVAddr, + IMG_DEV_VIRTADDR asRTCDevVAddr[RGXMKIF_NUM_GEOMDATAS], IMG_UINT32 uiRgnHeaderSize, IMG_UINT32 ui32ISPMtileSize, IMG_UINT16 ui16MaxRTs, @@ -1637,13 +1626,13 @@ PVRSRV_ERROR RGXCreateHWRTDataSet(CONNECTION_DATA *psConnection, eError = RGXCreateHWRTData_aux( psConnection, psDeviceNode, - psVHeapTableDevVAddr, + asVHeapTableDevVAddr[ui32RTDataID % RGXMKIF_NUM_GEOMDATAS], asPMMListDevVAddr[ui32RTDataID], - apsFreeLists, - sTailPtrsDevVAddr, + &apsFreeLists[(ui32RTDataID % RGXMKIF_NUM_GEOMDATAS) * RGXFW_MAX_FREELISTS], + asTailPtrsDevVAddr[ui32RTDataID % RGXMKIF_NUM_GEOMDATAS], asMacrotileArrayDevVAddr[ui32RTDataID], asRgnHeaderDevVAddr[ui32RTDataID], - sRTCDevVAddr, + asRTCDevVAddr[ui32RTDataID % RGXMKIF_NUM_GEOMDATAS], ui16MaxRTs, psHWRTDataCommonCookie, &pasKMHWRTDataSet[ui32RTDataID]); @@ -1711,7 +1700,7 @@ PVRSRV_ERROR RGXDestroyHWRTDataSet(RGX_KM_HW_RT_DATASET *psKMHWRTDataSet) /* Cleanup HWRTData */ eError = RGXFWRequestHWRTDataCleanUp(psDevNode, psHWRTData); - if (eError == PVRSRV_ERROR_RETRY) + if (eError != PVRSRV_OK) { return eError; } @@ -1821,6 +1810,7 @@ PVRSRV_ERROR RGXCreateFreeList(CONNECTION_DATA *psConnection, eError = DevmemFwAllocate(psDevInfo, sizeof(*psFWFreeList), PVRSRV_MEMALLOCFLAG_DEVICE_FLAG(PMMETA_PROTECT) | + PVRSRV_MEMALLOCFLAG_DEVICE_FLAG(FIRMWARE_CACHED) | PVRSRV_MEMALLOCFLAG_ZERO_ON_ALLOC | PVRSRV_MEMALLOCFLAG_GPU_READABLE | PVRSRV_MEMALLOCFLAG_GPU_WRITEABLE | @@ -2133,6 +2123,7 @@ PVRSRV_ERROR RGXCreateZSBufferKM(CONNECTION_DATA * psConnection, eError = DevmemFwAllocate(psDevInfo, sizeof(*psFWZSBuffer), PVRSRV_MEMALLOCFLAG_DEVICE_FLAG(PMMETA_PROTECT) | + PVRSRV_MEMALLOCFLAG_DEVICE_FLAG(FIRMWARE_CACHED) | PVRSRV_MEMALLOCFLAG_ZERO_ON_ALLOC | PVRSRV_MEMALLOCFLAG_GPU_READABLE | PVRSRV_MEMALLOCFLAG_GPU_WRITEABLE | @@ -2226,7 +2217,7 @@ PVRSRV_ERROR RGXDestroyZSBufferKM(RGX_ZSBUFFER_DATA *psZSBuffer) /* Request ZS Buffer cleanup */ eError = RGXFWRequestZSBufferCleanUp(psZSBuffer->psDevInfo, psZSBuffer->sZSBufferFWDevVAddr); - if (eError != PVRSRV_ERROR_RETRY) + if (eError == PVRSRV_OK) { /* Free the firmware render context. */ RGXUnsetFirmwareAddress(psZSBuffer->psFWZSBufferMemDesc); @@ -2503,7 +2494,6 @@ void RGXProcessRequestZSBufferBacking(PVRSRV_RGXDEV_INFO *psDevInfo, eError = RGXScheduleCommand(psDevInfo, RGXFWIF_DM_GEOM, &sTACCBCmd, - 0, PDUMP_FLAGS_NONE); if (eError != PVRSRV_ERROR_RETRY) { @@ -2565,7 +2555,6 @@ void RGXProcessRequestZSBufferUnbacking(PVRSRV_RGXDEV_INFO *psDevInfo, eError = RGXScheduleCommand(psDevInfo, RGXFWIF_DM_GEOM, &sTACCBCmd, - 0, PDUMP_FLAGS_NONE); if (eError != PVRSRV_ERROR_RETRY) { @@ -2593,6 +2582,7 @@ PVRSRV_ERROR _CreateTAContext(CONNECTION_DATA *psConnection, IMG_UINT32 ui32AllocatedOffset, DEVMEM_MEMDESC *psFWMemContextMemDesc, IMG_DEV_VIRTADDR sVDMCallStackAddr, + IMG_UINT32 ui32CallStackDepth, IMG_UINT32 ui32Priority, IMG_UINT32 ui32MaxDeadlineMS, IMG_UINT64 ui64RobustnessAddress, @@ -2604,6 +2594,7 @@ PVRSRV_ERROR _CreateTAContext(CONNECTION_DATA *psConnection, { PVRSRV_RGXDEV_INFO *psDevInfo = psDeviceNode->pvDevice; RGXFWIF_TACTX_STATE *psContextState; + IMG_UINT32 uiCoreIdx; PVRSRV_ERROR eError; /* Allocate device memory for the firmware GPU context suspend state. @@ -2635,7 +2626,13 @@ PVRSRV_ERROR _CreateTAContext(CONNECTION_DATA *psConnection, PVRSRVGetErrorString(eError))); goto fail_suspendcpuvirtacquire; } - psContextState->uTAReg_VDM_CALL_STACK_POINTER_Init = sVDMCallStackAddr.uiAddr; + + for (uiCoreIdx = 0; uiCoreIdx < RGX_NUM_GEOM_CORES; uiCoreIdx++) + { + psContextState->asGeomCore[uiCoreIdx].uTAReg_VDM_CALL_STACK_POINTER_Init = + sVDMCallStackAddr.uiAddr + (uiCoreIdx * ui32CallStackDepth * sizeof(IMG_UINT64)); + } + DevmemReleaseCpuVirtAddr(psTAData->psContextStateMemDesc); eError = FWCommonContextAllocate(psConnection, @@ -2802,6 +2799,7 @@ PVRSRV_ERROR PVRSRVRGXCreateRenderContextKM(CONNECTION_DATA *psConnection, PVRSRV_DEVICE_NODE *psDeviceNode, IMG_UINT32 ui32Priority, IMG_DEV_VIRTADDR sVDMCallStackAddr, + IMG_UINT32 ui32CallStackDepth, IMG_UINT32 ui32FrameworkRegisterSize, IMG_PBYTE pabyFrameworkRegisters, IMG_HANDLE hMemCtxPrivData, @@ -2919,6 +2917,7 @@ PVRSRV_ERROR PVRSRVRGXCreateRenderContextKM(CONNECTION_DATA *psConnection, offsetof(RGXFWIF_FWRENDERCONTEXT, sTAContext), psFWMemContextMemDesc, sVDMCallStackAddr, + ui32CallStackDepth, ui32Priority, ui32MaxTADeadlineMS, ui64RobustnessAddress, @@ -3266,7 +3265,6 @@ static void DumpUfoList(IMG_UINT32 ui32ClientTAFenceCount, * PVRSRVRGXKickTA3DKM */ PVRSRV_ERROR PVRSRVRGXKickTA3DKM(RGX_SERVER_RENDER_CONTEXT *psRenderContext, - IMG_UINT32 ui32ClientCacheOpSeqNum, IMG_UINT32 ui32ClientTAFenceCount, SYNC_PRIMITIVE_BLOCK **apsClientTAFenceSyncPrimBlock, IMG_UINT32 *paui32ClientTAFenceSyncOffset, @@ -3796,6 +3794,7 @@ PVRSRV_ERROR PVRSRVRGXKickTA3DKM(RGX_SERVER_RENDER_CONTEXT *psRenderContext, __func__, ui32TAFenceCount, ui32TAUpdateCount)); RGXCmdHelperInitCmdCCB_CommandSize( + psDevInfo, 0, ui32TAFenceCount, ui32TAUpdateCount, @@ -3814,6 +3813,7 @@ PVRSRV_ERROR PVRSRVRGXKickTA3DKM(RGX_SERVER_RENDER_CONTEXT *psRenderContext, ui323DFenceCount)); RGXCmdHelperInitCmdCCB_CommandSize( + psDevInfo, 0, ui323DFenceCount, 0, @@ -3832,6 +3832,7 @@ PVRSRV_ERROR PVRSRVRGXKickTA3DKM(RGX_SERVER_RENDER_CONTEXT *psRenderContext, ui32PRUpdateCount)); RGXCmdHelperInitCmdCCB_CommandSize( + psDevInfo, 0, 0, ui32PRUpdateCount, @@ -3855,6 +3856,7 @@ PVRSRV_ERROR PVRSRVRGXKickTA3DKM(RGX_SERVER_RENDER_CONTEXT *psRenderContext, } RGXCmdHelperInitCmdCCB_CommandSize( + psDevInfo, 0, bKickTA ? 0 : ui323DFenceCount, ui323DUpdateCount, @@ -4926,7 +4928,6 @@ PVRSRV_ERROR PVRSRVRGXKickTA3DKM(RGX_SERVER_RENDER_CONTEXT *psRenderContext, eError2 = RGXScheduleCommand(psRenderContext->psDeviceNode->pvDevice, RGXFWIF_DM_GEOM, &sTAKCCBCmd, - ui32ClientCacheOpSeqNum, ui32PDumpFlags); if (eError2 != PVRSRV_ERROR_RETRY) { @@ -5028,7 +5029,6 @@ PVRSRV_ERROR PVRSRVRGXKickTA3DKM(RGX_SERVER_RENDER_CONTEXT *psRenderContext, eError2 = RGXScheduleCommand(psRenderContext->psDeviceNode->pvDevice, RGXFWIF_DM_3D, &s3DKCCBCmd, - ui32ClientCacheOpSeqNum, ui32PDumpFlags); if (eError2 != PVRSRV_ERROR_RETRY) { @@ -5329,24 +5329,23 @@ PVRSRV_ERROR PVRSRVRGXSetRenderContextPropertyKM(RGX_SERVER_RENDER_CONTEXT *psRe IMG_UINT64 ui64Input, IMG_UINT64 *pui64Output) { - PVRSRV_ERROR eError; - PVRSRV_ERROR eError2 = PVRSRV_OK; + PVRSRV_ERROR eError = PVRSRV_OK; switch (eContextProperty) { case RGX_CONTEXT_PROPERTY_FLAGS: { + IMG_UINT32 ui32ContextFlags = (IMG_UINT32)ui64Input; + OSLockAcquire(psRenderContext->hLock); eError = FWCommonContextSetFlags(psRenderContext->sTAData.psServerCommonContext, - (IMG_UINT32)ui64Input); + ui32ContextFlags); if (eError == PVRSRV_OK) { - eError2 = FWCommonContextSetFlags(psRenderContext->s3DData.psServerCommonContext, - (IMG_UINT32)ui64Input); + eError = FWCommonContextSetFlags(psRenderContext->s3DData.psServerCommonContext, + ui32ContextFlags); } OSLockRelease(psRenderContext->hLock); - PVR_LOG_IF_ERROR(eError, "FWCommonContextSetFlags eError"); - PVR_LOG_IF_ERROR(eError2, "FWCommonContextSetFlags eError2"); break; } diff --git a/drivers/gpu/drm/img-rogue/rgxta3d.h b/drivers/gpu/drm/img-rogue/rgxta3d.h index 94ddfb5b2..89a5b225a 100644 --- a/drivers/gpu/drm/img-rogue/rgxta3d.h +++ b/drivers/gpu/drm/img-rogue/rgxta3d.h @@ -225,14 +225,14 @@ IMG_BOOL RGXDumpFreeListPageList(RGX_FREELIST *psFreeList); /* Create set of HWRTData(s) */ PVRSRV_ERROR RGXCreateHWRTDataSet(CONNECTION_DATA *psConnection, PVRSRV_DEVICE_NODE *psDeviceNode, - IMG_DEV_VIRTADDR psVHeapTableDevVAddr, + IMG_DEV_VIRTADDR asVHeapTableDevVAddr[RGXMKIF_NUM_GEOMDATAS], IMG_DEV_VIRTADDR psPMMListDevVAddr[RGXMKIF_NUM_RTDATAS], - RGX_FREELIST *apsFreeLists[RGXFW_MAX_FREELISTS], + RGX_FREELIST *apsFreeLists[RGXMKIF_NUM_RTDATA_FREELISTS], IMG_UINT32 ui32ScreenPixelMax, IMG_UINT64 ui64MultiSampleCtl, IMG_UINT64 ui64FlippedMultiSampleCtl, IMG_UINT32 ui32TPCStride, - IMG_DEV_VIRTADDR sTailPtrsDevVAddr, + IMG_DEV_VIRTADDR asTailPtrsDevVAddr[RGXMKIF_NUM_GEOMDATAS], IMG_UINT32 ui32TPCSize, IMG_UINT32 ui32TEScreen, IMG_UINT32 ui32TEAA, @@ -247,7 +247,7 @@ PVRSRV_ERROR RGXCreateHWRTDataSet(CONNECTION_DATA *psConnection, IMG_UINT32 ui32ISPMergeScaleY, IMG_DEV_VIRTADDR sMacrotileArrayDevVAddr[RGXMKIF_NUM_RTDATAS], IMG_DEV_VIRTADDR sRgnHeaderDevVAddr[RGXMKIF_NUM_RTDATAS], - IMG_DEV_VIRTADDR sRTCDevVAddr, + IMG_DEV_VIRTADDR asRTCDevVAddr[RGXMKIF_NUM_GEOMDATAS], IMG_UINT32 uiRgnHeaderSize, IMG_UINT32 ui32ISPMtileSize, IMG_UINT16 ui16MaxRTs, @@ -363,6 +363,7 @@ void RGXProcessRequestFreelistsReconstruction(PVRSRV_RGXDEV_INFO *psDevInfo, @Input psDeviceNode - device node @Input ui32Priority - context priority @Input sVDMCallStackAddr - VDM call stack device virtual address + @Input ui32CallStackDepth - VDM call stack depth @Input ui32FrameworkCommandSize - framework command size @Input pabyFrameworkCommand - ptr to framework command @Input hMemCtxPrivData - memory context private data @@ -383,6 +384,7 @@ PVRSRV_ERROR PVRSRVRGXCreateRenderContextKM(CONNECTION_DATA *psConnection, PVRSRV_DEVICE_NODE *psDeviceNode, IMG_UINT32 ui32Priority, IMG_DEV_VIRTADDR sVDMCallStackAddr, + IMG_UINT32 ui32CallStackDepth, IMG_UINT32 ui32FrameworkCommandSize, IMG_PBYTE pabyFrameworkCommand, IMG_HANDLE hMemCtxPrivData, @@ -428,7 +430,6 @@ PVRSRV_ERROR PVRSRVRGXDestroyRenderContextKM(RGX_SERVER_RENDER_CONTEXT *psRender ******************************************************************************/ PVRSRV_ERROR PVRSRVRGXKickTA3DKM(RGX_SERVER_RENDER_CONTEXT *psRenderContext, - IMG_UINT32 ui32ClientCacheOpSeqNum, IMG_UINT32 ui32ClientTAFenceCount, SYNC_PRIMITIVE_BLOCK **apsClientTAFenceSyncPrimBlock, IMG_UINT32 *paui32ClientTAFenceSyncOffset, diff --git a/drivers/gpu/drm/img-rogue/rgxtdmtransfer.c b/drivers/gpu/drm/img-rogue/rgxtdmtransfer.c index 429338ab1..f341464e7 100644 --- a/drivers/gpu/drm/img-rogue/rgxtdmtransfer.c +++ b/drivers/gpu/drm/img-rogue/rgxtdmtransfer.c @@ -124,7 +124,8 @@ static PVRSRV_ERROR _CreateTDMTransferContext( RGX_SERVER_TQ_TDM_DATA * psTDMData, IMG_UINT32 ui32CCBAllocSizeLog2, IMG_UINT32 ui32CCBMaxAllocSizeLog2, - IMG_UINT32 ui32ContextFlags) + IMG_UINT32 ui32ContextFlags, + IMG_UINT64 ui64RobustnessAddress) { PVRSRV_ERROR eError; @@ -158,7 +159,7 @@ static PVRSRV_ERROR _CreateTDMTransferContext( ui32ContextFlags, ui32Priority, UINT_MAX, /* max deadline MS */ - 0, /* robustness address */ + ui64RobustnessAddress, psInfo, &psTDMData->psServerCommonContext); if (eError != PVRSRV_OK) @@ -227,6 +228,7 @@ PVRSRV_ERROR PVRSRVRGXTDMCreateTransferContextKM( IMG_HANDLE hMemCtxPrivData, IMG_UINT32 ui32PackedCCBSizeU88, IMG_UINT32 ui32ContextFlags, + IMG_UINT64 ui64RobustnessAddress, RGX_SERVER_TQ_TDM_CONTEXT ** ppsTransferContext) { RGX_SERVER_TQ_TDM_CONTEXT * psTransferContext; @@ -314,7 +316,8 @@ PVRSRV_ERROR PVRSRVRGXTDMCreateTransferContextKM( &psTransferContext->sTDMData, U32toU8_Unpack1(ui32PackedCCBSizeU88), U32toU8_Unpack2(ui32PackedCCBSizeU88), - ui32ContextFlags); + ui32ContextFlags, + ui64RobustnessAddress); if (eError != PVRSRV_OK) { goto fail_tdmtransfercontext; @@ -466,7 +469,6 @@ fail_destroyTDM: PVRSRV_ERROR PVRSRVRGXTDMSubmitTransferKM( RGX_SERVER_TQ_TDM_CONTEXT * psTransferContext, IMG_UINT32 ui32PDumpFlags, - IMG_UINT32 ui32ClientCacheOpSeqNum, IMG_UINT32 ui32ClientUpdateCount, SYNC_PRIMITIVE_BLOCK ** pauiClientUpdateUFODevVarBlock, IMG_UINT32 * paui32ClientUpdateSyncOffset, @@ -914,7 +916,8 @@ PVRSRV_ERROR PVRSRVRGXTDMSubmitTransferKM( /* Create the command helper data for this command */ - RGXCmdHelperInitCmdCCB(psClientCCB, + RGXCmdHelperInitCmdCCB(psDevInfo, + psClientCCB, 0, ui32IntClientFenceCount, pauiIntFenceUFOAddress, @@ -1041,7 +1044,6 @@ PVRSRV_ERROR PVRSRVRGXTDMSubmitTransferKM( eError2 = RGXScheduleCommand(psDeviceNode->pvDevice, RGXFWIF_DM_TDM, & sTDMKCCBCmd, - ui32ClientCacheOpSeqNum, ui32PDumpFlags); if (eError2 != PVRSRV_ERROR_RETRY) { @@ -1197,7 +1199,6 @@ PVRSRV_ERROR PVRSRVRGXTDMNotifyWriteOffsetUpdateKM( eError = RGXScheduleCommand(psTransferContext->psDeviceNode->pvDevice, RGXFWIF_DM_TDM, &sKCCBCmd, - 0, ui32PDumpFlags); if (eError != PVRSRV_ERROR_RETRY) { @@ -1253,21 +1254,18 @@ PVRSRV_ERROR PVRSRVRGXTDMSetTransferContextPropertyKM(RGX_SERVER_TQ_TDM_CONTEXT IMG_UINT64 ui64Input, IMG_UINT64 *pui64Output) { - PVRSRV_ERROR eError; + PVRSRV_ERROR eError = PVRSRV_OK; switch (eContextProperty) { case RGX_CONTEXT_PROPERTY_FLAGS: { + IMG_UINT32 ui32ContextFlags = (IMG_UINT32)ui64Input; + OSLockAcquire(psTransferContext->hLock); eError = FWCommonContextSetFlags(psTransferContext->sTDMData.psServerCommonContext, - (IMG_UINT32)ui64Input); - if (eError == PVRSRV_OK) - { - psTransferContext->ui32Flags = (IMG_UINT32)ui64Input; - } + ui32ContextFlags); OSLockRelease(psTransferContext->hLock); - PVR_LOG_IF_ERROR(eError, "FWCommonContextSetFlags"); break; } diff --git a/drivers/gpu/drm/img-rogue/rgxtdmtransfer.h b/drivers/gpu/drm/img-rogue/rgxtdmtransfer.h index 106b7bdae..87ca2cf2c 100644 --- a/drivers/gpu/drm/img-rogue/rgxtdmtransfer.h +++ b/drivers/gpu/drm/img-rogue/rgxtdmtransfer.h @@ -67,6 +67,7 @@ PVRSRV_ERROR PVRSRVRGXTDMCreateTransferContextKM( IMG_HANDLE hMemCtxPrivData, IMG_UINT32 ui32PackedCCBSizeU88, IMG_UINT32 ui32ContextFlags, + IMG_UINT64 ui64RobustnessAddress, RGX_SERVER_TQ_TDM_CONTEXT **ppsTransferContext); @@ -86,7 +87,6 @@ PVRSRV_ERROR PVRSRVRGXTDMDestroyTransferContextKM(RGX_SERVER_TQ_TDM_CONTEXT *psT PVRSRV_ERROR PVRSRVRGXTDMSubmitTransferKM( RGX_SERVER_TQ_TDM_CONTEXT * psTransferContext, IMG_UINT32 ui32PDumpFlags, - IMG_UINT32 ui32ClientCacheOpSeqNum, IMG_UINT32 ui32ClientUpdateCount, SYNC_PRIMITIVE_BLOCK ** pauiClientUpdateUFODevVarBlock, IMG_UINT32 * paui32ClientUpdateSyncOffset, diff --git a/drivers/gpu/drm/img-rogue/rgxtimecorr.c b/drivers/gpu/drm/img-rogue/rgxtimecorr.c index cf558f44a..584dbf1e3 100644 --- a/drivers/gpu/drm/img-rogue/rgxtimecorr.c +++ b/drivers/gpu/drm/img-rogue/rgxtimecorr.c @@ -259,7 +259,7 @@ static void _RGXMakeTimeCorrData(PVRSRV_DEVICE_NODE *psDeviceNode, RGXTIMECORR_E } /* Make sure the values are written to memory before updating the index of the current entry */ - OSWriteMemoryBarrier(); + OSWriteMemoryBarrier(psTimeCorr); /* Update the index of the current entry in the timer correlation array */ psGpuUtilFWCB->ui32TimeCorrSeqCount = ui32NewSeqCount; diff --git a/drivers/gpu/drm/img-rogue/rgxtimerquery.c b/drivers/gpu/drm/img-rogue/rgxtimerquery.c index 82a2b7a77..d5d11bff9 100644 --- a/drivers/gpu/drm/img-rogue/rgxtimerquery.c +++ b/drivers/gpu/drm/img-rogue/rgxtimerquery.c @@ -72,7 +72,7 @@ PVRSRVRGXBeginTimerQueryKM(CONNECTION_DATA * psConnection, /* clear the stamps, in case there is no Kick */ psDevInfo->pui64StartTimeById[ui32QueryId] = 0UL; psDevInfo->pui64EndTimeById[ui32QueryId] = 0UL; - OSWriteMemoryBarrier(); + OSWriteMemoryBarrier(&psDevInfo->pui64EndTimeById[ui32QueryId]); /* save of the active query index */ psDevInfo->ui32ActiveQueryId = ui32QueryId; diff --git a/drivers/gpu/drm/img-rogue/rgxtransfer.c b/drivers/gpu/drm/img-rogue/rgxtransfer.c index d816faf88..91b3b8d28 100644 --- a/drivers/gpu/drm/img-rogue/rgxtransfer.c +++ b/drivers/gpu/drm/img-rogue/rgxtransfer.c @@ -137,7 +137,8 @@ static PVRSRV_ERROR _Create3DTransferContext(CONNECTION_DATA *psConnection, RGX_SERVER_TQ_3D_DATA *ps3DData, IMG_UINT32 ui32CCBAllocSizeLog2, IMG_UINT32 ui32CCBMaxAllocSizeLog2, - IMG_UINT32 ui32ContextFlags) + IMG_UINT32 ui32ContextFlags, + IMG_UINT64 ui64RobustnessAddress) { PVRSRV_RGXDEV_INFO *psDevInfo = psDeviceNode->pvDevice; PVRSRV_ERROR eError; @@ -198,7 +199,7 @@ static PVRSRV_ERROR _Create3DTransferContext(CONNECTION_DATA *psConnection, ui32ContextFlags, ui32Priority, UINT_MAX, /* max deadline MS */ - 0, /* robustness address */ + ui64RobustnessAddress, psInfo, &ps3DData->psServerCommonContext); if (eError != PVRSRV_OK) @@ -226,6 +227,7 @@ fail_buffer_sync_context_create: } +#if defined(RGX_FEATURE_TLA_BIT_MASK) static PVRSRV_ERROR _Create2DTransferContext(CONNECTION_DATA *psConnection, PVRSRV_DEVICE_NODE *psDeviceNode, DEVMEM_MEMDESC *psFWMemContextMemDesc, @@ -234,7 +236,8 @@ static PVRSRV_ERROR _Create2DTransferContext(CONNECTION_DATA *psConnection, RGX_SERVER_TQ_2D_DATA *ps2DData, IMG_UINT32 ui32CCBAllocSizeLog2, IMG_UINT32 ui32CCBMaxAllocSizeLog2, - IMG_UINT32 ui32ContextFlags) + IMG_UINT32 ui32ContextFlags, + IMG_UINT64 ui64RobustnessAddress) { PVRSRV_ERROR eError; @@ -267,7 +270,7 @@ static PVRSRV_ERROR _Create2DTransferContext(CONNECTION_DATA *psConnection, ui32ContextFlags, ui32Priority, UINT_MAX, /* max deadline MS */ - 0, /* robustness address */ + ui64RobustnessAddress, psInfo, &ps2DData->psServerCommonContext); if (eError != PVRSRV_OK) @@ -312,7 +315,7 @@ static PVRSRV_ERROR _Destroy2DTransferContext(RGX_SERVER_TQ_2D_DATA *ps2DData, return eError; } - /* ... it has so we can free it's resources */ + /* ... it has so we can free its resources */ FWCommonContextFree(ps2DData->psServerCommonContext); ps2DData->psServerCommonContext = NULL; @@ -323,6 +326,7 @@ static PVRSRV_ERROR _Destroy2DTransferContext(RGX_SERVER_TQ_2D_DATA *ps2DData, return PVRSRV_OK; } +#endif /* #if defined(RGX_FEATURE_TLA_BIT_MASK) */ static PVRSRV_ERROR _Destroy3DTransferContext(RGX_SERVER_TQ_3D_DATA *ps3DData, PVRSRV_DEVICE_NODE *psDeviceNode, @@ -347,7 +351,7 @@ static PVRSRV_ERROR _Destroy3DTransferContext(RGX_SERVER_TQ_3D_DATA *ps3DData, return eError; } - /* ... it has so we can free it's resources */ + /* ... it has so we can free its resources */ DevmemFwUnmapAndFree(psDeviceNode->pvDevice, ps3DData->psFWContextStateMemDesc); FWCommonContextFree(ps3DData->psServerCommonContext); ps3DData->psServerCommonContext = NULL; @@ -372,6 +376,7 @@ PVRSRV_ERROR PVRSRVRGXCreateTransferContextKM(CONNECTION_DATA *psConnection, IMG_HANDLE hMemCtxPrivData, IMG_UINT32 ui32PackedCCBSizeU8888, IMG_UINT32 ui32ContextFlags, + IMG_UINT64 ui64RobustnessAddress, RGX_SERVER_TQ_CONTEXT **ppsTransferContext, PMR **ppsCLIPMRMem, PMR **ppsUSCPMRMem) @@ -379,7 +384,7 @@ PVRSRV_ERROR PVRSRVRGXCreateTransferContextKM(CONNECTION_DATA *psConnection, RGX_SERVER_TQ_CONTEXT *psTransferContext; PVRSRV_RGXDEV_INFO *psDevInfo = psDeviceNode->pvDevice; DEVMEM_MEMDESC *psFWMemContextMemDesc = RGXGetFWMemDescFromMemoryContextHandle(hMemCtxPrivData); - RGX_COMMON_CONTEXT_INFO sInfo; + RGX_COMMON_CONTEXT_INFO sInfo = {NULL}; PVRSRV_ERROR eError = PVRSRV_OK; /* Allocate the server side structure */ @@ -460,13 +465,15 @@ PVRSRV_ERROR PVRSRVRGXCreateTransferContextKM(CONNECTION_DATA *psConnection, &psTransferContext->s3DData, U32toU8_Unpack3(ui32PackedCCBSizeU8888), U32toU8_Unpack4(ui32PackedCCBSizeU8888), - ui32ContextFlags); + ui32ContextFlags, + ui64RobustnessAddress); if (eError != PVRSRV_OK) { goto fail_3dtransfercontext; } psTransferContext->ui32Flags |= RGX_SERVER_TQ_CONTEXT_FLAGS_3D; +#if defined(RGX_FEATURE_TLA_BIT_MASK) if (RGX_IS_FEATURE_SUPPORTED(psDevInfo, TLA)) { eError = _Create2DTransferContext(psConnection, @@ -477,13 +484,15 @@ PVRSRV_ERROR PVRSRVRGXCreateTransferContextKM(CONNECTION_DATA *psConnection, &psTransferContext->s2DData, U32toU8_Unpack1(ui32PackedCCBSizeU8888), U32toU8_Unpack2(ui32PackedCCBSizeU8888), - ui32ContextFlags); + ui32ContextFlags, + ui64RobustnessAddress); if (eError != PVRSRV_OK) { goto fail_2dtransfercontext; } psTransferContext->ui32Flags |= RGX_SERVER_TQ_CONTEXT_FLAGS_2D; } +#endif PVRSRVTQAcquireShaders(psDeviceNode, ppsCLIPMRMem, ppsUSCPMRMem); @@ -498,10 +507,12 @@ PVRSRV_ERROR PVRSRVRGXCreateTransferContextKM(CONNECTION_DATA *psConnection, return PVRSRV_OK; +#if defined(RGX_FEATURE_TLA_BIT_MASK) fail_2dtransfercontext: _Destroy3DTransferContext(&psTransferContext->s3DData, psTransferContext->psDeviceNode, psTransferContext->ui32PDumpFlags); +#endif fail_3dtransfercontext: fail_frameworkcopy: if (psTransferContext->psFWFrameworkMemDesc) @@ -533,6 +544,7 @@ PVRSRV_ERROR PVRSRVRGXDestroyTransferContextKM(RGX_SERVER_TQ_CONTEXT *psTransfer dllist_remove_node(&(psTransferContext->sListNode)); OSWRLockReleaseWrite(psDevInfo->hTransferCtxListLock); +#if defined(RGX_FEATURE_TLA_BIT_MASK) if ((psTransferContext->ui32Flags & RGX_SERVER_TQ_CONTEXT_FLAGS_2D) && (RGX_IS_FEATURE_SUPPORTED(psDevInfo, TLA))) { @@ -546,6 +558,7 @@ PVRSRV_ERROR PVRSRVRGXDestroyTransferContextKM(RGX_SERVER_TQ_CONTEXT *psTransfer /* We've freed the 2D context, don't try to free it again */ psTransferContext->ui32Flags &= ~RGX_SERVER_TQ_CONTEXT_FLAGS_2D; } +#endif if (psTransferContext->ui32Flags & RGX_SERVER_TQ_CONTEXT_FLAGS_3D) { @@ -581,8 +594,10 @@ PVRSRV_ERROR PVRSRVRGXDestroyTransferContextKM(RGX_SERVER_TQ_CONTEXT *psTransfer return PVRSRV_OK; fail_destroy3d: +#if defined(RGX_FEATURE_TLA_BIT_MASK) fail_destroy2d: +#endif OSWRLockAcquireWrite(psDevInfo->hTransferCtxListLock); dllist_add_to_tail(&(psDevInfo->sTransferCtxtListHead), &(psTransferContext->sListNode)); OSWRLockReleaseWrite(psDevInfo->hTransferCtxListLock); @@ -594,7 +609,6 @@ fail_destroy2d: * PVRSRVSubmitTQ3DKickKM */ PVRSRV_ERROR PVRSRVRGXSubmitTransferKM(RGX_SERVER_TQ_CONTEXT *psTransferContext, - IMG_UINT32 ui32ClientCacheOpSeqNum, IMG_UINT32 ui32PrepareCount, IMG_UINT32 *paui32ClientUpdateCount, SYNC_PRIMITIVE_BLOCK ***papauiClientUpdateUFODevVarBlock, @@ -617,30 +631,38 @@ PVRSRV_ERROR PVRSRVRGXSubmitTransferKM(RGX_SERVER_TQ_CONTEXT *psTransferContext, PVRSRV_DEVICE_NODE *psDeviceNode = psTransferContext->psDeviceNode; PVRSRV_RGXDEV_INFO *psDevInfo = psDeviceNode->pvDevice; RGX_CCB_CMD_HELPER_DATA *pas3DCmdHelper; +#if defined(RGX_FEATURE_TLA_BIT_MASK) RGX_CCB_CMD_HELPER_DATA *pas2DCmdHelper; +#endif IMG_UINT32 ui323DCmdCount = 0; - IMG_UINT32 ui322DCmdCount = 0; IMG_UINT32 ui323DCmdLast = 0; - IMG_UINT32 ui322DCmdLast = 0; IMG_UINT32 ui323DCmdOffset = 0; +#if defined(RGX_FEATURE_TLA_BIT_MASK) + IMG_UINT32 ui322DCmdCount = 0; + IMG_UINT32 ui322DCmdLast = 0; IMG_UINT32 ui322DCmdOffset = 0; +#endif IMG_UINT32 ui32PDumpFlags = PDUMP_FLAGS_NONE; IMG_UINT32 i; IMG_UINT64 uiCheckFenceUID = 0; +#if defined(RGX_FEATURE_TLA_BIT_MASK) IMG_UINT64 ui2DUpdateFenceUID = 0; +#endif IMG_UINT64 ui3DUpdateFenceUID = 0; - PSYNC_CHECKPOINT ps2DUpdateSyncCheckpoint = NULL; PSYNC_CHECKPOINT ps3DUpdateSyncCheckpoint = NULL; PSYNC_CHECKPOINT *apsFenceSyncCheckpoints = NULL; IMG_UINT32 ui32FenceSyncCheckpointCount = 0; - IMG_UINT32 *pui322DIntAllocatedUpdateValues = NULL; IMG_UINT32 *pui323DIntAllocatedUpdateValues = NULL; +#if defined(RGX_FEATURE_TLA_BIT_MASK) + PSYNC_CHECKPOINT ps2DUpdateSyncCheckpoint = NULL; + IMG_UINT32 *pui322DIntAllocatedUpdateValues = NULL; PVRSRV_CLIENT_SYNC_PRIM *ps2DFenceTimelineUpdateSync = NULL; - PVRSRV_CLIENT_SYNC_PRIM *ps3DFenceTimelineUpdateSync = NULL; IMG_UINT32 ui322DFenceTimelineUpdateValue = 0; - IMG_UINT32 ui323DFenceTimelineUpdateValue = 0; void *pv2DUpdateFenceFinaliseData = NULL; +#endif + PVRSRV_CLIENT_SYNC_PRIM *ps3DFenceTimelineUpdateSync = NULL; + IMG_UINT32 ui323DFenceTimelineUpdateValue = 0; void *pv3DUpdateFenceFinaliseData = NULL; #if defined(SUPPORT_BUFFER_SYNC) PSYNC_CHECKPOINT psBufferUpdateSyncCheckpoint = NULL; @@ -651,7 +673,9 @@ PVRSRV_ERROR PVRSRVRGXSubmitTransferKM(RGX_SERVER_TQ_CONTEXT *psTransferContext, PVRSRV_ERROR eError = PVRSRV_OK; PVRSRV_ERROR eError2; +#if defined(RGX_FEATURE_TLA_BIT_MASK) PVRSRV_FENCE i2DUpdateFence = PVRSRV_NO_FENCE; +#endif PVRSRV_FENCE i3DUpdateFence = PVRSRV_NO_FENCE; IMG_UINT32 ui32IntJobRef = OSAtomicIncrement(&psDevInfo->iCCBSubmissionOrdinal); IMG_UINT32 ui32PreparesDone = 0; @@ -661,15 +685,21 @@ PVRSRV_ERROR PVRSRVRGXSubmitTransferKM(RGX_SERVER_TQ_CONTEXT *psTransferContext, PRGXFWIF_TIMESTAMP_ADDR pPostAddr; PRGXFWIF_UFO_ADDR pRMWUFOAddr; +#if !defined(RGX_FEATURE_TLA_BIT_MASK) + PVR_UNREFERENCED_PARAMETER(i2DUpdateTimeline); + PVR_UNREFERENCED_PARAMETER(pi2DUpdateFence); +#endif + RGX_GetTimestampCmdHelper((PVRSRV_RGXDEV_INFO*) psDeviceNode->pvDevice, &pPreAddr, &pPostAddr, &pRMWUFOAddr); - +#if defined(RGX_FEATURE_TLA_BIT_MASK) if (i2DUpdateTimeline != PVRSRV_NO_TIMELINE && !pi2DUpdateFence) { return PVRSRV_ERROR_INVALID_PARAMS; } +#endif if (i3DUpdateTimeline != PVRSRV_NO_TIMELINE && !pi3DUpdateFence) { return PVRSRV_ERROR_INVALID_PARAMS; @@ -743,12 +773,15 @@ PVRSRV_ERROR PVRSRVRGXSubmitTransferKM(RGX_SERVER_TQ_CONTEXT *psTransferContext, eError = PVRSRV_ERROR_OUT_OF_MEMORY; goto fail_alloc3dhelper; } + +#if defined(RGX_FEATURE_TLA_BIT_MASK) pas2DCmdHelper = OSAllocMem(sizeof(*pas2DCmdHelper) * ui32PrepareCount); if (pas2DCmdHelper == NULL) { eError = PVRSRV_ERROR_OUT_OF_MEMORY; goto fail_alloc2dhelper; } +#endif if (iCheckFence != PVRSRV_NO_FENCE) { @@ -786,11 +819,14 @@ PVRSRV_ERROR PVRSRVRGXSubmitTransferKM(RGX_SERVER_TQ_CONTEXT *psTransferContext, if (TQ_PREP_FLAGS_COMMAND_IS(pui32TQPrepareFlags[i], 3D)) { ui323DCmdLast++; - } else if (TQ_PREP_FLAGS_COMMAND_IS(pui32TQPrepareFlags[i], 2D) && + } +#if defined(RGX_FEATURE_TLA_BIT_MASK) + else if (TQ_PREP_FLAGS_COMMAND_IS(pui32TQPrepareFlags[i], 2D) && (RGX_IS_FEATURE_SUPPORTED(psDevInfo, TLA))) { ui322DCmdLast++; } +#endif } /* @@ -853,7 +889,9 @@ PVRSRV_ERROR PVRSRVRGXSubmitTransferKM(RGX_SERVER_TQ_CONTEXT *psTransferContext, puiUpdateFenceUID = &ui3DUpdateFenceUID; } } - else if (TQ_PREP_FLAGS_COMMAND_IS(pui32TQPrepareFlags[i], 2D) && + else +#if defined(RGX_FEATURE_TLA_BIT_MASK) + if (TQ_PREP_FLAGS_COMMAND_IS(pui32TQPrepareFlags[i], 2D) && (RGX_IS_FEATURE_SUPPORTED(psDevInfo, TLA))) { psServerCommonCtx = psTransferContext->s2DData.psServerCommonContext; @@ -881,6 +919,7 @@ PVRSRV_ERROR PVRSRVRGXSubmitTransferKM(RGX_SERVER_TQ_CONTEXT *psTransferContext, } } else +#endif { eError = PVRSRV_ERROR_INVALID_PARAMS; goto fail_prepare_loop; @@ -1190,7 +1229,8 @@ PVRSRV_ERROR PVRSRVRGXSubmitTransferKM(RGX_SERVER_TQ_CONTEXT *psTransferContext, /* Create the command helper data for this command */ - RGXCmdHelperInitCmdCCB(psClientCCB, + RGXCmdHelperInitCmdCCB(psDevInfo, + psClientCCB, 0, ui32IntClientFenceCount, pauiIntFenceUFOAddress, @@ -1226,7 +1266,8 @@ PVRSRV_ERROR PVRSRVRGXSubmitTransferKM(RGX_SERVER_TQ_CONTEXT *psTransferContext, } } - if (ui322DCmdCount) +#if defined(RGX_FEATURE_TLA_BIT_MASK) + if ((ui322DCmdCount) && (RGX_IS_FEATURE_SUPPORTED(psDevInfo, TLA))) { eError = RGXCmdHelperAcquireCmdCCB(ui322DCmdCount, &pas2DCmdHelper[0]); @@ -1235,6 +1276,7 @@ PVRSRV_ERROR PVRSRVRGXSubmitTransferKM(RGX_SERVER_TQ_CONTEXT *psTransferContext, goto fail_cmdacquire; } } +#endif /* We should acquire the kernel CCB(s) space here as the schedule could fail @@ -1250,6 +1292,7 @@ PVRSRV_ERROR PVRSRVRGXSubmitTransferKM(RGX_SERVER_TQ_CONTEXT *psTransferContext, FWCommonContextGetFWAddress(psTransferContext->s3DData.psServerCommonContext).ui32Addr); } +#if defined(RGX_FEATURE_TLA_BIT_MASK) if ((ui322DCmdCount) && (RGX_IS_FEATURE_SUPPORTED(psDevInfo, TLA))) { ui322DCmdOffset = RGXGetHostWriteOffsetCCB(FWCommonContextGetClientCCB(psTransferContext->s2DData.psServerCommonContext)); @@ -1258,6 +1301,7 @@ PVRSRV_ERROR PVRSRVRGXSubmitTransferKM(RGX_SERVER_TQ_CONTEXT *psTransferContext, "TQ_2D", FWCommonContextGetFWAddress(psTransferContext->s2DData.psServerCommonContext).ui32Addr); } +#endif if (ui323DCmdCount) { @@ -1307,7 +1351,6 @@ PVRSRV_ERROR PVRSRVRGXSubmitTransferKM(RGX_SERVER_TQ_CONTEXT *psTransferContext, eError2 = RGXScheduleCommand(psDevInfo, RGXFWIF_DM_3D, &s3DKCCBCmd, - ui32ClientCacheOpSeqNum, ui32PDumpFlags); if (eError2 != PVRSRV_ERROR_RETRY) { @@ -1330,6 +1373,7 @@ PVRSRV_ERROR PVRSRVRGXSubmitTransferKM(RGX_SERVER_TQ_CONTEXT *psTransferContext, ui32IntJobRef, RGX_HWPERF_KICK_TYPE_TQ3D); } +#if defined(RGX_FEATURE_TLA_BIT_MASK) if ((ui322DCmdCount) && (RGX_IS_FEATURE_SUPPORTED(psDevInfo, TLA))) { RGXFWIF_KCCB_CMD s2DKCCBCmd; @@ -1376,7 +1420,6 @@ PVRSRV_ERROR PVRSRVRGXSubmitTransferKM(RGX_SERVER_TQ_CONTEXT *psTransferContext, eError2 = RGXScheduleCommand(psDevInfo, RGXFWIF_DM_2D, &s2DKCCBCmd, - ui32ClientCacheOpSeqNum, ui32PDumpFlags); if (eError2 != PVRSRV_ERROR_RETRY) { @@ -1398,6 +1441,7 @@ PVRSRV_ERROR PVRSRVRGXSubmitTransferKM(RGX_SERVER_TQ_CONTEXT *psTransferContext, PVRGpuTraceEnqueueEvent(psDeviceNode, ui32FWCtx, ui32ExtJobRef, ui32IntJobRef, RGX_HWPERF_KICK_TYPE_TQ2D); } +#endif /* * Now check eError (which may have returned an error from our earlier calls @@ -1411,6 +1455,7 @@ PVRSRV_ERROR PVRSRVRGXSubmitTransferKM(RGX_SERVER_TQ_CONTEXT *psTransferContext, #if defined(NO_HARDWARE) /* If NO_HARDWARE, signal the output fence's sync checkpoint and sync prim */ +#if defined(RGX_FEATURE_TLA_BIT_MASK) if (ps2DUpdateSyncCheckpoint) { CHKPT_DBG((PVR_DBG_ERROR, "%s: Signalling TLA NOHW sync checkpoint<%p>, ID:%d, FwAddr=0x%x", __func__, (void*)ps2DUpdateSyncCheckpoint, SyncCheckpointGetId(ps2DUpdateSyncCheckpoint), SyncCheckpointGetFirmwareAddr(ps2DUpdateSyncCheckpoint))); @@ -1421,6 +1466,7 @@ PVRSRV_ERROR PVRSRVRGXSubmitTransferKM(RGX_SERVER_TQ_CONTEXT *psTransferContext, CHKPT_DBG((PVR_DBG_ERROR, "%s: Updating TLA NOHW sync prim<%p> to %d", __func__, (void*)ps2DFenceTimelineUpdateSync, ui322DFenceTimelineUpdateValue)); SyncPrimNoHwUpdate(ps2DFenceTimelineUpdateSync, ui322DFenceTimelineUpdateValue); } +#endif if (ps3DUpdateSyncCheckpoint) { CHKPT_DBG((PVR_DBG_ERROR, "%s: Signalling TQ3D NOHW sync checkpoint<%p>, ID:%d, FwAddr=0x%x", __func__, (void*)ps3DUpdateSyncCheckpoint, SyncCheckpointGetId(ps3DUpdateSyncCheckpoint), SyncCheckpointGetFirmwareAddr(ps3DUpdateSyncCheckpoint))); @@ -1445,26 +1491,32 @@ PVRSRV_ERROR PVRSRVRGXSubmitTransferKM(RGX_SERVER_TQ_CONTEXT *psTransferContext, } #endif /* defined(SUPPORT_BUFFER_SYNC) */ +#if defined(RGX_FEATURE_TLA_BIT_MASK) if (pi2DUpdateFence) { *pi2DUpdateFence = i2DUpdateFence; } +#endif if (pi3DUpdateFence) { *pi3DUpdateFence = i3DUpdateFence; } +#if defined(RGX_FEATURE_TLA_BIT_MASK) if (pv2DUpdateFenceFinaliseData && (i2DUpdateFence != PVRSRV_NO_FENCE)) { SyncCheckpointFinaliseFence(psDeviceNode, i2DUpdateFence, pv2DUpdateFenceFinaliseData, ps2DUpdateSyncCheckpoint, szFenceName); } +#endif if (pv3DUpdateFenceFinaliseData && (i3DUpdateFence != PVRSRV_NO_FENCE)) { SyncCheckpointFinaliseFence(psDeviceNode, i3DUpdateFence, pv3DUpdateFenceFinaliseData, ps3DUpdateSyncCheckpoint, szFenceName); } +#if defined(RGX_FEATURE_TLA_BIT_MASK) OSFreeMem(pas2DCmdHelper); +#endif OSFreeMem(pas3DCmdHelper); /* Drop the references taken on the sync checkpoints in the @@ -1477,11 +1529,13 @@ PVRSRV_ERROR PVRSRVRGXSubmitTransferKM(RGX_SERVER_TQ_CONTEXT *psTransferContext, SyncCheckpointFreeCheckpointListMem(apsFenceSyncCheckpoints); } /* Free memory allocated to hold the internal list of update values */ +#if defined(RGX_FEATURE_TLA_BIT_MASK) if (pui322DIntAllocatedUpdateValues) { OSFreeMem(pui322DIntAllocatedUpdateValues); pui322DIntAllocatedUpdateValues = NULL; } +#endif if (pui323DIntAllocatedUpdateValues) { OSFreeMem(pui323DIntAllocatedUpdateValues); @@ -1516,21 +1570,24 @@ fail_prepare_loop: #endif /* Free memory allocated to hold the internal list of update values */ +#if defined(RGX_FEATURE_TLA_BIT_MASK) if (pui322DIntAllocatedUpdateValues) { OSFreeMem(pui322DIntAllocatedUpdateValues); pui322DIntAllocatedUpdateValues = NULL; } +#endif if (pui323DIntAllocatedUpdateValues) { OSFreeMem(pui323DIntAllocatedUpdateValues); pui323DIntAllocatedUpdateValues = NULL; } - +#if defined(RGX_FEATURE_TLA_BIT_MASK) if (i2DUpdateFence != PVRSRV_NO_FENCE) { SyncCheckpointRollbackFenceData(i2DUpdateFence, pv2DUpdateFenceFinaliseData); } +#endif if (i3DUpdateFence != PVRSRV_NO_FENCE) { SyncCheckpointRollbackFenceData(i3DUpdateFence, pv3DUpdateFenceFinaliseData); @@ -1561,8 +1618,10 @@ fail_resolve_buffersync_input_fence: SyncCheckpointFreeCheckpointListMem(apsFenceSyncCheckpoints); } fail_resolve_fencesync_input_fence: +#if defined(RGX_FEATURE_TLA_BIT_MASK) OSFreeMem(pas2DCmdHelper); fail_alloc2dhelper: +#endif OSFreeMem(pas3DCmdHelper); fail_alloc3dhelper: @@ -1577,12 +1636,14 @@ PVRSRV_ERROR PVRSRVRGXSetTransferContextPriorityKM(CONNECTION_DATA *psConnection IMG_UINT32 ui32Priority) { PVRSRV_ERROR eError; +#if defined(RGX_FEATURE_TLA_BIT_MASK) PVRSRV_RGXDEV_INFO *psDevInfo = psDevNode->pvDevice; - +#endif PVR_UNREFERENCED_PARAMETER(psDevNode); OSLockAcquire(psTransferContext->hLock); +#if defined(RGX_FEATURE_TLA_BIT_MASK) if ((psTransferContext->s2DData.ui32Priority != ui32Priority) && (RGX_IS_FEATURE_SUPPORTED(psDevInfo, TLA))) { @@ -1601,6 +1662,7 @@ PVRSRV_ERROR PVRSRVRGXSetTransferContextPriorityKM(CONNECTION_DATA *psConnection } psTransferContext->s2DData.ui32Priority = ui32Priority; } +#endif if (psTransferContext->s3DData.ui32Priority != ui32Priority) { @@ -1624,8 +1686,10 @@ PVRSRV_ERROR PVRSRVRGXSetTransferContextPriorityKM(CONNECTION_DATA *psConnection return PVRSRV_OK; fail_3dcontext: +#if defined(RGX_FEATURE_TLA_BIT_MASK) fail_2dcontext: +#endif OSLockRelease(psTransferContext->hLock); PVR_ASSERT(eError != PVRSRV_OK); return eError; @@ -1636,28 +1700,23 @@ PVRSRV_ERROR PVRSRVRGXSetTransferContextPropertyKM(RGX_SERVER_TQ_CONTEXT *psTran IMG_UINT64 ui64Input, IMG_UINT64 *pui64Output) { - PVRSRV_ERROR eError; - PVRSRV_ERROR eError2 = PVRSRV_OK; + PVRSRV_ERROR eError = PVRSRV_OK; switch (eContextProperty) { case RGX_CONTEXT_PROPERTY_FLAGS: { + IMG_UINT32 ui32ContextFlags = (IMG_UINT32)ui64Input; + OSLockAcquire(psTransferContext->hLock); eError = FWCommonContextSetFlags(psTransferContext->s2DData.psServerCommonContext, - (IMG_UINT32)ui64Input); + ui32ContextFlags); if (eError == PVRSRV_OK) { - eError2 = FWCommonContextSetFlags(psTransferContext->s3DData.psServerCommonContext, - (IMG_UINT32)ui64Input); - } - if ((eError == PVRSRV_OK) && (eError2 == PVRSRV_OK)) - { - psTransferContext->ui32Flags = (IMG_UINT32)ui64Input; + eError = FWCommonContextSetFlags(psTransferContext->s3DData.psServerCommonContext, + ui32ContextFlags); } OSLockRelease(psTransferContext->hLock); - PVR_LOG_IF_ERROR(eError, "FWCommonContextSetFlags eError"); - PVR_LOG_IF_ERROR(eError2, "FWCommonContextSetFlags eError2"); break; } @@ -1685,12 +1744,14 @@ void DumpTransferCtxtsInfo(PVRSRV_RGXDEV_INFO *psDevInfo, RGX_SERVER_TQ_CONTEXT *psCurrentServerTransferCtx = IMG_CONTAINER_OF(psNode, RGX_SERVER_TQ_CONTEXT, sListNode); +#if defined(RGX_FEATURE_TLA_BIT_MASK) if ((psCurrentServerTransferCtx->ui32Flags & RGX_SERVER_TQ_CONTEXT_FLAGS_2D) && (RGX_IS_FEATURE_SUPPORTED(psDevInfo, TLA))) { DumpFWCommonContextInfo(psCurrentServerTransferCtx->s2DData.psServerCommonContext, pfnDumpDebugPrintf, pvDumpDebugFile, ui32VerbLevel); } +#endif if (psCurrentServerTransferCtx->ui32Flags & RGX_SERVER_TQ_CONTEXT_FLAGS_3D) { @@ -1714,6 +1775,7 @@ IMG_UINT32 CheckForStalledClientTransferCtxt(PVRSRV_RGXDEV_INFO *psDevInfo) RGX_SERVER_TQ_CONTEXT *psCurrentServerTransferCtx = IMG_CONTAINER_OF(psNode, RGX_SERVER_TQ_CONTEXT, sListNode); +#if defined(RGX_FEATURE_TLA_BIT_MASK) if ((psCurrentServerTransferCtx->ui32Flags & RGX_SERVER_TQ_CONTEXT_FLAGS_2D) && (NULL != psCurrentServerTransferCtx->s2DData.psServerCommonContext) && (RGX_IS_FEATURE_SUPPORTED(psDevInfo, TLA))) @@ -1723,6 +1785,7 @@ IMG_UINT32 CheckForStalledClientTransferCtxt(PVRSRV_RGXDEV_INFO *psDevInfo) ui32ContextBitMask |= RGX_KICK_TYPE_DM_TQ2D; } } +#endif if ((psCurrentServerTransferCtx->ui32Flags & RGX_SERVER_TQ_CONTEXT_FLAGS_3D) && (NULL != psCurrentServerTransferCtx->s3DData.psServerCommonContext)) { diff --git a/drivers/gpu/drm/img-rogue/rgxtransfer.h b/drivers/gpu/drm/img-rogue/rgxtransfer.h index bd763f707..cbc5b73f6 100644 --- a/drivers/gpu/drm/img-rogue/rgxtransfer.h +++ b/drivers/gpu/drm/img-rogue/rgxtransfer.h @@ -78,6 +78,7 @@ PVRSRV_ERROR PVRSRVRGXCreateTransferContextKM(CONNECTION_DATA *psConnection, IMG_HANDLE hMemCtxPrivData, IMG_UINT32 ui32PackedCCBSizeU8888, IMG_UINT32 ui32ContextFlags, + IMG_UINT64 ui64RobustnessAddress, RGX_SERVER_TQ_CONTEXT **ppsTransferContext, PMR **ppsCLIPMRMem, PMR **ppsUSCPMRMem); @@ -111,7 +112,6 @@ PVRSRV_ERROR PVRSRVRGXDestroyTransferContextKM(RGX_SERVER_TQ_CONTEXT *psTransfer ******************************************************************************/ PVRSRV_ERROR PVRSRVRGXSubmitTransferKM(RGX_SERVER_TQ_CONTEXT *psTransferContext, - IMG_UINT32 ui32ClientCacheOpSeqNum, IMG_UINT32 ui32PrepareCount, IMG_UINT32 *paui32ClientUpdateCount, SYNC_PRIMITIVE_BLOCK ***papauiClientUpdateUFODevVarBlock, diff --git a/drivers/gpu/drm/img-rogue/rgxutils.c b/drivers/gpu/drm/img-rogue/rgxutils.c index a7680d694..866fd014a 100644 --- a/drivers/gpu/drm/img-rogue/rgxutils.c +++ b/drivers/gpu/drm/img-rogue/rgxutils.c @@ -75,7 +75,9 @@ PVRSRV_ERROR RGXSetAPMState(const PVRSRV_DEVICE_NODE *psDeviceNode, IMG_UINT32 ui32State) { PVRSRV_ERROR eError = PVRSRV_OK; +#if !defined(NO_HARDWARE) PVRSRV_RGXDEV_INFO *psDevInfo; +#endif PVR_UNREFERENCED_PARAMETER(pvPrivateData); @@ -84,17 +86,15 @@ PVRSRV_ERROR RGXSetAPMState(const PVRSRV_DEVICE_NODE *psDeviceNode, return PVRSRV_ERROR_INVALID_PARAMS; } - psDevInfo = psDeviceNode->pvDevice; - - if (RGX_ACTIVEPM_FORCE_OFF != ui32State - || !psDevInfo->pvAPMISRData) + if (RGX_ACTIVEPM_FORCE_OFF != ui32State) { return PVRSRV_ERROR_NOT_SUPPORTED; } #if !defined(NO_HARDWARE) - eError = OSUninstallMISR(psDevInfo->pvAPMISRData); - if (PVRSRV_OK == eError) + psDevInfo = psDeviceNode->pvDevice; + + if (psDevInfo->pvAPMISRData) { psDevInfo->eActivePMConf = RGX_ACTIVEPM_FORCE_OFF; psDevInfo->pvAPMISRData = NULL; diff --git a/drivers/gpu/drm/img-rogue/ri_server.c b/drivers/gpu/drm/img-rogue/ri_server.c index 6d9e69e01..d1fe2b286 100644 --- a/drivers/gpu/drm/img-rogue/ri_server.c +++ b/drivers/gpu/drm/img-rogue/ri_server.c @@ -41,7 +41,16 @@ IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. */ /**************************************************************************/ -#include +#if defined(__linux__) + #include + #if (LINUX_VERSION_CODE >= KERNEL_VERSION(5, 15, 0)) + #include + #else + #include + #endif /* LINUX_VERSION_CODE >= KERNEL_VERSION(5, 15, 0) */ +#else + #include +#endif /* __linux__ */ #include "img_defs.h" #include "allocmem.h" #include "pvr_debug.h" diff --git a/drivers/gpu/drm/img-rogue/server_cache_bridge.c b/drivers/gpu/drm/img-rogue/server_cache_bridge.c index 420e58031..18509ba08 100644 --- a/drivers/gpu/drm/img-rogue/server_cache_bridge.c +++ b/drivers/gpu/drm/img-rogue/server_cache_bridge.c @@ -269,12 +269,7 @@ PVRSRVBridgeCacheOpQueue(IMG_UINT32 ui32DispatchTableEntry, psCacheOpQueueIN->ui32NumCacheOps, psPMRInt, ui64AddressInt, - uiOffsetInt, - uiSizeInt, - iuCacheOpInt, - psCacheOpQueueIN->ui32OpTimeline, - psCacheOpQueueIN->ui32CurrentFenceSeqNum, - &psCacheOpQueueOUT->ui32NextFenceSeqNum); + uiOffsetInt, uiSizeInt, iuCacheOpInt, psCacheOpQueueIN->ui32OpTimeline); CacheOpQueue_exit: @@ -402,9 +397,8 @@ PVRSRVBridgeCacheOpLog(IMG_UINT32 ui32DispatchTableEntry, psCacheOpLogIN->ui64Address, psCacheOpLogIN->uiOffset, psCacheOpLogIN->uiSize, - psCacheOpLogIN->i64QueuedTimeUs, - psCacheOpLogIN->i64ExecuteTimeUs, - psCacheOpLogIN->i32NumRBF, psCacheOpLogIN->iuCacheOp); + psCacheOpLogIN->i64StartTime, + psCacheOpLogIN->i64EndTime, psCacheOpLogIN->iuCacheOp); CacheOpLog_exit: @@ -428,7 +422,7 @@ CacheOpLog_exit: */ PVRSRV_ERROR InitCACHEBridge(void); -PVRSRV_ERROR DeinitCACHEBridge(void); +void DeinitCACHEBridge(void); /* * Register all CACHE functions with services @@ -451,7 +445,7 @@ PVRSRV_ERROR InitCACHEBridge(void) /* * Unregister all cache functions with services */ -PVRSRV_ERROR DeinitCACHEBridge(void) +void DeinitCACHEBridge(void) { UnsetDispatchTableEntry(PVRSRV_BRIDGE_CACHE, PVRSRV_BRIDGE_CACHE_CACHEOPQUEUE); @@ -460,5 +454,4 @@ PVRSRV_ERROR DeinitCACHEBridge(void) UnsetDispatchTableEntry(PVRSRV_BRIDGE_CACHE, PVRSRV_BRIDGE_CACHE_CACHEOPLOG); - return PVRSRV_OK; } diff --git a/drivers/gpu/drm/img-rogue/server_cmm_bridge.c b/drivers/gpu/drm/img-rogue/server_cmm_bridge.c index e66206706..b95f8589a 100644 --- a/drivers/gpu/drm/img-rogue/server_cmm_bridge.c +++ b/drivers/gpu/drm/img-rogue/server_cmm_bridge.c @@ -199,10 +199,11 @@ PVRSRVBridgeDevmemIntUnexportCtx(IMG_UINT32 ui32DispatchTableEntry, LockHandle(psConnection->psHandleBase); psDevmemIntUnexportCtxOUT->eError = - PVRSRVReleaseHandleStagedUnlock(psConnection->psHandleBase, - (IMG_HANDLE) psDevmemIntUnexportCtxIN->hContextExport, - PVRSRV_HANDLE_TYPE_DEVMEMINT_CTX_EXPORT); + PVRSRVDestroyHandleStagedUnlocked(psConnection->psHandleBase, + (IMG_HANDLE) psDevmemIntUnexportCtxIN->hContextExport, + PVRSRV_HANDLE_TYPE_DEVMEMINT_CTX_EXPORT); if (unlikely((psDevmemIntUnexportCtxOUT->eError != PVRSRV_OK) && + (psDevmemIntUnexportCtxOUT->eError != PVRSRV_ERROR_KERNEL_CCB_FULL) && (psDevmemIntUnexportCtxOUT->eError != PVRSRV_ERROR_RETRY))) { PVR_DPF((PVR_DBG_ERROR, @@ -325,7 +326,7 @@ DevmemIntAcquireRemoteCtx_exit: /* Lock over handle creation cleanup. */ LockHandle(psConnection->psHandleBase); - eError = PVRSRVReleaseHandleUnlocked(psConnection->psHandleBase, + eError = PVRSRVDestroyHandleUnlocked(psConnection->psHandleBase, (IMG_HANDLE) psDevmemIntAcquireRemoteCtxOUT-> hContext, @@ -363,7 +364,7 @@ DevmemIntAcquireRemoteCtx_exit: #if !defined(EXCLUDE_CMM_BRIDGE) PVRSRV_ERROR InitCMMBridge(void); -PVRSRV_ERROR DeinitCMMBridge(void); +void DeinitCMMBridge(void); /* * Register all CMM functions with services @@ -386,7 +387,7 @@ PVRSRV_ERROR InitCMMBridge(void) /* * Unregister all cmm functions with services */ -PVRSRV_ERROR DeinitCMMBridge(void) +void DeinitCMMBridge(void) { UnsetDispatchTableEntry(PVRSRV_BRIDGE_CMM, PVRSRV_BRIDGE_CMM_DEVMEMINTEXPORTCTX); @@ -395,7 +396,6 @@ PVRSRV_ERROR DeinitCMMBridge(void) UnsetDispatchTableEntry(PVRSRV_BRIDGE_CMM, PVRSRV_BRIDGE_CMM_DEVMEMINTACQUIREREMOTECTX); - return PVRSRV_OK; } #else /* EXCLUDE_CMM_BRIDGE */ /* This bridge is conditional on EXCLUDE_CMM_BRIDGE - when defined, @@ -404,7 +404,6 @@ PVRSRV_ERROR DeinitCMMBridge(void) #define InitCMMBridge() \ PVRSRV_OK -#define DeinitCMMBridge() \ - PVRSRV_OK +#define DeinitCMMBridge() #endif /* EXCLUDE_CMM_BRIDGE */ diff --git a/drivers/gpu/drm/img-rogue/server_devicememhistory_bridge.c b/drivers/gpu/drm/img-rogue/server_devicememhistory_bridge.c index e3ecb2535..db440d051 100644 --- a/drivers/gpu/drm/img-rogue/server_devicememhistory_bridge.c +++ b/drivers/gpu/drm/img-rogue/server_devicememhistory_bridge.c @@ -788,7 +788,7 @@ DevicememHistorySparseChange_exit: static POS_LOCK pDEVICEMEMHISTORYBridgeLock; PVRSRV_ERROR InitDEVICEMEMHISTORYBridge(void); -PVRSRV_ERROR DeinitDEVICEMEMHISTORYBridge(void); +void DeinitDEVICEMEMHISTORYBridge(void); /* * Register all DEVICEMEMHISTORY functions with services @@ -824,9 +824,9 @@ PVRSRV_ERROR InitDEVICEMEMHISTORYBridge(void) /* * Unregister all devicememhistory functions with services */ -PVRSRV_ERROR DeinitDEVICEMEMHISTORYBridge(void) +void DeinitDEVICEMEMHISTORYBridge(void) { - PVR_LOG_RETURN_IF_ERROR(OSLockDestroy(pDEVICEMEMHISTORYBridgeLock), "OSLockDestroy"); + OSLockDestroy(pDEVICEMEMHISTORYBridgeLock); UnsetDispatchTableEntry(PVRSRV_BRIDGE_DEVICEMEMHISTORY, PVRSRV_BRIDGE_DEVICEMEMHISTORY_DEVICEMEMHISTORYMAP); @@ -843,5 +843,4 @@ PVRSRV_ERROR DeinitDEVICEMEMHISTORYBridge(void) UnsetDispatchTableEntry(PVRSRV_BRIDGE_DEVICEMEMHISTORY, PVRSRV_BRIDGE_DEVICEMEMHISTORY_DEVICEMEMHISTORYSPARSECHANGE); - return PVRSRV_OK; } diff --git a/drivers/gpu/drm/img-rogue/server_di_bridge.c b/drivers/gpu/drm/img-rogue/server_di_bridge.c index 7200b215b..49a97a051 100644 --- a/drivers/gpu/drm/img-rogue/server_di_bridge.c +++ b/drivers/gpu/drm/img-rogue/server_di_bridge.c @@ -223,10 +223,11 @@ PVRSRVBridgeDIDestroyContext(IMG_UINT32 ui32DispatchTableEntry, LockHandle(psConnection->psHandleBase); psDIDestroyContextOUT->eError = - PVRSRVReleaseHandleStagedUnlock(psConnection->psHandleBase, - (IMG_HANDLE) psDIDestroyContextIN->hContext, - PVRSRV_HANDLE_TYPE_DI_CONTEXT); + PVRSRVDestroyHandleStagedUnlocked(psConnection->psHandleBase, + (IMG_HANDLE) psDIDestroyContextIN->hContext, + PVRSRV_HANDLE_TYPE_DI_CONTEXT); if (unlikely((psDIDestroyContextOUT->eError != PVRSRV_OK) && + (psDIDestroyContextOUT->eError != PVRSRV_ERROR_KERNEL_CCB_FULL) && (psDIDestroyContextOUT->eError != PVRSRV_ERROR_RETRY))) { PVR_DPF((PVR_DBG_ERROR, @@ -593,7 +594,7 @@ DIListAllEntries_exit: */ PVRSRV_ERROR InitDIBridge(void); -PVRSRV_ERROR DeinitDIBridge(void); +void DeinitDIBridge(void); /* * Register all DI functions with services @@ -622,7 +623,7 @@ PVRSRV_ERROR InitDIBridge(void) /* * Unregister all di functions with services */ -PVRSRV_ERROR DeinitDIBridge(void) +void DeinitDIBridge(void) { UnsetDispatchTableEntry(PVRSRV_BRIDGE_DI, PVRSRV_BRIDGE_DI_DICREATECONTEXT); @@ -635,5 +636,4 @@ PVRSRV_ERROR DeinitDIBridge(void) UnsetDispatchTableEntry(PVRSRV_BRIDGE_DI, PVRSRV_BRIDGE_DI_DILISTALLENTRIES); - return PVRSRV_OK; } diff --git a/drivers/gpu/drm/img-rogue/server_dmabuf_bridge.c b/drivers/gpu/drm/img-rogue/server_dmabuf_bridge.c index bc95a0b3d..07851ded9 100644 --- a/drivers/gpu/drm/img-rogue/server_dmabuf_bridge.c +++ b/drivers/gpu/drm/img-rogue/server_dmabuf_bridge.c @@ -229,6 +229,170 @@ PhysmemImportDmaBuf_exit: return 0; } +static PVRSRV_ERROR _PhysmemImportDmaBufLockedpsPMRPtrIntRelease(void *pvData) +{ + PVRSRV_ERROR eError; + eError = PMRUnrefUnlockPMR((PMR *) pvData); + return eError; +} + +static_assert(DEVMEM_ANNOTATION_MAX_LEN <= IMG_UINT32_MAX, + "DEVMEM_ANNOTATION_MAX_LEN must not be larger than IMG_UINT32_MAX"); + +static IMG_INT +PVRSRVBridgePhysmemImportDmaBufLocked(IMG_UINT32 ui32DispatchTableEntry, + IMG_UINT8 * psPhysmemImportDmaBufLockedIN_UI8, + IMG_UINT8 * psPhysmemImportDmaBufLockedOUT_UI8, + CONNECTION_DATA * psConnection) +{ + PVRSRV_BRIDGE_IN_PHYSMEMIMPORTDMABUFLOCKED *psPhysmemImportDmaBufLockedIN = + (PVRSRV_BRIDGE_IN_PHYSMEMIMPORTDMABUFLOCKED *) + IMG_OFFSET_ADDR(psPhysmemImportDmaBufLockedIN_UI8, 0); + PVRSRV_BRIDGE_OUT_PHYSMEMIMPORTDMABUFLOCKED *psPhysmemImportDmaBufLockedOUT = + (PVRSRV_BRIDGE_OUT_PHYSMEMIMPORTDMABUFLOCKED *) + IMG_OFFSET_ADDR(psPhysmemImportDmaBufLockedOUT_UI8, 0); + + IMG_CHAR *uiNameInt = NULL; + PMR *psPMRPtrInt = NULL; + + IMG_UINT32 ui32NextOffset = 0; + IMG_BYTE *pArrayArgsBuffer = NULL; +#if !defined(INTEGRITY_OS) + IMG_BOOL bHaveEnoughSpace = IMG_FALSE; +#endif + + IMG_UINT32 ui32BufferSize = 0; + IMG_UINT64 ui64BufferSize = + ((IMG_UINT64) psPhysmemImportDmaBufLockedIN->ui32NameSize * sizeof(IMG_CHAR)) + 0; + + if (unlikely(psPhysmemImportDmaBufLockedIN->ui32NameSize > DEVMEM_ANNOTATION_MAX_LEN)) + { + psPhysmemImportDmaBufLockedOUT->eError = PVRSRV_ERROR_BRIDGE_ARRAY_SIZE_TOO_BIG; + goto PhysmemImportDmaBufLocked_exit; + } + + if (ui64BufferSize > IMG_UINT32_MAX) + { + psPhysmemImportDmaBufLockedOUT->eError = PVRSRV_ERROR_BRIDGE_BUFFER_TOO_SMALL; + goto PhysmemImportDmaBufLocked_exit; + } + + ui32BufferSize = (IMG_UINT32) ui64BufferSize; + + if (ui32BufferSize != 0) + { +#if !defined(INTEGRITY_OS) + /* Try to use remainder of input buffer for copies if possible, word-aligned for safety. */ + IMG_UINT32 ui32InBufferOffset = + PVR_ALIGN(sizeof(*psPhysmemImportDmaBufLockedIN), sizeof(unsigned long)); + IMG_UINT32 ui32InBufferExcessSize = + ui32InBufferOffset >= + PVRSRV_MAX_BRIDGE_IN_SIZE ? 0 : PVRSRV_MAX_BRIDGE_IN_SIZE - ui32InBufferOffset; + + bHaveEnoughSpace = ui32BufferSize <= ui32InBufferExcessSize; + if (bHaveEnoughSpace) + { + IMG_BYTE *pInputBuffer = (IMG_BYTE *) (void *)psPhysmemImportDmaBufLockedIN; + + pArrayArgsBuffer = &pInputBuffer[ui32InBufferOffset]; + } + else +#endif + { + pArrayArgsBuffer = OSAllocMemNoStats(ui32BufferSize); + + if (!pArrayArgsBuffer) + { + psPhysmemImportDmaBufLockedOUT->eError = PVRSRV_ERROR_OUT_OF_MEMORY; + goto PhysmemImportDmaBufLocked_exit; + } + } + } + + if (psPhysmemImportDmaBufLockedIN->ui32NameSize != 0) + { + uiNameInt = (IMG_CHAR *) IMG_OFFSET_ADDR(pArrayArgsBuffer, ui32NextOffset); + ui32NextOffset += psPhysmemImportDmaBufLockedIN->ui32NameSize * sizeof(IMG_CHAR); + } + + /* Copy the data over */ + if (psPhysmemImportDmaBufLockedIN->ui32NameSize * sizeof(IMG_CHAR) > 0) + { + if (OSCopyFromUser + (NULL, uiNameInt, (const void __user *)psPhysmemImportDmaBufLockedIN->puiName, + psPhysmemImportDmaBufLockedIN->ui32NameSize * sizeof(IMG_CHAR)) != PVRSRV_OK) + { + psPhysmemImportDmaBufLockedOUT->eError = PVRSRV_ERROR_INVALID_PARAMS; + + goto PhysmemImportDmaBufLocked_exit; + } + ((IMG_CHAR *) + uiNameInt)[(psPhysmemImportDmaBufLockedIN->ui32NameSize * sizeof(IMG_CHAR)) - 1] = + '\0'; + } + + psPhysmemImportDmaBufLockedOUT->eError = + PhysmemImportDmaBufLocked(psConnection, OSGetDevNode(psConnection), + psPhysmemImportDmaBufLockedIN->ifd, + psPhysmemImportDmaBufLockedIN->uiFlags, + psPhysmemImportDmaBufLockedIN->ui32NameSize, + uiNameInt, + &psPMRPtrInt, + &psPhysmemImportDmaBufLockedOUT->uiSize, + &psPhysmemImportDmaBufLockedOUT->uiAlign); + /* Exit early if bridged call fails */ + if (unlikely(psPhysmemImportDmaBufLockedOUT->eError != PVRSRV_OK)) + { + goto PhysmemImportDmaBufLocked_exit; + } + + /* Lock over handle creation. */ + LockHandle(psConnection->psHandleBase); + + psPhysmemImportDmaBufLockedOUT->eError = + PVRSRVAllocHandleUnlocked(psConnection->psHandleBase, + &psPhysmemImportDmaBufLockedOUT->hPMRPtr, (void *)psPMRPtrInt, + PVRSRV_HANDLE_TYPE_PHYSMEM_PMR, + PVRSRV_HANDLE_ALLOC_FLAG_MULTI, + (PFN_HANDLE_RELEASE) & + _PhysmemImportDmaBufLockedpsPMRPtrIntRelease); + if (unlikely(psPhysmemImportDmaBufLockedOUT->eError != PVRSRV_OK)) + { + UnlockHandle(psConnection->psHandleBase); + goto PhysmemImportDmaBufLocked_exit; + } + + /* Release now we have created handles. */ + UnlockHandle(psConnection->psHandleBase); + +PhysmemImportDmaBufLocked_exit: + + if (psPhysmemImportDmaBufLockedOUT->eError != PVRSRV_OK) + { + if (psPMRPtrInt) + { + LockHandle(KERNEL_HANDLE_BASE); + PMRUnrefUnlockPMR(psPMRPtrInt); + UnlockHandle(KERNEL_HANDLE_BASE); + } + } + + /* Allocated space should be equal to the last updated offset */ +#ifdef PVRSRV_NEED_PVR_ASSERT + if (psPhysmemImportDmaBufLockedOUT->eError == PVRSRV_OK) + PVR_ASSERT(ui32BufferSize == ui32NextOffset); +#endif /* PVRSRV_NEED_PVR_ASSERT */ + +#if defined(INTEGRITY_OS) + if (pArrayArgsBuffer) +#else + if (!bHaveEnoughSpace && pArrayArgsBuffer) +#endif + OSFreeMemNoStats(pArrayArgsBuffer); + + return 0; +} + static IMG_INT PVRSRVBridgePhysmemExportDmaBuf(IMG_UINT32 ui32DispatchTableEntry, IMG_UINT8 * psPhysmemExportDmaBufIN_UI8, @@ -483,176 +647,12 @@ PhysmemImportSparseDmaBuf_exit: return 0; } -static PVRSRV_ERROR _PhysmemImportDmaBufLockedpsPMRPtrIntRelease(void *pvData) -{ - PVRSRV_ERROR eError; - eError = PMRUnrefUnlockPMR((PMR *) pvData); - return eError; -} - -static_assert(DEVMEM_ANNOTATION_MAX_LEN <= IMG_UINT32_MAX, - "DEVMEM_ANNOTATION_MAX_LEN must not be larger than IMG_UINT32_MAX"); - -static IMG_INT -PVRSRVBridgePhysmemImportDmaBufLocked(IMG_UINT32 ui32DispatchTableEntry, - IMG_UINT8 * psPhysmemImportDmaBufLockedIN_UI8, - IMG_UINT8 * psPhysmemImportDmaBufLockedOUT_UI8, - CONNECTION_DATA * psConnection) -{ - PVRSRV_BRIDGE_IN_PHYSMEMIMPORTDMABUFLOCKED *psPhysmemImportDmaBufLockedIN = - (PVRSRV_BRIDGE_IN_PHYSMEMIMPORTDMABUFLOCKED *) - IMG_OFFSET_ADDR(psPhysmemImportDmaBufLockedIN_UI8, 0); - PVRSRV_BRIDGE_OUT_PHYSMEMIMPORTDMABUFLOCKED *psPhysmemImportDmaBufLockedOUT = - (PVRSRV_BRIDGE_OUT_PHYSMEMIMPORTDMABUFLOCKED *) - IMG_OFFSET_ADDR(psPhysmemImportDmaBufLockedOUT_UI8, 0); - - IMG_CHAR *uiNameInt = NULL; - PMR *psPMRPtrInt = NULL; - - IMG_UINT32 ui32NextOffset = 0; - IMG_BYTE *pArrayArgsBuffer = NULL; -#if !defined(INTEGRITY_OS) - IMG_BOOL bHaveEnoughSpace = IMG_FALSE; -#endif - - IMG_UINT32 ui32BufferSize = 0; - IMG_UINT64 ui64BufferSize = - ((IMG_UINT64) psPhysmemImportDmaBufLockedIN->ui32NameSize * sizeof(IMG_CHAR)) + 0; - - if (unlikely(psPhysmemImportDmaBufLockedIN->ui32NameSize > DEVMEM_ANNOTATION_MAX_LEN)) - { - psPhysmemImportDmaBufLockedOUT->eError = PVRSRV_ERROR_BRIDGE_ARRAY_SIZE_TOO_BIG; - goto PhysmemImportDmaBufLocked_exit; - } - - if (ui64BufferSize > IMG_UINT32_MAX) - { - psPhysmemImportDmaBufLockedOUT->eError = PVRSRV_ERROR_BRIDGE_BUFFER_TOO_SMALL; - goto PhysmemImportDmaBufLocked_exit; - } - - ui32BufferSize = (IMG_UINT32) ui64BufferSize; - - if (ui32BufferSize != 0) - { -#if !defined(INTEGRITY_OS) - /* Try to use remainder of input buffer for copies if possible, word-aligned for safety. */ - IMG_UINT32 ui32InBufferOffset = - PVR_ALIGN(sizeof(*psPhysmemImportDmaBufLockedIN), sizeof(unsigned long)); - IMG_UINT32 ui32InBufferExcessSize = - ui32InBufferOffset >= - PVRSRV_MAX_BRIDGE_IN_SIZE ? 0 : PVRSRV_MAX_BRIDGE_IN_SIZE - ui32InBufferOffset; - - bHaveEnoughSpace = ui32BufferSize <= ui32InBufferExcessSize; - if (bHaveEnoughSpace) - { - IMG_BYTE *pInputBuffer = (IMG_BYTE *) (void *)psPhysmemImportDmaBufLockedIN; - - pArrayArgsBuffer = &pInputBuffer[ui32InBufferOffset]; - } - else -#endif - { - pArrayArgsBuffer = OSAllocMemNoStats(ui32BufferSize); - - if (!pArrayArgsBuffer) - { - psPhysmemImportDmaBufLockedOUT->eError = PVRSRV_ERROR_OUT_OF_MEMORY; - goto PhysmemImportDmaBufLocked_exit; - } - } - } - - if (psPhysmemImportDmaBufLockedIN->ui32NameSize != 0) - { - uiNameInt = (IMG_CHAR *) IMG_OFFSET_ADDR(pArrayArgsBuffer, ui32NextOffset); - ui32NextOffset += psPhysmemImportDmaBufLockedIN->ui32NameSize * sizeof(IMG_CHAR); - } - - /* Copy the data over */ - if (psPhysmemImportDmaBufLockedIN->ui32NameSize * sizeof(IMG_CHAR) > 0) - { - if (OSCopyFromUser - (NULL, uiNameInt, (const void __user *)psPhysmemImportDmaBufLockedIN->puiName, - psPhysmemImportDmaBufLockedIN->ui32NameSize * sizeof(IMG_CHAR)) != PVRSRV_OK) - { - psPhysmemImportDmaBufLockedOUT->eError = PVRSRV_ERROR_INVALID_PARAMS; - - goto PhysmemImportDmaBufLocked_exit; - } - ((IMG_CHAR *) - uiNameInt)[(psPhysmemImportDmaBufLockedIN->ui32NameSize * sizeof(IMG_CHAR)) - 1] = - '\0'; - } - - psPhysmemImportDmaBufLockedOUT->eError = - PhysmemImportDmaBufLocked(psConnection, OSGetDevNode(psConnection), - psPhysmemImportDmaBufLockedIN->ifd, - psPhysmemImportDmaBufLockedIN->uiFlags, - psPhysmemImportDmaBufLockedIN->ui32NameSize, - uiNameInt, - &psPMRPtrInt, - &psPhysmemImportDmaBufLockedOUT->uiSize, - &psPhysmemImportDmaBufLockedOUT->uiAlign); - /* Exit early if bridged call fails */ - if (unlikely(psPhysmemImportDmaBufLockedOUT->eError != PVRSRV_OK)) - { - goto PhysmemImportDmaBufLocked_exit; - } - - /* Lock over handle creation. */ - LockHandle(psConnection->psHandleBase); - - psPhysmemImportDmaBufLockedOUT->eError = - PVRSRVAllocHandleUnlocked(psConnection->psHandleBase, - &psPhysmemImportDmaBufLockedOUT->hPMRPtr, (void *)psPMRPtrInt, - PVRSRV_HANDLE_TYPE_PHYSMEM_PMR, - PVRSRV_HANDLE_ALLOC_FLAG_MULTI, - (PFN_HANDLE_RELEASE) & - _PhysmemImportDmaBufLockedpsPMRPtrIntRelease); - if (unlikely(psPhysmemImportDmaBufLockedOUT->eError != PVRSRV_OK)) - { - UnlockHandle(psConnection->psHandleBase); - goto PhysmemImportDmaBufLocked_exit; - } - - /* Release now we have created handles. */ - UnlockHandle(psConnection->psHandleBase); - -PhysmemImportDmaBufLocked_exit: - - if (psPhysmemImportDmaBufLockedOUT->eError != PVRSRV_OK) - { - if (psPMRPtrInt) - { - LockHandle(KERNEL_HANDLE_BASE); - PMRUnrefUnlockPMR(psPMRPtrInt); - UnlockHandle(KERNEL_HANDLE_BASE); - } - } - - /* Allocated space should be equal to the last updated offset */ -#ifdef PVRSRV_NEED_PVR_ASSERT - if (psPhysmemImportDmaBufLockedOUT->eError == PVRSRV_OK) - PVR_ASSERT(ui32BufferSize == ui32NextOffset); -#endif /* PVRSRV_NEED_PVR_ASSERT */ - -#if defined(INTEGRITY_OS) - if (pArrayArgsBuffer) -#else - if (!bHaveEnoughSpace && pArrayArgsBuffer) -#endif - OSFreeMemNoStats(pArrayArgsBuffer); - - return 0; -} - /* *************************************************************************** * Server bridge dispatch related glue */ PVRSRV_ERROR InitDMABUFBridge(void); -PVRSRV_ERROR DeinitDMABUFBridge(void); +void DeinitDMABUFBridge(void); /* * Register all DMABUF functions with services @@ -663,33 +663,32 @@ PVRSRV_ERROR InitDMABUFBridge(void) SetDispatchTableEntry(PVRSRV_BRIDGE_DMABUF, PVRSRV_BRIDGE_DMABUF_PHYSMEMIMPORTDMABUF, PVRSRVBridgePhysmemImportDmaBuf, NULL); + SetDispatchTableEntry(PVRSRV_BRIDGE_DMABUF, PVRSRV_BRIDGE_DMABUF_PHYSMEMIMPORTDMABUFLOCKED, + PVRSRVBridgePhysmemImportDmaBufLocked, NULL); + SetDispatchTableEntry(PVRSRV_BRIDGE_DMABUF, PVRSRV_BRIDGE_DMABUF_PHYSMEMEXPORTDMABUF, PVRSRVBridgePhysmemExportDmaBuf, NULL); SetDispatchTableEntry(PVRSRV_BRIDGE_DMABUF, PVRSRV_BRIDGE_DMABUF_PHYSMEMIMPORTSPARSEDMABUF, PVRSRVBridgePhysmemImportSparseDmaBuf, NULL); - SetDispatchTableEntry(PVRSRV_BRIDGE_DMABUF, PVRSRV_BRIDGE_DMABUF_PHYSMEMIMPORTDMABUFLOCKED, - PVRSRVBridgePhysmemImportDmaBufLocked, NULL); - return PVRSRV_OK; } /* * Unregister all dmabuf functions with services */ -PVRSRV_ERROR DeinitDMABUFBridge(void) +void DeinitDMABUFBridge(void) { UnsetDispatchTableEntry(PVRSRV_BRIDGE_DMABUF, PVRSRV_BRIDGE_DMABUF_PHYSMEMIMPORTDMABUF); + UnsetDispatchTableEntry(PVRSRV_BRIDGE_DMABUF, + PVRSRV_BRIDGE_DMABUF_PHYSMEMIMPORTDMABUFLOCKED); + UnsetDispatchTableEntry(PVRSRV_BRIDGE_DMABUF, PVRSRV_BRIDGE_DMABUF_PHYSMEMEXPORTDMABUF); UnsetDispatchTableEntry(PVRSRV_BRIDGE_DMABUF, PVRSRV_BRIDGE_DMABUF_PHYSMEMIMPORTSPARSEDMABUF); - UnsetDispatchTableEntry(PVRSRV_BRIDGE_DMABUF, - PVRSRV_BRIDGE_DMABUF_PHYSMEMIMPORTDMABUFLOCKED); - - return PVRSRV_OK; } diff --git a/drivers/gpu/drm/img-rogue/server_htbuffer_bridge.c b/drivers/gpu/drm/img-rogue/server_htbuffer_bridge.c index 20b9491e0..dd81d914b 100644 --- a/drivers/gpu/drm/img-rogue/server_htbuffer_bridge.c +++ b/drivers/gpu/drm/img-rogue/server_htbuffer_bridge.c @@ -309,7 +309,7 @@ static POS_LOCK pHTBUFFERBridgeLock; #if !defined(EXCLUDE_HTBUFFER_BRIDGE) PVRSRV_ERROR InitHTBUFFERBridge(void); -PVRSRV_ERROR DeinitHTBUFFERBridge(void); +void DeinitHTBUFFERBridge(void); /* * Register all HTBUFFER functions with services @@ -330,15 +330,14 @@ PVRSRV_ERROR InitHTBUFFERBridge(void) /* * Unregister all htbuffer functions with services */ -PVRSRV_ERROR DeinitHTBUFFERBridge(void) +void DeinitHTBUFFERBridge(void) { - PVR_LOG_RETURN_IF_ERROR(OSLockDestroy(pHTBUFFERBridgeLock), "OSLockDestroy"); + OSLockDestroy(pHTBUFFERBridgeLock); UnsetDispatchTableEntry(PVRSRV_BRIDGE_HTBUFFER, PVRSRV_BRIDGE_HTBUFFER_HTBCONTROL); UnsetDispatchTableEntry(PVRSRV_BRIDGE_HTBUFFER, PVRSRV_BRIDGE_HTBUFFER_HTBLOG); - return PVRSRV_OK; } #else /* EXCLUDE_HTBUFFER_BRIDGE */ /* This bridge is conditional on EXCLUDE_HTBUFFER_BRIDGE - when defined, @@ -347,7 +346,6 @@ PVRSRV_ERROR DeinitHTBUFFERBridge(void) #define InitHTBUFFERBridge() \ PVRSRV_OK -#define DeinitHTBUFFERBridge() \ - PVRSRV_OK +#define DeinitHTBUFFERBridge() #endif /* EXCLUDE_HTBUFFER_BRIDGE */ diff --git a/drivers/gpu/drm/img-rogue/server_mm_bridge.c b/drivers/gpu/drm/img-rogue/server_mm_bridge.c index 26868095f..7375eb61f 100644 --- a/drivers/gpu/drm/img-rogue/server_mm_bridge.c +++ b/drivers/gpu/drm/img-rogue/server_mm_bridge.c @@ -201,7 +201,7 @@ PMRExportPMR_exit: /* Lock over handle creation cleanup. */ LockHandle(KERNEL_HANDLE_BASE); - eError = PVRSRVReleaseHandleUnlocked(KERNEL_HANDLE_BASE, + eError = PVRSRVDestroyHandleUnlocked(KERNEL_HANDLE_BASE, (IMG_HANDLE) psPMRExportPMROUT-> hPMRExport, PVRSRV_HANDLE_TYPE_PHYSMEM_PMR_EXPORT); @@ -226,7 +226,7 @@ PMRExportPMR_exit: LockHandle(psConnection->psProcessHandleBase->psHandleBase); eError = - PVRSRVReleaseHandleUnlocked(psConnection->psProcessHandleBase-> + PVRSRVDestroyHandleUnlocked(psConnection->psProcessHandleBase-> psHandleBase, hPMRExportInt, PVRSRV_HANDLE_TYPE_PHYSMEM_PMR_EXPORT); if ((eError != PVRSRV_OK) && (eError != PVRSRV_ERROR_RETRY)) @@ -307,9 +307,10 @@ PVRSRVBridgePMRUnexportPMR(IMG_UINT32 ui32DispatchTableEntry, PVR_ASSERT(psPMRUnexportPMROUT->eError == PVRSRV_OK); psPMRUnexportPMROUT->eError = - PVRSRVReleaseHandleStagedUnlock(psConnection->psProcessHandleBase->psHandleBase, - hPMRExportInt, PVRSRV_HANDLE_TYPE_PHYSMEM_PMR_EXPORT); + PVRSRVDestroyHandleStagedUnlocked(psConnection->psProcessHandleBase->psHandleBase, + hPMRExportInt, PVRSRV_HANDLE_TYPE_PHYSMEM_PMR_EXPORT); if (unlikely((psPMRUnexportPMROUT->eError != PVRSRV_OK) && + (psPMRUnexportPMROUT->eError != PVRSRV_ERROR_KERNEL_CCB_FULL) && (psPMRUnexportPMROUT->eError != PVRSRV_ERROR_RETRY))) { PVR_DPF((PVR_DBG_ERROR, @@ -324,10 +325,11 @@ PVRSRVBridgePMRUnexportPMR(IMG_UINT32 ui32DispatchTableEntry, LockHandle(KERNEL_HANDLE_BASE); psPMRUnexportPMROUT->eError = - PVRSRVReleaseHandleStagedUnlock(KERNEL_HANDLE_BASE, - (IMG_HANDLE) psPMRUnexportPMRIN->hPMRExport, - PVRSRV_HANDLE_TYPE_PHYSMEM_PMR_EXPORT); + PVRSRVDestroyHandleStagedUnlocked(KERNEL_HANDLE_BASE, + (IMG_HANDLE) psPMRUnexportPMRIN->hPMRExport, + PVRSRV_HANDLE_TYPE_PHYSMEM_PMR_EXPORT); if (unlikely((psPMRUnexportPMROUT->eError != PVRSRV_OK) && + (psPMRUnexportPMROUT->eError != PVRSRV_ERROR_KERNEL_CCB_FULL) && (psPMRUnexportPMROUT->eError != PVRSRV_ERROR_RETRY))) { PVR_DPF((PVR_DBG_ERROR, @@ -503,10 +505,11 @@ PVRSRVBridgePMRUnmakeLocalImportHandle(IMG_UINT32 ui32DispatchTableEntry, LockHandle(psConnection->psProcessHandleBase->psHandleBase); psPMRUnmakeLocalImportHandleOUT->eError = - PVRSRVReleaseHandleStagedUnlock(psConnection->psProcessHandleBase->psHandleBase, - (IMG_HANDLE) psPMRUnmakeLocalImportHandleIN->hExtMem, - PVRSRV_HANDLE_TYPE_DEVMEM_MEM_IMPORT); + PVRSRVDestroyHandleStagedUnlocked(psConnection->psProcessHandleBase->psHandleBase, + (IMG_HANDLE) psPMRUnmakeLocalImportHandleIN->hExtMem, + PVRSRV_HANDLE_TYPE_DEVMEM_MEM_IMPORT); if (unlikely((psPMRUnmakeLocalImportHandleOUT->eError != PVRSRV_OK) && + (psPMRUnmakeLocalImportHandleOUT->eError != PVRSRV_ERROR_KERNEL_CCB_FULL) && (psPMRUnmakeLocalImportHandleOUT->eError != PVRSRV_ERROR_RETRY))) { PVR_DPF((PVR_DBG_ERROR, @@ -727,10 +730,11 @@ PVRSRVBridgePMRUnrefPMR(IMG_UINT32 ui32DispatchTableEntry, LockHandle(psConnection->psHandleBase); psPMRUnrefPMROUT->eError = - PVRSRVReleaseHandleStagedUnlock(psConnection->psHandleBase, - (IMG_HANDLE) psPMRUnrefPMRIN->hPMR, - PVRSRV_HANDLE_TYPE_PHYSMEM_PMR); + PVRSRVDestroyHandleStagedUnlocked(psConnection->psHandleBase, + (IMG_HANDLE) psPMRUnrefPMRIN->hPMR, + PVRSRV_HANDLE_TYPE_PHYSMEM_PMR); if (unlikely((psPMRUnrefPMROUT->eError != PVRSRV_OK) && + (psPMRUnrefPMROUT->eError != PVRSRV_ERROR_KERNEL_CCB_FULL) && (psPMRUnrefPMROUT->eError != PVRSRV_ERROR_RETRY))) { PVR_DPF((PVR_DBG_ERROR, @@ -762,10 +766,11 @@ PVRSRVBridgePMRUnrefUnlockPMR(IMG_UINT32 ui32DispatchTableEntry, LockHandle(psConnection->psHandleBase); psPMRUnrefUnlockPMROUT->eError = - PVRSRVReleaseHandleStagedUnlock(psConnection->psHandleBase, - (IMG_HANDLE) psPMRUnrefUnlockPMRIN->hPMR, - PVRSRV_HANDLE_TYPE_PHYSMEM_PMR); + PVRSRVDestroyHandleStagedUnlocked(psConnection->psHandleBase, + (IMG_HANDLE) psPMRUnrefUnlockPMRIN->hPMR, + PVRSRV_HANDLE_TYPE_PHYSMEM_PMR); if (unlikely((psPMRUnrefUnlockPMROUT->eError != PVRSRV_OK) && + (psPMRUnrefUnlockPMROUT->eError != PVRSRV_ERROR_KERNEL_CCB_FULL) && (psPMRUnrefUnlockPMROUT->eError != PVRSRV_ERROR_RETRY))) { PVR_DPF((PVR_DBG_ERROR, @@ -1518,7 +1523,7 @@ DevmemIntCtxCreate_exit: /* Lock over handle creation cleanup. */ LockHandle(psConnection->psHandleBase); - eError = PVRSRVReleaseHandleUnlocked(psConnection->psHandleBase, + eError = PVRSRVDestroyHandleUnlocked(psConnection->psHandleBase, (IMG_HANDLE) psDevmemIntCtxCreateOUT-> hDevMemServerContext, PVRSRV_HANDLE_TYPE_DEVMEMINT_CTX); @@ -1564,11 +1569,13 @@ PVRSRVBridgeDevmemIntCtxDestroy(IMG_UINT32 ui32DispatchTableEntry, LockHandle(psConnection->psHandleBase); psDevmemIntCtxDestroyOUT->eError = - PVRSRVReleaseHandleStagedUnlock(psConnection->psHandleBase, - (IMG_HANDLE) psDevmemIntCtxDestroyIN-> - hDevmemServerContext, PVRSRV_HANDLE_TYPE_DEVMEMINT_CTX); + PVRSRVDestroyHandleStagedUnlocked(psConnection->psHandleBase, + (IMG_HANDLE) psDevmemIntCtxDestroyIN-> + hDevmemServerContext, + PVRSRV_HANDLE_TYPE_DEVMEMINT_CTX); if (unlikely ((psDevmemIntCtxDestroyOUT->eError != PVRSRV_OK) + && (psDevmemIntCtxDestroyOUT->eError != PVRSRV_ERROR_KERNEL_CCB_FULL) && (psDevmemIntCtxDestroyOUT->eError != PVRSRV_ERROR_RETRY))) { PVR_DPF((PVR_DBG_ERROR, @@ -1699,10 +1706,11 @@ PVRSRVBridgeDevmemIntHeapDestroy(IMG_UINT32 ui32DispatchTableEntry, LockHandle(psConnection->psHandleBase); psDevmemIntHeapDestroyOUT->eError = - PVRSRVReleaseHandleStagedUnlock(psConnection->psHandleBase, - (IMG_HANDLE) psDevmemIntHeapDestroyIN->hDevmemHeap, - PVRSRV_HANDLE_TYPE_DEVMEMINT_HEAP); + PVRSRVDestroyHandleStagedUnlocked(psConnection->psHandleBase, + (IMG_HANDLE) psDevmemIntHeapDestroyIN->hDevmemHeap, + PVRSRV_HANDLE_TYPE_DEVMEMINT_HEAP); if (unlikely((psDevmemIntHeapDestroyOUT->eError != PVRSRV_OK) && + (psDevmemIntHeapDestroyOUT->eError != PVRSRV_ERROR_KERNEL_CCB_FULL) && (psDevmemIntHeapDestroyOUT->eError != PVRSRV_ERROR_RETRY))) { PVR_DPF((PVR_DBG_ERROR, @@ -1868,10 +1876,11 @@ PVRSRVBridgeDevmemIntUnmapPMR(IMG_UINT32 ui32DispatchTableEntry, LockHandle(psConnection->psHandleBase); psDevmemIntUnmapPMROUT->eError = - PVRSRVReleaseHandleStagedUnlock(psConnection->psHandleBase, - (IMG_HANDLE) psDevmemIntUnmapPMRIN->hMapping, - PVRSRV_HANDLE_TYPE_DEVMEMINT_MAPPING); + PVRSRVDestroyHandleStagedUnlocked(psConnection->psHandleBase, + (IMG_HANDLE) psDevmemIntUnmapPMRIN->hMapping, + PVRSRV_HANDLE_TYPE_DEVMEMINT_MAPPING); if (unlikely((psDevmemIntUnmapPMROUT->eError != PVRSRV_OK) && + (psDevmemIntUnmapPMROUT->eError != PVRSRV_ERROR_KERNEL_CCB_FULL) && (psDevmemIntUnmapPMROUT->eError != PVRSRV_ERROR_RETRY))) { PVR_DPF((PVR_DBG_ERROR, @@ -2001,11 +2010,14 @@ PVRSRVBridgeDevmemIntUnreserveRange(IMG_UINT32 ui32DispatchTableEntry, LockHandle(psConnection->psHandleBase); psDevmemIntUnreserveRangeOUT->eError = - PVRSRVReleaseHandleStagedUnlock(psConnection->psHandleBase, - (IMG_HANDLE) psDevmemIntUnreserveRangeIN->hReservation, - PVRSRV_HANDLE_TYPE_DEVMEMINT_RESERVATION); - if (unlikely((psDevmemIntUnreserveRangeOUT->eError != PVRSRV_OK) && - (psDevmemIntUnreserveRangeOUT->eError != PVRSRV_ERROR_RETRY))) + PVRSRVDestroyHandleStagedUnlocked(psConnection->psHandleBase, + (IMG_HANDLE) psDevmemIntUnreserveRangeIN-> + hReservation, + PVRSRV_HANDLE_TYPE_DEVMEMINT_RESERVATION); + if (unlikely + ((psDevmemIntUnreserveRangeOUT->eError != PVRSRV_OK) + && (psDevmemIntUnreserveRangeOUT->eError != PVRSRV_ERROR_KERNEL_CCB_FULL) + && (psDevmemIntUnreserveRangeOUT->eError != PVRSRV_ERROR_RETRY))) { PVR_DPF((PVR_DBG_ERROR, "%s: %s", @@ -3276,12 +3288,291 @@ PVRSRVBridgePVRSRVUpdateOOMStats(IMG_UINT32 ui32DispatchTableEntry, #define PVRSRVBridgePVRSRVUpdateOOMStats NULL #endif +static_assert(PVRSRV_PHYS_HEAP_LAST <= IMG_UINT32_MAX, + "PVRSRV_PHYS_HEAP_LAST must not be larger than IMG_UINT32_MAX"); + +static IMG_INT +PVRSRVBridgePhysHeapGetMemInfoPkd(IMG_UINT32 ui32DispatchTableEntry, + IMG_UINT8 * psPhysHeapGetMemInfoPkdIN_UI8, + IMG_UINT8 * psPhysHeapGetMemInfoPkdOUT_UI8, + CONNECTION_DATA * psConnection) +{ + PVRSRV_BRIDGE_IN_PHYSHEAPGETMEMINFOPKD *psPhysHeapGetMemInfoPkdIN = + (PVRSRV_BRIDGE_IN_PHYSHEAPGETMEMINFOPKD *) + IMG_OFFSET_ADDR(psPhysHeapGetMemInfoPkdIN_UI8, 0); + PVRSRV_BRIDGE_OUT_PHYSHEAPGETMEMINFOPKD *psPhysHeapGetMemInfoPkdOUT = + (PVRSRV_BRIDGE_OUT_PHYSHEAPGETMEMINFOPKD *) + IMG_OFFSET_ADDR(psPhysHeapGetMemInfoPkdOUT_UI8, 0); + + PVRSRV_PHYS_HEAP *eaPhysHeapIDInt = NULL; + PHYS_HEAP_MEM_STATS_PKD *psapPhysHeapMemStatsInt = NULL; + + IMG_UINT32 ui32NextOffset = 0; + IMG_BYTE *pArrayArgsBuffer = NULL; +#if !defined(INTEGRITY_OS) + IMG_BOOL bHaveEnoughSpace = IMG_FALSE; +#endif + + IMG_UINT32 ui32BufferSize = 0; + IMG_UINT64 ui64BufferSize = + ((IMG_UINT64) psPhysHeapGetMemInfoPkdIN->ui32PhysHeapCount * sizeof(PVRSRV_PHYS_HEAP)) + + ((IMG_UINT64) psPhysHeapGetMemInfoPkdIN->ui32PhysHeapCount * + sizeof(PHYS_HEAP_MEM_STATS_PKD)) + 0; + + if (unlikely(psPhysHeapGetMemInfoPkdIN->ui32PhysHeapCount > PVRSRV_PHYS_HEAP_LAST)) + { + psPhysHeapGetMemInfoPkdOUT->eError = PVRSRV_ERROR_BRIDGE_ARRAY_SIZE_TOO_BIG; + goto PhysHeapGetMemInfoPkd_exit; + } + + psPhysHeapGetMemInfoPkdOUT->psapPhysHeapMemStats = + psPhysHeapGetMemInfoPkdIN->psapPhysHeapMemStats; + + if (ui64BufferSize > IMG_UINT32_MAX) + { + psPhysHeapGetMemInfoPkdOUT->eError = PVRSRV_ERROR_BRIDGE_BUFFER_TOO_SMALL; + goto PhysHeapGetMemInfoPkd_exit; + } + + ui32BufferSize = (IMG_UINT32) ui64BufferSize; + + if (ui32BufferSize != 0) + { +#if !defined(INTEGRITY_OS) + /* Try to use remainder of input buffer for copies if possible, word-aligned for safety. */ + IMG_UINT32 ui32InBufferOffset = + PVR_ALIGN(sizeof(*psPhysHeapGetMemInfoPkdIN), sizeof(unsigned long)); + IMG_UINT32 ui32InBufferExcessSize = + ui32InBufferOffset >= + PVRSRV_MAX_BRIDGE_IN_SIZE ? 0 : PVRSRV_MAX_BRIDGE_IN_SIZE - ui32InBufferOffset; + + bHaveEnoughSpace = ui32BufferSize <= ui32InBufferExcessSize; + if (bHaveEnoughSpace) + { + IMG_BYTE *pInputBuffer = (IMG_BYTE *) (void *)psPhysHeapGetMemInfoPkdIN; + + pArrayArgsBuffer = &pInputBuffer[ui32InBufferOffset]; + } + else +#endif + { + pArrayArgsBuffer = OSAllocMemNoStats(ui32BufferSize); + + if (!pArrayArgsBuffer) + { + psPhysHeapGetMemInfoPkdOUT->eError = PVRSRV_ERROR_OUT_OF_MEMORY; + goto PhysHeapGetMemInfoPkd_exit; + } + } + } + + if (psPhysHeapGetMemInfoPkdIN->ui32PhysHeapCount != 0) + { + eaPhysHeapIDInt = + (PVRSRV_PHYS_HEAP *) IMG_OFFSET_ADDR(pArrayArgsBuffer, ui32NextOffset); + ui32NextOffset += + psPhysHeapGetMemInfoPkdIN->ui32PhysHeapCount * sizeof(PVRSRV_PHYS_HEAP); + } + + /* Copy the data over */ + if (psPhysHeapGetMemInfoPkdIN->ui32PhysHeapCount * sizeof(PVRSRV_PHYS_HEAP) > 0) + { + if (OSCopyFromUser + (NULL, eaPhysHeapIDInt, + (const void __user *)psPhysHeapGetMemInfoPkdIN->peaPhysHeapID, + psPhysHeapGetMemInfoPkdIN->ui32PhysHeapCount * sizeof(PVRSRV_PHYS_HEAP)) != + PVRSRV_OK) + { + psPhysHeapGetMemInfoPkdOUT->eError = PVRSRV_ERROR_INVALID_PARAMS; + + goto PhysHeapGetMemInfoPkd_exit; + } + } + if (psPhysHeapGetMemInfoPkdIN->ui32PhysHeapCount != 0) + { + psapPhysHeapMemStatsInt = + (PHYS_HEAP_MEM_STATS_PKD *) IMG_OFFSET_ADDR(pArrayArgsBuffer, ui32NextOffset); + ui32NextOffset += + psPhysHeapGetMemInfoPkdIN->ui32PhysHeapCount * sizeof(PHYS_HEAP_MEM_STATS_PKD); + } + + psPhysHeapGetMemInfoPkdOUT->eError = + PVRSRVPhysHeapGetMemInfoPkdKM(psConnection, OSGetDevNode(psConnection), + psPhysHeapGetMemInfoPkdIN->ui32PhysHeapCount, + eaPhysHeapIDInt, psapPhysHeapMemStatsInt); + /* Exit early if bridged call fails */ + if (unlikely(psPhysHeapGetMemInfoPkdOUT->eError != PVRSRV_OK)) + { + goto PhysHeapGetMemInfoPkd_exit; + } + + /* If dest ptr is non-null and we have data to copy */ + if ((psapPhysHeapMemStatsInt) && + ((psPhysHeapGetMemInfoPkdIN->ui32PhysHeapCount * sizeof(PHYS_HEAP_MEM_STATS_PKD)) > 0)) + { + if (unlikely + (OSCopyToUser + (NULL, (void __user *)psPhysHeapGetMemInfoPkdOUT->psapPhysHeapMemStats, + psapPhysHeapMemStatsInt, + (psPhysHeapGetMemInfoPkdIN->ui32PhysHeapCount * + sizeof(PHYS_HEAP_MEM_STATS_PKD))) != PVRSRV_OK)) + { + psPhysHeapGetMemInfoPkdOUT->eError = PVRSRV_ERROR_INVALID_PARAMS; + + goto PhysHeapGetMemInfoPkd_exit; + } + } + +PhysHeapGetMemInfoPkd_exit: + + /* Allocated space should be equal to the last updated offset */ +#ifdef PVRSRV_NEED_PVR_ASSERT + if (psPhysHeapGetMemInfoPkdOUT->eError == PVRSRV_OK) + PVR_ASSERT(ui32BufferSize == ui32NextOffset); +#endif /* PVRSRV_NEED_PVR_ASSERT */ + +#if defined(INTEGRITY_OS) + if (pArrayArgsBuffer) +#else + if (!bHaveEnoughSpace && pArrayArgsBuffer) +#endif + OSFreeMemNoStats(pArrayArgsBuffer); + + return 0; +} + +static IMG_INT +PVRSRVBridgeGetHeapPhysMemUsagePkd(IMG_UINT32 ui32DispatchTableEntry, + IMG_UINT8 * psGetHeapPhysMemUsagePkdIN_UI8, + IMG_UINT8 * psGetHeapPhysMemUsagePkdOUT_UI8, + CONNECTION_DATA * psConnection) +{ + PVRSRV_BRIDGE_IN_GETHEAPPHYSMEMUSAGEPKD *psGetHeapPhysMemUsagePkdIN = + (PVRSRV_BRIDGE_IN_GETHEAPPHYSMEMUSAGEPKD *) + IMG_OFFSET_ADDR(psGetHeapPhysMemUsagePkdIN_UI8, 0); + PVRSRV_BRIDGE_OUT_GETHEAPPHYSMEMUSAGEPKD *psGetHeapPhysMemUsagePkdOUT = + (PVRSRV_BRIDGE_OUT_GETHEAPPHYSMEMUSAGEPKD *) + IMG_OFFSET_ADDR(psGetHeapPhysMemUsagePkdOUT_UI8, 0); + + PHYS_HEAP_MEM_STATS_PKD *psapPhysHeapMemStatsInt = NULL; + + IMG_UINT32 ui32NextOffset = 0; + IMG_BYTE *pArrayArgsBuffer = NULL; +#if !defined(INTEGRITY_OS) + IMG_BOOL bHaveEnoughSpace = IMG_FALSE; +#endif + + IMG_UINT32 ui32BufferSize = 0; + IMG_UINT64 ui64BufferSize = + ((IMG_UINT64) psGetHeapPhysMemUsagePkdIN->ui32PhysHeapCount * + sizeof(PHYS_HEAP_MEM_STATS_PKD)) + 0; + + if (psGetHeapPhysMemUsagePkdIN->ui32PhysHeapCount > PVRSRV_PHYS_HEAP_LAST) + { + psGetHeapPhysMemUsagePkdOUT->eError = PVRSRV_ERROR_BRIDGE_ARRAY_SIZE_TOO_BIG; + goto GetHeapPhysMemUsagePkd_exit; + } + + psGetHeapPhysMemUsagePkdOUT->psapPhysHeapMemStats = + psGetHeapPhysMemUsagePkdIN->psapPhysHeapMemStats; + + if (ui64BufferSize > IMG_UINT32_MAX) + { + psGetHeapPhysMemUsagePkdOUT->eError = PVRSRV_ERROR_BRIDGE_BUFFER_TOO_SMALL; + goto GetHeapPhysMemUsagePkd_exit; + } + + ui32BufferSize = (IMG_UINT32) ui64BufferSize; + + if (ui32BufferSize != 0) + { +#if !defined(INTEGRITY_OS) + /* Try to use remainder of input buffer for copies if possible, word-aligned for safety. */ + IMG_UINT32 ui32InBufferOffset = + PVR_ALIGN(sizeof(*psGetHeapPhysMemUsagePkdIN), sizeof(unsigned long)); + IMG_UINT32 ui32InBufferExcessSize = + ui32InBufferOffset >= + PVRSRV_MAX_BRIDGE_IN_SIZE ? 0 : PVRSRV_MAX_BRIDGE_IN_SIZE - ui32InBufferOffset; + + bHaveEnoughSpace = ui32BufferSize <= ui32InBufferExcessSize; + if (bHaveEnoughSpace) + { + IMG_BYTE *pInputBuffer = (IMG_BYTE *) (void *)psGetHeapPhysMemUsagePkdIN; + + pArrayArgsBuffer = &pInputBuffer[ui32InBufferOffset]; + } + else +#endif + { + pArrayArgsBuffer = OSAllocMemNoStats(ui32BufferSize); + + if (!pArrayArgsBuffer) + { + psGetHeapPhysMemUsagePkdOUT->eError = PVRSRV_ERROR_OUT_OF_MEMORY; + goto GetHeapPhysMemUsagePkd_exit; + } + } + } + + if (psGetHeapPhysMemUsagePkdIN->ui32PhysHeapCount != 0) + { + psapPhysHeapMemStatsInt = + (PHYS_HEAP_MEM_STATS_PKD *) IMG_OFFSET_ADDR(pArrayArgsBuffer, ui32NextOffset); + ui32NextOffset += + psGetHeapPhysMemUsagePkdIN->ui32PhysHeapCount * sizeof(PHYS_HEAP_MEM_STATS_PKD); + } + + psGetHeapPhysMemUsagePkdOUT->eError = + PVRSRVGetHeapPhysMemUsagePkdKM(psConnection, OSGetDevNode(psConnection), + psGetHeapPhysMemUsagePkdIN->ui32PhysHeapCount, + psapPhysHeapMemStatsInt); + /* Exit early if bridged call fails */ + if (unlikely(psGetHeapPhysMemUsagePkdOUT->eError != PVRSRV_OK)) + { + goto GetHeapPhysMemUsagePkd_exit; + } + + /* If dest ptr is non-null and we have data to copy */ + if ((psapPhysHeapMemStatsInt) && + ((psGetHeapPhysMemUsagePkdIN->ui32PhysHeapCount * sizeof(PHYS_HEAP_MEM_STATS_PKD)) > 0)) + { + if (unlikely + (OSCopyToUser + (NULL, (void __user *)psGetHeapPhysMemUsagePkdOUT->psapPhysHeapMemStats, + psapPhysHeapMemStatsInt, + (psGetHeapPhysMemUsagePkdIN->ui32PhysHeapCount * + sizeof(PHYS_HEAP_MEM_STATS_PKD))) != PVRSRV_OK)) + { + psGetHeapPhysMemUsagePkdOUT->eError = PVRSRV_ERROR_INVALID_PARAMS; + + goto GetHeapPhysMemUsagePkd_exit; + } + } + +GetHeapPhysMemUsagePkd_exit: + + /* Allocated space should be equal to the last updated offset */ +#ifdef PVRSRV_NEED_PVR_ASSERT + if (psGetHeapPhysMemUsagePkdOUT->eError == PVRSRV_OK) + PVR_ASSERT(ui32BufferSize == ui32NextOffset); +#endif /* PVRSRV_NEED_PVR_ASSERT */ + +#if defined(INTEGRITY_OS) + if (pArrayArgsBuffer) +#else + if (!bHaveEnoughSpace && pArrayArgsBuffer) +#endif + OSFreeMemNoStats(pArrayArgsBuffer); + + return 0; +} + /* *************************************************************************** * Server bridge dispatch related glue */ PVRSRV_ERROR InitMMBridge(void); -PVRSRV_ERROR DeinitMMBridge(void); +void DeinitMMBridge(void); /* * Register all MM functions with services @@ -3409,13 +3700,19 @@ PVRSRV_ERROR InitMMBridge(void) SetDispatchTableEntry(PVRSRV_BRIDGE_MM, PVRSRV_BRIDGE_MM_PVRSRVUPDATEOOMSTATS, PVRSRVBridgePVRSRVUpdateOOMStats, NULL); + SetDispatchTableEntry(PVRSRV_BRIDGE_MM, PVRSRV_BRIDGE_MM_PHYSHEAPGETMEMINFOPKD, + PVRSRVBridgePhysHeapGetMemInfoPkd, NULL); + + SetDispatchTableEntry(PVRSRV_BRIDGE_MM, PVRSRV_BRIDGE_MM_GETHEAPPHYSMEMUSAGEPKD, + PVRSRVBridgeGetHeapPhysMemUsagePkd, NULL); + return PVRSRV_OK; } /* * Unregister all mm functions with services */ -PVRSRV_ERROR DeinitMMBridge(void) +void DeinitMMBridge(void) { UnsetDispatchTableEntry(PVRSRV_BRIDGE_MM, PVRSRV_BRIDGE_MM_PMREXPORTPMR); @@ -3498,5 +3795,8 @@ PVRSRV_ERROR DeinitMMBridge(void) UnsetDispatchTableEntry(PVRSRV_BRIDGE_MM, PVRSRV_BRIDGE_MM_PVRSRVUPDATEOOMSTATS); - return PVRSRV_OK; + UnsetDispatchTableEntry(PVRSRV_BRIDGE_MM, PVRSRV_BRIDGE_MM_PHYSHEAPGETMEMINFOPKD); + + UnsetDispatchTableEntry(PVRSRV_BRIDGE_MM, PVRSRV_BRIDGE_MM_GETHEAPPHYSMEMUSAGEPKD); + } diff --git a/drivers/gpu/drm/img-rogue/server_pvrtl_bridge.c b/drivers/gpu/drm/img-rogue/server_pvrtl_bridge.c index 02c937d3f..e25137ca7 100644 --- a/drivers/gpu/drm/img-rogue/server_pvrtl_bridge.c +++ b/drivers/gpu/drm/img-rogue/server_pvrtl_bridge.c @@ -209,7 +209,7 @@ TLOpenStream_exit: /* Lock over handle creation cleanup. */ LockHandle(psConnection->psHandleBase); - eError = PVRSRVReleaseHandleUnlocked(psConnection->psHandleBase, + eError = PVRSRVDestroyHandleUnlocked(psConnection->psHandleBase, (IMG_HANDLE) psTLOpenStreamOUT->hSD, PVRSRV_HANDLE_TYPE_PVR_TL_SD); if (unlikely((eError != PVRSRV_OK) && (eError != PVRSRV_ERROR_RETRY))) @@ -264,10 +264,11 @@ PVRSRVBridgeTLCloseStream(IMG_UINT32 ui32DispatchTableEntry, LockHandle(psConnection->psHandleBase); psTLCloseStreamOUT->eError = - PVRSRVReleaseHandleStagedUnlock(psConnection->psHandleBase, - (IMG_HANDLE) psTLCloseStreamIN->hSD, - PVRSRV_HANDLE_TYPE_PVR_TL_SD); + PVRSRVDestroyHandleStagedUnlocked(psConnection->psHandleBase, + (IMG_HANDLE) psTLCloseStreamIN->hSD, + PVRSRV_HANDLE_TYPE_PVR_TL_SD); if (unlikely((psTLCloseStreamOUT->eError != PVRSRV_OK) && + (psTLCloseStreamOUT->eError != PVRSRV_ERROR_KERNEL_CCB_FULL) && (psTLCloseStreamOUT->eError != PVRSRV_ERROR_RETRY))) { PVR_DPF((PVR_DBG_ERROR, @@ -775,7 +776,7 @@ TLWriteData_exit: */ PVRSRV_ERROR InitPVRTLBridge(void); -PVRSRV_ERROR DeinitPVRTLBridge(void); +void DeinitPVRTLBridge(void); /* * Register all PVRTL functions with services @@ -813,7 +814,7 @@ PVRSRV_ERROR InitPVRTLBridge(void) /* * Unregister all pvrtl functions with services */ -PVRSRV_ERROR DeinitPVRTLBridge(void) +void DeinitPVRTLBridge(void) { UnsetDispatchTableEntry(PVRSRV_BRIDGE_PVRTL, PVRSRV_BRIDGE_PVRTL_TLOPENSTREAM); @@ -832,5 +833,4 @@ PVRSRV_ERROR DeinitPVRTLBridge(void) UnsetDispatchTableEntry(PVRSRV_BRIDGE_PVRTL, PVRSRV_BRIDGE_PVRTL_TLWRITEDATA); - return PVRSRV_OK; } diff --git a/drivers/gpu/drm/img-rogue/server_rgxbreakpoint_bridge.c b/drivers/gpu/drm/img-rogue/server_rgxbreakpoint_bridge.c index 29a1bcd4c..bb7d01204 100644 --- a/drivers/gpu/drm/img-rogue/server_rgxbreakpoint_bridge.c +++ b/drivers/gpu/drm/img-rogue/server_rgxbreakpoint_bridge.c @@ -305,7 +305,7 @@ PVRSRVBridgeRGXOverallocateBPRegisters(IMG_UINT32 ui32DispatchTableEntry, #if !defined(EXCLUDE_RGXBREAKPOINT_BRIDGE) PVRSRV_ERROR InitRGXBREAKPOINTBridge(void); -PVRSRV_ERROR DeinitRGXBREAKPOINTBridge(void); +void DeinitRGXBREAKPOINTBridge(void); /* * Register all RGXBREAKPOINT functions with services @@ -339,7 +339,7 @@ PVRSRV_ERROR InitRGXBREAKPOINTBridge(void) /* * Unregister all rgxbreakpoint functions with services */ -PVRSRV_ERROR DeinitRGXBREAKPOINTBridge(void) +void DeinitRGXBREAKPOINTBridge(void) { UnsetDispatchTableEntry(PVRSRV_BRIDGE_RGXBREAKPOINT, @@ -357,7 +357,6 @@ PVRSRV_ERROR DeinitRGXBREAKPOINTBridge(void) UnsetDispatchTableEntry(PVRSRV_BRIDGE_RGXBREAKPOINT, PVRSRV_BRIDGE_RGXBREAKPOINT_RGXOVERALLOCATEBPREGISTERS); - return PVRSRV_OK; } #else /* EXCLUDE_RGXBREAKPOINT_BRIDGE */ /* This bridge is conditional on EXCLUDE_RGXBREAKPOINT_BRIDGE - when defined, @@ -366,7 +365,6 @@ PVRSRV_ERROR DeinitRGXBREAKPOINTBridge(void) #define InitRGXBREAKPOINTBridge() \ PVRSRV_OK -#define DeinitRGXBREAKPOINTBridge() \ - PVRSRV_OK +#define DeinitRGXBREAKPOINTBridge() #endif /* EXCLUDE_RGXBREAKPOINT_BRIDGE */ diff --git a/drivers/gpu/drm/img-rogue/server_rgxcmp_bridge.c b/drivers/gpu/drm/img-rogue/server_rgxcmp_bridge.c index eefd2b3a5..9b97e78e1 100644 --- a/drivers/gpu/drm/img-rogue/server_rgxcmp_bridge.c +++ b/drivers/gpu/drm/img-rogue/server_rgxcmp_bridge.c @@ -348,12 +348,13 @@ PVRSRVBridgeRGXDestroyComputeContext(IMG_UINT32 ui32DispatchTableEntry, LockHandle(psConnection->psHandleBase); psRGXDestroyComputeContextOUT->eError = - PVRSRVReleaseHandleStagedUnlock(psConnection->psHandleBase, - (IMG_HANDLE) psRGXDestroyComputeContextIN-> - hComputeContext, - PVRSRV_HANDLE_TYPE_RGX_SERVER_COMPUTE_CONTEXT); + PVRSRVDestroyHandleStagedUnlocked(psConnection->psHandleBase, + (IMG_HANDLE) psRGXDestroyComputeContextIN-> + hComputeContext, + PVRSRV_HANDLE_TYPE_RGX_SERVER_COMPUTE_CONTEXT); if (unlikely ((psRGXDestroyComputeContextOUT->eError != PVRSRV_OK) + && (psRGXDestroyComputeContextOUT->eError != PVRSRV_ERROR_KERNEL_CCB_FULL) && (psRGXDestroyComputeContextOUT->eError != PVRSRV_ERROR_RETRY))) { PVR_DPF((PVR_DBG_ERROR, @@ -905,7 +906,6 @@ PVRSRVBridgeRGXKickCDM2(IMG_UINT32 ui32DispatchTableEntry, psRGXKickCDM2OUT->eError = PVRSRVRGXKickCDMKM(psComputeContextInt, - psRGXKickCDM2IN->ui32ClientCacheOpSeqNum, psRGXKickCDM2IN->ui32ClientUpdateCount, psClientUpdateUFOSyncPrimBlockInt, ui32ClientUpdateOffsetInt, @@ -1104,7 +1104,7 @@ RGXGetLastDeviceError_exit: */ PVRSRV_ERROR InitRGXCMPBridge(void); -PVRSRV_ERROR DeinitRGXCMPBridge(void); +void DeinitRGXCMPBridge(void); /* * Register all RGXCMP functions with services @@ -1145,7 +1145,7 @@ PVRSRV_ERROR InitRGXCMPBridge(void) /* * Unregister all rgxcmp functions with services */ -PVRSRV_ERROR DeinitRGXCMPBridge(void) +void DeinitRGXCMPBridge(void) { UnsetDispatchTableEntry(PVRSRV_BRIDGE_RGXCMP, PVRSRV_BRIDGE_RGXCMP_RGXCREATECOMPUTECONTEXT); @@ -1168,5 +1168,4 @@ PVRSRV_ERROR DeinitRGXCMPBridge(void) UnsetDispatchTableEntry(PVRSRV_BRIDGE_RGXCMP, PVRSRV_BRIDGE_RGXCMP_RGXGETLASTDEVICEERROR); - return PVRSRV_OK; } diff --git a/drivers/gpu/drm/img-rogue/server_rgxfwdbg_bridge.c b/drivers/gpu/drm/img-rogue/server_rgxfwdbg_bridge.c index 571bf1bad..e66ce89c6 100644 --- a/drivers/gpu/drm/img-rogue/server_rgxfwdbg_bridge.c +++ b/drivers/gpu/drm/img-rogue/server_rgxfwdbg_bridge.c @@ -235,7 +235,7 @@ PVRSRVBridgeRGXCurrentTime(IMG_UINT32 ui32DispatchTableEntry, */ PVRSRV_ERROR InitRGXFWDBGBridge(void); -PVRSRV_ERROR DeinitRGXFWDBGBridge(void); +void DeinitRGXFWDBGBridge(void); /* * Register all RGXFWDBG functions with services @@ -277,7 +277,7 @@ PVRSRV_ERROR InitRGXFWDBGBridge(void) /* * Unregister all rgxfwdbg functions with services */ -PVRSRV_ERROR DeinitRGXFWDBGBridge(void) +void DeinitRGXFWDBGBridge(void) { UnsetDispatchTableEntry(PVRSRV_BRIDGE_RGXFWDBG, PVRSRV_BRIDGE_RGXFWDBG_RGXFWDEBUGSETFWLOG); @@ -302,5 +302,4 @@ PVRSRV_ERROR DeinitRGXFWDBGBridge(void) UnsetDispatchTableEntry(PVRSRV_BRIDGE_RGXFWDBG, PVRSRV_BRIDGE_RGXFWDBG_RGXCURRENTTIME); - return PVRSRV_OK; } diff --git a/drivers/gpu/drm/img-rogue/server_rgxhwperf_bridge.c b/drivers/gpu/drm/img-rogue/server_rgxhwperf_bridge.c index 2dbd323fb..cc22ee30e 100644 --- a/drivers/gpu/drm/img-rogue/server_rgxhwperf_bridge.c +++ b/drivers/gpu/drm/img-rogue/server_rgxhwperf_bridge.c @@ -591,7 +591,7 @@ RGXConfigureHWPerfBlocks_exit: */ PVRSRV_ERROR InitRGXHWPERFBridge(void); -PVRSRV_ERROR DeinitRGXHWPERFBridge(void); +void DeinitRGXHWPERFBridge(void); /* * Register all RGXHWPERF functions with services @@ -628,7 +628,7 @@ PVRSRV_ERROR InitRGXHWPERFBridge(void) /* * Unregister all rgxhwperf functions with services */ -PVRSRV_ERROR DeinitRGXHWPERFBridge(void) +void DeinitRGXHWPERFBridge(void) { UnsetDispatchTableEntry(PVRSRV_BRIDGE_RGXHWPERF, PVRSRV_BRIDGE_RGXHWPERF_RGXCTRLHWPERF); @@ -648,5 +648,4 @@ PVRSRV_ERROR DeinitRGXHWPERFBridge(void) UnsetDispatchTableEntry(PVRSRV_BRIDGE_RGXHWPERF, PVRSRV_BRIDGE_RGXHWPERF_RGXCONFIGUREHWPERFBLOCKS); - return PVRSRV_OK; } diff --git a/drivers/gpu/drm/img-rogue/server_rgxkicksync_bridge.c b/drivers/gpu/drm/img-rogue/server_rgxkicksync_bridge.c index 4e248ce13..25f68f302 100644 --- a/drivers/gpu/drm/img-rogue/server_rgxkicksync_bridge.c +++ b/drivers/gpu/drm/img-rogue/server_rgxkicksync_bridge.c @@ -179,12 +179,13 @@ PVRSRVBridgeRGXDestroyKickSyncContext(IMG_UINT32 ui32DispatchTableEntry, LockHandle(psConnection->psHandleBase); psRGXDestroyKickSyncContextOUT->eError = - PVRSRVReleaseHandleStagedUnlock(psConnection->psHandleBase, - (IMG_HANDLE) psRGXDestroyKickSyncContextIN-> - hKickSyncContext, - PVRSRV_HANDLE_TYPE_RGX_SERVER_KICKSYNC_CONTEXT); + PVRSRVDestroyHandleStagedUnlocked(psConnection->psHandleBase, + (IMG_HANDLE) psRGXDestroyKickSyncContextIN-> + hKickSyncContext, + PVRSRV_HANDLE_TYPE_RGX_SERVER_KICKSYNC_CONTEXT); if (unlikely ((psRGXDestroyKickSyncContextOUT->eError != PVRSRV_OK) + && (psRGXDestroyKickSyncContextOUT->eError != PVRSRV_ERROR_KERNEL_CCB_FULL) && (psRGXDestroyKickSyncContextOUT->eError != PVRSRV_ERROR_RETRY))) { PVR_DPF((PVR_DBG_ERROR, @@ -413,7 +414,6 @@ PVRSRVBridgeRGXKickSync2(IMG_UINT32 ui32DispatchTableEntry, psRGXKickSync2OUT->eError = PVRSRVRGXKickSyncKM(psKickSyncContextInt, - psRGXKickSync2IN->ui32ClientCacheOpSeqNum, psRGXKickSync2IN->ui32ClientUpdateCount, psUpdateUFODevVarBlockInt, ui32UpdateDevVarOffsetInt, @@ -533,7 +533,7 @@ RGXSetKickSyncContextProperty_exit: */ PVRSRV_ERROR InitRGXKICKSYNCBridge(void); -PVRSRV_ERROR DeinitRGXKICKSYNCBridge(void); +void DeinitRGXKICKSYNCBridge(void); /* * Register all RGXKICKSYNC functions with services @@ -562,7 +562,7 @@ PVRSRV_ERROR InitRGXKICKSYNCBridge(void) /* * Unregister all rgxkicksync functions with services */ -PVRSRV_ERROR DeinitRGXKICKSYNCBridge(void) +void DeinitRGXKICKSYNCBridge(void) { UnsetDispatchTableEntry(PVRSRV_BRIDGE_RGXKICKSYNC, @@ -576,5 +576,4 @@ PVRSRV_ERROR DeinitRGXKICKSYNCBridge(void) UnsetDispatchTableEntry(PVRSRV_BRIDGE_RGXKICKSYNC, PVRSRV_BRIDGE_RGXKICKSYNC_RGXSETKICKSYNCCONTEXTPROPERTY); - return PVRSRV_OK; } diff --git a/drivers/gpu/drm/img-rogue/server_rgxregconfig_bridge.c b/drivers/gpu/drm/img-rogue/server_rgxregconfig_bridge.c index a04e0829f..4cdcb1272 100644 --- a/drivers/gpu/drm/img-rogue/server_rgxregconfig_bridge.c +++ b/drivers/gpu/drm/img-rogue/server_rgxregconfig_bridge.c @@ -174,7 +174,7 @@ PVRSRVBridgeRGXDisableRegConfig(IMG_UINT32 ui32DispatchTableEntry, #if !defined(EXCLUDE_RGXREGCONFIG_BRIDGE) PVRSRV_ERROR InitRGXREGCONFIGBridge(void); -PVRSRV_ERROR DeinitRGXREGCONFIGBridge(void); +void DeinitRGXREGCONFIGBridge(void); /* * Register all RGXREGCONFIG functions with services @@ -208,7 +208,7 @@ PVRSRV_ERROR InitRGXREGCONFIGBridge(void) /* * Unregister all rgxregconfig functions with services */ -PVRSRV_ERROR DeinitRGXREGCONFIGBridge(void) +void DeinitRGXREGCONFIGBridge(void) { UnsetDispatchTableEntry(PVRSRV_BRIDGE_RGXREGCONFIG, @@ -226,7 +226,6 @@ PVRSRV_ERROR DeinitRGXREGCONFIGBridge(void) UnsetDispatchTableEntry(PVRSRV_BRIDGE_RGXREGCONFIG, PVRSRV_BRIDGE_RGXREGCONFIG_RGXDISABLEREGCONFIG); - return PVRSRV_OK; } #else /* EXCLUDE_RGXREGCONFIG_BRIDGE */ /* This bridge is conditional on EXCLUDE_RGXREGCONFIG_BRIDGE - when defined, @@ -235,7 +234,6 @@ PVRSRV_ERROR DeinitRGXREGCONFIGBridge(void) #define InitRGXREGCONFIGBridge() \ PVRSRV_OK -#define DeinitRGXREGCONFIGBridge() \ - PVRSRV_OK +#define DeinitRGXREGCONFIGBridge() #endif /* EXCLUDE_RGXREGCONFIG_BRIDGE */ diff --git a/drivers/gpu/drm/img-rogue/server_rgxta3d_bridge.c b/drivers/gpu/drm/img-rogue/server_rgxta3d_bridge.c index d10c0c8f4..44300ec85 100644 --- a/drivers/gpu/drm/img-rogue/server_rgxta3d_bridge.c +++ b/drivers/gpu/drm/img-rogue/server_rgxta3d_bridge.c @@ -72,14 +72,20 @@ static PVRSRV_ERROR _RGXCreateHWRTDataSetpsKmHwRTDataSetIntRelease(void *pvData) return eError; } +static_assert(RGXMKIF_NUM_GEOMDATAS <= IMG_UINT32_MAX, + "RGXMKIF_NUM_GEOMDATAS must not be larger than IMG_UINT32_MAX"); static_assert(RGXMKIF_NUM_RTDATAS <= IMG_UINT32_MAX, "RGXMKIF_NUM_RTDATAS must not be larger than IMG_UINT32_MAX"); -static_assert(RGXFW_MAX_FREELISTS <= IMG_UINT32_MAX, - "RGXFW_MAX_FREELISTS must not be larger than IMG_UINT32_MAX"); +static_assert(RGXMKIF_NUM_RTDATA_FREELISTS <= IMG_UINT32_MAX, + "RGXMKIF_NUM_RTDATA_FREELISTS must not be larger than IMG_UINT32_MAX"); +static_assert(RGXMKIF_NUM_GEOMDATAS <= IMG_UINT32_MAX, + "RGXMKIF_NUM_GEOMDATAS must not be larger than IMG_UINT32_MAX"); static_assert(RGXMKIF_NUM_RTDATAS <= IMG_UINT32_MAX, "RGXMKIF_NUM_RTDATAS must not be larger than IMG_UINT32_MAX"); static_assert(RGXMKIF_NUM_RTDATAS <= IMG_UINT32_MAX, "RGXMKIF_NUM_RTDATAS must not be larger than IMG_UINT32_MAX"); +static_assert(RGXMKIF_NUM_GEOMDATAS <= IMG_UINT32_MAX, + "RGXMKIF_NUM_GEOMDATAS must not be larger than IMG_UINT32_MAX"); static IMG_INT PVRSRVBridgeRGXCreateHWRTDataSet(IMG_UINT32 ui32DispatchTableEntry, @@ -94,11 +100,14 @@ PVRSRVBridgeRGXCreateHWRTDataSet(IMG_UINT32 ui32DispatchTableEntry, (PVRSRV_BRIDGE_OUT_RGXCREATEHWRTDATASET *) IMG_OFFSET_ADDR(psRGXCreateHWRTDataSetOUT_UI8, 0); + IMG_DEV_VIRTADDR *sVHeapTableDevVAddrInt = NULL; IMG_DEV_VIRTADDR *sPMMlistDevVAddrInt = NULL; RGX_FREELIST **psapsFreeListsInt = NULL; IMG_HANDLE *hapsFreeListsInt2 = NULL; + IMG_DEV_VIRTADDR *sTailPtrsDevVAddrInt = NULL; IMG_DEV_VIRTADDR *sMacrotileArrayDevVAddrInt = NULL; IMG_DEV_VIRTADDR *sRgnHeaderDevVAddrInt = NULL; + IMG_DEV_VIRTADDR *sRTCDevVAddrInt = NULL; RGX_KM_HW_RT_DATASET **psKmHwRTDataSetInt = NULL; IMG_HANDLE *hKmHwRTDataSetInt2 = NULL; @@ -110,11 +119,14 @@ PVRSRVBridgeRGXCreateHWRTDataSet(IMG_UINT32 ui32DispatchTableEntry, IMG_UINT32 ui32BufferSize = 0; IMG_UINT64 ui64BufferSize = + ((IMG_UINT64) RGXMKIF_NUM_GEOMDATAS * sizeof(IMG_DEV_VIRTADDR)) + ((IMG_UINT64) RGXMKIF_NUM_RTDATAS * sizeof(IMG_DEV_VIRTADDR)) + - ((IMG_UINT64) RGXFW_MAX_FREELISTS * sizeof(RGX_FREELIST *)) + - ((IMG_UINT64) RGXFW_MAX_FREELISTS * sizeof(IMG_HANDLE)) + + ((IMG_UINT64) RGXMKIF_NUM_RTDATA_FREELISTS * sizeof(RGX_FREELIST *)) + + ((IMG_UINT64) RGXMKIF_NUM_RTDATA_FREELISTS * sizeof(IMG_HANDLE)) + + ((IMG_UINT64) RGXMKIF_NUM_GEOMDATAS * sizeof(IMG_DEV_VIRTADDR)) + ((IMG_UINT64) RGXMKIF_NUM_RTDATAS * sizeof(IMG_DEV_VIRTADDR)) + ((IMG_UINT64) RGXMKIF_NUM_RTDATAS * sizeof(IMG_DEV_VIRTADDR)) + + ((IMG_UINT64) RGXMKIF_NUM_GEOMDATAS * sizeof(IMG_DEV_VIRTADDR)) + ((IMG_UINT64) RGXMKIF_NUM_RTDATAS * sizeof(RGX_KM_HW_RT_DATASET *)) + ((IMG_UINT64) RGXMKIF_NUM_RTDATAS * sizeof(IMG_HANDLE)) + 0; @@ -158,6 +170,26 @@ PVRSRVBridgeRGXCreateHWRTDataSet(IMG_UINT32 ui32DispatchTableEntry, } } + { + sVHeapTableDevVAddrInt = + (IMG_DEV_VIRTADDR *) IMG_OFFSET_ADDR(pArrayArgsBuffer, ui32NextOffset); + ui32NextOffset += RGXMKIF_NUM_GEOMDATAS * sizeof(IMG_DEV_VIRTADDR); + } + + /* Copy the data over */ + if (RGXMKIF_NUM_GEOMDATAS * sizeof(IMG_DEV_VIRTADDR) > 0) + { + if (OSCopyFromUser + (NULL, sVHeapTableDevVAddrInt, + (const void __user *)psRGXCreateHWRTDataSetIN->psVHeapTableDevVAddr, + RGXMKIF_NUM_GEOMDATAS * sizeof(IMG_DEV_VIRTADDR)) != PVRSRV_OK) + { + psRGXCreateHWRTDataSetOUT->eError = PVRSRV_ERROR_INVALID_PARAMS; + + goto RGXCreateHWRTDataSet_exit; + } + } + { sPMMlistDevVAddrInt = (IMG_DEV_VIRTADDR *) IMG_OFFSET_ADDR(pArrayArgsBuffer, ui32NextOffset); @@ -181,20 +213,41 @@ PVRSRVBridgeRGXCreateHWRTDataSet(IMG_UINT32 ui32DispatchTableEntry, { psapsFreeListsInt = (RGX_FREELIST **) IMG_OFFSET_ADDR(pArrayArgsBuffer, ui32NextOffset); - OSCachedMemSet(psapsFreeListsInt, 0, RGXFW_MAX_FREELISTS * sizeof(RGX_FREELIST *)); - ui32NextOffset += RGXFW_MAX_FREELISTS * sizeof(RGX_FREELIST *); + OSCachedMemSet(psapsFreeListsInt, 0, + RGXMKIF_NUM_RTDATA_FREELISTS * sizeof(RGX_FREELIST *)); + ui32NextOffset += RGXMKIF_NUM_RTDATA_FREELISTS * sizeof(RGX_FREELIST *); hapsFreeListsInt2 = (IMG_HANDLE *) IMG_OFFSET_ADDR(pArrayArgsBuffer, ui32NextOffset); - ui32NextOffset += RGXFW_MAX_FREELISTS * sizeof(IMG_HANDLE); + ui32NextOffset += RGXMKIF_NUM_RTDATA_FREELISTS * sizeof(IMG_HANDLE); } /* Copy the data over */ - if (RGXFW_MAX_FREELISTS * sizeof(IMG_HANDLE) > 0) + if (RGXMKIF_NUM_RTDATA_FREELISTS * sizeof(IMG_HANDLE) > 0) { if (OSCopyFromUser (NULL, hapsFreeListsInt2, (const void __user *)psRGXCreateHWRTDataSetIN->phapsFreeLists, - RGXFW_MAX_FREELISTS * sizeof(IMG_HANDLE)) != PVRSRV_OK) + RGXMKIF_NUM_RTDATA_FREELISTS * sizeof(IMG_HANDLE)) != PVRSRV_OK) + { + psRGXCreateHWRTDataSetOUT->eError = PVRSRV_ERROR_INVALID_PARAMS; + + goto RGXCreateHWRTDataSet_exit; + } + } + + { + sTailPtrsDevVAddrInt = + (IMG_DEV_VIRTADDR *) IMG_OFFSET_ADDR(pArrayArgsBuffer, ui32NextOffset); + ui32NextOffset += RGXMKIF_NUM_GEOMDATAS * sizeof(IMG_DEV_VIRTADDR); + } + + /* Copy the data over */ + if (RGXMKIF_NUM_GEOMDATAS * sizeof(IMG_DEV_VIRTADDR) > 0) + { + if (OSCopyFromUser + (NULL, sTailPtrsDevVAddrInt, + (const void __user *)psRGXCreateHWRTDataSetIN->psTailPtrsDevVAddr, + RGXMKIF_NUM_GEOMDATAS * sizeof(IMG_DEV_VIRTADDR)) != PVRSRV_OK) { psRGXCreateHWRTDataSetOUT->eError = PVRSRV_ERROR_INVALID_PARAMS; @@ -241,6 +294,26 @@ PVRSRVBridgeRGXCreateHWRTDataSet(IMG_UINT32 ui32DispatchTableEntry, goto RGXCreateHWRTDataSet_exit; } } + + { + sRTCDevVAddrInt = + (IMG_DEV_VIRTADDR *) IMG_OFFSET_ADDR(pArrayArgsBuffer, ui32NextOffset); + ui32NextOffset += RGXMKIF_NUM_GEOMDATAS * sizeof(IMG_DEV_VIRTADDR); + } + + /* Copy the data over */ + if (RGXMKIF_NUM_GEOMDATAS * sizeof(IMG_DEV_VIRTADDR) > 0) + { + if (OSCopyFromUser + (NULL, sRTCDevVAddrInt, + (const void __user *)psRGXCreateHWRTDataSetIN->psRTCDevVAddr, + RGXMKIF_NUM_GEOMDATAS * sizeof(IMG_DEV_VIRTADDR)) != PVRSRV_OK) + { + psRGXCreateHWRTDataSetOUT->eError = PVRSRV_ERROR_INVALID_PARAMS; + + goto RGXCreateHWRTDataSet_exit; + } + } if (IMG_OFFSET_ADDR(pArrayArgsBuffer, ui32NextOffset) != NULL) { psKmHwRTDataSetInt = @@ -259,7 +332,7 @@ PVRSRVBridgeRGXCreateHWRTDataSet(IMG_UINT32 ui32DispatchTableEntry, { IMG_UINT32 i; - for (i = 0; i < RGXFW_MAX_FREELISTS; i++) + for (i = 0; i < RGXMKIF_NUM_RTDATA_FREELISTS; i++) { /* Look up the address from the handle */ psRGXCreateHWRTDataSetOUT->eError = @@ -279,31 +352,31 @@ PVRSRVBridgeRGXCreateHWRTDataSet(IMG_UINT32 ui32DispatchTableEntry, psRGXCreateHWRTDataSetOUT->eError = RGXCreateHWRTDataSet(psConnection, OSGetDevNode(psConnection), - psRGXCreateHWRTDataSetIN->ssVHeapTableDevVAddr, + sVHeapTableDevVAddrInt, sPMMlistDevVAddrInt, psapsFreeListsInt, psRGXCreateHWRTDataSetIN->ui32PPPScreen, psRGXCreateHWRTDataSetIN->ui64MultiSampleCtl, psRGXCreateHWRTDataSetIN->ui64FlippedMultiSampleCtl, psRGXCreateHWRTDataSetIN->ui32TPCStride, - psRGXCreateHWRTDataSetIN->sTailPtrsDevVAddr, + sTailPtrsDevVAddrInt, psRGXCreateHWRTDataSetIN->ui32TPCSize, psRGXCreateHWRTDataSetIN->ui32TEScreen, psRGXCreateHWRTDataSetIN->ui32TEAA, psRGXCreateHWRTDataSetIN->ui32TEMTILE1, psRGXCreateHWRTDataSetIN->ui32TEMTILE2, psRGXCreateHWRTDataSetIN->ui32MTileStride, - psRGXCreateHWRTDataSetIN->ui32ui32ISPMergeLowerX, - psRGXCreateHWRTDataSetIN->ui32ui32ISPMergeLowerY, - psRGXCreateHWRTDataSetIN->ui32ui32ISPMergeUpperX, - psRGXCreateHWRTDataSetIN->ui32ui32ISPMergeUpperY, - psRGXCreateHWRTDataSetIN->ui32ui32ISPMergeScaleX, - psRGXCreateHWRTDataSetIN->ui32ui32ISPMergeScaleY, + psRGXCreateHWRTDataSetIN->ui32ISPMergeLowerX, + psRGXCreateHWRTDataSetIN->ui32ISPMergeLowerY, + psRGXCreateHWRTDataSetIN->ui32ISPMergeUpperX, + psRGXCreateHWRTDataSetIN->ui32ISPMergeUpperY, + psRGXCreateHWRTDataSetIN->ui32ISPMergeScaleX, + psRGXCreateHWRTDataSetIN->ui32ISPMergeScaleY, sMacrotileArrayDevVAddrInt, sRgnHeaderDevVAddrInt, - psRGXCreateHWRTDataSetIN->ssRTCDevVAddr, - psRGXCreateHWRTDataSetIN->ui32uiRgnHeaderSize, - psRGXCreateHWRTDataSetIN->ui32ui32ISPMtileSize, + sRTCDevVAddrInt, + psRGXCreateHWRTDataSetIN->ui32RgnHeaderSize, + psRGXCreateHWRTDataSetIN->ui32ISPMtileSize, psRGXCreateHWRTDataSetIN->ui16MaxRTs, psKmHwRTDataSetInt); /* Exit early if bridged call fails */ if (unlikely(psRGXCreateHWRTDataSetOUT->eError != PVRSRV_OK)) @@ -363,7 +436,7 @@ RGXCreateHWRTDataSet_exit: { IMG_UINT32 i; - for (i = 0; i < RGXFW_MAX_FREELISTS; i++) + for (i = 0; i < RGXMKIF_NUM_RTDATA_FREELISTS; i++) { /* Unreference the previously looked up handle */ @@ -429,11 +502,14 @@ PVRSRVBridgeRGXDestroyHWRTDataSet(IMG_UINT32 ui32DispatchTableEntry, LockHandle(psConnection->psHandleBase); psRGXDestroyHWRTDataSetOUT->eError = - PVRSRVReleaseHandleStagedUnlock(psConnection->psHandleBase, - (IMG_HANDLE) psRGXDestroyHWRTDataSetIN->hKmHwRTDataSet, - PVRSRV_HANDLE_TYPE_RGX_KM_HW_RT_DATASET); - if (unlikely((psRGXDestroyHWRTDataSetOUT->eError != PVRSRV_OK) && - (psRGXDestroyHWRTDataSetOUT->eError != PVRSRV_ERROR_RETRY))) + PVRSRVDestroyHandleStagedUnlocked(psConnection->psHandleBase, + (IMG_HANDLE) psRGXDestroyHWRTDataSetIN-> + hKmHwRTDataSet, + PVRSRV_HANDLE_TYPE_RGX_KM_HW_RT_DATASET); + if (unlikely + ((psRGXDestroyHWRTDataSetOUT->eError != PVRSRV_OK) + && (psRGXDestroyHWRTDataSetOUT->eError != PVRSRV_ERROR_KERNEL_CCB_FULL) + && (psRGXDestroyHWRTDataSetOUT->eError != PVRSRV_ERROR_RETRY))) { PVR_DPF((PVR_DBG_ERROR, "%s: %s", @@ -580,11 +656,14 @@ PVRSRVBridgeRGXDestroyZSBuffer(IMG_UINT32 ui32DispatchTableEntry, LockHandle(psConnection->psHandleBase); psRGXDestroyZSBufferOUT->eError = - PVRSRVReleaseHandleStagedUnlock(psConnection->psHandleBase, - (IMG_HANDLE) psRGXDestroyZSBufferIN->hsZSBufferMemDesc, - PVRSRV_HANDLE_TYPE_RGX_FWIF_ZSBUFFER); - if (unlikely((psRGXDestroyZSBufferOUT->eError != PVRSRV_OK) && - (psRGXDestroyZSBufferOUT->eError != PVRSRV_ERROR_RETRY))) + PVRSRVDestroyHandleStagedUnlocked(psConnection->psHandleBase, + (IMG_HANDLE) psRGXDestroyZSBufferIN-> + hsZSBufferMemDesc, + PVRSRV_HANDLE_TYPE_RGX_FWIF_ZSBUFFER); + if (unlikely + ((psRGXDestroyZSBufferOUT->eError != PVRSRV_OK) + && (psRGXDestroyZSBufferOUT->eError != PVRSRV_ERROR_KERNEL_CCB_FULL) + && (psRGXDestroyZSBufferOUT->eError != PVRSRV_ERROR_RETRY))) { PVR_DPF((PVR_DBG_ERROR, "%s: %s", @@ -712,10 +791,11 @@ PVRSRVBridgeRGXUnpopulateZSBuffer(IMG_UINT32 ui32DispatchTableEntry, LockHandle(psConnection->psHandleBase); psRGXUnpopulateZSBufferOUT->eError = - PVRSRVReleaseHandleStagedUnlock(psConnection->psHandleBase, - (IMG_HANDLE) psRGXUnpopulateZSBufferIN->hsPopulation, - PVRSRV_HANDLE_TYPE_RGX_POPULATION); + PVRSRVDestroyHandleStagedUnlocked(psConnection->psHandleBase, + (IMG_HANDLE) psRGXUnpopulateZSBufferIN->hsPopulation, + PVRSRV_HANDLE_TYPE_RGX_POPULATION); if (unlikely((psRGXUnpopulateZSBufferOUT->eError != PVRSRV_OK) && + (psRGXUnpopulateZSBufferOUT->eError != PVRSRV_ERROR_KERNEL_CCB_FULL) && (psRGXUnpopulateZSBufferOUT->eError != PVRSRV_ERROR_RETRY))) { PVR_DPF((PVR_DBG_ERROR, @@ -899,10 +979,11 @@ PVRSRVBridgeRGXDestroyFreeList(IMG_UINT32 ui32DispatchTableEntry, LockHandle(psConnection->psHandleBase); psRGXDestroyFreeListOUT->eError = - PVRSRVReleaseHandleStagedUnlock(psConnection->psHandleBase, - (IMG_HANDLE) psRGXDestroyFreeListIN->hCleanupCookie, - PVRSRV_HANDLE_TYPE_RGX_FREELIST); + PVRSRVDestroyHandleStagedUnlocked(psConnection->psHandleBase, + (IMG_HANDLE) psRGXDestroyFreeListIN->hCleanupCookie, + PVRSRV_HANDLE_TYPE_RGX_FREELIST); if (unlikely((psRGXDestroyFreeListOUT->eError != PVRSRV_OK) && + (psRGXDestroyFreeListOUT->eError != PVRSRV_ERROR_KERNEL_CCB_FULL) && (psRGXDestroyFreeListOUT->eError != PVRSRV_ERROR_RETRY))) { PVR_DPF((PVR_DBG_ERROR, @@ -1079,6 +1160,7 @@ PVRSRVBridgeRGXCreateRenderContext(IMG_UINT32 ui32DispatchTableEntry, PVRSRVRGXCreateRenderContextKM(psConnection, OSGetDevNode(psConnection), psRGXCreateRenderContextIN->ui32Priority, psRGXCreateRenderContextIN->sVDMCallStackAddr, + psRGXCreateRenderContextIN->ui32ui32CallStackDepth, psRGXCreateRenderContextIN->ui32FrameworkCmdSize, ui8FrameworkCmdInt, hPrivDataInt, @@ -1172,12 +1254,13 @@ PVRSRVBridgeRGXDestroyRenderContext(IMG_UINT32 ui32DispatchTableEntry, LockHandle(psConnection->psHandleBase); psRGXDestroyRenderContextOUT->eError = - PVRSRVReleaseHandleStagedUnlock(psConnection->psHandleBase, - (IMG_HANDLE) psRGXDestroyRenderContextIN-> - hCleanupCookie, - PVRSRV_HANDLE_TYPE_RGX_SERVER_RENDER_CONTEXT); + PVRSRVDestroyHandleStagedUnlocked(psConnection->psHandleBase, + (IMG_HANDLE) psRGXDestroyRenderContextIN-> + hCleanupCookie, + PVRSRV_HANDLE_TYPE_RGX_SERVER_RENDER_CONTEXT); if (unlikely ((psRGXDestroyRenderContextOUT->eError != PVRSRV_OK) + && (psRGXDestroyRenderContextOUT->eError != PVRSRV_ERROR_KERNEL_CCB_FULL) && (psRGXDestroyRenderContextOUT->eError != PVRSRV_ERROR_RETRY))) { PVR_DPF((PVR_DBG_ERROR, @@ -1975,7 +2058,6 @@ PVRSRVBridgeRGXKickTA3D2(IMG_UINT32 ui32DispatchTableEntry, psRGXKickTA3D2OUT->eError = PVRSRVRGXKickTA3DKM(psRenderContextInt, - psRGXKickTA3D2IN->ui32ClientCacheOpSeqNum, psRGXKickTA3D2IN->ui32ClientTAFenceCount, psClientTAFenceSyncPrimBlockInt, ui32ClientTAFenceSyncOffsetInt, @@ -1989,8 +2071,8 @@ PVRSRVBridgeRGXKickTA3D2(IMG_UINT32 ui32DispatchTableEntry, ui32Client3DUpdateSyncOffsetInt, ui32Client3DUpdateValueInt, psPRFenceUFOSyncPrimBlockInt, - psRGXKickTA3D2IN->ui32FRFenceUFOSyncOffset, - psRGXKickTA3D2IN->ui32FRFenceValue, + psRGXKickTA3D2IN->ui32PRFenceUFOSyncOffset, + psRGXKickTA3D2IN->ui32PRFenceValue, psRGXKickTA3D2IN->hCheckFence, psRGXKickTA3D2IN->hUpdateTimeline, &psRGXKickTA3D2OUT->hUpdateFence, @@ -2227,7 +2309,7 @@ RGXSetRenderContextProperty_exit: */ PVRSRV_ERROR InitRGXTA3DBridge(void); -PVRSRV_ERROR DeinitRGXTA3DBridge(void); +void DeinitRGXTA3DBridge(void); /* * Register all RGXTA3D functions with services @@ -2285,7 +2367,7 @@ PVRSRV_ERROR InitRGXTA3DBridge(void) /* * Unregister all rgxta3d functions with services */ -PVRSRV_ERROR DeinitRGXTA3DBridge(void) +void DeinitRGXTA3DBridge(void) { UnsetDispatchTableEntry(PVRSRV_BRIDGE_RGXTA3D, PVRSRV_BRIDGE_RGXTA3D_RGXCREATEHWRTDATASET); @@ -2321,5 +2403,4 @@ PVRSRV_ERROR DeinitRGXTA3DBridge(void) UnsetDispatchTableEntry(PVRSRV_BRIDGE_RGXTA3D, PVRSRV_BRIDGE_RGXTA3D_RGXSETRENDERCONTEXTPROPERTY); - return PVRSRV_OK; } diff --git a/drivers/gpu/drm/img-rogue/server_rgxtimerquery_bridge.c b/drivers/gpu/drm/img-rogue/server_rgxtimerquery_bridge.c index ce97a1562..99e6239cf 100644 --- a/drivers/gpu/drm/img-rogue/server_rgxtimerquery_bridge.c +++ b/drivers/gpu/drm/img-rogue/server_rgxtimerquery_bridge.c @@ -126,7 +126,7 @@ PVRSRVBridgeRGXQueryTimer(IMG_UINT32 ui32DispatchTableEntry, */ PVRSRV_ERROR InitRGXTIMERQUERYBridge(void); -PVRSRV_ERROR DeinitRGXTIMERQUERYBridge(void); +void DeinitRGXTIMERQUERYBridge(void); /* * Register all RGXTIMERQUERY functions with services @@ -152,7 +152,7 @@ PVRSRV_ERROR InitRGXTIMERQUERYBridge(void) /* * Unregister all rgxtimerquery functions with services */ -PVRSRV_ERROR DeinitRGXTIMERQUERYBridge(void) +void DeinitRGXTIMERQUERYBridge(void) { UnsetDispatchTableEntry(PVRSRV_BRIDGE_RGXTIMERQUERY, @@ -164,5 +164,4 @@ PVRSRV_ERROR DeinitRGXTIMERQUERYBridge(void) UnsetDispatchTableEntry(PVRSRV_BRIDGE_RGXTIMERQUERY, PVRSRV_BRIDGE_RGXTIMERQUERY_RGXQUERYTIMER); - return PVRSRV_OK; } diff --git a/drivers/gpu/drm/img-rogue/server_rgxtq2_bridge.c b/drivers/gpu/drm/img-rogue/server_rgxtq2_bridge.c index 1edad51f1..f73bb906b 100644 --- a/drivers/gpu/drm/img-rogue/server_rgxtq2_bridge.c +++ b/drivers/gpu/drm/img-rogue/server_rgxtq2_bridge.c @@ -103,10 +103,10 @@ PVRSRVBridgeRGXTDMCreateTransferContext(IMG_UINT32 ui32DispatchTableEntry, IMG_UINT32 ui32BufferSize = 0; IMG_UINT64 ui64BufferSize = - ((IMG_UINT64) psRGXTDMCreateTransferContextIN->ui32FrameworkCmdize * sizeof(IMG_BYTE)) + - 0; + ((IMG_UINT64) psRGXTDMCreateTransferContextIN->ui32FrameworkCmdSize * + sizeof(IMG_BYTE)) + 0; - if (unlikely(psRGXTDMCreateTransferContextIN->ui32FrameworkCmdize > RGXFWIF_RF_CMD_SIZE)) + if (unlikely(psRGXTDMCreateTransferContextIN->ui32FrameworkCmdSize > RGXFWIF_RF_CMD_SIZE)) { psRGXTDMCreateTransferContextOUT->eError = PVRSRV_ERROR_BRIDGE_ARRAY_SIZE_TOO_BIG; goto RGXTDMCreateTransferContext_exit; @@ -166,20 +166,20 @@ PVRSRVBridgeRGXTDMCreateTransferContext(IMG_UINT32 ui32DispatchTableEntry, } } - if (psRGXTDMCreateTransferContextIN->ui32FrameworkCmdize != 0) + if (psRGXTDMCreateTransferContextIN->ui32FrameworkCmdSize != 0) { ui8FrameworkCmdInt = (IMG_BYTE *) IMG_OFFSET_ADDR(pArrayArgsBuffer, ui32NextOffset); ui32NextOffset += - psRGXTDMCreateTransferContextIN->ui32FrameworkCmdize * sizeof(IMG_BYTE); + psRGXTDMCreateTransferContextIN->ui32FrameworkCmdSize * sizeof(IMG_BYTE); } /* Copy the data over */ - if (psRGXTDMCreateTransferContextIN->ui32FrameworkCmdize * sizeof(IMG_BYTE) > 0) + if (psRGXTDMCreateTransferContextIN->ui32FrameworkCmdSize * sizeof(IMG_BYTE) > 0) { if (OSCopyFromUser (NULL, ui8FrameworkCmdInt, (const void __user *)psRGXTDMCreateTransferContextIN->pui8FrameworkCmd, - psRGXTDMCreateTransferContextIN->ui32FrameworkCmdize * sizeof(IMG_BYTE)) != + psRGXTDMCreateTransferContextIN->ui32FrameworkCmdSize * sizeof(IMG_BYTE)) != PVRSRV_OK) { psRGXTDMCreateTransferContextOUT->eError = PVRSRV_ERROR_INVALID_PARAMS; @@ -208,12 +208,13 @@ PVRSRVBridgeRGXTDMCreateTransferContext(IMG_UINT32 ui32DispatchTableEntry, PVRSRVRGXTDMCreateTransferContextKM(psConnection, OSGetDevNode(psConnection), psRGXTDMCreateTransferContextIN->ui32Priority, psRGXTDMCreateTransferContextIN-> - ui32FrameworkCmdize, ui8FrameworkCmdInt, + ui32FrameworkCmdSize, ui8FrameworkCmdInt, hPrivDataInt, psRGXTDMCreateTransferContextIN-> ui32PackedCCBSizeU88, psRGXTDMCreateTransferContextIN->ui32ContextFlags, - &psTransferContextInt); + psRGXTDMCreateTransferContextIN-> + ui64RobustnessAddress, &psTransferContextInt); /* Exit early if bridged call fails */ if (unlikely(psRGXTDMCreateTransferContextOUT->eError != PVRSRV_OK)) { @@ -309,12 +310,13 @@ PVRSRVBridgeRGXTDMDestroyTransferContext(IMG_UINT32 ui32DispatchTableEntry, LockHandle(psConnection->psHandleBase); psRGXTDMDestroyTransferContextOUT->eError = - PVRSRVReleaseHandleStagedUnlock(psConnection->psHandleBase, - (IMG_HANDLE) psRGXTDMDestroyTransferContextIN-> - hTransferContext, - PVRSRV_HANDLE_TYPE_RGX_SERVER_TQ_TDM_CONTEXT); + PVRSRVDestroyHandleStagedUnlocked(psConnection->psHandleBase, + (IMG_HANDLE) psRGXTDMDestroyTransferContextIN-> + hTransferContext, + PVRSRV_HANDLE_TYPE_RGX_SERVER_TQ_TDM_CONTEXT); if (unlikely ((psRGXTDMDestroyTransferContextOUT->eError != PVRSRV_OK) + && (psRGXTDMDestroyTransferContextOUT->eError != PVRSRV_ERROR_KERNEL_CCB_FULL) && (psRGXTDMDestroyTransferContextOUT->eError != PVRSRV_ERROR_RETRY))) { PVR_DPF((PVR_DBG_ERROR, @@ -816,7 +818,6 @@ PVRSRVBridgeRGXTDMSubmitTransfer2(IMG_UINT32 ui32DispatchTableEntry, psRGXTDMSubmitTransfer2OUT->eError = PVRSRVRGXTDMSubmitTransferKM(psTransferContextInt, psRGXTDMSubmitTransfer2IN->ui32PDumpFlags, - psRGXTDMSubmitTransfer2IN->ui32ClientCacheOpSeqNum, psRGXTDMSubmitTransfer2IN->ui32ClientUpdateCount, psUpdateUFOSyncPrimBlockInt, ui32UpdateSyncOffsetInt, @@ -1037,10 +1038,11 @@ PVRSRVBridgeRGXTDMReleaseSharedMemory(IMG_UINT32 ui32DispatchTableEntry, LockHandle(psConnection->psHandleBase); psRGXTDMReleaseSharedMemoryOUT->eError = - PVRSRVReleaseHandleStagedUnlock(psConnection->psHandleBase, - (IMG_HANDLE) psRGXTDMReleaseSharedMemoryIN->hPMRMem, - PVRSRV_HANDLE_TYPE_PMR_LOCAL_EXPORT_HANDLE); + PVRSRVDestroyHandleStagedUnlocked(psConnection->psHandleBase, + (IMG_HANDLE) psRGXTDMReleaseSharedMemoryIN->hPMRMem, + PVRSRV_HANDLE_TYPE_PMR_LOCAL_EXPORT_HANDLE); if (unlikely((psRGXTDMReleaseSharedMemoryOUT->eError != PVRSRV_OK) && + (psRGXTDMReleaseSharedMemoryOUT->eError != PVRSRV_ERROR_KERNEL_CCB_FULL) && (psRGXTDMReleaseSharedMemoryOUT->eError != PVRSRV_ERROR_RETRY))) { PVR_DPF((PVR_DBG_ERROR, @@ -1137,7 +1139,7 @@ RGXTDMSetTransferContextProperty_exit: */ PVRSRV_ERROR InitRGXTQ2Bridge(void); -PVRSRV_ERROR DeinitRGXTQ2Bridge(void); +void DeinitRGXTQ2Bridge(void); /* * Register all RGXTQ2 functions with services @@ -1180,7 +1182,7 @@ PVRSRV_ERROR InitRGXTQ2Bridge(void) /* * Unregister all rgxtq2 functions with services */ -PVRSRV_ERROR DeinitRGXTQ2Bridge(void) +void DeinitRGXTQ2Bridge(void) { UnsetDispatchTableEntry(PVRSRV_BRIDGE_RGXTQ2, @@ -1205,5 +1207,4 @@ PVRSRV_ERROR DeinitRGXTQ2Bridge(void) UnsetDispatchTableEntry(PVRSRV_BRIDGE_RGXTQ2, PVRSRV_BRIDGE_RGXTQ2_RGXTDMSETTRANSFERCONTEXTPROPERTY); - return PVRSRV_OK; } diff --git a/drivers/gpu/drm/img-rogue/server_rgxtq_bridge.c b/drivers/gpu/drm/img-rogue/server_rgxtq_bridge.c index 8d088da4c..70415f5ff 100644 --- a/drivers/gpu/drm/img-rogue/server_rgxtq_bridge.c +++ b/drivers/gpu/drm/img-rogue/server_rgxtq_bridge.c @@ -200,6 +200,7 @@ PVRSRVBridgeRGXCreateTransferContext(IMG_UINT32 ui32DispatchTableEntry, hPrivDataInt, psRGXCreateTransferContextIN->ui32PackedCCBSizeU8888, psRGXCreateTransferContextIN->ui32ContextFlags, + psRGXCreateTransferContextIN->ui64RobustnessAddress, &psTransferContextInt, &psCLIPMRMemInt, &psUSCPMRMemInt); /* Exit early if bridged call fails */ @@ -277,7 +278,7 @@ RGXCreateTransferContext_exit: /* Lock over handle creation cleanup. */ LockHandle(psConnection->psHandleBase); - eError = PVRSRVReleaseHandleUnlocked(psConnection->psHandleBase, + eError = PVRSRVDestroyHandleUnlocked(psConnection->psHandleBase, (IMG_HANDLE) psRGXCreateTransferContextOUT-> hTransferContext, @@ -337,12 +338,13 @@ PVRSRVBridgeRGXDestroyTransferContext(IMG_UINT32 ui32DispatchTableEntry, LockHandle(psConnection->psHandleBase); psRGXDestroyTransferContextOUT->eError = - PVRSRVReleaseHandleStagedUnlock(psConnection->psHandleBase, - (IMG_HANDLE) psRGXDestroyTransferContextIN-> - hTransferContext, - PVRSRV_HANDLE_TYPE_RGX_SERVER_TQ_CONTEXT); + PVRSRVDestroyHandleStagedUnlocked(psConnection->psHandleBase, + (IMG_HANDLE) psRGXDestroyTransferContextIN-> + hTransferContext, + PVRSRV_HANDLE_TYPE_RGX_SERVER_TQ_CONTEXT); if (unlikely ((psRGXDestroyTransferContextOUT->eError != PVRSRV_OK) + && (psRGXDestroyTransferContextOUT->eError != PVRSRV_ERROR_KERNEL_CCB_FULL) && (psRGXDestroyTransferContextOUT->eError != PVRSRV_ERROR_RETRY))) { PVR_DPF((PVR_DBG_ERROR, @@ -989,7 +991,6 @@ PVRSRVBridgeRGXSubmitTransfer2(IMG_UINT32 ui32DispatchTableEntry, psRGXSubmitTransfer2OUT->eError = PVRSRVRGXSubmitTransferKM(psTransferContextInt, - psRGXSubmitTransfer2IN->ui32ClientCacheOpSeqNum, psRGXSubmitTransfer2IN->ui32PrepareCount, ui32ClientUpdateCountInt, psUpdateUFOSyncPrimBlockInt, @@ -1152,7 +1153,7 @@ RGXSetTransferContextProperty_exit: #if defined(SUPPORT_RGXTQ_BRIDGE) PVRSRV_ERROR InitRGXTQBridge(void); -PVRSRV_ERROR DeinitRGXTQBridge(void); +void DeinitRGXTQBridge(void); /* * Register all RGXTQ functions with services @@ -1183,7 +1184,7 @@ PVRSRV_ERROR InitRGXTQBridge(void) /* * Unregister all rgxtq functions with services */ -PVRSRV_ERROR DeinitRGXTQBridge(void) +void DeinitRGXTQBridge(void) { UnsetDispatchTableEntry(PVRSRV_BRIDGE_RGXTQ, PVRSRV_BRIDGE_RGXTQ_RGXCREATETRANSFERCONTEXT); @@ -1198,7 +1199,6 @@ PVRSRV_ERROR DeinitRGXTQBridge(void) UnsetDispatchTableEntry(PVRSRV_BRIDGE_RGXTQ, PVRSRV_BRIDGE_RGXTQ_RGXSETTRANSFERCONTEXTPROPERTY); - return PVRSRV_OK; } #else /* SUPPORT_RGXTQ_BRIDGE */ /* This bridge is conditional on SUPPORT_RGXTQ_BRIDGE - when not defined, @@ -1207,7 +1207,6 @@ PVRSRV_ERROR DeinitRGXTQBridge(void) #define InitRGXTQBridge() \ PVRSRV_OK -#define DeinitRGXTQBridge() \ - PVRSRV_OK +#define DeinitRGXTQBridge() #endif /* SUPPORT_RGXTQ_BRIDGE */ diff --git a/drivers/gpu/drm/img-rogue/server_ri_bridge.c b/drivers/gpu/drm/img-rogue/server_ri_bridge.c index 9c1de3ef5..80f246c58 100644 --- a/drivers/gpu/drm/img-rogue/server_ri_bridge.c +++ b/drivers/gpu/drm/img-rogue/server_ri_bridge.c @@ -533,10 +533,11 @@ PVRSRVBridgeRIDeleteMEMDESCEntry(IMG_UINT32 ui32DispatchTableEntry, LockHandle(psConnection->psHandleBase); psRIDeleteMEMDESCEntryOUT->eError = - PVRSRVReleaseHandleStagedUnlock(psConnection->psHandleBase, - (IMG_HANDLE) psRIDeleteMEMDESCEntryIN->hRIHandle, - PVRSRV_HANDLE_TYPE_RI_HANDLE); + PVRSRVDestroyHandleStagedUnlocked(psConnection->psHandleBase, + (IMG_HANDLE) psRIDeleteMEMDESCEntryIN->hRIHandle, + PVRSRV_HANDLE_TYPE_RI_HANDLE); if (unlikely((psRIDeleteMEMDESCEntryOUT->eError != PVRSRV_OK) && + (psRIDeleteMEMDESCEntryOUT->eError != PVRSRV_ERROR_KERNEL_CCB_FULL) && (psRIDeleteMEMDESCEntryOUT->eError != PVRSRV_ERROR_RETRY))) { PVR_DPF((PVR_DBG_ERROR, @@ -694,7 +695,7 @@ RIWritePMREntryWithOwner_exit: */ PVRSRV_ERROR InitRIBridge(void); -PVRSRV_ERROR DeinitRIBridge(void); +void DeinitRIBridge(void); /* * Register all RI functions with services @@ -735,7 +736,7 @@ PVRSRV_ERROR InitRIBridge(void) /* * Unregister all ri functions with services */ -PVRSRV_ERROR DeinitRIBridge(void) +void DeinitRIBridge(void) { UnsetDispatchTableEntry(PVRSRV_BRIDGE_RI, PVRSRV_BRIDGE_RI_RIWRITEPMRENTRY); @@ -756,5 +757,4 @@ PVRSRV_ERROR DeinitRIBridge(void) UnsetDispatchTableEntry(PVRSRV_BRIDGE_RI, PVRSRV_BRIDGE_RI_RIWRITEPMRENTRYWITHOWNER); - return PVRSRV_OK; } diff --git a/drivers/gpu/drm/img-rogue/server_srvcore_bridge.c b/drivers/gpu/drm/img-rogue/server_srvcore_bridge.c index 271e10764..48abd121f 100644 --- a/drivers/gpu/drm/img-rogue/server_srvcore_bridge.c +++ b/drivers/gpu/drm/img-rogue/server_srvcore_bridge.c @@ -190,12 +190,13 @@ PVRSRVBridgeReleaseGlobalEventObject(IMG_UINT32 ui32DispatchTableEntry, LockHandle(psConnection->psHandleBase); psReleaseGlobalEventObjectOUT->eError = - PVRSRVReleaseHandleStagedUnlock(psConnection->psHandleBase, - (IMG_HANDLE) psReleaseGlobalEventObjectIN-> - hGlobalEventObject, - PVRSRV_HANDLE_TYPE_SHARED_EVENT_OBJECT); + PVRSRVDestroyHandleStagedUnlocked(psConnection->psHandleBase, + (IMG_HANDLE) psReleaseGlobalEventObjectIN-> + hGlobalEventObject, + PVRSRV_HANDLE_TYPE_SHARED_EVENT_OBJECT); if (unlikely ((psReleaseGlobalEventObjectOUT->eError != PVRSRV_OK) + && (psReleaseGlobalEventObjectOUT->eError != PVRSRV_ERROR_KERNEL_CCB_FULL) && (psReleaseGlobalEventObjectOUT->eError != PVRSRV_ERROR_RETRY))) { PVR_DPF((PVR_DBG_ERROR, @@ -365,10 +366,11 @@ PVRSRVBridgeEventObjectClose(IMG_UINT32 ui32DispatchTableEntry, LockHandle(psConnection->psHandleBase); psEventObjectCloseOUT->eError = - PVRSRVReleaseHandleStagedUnlock(psConnection->psHandleBase, - (IMG_HANDLE) psEventObjectCloseIN->hOSEventKM, - PVRSRV_HANDLE_TYPE_EVENT_OBJECT_CONNECT); + PVRSRVDestroyHandleStagedUnlocked(psConnection->psHandleBase, + (IMG_HANDLE) psEventObjectCloseIN->hOSEventKM, + PVRSRV_HANDLE_TYPE_EVENT_OBJECT_CONNECT); if (unlikely((psEventObjectCloseOUT->eError != PVRSRV_OK) && + (psEventObjectCloseOUT->eError != PVRSRV_ERROR_KERNEL_CCB_FULL) && (psEventObjectCloseOUT->eError != PVRSRV_ERROR_RETRY))) { PVR_DPF((PVR_DBG_ERROR, @@ -936,10 +938,11 @@ PVRSRVBridgeReleaseInfoPage(IMG_UINT32 ui32DispatchTableEntry, LockHandle(psConnection->psProcessHandleBase->psHandleBase); psReleaseInfoPageOUT->eError = - PVRSRVReleaseHandleStagedUnlock(psConnection->psProcessHandleBase->psHandleBase, - (IMG_HANDLE) psReleaseInfoPageIN->hPMR, - PVRSRV_HANDLE_TYPE_DEVMEM_MEM_IMPORT); + PVRSRVDestroyHandleStagedUnlocked(psConnection->psProcessHandleBase->psHandleBase, + (IMG_HANDLE) psReleaseInfoPageIN->hPMR, + PVRSRV_HANDLE_TYPE_DEVMEM_MEM_IMPORT); if (unlikely((psReleaseInfoPageOUT->eError != PVRSRV_OK) && + (psReleaseInfoPageOUT->eError != PVRSRV_ERROR_KERNEL_CCB_FULL) && (psReleaseInfoPageOUT->eError != PVRSRV_ERROR_RETRY))) { PVR_DPF((PVR_DBG_ERROR, @@ -961,7 +964,7 @@ ReleaseInfoPage_exit: */ PVRSRV_ERROR InitSRVCOREBridge(void); -PVRSRV_ERROR DeinitSRVCOREBridge(void); +void DeinitSRVCOREBridge(void); /* * Register all SRVCORE functions with services @@ -1026,7 +1029,7 @@ PVRSRV_ERROR InitSRVCOREBridge(void) /* * Unregister all srvcore functions with services */ -PVRSRV_ERROR DeinitSRVCOREBridge(void) +void DeinitSRVCOREBridge(void) { UnsetDispatchTableEntry(PVRSRV_BRIDGE_SRVCORE, PVRSRV_BRIDGE_SRVCORE_CONNECT); @@ -1066,5 +1069,4 @@ PVRSRV_ERROR DeinitSRVCOREBridge(void) UnsetDispatchTableEntry(PVRSRV_BRIDGE_SRVCORE, PVRSRV_BRIDGE_SRVCORE_RELEASEINFOPAGE); - return PVRSRV_OK; } diff --git a/drivers/gpu/drm/img-rogue/server_sync_bridge.c b/drivers/gpu/drm/img-rogue/server_sync_bridge.c index d5a3d56cf..4788fc1fb 100644 --- a/drivers/gpu/drm/img-rogue/server_sync_bridge.c +++ b/drivers/gpu/drm/img-rogue/server_sync_bridge.c @@ -153,7 +153,7 @@ AllocSyncPrimitiveBlock_exit: /* Lock over handle creation cleanup. */ LockHandle(psConnection->psHandleBase); - eError = PVRSRVReleaseHandleUnlocked(psConnection->psHandleBase, + eError = PVRSRVDestroyHandleUnlocked(psConnection->psHandleBase, (IMG_HANDLE) psAllocSyncPrimitiveBlockOUT-> hSyncHandle, @@ -200,10 +200,11 @@ PVRSRVBridgeFreeSyncPrimitiveBlock(IMG_UINT32 ui32DispatchTableEntry, LockHandle(psConnection->psHandleBase); psFreeSyncPrimitiveBlockOUT->eError = - PVRSRVReleaseHandleStagedUnlock(psConnection->psHandleBase, - (IMG_HANDLE) psFreeSyncPrimitiveBlockIN->hSyncHandle, - PVRSRV_HANDLE_TYPE_SYNC_PRIMITIVE_BLOCK); + PVRSRVDestroyHandleStagedUnlocked(psConnection->psHandleBase, + (IMG_HANDLE) psFreeSyncPrimitiveBlockIN->hSyncHandle, + PVRSRV_HANDLE_TYPE_SYNC_PRIMITIVE_BLOCK); if (unlikely((psFreeSyncPrimitiveBlockOUT->eError != PVRSRV_OK) && + (psFreeSyncPrimitiveBlockOUT->eError != PVRSRV_ERROR_KERNEL_CCB_FULL) && (psFreeSyncPrimitiveBlockOUT->eError != PVRSRV_ERROR_RETRY))) { PVR_DPF((PVR_DBG_ERROR, @@ -673,7 +674,7 @@ PVRSRVBridgeSyncCheckpointSignalledPDumpPol(IMG_UINT32 ui32DispatchTableEntry, */ PVRSRV_ERROR InitSYNCBridge(void); -PVRSRV_ERROR DeinitSYNCBridge(void); +void DeinitSYNCBridge(void); /* * Register all SYNC functions with services @@ -718,7 +719,7 @@ PVRSRV_ERROR InitSYNCBridge(void) /* * Unregister all sync functions with services */ -PVRSRV_ERROR DeinitSYNCBridge(void) +void DeinitSYNCBridge(void) { UnsetDispatchTableEntry(PVRSRV_BRIDGE_SYNC, PVRSRV_BRIDGE_SYNC_ALLOCSYNCPRIMITIVEBLOCK); @@ -742,5 +743,4 @@ PVRSRV_ERROR DeinitSYNCBridge(void) UnsetDispatchTableEntry(PVRSRV_BRIDGE_SYNC, PVRSRV_BRIDGE_SYNC_SYNCCHECKPOINTSIGNALLEDPDUMPPOL); - return PVRSRV_OK; } diff --git a/drivers/gpu/drm/img-rogue/server_synctracking_bridge.c b/drivers/gpu/drm/img-rogue/server_synctracking_bridge.c index c3e39db38..adc8ab487 100644 --- a/drivers/gpu/drm/img-rogue/server_synctracking_bridge.c +++ b/drivers/gpu/drm/img-rogue/server_synctracking_bridge.c @@ -83,10 +83,11 @@ PVRSRVBridgeSyncRecordRemoveByHandle(IMG_UINT32 ui32DispatchTableEntry, LockHandle(psConnection->psHandleBase); psSyncRecordRemoveByHandleOUT->eError = - PVRSRVReleaseHandleStagedUnlock(psConnection->psHandleBase, - (IMG_HANDLE) psSyncRecordRemoveByHandleIN->hhRecord, - PVRSRV_HANDLE_TYPE_SYNC_RECORD_HANDLE); + PVRSRVDestroyHandleStagedUnlocked(psConnection->psHandleBase, + (IMG_HANDLE) psSyncRecordRemoveByHandleIN->hhRecord, + PVRSRV_HANDLE_TYPE_SYNC_RECORD_HANDLE); if (unlikely((psSyncRecordRemoveByHandleOUT->eError != PVRSRV_OK) && + (psSyncRecordRemoveByHandleOUT->eError != PVRSRV_ERROR_KERNEL_CCB_FULL) && (psSyncRecordRemoveByHandleOUT->eError != PVRSRV_ERROR_RETRY))) { PVR_DPF((PVR_DBG_ERROR, @@ -299,7 +300,7 @@ SyncRecordAdd_exit: */ PVRSRV_ERROR InitSYNCTRACKINGBridge(void); -PVRSRV_ERROR DeinitSYNCTRACKINGBridge(void); +void DeinitSYNCTRACKINGBridge(void); /* * Register all SYNCTRACKING functions with services @@ -320,7 +321,7 @@ PVRSRV_ERROR InitSYNCTRACKINGBridge(void) /* * Unregister all synctracking functions with services */ -PVRSRV_ERROR DeinitSYNCTRACKINGBridge(void) +void DeinitSYNCTRACKINGBridge(void) { UnsetDispatchTableEntry(PVRSRV_BRIDGE_SYNCTRACKING, @@ -329,5 +330,4 @@ PVRSRV_ERROR DeinitSYNCTRACKINGBridge(void) UnsetDispatchTableEntry(PVRSRV_BRIDGE_SYNCTRACKING, PVRSRV_BRIDGE_SYNCTRACKING_SYNCRECORDADD); - return PVRSRV_OK; } diff --git a/drivers/gpu/drm/img-rogue/services_kernel_client.h b/drivers/gpu/drm/img-rogue/services_kernel_client.h index 7ad96e2af..aaca47f1e 100644 --- a/drivers/gpu/drm/img-rogue/services_kernel_client.h +++ b/drivers/gpu/drm/img-rogue/services_kernel_client.h @@ -55,6 +55,9 @@ CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. #include "pvrsrv_sync_km.h" #include "sync_checkpoint_external.h" +/* included for the define PVRSRV_LINUX_DEV_INIT_ON_PROBE */ +#include "pvr_drm.h" + #ifndef __pvrsrv_defined_struct_enum__ /* sync_external.h */ @@ -173,7 +176,7 @@ enum PVRSRV_ERROR_TAG PVRSRVCommonDeviceCreate(void *pvOSDevice, enum PVRSRV_ERROR_TAG PVRSRVCommonDeviceDestroy( struct _PVRSRV_DEVICE_NODE_ *psDeviceNode); const char *PVRSRVGetErrorString(enum PVRSRV_ERROR_TAG eError); -#if defined(SUPPORT_FWLOAD_ON_PROBE) +#if (PVRSRV_DEVICE_INIT_MODE == PVRSRV_LINUX_DEV_INIT_ON_PROBE) enum PVRSRV_ERROR_TAG PVRSRVCommonDeviceInitialise( struct _PVRSRV_DEVICE_NODE_ *psDeviceNode); #endif @@ -183,6 +186,7 @@ typedef PVRSRV_ERROR (*PFN_SYNC_CHECKPOINT_FENCE_RESOLVE_FN)(PSYNC_CHECKPOINT_CO #ifndef CHECKPOINT_PFNS typedef PVRSRV_ERROR (*PFN_SYNC_CHECKPOINT_FENCE_CREATE_FN)( + struct _PVRSRV_DEVICE_NODE_ *device, const char *fence_name, PVRSRV_TIMELINE timeline, PSYNC_CHECKPOINT_CONTEXT psSyncCheckpointContext, diff --git a/drivers/gpu/drm/img-rogue/servicesext.h b/drivers/gpu/drm/img-rogue/servicesext.h index 23fab1dac..5d685b2ad 100644 --- a/drivers/gpu/drm/img-rogue/servicesext.h +++ b/drivers/gpu/drm/img-rogue/servicesext.h @@ -88,25 +88,19 @@ typedef enum _PVRSRV_SYS_POWER_STATE_ /*! Device Power State Enum */ -typedef enum _PVRSRV_DEV_POWER_STATE_ -{ - PVRSRV_DEV_POWER_STATE_DEFAULT = -1, /*!< Default state for the device */ - PVRSRV_DEV_POWER_STATE_OFF = 0, /*!< Unpowered */ - PVRSRV_DEV_POWER_STATE_ON = 1, /*!< Running */ - - PVRSRV_DEV_POWER_STATE_FORCE_I32 = 0x7fffffff /*!< Force enum to be at least 32-bits wide */ - -} PVRSRV_DEV_POWER_STATE, *PPVRSRV_DEV_POWER_STATE; /*!< Typedef for ptr to PVRSRV_DEV_POWER_STATE */ /* PRQA S 3205 */ +typedef IMG_INT32 PVRSRV_DEV_POWER_STATE; +typedef IMG_INT32 *PPVRSRV_DEV_POWER_STATE; /*!< Typedef for ptr to PVRSRV_DEV_POWER_STATE */ /* PRQA S 3205 */ +#define PVRSRV_DEV_POWER_STATE_DEFAULT -1 /*!< Default state for the device */ +#define PVRSRV_DEV_POWER_STATE_OFF 0 /*!< Unpowered */ +#define PVRSRV_DEV_POWER_STATE_ON 1 /*!< Running */ /*! Power Flags Enum */ -typedef enum _PVRSRV_POWER_FLAGS_ -{ - PVRSRV_POWER_FLAGS_NONE = 0, /*!< No flags */ - PVRSRV_POWER_FLAGS_FORCED = 1 << 0, /*!< Power the transition should not fail */ - PVRSRV_POWER_FLAGS_SUSPEND = 1 << 1, /*!< Power transition is due to OS suspend request */ -} PVRSRV_POWER_FLAGS; +typedef IMG_UINT32 PVRSRV_POWER_FLAGS; +#define PVRSRV_POWER_FLAGS_NONE 0U /*!< No flags */ +#define PVRSRV_POWER_FLAGS_FORCED 1U << 0 /*!< Power the transition should not fail */ +#define PVRSRV_POWER_FLAGS_SUSPEND 1U << 1 /*!< Power transition is due to OS suspend request */ /* Clock speed handler prototypes */ diff --git a/drivers/gpu/drm/img-rogue/srvcore.c b/drivers/gpu/drm/img-rogue/srvcore.c index 18d0e5441..42a8a82c1 100644 --- a/drivers/gpu/drm/img-rogue/srvcore.c +++ b/drivers/gpu/drm/img-rogue/srvcore.c @@ -224,7 +224,7 @@ PVRSRV_ERROR PVRSRVPrintBridgeStats() "Total number of bytes copied via copy_from_user = %u\n" "Total number of bytes copied via copy_to_user = %u\n" "Total number of bytes copied via copy_*_user = %u\n\n" - "%3s: %-60s | %-48s | %10s | %20s | %20s | %20s | %20s \n", + "%3s: %-60s | %-48s | %10s | %20s | %20s | %20s | %20s\n", g_BridgeGlobalStats.ui32IOCTLCount, g_BridgeGlobalStats.ui32TotalCopyFromUserBytes, g_BridgeGlobalStats.ui32TotalCopyToUserBytes, @@ -655,12 +655,7 @@ PVRSRVConnectKM(CONNECTION_DATA *psConnection, __func__, ui32DDKBuild, ui32ClientDDKBuild)); } - /* If first connection, bind this and future PDump clients to use this device */ - if (psSRVData->ui32PDumpBoundDevice == PVRSRV_MAX_DEVICES) - { - psSRVData->ui32PDumpBoundDevice = psDeviceNode->sDevId.ui32InternalID; - } - +#if defined(PDUMP) /* Success so far so is it the PDump client that is connecting? */ if (ui32Flags & SRV_FLAGS_PDUMPCTRL) { @@ -676,7 +671,6 @@ PVRSRVConnectKM(CONNECTION_DATA *psConnection, goto chk_exit; } } -#if defined(PDUMP) else { /* Warn if the app is connecting to a device PDump won't be able to capture */ @@ -928,6 +922,14 @@ PVRSRV_ERROR PVRSRVGetMultiCoreInfoKM(CONNECTION_DATA *psConnection, PVRSRV_ERROR eError = PVRSRV_ERROR_NOT_SUPPORTED; PVR_UNREFERENCED_PARAMETER(psConnection); + if (ui32CapsSize > 0) + { + /* Clear the buffer to ensure no uninitialised data is returned to UM + * if the pfn call below does not write to the whole array, or is null. + */ + memset(pui64Caps, 0x00, (ui32CapsSize * sizeof(IMG_UINT64))); + } + if (psDeviceNode->pfnGetMultiCoreInfo != NULL) { eError = psDeviceNode->pfnGetMultiCoreInfo(psDeviceNode, ui32CapsSize, pui32NumCores, pui64Caps); diff --git a/drivers/gpu/drm/img-rogue/srvcore.h b/drivers/gpu/drm/img-rogue/srvcore.h index 2fec3faf8..0483b0aff 100644 --- a/drivers/gpu/drm/img-rogue/srvcore.h +++ b/drivers/gpu/drm/img-rogue/srvcore.h @@ -72,6 +72,8 @@ DummyBW(IMG_UINT32 ui32DispatchTableEntry, IMG_UINT8 *psBridgeOut, CONNECTION_DATA *psConnection); +typedef PVRSRV_ERROR (*ServerResourceDestroyFunction)(IMG_HANDLE, IMG_HANDLE); + typedef IMG_INT (*BridgeWrapperFunction)(IMG_UINT32 ui32DispatchTableEntry, IMG_UINT8 *psBridgeIn, IMG_UINT8 *psBridgeOut, @@ -209,6 +211,17 @@ PVRSRV_ERROR PVRSRVFindProcessMemStatsKM(IMG_PID pid, IMG_BOOL bAllProcessStats, IMG_UINT32 *ui32MemoryStats); +static INLINE +PVRSRV_ERROR DestroyServerResource(const SHARED_DEV_CONNECTION hConnection, + IMG_HANDLE hEvent, + ServerResourceDestroyFunction pfnDestroyCall, + IMG_HANDLE hResource) +{ + PVR_UNREFERENCED_PARAMETER(hEvent); + + return pfnDestroyCall(GetBridgeHandle(hConnection), hResource); +} + #endif /* SRVCORE_H */ /****************************************************************************** diff --git a/drivers/gpu/drm/img-rogue/sync.c b/drivers/gpu/drm/img-rogue/sync.c index 43f5de477..36234ae5e 100644 --- a/drivers/gpu/drm/img-rogue/sync.c +++ b/drivers/gpu/drm/img-rogue/sync.c @@ -60,6 +60,9 @@ CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. #include "log2.h" #if defined(__KERNEL__) #include "pvrsrv.h" +#include "srvcore.h" +#else +#include "srvcore_intern.h" #endif @@ -184,7 +187,9 @@ FreeSyncPrimitiveBlock(SYNC_PRIM_BLOCK *psSyncBlk) DevmemReleaseCpuVirtAddr(psSyncBlk->hMemDesc); DevmemFree(psSyncBlk->hMemDesc); - BridgeFreeSyncPrimitiveBlock(GetBridgeHandle(psContext->hDevConnection), + (void) DestroyServerResource(psContext->hDevConnection, + NULL, + BridgeFreeSyncPrimitiveBlock, psSyncBlk->hServerSyncPrimBlock); OSFreeMem(psSyncBlk); } @@ -308,16 +313,19 @@ static void SyncPrimLocalFree(SYNC_PRIM *psSyncInt, IMG_BOOL bFreeFirstSyncPrim) #endif { PVRSRV_ERROR eError; - IMG_HANDLE hBridge = - GetBridgeHandle(psSyncInt->u.sLocal.psSyncBlock->psContext->hDevConnection); + SHARED_DEV_CONNECTION hDevConnection = + psSyncInt->u.sLocal.psSyncBlock->psContext->hDevConnection; - if (GetInfoPageDebugFlags(psSyncInt->u.sLocal.psSyncBlock->psContext->hDevConnection) & DEBUG_FEATURE_FULL_SYNC_TRACKING_ENABLED) + if (GetInfoPageDebugFlags(hDevConnection) & DEBUG_FEATURE_FULL_SYNC_TRACKING_ENABLED) { if (psSyncInt->u.sLocal.hRecord) { /* remove this sync record */ - eError = BridgeSyncRecordRemoveByHandle(hBridge, - psSyncInt->u.sLocal.hRecord); + eError = DestroyServerResource(hDevConnection, + NULL, + BridgeSyncRecordRemoveByHandle, + psSyncInt->u.sLocal.hRecord); + PVR_LOG_IF_ERROR(eError, "BridgeSyncRecordRemoveByHandle"); } } else @@ -325,7 +333,7 @@ static void SyncPrimLocalFree(SYNC_PRIM *psSyncInt, IMG_BOOL bFreeFirstSyncPrim) IMG_UINT32 ui32FWAddr = psSyncBlock->ui32FirmwareAddr + SyncPrimGetOffset(psSyncInt); - eError = BridgeSyncFreeEvent(hBridge, ui32FWAddr); + eError = BridgeSyncFreeEvent(GetBridgeHandle(hDevConnection), ui32FWAddr); PVR_LOG_IF_ERROR(eError, "BridgeSyncFreeEvent"); } #if defined(PVRSRV_ENABLE_SYNC_POISONING) diff --git a/drivers/gpu/drm/img-rogue/sync_checkpoint.c b/drivers/gpu/drm/img-rogue/sync_checkpoint.c index 64acda765..1bab1afee 100644 --- a/drivers/gpu/drm/img-rogue/sync_checkpoint.c +++ b/drivers/gpu/drm/img-rogue/sync_checkpoint.c @@ -65,7 +65,7 @@ CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. #include "rgxhwperf.h" #if defined(SUPPORT_VALIDATION) && defined(SUPPORT_SOC_TIMER) -#include "validation_soc.h" +#include "rgxsoctimer.h" #endif #if defined(PVRSRV_NEED_PVR_DPF) @@ -173,7 +173,7 @@ struct _SYNC_CHECKPOINT_CONTEXT_CTL_ POS_SPINLOCK hDeferredCleanupListLock; #if (SYNC_CHECKPOINT_POOL_SIZE > 0) - _SYNC_CHECKPOINT *psSyncCheckpointPool[SYNC_CHECKPOINT_POOL_SIZE]; + SYNC_CHECKPOINT *psSyncCheckpointPool[SYNC_CHECKPOINT_POOL_SIZE]; IMG_BOOL bSyncCheckpointPoolFull; IMG_BOOL bSyncCheckpointPoolValid; IMG_UINT32 ui32SyncCheckpointPoolCount; @@ -207,8 +207,8 @@ struct SYNC_CHECKPOINT_RECORD static PFN_SYNC_CHECKPOINT_STRUCT *g_psSyncCheckpointPfnStruct = NULL; #if (SYNC_CHECKPOINT_POOL_SIZE > 0) -static _SYNC_CHECKPOINT *_GetCheckpointFromPool(_SYNC_CHECKPOINT_CONTEXT *psContext); -static IMG_BOOL _PutCheckpointInPool(_SYNC_CHECKPOINT *psSyncCheckpoint); +static SYNC_CHECKPOINT *_GetCheckpointFromPool(_SYNC_CHECKPOINT_CONTEXT *psContext); +static IMG_BOOL _PutCheckpointInPool(SYNC_CHECKPOINT *psSyncCheckpoint); static IMG_UINT32 _CleanCheckpointPool(_SYNC_CHECKPOINT_CONTEXT *psContext); #endif @@ -224,7 +224,7 @@ static IMG_UINT32 gui32NumSyncCheckpointContexts = 0; #if defined(SUPPORT_RGX) static inline void RGXSRVHWPerfSyncCheckpointUFOIsSignalled(PVRSRV_RGXDEV_INFO *psDevInfo, - _SYNC_CHECKPOINT *psSyncCheckpointInt, IMG_UINT32 ui32FenceSyncFlags) + SYNC_CHECKPOINT *psSyncCheckpointInt, IMG_UINT32 ui32FenceSyncFlags) { if (RGXHWPerfHostIsEventEnabled(psDevInfo, RGX_HWPERF_HOST_UFO) && !(ui32FenceSyncFlags & PVRSRV_FENCE_FLAG_SUPPRESS_HWP_PKT)) @@ -255,7 +255,7 @@ static inline void RGXSRVHWPerfSyncCheckpointUFOIsSignalled(PVRSRV_RGXDEV_INFO * } static inline void RGXSRVHWPerfSyncCheckpointUFOUpdate(PVRSRV_RGXDEV_INFO *psDevInfo, - _SYNC_CHECKPOINT *psSyncCheckpointInt, IMG_UINT32 ui32FenceSyncFlags) + SYNC_CHECKPOINT *psSyncCheckpointInt, IMG_UINT32 ui32FenceSyncFlags) { if (RGXHWPerfHostIsEventEnabled(psDevInfo, RGX_HWPERF_HOST_UFO) && !(ui32FenceSyncFlags & PVRSRV_FENCE_FLAG_SUPPRESS_HWP_PKT)) @@ -297,8 +297,8 @@ static void _SyncCheckpointRecordListDeinit(PVRSRV_DEVICE_NODE *psDevNode); #if defined(PDUMP) static void MISRHandler_PdumpDeferredSyncSignalPoster(void *pvData); -static PVRSRV_ERROR _SyncCheckpointAllocPDump(PVRSRV_DEVICE_NODE *psDevNode, _SYNC_CHECKPOINT *psSyncCheckpoint); -static PVRSRV_ERROR _SyncCheckpointUpdatePDump(PPVRSRV_DEVICE_NODE psDevNode, _SYNC_CHECKPOINT *psSyncCheckpoint, IMG_UINT32 ui32Status, IMG_UINT32 ui32FenceSyncFlags); +static PVRSRV_ERROR _SyncCheckpointAllocPDump(PVRSRV_DEVICE_NODE *psDevNode, SYNC_CHECKPOINT *psSyncCheckpoint); +static PVRSRV_ERROR _SyncCheckpointUpdatePDump(PPVRSRV_DEVICE_NODE psDevNode, SYNC_CHECKPOINT *psSyncCheckpoint, IMG_UINT32 ui32Status, IMG_UINT32 ui32FenceSyncFlags); static PVRSRV_ERROR _SyncCheckpointPDumpTransition(void *pvData, PDUMP_TRANSITION_EVENT eEvent); #endif @@ -528,7 +528,7 @@ _SyncCheckpointBlockUnimport(RA_PERARENA_HANDLE hArena, SyncCheckpointContextUnref((PSYNC_CHECKPOINT_CONTEXT)psContext); } -static INLINE IMG_UINT32 _SyncCheckpointGetOffset(_SYNC_CHECKPOINT *psSyncInt) +static INLINE IMG_UINT32 _SyncCheckpointGetOffset(SYNC_CHECKPOINT *psSyncInt) { IMG_UINT64 ui64Temp; @@ -564,18 +564,6 @@ SyncCheckpointRegisterFunctions(PFN_SYNC_CHECKPOINT_STRUCT *psSyncCheckpointPfns return PVRSRV_OK; } -#if defined(SUPPORT_NATIVE_FENCE_SYNC) -struct _PVRSRV_DEVICE_NODE_ *SyncCheckpointGetAssociatedDevice(PSYNC_CHECKPOINT_CONTEXT psSyncCheckpointContext) -{ - return ((_SYNC_CHECKPOINT_CONTEXT*)psSyncCheckpointContext)->psDevNode; -} -#else -PPVRSRV_DEVICE_NODE SyncCheckpointGetAssociatedDevice(PSYNC_CHECKPOINT_CONTEXT psSyncCheckpointContext) -{ - return ((_SYNC_CHECKPOINT_CONTEXT*)psSyncCheckpointContext)->psDevNode; -} -#endif - PVRSRV_ERROR SyncCheckpointResolveFence(PSYNC_CHECKPOINT_CONTEXT psSyncCheckpointContext, PVRSRV_FENCE hFence, IMG_UINT32 *pui32NumSyncCheckpoints, @@ -586,7 +574,7 @@ SyncCheckpointResolveFence(PSYNC_CHECKPOINT_CONTEXT psSyncCheckpointContext, PVRSRV_ERROR eError = PVRSRV_OK; IMG_UINT32 i; #if defined(PDUMP) - _SYNC_CHECKPOINT *psSyncCheckpoint = NULL; + SYNC_CHECKPOINT *psSyncCheckpoint = NULL; #endif if (unlikely(!g_psSyncCheckpointPfnStruct || !g_psSyncCheckpointPfnStruct->pfnFenceResolve)) @@ -620,7 +608,7 @@ SyncCheckpointResolveFence(PSYNC_CHECKPOINT_CONTEXT psSyncCheckpointContext, { for (i = 0; i < *pui32NumSyncCheckpoints; i++) { - psSyncCheckpoint = (_SYNC_CHECKPOINT *)(*papsSyncCheckpoints)[i]; + psSyncCheckpoint = (SYNC_CHECKPOINT *)(*papsSyncCheckpoints)[i]; psSyncCheckpoint->ui32PDumpFlags = ui32PDumpFlags; } } @@ -698,6 +686,7 @@ SyncCheckpointCreateFence(PVRSRV_DEVICE_NODE *psDevNode, else { eError = g_psSyncCheckpointPfnStruct->pfnFenceCreate( + psDevNode, pszFenceName, hTimeline, psSyncCheckpointContext, @@ -736,7 +725,7 @@ SyncCheckpointCreateFence(PVRSRV_DEVICE_NODE *psDevNode, #if defined(PDUMP) if (eError == PVRSRV_OK) { - _SYNC_CHECKPOINT *psSyncCheckpoint = (_SYNC_CHECKPOINT*)(*psNewSyncCheckpoint); + SYNC_CHECKPOINT *psSyncCheckpoint = (SYNC_CHECKPOINT*)(*psNewSyncCheckpoint); if (psSyncCheckpoint) { psSyncCheckpoint->ui32PDumpFlags = ui32PDumpFlags; @@ -1006,7 +995,7 @@ fail_alloc: /* Poisons and frees the checkpoint * Decrements context refcount. */ -static void _FreeSyncCheckpoint(_SYNC_CHECKPOINT *psSyncCheckpoint) +static void _FreeSyncCheckpoint(SYNC_CHECKPOINT *psSyncCheckpoint) { _SYNC_CHECKPOINT_CONTEXT *psContext = psSyncCheckpoint->psSyncCheckpointBlock->psContext; @@ -1085,7 +1074,7 @@ PVRSRV_ERROR SyncCheckpointContextDestroy(PSYNC_CHECKPOINT_CONTEXT psSyncCheckpo dllist_foreach_node(&psDevNode->sSyncCheckpointSyncsList, psNode, psNext) { - _SYNC_CHECKPOINT *psSyncCheckpoint = IMG_CONTAINER_OF(psNode, _SYNC_CHECKPOINT, sListNode); + SYNC_CHECKPOINT *psSyncCheckpoint = IMG_CONTAINER_OF(psNode, SYNC_CHECKPOINT, sListNode); bool bDeferredFree = dllist_node_is_in_list(&psSyncCheckpoint->sDeferredFreeListNode); /* Line below avoids build error in release builds (where PVR_DPF is not defined) */ @@ -1143,7 +1132,7 @@ SyncCheckpointAlloc(PSYNC_CHECKPOINT_CONTEXT psSyncContext, const IMG_CHAR *pszCheckpointName, PSYNC_CHECKPOINT *ppsSyncCheckpoint) { - _SYNC_CHECKPOINT *psNewSyncCheckpoint = NULL; + SYNC_CHECKPOINT *psNewSyncCheckpoint = NULL; _SYNC_CHECKPOINT_CONTEXT *psSyncContextInt = (_SYNC_CHECKPOINT_CONTEXT*)psSyncContext; PVRSRV_DEVICE_NODE *psDevNode; PVRSRV_ERROR eError; @@ -1316,7 +1305,7 @@ fail_alloc: return eError; } -static void SyncCheckpointUnref(_SYNC_CHECKPOINT *psSyncCheckpointInt) +static void SyncCheckpointUnref(SYNC_CHECKPOINT *psSyncCheckpointInt) { _SYNC_CHECKPOINT_CONTEXT *psContext; PVRSRV_DEVICE_NODE *psDevNode; @@ -1435,7 +1424,7 @@ static void SyncCheckpointUnref(_SYNC_CHECKPOINT *psSyncCheckpointInt) void SyncCheckpointFree(PSYNC_CHECKPOINT psSyncCheckpoint) { - _SYNC_CHECKPOINT *psSyncCheckpointInt = (_SYNC_CHECKPOINT*)psSyncCheckpoint; + SYNC_CHECKPOINT *psSyncCheckpointInt = (SYNC_CHECKPOINT*)psSyncCheckpoint; PVR_LOG_RETURN_VOID_IF_FALSE((psSyncCheckpoint != NULL), "psSyncCheckpoint invalid"); @@ -1454,7 +1443,7 @@ void SyncCheckpointFree(PSYNC_CHECKPOINT psSyncCheckpoint) void SyncCheckpointSignal(PSYNC_CHECKPOINT psSyncCheckpoint, IMG_UINT32 ui32FenceSyncFlags) { - _SYNC_CHECKPOINT *psSyncCheckpointInt = (_SYNC_CHECKPOINT*)psSyncCheckpoint; + SYNC_CHECKPOINT *psSyncCheckpointInt = (SYNC_CHECKPOINT*)psSyncCheckpoint; PVR_LOG_IF_FALSE((psSyncCheckpoint != NULL), "psSyncCheckpoint invalid"); @@ -1492,7 +1481,7 @@ SyncCheckpointSignal(PSYNC_CHECKPOINT psSyncCheckpoint, IMG_UINT32 ui32FenceSync void SyncCheckpointSignalNoHW(PSYNC_CHECKPOINT psSyncCheckpoint) { - _SYNC_CHECKPOINT *psSyncCheckpointInt = (_SYNC_CHECKPOINT*)psSyncCheckpoint; + SYNC_CHECKPOINT *psSyncCheckpointInt = (SYNC_CHECKPOINT*)psSyncCheckpoint; PVR_LOG_IF_FALSE((psSyncCheckpoint != NULL), "psSyncCheckpoint invalid"); @@ -1528,7 +1517,7 @@ SyncCheckpointSignalNoHW(PSYNC_CHECKPOINT psSyncCheckpoint) void SyncCheckpointError(PSYNC_CHECKPOINT psSyncCheckpoint, IMG_UINT32 ui32FenceSyncFlags) { - _SYNC_CHECKPOINT *psSyncCheckpointInt = (_SYNC_CHECKPOINT*)psSyncCheckpoint; + SYNC_CHECKPOINT *psSyncCheckpointInt = (SYNC_CHECKPOINT*)psSyncCheckpoint; PVR_LOG_IF_FALSE((psSyncCheckpoint != NULL), "psSyncCheckpoint invalid"); @@ -1566,7 +1555,7 @@ SyncCheckpointError(PSYNC_CHECKPOINT psSyncCheckpoint, IMG_UINT32 ui32FenceSyncF IMG_BOOL SyncCheckpointIsSignalled(PSYNC_CHECKPOINT psSyncCheckpoint, IMG_UINT32 ui32FenceSyncFlags) { IMG_BOOL bRet = IMG_FALSE; - _SYNC_CHECKPOINT *psSyncCheckpointInt = (_SYNC_CHECKPOINT*)psSyncCheckpoint; + SYNC_CHECKPOINT *psSyncCheckpointInt = (SYNC_CHECKPOINT*)psSyncCheckpoint; PVR_LOG_IF_FALSE((psSyncCheckpoint != NULL), "psSyncCheckpoint invalid"); @@ -1595,7 +1584,7 @@ IMG_BOOL SyncCheckpointIsErrored(PSYNC_CHECKPOINT psSyncCheckpoint, IMG_UINT32 ui32FenceSyncFlags) { IMG_BOOL bRet = IMG_FALSE; - _SYNC_CHECKPOINT *psSyncCheckpointInt = (_SYNC_CHECKPOINT*)psSyncCheckpoint; + SYNC_CHECKPOINT *psSyncCheckpointInt = (SYNC_CHECKPOINT*)psSyncCheckpoint; PVR_LOG_IF_FALSE((psSyncCheckpoint != NULL), "psSyncCheckpoint invalid"); @@ -1622,7 +1611,7 @@ SyncCheckpointIsErrored(PSYNC_CHECKPOINT psSyncCheckpoint, IMG_UINT32 ui32FenceS const IMG_CHAR * SyncCheckpointGetStateString(PSYNC_CHECKPOINT psSyncCheckpoint) { - _SYNC_CHECKPOINT *psSyncCheckpointInt = (_SYNC_CHECKPOINT*)psSyncCheckpoint; + SYNC_CHECKPOINT *psSyncCheckpointInt = (SYNC_CHECKPOINT*)psSyncCheckpoint; PVR_LOG_RETURN_IF_FALSE((psSyncCheckpoint != NULL), "psSyncCheckpoint invalid", "Null"); @@ -1645,7 +1634,7 @@ PVRSRV_ERROR SyncCheckpointTakeRef(PSYNC_CHECKPOINT psSyncCheckpoint) { PVRSRV_ERROR eRet = PVRSRV_OK; - _SYNC_CHECKPOINT *psSyncCheckpointInt = (_SYNC_CHECKPOINT*)psSyncCheckpoint; + SYNC_CHECKPOINT *psSyncCheckpointInt = (SYNC_CHECKPOINT*)psSyncCheckpoint; PVR_LOG_RETURN_IF_INVALID_PARAM(psSyncCheckpoint, "psSyncCheckpoint"); @@ -1666,7 +1655,7 @@ PVRSRV_ERROR SyncCheckpointDropRef(PSYNC_CHECKPOINT psSyncCheckpoint) { PVRSRV_ERROR eRet = PVRSRV_OK; - _SYNC_CHECKPOINT *psSyncCheckpointInt = (_SYNC_CHECKPOINT*)psSyncCheckpoint; + SYNC_CHECKPOINT *psSyncCheckpointInt = (SYNC_CHECKPOINT*)psSyncCheckpoint; PVR_LOG_RETURN_IF_INVALID_PARAM(psSyncCheckpoint, "psSyncCheckpoint"); @@ -1686,7 +1675,7 @@ SyncCheckpointDropRef(PSYNC_CHECKPOINT psSyncCheckpoint) void SyncCheckpointCCBEnqueued(PSYNC_CHECKPOINT psSyncCheckpoint) { - _SYNC_CHECKPOINT *psSyncCheckpointInt = (_SYNC_CHECKPOINT*)psSyncCheckpoint; + SYNC_CHECKPOINT *psSyncCheckpointInt = (SYNC_CHECKPOINT*)psSyncCheckpoint; PVR_LOG_RETURN_VOID_IF_FALSE(psSyncCheckpoint != NULL, "psSyncCheckpoint"); @@ -1709,7 +1698,7 @@ SyncCheckpointCCBEnqueued(PSYNC_CHECKPOINT psSyncCheckpoint) PRGXFWIF_UFO_ADDR* SyncCheckpointGetRGXFWIFUFOAddr(PSYNC_CHECKPOINT psSyncCheckpoint) { - _SYNC_CHECKPOINT *psSyncCheckpointInt = (_SYNC_CHECKPOINT*)psSyncCheckpoint; + SYNC_CHECKPOINT *psSyncCheckpointInt = (SYNC_CHECKPOINT*)psSyncCheckpoint; PVR_LOG_GOTO_IF_FALSE((psSyncCheckpoint != NULL), "psSyncCheckpoint invalid", invalid_chkpt); @@ -1736,7 +1725,7 @@ invalid_chkpt: IMG_UINT32 SyncCheckpointGetFirmwareAddr(PSYNC_CHECKPOINT psSyncCheckpoint) { - _SYNC_CHECKPOINT *psSyncCheckpointInt = (_SYNC_CHECKPOINT*)psSyncCheckpoint; + SYNC_CHECKPOINT *psSyncCheckpointInt = (SYNC_CHECKPOINT*)psSyncCheckpoint; IMG_UINT32 ui32Ret = 0; PVR_LOG_GOTO_IF_FALSE((psSyncCheckpoint != NULL), "psSyncCheckpoint invalid", invalid_chkpt); @@ -1764,7 +1753,7 @@ invalid_chkpt: IMG_UINT32 SyncCheckpointGetId(PSYNC_CHECKPOINT psSyncCheckpoint) { - _SYNC_CHECKPOINT *psSyncCheckpointInt = (_SYNC_CHECKPOINT*)psSyncCheckpoint; + SYNC_CHECKPOINT *psSyncCheckpointInt = (SYNC_CHECKPOINT*)psSyncCheckpoint; IMG_UINT32 ui32Ret = 0; PVR_LOG_GOTO_IF_FALSE((psSyncCheckpoint != NULL), "psSyncCheckpoint invalid", invalid_chkpt); @@ -1798,7 +1787,7 @@ invalid_chkpt: PVRSRV_TIMELINE SyncCheckpointGetTimeline(PSYNC_CHECKPOINT psSyncCheckpoint) { - _SYNC_CHECKPOINT *psSyncCheckpointInt = (_SYNC_CHECKPOINT*)psSyncCheckpoint; + SYNC_CHECKPOINT *psSyncCheckpointInt = (SYNC_CHECKPOINT*)psSyncCheckpoint; PVRSRV_TIMELINE i32Ret = PVRSRV_NO_TIMELINE; PVR_LOG_GOTO_IF_FALSE((psSyncCheckpoint != NULL), "psSyncCheckpoint invalid", invalid_chkpt); @@ -1817,7 +1806,7 @@ invalid_chkpt: IMG_UINT32 SyncCheckpointGetEnqueuedCount(PSYNC_CHECKPOINT psSyncCheckpoint) { - _SYNC_CHECKPOINT *psSyncCheckpointInt = (_SYNC_CHECKPOINT*)psSyncCheckpoint; + SYNC_CHECKPOINT *psSyncCheckpointInt = (SYNC_CHECKPOINT*)psSyncCheckpoint; PVR_LOG_RETURN_IF_FALSE(psSyncCheckpoint != NULL, "psSyncCheckpoint invalid", 0); return OSAtomicRead(&psSyncCheckpointInt->hEnqueuedCCBCount); @@ -1826,7 +1815,7 @@ SyncCheckpointGetEnqueuedCount(PSYNC_CHECKPOINT psSyncCheckpoint) IMG_UINT32 SyncCheckpointGetReferenceCount(PSYNC_CHECKPOINT psSyncCheckpoint) { - _SYNC_CHECKPOINT *psSyncCheckpointInt = (_SYNC_CHECKPOINT*)psSyncCheckpoint; + SYNC_CHECKPOINT *psSyncCheckpointInt = (SYNC_CHECKPOINT*)psSyncCheckpoint; PVR_LOG_RETURN_IF_FALSE(psSyncCheckpoint != NULL, "psSyncCheckpoint invalid", 0); return OSAtomicRead(&psSyncCheckpointInt->hRefCount); @@ -1835,7 +1824,7 @@ SyncCheckpointGetReferenceCount(PSYNC_CHECKPOINT psSyncCheckpoint) IMG_PID SyncCheckpointGetCreator(PSYNC_CHECKPOINT psSyncCheckpoint) { - _SYNC_CHECKPOINT *psSyncCheckpointInt = (_SYNC_CHECKPOINT*)psSyncCheckpoint; + SYNC_CHECKPOINT *psSyncCheckpointInt = (SYNC_CHECKPOINT*)psSyncCheckpoint; PVR_LOG_RETURN_IF_FALSE(psSyncCheckpoint != NULL, "psSyncCheckpoint invalid", 0); return psSyncCheckpointInt->uiProcess; @@ -1844,7 +1833,7 @@ SyncCheckpointGetCreator(PSYNC_CHECKPOINT psSyncCheckpoint) IMG_UINT32 SyncCheckpointStateFromUFO(PPVRSRV_DEVICE_NODE psDevNode, IMG_UINT32 ui32FwAddr) { - _SYNC_CHECKPOINT *psSyncCheckpointInt; + SYNC_CHECKPOINT *psSyncCheckpointInt; PDLLIST_NODE psNode, psNext; IMG_UINT32 ui32State = 0; OS_SPINLOCK_FLAGS uiFlags; @@ -1852,7 +1841,7 @@ IMG_UINT32 SyncCheckpointStateFromUFO(PPVRSRV_DEVICE_NODE psDevNode, OSSpinLockAcquire(psDevNode->hSyncCheckpointListLock, uiFlags); dllist_foreach_node(&psDevNode->sSyncCheckpointSyncsList, psNode, psNext) { - psSyncCheckpointInt = IMG_CONTAINER_OF(psNode, _SYNC_CHECKPOINT, sListNode); + psSyncCheckpointInt = IMG_CONTAINER_OF(psNode, SYNC_CHECKPOINT, sListNode); if (ui32FwAddr == SyncCheckpointGetFirmwareAddr((PSYNC_CHECKPOINT)psSyncCheckpointInt)) { ui32State = psSyncCheckpointInt->psSyncCheckpointFwObj->ui32State; @@ -1866,7 +1855,7 @@ IMG_UINT32 SyncCheckpointStateFromUFO(PPVRSRV_DEVICE_NODE psDevNode, void SyncCheckpointErrorFromUFO(PPVRSRV_DEVICE_NODE psDevNode, IMG_UINT32 ui32FwAddr) { - _SYNC_CHECKPOINT *psSyncCheckpointInt; + SYNC_CHECKPOINT *psSyncCheckpointInt; PDLLIST_NODE psNode, psNext; OS_SPINLOCK_FLAGS uiFlags; @@ -1880,7 +1869,7 @@ void SyncCheckpointErrorFromUFO(PPVRSRV_DEVICE_NODE psDevNode, OSSpinLockAcquire(psDevNode->hSyncCheckpointListLock, uiFlags); dllist_foreach_node(&psDevNode->sSyncCheckpointSyncsList, psNode, psNext) { - psSyncCheckpointInt = IMG_CONTAINER_OF(psNode, _SYNC_CHECKPOINT, sListNode); + psSyncCheckpointInt = IMG_CONTAINER_OF(psNode, SYNC_CHECKPOINT, sListNode); if (ui32FwAddr == SyncCheckpointGetFirmwareAddr((PSYNC_CHECKPOINT)psSyncCheckpointInt)) { #if (ENABLE_SYNC_CHECKPOINT_UFO_DEBUG == 1) @@ -1907,14 +1896,14 @@ void SyncCheckpointRollbackFromUFO(PPVRSRV_DEVICE_NODE psDevNode, IMG_UINT32 ui3 #endif #if !defined(NO_HARDWARE) { - _SYNC_CHECKPOINT *psSyncCheckpointInt = NULL; + SYNC_CHECKPOINT *psSyncCheckpointInt = NULL; PDLLIST_NODE psNode = NULL, psNext = NULL; OS_SPINLOCK_FLAGS uiFlags; OSSpinLockAcquire(psDevNode->hSyncCheckpointListLock, uiFlags); dllist_foreach_node(&psDevNode->sSyncCheckpointSyncsList, psNode, psNext) { - psSyncCheckpointInt = IMG_CONTAINER_OF(psNode, _SYNC_CHECKPOINT, sListNode); + psSyncCheckpointInt = IMG_CONTAINER_OF(psNode, SYNC_CHECKPOINT, sListNode); if (ui32FwAddr == SyncCheckpointGetFirmwareAddr((PSYNC_CHECKPOINT)psSyncCheckpointInt)) { #if ((ENABLE_SYNC_CHECKPOINT_UFO_DEBUG == 1)) || (ENABLE_SYNC_CHECKPOINT_ENQ_AND_SIGNAL_DEBUG == 1) @@ -1938,7 +1927,7 @@ static void _SyncCheckpointState(PDLLIST_NODE psNode, DUMPDEBUG_PRINTF_FUNC *pfnDumpDebugPrintf, void *pvDumpDebugFile) { - _SYNC_CHECKPOINT *psSyncCheckpoint = IMG_CONTAINER_OF(psNode, _SYNC_CHECKPOINT, sListNode); + SYNC_CHECKPOINT *psSyncCheckpoint = IMG_CONTAINER_OF(psNode, SYNC_CHECKPOINT, sListNode); if (psSyncCheckpoint->psSyncCheckpointFwObj->ui32State == PVRSRV_SYNC_CHECKPOINT_ACTIVE) { @@ -2299,7 +2288,7 @@ static void _SyncCheckpointRecordPrint(struct SYNC_CHECKPOINT_RECORD *psSyncChec DUMPDEBUG_PRINTF_FUNC *pfnDumpDebugPrintf, void *pvDumpDebugFile) { - _SYNC_CHECKPOINT *psSyncCheckpoint = (_SYNC_CHECKPOINT *)psSyncCheckpointRec->pSyncCheckpt; + SYNC_CHECKPOINT *psSyncCheckpoint = (SYNC_CHECKPOINT *)psSyncCheckpointRec->pSyncCheckpt; SYNC_CHECKPOINT_BLOCK *psSyncCheckpointBlock = psSyncCheckpointRec->psSyncCheckpointBlock; IMG_UINT64 ui64DeltaS; IMG_UINT32 ui32DeltaF; @@ -2460,7 +2449,7 @@ static void _SyncCheckpointRecordListDeinit(PVRSRV_DEVICE_NODE *psDevNode) #if defined(PDUMP) static PVRSRV_ERROR -_SyncCheckpointAllocPDump(PVRSRV_DEVICE_NODE *psDevNode, _SYNC_CHECKPOINT *psSyncCheckpoint) +_SyncCheckpointAllocPDump(PVRSRV_DEVICE_NODE *psDevNode, SYNC_CHECKPOINT *psSyncCheckpoint) { PDUMPCOMMENTWITHFLAGS(psDevNode, PDUMP_FLAGS_CONTINUOUS, "Allocated Sync Checkpoint %s (ID:%d, TL:%d, FirmwareVAddr = 0x%08x)", @@ -2477,7 +2466,7 @@ _SyncCheckpointAllocPDump(PVRSRV_DEVICE_NODE *psDevNode, _SYNC_CHECKPOINT *psSyn } static PVRSRV_ERROR -_SyncCheckpointUpdatePDump(PPVRSRV_DEVICE_NODE psDevNode, _SYNC_CHECKPOINT *psSyncCheckpoint, IMG_UINT32 ui32Status, IMG_UINT32 ui32FenceSyncFlags) +_SyncCheckpointUpdatePDump(PPVRSRV_DEVICE_NODE psDevNode, SYNC_CHECKPOINT *psSyncCheckpoint, IMG_UINT32 ui32Status, IMG_UINT32 ui32FenceSyncFlags) { IMG_BOOL bSleepAllowed = (ui32FenceSyncFlags & PVRSRV_FENCE_FLAG_CTX_ATOMIC) ? IMG_FALSE : IMG_TRUE; PVRSRV_RGXDEV_INFO *psDevInfo; @@ -2591,7 +2580,7 @@ PVRSRV_ERROR PVRSRVSyncCheckpointSignalledPDumpPolKM(PVRSRV_FENCE hFence) { PVRSRV_ERROR eError; PSYNC_CHECKPOINT *apsCheckpoints = NULL; - _SYNC_CHECKPOINT *psSyncCheckpoint = NULL; + SYNC_CHECKPOINT *psSyncCheckpoint = NULL; IMG_UINT32 i, uiNumCheckpoints = 0; #if defined(SUPPORT_VALIDATION) && defined(SUPPORT_SOC_TIMER) && defined(NO_HARDWARE) && defined(PDUMP) PVRSRV_RGXDEV_INFO *psDevInfo; @@ -2611,13 +2600,13 @@ PVRSRV_ERROR PVRSRVSyncCheckpointSignalledPDumpPolKM(PVRSRV_FENCE hFence) if (uiNumCheckpoints) { /* Flushing deferred fence signals to pdump */ - psSyncCheckpoint = (_SYNC_CHECKPOINT *)apsCheckpoints[0]; + psSyncCheckpoint = (SYNC_CHECKPOINT *)apsCheckpoints[0]; MISRHandler_PdumpDeferredSyncSignalPoster(psSyncCheckpoint->psSyncCheckpointBlock->psDevNode); } for (i=0; i < uiNumCheckpoints; i++) { - psSyncCheckpoint = (_SYNC_CHECKPOINT *)apsCheckpoints[i]; + psSyncCheckpoint = (SYNC_CHECKPOINT *)apsCheckpoints[i]; if (psSyncCheckpoint->psSyncCheckpointFwObj->ui32State == PVRSRV_SYNC_CHECKPOINT_SIGNALLED) { PDUMPCOMMENTWITHFLAGS(psSyncCheckpoint->psSyncCheckpointBlock->psDevNode, @@ -2640,11 +2629,11 @@ PVRSRV_ERROR PVRSRVSyncCheckpointSignalledPDumpPolKM(PVRSRV_FENCE hFence) /* Sampling of USC timers can only be done after synchronisation for a 3D kick is over */ if (uiNumCheckpoints) { - psSyncCheckpoint = (_SYNC_CHECKPOINT *)apsCheckpoints[0]; + psSyncCheckpoint = (SYNC_CHECKPOINT *)apsCheckpoints[0]; psDevInfo = psSyncCheckpoint->psSyncCheckpointBlock->psDevNode->pvDevice; if (psDevInfo->psRGXFWIfFwSysData->ui32ConfigFlags & RGXFWIF_INICFG_VALIDATE_SOCUSC_TIMER) { - PVRSRVValidateSOCUSCTimer(psDevInfo, PDUMP_CONT, 0, 0, NULL); + RGXValidateSOCUSCTimer(psDevInfo, PDUMP_CONT, 0, 0, NULL); } } #endif @@ -2719,8 +2708,8 @@ static void _CheckDeferredCleanupList(_SYNC_CHECKPOINT_CONTEXT *psContext) dllist_foreach_node(&psCtxCtl->sDeferredCleanupListHead, psNode, psNext) { - _SYNC_CHECKPOINT *psSyncCheckpointInt = - IMG_CONTAINER_OF(psNode, _SYNC_CHECKPOINT, sDeferredFreeListNode); + SYNC_CHECKPOINT *psSyncCheckpointInt = + IMG_CONTAINER_OF(psNode, SYNC_CHECKPOINT, sDeferredFreeListNode); if (psSyncCheckpointInt->psSyncCheckpointFwObj->ui32FwRefCount == (IMG_UINT32)(OSAtomicRead(&psSyncCheckpointInt->hEnqueuedCCBCount))) @@ -2756,8 +2745,8 @@ static void _CheckDeferredCleanupList(_SYNC_CHECKPOINT_CONTEXT *psContext) OSSpinLockRelease(psCtxCtl->hDeferredCleanupListLock, uiFlags); dllist_foreach_node(&sCleanupList, psNode, psNext) { - _SYNC_CHECKPOINT *psSyncCheckpointInt = - IMG_CONTAINER_OF(psNode, _SYNC_CHECKPOINT, sDeferredFreeListNode); + SYNC_CHECKPOINT *psSyncCheckpointInt = + IMG_CONTAINER_OF(psNode, SYNC_CHECKPOINT, sDeferredFreeListNode); /* Remove the sync checkpoint from the global list */ OSSpinLockAcquire(psDevNode->hSyncCheckpointListLock, uiFlags); @@ -2801,10 +2790,10 @@ static void _CheckDeferredCleanupList(_SYNC_CHECKPOINT_CONTEXT *psContext) } #if (SYNC_CHECKPOINT_POOL_SIZE > 0) -static _SYNC_CHECKPOINT *_GetCheckpointFromPool(_SYNC_CHECKPOINT_CONTEXT *psContext) +static SYNC_CHECKPOINT *_GetCheckpointFromPool(_SYNC_CHECKPOINT_CONTEXT *psContext) { _SYNC_CHECKPOINT_CONTEXT_CTL *const psCtxCtl = psContext->psContextCtl; - _SYNC_CHECKPOINT *psSyncCheckpoint = NULL; + SYNC_CHECKPOINT *psSyncCheckpoint = NULL; OS_SPINLOCK_FLAGS uiFlags; /* Acquire sync checkpoint pool lock */ @@ -2841,7 +2830,7 @@ static _SYNC_CHECKPOINT *_GetCheckpointFromPool(_SYNC_CHECKPOINT_CONTEXT *psCont return psSyncCheckpoint; } -static IMG_BOOL _PutCheckpointInPool(_SYNC_CHECKPOINT *psSyncCheckpoint) +static IMG_BOOL _PutCheckpointInPool(SYNC_CHECKPOINT *psSyncCheckpoint) { _SYNC_CHECKPOINT_CONTEXT *psContext = psSyncCheckpoint->psSyncCheckpointBlock->psContext; _SYNC_CHECKPOINT_CONTEXT_CTL *const psCtxCtl = psContext->psContextCtl; @@ -2885,7 +2874,7 @@ static IMG_BOOL _PutCheckpointInPool(_SYNC_CHECKPOINT *psSyncCheckpoint) static IMG_UINT32 _CleanCheckpointPool(_SYNC_CHECKPOINT_CONTEXT *psContext) { _SYNC_CHECKPOINT_CONTEXT_CTL *const psCtxCtl = psContext->psContextCtl; - _SYNC_CHECKPOINT *psCheckpoint = NULL; + SYNC_CHECKPOINT *psCheckpoint = NULL; DECLARE_DLLIST(sCleanupList); DLLIST_NODE *psThis, *psNext; OS_SPINLOCK_FLAGS uiFlags; @@ -2942,7 +2931,7 @@ static IMG_UINT32 _CleanCheckpointPool(_SYNC_CHECKPOINT_CONTEXT *psContext) dllist_foreach_node(&sCleanupList, psThis, psNext) { - psCheckpoint = IMG_CONTAINER_OF(psThis, _SYNC_CHECKPOINT, sListNode); + psCheckpoint = IMG_CONTAINER_OF(psThis, SYNC_CHECKPOINT, sListNode); #if (ENABLE_SYNC_CHECKPOINT_POOL_DEBUG == 1) if (psCheckpoint->ui32ValidationCheck != SYNC_CHECKPOINT_PATTERN_IN_POOL) diff --git a/drivers/gpu/drm/img-rogue/sync_checkpoint.h b/drivers/gpu/drm/img-rogue/sync_checkpoint.h index 9ca79cfd9..33c26f420 100644 --- a/drivers/gpu/drm/img-rogue/sync_checkpoint.h +++ b/drivers/gpu/drm/img-rogue/sync_checkpoint.h @@ -56,9 +56,9 @@ CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. #ifndef CHECKPOINT_TYPES #define CHECKPOINT_TYPES -typedef struct _SYNC_CHECKPOINT_CONTEXT *PSYNC_CHECKPOINT_CONTEXT; +typedef struct SYNC_CHECKPOINT_CONTEXT_TAG *PSYNC_CHECKPOINT_CONTEXT; -typedef struct _SYNC_CHECKPOINT *PSYNC_CHECKPOINT; +typedef struct SYNC_CHECKPOINT_TAG *PSYNC_CHECKPOINT; #endif /* definitions for functions to be implemented by OS-specific sync - the OS-specific sync code @@ -71,7 +71,8 @@ typedef PVRSRV_ERROR (*PFN_SYNC_CHECKPOINT_FENCE_RESOLVE_FN)(PSYNC_CHECKPOINT_CO IMG_UINT32 *nr_checkpoints, PSYNC_CHECKPOINT **checkpoint_handles, IMG_UINT64 *pui64FenceUID); -typedef PVRSRV_ERROR (*PFN_SYNC_CHECKPOINT_FENCE_CREATE_FN)(const IMG_CHAR *fence_name, +typedef PVRSRV_ERROR (*PFN_SYNC_CHECKPOINT_FENCE_CREATE_FN)(PPVRSRV_DEVICE_NODE device, + const IMG_CHAR *fence_name, PVRSRV_TIMELINE timeline, PSYNC_CHECKPOINT_CONTEXT psSyncCheckpointContext, PVRSRV_FENCE *new_fence, diff --git a/drivers/gpu/drm/img-rogue/sync_checkpoint_external.h b/drivers/gpu/drm/img-rogue/sync_checkpoint_external.h index 399e38084..19b5011aa 100644 --- a/drivers/gpu/drm/img-rogue/sync_checkpoint_external.h +++ b/drivers/gpu/drm/img-rogue/sync_checkpoint_external.h @@ -49,9 +49,9 @@ CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. #ifndef CHECKPOINT_TYPES #define CHECKPOINT_TYPES -typedef struct _SYNC_CHECKPOINT_CONTEXT *PSYNC_CHECKPOINT_CONTEXT; +typedef struct SYNC_CHECKPOINT_CONTEXT_TAG *PSYNC_CHECKPOINT_CONTEXT; -typedef struct _SYNC_CHECKPOINT *PSYNC_CHECKPOINT; +typedef struct SYNC_CHECKPOINT_TAG *PSYNC_CHECKPOINT; #endif /* PVRSRV_SYNC_CHECKPOINT states. @@ -68,7 +68,7 @@ typedef IMG_UINT32 PVRSRV_SYNC_CHECKPOINT_STATE; #define PVRSRV_SYNC_CHECKPOINT_ERRORED 0xeffU /*!< checkpoint has been errored */ -#define PVRSRV_UFO_IS_SYNC_CHECKPOINT_FWADDR(fwaddr) ((fwaddr) & 0x1U) +#define PVRSRV_UFO_IS_SYNC_CHECKPOINT_FWADDR(fwaddr) (((fwaddr) & 0x1U) != 0U) #define PVRSRV_UFO_IS_SYNC_CHECKPOINT(ufoptr) (PVRSRV_UFO_IS_SYNC_CHECKPOINT_FWADDR((ufoptr)->puiAddrUFO.ui32Addr)) /* Maximum number of sync checkpoints the firmware supports in one fence */ diff --git a/drivers/gpu/drm/img-rogue/sync_checkpoint_internal.h b/drivers/gpu/drm/img-rogue/sync_checkpoint_internal.h index 9371942c0..ce1784741 100644 --- a/drivers/gpu/drm/img-rogue/sync_checkpoint_internal.h +++ b/drivers/gpu/drm/img-rogue/sync_checkpoint_internal.h @@ -64,7 +64,7 @@ struct SYNC_CHECKPOINT_RECORD; typedef struct _SYNC_CHECKPOINT_CONTEXT_CTL_ _SYNC_CHECKPOINT_CONTEXT_CTL, *_PSYNC_CHECKPOINT_CONTEXT_CTL; -typedef struct _SYNC_CHECKPOINT_CONTEXT_ +typedef struct SYNC_CHECKPOINT_CONTEXT_TAG { PPVRSRV_DEVICE_NODE psDevNode; IMG_CHAR azName[PVRSRV_SYNC_NAME_LENGTH]; /*!< Name of the RA */ @@ -100,7 +100,7 @@ typedef struct _SYNC_CHECKPOINT_BLOCK_ typedef struct SYNC_CHECKPOINT_RECORD* PSYNC_CHECKPOINT_RECORD_HANDLE; -typedef struct _SYNC_CHECKPOINT_ +typedef struct SYNC_CHECKPOINT_TAG { //_SYNC_CHECKPOINT_CONTEXT *psContext; /*!< pointer to the parent context of this checkpoint */ /* A sync checkpoint is assigned a unique ID, to avoid any confusion should @@ -122,12 +122,12 @@ typedef struct _SYNC_CHECKPOINT_ DLLIST_NODE sDeferredFreeListNode; /*!< List node for the deferred free sync chkpt list */ IMG_UINT32 ui32FWAddr; /*!< FWAddr stored at sync checkpoint alloc time */ PDUMP_FLAGS_T ui32PDumpFlags; /*!< Pdump Capture mode to be used for POL*/ -} _SYNC_CHECKPOINT; +} SYNC_CHECKPOINT; typedef struct _SYNC_CHECKPOINT_SIGNAL_ { - _SYNC_CHECKPOINT asSyncCheckpoint; /*!< Store sync checkpt for deferred signal */ + SYNC_CHECKPOINT asSyncCheckpoint; /*!< Store sync checkpt for deferred signal */ IMG_UINT32 ui32Status; /*!< sync checkpt status signal/errored */ } _SYNC_CHECKPOINT_DEFERRED_SIGNAL; diff --git a/drivers/gpu/drm/img-rogue/sync_fallback_server.h b/drivers/gpu/drm/img-rogue/sync_fallback_server.h index 931bd7dfa..ac6bd4755 100644 --- a/drivers/gpu/drm/img-rogue/sync_fallback_server.h +++ b/drivers/gpu/drm/img-rogue/sync_fallback_server.h @@ -96,7 +96,8 @@ PVRSRV_ERROR SyncFbTimelineCreatePVR(IMG_UINT32 uiTimelineNameSize, const IMG_CHAR *pszTimelineName, PVRSRV_TIMELINE_SERVER **ppsTimeline); -PVRSRV_ERROR SyncFbFenceCreatePVR(const IMG_CHAR *pszName, +PVRSRV_ERROR SyncFbFenceCreatePVR(PPVRSRV_DEVICE_NODE psDeviceNode, + const IMG_CHAR *pszName, PVRSRV_TIMELINE iTl, PSYNC_CHECKPOINT_CONTEXT hSyncCheckpointContext, PVRSRV_FENCE *piOutFence, diff --git a/drivers/gpu/drm/img-rogue/tlclient.c b/drivers/gpu/drm/img-rogue/tlclient.c index be4539d79..dc3f17a46 100644 --- a/drivers/gpu/drm/img-rogue/tlclient.c +++ b/drivers/gpu/drm/img-rogue/tlclient.c @@ -70,6 +70,12 @@ CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. #include "pvrsrv_tlcommon.h" #include "client_pvrtl_bridge.h" +#if defined(__KERNEL__) +#include "srvcore.h" +#else +#include "srvcore_intern.h" +#endif + /* Defines/Constants */ @@ -226,8 +232,10 @@ PVRSRV_ERROR TLClientCloseStream(SHARED_DEV_CONNECTION hDevConnection, /* Send close to server to clean up kernel mode resources for this * handle and release the memory. */ - eError = BridgeTLCloseStream(GetBridgeHandle(hDevConnection), - psSD->hServerSD); + eError = DestroyServerResource(hDevConnection, + NULL, + BridgeTLCloseStream, + psSD->hServerSD); PVR_LOG_IF_ERROR(eError, "BridgeTLCloseStream"); if (psSD->ui32WritesFailed != 0) diff --git a/drivers/gpu/drm/img-rogue/tlstream.c b/drivers/gpu/drm/img-rogue/tlstream.c index 7aeef82ba..a80792e7b 100644 --- a/drivers/gpu/drm/img-rogue/tlstream.c +++ b/drivers/gpu/drm/img-rogue/tlstream.c @@ -1062,7 +1062,7 @@ TLStreamCommit(IMG_HANDLE hStream, IMG_UINT32 ui32ReqSize) /* Memory barrier required to ensure prior data written by writer is * flushed from WC buffer to main memory. */ - OSWriteMemoryBarrier(); + OSWriteMemoryBarrier(NULL); /* Acquire stream lock to ensure other context(s) (if any) * wait on the lock (in DoTLStreamReserve) for consistent values @@ -1073,6 +1073,9 @@ TLStreamCommit(IMG_HANDLE hStream, IMG_UINT32 ui32ReqSize) psTmp->ui32Write = ui32LWrite; psTmp->ui32Pending = ui32LPending; + /* Ensure write pointer is flushed */ + OSWriteMemoryBarrier(&psTmp->ui32Write); + TL_COUNTER_ADD(psTmp->ui32ProducerByteCount, ui32ReqSize); TL_COUNTER_INC(psTmp->ui32NumCommits); diff --git a/drivers/gpu/drm/img-rogue/vmm_impl.h b/drivers/gpu/drm/img-rogue/vmm_impl.h index 520f39109..9ad5adeda 100644 --- a/drivers/gpu/drm/img-rogue/vmm_impl.h +++ b/drivers/gpu/drm/img-rogue/vmm_impl.h @@ -121,7 +121,7 @@ typedef struct _VMM_PVZ_CONNECTION_ for allocating the physical heap that backs its firmware allocations, this is the default configuration. The physical heap is allocated within the guest VM IPA space and this - IPA Addr/Size must be re-expressed as PA space Addr/Size + IPA Addr/Size must be translated into the host's IPA space by the VM manager before forwarding request to host. If not implemented, return PVRSRV_ERROR_NOT_IMPLEMENTED. */ diff --git a/drivers/gpu/drm/img-rogue/vmm_pvz_client.c b/drivers/gpu/drm/img-rogue/vmm_pvz_client.c index d9f4d34af..427811a7b 100644 --- a/drivers/gpu/drm/img-rogue/vmm_pvz_client.c +++ b/drivers/gpu/drm/img-rogue/vmm_pvz_client.c @@ -80,7 +80,7 @@ PvzClientMapDevPhysHeap(PVRSRV_DEVICE_CONFIG *psDevConfig) IMG_DEV_PHYADDR sDevPAddr; VMM_PVZ_CONNECTION *psVmmPvz; IMG_UINT32 uiFuncID = PVZ_BRIDGE_MAPDEVICEPHYSHEAP; - PHYS_HEAP *psFwPhysHeap = psDevConfig->psDevNode->apsPhysHeap[PVRSRV_PHYS_HEAP_FW_CONFIG]; + PHYS_HEAP *psFwPhysHeap = psDevConfig->psDevNode->apsPhysHeap[PVRSRV_PHYS_HEAP_FW_MAIN]; eError = PhysHeapGetDevPAddr(psFwPhysHeap, &sDevPAddr);