mirror of
https://github.com/revyos/thead-kernel.git
synced 2026-07-20 23:28:04 +02:00
145 lines
6.9 KiB
C
145 lines
6.9 KiB
C
/* SPDX-License-Identifier: GPL-2.0 */
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/*
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* Copyright (C) 2022 Alibaba Group Holding Limited.
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*/
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#include <dt-bindings/clock/light-fm-ap-clock.h>
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#include <dt-bindings/clock/light-visys.h>
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#include <linux/clk.h>
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#include <linux/err.h>
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#include <linux/init.h>
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#include <linux/io.h>
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#include <linux/module.h>
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#include <linux/of.h>
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#include <linux/of_device.h>
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#include <linux/of_address.h>
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#include <linux/platform_device.h>
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#include <linux/types.h>
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#include "clk-gate.h"
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#include "../clk.h"
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static struct clk *gates[LIGHT_CLKGEN_VISYS_CLK_END];
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static struct clk_onecell_data clk_gate_data;
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static u32 share_cnt_isp0_hclk_en;
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static u32 share_cnt_isp0_aclk_en;
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static int light_visys_clk_probe(struct platform_device *pdev)
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{
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struct regmap *visys_regmap;
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struct device *dev = &pdev->dev;
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struct device_node *np = dev->of_node;
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int ret;
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visys_regmap = syscon_regmap_lookup_by_phandle(np, "visys-regmap");
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if (IS_ERR(visys_regmap)) {
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dev_err(&pdev->dev, "cannot find regmap for vi system register\n");
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return PTR_ERR(visys_regmap);
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}
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/* we assume that the gate clock is a root clock */
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gates[LIGHT_CLKGEN_DW200_ACLK] = thead_gate_clk_register("clkgen_dw200_aclk", NULL,
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visys_regmap, 0xa0, 27, GATE_NOT_SHARED, NULL, dev);
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gates[LIGHT_CLKGEN_AXI4_VISYS1_ACLK] = thead_gate_clk_register("clkgen_axi4_visys1_aclk", NULL,
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visys_regmap, 0xa0, 26, GATE_NOT_SHARED, NULL, dev);
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gates[LIGHT_CLKGEN_AXI4_VISYS2_ACLK] = thead_gate_clk_register("clkgen_axi4_visys2_aclk", NULL,
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visys_regmap, 0xa0, 25, GATE_NOT_SHARED, NULL, dev);
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gates[LIGHT_CLKGEN_AXI4_VISYS3_ACLK] = thead_gate_clk_register("clkgen_axi4_visys3_aclk", NULL,
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visys_regmap, 0xa0, 24, GATE_NOT_SHARED, NULL, dev);
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gates[LIGHT_CLKGEN_ISP_RY_ACLK] = thead_gate_clk_register("clkgen_isp_ry_aclk", NULL,
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visys_regmap, 0xa0, 22, GATE_NOT_SHARED, NULL, dev);
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gates[LIGHT_CLKGEN_ISP_VENC_SHAKE_ACLK] = thead_gate_clk_register("clkgen_isp_venc_shake_aclk", NULL,
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visys_regmap, 0xa0, 30, GATE_NOT_SHARED, NULL, dev);
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gates[LIGHT_CLKGEN_VIPRE_ACLK] = thead_gate_clk_register("clkgen_vipre_aclk", NULL,
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visys_regmap, 0xa0, 31, GATE_NOT_SHARED, NULL, dev);
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gates[LIGHT_CLKGEN_DW200_HCLK] = thead_gate_clk_register("clkgen_dw200_hclk", NULL,
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visys_regmap, 0xa0, 13, GATE_NOT_SHARED, NULL, dev);
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gates[LIGHT_CLKGEN_ISP_RY_HCLK] = thead_gate_clk_register("clkgen_isp_ry_hclk", NULL,
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visys_regmap, 0xa0, 12, GATE_NOT_SHARED, NULL, dev);
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gates[LIGHT_CLKGEN_MIPI_CSI0_PCLK] = thead_gate_clk_register("clkgen_mipi_csi0_pclk", NULL,
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visys_regmap, 0xa0, 18, GATE_NOT_SHARED, NULL, dev);
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gates[LIGHT_CLKGEN_MIPI_CSI1_PCLK] = thead_gate_clk_register("clkgen_mipi_csi1_pclk", NULL,
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visys_regmap, 0xa0, 17, GATE_NOT_SHARED, NULL, dev);
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gates[LIGHT_CLKGEN_MIPI_CSI2_PCLK] = thead_gate_clk_register("clkgen_mipi_csi2_pclk", NULL,
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visys_regmap, 0xa0, 16, GATE_NOT_SHARED, NULL, dev);
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gates[LIGHT_CLKGEN_VIPRE_PCLK] = thead_gate_clk_register("clkgen_vipre_pclk", NULL,
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visys_regmap, 0xa0, 15, GATE_NOT_SHARED, NULL, dev);
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gates[LIGHT_CLKGEN_ISP_VENC_SHAKE_PCLK] = thead_gate_clk_register("clkgen_isp_venc_shake_pclk", NULL,
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visys_regmap, 0xa0, 29, GATE_NOT_SHARED, NULL, dev);
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gates[LIGHT_CLKGEN_MIPI_CSI0_PIXCLK] = thead_gate_clk_register("clkgen_mipi_csi0_pixclk", NULL,
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visys_regmap, 0xa0, 11, GATE_NOT_SHARED, NULL, dev);
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gates[LIGHT_CLKGEN_MIPI_CSI1_PIXCLK] = thead_gate_clk_register("clkgen_mipi_csi1_pixclk", NULL,
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visys_regmap, 0xa0, 10, GATE_NOT_SHARED, NULL, dev);
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gates[LIGHT_CLKGEN_MIPI_CSI2_PIXCLK] = thead_gate_clk_register("clkgen_mipi_csi2_pixclk", NULL,
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visys_regmap, 0xa0, 9, GATE_NOT_SHARED, NULL, dev);
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gates[LIGHT_CLKGEN_VIPRE_PIXELCLK] = thead_gate_clk_register("clkgen_vipre_pixelclk", NULL,
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visys_regmap, 0xa4, 23, GATE_NOT_SHARED, NULL, dev);
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gates[LIGHT_CLKGEN_MIPI_CSI0_CFG_CLK] = thead_gate_clk_register("clkgen_mipi_csi0_cfg_clk", NULL,
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visys_regmap, 0xa0, 8, GATE_NOT_SHARED, NULL, dev);
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gates[LIGHT_CLKGEN_MIPI_CSI1_CFG_CLK] = thead_gate_clk_register("clkgen_mipi_csi1_cfg_clk", NULL,
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visys_regmap, 0xa0, 6, GATE_NOT_SHARED, NULL, dev);
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gates[LIGHT_CLKGEN_MIPI_CSI2_CFG_CLK] = thead_gate_clk_register("clkgen_mipi_csi2_cfg_clk", NULL,
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visys_regmap, 0xa0, 7, GATE_NOT_SHARED, NULL, dev);
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gates[LIGHT_CLKGEN_DW200_CLK_VSE] = thead_gate_clk_register("clkgen_dw200_clk_vse", NULL,
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visys_regmap, 0xa0, 5, GATE_NOT_SHARED, NULL, dev);
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gates[LIGHT_CLKGEN_DW200_CLK_DWE] = thead_gate_clk_register("clkgen_dw200_clk_dwe", NULL,
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visys_regmap, 0xa0, 4, GATE_NOT_SHARED, NULL, dev);
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gates[LIGHT_CLKGEN_ISP0_CLK] = thead_gate_clk_register("clkgen_isp_clk_0", NULL,
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visys_regmap, 0xa4, 31, GATE_NOT_SHARED, NULL, dev);
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gates[LIGHT_CLKGEN_ISP1_CLK] = thead_gate_clk_register("clkgen_isp_clk_1", NULL,
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visys_regmap, 0xa4, 30, GATE_NOT_SHARED, NULL, dev);
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gates[LIGHT_CLKGEN_ISP_RY_CCLK] = thead_gate_clk_register("clkgen_isp_ry_cclk", NULL,
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visys_regmap, 0xa0, 21, GATE_NOT_SHARED, NULL, dev);
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gates[LIGHT_CLKGEN_ISP1_PIXELCLK] = thead_gate_clk_register("clkgen_isp1_pixelclk", NULL,
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visys_regmap, 0xa4, 28, GATE_NOT_SHARED, NULL, dev);
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gates[LIGHT_CLKGEN_ISP0_PIXELCLK] = thead_gate_clk_register("clkgen_isp0_pixelclk", NULL,
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visys_regmap, 0xa4, 29, GATE_NOT_SHARED, NULL, dev);
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gates[LIGHT_CLKGEN_ISP1_HCLK] = thead_gate_clk_register("clkgen_isp1_hclk", NULL,
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visys_regmap, 0xa0, 1, GATE_SHARED, &share_cnt_isp0_hclk_en, dev);
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gates[LIGHT_CLKGEN_ISP0_HCLK] = thead_gate_clk_register("clkgen_isp0_hclk", NULL,
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visys_regmap, 0xa0, 1, GATE_SHARED, &share_cnt_isp0_hclk_en, dev);
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gates[LIGHT_CLKGEN_ISP1_ACLK] = thead_gate_clk_register("clkgen_isp1_aclk", NULL,
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visys_regmap, 0xa0, 3, GATE_SHARED, &share_cnt_isp0_aclk_en, dev);
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gates[LIGHT_CLKGEN_ISP0_ACLK] = thead_gate_clk_register("clkgen_isp0_aclk", NULL,
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visys_regmap, 0xa0, 3, GATE_SHARED, &share_cnt_isp0_aclk_en, dev);
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clk_gate_data.clks = gates;
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clk_gate_data.clk_num = ARRAY_SIZE(gates);
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ret = of_clk_add_provider(np, of_clk_src_onecell_get, &clk_gate_data);
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if (ret < 0) {
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dev_err(dev, "failed to register gate clks for light visys\n");
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goto unregister_clks;
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}
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dev_info(dev, "succeed to register visys gate clock provider\n");
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return 0;
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unregister_clks:
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thead_unregister_clocks(gates, ARRAY_SIZE(gates));
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return ret;
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}
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static const struct of_device_id visys_clk_gate_of_match[] = {
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{ .compatible = "thead,visys-gate-controller" },
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{ /* sentinel */ },
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};
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MODULE_DEVICE_TABLE(of, visys_clk_gate_of_match);
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static struct platform_driver light_visys_clk_driver = {
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.probe = light_visys_clk_probe,
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.driver = {
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.name = "visys-clk-gate-provider",
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.of_match_table = of_match_ptr(visys_clk_gate_of_match),
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},
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};
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module_platform_driver(light_visys_clk_driver);
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MODULE_AUTHOR("wei.liu <lw312886@linux.alibaba.com>");
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MODULE_DESCRIPTION("Thead Light Fullmask visys clock gate provider");
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MODULE_LICENSE("GPL v2");
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