mirror of
https://github.com/revyos/thead-kernel.git
synced 2026-08-10 08:11:21 +02:00
112 lines
5.2 KiB
C
112 lines
5.2 KiB
C
/* SPDX-License-Identifier: GPL-2.0 */
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/*
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* Copyright (C) 2022 Alibaba Group Holding Limited.
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*/
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#include <dt-bindings/clock/light-fm-ap-clock.h>
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#include <dt-bindings/clock/light-vosys.h>
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#include <linux/clk.h>
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#include <linux/err.h>
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#include <linux/init.h>
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#include <linux/io.h>
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#include <linux/module.h>
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#include <linux/of.h>
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#include <linux/of_device.h>
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#include <linux/of_address.h>
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#include <linux/platform_device.h>
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#include <linux/types.h>
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#include "../clk.h"
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static struct clk *gates[LIGHT_CLKGEN_VOSYS_CLK_END];
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static struct clk_onecell_data clk_gate_data;
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static int light_vosys_clk_probe(struct platform_device *pdev)
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{
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struct device *dev = &pdev->dev;
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struct device_node *np = dev->of_node;
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void __iomem *gate_base;
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int ret;
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gate_base = devm_platform_ioremap_resource(pdev, 0);
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if (WARN_ON(IS_ERR(gate_base)))
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return PTR_ERR(gate_base);
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/* we assume that the gate clock is a root clock */
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gates[LIGHT_CLKGEN_AXI4_VO_PCLK] = thead_clk_light_gate("clkgen_axi4_vo_pclk", NULL,
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gate_base + 0x50, 22);
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gates[LIGHT_CLKGEN_IOPMP_VOSYS_DPU_PCLK] = thead_clk_light_gate("clkgen_iopmp_dpu_pclk", NULL,
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gate_base + 0x50, 23);
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gates[LIGHT_CLKGEN_IOPMP_VOSYS_DPU1_PCLK] = thead_clk_light_gate("clkgen_iopmp_dpu1_pclk", NULL,
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gate_base + 0x50, 24);
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gates[LIGHT_CLKGEN_IOPMP_VOSYS_GPU_PCLK] = thead_clk_light_gate("clkgen_iopmp_gpu_pclk", NULL,
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gate_base + 0x50, 25);
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gates[LIGHT_CLKGEN_HDMI_PCLK] = thead_clk_light_gate("clkgen_hdmi_pclk", NULL, gate_base + 0x50, 11);
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gates[LIGHT_CLKGEN_MIPIDSI0_PCLK] = thead_clk_light_gate("clkgen_mipidsi0_pclk", NULL,
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gate_base + 0x50, 13);
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gates[LIGHT_CLKGEN_MIPIDSI1_PCLK] = thead_clk_light_gate("clkgen_mipidsi1_pclk", NULL,
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gate_base + 0x50, 14);
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gates[LIGHT_CLKGEN_AXI4_VO_ACLK] = thead_clk_light_gate("clkgen_axi4_vo_aclk", NULL,
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gate_base + 0x50, 0);
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gates[LIGHT_CLKGEN_IOPMP_GPU_ACLK] = thead_clk_light_gate("clkgen_iopmp_gpu_aclk", NULL,
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gate_base + 0x50, 29);
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gates[LIGHT_CLKGEN_IOPMP_DPU_ACLK] = thead_clk_light_gate("clkgen_iopmp_dpu_aclk", NULL,
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gate_base + 0x50, 28);
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gates[LIGHT_CLKGEN_IOPMP_DPU1_ACLK] = thead_clk_light_gate("clkgen_iopmp_dpu1_aclk", NULL,
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gate_base + 0x50, 27);
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gates[LIGHT_CLKGEN_X2H_DPU_ACLK] = thead_clk_light_gate("clkgen_x2h_dpu_aclk", NULL, gate_base + 0x50, 21);
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gates[LIGHT_CLKGEN_X2H_DPU1_ACLK] = thead_clk_light_gate("clkgen_x2h_dpu1_aclk", NULL, gate_base + 0x50, 20);
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gates[LIGHT_CLKGEN_MIPIDSI0_PIXCLK] = thead_clk_light_gate("clkgen_mipidsi0_pixclk", NULL, gate_base + 0x50, 30);
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gates[LIGHT_CLKGEN_HDMI_PIXCLK] = thead_clk_light_gate("clkgen_hdmi_pixclk", NULL, gate_base + 0x54, 0);
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gates[LIGHT_CLKGEN_MIPIDSI1_PIXCLK] = thead_clk_light_gate("clkgen_mipidsi1_pixclk", NULL, gate_base + 0x50, 31);
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gates[LIGHT_CLKGEN_HDMI_SFR_CLK] = thead_clk_light_gate("clkgen_hdmi_sfr_clk", NULL, gate_base + 0x50, 10);
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gates[LIGHT_CLKGEN_HDMI_CEC_CLK] = thead_clk_light_gate("clkgen_hdmi_cec_cclk", NULL, gate_base + 0x50, 12);
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gates[LIGHT_CLKGEN_HDMI_I2S_CLK] = thead_clk_light_gate("clkgen_hdmi_i2s_clk", NULL, gate_base + 0x50, 19);
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gates[LIGHT_CLKGEN_MIPIDSI0_CFG_CLK] = thead_clk_light_gate("clkgen_mipidsi0_cfg_clk", NULL, gate_base + 0x50, 15);
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gates[LIGHT_CLKGEN_MIPIDSI1_CFG_CLK] = thead_clk_light_gate("clkgen_mipidsi1_cfg_clk", NULL, gate_base + 0x50, 16);
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gates[LIGHT_CLKGEN_MIPIDSI0_REFCLK] = thead_clk_light_gate("clkgen_mipidsi0_refclk", NULL, gate_base + 0x50, 17);
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gates[LIGHT_CLKGEN_MIPIDSI1_REFCLK] = thead_clk_light_gate("clkgen_mipidsi1_refclk", NULL, gate_base + 0x50, 18);
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gates[LIGHT_CLKGEN_GPU_CORE_CLK] = thead_clk_light_gate("clkgen_gpu_core_clk", NULL, gate_base + 0x50, 3);
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gates[LIGHT_CLKGEN_GPU_CFG_ACLK] = thead_clk_light_gate("clkgen_gpu_cfg_aclk", NULL, gate_base + 0x50, 4);
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gates[LIGHT_CLKGEN_DPU_HCLK] = thead_clk_light_gate("clkgen_dpu_hclk", NULL, gate_base + 0x50, 7);
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gates[LIGHT_CLKGEN_DPU_ACLK] = thead_clk_light_gate("clkgen_dpu_aclk", NULL, gate_base + 0x50, 8);
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gates[LIGHT_CLKGEN_DPU_CCLK] = thead_clk_light_gate("clkgen_dpu_cclk", NULL, gate_base + 0x50, 9);
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gates[LIGHT_CLKGEN_DPU_PIXCLK0] = thead_clk_light_gate("clkgen_dpu_pixclk0", NULL, gate_base + 0x50, 5);
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gates[LIGHT_CLKGEN_DPU_PIXCLK1] = thead_clk_light_gate("clkgen_dpu_pixclk1", NULL, gate_base + 0x50, 6);
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clk_gate_data.clks = gates;
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clk_gate_data.clk_num = ARRAY_SIZE(gates);
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ret = of_clk_add_provider(np, of_clk_src_onecell_get, &clk_gate_data);
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if (ret < 0) {
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dev_err(dev, "failed to register gate clks for light vosys\n");
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goto unregister_clks;
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}
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dev_info(dev, "succeed to register vosys gate clock provider\n");
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return 0;
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unregister_clks:
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thead_unregister_clocks(gates, ARRAY_SIZE(gates));
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return ret;
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}
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static const struct of_device_id vosys_clk_gate_of_match[] = {
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{ .compatible = "thead,vosys-gate-controller" },
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{ /* sentinel */ },
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};
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MODULE_DEVICE_TABLE(of, vosys_clk_gate_of_match);
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static struct platform_driver light_vosys_clk_driver = {
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.probe = light_vosys_clk_probe,
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.driver = {
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.name = "vosys-clk-gate-provider",
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.of_match_table = of_match_ptr(vosys_clk_gate_of_match),
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},
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};
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module_platform_driver(light_vosys_clk_driver);
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MODULE_AUTHOR("wei.liu <lw312886@linux.alibaba.com>");
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MODULE_DESCRIPTION("Thead Light Fullmask vosys clock gate provider");
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MODULE_LICENSE("GPL v2");
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