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429 lines
13 KiB
C
429 lines
13 KiB
C
/*************************************************************************/ /*!
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@File
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@Title RISC-V specific OS functions
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@Copyright Copyright (c) Imagination Technologies Ltd. All Rights Reserved
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@Description Processor specific OS functions
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@License Dual MIT/GPLv2
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The contents of this file are subject to the MIT license as set out below.
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Permission is hereby granted, free of charge, to any person obtaining a copy
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of this software and associated documentation files (the "Software"), to deal
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in the Software without restriction, including without limitation the rights
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to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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copies of the Software, and to permit persons to whom the Software is
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furnished to do so, subject to the following conditions:
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The above copyright notice and this permission notice shall be included in
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all copies or substantial portions of the Software.
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Alternatively, the contents of this file may be used under the terms of
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the GNU General Public License Version 2 ("GPL") in which case the provisions
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of GPL are applicable instead of those above.
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If you wish to allow use of your version of this file only under the terms of
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GPL, and not to allow others to use your version of this file under the terms
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of the MIT license, indicate your decision by deleting the provisions above
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and replace them with the notice and other provisions required by GPL as set
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out in the file called "GPL-COPYING" included in this distribution. If you do
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not delete the provisions above, a recipient may use your version of this file
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under the terms of either the MIT license or GPL.
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This License is also included in this distribution in the file called
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"MIT-COPYING".
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EXCEPT AS OTHERWISE STATED IN A NEGOTIATED AGREEMENT: (A) THE SOFTWARE IS
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PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING
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BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR
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PURPOSE AND NONINFRINGEMENT; AND (B) IN NO EVENT SHALL THE AUTHORS OR
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COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
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IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
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CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
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*/ /**************************************************************************/
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#include <linux/version.h>
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#include <linux/dma-mapping.h>
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//#include <linux/uaccess.h>
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#include <asm/uaccess.h>
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#include <asm/cacheflush.h>
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#include "img_defs.h"
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#include "osfunc.h"
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#include "pvr_debug.h"
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#include "cache_ops.h"
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#if 0
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#define __enable_user_access() \
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__asm__ __volatile__ ("csrs sstatus, %0" : : "r" (SR_SUM) : "memory")
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#define __disable_user_access() \
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__asm__ __volatile__ ("csrc sstatus, %0" : : "r" (SR_SUM) : "memory")
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#endif
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//asm volatile (".long 0x0275000b"); /* dcache.civa a0 */
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//asm volatile (".long 0x0255000b"); /* dcache.cva a0 */
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#define sync_is() asm volatile (".long 0x01b0000b")
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static void riscv_dma_wbinv_range(unsigned long start, unsigned long end)
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{
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//#if (LINUX_VERSION_CODE >= KERNEL_VERSION(4,4,168))
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//#endif
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register unsigned long i asm("a0") = start & ~(L1_CACHE_BYTES - 1);
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for (; i < end; i += L1_CACHE_BYTES)
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asm volatile (".long 0x02b5000b"); /* dcache.civa a0 */
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sync_is();
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//#if (LINUX_VERSION_CODE >= KERNEL_VERSION(4,4,168))
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//#endif
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}
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static void riscv_dma_wb_range(unsigned long start, unsigned long end)
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{
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register unsigned long i asm("a0") = start & ~(L1_CACHE_BYTES - 1);
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for (; i < end; i += L1_CACHE_BYTES)
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asm volatile (".long 0x0295000b"); /* dcache.cva a0 */
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sync_is();
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}
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static inline void begin_user_mode_access(void)
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{
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}
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static inline void end_user_mode_access(void)
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{
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}
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static inline void FlushRange(void *pvRangeAddrStart,
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void *pvRangeAddrEnd,
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PVRSRV_CACHE_OP eCacheOp)
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{
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// IMG_UINT32 ui32CacheLineSize = OSCPUCacheAttributeSize(OS_CPU_CACHE_ATTRIBUTE_LINE_SIZE);
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IMG_BYTE *pbStart = pvRangeAddrStart;
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IMG_BYTE *pbEnd = pvRangeAddrEnd;
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// IMG_BYTE *pbBase;
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//PVR_DPF((PVR_DBG_WARNING, "%s:&&&&&&%d %lx, %lx %x", __func__, __LINE__, (unsigned long)pbStart, (unsigned long)pbEnd, (uint32_t)eCacheOp));
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__enable_user_access();
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switch (eCacheOp)
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{
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case PVRSRV_CACHE_OP_CLEAN:
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riscv_dma_wb_range((unsigned long)pbStart, (unsigned long)pbEnd);
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break;
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case PVRSRV_CACHE_OP_INVALIDATE:
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case PVRSRV_CACHE_OP_FLUSH:
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// PVR_DPF((PVR_DBG_WARNING, "%s:&&&&&&%d %lx, %lx %x", __func__, __LINE__, (unsigned long)pbStart, (unsigned long)pbEnd, (uint32_t)eCacheOp));
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riscv_dma_wbinv_range((unsigned long)pbStart, (unsigned long)pbEnd);
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//PVR_DPF((PVR_DBG_WARNING, "%s:&&&&&&%d %lx, %lx %x", __func__, __LINE__, (unsigned long)pbStart, (unsigned long)pbEnd, (uint32_t)eCacheOp));
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break;
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default:
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PVR_DPF((PVR_DBG_ERROR,
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"%s: Cache maintenance operation type %d is invalid",
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__func__, eCacheOp));
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break;
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}
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__disable_user_access();
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/*
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On arm64, the TRM states in D5.8.1 (data and unified caches) that if cache
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maintenance is performed on a memory location using a VA, the effect of
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that cache maintenance is visible to all VA aliases of the physical memory
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location. So here it's quicker to issue the machine cache maintenance
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instruction directly without going via the Linux kernel DMA framework as
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this is sufficient to maintain the CPU d-caches on arm64.
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*/
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// begin_user_mode_access();
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//
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// pbEnd = (IMG_BYTE *) PVR_ALIGN((uintptr_t)pbEnd, (uintptr_t)ui32CacheLineSize);
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// for (pbBase = pbStart; pbBase < pbEnd; pbBase += ui32CacheLineSize)
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// {
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// switch (eCacheOp)
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// {
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// case PVRSRV_CACHE_OP_CLEAN:
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// asm volatile ("dcache.cva %0" : : "r"(pbBase));
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// break;
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//
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// case PVRSRV_CACHE_OP_INVALIDATE:
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// asm volatile ("dcache.iva %0" :: "r" (pbBase));
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// break;
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//
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// case PVRSRV_CACHE_OP_FLUSH:
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// asm volatile ("dcache.civa %0" :: "r" (pbBase));
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// break;
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//
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// default:
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// PVR_DPF((PVR_DBG_ERROR,
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// "%s: Cache maintenance operation type %d is invalid",
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// __func__, eCacheOp));
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// break;
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// }
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// }
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//
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// end_user_mode_access();
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}
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void OSCPUCacheFlushRangeKM(PVRSRV_DEVICE_NODE *psDevNode,
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void *pvVirtStart,
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void *pvVirtEnd,
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IMG_CPU_PHYADDR sCPUPhysStart,
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IMG_CPU_PHYADDR sCPUPhysEnd)
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{
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struct device *dev;
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#if 0
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if (pvVirtStart)
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{
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PVR_DPF((PVR_DBG_WARNING, "%s:********&&&&&&%d %lx %lx", __func__, __LINE__, (unsigned long)sCPUPhysStart.uiAddr, (unsigned long)sCPUPhysEnd.uiAddr));
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FlushRange(pvVirtStart, pvVirtEnd, PVRSRV_CACHE_OP_FLUSH);
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return;
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}
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#else
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//PVR_DPF((PVR_DBG_WARNING, "%s:********&&&&&&%d", __func__, __LINE__));
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FlushRange((void *)(sCPUPhysStart.uiAddr), (void *)(sCPUPhysEnd.uiAddr), PVRSRV_CACHE_OP_FLUSH);
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return;
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#endif
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dev = psDevNode->psDevConfig->pvOSDevice;
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if (dev)
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{
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PVR_DPF((PVR_DBG_WARNING, "%s:********&&&&&&%d", __func__, __LINE__));
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dma_sync_single_for_device(dev, sCPUPhysStart.uiAddr,
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sCPUPhysEnd.uiAddr - sCPUPhysStart.uiAddr,
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DMA_TO_DEVICE);
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dma_sync_single_for_cpu(dev, sCPUPhysStart.uiAddr,
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sCPUPhysEnd.uiAddr - sCPUPhysStart.uiAddr,
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DMA_FROM_DEVICE);
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}
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else
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{
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/*
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* Allocations done prior to obtaining device pointer may
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* affect in cache operations being scheduled.
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*
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* Ignore operations with null device pointer.
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* This prevents crashes on newer kernels that don't return dummy ops
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* when null pointer is passed to get_dma_ops.
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*
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*/
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/* Don't spam on nohw */
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#if !defined(NO_HARDWARE)
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PVR_DPF((PVR_DBG_WARNING, "Cache operation cannot be completed!"));
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#endif
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}
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/*
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* RISC-V cache maintenance mechanism is not part of the core spec.
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* This leaves the actual mechanism of action to an implementer.
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* Here we let the system layer decide how maintenance is done.
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*/
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// if (psDevNode->psDevConfig->pfnHostCacheMaintenance)
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// {
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// psDevNode->psDevConfig->pfnHostCacheMaintenance(
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// psDevNode->psDevConfig->hSysData,
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// PVRSRV_CACHE_OP_FLUSH,
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// pvVirtStart,
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// pvVirtEnd,
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// sCPUPhysStart,
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// sCPUPhysEnd);
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//
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// }
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//#if !defined(NO_HARDWARE)
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// else
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// {
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// PVR_DPF((PVR_DBG_WARNING,
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// "%s: System doesn't implement cache maintenance. Skipping!",
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// __func__));
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// }
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//#endif
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}
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void OSCPUCacheCleanRangeKM(PVRSRV_DEVICE_NODE *psDevNode,
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void *pvVirtStart,
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void *pvVirtEnd,
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IMG_CPU_PHYADDR sCPUPhysStart,
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IMG_CPU_PHYADDR sCPUPhysEnd)
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{
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struct device *dev;
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#if 0
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if (pvVirtStart)
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{
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PVR_DPF((PVR_DBG_WARNING, "%s:****&&&&&&%d", __func__, __LINE__));
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FlushRange(pvVirtStart, pvVirtEnd, PVRSRV_CACHE_OP_CLEAN);
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return;
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}
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#else
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FlushRange((void *)(sCPUPhysStart.uiAddr), (void *)(sCPUPhysEnd.uiAddr), PVRSRV_CACHE_OP_CLEAN);
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return;
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#endif
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dev = psDevNode->psDevConfig->pvOSDevice;
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if (dev)
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{
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PVR_DPF((PVR_DBG_WARNING, "%s:******&&&&&&%d", __func__, __LINE__));
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dma_sync_single_for_device(dev, sCPUPhysStart.uiAddr,
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sCPUPhysEnd.uiAddr - sCPUPhysStart.uiAddr,
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DMA_TO_DEVICE);
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}
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else
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{
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/*
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* Allocations done prior to obtaining device pointer may
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* affect in cache operations being scheduled.
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*
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* Ignore operations with null device pointer.
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* This prevents crashes on newer kernels that don't return dummy ops
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* when null pointer is passed to get_dma_ops.
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*
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*/
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/* Don't spam on nohw */
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#if !defined(NO_HARDWARE)
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PVR_DPF((PVR_DBG_WARNING, "Cache operation cannot be completed!"));
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#endif
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}
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/*
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* RISC-V cache maintenance mechanism is not part of the core spec.
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* This leaves the actual mechanism of action to an implementer.
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* Here we let the system layer decide how maintenance is done.
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*/
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// if (psDevNode->psDevConfig->pfnHostCacheMaintenance)
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// {
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// psDevNode->psDevConfig->pfnHostCacheMaintenance(
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// psDevNode->psDevConfig->hSysData,
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// PVRSRV_CACHE_OP_CLEAN,
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// pvVirtStart,
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// pvVirtEnd,
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// sCPUPhysStart,
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// sCPUPhysEnd);
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//
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// }
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//#if !defined(NO_HARDWARE)
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// else
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// {
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// PVR_DPF((PVR_DBG_WARNING,
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// "%s: System doesn't implement cache maintenance. Skipping!",
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// __func__));
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// }
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//#endif
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}
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void OSCPUCacheInvalidateRangeKM(PVRSRV_DEVICE_NODE *psDevNode,
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void *pvVirtStart,
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void *pvVirtEnd,
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IMG_CPU_PHYADDR sCPUPhysStart,
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IMG_CPU_PHYADDR sCPUPhysEnd)
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{
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struct device *dev;
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#if 0
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if (pvVirtStart)
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{
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PVR_DPF((PVR_DBG_WARNING, "%s:**&&&&&&%d", __func__, __LINE__));
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FlushRange(pvVirtStart, pvVirtEnd, PVRSRV_CACHE_OP_INVALIDATE);
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return;
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}
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#else
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FlushRange((void *)(sCPUPhysStart.uiAddr), (void *)(sCPUPhysEnd.uiAddr), PVRSRV_CACHE_OP_INVALIDATE);
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return;
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#endif
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dev = psDevNode->psDevConfig->pvOSDevice;
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if (dev)
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{
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PVR_DPF((PVR_DBG_WARNING, "%s:***&&&&&&%d", __func__, __LINE__));
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dma_sync_single_for_cpu(dev, sCPUPhysStart.uiAddr,
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sCPUPhysEnd.uiAddr - sCPUPhysStart.uiAddr,
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DMA_FROM_DEVICE);
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}
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else
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{
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/*
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* Allocations done prior to obtaining device pointer may
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* affect in cache operations being scheduled.
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*
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* Ignore operations with null device pointer.
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* This prevents crashes on newer kernels that don't return dummy ops
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* when null pointer is passed to get_dma_ops.
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*
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*/
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/* Don't spam on nohw */
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#if !defined(NO_HARDWARE)
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PVR_DPF((PVR_DBG_WARNING, "Cache operation cannot be completed!"));
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#endif
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}
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/*
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* RISC-V cache maintenance mechanism is not part of the core spec.
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* This leaves the actual mechanism of action to an implementer.
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* Here we let the system layer decide how maintenance is done.
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*/
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// if (psDevNode->psDevConfig->pfnHostCacheMaintenance)
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// {
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// psDevNode->psDevConfig->pfnHostCacheMaintenance(
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// psDevNode->psDevConfig->hSysData,
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// PVRSRV_CACHE_OP_INVALIDATE,
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// pvVirtStart,
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// pvVirtEnd,
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// sCPUPhysStart,
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// sCPUPhysEnd);
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//
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// }
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//#if !defined(NO_HARDWARE)
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// else
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// {
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// PVR_DPF((PVR_DBG_WARNING,
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// "%s: System doesn't implement cache maintenance. Skipping!",
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// __func__));
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// }
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//#endif
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}
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OS_CACHE_OP_ADDR_TYPE OSCPUCacheOpAddressType(void)
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{
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/*
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* Need to obtain psDevNode here and do the following:
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*
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* OS_CACHE_OP_ADDR_TYPE eOpAddrType =
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* psDevNode->psDevConfig->bHasPhysicalCacheMaintenance ?
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* OS_CACHE_OP_ADDR_TYPE_PHYSICAL : OS_CACHE_OP_ADDR_TYPE_VIRTUAL;
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*
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* Return BOTH for now on.
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*
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*/
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//return OS_CACHE_OP_ADDR_TYPE_BOTH;
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return OS_CACHE_OP_ADDR_TYPE_PHYSICAL;
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}
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void OSUserModeAccessToPerfCountersEn(void)
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{
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#if !defined(NO_HARDWARE)
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PVR_DPF((PVR_DBG_WARNING, "%s: Not implemented!", __func__));
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// PVR_ASSERT(0);
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#endif
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}
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IMG_BOOL OSIsWriteCombineUnalignedSafe(void)
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{
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#if !defined(NO_HARDWARE)
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//PVR_DPF((PVR_DBG_WARNING,
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// "%s: Not implemented (assuming false)!",
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// __func__));
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//PVR_ASSERT(0);
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//return IMG_FALSE;
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return IMG_TRUE;
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#else
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return IMG_TRUE;
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#endif
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}
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