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152 lines
6.0 KiB
C
152 lines
6.0 KiB
C
/*************************************************************************/ /*!
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@File
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@Title arm specific OS functions
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@Copyright Copyright (c) Imagination Technologies Ltd. All Rights Reserved
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@Description Processor specific OS functions
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@License Dual MIT/GPLv2
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The contents of this file are subject to the MIT license as set out below.
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Permission is hereby granted, free of charge, to any person obtaining a copy
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of this software and associated documentation files (the "Software"), to deal
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in the Software without restriction, including without limitation the rights
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to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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copies of the Software, and to permit persons to whom the Software is
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furnished to do so, subject to the following conditions:
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The above copyright notice and this permission notice shall be included in
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all copies or substantial portions of the Software.
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Alternatively, the contents of this file may be used under the terms of
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the GNU General Public License Version 2 ("GPL") in which case the provisions
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of GPL are applicable instead of those above.
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If you wish to allow use of your version of this file only under the terms of
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GPL, and not to allow others to use your version of this file under the terms
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of the MIT license, indicate your decision by deleting the provisions above
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and replace them with the notice and other provisions required by GPL as set
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out in the file called "GPL-COPYING" included in this distribution. If you do
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not delete the provisions above, a recipient may use your version of this file
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under the terms of either the MIT license or GPL.
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This License is also included in this distribution in the file called
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"MIT-COPYING".
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EXCEPT AS OTHERWISE STATED IN A NEGOTIATED AGREEMENT: (A) THE SOFTWARE IS
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PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING
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BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR
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PURPOSE AND NONINFRINGEMENT; AND (B) IN NO EVENT SHALL THE AUTHORS OR
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COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
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IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
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CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
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*/ /**************************************************************************/
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#include <linux/version.h>
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#include <linux/dma-mapping.h>
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#if (LINUX_VERSION_CODE < KERNEL_VERSION(3,15,0))
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#include <asm/system.h>
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#endif
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#include <asm/cacheflush.h>
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#include "pvrsrv_error.h"
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#include "img_types.h"
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#include "img_defs.h"
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#include "osfunc.h"
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#include "pvr_debug.h"
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static inline size_t pvr_dmac_range_len(const void *pvStart, const void *pvEnd)
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{
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return (size_t)((char *)pvEnd - (char *)pvStart);
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}
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void OSCPUCacheFlushRangeKM(PVRSRV_DEVICE_NODE *psDevNode,
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void *pvVirtStart,
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void *pvVirtEnd,
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IMG_CPU_PHYADDR sCPUPhysStart,
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IMG_CPU_PHYADDR sCPUPhysEnd)
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{
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PVR_UNREFERENCED_PARAMETER(psDevNode);
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#if (LINUX_VERSION_CODE >= KERNEL_VERSION(3,7,0))
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arm_dma_ops.sync_single_for_device(psDevNode->psDevConfig->pvOSDevice, sCPUPhysStart.uiAddr, sCPUPhysEnd.uiAddr - sCPUPhysStart.uiAddr, DMA_TO_DEVICE);
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arm_dma_ops.sync_single_for_cpu(psDevNode->psDevConfig->pvOSDevice, sCPUPhysStart.uiAddr, sCPUPhysEnd.uiAddr - sCPUPhysStart.uiAddr, DMA_FROM_DEVICE);
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#else /* (LINUX_VERSION_CODE >= KERNEL_VERSION(3,7,0)) */
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/* Inner cache */
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dmac_flush_range(pvVirtStart, pvVirtEnd);
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/* Outer cache */
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outer_flush_range(sCPUPhysStart.uiAddr, sCPUPhysEnd.uiAddr);
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#endif /* (LINUX_VERSION_CODE >= KERNEL_VERSION(3,7,0)) */
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}
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void OSCPUCacheCleanRangeKM(PVRSRV_DEVICE_NODE *psDevNode,
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void *pvVirtStart,
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void *pvVirtEnd,
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IMG_CPU_PHYADDR sCPUPhysStart,
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IMG_CPU_PHYADDR sCPUPhysEnd)
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{
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PVR_UNREFERENCED_PARAMETER(psDevNode);
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#if (LINUX_VERSION_CODE >= KERNEL_VERSION(3,7,0))
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arm_dma_ops.sync_single_for_device(psDevNode->psDevConfig->pvOSDevice, sCPUPhysStart.uiAddr, sCPUPhysEnd.uiAddr - sCPUPhysStart.uiAddr, DMA_TO_DEVICE);
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#else /* (LINUX_VERSION_CODE >= KERNEL_VERSION(3,7,0)) */
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/* Inner cache */
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dmac_map_area(pvVirtStart, pvr_dmac_range_len(pvVirtStart, pvVirtEnd), DMA_TO_DEVICE);
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/* Outer cache */
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outer_clean_range(sCPUPhysStart.uiAddr, sCPUPhysEnd.uiAddr);
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#endif /* (LINUX_VERSION_CODE >= KERNEL_VERSION(3,7,0)) */
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}
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void OSCPUCacheInvalidateRangeKM(PVRSRV_DEVICE_NODE *psDevNode,
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void *pvVirtStart,
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void *pvVirtEnd,
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IMG_CPU_PHYADDR sCPUPhysStart,
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IMG_CPU_PHYADDR sCPUPhysEnd)
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{
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PVR_UNREFERENCED_PARAMETER(psDevNode);
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#if (LINUX_VERSION_CODE >= KERNEL_VERSION(3,7,0))
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arm_dma_ops.sync_single_for_cpu(psDevNode->psDevConfig->pvOSDevice, sCPUPhysStart.uiAddr, sCPUPhysEnd.uiAddr - sCPUPhysStart.uiAddr, DMA_FROM_DEVICE);
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#else /* (LINUX_VERSION_CODE >= KERNEL_VERSION(3,7,0)) */
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/* Inner cache */
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dmac_map_area(pvVirtStart, pvr_dmac_range_len(pvVirtStart, pvVirtEnd), DMA_FROM_DEVICE);
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/* Outer cache */
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outer_inv_range(sCPUPhysStart.uiAddr, sCPUPhysEnd.uiAddr);
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#endif /* (LINUX_VERSION_CODE >= KERNEL_VERSION(3,7,0)) */
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}
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OS_CACHE_OP_ADDR_TYPE OSCPUCacheOpAddressType(void)
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{
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#if (LINUX_VERSION_CODE >= KERNEL_VERSION(3,7,0))
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return OS_CACHE_OP_ADDR_TYPE_PHYSICAL;
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#else
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return OS_CACHE_OP_ADDR_TYPE_BOTH;
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#endif
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}
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/* User Enable Register */
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#define PMUSERENR_EN 0x00000001 /* enable user access to the counters */
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static void per_cpu_perf_counter_user_access_en(void *data)
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{
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PVR_UNREFERENCED_PARAMETER(data);
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/* Enable user-mode access to counters. */
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asm volatile("mcr p15, 0, %0, c9, c14, 0" :: "r"(PMUSERENR_EN));
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}
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void OSUserModeAccessToPerfCountersEn(void)
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{
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on_each_cpu(per_cpu_perf_counter_user_access_en, NULL, 1);
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}
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IMG_BOOL OSIsWriteCombineUnalignedSafe(void)
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{
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/*
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* The kernel looks to have always used normal memory under ARM32.
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* See osfunc_arm64.c implementation for more details.
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*/
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return IMG_TRUE;
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}
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