mirror of
https://github.com/revyos/thead-kernel.git
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100 lines
3.8 KiB
C
100 lines
3.8 KiB
C
/* SPDX-License-Identifier: GPL-2.0 */
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/*
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* Copyright (C) 2022 Alibaba Group Holding Limited.
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*/
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#include <dt-bindings/clock/light-fm-ap-clock.h>
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#include <dt-bindings/clock/light-vpsys.h>
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#include <linux/clk.h>
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#include <linux/err.h>
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#include <linux/init.h>
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#include <linux/io.h>
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#include <linux/module.h>
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#include <linux/of.h>
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#include <linux/of_device.h>
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#include <linux/of_address.h>
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#include <linux/platform_device.h>
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#include <linux/types.h>
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#include "../clk.h"
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static struct clk *gates[LIGHT_VPSYS_CLK_END];
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static struct clk_onecell_data clk_gate_data;
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static u32 share_cnt_g2d_clk_en;
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static u32 share_cnt_fce_clk_en;
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static int light_vpsys_clk_probe(struct platform_device *pdev)
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{
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struct device *dev = &pdev->dev;
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struct device_node *np = dev->of_node;
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void __iomem *gate_base;
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int ret;
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gate_base = devm_platform_ioremap_resource(pdev, 0);
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if (WARN_ON(IS_ERR(gate_base)))
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return PTR_ERR(gate_base);
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// DIV & CDE
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gates[LIGHT_VPSYS_G2D_CCLK_DIV] = thead_clk_light_divider("light_vpsys_g2d_cclk_div", "video_pll_foutvco", gate_base + 0x30, 0, 4, 4, MUX_TYPE_DIV, 3, 15);
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gates[LIGHT_VPSYS_DEC_CCLK_DIV] = thead_clk_light_divider("light_vpsys_dec_cclk_div", "video_pll_foutvco", gate_base + 0x24, 0, 4, 4, MUX_TYPE_DIV, 4, 15);
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/* G2D clock configuration : Completed the upward configuration of CCLK */
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gates[LIGHT_VPSYS_G2D_PCLK] = thead_clk_light_gate_shared("clkgen_vpsys_g2d_pclk", NULL,
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gate_base + 0x20, 3, &share_cnt_g2d_clk_en);
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gates[LIGHT_VPSYS_G2D_ACLK] = thead_clk_light_gate_shared("clkgen_vpsys_g2d_aclk", NULL,
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gate_base + 0x20, 3, &share_cnt_g2d_clk_en);
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gates[LIGHT_VPSYS_G2D_CCLK] = thead_clk_light_gate_shared("clkgen_vpsys_g2d_cclk", "light_vpsys_g2d_cclk_div",
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gate_base + 0x20, 3, &share_cnt_g2d_clk_en);
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/* we assume that the gate clock is a root clock */
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gates[LIGHT_VPSYS_FCE_PCLK] = thead_clk_light_gate_shared("clkgen_vpsys_fce_pclk", NULL,
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gate_base + 0x20, 2, &share_cnt_fce_clk_en);
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gates[LIGHT_VPSYS_FCE_ACLK] = thead_clk_light_gate_shared("clkgen_vpsys_fce_aclk", NULL,
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gate_base + 0x20, 2, &share_cnt_fce_clk_en);
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/* VENC&VDEC clock configuration : Completed the upward configuration of CCLK */
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gates[LIGHT_VPSYS_VDEC_ACLK] = thead_clk_light_gate("clkgen_vdec_aclk", NULL, gate_base + 0x20, 4);
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gates[LIGHT_VPSYS_VDEC_CCLK] = thead_clk_light_gate("clkgen_vdec_cclk", "light_vpsys_dec_cclk_div", gate_base + 0x20, 5);
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gates[LIGHT_VPSYS_VDEC_PCLK] = thead_clk_light_gate("clkgen_vdec_pclk", NULL, gate_base + 0x20, 6);
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gates[LIGHT_VPSYS_VENC_CCLK] = thead_clk_light_gate("clkgen_venc_cclk", "clkgen_vpsys_venc_cclk", gate_base + 0x20, 8);
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gates[LIGHT_VPSYS_VENC_PCLK] = thead_clk_light_gate("clkgen_venc_pclk", NULL, gate_base + 0x20, 9);
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gates[LIGHT_VPSYS_VENC_ACLK] = thead_clk_light_gate("clkgen_venc_aclk", NULL, gate_base + 0x20, 7);
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clk_gate_data.clks = gates;
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clk_gate_data.clk_num = ARRAY_SIZE(gates);
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ret = of_clk_add_provider(np, of_clk_src_onecell_get, &clk_gate_data);
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if (ret < 0) {
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dev_err(dev, "failed to register gate clks for light vpsys\n");
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goto unregister_clks;
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}
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dev_info(dev, "succeed to register vpsys gate clock provider\n");
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return 0;
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unregister_clks:
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thead_unregister_clocks(gates, ARRAY_SIZE(gates));
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return ret;
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}
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static const struct of_device_id vpsys_clk_gate_of_match[] = {
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{ .compatible = "thead,vpsys-gate-controller" },
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{ /* sentinel */ },
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};
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MODULE_DEVICE_TABLE(of, vpsys_clk_gate_of_match);
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static struct platform_driver light_vpsys_clk_driver = {
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.probe = light_vpsys_clk_probe,
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.driver = {
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.name = "vpsys-clk-gate-provider",
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.of_match_table = of_match_ptr(vpsys_clk_gate_of_match),
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},
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};
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module_platform_driver(light_vpsys_clk_driver);
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MODULE_AUTHOR("wei.liu <lw312886@linux.alibaba.com>");
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MODULE_DESCRIPTION("Thead Light Fullmask vpsys clock gate provider");
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MODULE_LICENSE("GPL v2");
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