mirror of
https://github.com/revyos/thead-kernel.git
synced 2026-09-17 12:52:10 +02:00
100 lines
3.0 KiB
Plaintext
100 lines
3.0 KiB
Plaintext
/* SPDX-License-Identifier: GPL-2.0 */
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/*
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* Copyright (C) 2021 Alibaba Group Holding Limited.
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*/
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&npu {
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power-domains = <&pd LIGHT_AON_NPU_PD>;
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};
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&gpu {
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power-domains = <&pd LIGHT_AON_GPU_PD>;
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};
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&vdec {
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power-domains = <&pd LIGHT_AON_VDEC_PD>;
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};
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&venc {
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power-domains = <&pd LIGHT_AON_VENC_PD>;
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};
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&xtensa_dsp0 {
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power-domains = <&pd LIGHT_AON_DSP0_PD>;
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clocks = <&dspsys_clk_gate CLKGEN_DSP0_PCLK>, <&dspsys_clk_gate CLKGEN_DSP0_CCLK>;
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clock-names = "pclk", "cclk";
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};
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&xtensa_dsp1 {
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power-domains = <&pd LIGHT_AON_DSP1_PD>;
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clocks = <&dspsys_clk_gate CLKGEN_DSP1_PCLK>, <&dspsys_clk_gate CLKGEN_DSP1_CCLK>;
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clock-names = "pclk", "cclk";
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};
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&isp0 {
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clocks = <&visys_clk_gate LIGHT_CLKGEN_ISP0_ACLK>,
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<&visys_clk_gate LIGHT_CLKGEN_ISP0_HCLK>,
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<&visys_clk_gate LIGHT_CLKGEN_ISP0_PIXELCLK>,
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<&visys_clk_gate LIGHT_CLKGEN_ISP0_CLK>;
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clock-names = "aclk", "hclk", "isp0_pclk", "cclk";
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};
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&isp1 {
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clocks = <&visys_clk_gate LIGHT_CLKGEN_ISP0_ACLK>,
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<&visys_clk_gate LIGHT_CLKGEN_ISP0_HCLK>,
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<&visys_clk_gate LIGHT_CLKGEN_ISP0_PIXELCLK>,
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<&visys_clk_gate LIGHT_CLKGEN_ISP1_CLK>,
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<&visys_clk_gate LIGHT_CLKGEN_ISP1_PIXELCLK>;
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clock-names = "aclk", "hclk", "isp0_pclk", "cclk", "isp1_pclk";
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};
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&isp_ry0 {
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clocks = <&visys_clk_gate LIGHT_CLKGEN_ISP_RY_ACLK>,
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<&visys_clk_gate LIGHT_CLKGEN_ISP_RY_HCLK>,
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<&visys_clk_gate LIGHT_CLKGEN_ISP_RY_CCLK>;
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clock-names = "aclk", "hclk", "cclk";
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};
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&dewarp {
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clocks = <&visys_clk_gate LIGHT_CLKGEN_DW200_ACLK>,
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<&visys_clk_gate LIGHT_CLKGEN_DW200_HCLK>,
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<&visys_clk_gate LIGHT_CLKGEN_DW200_CLK_VSE>,
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<&visys_clk_gate LIGHT_CLKGEN_DW200_CLK_DWE>;
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clock-names = "aclk", "hclk", "vseclk", "dweclk";
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};
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&bm_csi0 { //CSI2
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clocks = <&visys_clk_gate LIGHT_CLKGEN_MIPI_CSI0_PCLK>,
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<&visys_clk_gate LIGHT_CLKGEN_MIPI_CSI0_PIXCLK>,
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<&visys_clk_gate LIGHT_CLKGEN_MIPI_CSI0_CFG_CLK>,
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<&visys_clk_gate LIGHT_CLKGEN_MIPI_CSI1_CFG_CLK>,
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<&visys_clk_gate LIGHT_CLKGEN_MIPI_CSI2_CFG_CLK>;
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clock-names = "pclk", "pixclk", "cfg_clk0", "cfg_clk1", "cfg_clk2";
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};
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&bm_csi1 { //CSI2X2_B
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clocks = <&visys_clk_gate LIGHT_CLKGEN_MIPI_CSI1_PCLK>,
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<&visys_clk_gate LIGHT_CLKGEN_MIPI_CSI1_PIXCLK>,
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<&visys_clk_gate LIGHT_CLKGEN_MIPI_CSI0_CFG_CLK>,
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<&visys_clk_gate LIGHT_CLKGEN_MIPI_CSI1_CFG_CLK>,
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<&visys_clk_gate LIGHT_CLKGEN_MIPI_CSI2_CFG_CLK>;
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clock-names = "pclk", "pixclk", "cfg_clk0", "cfg_clk1", "cfg_clk2";
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};
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&bm_csi2 { //CSI2X2_A
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clocks = <&visys_clk_gate LIGHT_CLKGEN_MIPI_CSI2_PCLK>,
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<&visys_clk_gate LIGHT_CLKGEN_MIPI_CSI2_PIXCLK>,
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<&visys_clk_gate LIGHT_CLKGEN_MIPI_CSI0_CFG_CLK>,
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<&visys_clk_gate LIGHT_CLKGEN_MIPI_CSI1_CFG_CLK>,
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<&visys_clk_gate LIGHT_CLKGEN_MIPI_CSI2_CFG_CLK>;
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clock-names = "pclk", "pixclk", "cfg_clk0", "cfg_clk1", "cfg_clk2";
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};
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&vi_pre {
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clocks = <&visys_clk_gate LIGHT_CLKGEN_VIPRE_ACLK>,
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<&visys_clk_gate LIGHT_CLKGEN_VIPRE_PCLK>,
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<&visys_clk_gate LIGHT_CLKGEN_VIPRE_PIXELCLK>;
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clock-names ="aclk", "pclk", "pixclk";
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};
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