mirror of
https://github.com/revyos/thead-kernel.git
synced 2026-09-16 12:22:33 +02:00
583 lines
17 KiB
C
583 lines
17 KiB
C
/* SPDX-License-Identifier: GPL-2.0 */
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/*
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* Copyright (C) 2020 VeriSilicon Holdings Co., Ltd.
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*/
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#ifndef __VS_DC_HW_H__
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#define __VS_DC_HW_H__
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#include <linux/version.h>
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#if LINUX_VERSION_CODE < KERNEL_VERSION(5, 5, 0)
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#include <drm/drmP.h>
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#endif
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#ifdef CONFIG_VERISILICON_MMU
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#include "vs_dc_mmu.h"
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#endif
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#define AQ_INTR_ACKNOWLEDGE 0x0010
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#define AQ_INTR_ENBL 0x0014
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#define DC_HW_REVISION 0x0024
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#define DC_HW_CHIP_CID 0x0030
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#define DC_REG_BASE 0x0800
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#define DC_REG_RANGE 0x2000
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#define DC_SEC_REG_OFFSET 0x100000
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#define DC_FRAMEBUFFER_CONFIG 0x1518
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#define DC_FRAMEBUFFER_CONFIG_EX 0x1CC0
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#define DC_FRAMEBUFFER_SCALE_CONFIG 0x1520
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#define DC_FRAMEBUFFER_TOP_LEFT 0x24D8
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#define DC_FRAMEBUFFER_BOTTOM_RIGHT 0x24E0
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#define DC_FRAMEBUFFER_ADDRESS 0x1400
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#define DC_FRAMEBUFFER_U_ADDRESS 0x1530
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#define DC_FRAMEBUFFER_V_ADDRESS 0x1538
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#define DC_FRAMEBUFFER_STRIDE 0x1408
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#define DC_FRAMEBUFFER_U_STRIDE 0x1800
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#define DC_FRAMEBUFFER_V_STRIDE 0x1808
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#define DC_FRAMEBUFFER_SIZE 0x1810
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#define DC_FRAMEBUFFER_SCALE_FACTOR_X 0x1828
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#define DC_FRAMEBUFFER_SCALE_FACTOR_Y 0x1830
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#define DC_FRAMEBUFFER_H_FILTER_COEF_INDEX 0x1838
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#define DC_FRAMEBUFFER_H_FILTER_COEF_DATA 0x1A00
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#define DC_FRAMEBUFFER_V_FILTER_COEF_INDEX 0x1A08
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#define DC_FRAMEBUFFER_V_FILTER_COEF_DATA 0x1A10
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#define DC_FRAMEBUFFER_INIT_OFFSET 0x1A20
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#define DC_FRAMEBUFFER_COLOR_KEY 0x1508
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#define DC_FRAMEBUFFER_COLOR_KEY_HIGH 0x1510
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#define DC_FRAMEBUFFER_CLEAR_VALUE 0x1A18
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#define DC_FRAMEBUFFER_COLOR_TABLE_INDEX 0x1818
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#define DC_FRAMEBUFFER_COLOR_TABLE_DATA 0x1820
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#define DC_FRAMEBUFFER_BG_COLOR 0x1528
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#define DC_FRAMEBUFFER_ROI_ORIGIN 0x1CB0
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#define DC_FRAMEBUFFER_ROI_SIZE 0x1CB8
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#define DC_FRAMEBUFFER_WATER_MARK 0x1CE8
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#define DC_FRAMEBUFFER_DEGAMMA_INDEX 0x1D88
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#define DC_FRAMEBUFFER_DEGAMMA_DATA 0x1D90
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#define DC_FRAMEBUFFER_DEGAMMA_EX_DATA 0x1D98
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#define DC_FRAMEBUFFER_YUVTORGB_COEF0 0x1DA0
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#define DC_FRAMEBUFFER_YUVTORGB_COEF1 0x1DA8
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#define DC_FRAMEBUFFER_YUVTORGB_COEF2 0x1DB0
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#define DC_FRAMEBUFFER_YUVTORGB_COEF3 0x1DB8
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#define DC_FRAMEBUFFER_YUVTORGB_COEF4 0x1E00
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#define DC_FRAMEBUFFER_YUVTORGB_COEFD0 0x1E08
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#define DC_FRAMEBUFFER_YUVTORGB_COEFD1 0x1E10
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#define DC_FRAMEBUFFER_YUVTORGB_COEFD2 0x1E18
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#define DC_FRAMEBUFFER_Y_CLAMP_BOUND 0x1E88
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#define DC_FRAMEBUFFER_UV_CLAMP_BOUND 0x1E90
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#define DC_FRAMEBUFFER_RGBTORGB_COEF0 0x1E20
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#define DC_FRAMEBUFFER_RGBTORGB_COEF1 0x1E28
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#define DC_FRAMEBUFFER_RGBTORGB_COEF2 0x1E30
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#define DC_FRAMEBUFFER_RGBTORGB_COEF3 0x1E38
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#define DC_FRAMEBUFFER_RGBTORGB_COEF4 0x1E40
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#define DC_FRAMEBUFFER_BLEND_CONFIG 0x2510
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#define DC_FRAMEBUFFER_SRC_GLOBAL_COLOR 0x2500
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#define DC_FRAMEBUFFER_DST_GLOBAL_COLOR 0x2508
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#define DC_OVERLAY_CONFIG 0x1540
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#define DC_OVERLAY_CONFIG_EX 0x2540
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#define DC_OVERLAY_SCALE_CONFIG 0x1C00
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#define DC_OVERLAY_BLEND_CONFIG 0x1580
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#define DC_OVERLAY_TOP_LEFT 0x1640
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#define DC_OVERLAY_BOTTOM_RIGHT 0x1680
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#define DC_OVERLAY_ADDRESS 0x15C0
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#define DC_OVERLAY_U_ADDRESS 0x1840
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#define DC_OVERLAY_V_ADDRESS 0x1880
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#define DC_OVERLAY_STRIDE 0x1600
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#define DC_OVERLAY_U_STRIDE 0x18C0
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#define DC_OVERLAY_V_STRIDE 0x1900
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#define DC_OVERLAY_SIZE 0x17C0
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#define DC_OVERLAY_SCALE_FACTOR_X 0x1A40
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#define DC_OVERLAY_SCALE_FACTOR_Y 0x1A80
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#define DC_OVERLAY_H_FILTER_COEF_INDEX 0x1AC0
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#define DC_OVERLAY_H_FILTER_COEF_DATA 0x1B00
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#define DC_OVERLAY_V_FILTER_COEF_INDEX 0x1B40
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#define DC_OVERLAY_V_FILTER_COEF_DATA 0x1B80
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#define DC_OVERLAY_INIT_OFFSET 0x1BC0
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#define DC_OVERLAY_COLOR_KEY 0x1740
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#define DC_OVERLAY_COLOR_KEY_HIGH 0x1780
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#define DC_OVERLAY_CLEAR_VALUE 0x1940
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#define DC_OVERLAY_COLOR_TABLE_INDEX 0x1980
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#define DC_OVERLAY_COLOR_TABLE_DATA 0x19C0
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#define DC_OVERLAY_SRC_GLOBAL_COLOR 0x16C0
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#define DC_OVERLAY_DST_GLOBAL_COLOR 0x1700
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#define DC_OVERLAY_ROI_ORIGIN 0x1D00
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#define DC_OVERLAY_ROI_SIZE 0x1D40
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#define DC_OVERLAY_WATER_MARK 0x1DC0
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#define DC_OVERLAY_DEGAMMA_INDEX 0x2200
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#define DC_OVERLAY_DEGAMMA_DATA 0x2240
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#define DC_OVERLAY_DEGAMMA_EX_DATA 0x2280
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#define DC_OVERLAY_YUVTORGB_COEF0 0x1EC0
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#define DC_OVERLAY_YUVTORGB_COEF1 0x1F00
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#define DC_OVERLAY_YUVTORGB_COEF2 0x1F40
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#define DC_OVERLAY_YUVTORGB_COEF3 0x1F80
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#define DC_OVERLAY_YUVTORGB_COEF4 0x1FC0
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#define DC_OVERLAY_YUVTORGB_COEFD0 0x2000
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#define DC_OVERLAY_YUVTORGB_COEFD1 0x2040
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#define DC_OVERLAY_YUVTORGB_COEFD2 0x2080
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#define DC_OVERLAY_Y_CLAMP_BOUND 0x22C0
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#define DC_OVERLAY_UV_CLAMP_BOUND 0x2300
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#define DC_OVERLAY_RGBTORGB_COEF0 0x20C0
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#define DC_OVERLAY_RGBTORGB_COEF1 0x2100
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#define DC_OVERLAY_RGBTORGB_COEF2 0x2140
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#define DC_OVERLAY_RGBTORGB_COEF3 0x2180
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#define DC_OVERLAY_RGBTORGB_COEF4 0x21C0
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#define DC_CURSOR_CONFIG 0x1468
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#define DC_CURSOR_ADDRESS 0x146C
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#define DC_CURSOR_LOCATION 0x1470
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#define DC_CURSOR_BACKGROUND 0x1474
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#define DC_CURSOR_FOREGROUND 0x1478
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#define DC_CURSOR_CLK_GATING 0x1484
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#define DC_CURSOR_CONFIG_EX 0x24E8
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#define DC_CURSOR_OFFSET 0x1080
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#define DC_DISPLAY_DITHER_CONFIG 0x1410
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#define DC_DISPLAY_PANEL_CONFIG 0x1418
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#define DC_DISPLAY_PANEL_CONFIG_EX 0x2518
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#define DC_DISPLAY_DITHER_TABLE_LOW 0x1420
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#define DC_DISPLAY_DITHER_TABLE_HIGH 0x1428
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#define DC_DISPLAY_H 0x1430
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#define DC_DISPLAY_H_SYNC 0x1438
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#define DC_DISPLAY_V 0x1440
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#define DC_DISPLAY_V_SYNC 0x1448
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#define DC_DISPLAY_CURRENT_LOCATION 0x1450
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#define DC_DISPLAY_GAMMA_INDEX 0x1458
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#define DC_DISPLAY_GAMMA_DATA 0x1460
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#define DC_DISPLAY_INT 0x147C
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#define DC_DISPLAY_INT_ENABLE 0x1480
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#define DC_DISPLAY_DBI_CONFIG 0x1488
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#define DC_DISPLAY_GENERAL_CONFIG 0x14B0
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#define DC_DISPLAY_DPI_CONFIG 0x14B8
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#define DC_DISPLAY_PANEL_START 0x1CCC
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#define DC_DISPLAY_DEBUG_COUNTER_SELECT 0x14D0
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#define DC_DISPLAY_DEBUG_COUNTER_VALUE 0x14D8
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#define DC_DISPLAY_DP_CONFIG 0x1CD0
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#define DC_DISPLAY_GAMMA_EX_INDEX 0x1CF0
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#define DC_DISPLAY_GAMMA_EX_DATA 0x1CF8
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#define DC_DISPLAY_GAMMA_EX_ONE_DATA 0x1D80
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#define DC_DISPLAY_RGBTOYUV_COEF0 0x1E48
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#define DC_DISPLAY_RGBTOYUV_COEF1 0x1E50
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#define DC_DISPLAY_RGBTOYUV_COEF2 0x1E58
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#define DC_DISPLAY_RGBTOYUV_COEF3 0x1E60
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#define DC_DISPLAY_RGBTOYUV_COEF4 0x1E68
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#define DC_DISPLAY_RGBTOYUV_COEFD0 0x1E70
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#define DC_DISPLAY_RGBTOYUV_COEFD1 0x1E78
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#define DC_DISPLAY_RGBTOYUV_COEFD2 0x1E80
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#define DC_CLK_GATTING 0x1A28
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#define DC_QOS_CONFIG 0x1A38
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#define DC_TRANSPARENCY_OPAQUE 0x00
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#define DC_TRANSPARENCY_KEY 0x02
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#define DC_DISPLAY_DITHERTABLE_LOW 0x7B48F3C0
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#define DC_DISPLAY_DITHERTABLE_HIGH 0x596AD1E2
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#define GAMMA_SIZE 256
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#define GAMMA_EX_SIZE 300
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#define DEGAMMA_SIZE 260
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#define RGB_TO_RGB_TABLE_SIZE 9
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#define YUV_TO_RGB_TABLE_SIZE 16
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#define RGB_TO_YUV_TABLE_SIZE 12
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#ifdef CONFIG_VERISILICON_DEC
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/* DEC400 register */
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#define DEC_CONTROL 0x0800
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#define DEC_CONTROL_EX 0x0804
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#define DEC_CONTROL_EX2 0x0808
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#define DEC_READ_CONFIG 0x0880
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#define DEC_READ_EX_CONFIG 0x0900
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#define DEC_READ_BUFFER_BASE 0x0A80
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#define DEC_READ_BUFFER_END 0x0B80
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#define DEC_READ_CACHE_BASE 0x1080
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#define DEC_CONTROL_RESET 0x0301018A
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#define DEC_CONTROL_EX_RESET 0x00080000
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#define DEC_CONTROL_EX2_RESET 0x103FC810
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#define DEC_READ_CONFIG_RESET 0x00020000
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#endif
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#ifdef CONFIG_VERISILICON_MMU
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#define DC_MMU_PREFETCH 0x1E98
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#define MMU_REG_BASE 0x0180
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#define MMU_REG_RANGE 0x700
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#define MMU_REG_CONFIG 0x0184
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#define MMU_REG_CONTROL 0x0388
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#define MMU_REG_TABLE_ARRAY_SIZE 0x0394
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#define MMU_REG_SAFE_NON_SECURE 0x0398
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#define MMU_REG_SAFE_SECURE 0x039C
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#define MMU_REG_SAFE_EXT_ADDRESS 0x03A0
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#define MMU_REG_CONTEXT_PD 0x03B4
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#define DEC_REG_CONTROL 0x0800
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#define DEC_REG_CONTROL_VALUE 0x02010188
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#define SE_MMU_REG_BASE 0x10010
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#define SE_MMU_REG_RANGE 0x60
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#define SE_MMU_REG_CONFIG 0x10010
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#define SE_MMU_REG_CONTROL 0x10024
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#define SE_MMU_REG_TABLE_ARRAY_SIZE 0x10030
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#define SE_MMU_REG_SAFE_NON_SECUR 0x10034
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#define SE_MMU_REG_SAFE_SECURE 0x10038
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#define SE_MMU_REG_SAFE_EXT_ADDRESS 0x1003C
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#define SE_MMU_REG_CONTEXT_PD 0x10040
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#define SE_MMU_REG_INTR_ENBL 0x10044
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#endif
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#define DC_LAYER_NUM 6
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#define DC_DISPLAY_NUM 2
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#define DC_CURSOR_NUM 2
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enum dc_chip_rev {
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DC_REV_0, /* For HW_REV_5720;
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* HW_REV_5721_311 */
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DC_REV_1, /* For HW_REV_5721_30B */
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DC_REV_2, /* For HW_REV_5721_310 */
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};
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enum dc_hw_plane_id {
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PRIMARY_PLANE_0,
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OVERLAY_PLANE_0,
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OVERLAY_PLANE_1,
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PRIMARY_PLANE_1,
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OVERLAY_PLANE_2,
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OVERLAY_PLANE_3,
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CURSOR_PLANE_0,
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CURSOR_PLANE_1,
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PLANE_NUM
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};
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enum dc_hw_color_format {
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FORMAT_X4R4G4B4,
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FORMAT_A4R4G4B4,
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FORMAT_X1R5G5B5,
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FORMAT_A1R5G5B5,
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FORMAT_R5G6B5,
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FORMAT_X8R8G8B8,
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FORMAT_A8R8G8B8,
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FORMAT_YUY2,
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FORMAT_UYVY,
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FORMAT_INDEX8,
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FORMAT_MONOCHROME,
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FORMAT_YV12 = 0xf,
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FORMAT_A8,
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FORMAT_NV12,
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FORMAT_NV16,
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FORMAT_RG16,
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FORMAT_R8,
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FORMAT_NV12_10BIT,
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FORMAT_A2R10G10B10,
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FORMAT_NV16_10BIT,
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FORMAT_INDEX1,
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FORMAT_INDEX2,
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FORMAT_INDEX4,
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FORMAT_P010,
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FORMAT_YUV444,
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FORMAT_YUV444_10BIT,
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};
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enum dc_hw_yuv_color_space {
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COLOR_SPACE_601 = 0,
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COLOR_SPACE_709 = 1,
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COLOR_SPACE_2020 = 3,
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};
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enum dc_hw_rotation {
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ROT_0 = 0,
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ROT_90 = 4,
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ROT_180 = 5,
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ROT_270 = 6,
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FLIP_X = 1,
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FLIP_Y = 2,
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FLIP_XY = 3,
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};
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enum dc_hw_swizzle {
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SWIZZLE_ARGB = 0,
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SWIZZLE_RGBA,
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SWIZZLE_ABGR,
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SWIZZLE_BGRA,
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};
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enum dc_hw_out {
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OUT_DPI,
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OUT_DP,
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};
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enum dc_hw_cursor_size {
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CURSOR_SIZE_32X32 = 0,
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CURSOR_SIZE_64X64,
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};
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enum dc_hw_blend_mode {
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/* out.rgb = plane_alpha * fg.rgb +
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* (1 - (plane_alpha * fg.alpha)) * bg.rgb
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*/
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BLEND_PREMULTI,
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/* out.rgb = plane_alpha * fg.alpha * fg.rgb +
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* (1 - (plane_alpha * fg.alpha)) * bg.rgb
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*/
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BLEND_COVERAGE,
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/* out.rgb = plane_alpha * fg.rgb +
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* (1 - plane_alpha) * bg.rgb
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*/
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BLEND_PIXEL_NONE,
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};
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struct dc_hw_plane_reg {
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u32 y_address;
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u32 u_address;
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u32 v_address;
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u32 y_stride;
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u32 u_stride;
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u32 v_stride;
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u32 size;
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u32 top_left;
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u32 bottom_right;
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u32 scale_factor_x;
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u32 scale_factor_y;
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u32 h_filter_coef_index;
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u32 h_filter_coef_data;
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u32 v_filter_coef_index;
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u32 v_filter_coef_data;
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u32 init_offset;
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u32 color_key;
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u32 color_key_high;
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u32 clear_value;
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u32 color_table_index;
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u32 color_table_data;
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u32 scale_config;
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u32 water_mark;
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u32 degamma_index;
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u32 degamma_data;
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u32 degamma_ex_data;
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u32 src_global_color;
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u32 dst_global_color;
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u32 blend_config;
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u32 roi_origin;
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u32 roi_size;
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u32 YUVToRGBCoef0;
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u32 YUVToRGBCoef1;
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u32 YUVToRGBCoef2;
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u32 YUVToRGBCoef3;
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u32 YUVToRGBCoef4;
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u32 YUVToRGBCoefD0;
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u32 YUVToRGBCoefD1;
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u32 YUVToRGBCoefD2;
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u32 YClampBound;
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u32 UVClampBound;
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u32 RGBToRGBCoef0;
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u32 RGBToRGBCoef1;
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u32 RGBToRGBCoef2;
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u32 RGBToRGBCoef3;
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u32 RGBToRGBCoef4;
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};
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#ifdef CONFIG_VERISILICON_MMU
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struct dc_hw_mmu_reg {
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u32 mmu_config;
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u32 mmu_control;
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u32 table_array_size;
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u32 safe_non_secure;
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u32 safe_secure;
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u32 safe_ex;
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u32 context_pd_entry;
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};
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#endif
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struct dc_hw_fb {
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u32 y_address;
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u32 u_address;
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u32 v_address;
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u32 clear_value;
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u32 water_mark;
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u16 y_stride;
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u16 u_stride;
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u16 v_stride;
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u16 width;
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u16 height;
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u8 format;
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u8 tile_mode;
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u8 rotation;
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u8 yuv_color_space;
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u8 swizzle;
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u8 uv_swizzle;
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u8 zpos;
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u8 display_id;
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bool clear_enable;
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bool dec_enable;
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bool enable;
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bool dirty;
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};
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struct dc_hw_scale {
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u32 scale_factor_x;
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u32 scale_factor_y;
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bool enable;
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bool dirty;
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};
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struct dc_hw_position {
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u16 start_x;
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u16 start_y;
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u16 end_x;
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u16 end_y;
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bool dirty;
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};
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struct dc_hw_blend {
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u8 alpha;
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u8 blend_mode;
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bool dirty;
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};
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struct dc_hw_colorkey {
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u32 colorkey;
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u32 colorkey_high;
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u8 transparency;
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bool dirty;
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};
|
|
|
|
struct dc_hw_roi {
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|
u16 x;
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|
u16 y;
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|
u16 width;
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|
u16 height;
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|
bool enable;
|
|
bool dirty;
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|
};
|
|
|
|
struct dc_hw_cursor {
|
|
u32 address;
|
|
u16 x;
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|
u16 y;
|
|
u16 hot_x;
|
|
u16 hot_y;
|
|
u8 size;
|
|
u8 display_id;
|
|
bool enable;
|
|
bool dirty;
|
|
};
|
|
|
|
struct dc_hw_display {
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|
u32 bus_format;
|
|
u16 h_active;
|
|
u16 h_total;
|
|
u16 h_sync_start;
|
|
u16 h_sync_end;
|
|
u16 v_active;
|
|
u16 v_total;
|
|
u16 v_sync_start;
|
|
u16 v_sync_end;
|
|
u16 sync_mode;
|
|
u32 bg_color;
|
|
u8 id;
|
|
bool h_sync_polarity;
|
|
bool v_sync_polarity;
|
|
bool enable;
|
|
bool sync_enable;
|
|
bool dither_enable;
|
|
};
|
|
|
|
struct dc_hw_gamma {
|
|
u16 gamma[GAMMA_EX_SIZE][3];
|
|
bool enable;
|
|
bool dirty;
|
|
};
|
|
|
|
struct dc_hw_degamma {
|
|
u16 degamma[DEGAMMA_SIZE][3];
|
|
u32 mode;
|
|
bool dirty;
|
|
};
|
|
|
|
struct dc_hw_plane {
|
|
struct dc_hw_fb fb;
|
|
struct dc_hw_position pos;
|
|
struct dc_hw_scale scale;
|
|
struct dc_hw_blend blend;
|
|
struct dc_hw_roi roi;
|
|
struct dc_hw_colorkey colorkey;
|
|
struct dc_hw_degamma degamma;
|
|
};
|
|
|
|
struct dc_hw_qos {
|
|
u8 low_value;
|
|
u8 high_value;
|
|
bool dirty;
|
|
};
|
|
|
|
struct dc_hw_read {
|
|
u32 reg;
|
|
u32 value;
|
|
};
|
|
|
|
struct dc_hw;
|
|
struct dc_hw_funcs {
|
|
void (*gamma)(struct dc_hw *hw);
|
|
void (*plane)(struct dc_hw *hw);
|
|
void (*display)(struct dc_hw *hw, struct dc_hw_display *display);
|
|
};
|
|
|
|
struct dc_hw {
|
|
enum dc_chip_rev rev;
|
|
enum dc_hw_out out[DC_DISPLAY_NUM];
|
|
void *hi_base;
|
|
void *reg_base;
|
|
#ifdef CONFIG_VERISILICON_MMU
|
|
void *mmu_base;
|
|
#endif
|
|
struct dc_hw_display display[DC_DISPLAY_NUM];
|
|
struct dc_hw_gamma gamma[DC_DISPLAY_NUM];
|
|
struct dc_hw_plane plane[DC_LAYER_NUM];
|
|
struct dc_hw_cursor cursor[DC_CURSOR_NUM];
|
|
struct dc_hw_qos qos;
|
|
struct dc_hw_funcs *func;
|
|
struct vs_dc_info *info;
|
|
};
|
|
|
|
int dc_hw_init(struct dc_hw *hw);
|
|
void dc_hw_deinit(struct dc_hw *hw);
|
|
void dc_hw_update_plane(struct dc_hw *hw, u8 id,
|
|
struct dc_hw_fb *fb, struct dc_hw_scale *scale,
|
|
struct dc_hw_position *pos, struct dc_hw_blend *blend);
|
|
void dc_hw_update_degamma(struct dc_hw *hw, u8 id, u32 mode);
|
|
void dc_hw_update_roi(struct dc_hw *hw, u8 id, struct dc_hw_roi *roi);
|
|
void dc_hw_update_colorkey(struct dc_hw *hw, u8 id,
|
|
struct dc_hw_colorkey *colorkey);
|
|
void dc_hw_update_qos(struct dc_hw *hw, struct dc_hw_qos *qos);
|
|
void dc_hw_update_cursor(struct dc_hw *hw, u8 id, struct dc_hw_cursor *cursor);
|
|
void dc_hw_update_gamma(struct dc_hw *hw, u8 id, u16 index,
|
|
u16 r, u16 g, u16 b);
|
|
void dc_hw_enable_gamma(struct dc_hw *hw, u8 id, bool enable);
|
|
void dc_hw_enable_dump(struct dc_hw *hw, u32 addr, u32 pitch);
|
|
void dc_hw_disable_dump(struct dc_hw *hw);
|
|
void dc_hw_setup_display(struct dc_hw *hw, struct dc_hw_display *display);
|
|
void dc_hw_enable_interrupt(struct dc_hw *hw, bool enable);
|
|
void dc_hw_enable_irq(struct dc_hw *hw, u32 irq, bool enable);
|
|
u32 dc_hw_get_interrupt(struct dc_hw *hw);
|
|
bool dc_hw_check_underflow(struct dc_hw *hw);
|
|
void dc_hw_enable_shadow_register(struct dc_hw *hw, bool enable);
|
|
void dc_hw_set_out(struct dc_hw *hw, enum dc_hw_out out, u8 id);
|
|
void dc_hw_commit(struct dc_hw *hw);
|
|
#ifdef CONFIG_VERISILICON_DEC
|
|
void dc_hw_dec_init(struct dc_hw *hw);
|
|
void dc_hw_dec_stream_set(struct dc_hw *hw,u32 main_base_addr,
|
|
u32 ts_base_addr, u8 tile_mode, u8 align_mode,
|
|
u8 format, u8 depth, u8 stream_id);
|
|
void dc_hw_dec_stream_disable(struct dc_hw *hw, u8 stream_id);
|
|
#endif
|
|
|
|
#ifdef CONFIG_VERISILICON_MMU
|
|
int dc_hw_mmu_init(struct dc_hw *hw, dc_mmu_pt mmu);
|
|
void dc_hw_enable_mmu_prefetch(struct dc_hw *hw, bool enable);
|
|
#endif
|
|
|
|
#endif /* __VS_DC_HW_H__ */
|