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https://github.com/revyos/thead-kernel.git
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9e49618e75
Add a new driver npu-ax3386-gpl, default compile as module. The default generated modules are: - vha.ko - img_mem.ko - vha_info.ko Signed-off-by: Mingzheng Xing <xingmingzheng@iscas.ac.cn>
105 lines
4.2 KiB
C
105 lines
4.2 KiB
C
/*!
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*****************************************************************************
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*
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* @File vha_plat.h
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* ---------------------------------------------------------------------------
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*
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* Copyright (c) Imagination Technologies Ltd.
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*
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* The contents of this file are subject to the MIT license as set out below.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
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* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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* THE SOFTWARE.
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*
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* Alternatively, the contents of this file may be used under the terms of the
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* GNU General Public License Version 2 ("GPL")in which case the provisions of
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* GPL are applicable instead of those above.
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*
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* If you wish to allow use of your version of this file only under the terms
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* of GPL, and not to allow others to use your version of this file under the
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* terms of the MIT license, indicate your decision by deleting the provisions
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* above and replace them with the notice and other provisions required by GPL
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* as set out in the file called "GPLHEADER" included in this distribution. If
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* you do not delete the provisions above, a recipient may use your version of
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* this file under the terms of either the MIT license or GPL.
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*
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* This License is also included in this distribution in the file called
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* "MIT_COPYING".
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*
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*****************************************************************************/
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#ifndef VHA_PLAT_H
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#define VHA_PLAT_H
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/* Core clock frequency: default 30MHz */
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#define VHA_CORE_CLOCK_MHZ 30
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/* Core watchdog cycles default value */
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#if defined(HW_AX2)
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#define VHA_CORE_WDT_CYCLES 0x7fffff
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#elif defined(HW_AX3)
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/* MMM can transfer any number of bytes at cost of higher cycles, setting it to ~100ms @800MHz */
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#define VHA_CORE_WDT_CYCLES 0xfffffff
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/* Memory watchdog is set ~1ms @800MHz which is very safe value to avoid any false interrupts */
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#define VHA_CORE_MEM_WDT_CYCLES 0xffffffff
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#endif
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#ifdef CONFIG_HW_MULTICORE
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/* System watchdog cycles default values */
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#define VHA_SYS_MEM_WDT_CYCLES 0xffffffff
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/* WM watchdog cycles default values */
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#define VHA_WM_WDT_CYCLES 0xffffffff
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#define VHA_WM_IDLE_WDT_CYCLES 0xfffff
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#define VHA_WM_SOCIF_WDT_CYCLES 0xfffff
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/* Core watchdog cycles default values */
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/* MMM can transfer any number of bytes at cost of higher cycles, setting it to ~100ms @800MHz */
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#define VHA_CORE_WDT_CYCLES 0xfffffff
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/* Memory watchdog is set ~1ms @800MHz which is very safe value to avoid any false interrupts */
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#define VHA_CORE_MEM_WDT_CYCLES 0xffffffff
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#define VHA_CORE_SYNC_WDT_CYCLES 0xffff
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#endif
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/* Memory burst size */
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#define VHA_CORE_MH_MAX_BURST_LENGTH 128
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/* SLC cache policy type (0-use cache, 1-bypass cache) */
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#define VHA_CORE_MH_SLC_CACHE_POLICY_TYPE 1
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/* GPU pipe coherent type */
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#define VHA_CORE_MH_GPU_PIPE_COHERENT_TYPE 1
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/* Persistence priority 0-lowest,3-highest */
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#define VHA_CORE_MH_PERSISTENCE_PRIO 0
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/* Suspend delay in ms after which the
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* runtime suspend callback is called */
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#define VHA_CORE_SUSPEND_DELAY 10
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/* Default OCM start address */
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#ifdef CONFIG_HW_MULTICORE
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#define VHA_OCM_ADDR_START 0x1000
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#else
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#define VHA_OCM_ADDR_START (~0)
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#endif
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/* IO hooks */
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uint64_t vha_plat_read64(void *addr);
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void vha_plat_write64(void *addr, uint64_t val);
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int vha_plat_init(void);
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int vha_plat_deinit(void);
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#endif /* VHA_PLAT_H */
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