mirror of
https://github.com/revyos/thead-opensbi.git
synced 2026-06-21 09:12:28 +02:00
219 lines
11 KiB
C
219 lines
11 KiB
C
//------------------------------------------------------------
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// DONOT MODIFY THIS FILE
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// generated by JISHENGJU automatically
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//------------------------------------------------------------
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#ifndef AONSYS_SYSREG_REG_OFFSET_DEFINE_H
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#define AONSYS_SYSREG_REG_OFFSET_DEFINE_H
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#define AONSYS_REG_BASE 0xFFFFF48000
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#define REG_AON_CPU_LP_MODE (AONSYS_REG_BASE + 0x0 )
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#define REG_AON_CHIP_LP_MODE (AONSYS_REG_BASE + 0x4 )
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#define REG_AON_AO_SERAM_TRN (AONSYS_REG_BASE + 0x10 )
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#define REG_AON_AO_SERAM_INT (AONSYS_REG_BASE + 0x14 )
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#define REG_AON_STR_SERAM_TRN (AONSYS_REG_BASE + 0x18 )
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#define REG_AON_STR_SERAM_INT (AONSYS_REG_BASE + 0x1c )
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#define REG_AON_STR_INDICATOR_0 (AONSYS_REG_BASE + 0x20 )
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#define REG_AON_STR_INDICATOR_1 (AONSYS_REG_BASE + 0x24 )
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#define REG_AON_STR_INDICATOR_2 (AONSYS_REG_BASE + 0x28 )
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#define REG_AON_STR_INDICATOR_3 (AONSYS_REG_BASE + 0x2c )
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#define REG_AON_PVTC_WR_LOCK (AONSYS_REG_BASE + 0x30 )
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#define REG_AON_PVTC_TS_ALARM (AONSYS_REG_BASE + 0x34 )
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#define REG_AON_PVTC_VM_ALARM (AONSYS_REG_BASE + 0x38 )
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#define REG_AON_PVTC_PD_ALARM (AONSYS_REG_BASE + 0x3c )
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#define REG_AON_E902_CNT_CLR (AONSYS_REG_BASE + 0x40 )
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#define REG_AON_E902_RST_ADDR (AONSYS_REG_BASE + 0x44 )
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#define REG_AON_C906_RST_ADDR_L (AONSYS_REG_BASE + 0x48 )
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#define REG_AON_C906_RST_ADDR_H (AONSYS_REG_BASE + 0x4c )
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#define REG_AON_RESERVED_REG_0 (AONSYS_REG_BASE + 0x50 )
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#define REG_AON_RESERVED_REG_1 (AONSYS_REG_BASE + 0x54 )
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#define REG_AON_RESERVED_REG_2 (AONSYS_REG_BASE + 0x58 )
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#define REG_AON_RESERVED_REG_3 (AONSYS_REG_BASE + 0x5c )
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#define REG_AON_AON_AHB_ADEXT (AONSYS_REG_BASE + 0x60 )
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#define REG_AON_RC_EN (AONSYS_REG_BASE + 0x70 )
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#define REG_AON_RC_FCAL (AONSYS_REG_BASE + 0x74 )
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#define REG_AON_RC_MODE (AONSYS_REG_BASE + 0x78 )
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#define REG_AON_RC_READY (AONSYS_REG_BASE + 0x7c )
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#define REG_AON_ISO_CFG (AONSYS_REG_BASE + 0x80 )
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#define REG_AON_OCRAM_ERR (AONSYS_REG_BASE + 0x90 )
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#define REG_AON_TIMER_LINK (AONSYS_REG_BASE + 0x100)
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#define REG_AON_PD_REQ (AONSYS_REG_BASE + 0x110)
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#define REG_AON_PD_ISO_EN_SET (AONSYS_REG_BASE + 0x114)
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#define REG_AON_PD_ISO_EN_CLR (AONSYS_REG_BASE + 0x118)
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#define REG_AON_PD_SW_EN_SET (AONSYS_REG_BASE + 0x11c)
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#define REG_AON_PD_SW_EN_CLR (AONSYS_REG_BASE + 0x120)
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#define REG_AON_PD_SW_ACK (AONSYS_REG_BASE + 0x124)
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#define REG_AON_PD_SW_CNT_EN (AONSYS_REG_BASE + 0x128)
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#define REG_AON_PD_FSM_RST (AONSYS_REG_BASE + 0x12c)
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#define REG_AON_PD_INT_MASK (AONSYS_REG_BASE + 0x130)
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#define REG_AON_PD_FSM_STS_L (AONSYS_REG_BASE + 0x134)
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#define REG_AON_PD_FSM_STS_H (AONSYS_REG_BASE + 0x138)
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#define REG_AON_PD_INT_STS (AONSYS_REG_BASE + 0x13c)
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#define REG_AON_PD_INT_CLR (AONSYS_REG_BASE + 0x140)
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#define REG_AON_PD_BLK0_SW_CNT (AONSYS_REG_BASE + 0x144)
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#define REG_AON_PD_BLK1_SW_CNT (AONSYS_REG_BASE + 0x148)
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#define REG_AON_PD_BLK2_SW_CNT (AONSYS_REG_BASE + 0x14c)
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#define REG_AON_PD_BLK3_SW_CNT (AONSYS_REG_BASE + 0x150)
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#define REG_AON_PD_BLK4_SW_CNT (AONSYS_REG_BASE + 0x154)
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#define REG_AON_PD_BLK5_SW_CNT (AONSYS_REG_BASE + 0x158)
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#define REG_AON_PD_BLK6_SW_CNT (AONSYS_REG_BASE + 0x15c)
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#define REG_AON_PD_BLK7_SW_CNT (AONSYS_REG_BASE + 0x160)
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#define REG_AON_PD_BLK8_SW_CNT (AONSYS_REG_BASE + 0x164)
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#define REG_AON_PD_BLK9_SW_CNT (AONSYS_REG_BASE + 0x168)
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#define REG_AON_PD_BLK10_SW_CNT (AONSYS_REG_BASE + 0x16c)
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#define REG_AON_PD_BLK0_INTV_CNT (AONSYS_REG_BASE + 0x180)
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#define REG_AON_PD_BLK1_INTV_CNT (AONSYS_REG_BASE + 0x184)
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#define REG_AON_PD_BLK2_INTV_CNT (AONSYS_REG_BASE + 0x188)
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#define REG_AON_PD_BLK3_INTV_CNT (AONSYS_REG_BASE + 0x18c)
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#define REG_AON_PD_BLK4_INTV_CNT (AONSYS_REG_BASE + 0x190)
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#define REG_AON_PD_BLK5_INTV_CNT (AONSYS_REG_BASE + 0x194)
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#define REG_AON_PD_BLK6_INTV_CNT (AONSYS_REG_BASE + 0x198)
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#define REG_AON_PD_BLK7_INTV_CNT (AONSYS_REG_BASE + 0x19c)
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#define REG_AON_PD_BLK8_INTV_CNT (AONSYS_REG_BASE + 0x1a0)
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#define REG_AON_PD_BLK9_INTV_CNT (AONSYS_REG_BASE + 0x1a4)
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#define REG_AON_PD_BLK10_INTV_CNT (AONSYS_REG_BASE + 0x1a8)
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#define REG_AON_AUDIO_PMU_REQ (AONSYS_REG_BASE + 0x1f8)
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#define REG_AON_AUDIO_PMU_STS (AONSYS_REG_BASE + 0x1fc)
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#define REG_AON_AUDIO_PMU_INTR (AONSYS_REG_BASE + 0x204)
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#define REG_AON_PMU_AUDIO_REQ (AONSYS_REG_BASE + 0x208)
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#define REG_AON_PMU_AUDIO_STS (AONSYS_REG_BASE + 0x20c)
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#define REG_AON_MEM_LP_MODE (AONSYS_REG_BASE + 0x210)
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#define REG_AON_C910_DBG_MASK (AONSYS_REG_BASE + 0x214)
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#define REG_AON_C910_L2CACHE (AONSYS_REG_BASE + 0x218)
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#define REG_AON_BISR_CTRL (AONSYS_REG_BASE + 0x220)
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#define REG_AON_EFUSE_PRELOAD_DONE (AONSYS_REG_BASE + 0x224)
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#define REG_AON_GPIO_RTE (AONSYS_REG_BASE + 0x228)
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#define REG_AON_PLL_DSKEW_LOCK (AONSYS_REG_BASE + 0x22c)
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#define REG_AON_SRAM_AXI_CFG (AONSYS_REG_BASE + 0x230)
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#define REG_AON_SRAM_AXI_ST (AONSYS_REG_BASE + 0x234)
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#define REG_AON_SRAM_AXI_ERR_STS_0 (AONSYS_REG_BASE + 0x238)
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#define REG_AON_SRAM_AXI_ERR_STS_1 (AONSYS_REG_BASE + 0x23c)
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#define REG_AON_SRAM_AXI_ERR_STS_2 (AONSYS_REG_BASE + 0x240)
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#define REG_AON_SRAM_AXI_ERR_STS_3 (AONSYS_REG_BASE + 0x244)
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#define REG_AON_SRAM_AXI_ERR_STS_4 (AONSYS_REG_BASE + 0x248)
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#define REG_AON_SE_MUX_LOCK (AONSYS_REG_BASE + 0x24c)
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#define REG_AON_CPU_DBG_DIS_LOCK (AONSYS_REG_BASE + 0x270)
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#define REG_AON_RESERVED_REG_4 (AONSYS_REG_BASE + 0x300)
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#define REG_AON_RESERVED_REG_5 (AONSYS_REG_BASE + 0x304)
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#define REG_AON_RESERVED_REG_6 (AONSYS_REG_BASE + 0x308)
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#define REG_AON_RESERVED_REG_7 (AONSYS_REG_BASE + 0x30c)
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#define REG_AON_RESERVED_REG_8 (AONSYS_REG_BASE + 0x400)
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#define REG_AON_RESERVED_REG_9 (AONSYS_REG_BASE + 0x404)
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#define REG_AON_RESERVED_REG_10 (AONSYS_REG_BASE + 0x408)
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#define REG_AON_RESERVED_REG_11 (AONSYS_REG_BASE + 0x40c)
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#define REG_AON_RESERVED_REG_12 (AONSYS_REG_BASE + 0x500)
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#define REG_AON_RESERVED_REG_13 (AONSYS_REG_BASE + 0x504)
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#define REG_AON_RESERVED_REG_14 (AONSYS_REG_BASE + 0x508)
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#define REG_AON_RESERVED_REG_15 (AONSYS_REG_BASE + 0x50c)
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#define REG_AON_RESERVED_REG_16 (AONSYS_REG_BASE + 0x600)
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#define REG_AON_RESERVED_REG_17 (AONSYS_REG_BASE + 0x604)
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#define REG_AON_RESERVED_REG_18 (AONSYS_REG_BASE + 0x608)
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#define REG_AON_RESERVED_REG_19 (AONSYS_REG_BASE + 0x60c)
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#define CPU_LP_MODE_DFLT_VAL 0x3ff
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#define CHIP_LP_MODE_DFLT_VAL 0x0
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#define AO_SERAM_TRN_DFLT_VAL 0x0
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#define AO_SERAM_INT_DFLT_VAL 0x0
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#define STR_SERAM_TRN_DFLT_VAL 0x0
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#define STR_SERAM_INT_DFLT_VAL 0x0
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#define STR_INDICATOR_0_DFLT_VAL 0x0
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#define STR_INDICATOR_1_DFLT_VAL 0x0
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#define STR_INDICATOR_2_DFLT_VAL 0x0
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#define STR_INDICATOR_3_DFLT_VAL 0x0
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#define PVTC_WR_LOCK_DFLT_VAL 0x0
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#define PVTC_TS_ALARM_DFLT_VAL 0x0
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#define PVTC_VM_ALARM_DFLT_VAL 0x0
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#define PVTC_PD_ALARM_DFLT_VAL 0x0
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#define E902_CNT_CLR_DFLT_VAL 0x0
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#define E902_RST_ADDR_DFLT_VAL 0xffef8000
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#define C906_RST_ADDR_L_DFLT_VAL 0xc0000000
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#define C906_RST_ADDR_H_DFLT_VAL 0xff
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#define RESERVED_REG_0_DFLT_VAL 0x0
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#define RESERVED_REG_1_DFLT_VAL 0x0
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#define RESERVED_REG_2_DFLT_VAL 0x0
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#define RESERVED_REG_3_DFLT_VAL 0x0
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#define AON_AHB_ADEXT_DFLT_VAL 0x0
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#define RC_EN_DFLT_VAL 0x1
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#define RC_FCAL_DFLT_VAL 0x77f
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#define RC_MODE_DFLT_VAL 0x1
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#define RC_READY_DFLT_VAL 0x0
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#define ISO_CFG_DFLT_VAL 0x0
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#define OCRAM_ERR_DFLT_VAL 0x0
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#define TIMER_LINK_DFLT_VAL 0x0
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#define PD_REQ_DFLT_VAL 0x0
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#define PD_ISO_EN_SET_DFLT_VAL 0x0
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#define PD_ISO_EN_CLR_DFLT_VAL 0x0
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#define PD_SW_EN_SET_DFLT_VAL 0x0
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#define PD_SW_EN_CLR_DFLT_VAL 0x0
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#define PD_SW_ACK_DFLT_VAL 0x3fffff
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#define PD_SW_CNT_EN_DFLT_VAL 0x0
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#define PD_FSM_RST_DFLT_VAL 0x0
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#define PD_INT_MASK_DFLT_VAL 0x3fffff
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#define PD_FSM_STS_L_DFLT_VAL 0x0
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#define PD_FSM_STS_H_DFLT_VAL 0x0
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#define PD_INT_STS_DFLT_VAL 0x0
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#define PD_INT_CLR_DFLT_VAL 0x0
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#define PD_BLK0_SW_CNT_DFLT_VAL 0xff00ff
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#define PD_BLK1_SW_CNT_DFLT_VAL 0xff00ff
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#define PD_BLK2_SW_CNT_DFLT_VAL 0xff00ff
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#define PD_BLK3_SW_CNT_DFLT_VAL 0xff00ff
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#define PD_BLK4_SW_CNT_DFLT_VAL 0xff00ff
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#define PD_BLK5_SW_CNT_DFLT_VAL 0xff00ff
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#define PD_BLK6_SW_CNT_DFLT_VAL 0xff00ff
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#define PD_BLK7_SW_CNT_DFLT_VAL 0xff00ff
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#define PD_BLK8_SW_CNT_DFLT_VAL 0xff00ff
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#define PD_BLK9_SW_CNT_DFLT_VAL 0xff00ff
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#define PD_BLK10_SW_CNT_DFLT_VAL 0xff00ff
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#define PD_BLK0_INTV_CNT_DFLT_VAL 0xff0ffff
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#define PD_BLK1_INTV_CNT_DFLT_VAL 0xff0ffff
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#define PD_BLK2_INTV_CNT_DFLT_VAL 0xff0ffff
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#define PD_BLK3_INTV_CNT_DFLT_VAL 0xff0ffff
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#define PD_BLK4_INTV_CNT_DFLT_VAL 0xff0ffff
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#define PD_BLK5_INTV_CNT_DFLT_VAL 0xff0ffff
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#define PD_BLK6_INTV_CNT_DFLT_VAL 0xff0ffff
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#define PD_BLK7_INTV_CNT_DFLT_VAL 0xff0ffff
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#define PD_BLK8_INTV_CNT_DFLT_VAL 0xff0ffff
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#define PD_BLK9_INTV_CNT_DFLT_VAL 0xff0ffff
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#define PD_BLK10_INTV_CNT_DFLT_VAL 0xff0ffff
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#define AUDIO_PMU_REQ_DFLT_VAL 0x0
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#define AUDIO_PMU_STS_DFLT_VAL 0x0
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#define AUDIO_PMU_INTR_DFLT_VAL 0x0
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#define PMU_AUDIO_REQ_DFLT_VAL 0x0
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#define PMU_AUDIO_STS_DFLT_VAL 0x0
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#define MEM_LP_MODE_DFLT_VAL 0x0
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#define C910_DBG_MASK_DFLT_VAL 0x0
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#define C910_L2CACHE_DFLT_VAL 0x0
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#define BISR_CTRL_DFLT_VAL 0x0
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#define EFUSE_PRELOAD_DONE_DFLT_VAL 0x0
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#define GPIO_RTE_DFLT_VAL 0x0
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#define PLL_DSKEW_LOCK_DFLT_VAL 0x0
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#define SRAM_AXI_CFG_DFLT_VAL 0x0
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#define SRAM_AXI_ST_DFLT_VAL 0x0
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#define SRAM_AXI_ERR_STS_0_DFLT_VAL 0x0
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#define SRAM_AXI_ERR_STS_1_DFLT_VAL 0x0
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#define SRAM_AXI_ERR_STS_2_DFLT_VAL 0x0
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#define SRAM_AXI_ERR_STS_3_DFLT_VAL 0x0
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#define SRAM_AXI_ERR_STS_4_DFLT_VAL 0x0
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#define SE_MUX_LOCK_DFLT_VAL 0x0
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#define CPU_DBG_DIS_LOCK_DFLT_VAL 0x0
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#define RESERVED_REG_4_DFLT_VAL 0x0
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#define RESERVED_REG_5_DFLT_VAL 0x0
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#define RESERVED_REG_6_DFLT_VAL 0x0
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#define RESERVED_REG_7_DFLT_VAL 0x0
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#define RESERVED_REG_8_DFLT_VAL 0x0
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#define RESERVED_REG_9_DFLT_VAL 0x0
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#define RESERVED_REG_10_DFLT_VAL 0x0
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#define RESERVED_REG_11_DFLT_VAL 0x0
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#define RESERVED_REG_12_DFLT_VAL 0x0
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#define RESERVED_REG_13_DFLT_VAL 0x0
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#define RESERVED_REG_14_DFLT_VAL 0x0
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#define RESERVED_REG_15_DFLT_VAL 0x0
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#define RESERVED_REG_16_DFLT_VAL 0x0
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#define RESERVED_REG_17_DFLT_VAL 0x0
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#define RESERVED_REG_18_DFLT_VAL 0x0
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#define RESERVED_REG_19_DFLT_VAL 0x0
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#endif
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