//------------------------------------------------------------
// DONOT MODIFY THIS FILE
// generated by JISHENGJU automatically
//------------------------------------------------------------

#ifndef DDR_SYSREG_REG_SW_H
#define DDR_SYSREG_REG_SW_H

typedef union {
    struct {
        unsigned int rg_broadcast_mode : 1; // [0]
        unsigned int rg_ddrc_32en : 1; // [1]
        unsigned int RESERVED_0 : 2; // [3:2]
        unsigned int rg_ctl_ddr_usw_rst_reg : 28; // [31:4]
    };
    unsigned int u32;
} DDR_SYSREG_REG_SW_DDR_CFG0_U;

typedef union {
    struct {
        unsigned int rg_axi_clk_free_en : 5; // [4:0]
        unsigned int RESERVED_2 : 3; // [7:5]
        unsigned int rg_ddrc_ck_free : 1; // [8]
        unsigned int RESERVED_1 : 7; // [15:9]
        unsigned int rg_ddrc_auto_sr_dly : 6; // [21:16]
        unsigned int RESERVED_0 : 10; // [31:22]
    };
    unsigned int u32;
} DDR_SYSREG_REG_SW_DDR_CFG1_U;

typedef union {
    struct {
        unsigned int ddr_pll_refdiv : 6; // [5:0]
        unsigned int RESERVED_2 : 2; // [7:6]
        unsigned int ddr_pll_fbdiv : 12; // [19:8]
        unsigned int ddr_pll_postdiv1 : 3; // [22:20]
        unsigned int RESERVED_1 : 1; // [23]
        unsigned int ddr_pll_postdiv2 : 3; // [26:24]
        unsigned int RESERVED_0 : 5; // [31:27]
    };
    unsigned int u32;
} DDR_SYSREG_REG_SW_DDR_PLL_CFG0_U;

typedef union {
    struct {
        unsigned int ddr_pll_frac : 24; // [23:0]
        unsigned int ddr_pll_dsmpd : 1; // [24]
        unsigned int ddr_pll_dacpd : 1; // [25]
        unsigned int RESERVED_1 : 1; // [26]
        unsigned int ddr_pll_fout4phasepd : 1; // [27]
        unsigned int ddr_pll_foutpostdivpd : 1; // [28]
        unsigned int RESERVED_0 : 1; // [29]
        unsigned int ddr_pll_rst : 1; // [30]
        unsigned int ddr_pll_bypass : 1; // [31]
    };
    unsigned int u32;
} DDR_SYSREG_REG_SW_DDR_PLL_CFG1_U;

typedef union {
    struct {
        unsigned int ddr_pll_dskewcalout : 12; // [11:0]
        unsigned int ddr_pll_dskewcalin : 12; // [23:12]
        unsigned int ddr_pll_dskewcalcnt : 3; // [26:24]
        unsigned int ddr_pll_dskewfastcal : 1; // [27]
        unsigned int ddr_pll_dskewcalen : 1; // [28]
        unsigned int ddr_pll_dskewcalbyp : 1; // [29]
        unsigned int ddr_pll_dskewcallock : 1; // [30]
        unsigned int RESERVED_0 : 1; // [31]
    };
    unsigned int u32;
} DDR_SYSREG_REG_SW_DDR_PLL_CFG2_U;

typedef union {
    struct {
        unsigned int rg_ctl_ddr_pll_clk_en : 1; // [0]
        unsigned int RESERVED_1 : 6; // [6:1]
        unsigned int ddr_pll_deskewcal_rdy : 1; // [7]
        unsigned int ddr_pll_deskewcal_sw_en : 1; // [8]
        unsigned int ddr_pll_deskewcal_pulse : 1; // [9]
        unsigned int ddr_pll_callock_cnt_en : 1; // [10]
        unsigned int RESERVED_0 : 1; // [11]
        unsigned int ddr_pll_callock_cnt : 20; // [31:12]
    };
    unsigned int u32;
} DDR_SYSREG_REG_SW_DDR_PLL_CFG3_U;

typedef union {
    struct {
        unsigned int rg_sta_ddr_pll_lock : 1; // [0]
        unsigned int RESERVED_0 : 31; // [31:1]
    };
    unsigned int u32;
} DDR_SYSREG_REG_SW_DDR_PLL_STS_U;

typedef union {
    struct {
        unsigned int ddr_dfi_init_start : 2; // [1:0]
        unsigned int ddr_dfi_init_complete : 2; // [3:2]
        unsigned int ddr_ctl_idle : 2; // [5:4]
        unsigned int RESERVED_0 : 26; // [31:6]
    };
    unsigned int u32;
} DDR_SYSREG_REG_SW_DDR_STS0_U;

typedef union {
    struct {
        unsigned int pll_test_clk_freq_stat : 32; // [31:0]
    };
    unsigned int u32;
} DDR_SYSREG_REG_SW_DDR_PLL_MON_STS_U;

typedef union {
    struct {
        unsigned int pll_test_clk_sample_en : 1; // [0]
        unsigned int RESERVED_1 : 3; // [3:1]
        unsigned int pll_test_clk_sel : 4; // [7:4]
        unsigned int RESERVED_0 : 24; // [31:8]
    };
    unsigned int u32;
} DDR_SYSREG_REG_SW_DDR_PLL_MON_CFG_U;

typedef union {
    struct {
        unsigned int hif_mrr_data : 32; // [31:0]
    };
    unsigned int u32;
} DDR_SYSREG_REG_SW_MRR_STS_CH0_U;

typedef union {
    struct {
        unsigned int hif_mrr_data_dch1 : 32; // [31:0]
    };
    unsigned int u32;
} DDR_SYSREG_REG_SW_MRR_STS_CH1_U;

typedef union {
    struct {
        unsigned int wr_credit_cnt : 7; // [6:0]
        unsigned int RESERVED_2 : 1; // [7]
        unsigned int lpr_credit_cnt : 7; // [14:8]
        unsigned int RESERVED_1 : 1; // [15]
        unsigned int hpr_credit_cnt : 7; // [22:16]
        unsigned int RESERVED_0 : 8; // [30:23]
        unsigned int mon_clr : 1; // [31]
    };
    unsigned int u32;
} DDR_SYSREG_REG_SW_DDR_STS1_U;

typedef union {
    struct {
        unsigned int wr_credit_cnt_dch1 : 7; // [6:0]
        unsigned int RESERVED_2 : 1; // [7]
        unsigned int lpr_credit_cnt_dch1 : 7; // [14:8]
        unsigned int RESERVED_1 : 1; // [15]
        unsigned int hpr_credit_cnt_dch1 : 7; // [22:16]
        unsigned int RESERVED_0 : 9; // [31:23]
    };
    unsigned int u32;
} DDR_SYSREG_REG_SW_DDR_STS2_U;

typedef union {
    struct {
        unsigned int dfi0_error_info_dch1 : 4; // [3:0]
        unsigned int dfi0_error_dch1 : 1; // [4]
        unsigned int RESERVED_2 : 3; // [7:5]
        unsigned int dfi0_error_info : 4; // [11:8]
        unsigned int dfi0_error : 1; // [12]
        unsigned int RESERVED_1 : 3; // [15:13]
        unsigned int derate_temp_limit_intr_fault_dch1 : 1; // [16]
        unsigned int derate_temp_limit_intr_dch1 : 1; // [17]
        unsigned int derate_temp_limit_intr_fault : 1; // [18]
        unsigned int derate_temp_limit_intr : 1; // [19]
        unsigned int RESERVED_0 : 12; // [31:20]
    };
    unsigned int u32;
} DDR_SYSREG_REG_SW_DFI0_INFO_U;

typedef union {
    struct {
        unsigned int i_slp : 1; // [0]
        unsigned int i_dslp : 1; // [1]
        unsigned int i_sd : 1; // [2]
        unsigned int RESERVED_2 : 1; // [3]
        unsigned int i_slp_dcb : 1; // [4]
        unsigned int i_dslp_dcb : 1; // [5]
        unsigned int i_sd_dcb : 1; // [6]
        unsigned int RESERVED_1 : 9; // [15:7]
        unsigned int o_iccm_pudelay_u0 : 1; // [16]
        unsigned int o_iccm_pudelay_u1 : 1; // [17]
        unsigned int o_dccm_pudelay_u0 : 1; // [18]
        unsigned int o_dccm_pudelay_u1 : 1; // [19]
        unsigned int o_dccm_pudelay_u2 : 1; // [20]
        unsigned int o_dccm_pudelay_u3 : 1; // [21]
        unsigned int o_iccm_pudelay_u0_dcb : 1; // [22]
        unsigned int o_iccm_pudelay_u1_dcb : 1; // [23]
        unsigned int o_dccm_pudelay_u0_dcb : 1; // [24]
        unsigned int o_dccm_pudelay_u1_dcb : 1; // [25]
        unsigned int o_dccm_pudelay_u2_dcb : 1; // [26]
        unsigned int o_dccm_pudelay_u3_dcb : 1; // [27]
        unsigned int RESERVED_0 : 4; // [31:28]
    };
    unsigned int u32;
} DDR_SYSREG_REG_SW_DDR_SRAM_CFG_U;

typedef union {
    struct {
        unsigned int dfi1_error_info_dch1 : 4; // [3:0]
        unsigned int dfi1_error_dch1 : 1; // [4]
        unsigned int RESERVED_1 : 3; // [7:5]
        unsigned int dfi1_error_info : 4; // [11:8]
        unsigned int dfi1_error : 1; // [12]
        unsigned int RESERVED_0 : 19; // [31:13]
    };
    unsigned int u32;
} DDR_SYSREG_REG_SW_DFI1_INFO_U;

typedef union {
    struct {
        unsigned int BypassOutEnAC : 24; // [23:0]
        unsigned int RESERVED_0 : 7; // [30:24]
        unsigned int BypassModeEnAC : 1; // [31]
    };
    unsigned int u32;
} DDR_SYSREG_REG_SW_BPAC_CFG0_U;

typedef union {
    struct {
        unsigned int BypassOutDataAC : 24; // [23:0]
        unsigned int RESERVED_0 : 8; // [31:24]
    };
    unsigned int u32;
} DDR_SYSREG_REG_SW_BPAC_CFG1_U;

typedef union {
    struct {
        unsigned int BypassInDataAC : 24; // [23:0]
        unsigned int RESERVED_0 : 8; // [31:24]
    };
    unsigned int u32;
} DDR_SYSREG_REG_SW_BPAC_STS_U;

typedef union {
    struct {
        unsigned int BypassOutEnDAT_L : 24; // [23:0]
        unsigned int RESERVED_0 : 7; // [30:24]
        unsigned int BypassModeEnDAT : 1; // [31]
    };
    unsigned int u32;
} DDR_SYSREG_REG_SW_BPDA_CFG0_U;

typedef union {
    struct {
        unsigned int BypassOutEnDAT_H : 24; // [23:0]
        unsigned int RESERVED_0 : 8; // [31:24]
    };
    unsigned int u32;
} DDR_SYSREG_REG_SW_BPDA_CFG1_U;

typedef union {
    struct {
        unsigned int BypassOutDataDAT_L : 24; // [23:0]
        unsigned int RESERVED_0 : 8; // [31:24]
    };
    unsigned int u32;
} DDR_SYSREG_REG_SW_BPDA_CFG2_U;

typedef union {
    struct {
        unsigned int BypassOutDataDAT_H : 24; // [23:0]
        unsigned int RESERVED_0 : 8; // [31:24]
    };
    unsigned int u32;
} DDR_SYSREG_REG_SW_BPDA_CFG3_U;

typedef union {
    struct {
        unsigned int BypassInDataDAT_L : 24; // [23:0]
        unsigned int RESERVED_0 : 8; // [31:24]
    };
    unsigned int u32;
} DDR_SYSREG_REG_SW_BPDA_STS0_U;

typedef union {
    struct {
        unsigned int BypassInDataDAT_H : 24; // [23:0]
        unsigned int RESERVED_0 : 8; // [31:24]
    };
    unsigned int u32;
} DDR_SYSREG_REG_SW_BPDA_STS1_U;

typedef union {
    struct {
        unsigned int BypassInDataMASTER : 2; // [1:0]
        unsigned int RESERVED_2 : 2; // [3:2]
        unsigned int BypassOutDataMASTER : 2; // [5:4]
        unsigned int RESERVED_1 : 2; // [7:6]
        unsigned int BypassOutEnMASTER : 2; // [9:8]
        unsigned int RESERVED_0 : 21; // [30:10]
        unsigned int BypassModeEnMASTER : 1; // [31]
    };
    unsigned int u32;
} DDR_SYSREG_REG_SW_BPMA_CFG_U;

typedef union {
    struct {
        unsigned int BypassOutEnAC_dch : 24; // [23:0]
        unsigned int RESERVED_0 : 7; // [30:24]
        unsigned int BypassModeEnAC_dch : 1; // [31]
    };
    unsigned int u32;
} DDR_SYSREG_REG_SW_BPAC_DCH_CFG0_U;

typedef union {
    struct {
        unsigned int BypassOutDataAC_dch : 24; // [23:0]
        unsigned int RESERVED_0 : 8; // [31:24]
    };
    unsigned int u32;
} DDR_SYSREG_REG_SW_BPAC_DCH_CFG1_U;

typedef union {
    struct {
        unsigned int BypassInDataAC_dch : 24; // [23:0]
        unsigned int RESERVED_0 : 8; // [31:24]
    };
    unsigned int u32;
} DDR_SYSREG_REG_SW_BPAC_DCH_STS_U;

typedef union {
    struct {
        unsigned int BypassOutEnDAT_dch_L : 24; // [23:0]
        unsigned int RESERVED_0 : 7; // [30:24]
        unsigned int BypassModeEnDAT_dch : 1; // [31]
    };
    unsigned int u32;
} DDR_SYSREG_REG_SW_BPDA_DCH_CFG0_U;

typedef union {
    struct {
        unsigned int BypassOutEnDAT_dch_H : 24; // [23:0]
        unsigned int RESERVED_0 : 8; // [31:24]
    };
    unsigned int u32;
} DDR_SYSREG_REG_SW_BPDA_DCH_CFG1_U;

typedef union {
    struct {
        unsigned int BypassOutDataDAT_dch_L : 24; // [23:0]
        unsigned int RESERVED_0 : 8; // [31:24]
    };
    unsigned int u32;
} DDR_SYSREG_REG_SW_BPDA_DCH_CFG2_U;

typedef union {
    struct {
        unsigned int BypassOutDataDAT_dch_H : 24; // [23:0]
        unsigned int RESERVED_0 : 8; // [31:24]
    };
    unsigned int u32;
} DDR_SYSREG_REG_SW_BPDA_DCH_CFG3_U;

typedef union {
    struct {
        unsigned int BypassInDataDAT_dch_L : 24; // [23:0]
        unsigned int RESERVED_0 : 8; // [31:24]
    };
    unsigned int u32;
} DDR_SYSREG_REG_SW_BPDA_DCH_STS0_U;

typedef union {
    struct {
        unsigned int BypassInDataDAT_dch_H : 24; // [23:0]
        unsigned int RESERVED_0 : 8; // [31:24]
    };
    unsigned int u32;
} DDR_SYSREG_REG_SW_BPDA_DCH_STS1_U;

typedef union {
    struct {
        unsigned int BypassInDataMASTER_dch : 2; // [1:0]
        unsigned int RESERVED_2 : 2; // [3:2]
        unsigned int BypassOutDataMASTER_dch : 2; // [5:4]
        unsigned int RESERVED_1 : 2; // [7:6]
        unsigned int BypassOutEnMASTER_dch : 2; // [9:8]
        unsigned int RESERVED_0 : 21; // [30:10]
        unsigned int BypassModeEnMASTER_dch : 1; // [31]
    };
    unsigned int u32;
} DDR_SYSREG_REG_SW_BPMA_DCH_CFG_U;

typedef union {
    volatile DDR_SYSREG_REG_SW_DDR_CFG0_U ddr_sysreg_registers_struct_ddr_cfg0;    // 0x0
    volatile DDR_SYSREG_REG_SW_DDR_CFG1_U ddr_sysreg_registers_struct_ddr_cfg1;    // 0x4
    volatile DDR_SYSREG_REG_SW_DDR_PLL_CFG0_U ddr_sysreg_registers_struct_ddr_pll_cfg0;    // 0x8
    volatile DDR_SYSREG_REG_SW_DDR_PLL_CFG1_U ddr_sysreg_registers_struct_ddr_pll_cfg1;    // 0xc
    volatile DDR_SYSREG_REG_SW_DDR_PLL_CFG2_U ddr_sysreg_registers_struct_ddr_pll_cfg2;    // 0x10
    volatile DDR_SYSREG_REG_SW_DDR_PLL_CFG3_U ddr_sysreg_registers_struct_ddr_pll_cfg3;    // 0x14
    volatile DDR_SYSREG_REG_SW_DDR_PLL_STS_U ddr_sysreg_registers_struct_ddr_pll_sts;    // 0x18
    volatile DDR_SYSREG_REG_SW_DDR_STS0_U ddr_sysreg_registers_struct_ddr_sts0;    // 0x1c
    volatile DDR_SYSREG_REG_SW_DDR_PLL_MON_STS_U ddr_sysreg_registers_struct_ddr_pll_mon_sts;    // 0x20
    volatile DDR_SYSREG_REG_SW_DDR_PLL_MON_CFG_U ddr_sysreg_registers_struct_ddr_pll_mon_cfg;    // 0x24
    volatile DDR_SYSREG_REG_SW_MRR_STS_CH0_U ddr_sysreg_registers_struct_mrr_sts_ch0;    // 0x2c
    volatile DDR_SYSREG_REG_SW_MRR_STS_CH1_U ddr_sysreg_registers_struct_mrr_sts_ch1;    // 0x30
    volatile DDR_SYSREG_REG_SW_DDR_STS1_U ddr_sysreg_registers_struct_ddr_sts1;    // 0x34
    volatile DDR_SYSREG_REG_SW_DDR_STS2_U ddr_sysreg_registers_struct_ddr_sts2;    // 0x38
    volatile DDR_SYSREG_REG_SW_DFI0_INFO_U ddr_sysreg_registers_struct_dfi0_info;    // 0x3c
    volatile DDR_SYSREG_REG_SW_DDR_SRAM_CFG_U ddr_sysreg_registers_struct_ddr_sram_cfg;    // 0x40
    volatile DDR_SYSREG_REG_SW_DFI1_INFO_U ddr_sysreg_registers_struct_dfi1_info;    // 0x44
    volatile DDR_SYSREG_REG_SW_BPAC_CFG0_U ddr_sysreg_registers_struct_bpac_cfg0;    // 0x48
    volatile DDR_SYSREG_REG_SW_BPAC_CFG1_U ddr_sysreg_registers_struct_bpac_cfg1;    // 0x4c
    volatile DDR_SYSREG_REG_SW_BPAC_STS_U ddr_sysreg_registers_struct_bpac_sts;    // 0x50
    volatile DDR_SYSREG_REG_SW_BPDA_CFG0_U ddr_sysreg_registers_struct_bpda_cfg0;    // 0x54
    volatile DDR_SYSREG_REG_SW_BPDA_CFG1_U ddr_sysreg_registers_struct_bpda_cfg1;    // 0x58
    volatile DDR_SYSREG_REG_SW_BPDA_CFG2_U ddr_sysreg_registers_struct_bpda_cfg2;    // 0x5c
    volatile DDR_SYSREG_REG_SW_BPDA_CFG3_U ddr_sysreg_registers_struct_bpda_cfg3;    // 0x60
    volatile DDR_SYSREG_REG_SW_BPDA_STS0_U ddr_sysreg_registers_struct_bpda_sts0;    // 0x64
    volatile DDR_SYSREG_REG_SW_BPDA_STS1_U ddr_sysreg_registers_struct_bpda_sts1;    // 0x68
    volatile DDR_SYSREG_REG_SW_BPMA_CFG_U ddr_sysreg_registers_struct_bpma_cfg;    // 0x6c
    volatile DDR_SYSREG_REG_SW_BPAC_DCH_CFG0_U ddr_sysreg_registers_struct_bpac_dch_cfg0;    // 0x70
    volatile DDR_SYSREG_REG_SW_BPAC_DCH_CFG1_U ddr_sysreg_registers_struct_bpac_dch_cfg1;    // 0x74
    volatile DDR_SYSREG_REG_SW_BPAC_DCH_STS_U ddr_sysreg_registers_struct_bpac_dch_sts;    // 0x78
    volatile DDR_SYSREG_REG_SW_BPDA_DCH_CFG0_U ddr_sysreg_registers_struct_bpda_dch_cfg0;    // 0x7c
    volatile DDR_SYSREG_REG_SW_BPDA_DCH_CFG1_U ddr_sysreg_registers_struct_bpda_dch_cfg1;    // 0x80
    volatile DDR_SYSREG_REG_SW_BPDA_DCH_CFG2_U ddr_sysreg_registers_struct_bpda_dch_cfg2;    // 0x84
    volatile DDR_SYSREG_REG_SW_BPDA_DCH_CFG3_U ddr_sysreg_registers_struct_bpda_dch_cfg3;    // 0x88
    volatile DDR_SYSREG_REG_SW_BPDA_DCH_STS0_U ddr_sysreg_registers_struct_bpda_dch_sts0;    // 0x8c
    volatile DDR_SYSREG_REG_SW_BPDA_DCH_STS1_U ddr_sysreg_registers_struct_bpda_dch_sts1;    // 0x90
    volatile DDR_SYSREG_REG_SW_BPMA_DCH_CFG_U ddr_sysreg_registers_struct_bpma_dch_cfg;    // 0x94
} DDR_SYSREG_REG_SW_REG_S;
//DDR_SYSREG_REG_SW_REG_S ddr_sysreg;
#endif

