//------------------------------------------------------------
// DONOT MODIFY THIS FILE
// generated by JISHENGJU automatically
//------------------------------------------------------------

#ifndef AONSYS_RSTGEN_REG_OFFSET_DEFINE_H
#define AONSYS_RSTGEN_REG_OFFSET_DEFINE_H

#define AONSYS_RSTGEN_REG_BASE	0xFFFFF44000

#define REG_AON_RST_CNT             (AONSYS_RSTGEN_REG_BASE + 0x0   )
#define REG_AON_SYS_RST_CFG         (AONSYS_RSTGEN_REG_BASE + 0x10  )
#define REG_AON_RTC_RST_CFG         (AONSYS_RSTGEN_REG_BASE + 0x14  )
#define REG_AON_AOGPIO_RST_CFG      (AONSYS_RSTGEN_REG_BASE + 0x18  )
#define REG_AON_AOI2C_RST_CFG       (AONSYS_RSTGEN_REG_BASE + 0x1c  )
#define REG_AON_PVTC_RST_CFG        (AONSYS_RSTGEN_REG_BASE + 0x20  )
#define REG_AON_E902_RST_CFG        (AONSYS_RSTGEN_REG_BASE + 0x24  )
#define REG_AON_AOTIMER_RST_CFG     (AONSYS_RSTGEN_REG_BASE + 0x28  )
#define REG_AON_AOWDT_RST_CFG       (AONSYS_RSTGEN_REG_BASE + 0x2c  )
#define REG_AON_APSYS_RST_CFG       (AONSYS_RSTGEN_REG_BASE + 0x30  )
#define REG_AON_NPUSYS_RST_CFG      (AONSYS_RSTGEN_REG_BASE + 0x34  )
#define REG_AON_DDRSYS_RST_CFG      (AONSYS_RSTGEN_REG_BASE + 0x38  )
#define REG_AON_AUDIO_RST_CFG       (AONSYS_RSTGEN_REG_BASE + 0x3c  )
#define REG_AON_BISR_RST_CFG        (AONSYS_RSTGEN_REG_BASE + 0x50  )
#define REG_AON_DSP0_RST_CFG        (AONSYS_RSTGEN_REG_BASE + 0x54  )
#define REG_AON_DSP1_RST_CFG        (AONSYS_RSTGEN_REG_BASE + 0x58  )
#define REG_AON_GPU_RST_CFG         (AONSYS_RSTGEN_REG_BASE + 0x5c  )
#define REG_AON_VDEC_RST_CFG        (AONSYS_RSTGEN_REG_BASE + 0x60  )
#define REG_AON_VENC_RST_CFG        (AONSYS_RSTGEN_REG_BASE + 0x64  )
#define REG_AON_ADC_RST_CFG         (AONSYS_RSTGEN_REG_BASE + 0x70  )
#define REG_AON_AUDGPIO_RST_CFG     (AONSYS_RSTGEN_REG_BASE + 0x74  )
#define REG_AON_AOUART_RST_CFG      (AONSYS_RSTGEN_REG_BASE + 0x78  )
#define REG_AON_RST_CLR_0           (AONSYS_RSTGEN_REG_BASE + 0x100 )
#define REG_AON_RST_CLR_1           (AONSYS_RSTGEN_REG_BASE + 0x104 )
#define REG_AON_RST_CLR_2           (AONSYS_RSTGEN_REG_BASE + 0x108 )
#define REG_AON_RST_CLR_3           (AONSYS_RSTGEN_REG_BASE + 0x10c )
#define REG_AON_RST_CLR_4           (AONSYS_RSTGEN_REG_BASE + 0x110 )
#define REG_AON_RST_STS_0           (AONSYS_RSTGEN_REG_BASE + 0x120 )
#define REG_AON_RST_STS_1           (AONSYS_RSTGEN_REG_BASE + 0x124 )
#define REG_AON_RST_STS_2           (AONSYS_RSTGEN_REG_BASE + 0x128 )
#define REG_AON_RST_STS_3           (AONSYS_RSTGEN_REG_BASE + 0x12c )
#define REG_AON_RST_STS_4           (AONSYS_RSTGEN_REG_BASE + 0x130 )
#define REG_AON_RST_REQ_EN_0        (AONSYS_RSTGEN_REG_BASE + 0x140 )
#define REG_AON_RST_REQ_EN_1        (AONSYS_RSTGEN_REG_BASE + 0x144 )
#define REG_AON_RST_REQ_EN_2        (AONSYS_RSTGEN_REG_BASE + 0x148 )
#define REG_AON_RST_REQ_EN_3        (AONSYS_RSTGEN_REG_BASE + 0x14c )
#define REG_AON_SRAM_AXI_RST_CFG    (AONSYS_RSTGEN_REG_BASE + 0x11f4)
#define REG_AON_SE_RST_CFG          (AONSYS_RSTGEN_REG_BASE + 0x160 )

#define RST_CNT_DFLT_VAL              0xf0f
#define SYS_RST_CFG_DFLT_VAL          0x0
#define RTC_RST_CFG_DFLT_VAL          0x3
#define AOGPIO_RST_CFG_DFLT_VAL       0x3
#define AOI2C_RST_CFG_DFLT_VAL        0x1
#define PVTC_RST_CFG_DFLT_VAL         0x1
#define E902_RST_CFG_DFLT_VAL         0x2
#define AOTIMER_RST_CFG_DFLT_VAL      0x3
#define AOWDT_RST_CFG_DFLT_VAL        0x1
#define APSYS_RST_CFG_DFLT_VAL        0x1
#define NPUSYS_RST_CFG_DFLT_VAL       0x1
#define DDRSYS_RST_CFG_DFLT_VAL       0x1
#define AUDIO_RST_CFG_DFLT_VAL        0x0
#define BISR_RST_CFG_DFLT_VAL         0x3
#define DSP0_RST_CFG_DFLT_VAL         0x1
#define DSP1_RST_CFG_DFLT_VAL         0x1
#define GPU_RST_CFG_DFLT_VAL          0x1
#define VDEC_RST_GEN_RST_CFG_DFLT_VAL         0x1
#define VENC_RST_CFG_DFLT_VAL         0x1
#define ADC_RST_CFG_DFLT_VAL          0x1
#define AUDGPIO_RST_CFG_DFLT_VAL      0x3
#define AOUART_RST_CFG_DFLT_VAL       0x3
#define RST_CLR_0_DFLT_VAL            0x0
#define RST_CLR_1_DFLT_VAL            0x0
#define RST_CLR_2_DFLT_VAL            0x0
#define RST_CLR_3_DFLT_VAL            0x0
#define RST_CLR_4_DFLT_VAL            0x0
#define RST_STS_0_DFLT_VAL            0x0
#define RST_STS_1_DFLT_VAL            0x0
#define RST_STS_2_DFLT_VAL            0x0
#define RST_STS_3_DFLT_VAL            0x0
#define RST_STS_4_DFLT_VAL            0x0
#define RST_REQ_EN_0_DFLT_VAL         0x11100
#define RST_REQ_EN_1_DFLT_VAL         0xbb000000
#define RST_REQ_EN_2_DFLT_VAL         0x0
#define RST_REQ_EN_3_DFLT_VAL         0x0
#define SRAM_AXI_RST_CFG_DFLT_VAL     0x5f
#define SE_RST_CFG_DFLT_VAL           0x1


#endif
