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Linux_SDK_V1.0.3

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thead_admin
2023-01-04 13:12:02 +08:00
parent 0c8e009c3a
commit 02deb8b059
66 changed files with 32487 additions and 145 deletions
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171
lib/sec_library/include/aes.h
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@@ -1,5 +1,5 @@
/*
* Copyright (C) 2017-2021 Alibaba Group Holding Limited
* Copyright (C) 2017-2020 Alibaba Group Holding Limited
*/
/******************************************************************************
@@ -14,7 +14,7 @@
#define _DRV_AES_H_
#include <stdint.h>
#include <drv/common.h>
#include "common.h"
#ifdef __cplusplus
extern "C" {
@@ -27,10 +27,70 @@ typedef enum {
AES_KEY_LEN_BITS_256 ///< 256 Data bits
} csi_aes_key_bits_t;
typedef enum{
AES_MODE_ECB = 0,
AES_MODE_CBC = 0x20000020,
AES_MODE_CTR = 0x200001c0,
AES_MODE_CFB = 0x20000400,
AES_MODE_GCM = 0x20030040,
AES_MODE_CCM = 0x21D40040,
AES_MODE_OFB = 0x24000000,
} aes_mode_t;
#define AES_KEY_LEN_BYTES_32 32
#define AES_KEY_LEN_BYTES_24 24
#define AES_KEY_LEN_BYTES_16 16
#define AES_CRYPTO_CTRL_CBC_256 0x20000038
#define AES_CRYPTO_CTRL_CBC_192 0x20000030
#define AES_CRYPTO_CTRL_CBC_128 0x20000028
#define AES_CRYPTO_CTRL_ECB_256 0x00000018
#define AES_CRYPTO_CTRL_ECB_192 0x00000010
#define AES_CRYPTO_CTRL_ECB_128 0x00000008
#define AES_BLOCK_IV_SIZE 16
#define AES_BLOCK_TAG_SIZE 16
#define AES_BLOCK_CRYPTO_SIZE 16
#define AES_DIR_ENCRYPT 1
#define AES_DIR_DECRYPT 0
#define KEY_128_BITS 0x8
#define KEY_192_BITS 0x10
#define KEY_256_BITS 0x18
#define AES_DMA_ENABLE 1
#define AES_DMA_DISABLE 0
typedef enum{
AES_CRYPTO_ECB_256_MODE = 0,
AES_CRYPTO_ECB_192_MODE,
AES_CRYPTO_ECB_128_MODE,
AES_CRYPTO_CBC_256_MODE,
AES_CRYPTO_CBC_192_MODE,
AES_CRYPTO_CBC_128_MODE,
} csi_aes_mode_t;
typedef struct {
uint32_t busy : 1; ///< Calculate busy flag
uint32_t error : 1; ///< Calculate error flag
} csi_aes_state_t;
typedef struct {
uint32_t key_len_byte;
uint8_t key[32]; ///< Data block being processed
uint32_t sca;
uint32_t is_kdf;
uint32_t is_dma;
} csi_aes_context_t;
/**
\brief AES Ctrl Block
*/
typedef struct {
csi_aes_state_t state;
csi_aes_context_t context;
csi_dev_t dev;
void *priv;
} csi_aes_t;
@@ -97,7 +157,7 @@ csi_error_t csi_aes_ecb_decrypt(csi_aes_t *aes, void *in, void *out, uint32_t si
\param[in] iv Init vector
\return Error code \ref Csi_error_t
*/
csi_error_t csi_aes_cbc_encrypt(csi_aes_t *aes, void *in, void *out, uint32_t size, void *iv);
csi_error_t csi_aes_cbc_encrypt(csi_aes_t *aes, void *in, void *out, uint32_t size, void *iv) ;
/**
\brief AES cbc decrypt
@@ -161,10 +221,9 @@ csi_error_t csi_aes_cfb8_decrypt(csi_aes_t *aes, void *in, void *out, uint32_t s
\param[out] out Pointer to the result data
\param[in] size The source data size
\param[in] iv Init vector
\param[out] num The number of the 128-bit block we have used
\return Error code \ref csi_error_t
*/
csi_error_t csi_aes_cfb128_decrypt(csi_aes_t *aes, void *in, void *out, uint32_t size, void *iv, uint32_t *num);
csi_error_t csi_aes_cfb128_decrypt(csi_aes_t *aes, void *in, void *out, uint32_t size, void *iv);
/**
\brief AES cfb128 encrypt
@@ -173,10 +232,9 @@ csi_error_t csi_aes_cfb128_decrypt(csi_aes_t *aes, void *in, void *out, uint32_t
\param[out] out Pointer to the result data
\param[in] size The source data size
\param[in] iv Init vector
\param[out] num The number of the 128-bit block we have used
\return Error code \ref csi_error_t
*/
csi_error_t csi_aes_cfb128_encrypt(csi_aes_t *aes, void *in, void *out, uint32_t size, void *iv, uint32_t *num);
csi_error_t csi_aes_cfb128_encrypt(csi_aes_t *aes, void *in, void *out, uint32_t size, void *iv);
/**
\brief AES ofb encrypt
@@ -185,22 +243,22 @@ csi_error_t csi_aes_cfb128_encrypt(csi_aes_t *aes, void *in, void *out, uint32_t
\param[out] out Pointer to the result data
\param[in] size The source data size
\param[in] iv Init vector
\param[out] num The number of the 128-bit block we have used
\param[in] key_len key bits
\return Error code \ref csi_error_t
*/
csi_error_t csi_aes_ofb_encrypt(csi_aes_t *aes, void *in, void *out, uint32_t size, void *iv, uint32_t *num);
csi_error_t csi_aes_ofb_encrypt(csi_aes_t *aes, void *in, void *out, uint32_t size, void *iv);
/**
\brief AES ofb decrypt
\param[in] aes Handle to operate
\param[in] in Pointer to the source data
\param[out] out Pointer to the result data
\param[in] size The source data size
\param[in] iv Init vector
\param[out] num The number of the 128-bit block we have used
\return Error code \ref csi_error_t
\brief Aes ofb decrypt
\param[in] dev_aes dev_aes handle to operate
\param[in] in Pointer to the Source data
\param[out] out Pointer to the Result data
\param[in] size the Source data size
\param[in] iv init vector
\param[in] key_len key bits
\return error code \ref csi_error_t
*/
csi_error_t csi_aes_ofb_decrypt(csi_aes_t *aes, void *in, void *out, uint32_t size, void *iv, uint32_t *num);
csi_error_t csi_aes_ofb_decrypt(csi_aes_t *aes, void *in, void *out,uint32_t size, void *iv);
/**
\brief AES ctr encrypt
@@ -208,20 +266,10 @@ csi_error_t csi_aes_ofb_decrypt(csi_aes_t *aes, void *in, void *out, uint32_t si
\param[in] in Pointer to the source data
\param[out] out Pointer to the result data
\param[in] size The source data size
\param[in] nonce_counter Pointer to the 128-bit nonce and counter
\param[in] stream_block Pointer to the saved stream-block for resuming
\param[in] iv Init vector
\param[out] num The number of the 128-bit block we have used
\return Error code \ref csi_error_t
*/
csi_error_t csi_aes_ctr_encrypt(csi_aes_t *aes,
void *in,
void *out,
uint32_t size,
uint8_t nonce_counter[16],
uint8_t stream_block[16],
void *iv,
uint32_t *num);
csi_error_t csi_aes_ctr_encrypt(csi_aes_t *aes,void *in,void *out,uint32_t size,void *iv);
/**
\brief AES ctr decrypt
@@ -229,20 +277,56 @@ csi_error_t csi_aes_ctr_encrypt(csi_aes_t *aes,
\param[in] in Pointer to the source data
\param[out] out Pointer to the result data
\param[in] size The source data size
\param[in] nonce_counter Pointer to the 128-bit nonce and counter
\param[in] stream_block Pointer to the saved stream-block for resuming
\param[in] iv Init vecotr
\param[out] num The number of the 128-bit block we have used
\return Error code \ref csi_error_t
*/
csi_error_t csi_aes_ctr_decrypt(csi_aes_t *aes,
void *in,
void *out,
uint32_t size,
uint8_t nonce_counter[16],
uint8_t stream_block[16],
void *iv,
uint32_t *num);
csi_error_t csi_aes_ctr_decrypt(csi_aes_t *aes,void *in,void *out,uint32_t size,void *iv);
/**
\brief Aes gcm encrypt
\param[in] dev_aes dev_aes handle to operate
\param[in] in Pointer to the Source data
\param[out] out Pointer to the Result data
\param[in] size the Source data size
\param[in] iv init vector
\return error code \ref csi_error_t
*/
csi_error_t csi_aes_gcm_encrypt(csi_aes_t *aes, void *in, void *out,uint32_t size, uint32_t add_len, void *iv);
/**
\brief Aes gcm decrypt
\param[in] dev_aes dev_aes handle to operate
\param[in] in Pointer to the Source data.
\param[out] out Pointer to the Result data
\param[in] size the Source data size
\param[in] iv init vecotr
\return error code \ref csi_error_t
*/
csi_error_t csi_aes_gcm_decrypt(csi_aes_t *aes, void *in, void *out,uint32_t size, uint32_t add_len, void *iv);
/**
\brief Aes ccm encrypt
\param[in] dev_aes dev_aes handle to operate
\param[in] in Pointer to the Source data
\param[out] out Pointer to the Result data
\param[in] size the Source data size
\param[in] iv init vector
\param[in] tag_out tag output
\return error code \ref csi_error_t
*/
csi_error_t csi_aes_ccm_encrypt(csi_aes_t *aes, void *in, void *out,uint32_t size, uint32_t add_len, void *iv, uint8_t *tag_out);
/**
\brief Aes ccm decrypt
\param[in] dev_aes dev_aes handle to operate
\param[in] in Pointer to the Source data
\param[out] out Pointer to the Result data
\param[in] size the Source data size
\param[in] iv init vecotr
\param[in] tag_out tag output
\return error code \ref csi_error_t
*/
csi_error_t csi_aes_ccm_decrypt(csi_aes_t *aes, void *in, void *out,uint32_t size, uint32_t add_len, void *iv, uint8_t *tag_out);
/**
\brief Enable AES power manage
@@ -258,6 +342,13 @@ csi_error_t csi_aes_enable_pm(csi_aes_t *aes);
*/
void csi_aes_disable_pm(csi_aes_t *aes);
/**
\brief Config AES mode dma or slave
\param[in] dam_en zero disable dma, not zero enable dma
\return None
*/
void csi_aes_dma_enable(csi_aes_t *aes, uint8_t dma_en);
#ifdef __cplusplus
}
#endif

144
lib/sec_library/include/common.h Normal file
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@@ -0,0 +1,144 @@
/*
* Copyright (C) 2017-2020 Alibaba Group Holding Limited
*/
/******************************************************************************
* @file drv/common.h
* @brief Header File for Common Driver
* @version V1.0
* @date 31. March 2020
* @model common
******************************************************************************/
#ifndef _DRV_COMMON_H_
#define _DRV_COMMON_H_
#include <stdint.h>
#include <stdio.h>
#include <string.h>
#include <stdbool.h>
#include "list.h"
#include "dev_tag.h"
#ifdef __cplusplus
extern "C" {
#endif
#ifdef CONFIG_DEBUG_MODE
#define CSI_ASSERT(expr) \
do { \
if ((unsigned long)expr == (unsigned long)NULL) { \
printf("PROGRAM ASSERT\n"); \
while(1); \
} \
} while(0);
#else
#define CSI_ASSERT(expr) ((void)0U)
#endif
#ifdef CONFIG_PARAM_NOT_CHECK
#define CSI_PARAM_CHK(para, err) \
do { \
if ((unsigned long)para == (unsigned long)NULL) { \
return (err); \
} \
} while (0)
#define CSI_PARAM_CHK_NORETVAL(para) \
do { \
if ((unsigned long)para == (unsigned long)NULL) { \
return; \
} \
} while (0)
#else
#define CSI_PARAM_CHK(para, err)
#define CSI_PARAM_CHK_NORETVAL(para)
#endif
#define CSI_EXAMPLE_RESULT(val) \
do { \
if(val>=0) \
{ \
printf("-*success*-\n"); \
} \
else \
{ \
printf("-*fail*-\n"); \
} \
} while (0);
typedef enum {
CSI_OK = 0,
CSI_ERROR = -1,
CSI_BUSY = -2,
CSI_TIMEOUT = -3,
CSI_UNSUPPORTED = -4
} csi_error_t;
typedef struct {
uint8_t readable;
uint8_t writeable;
uint8_t error;
} csi_state_t;
typedef struct csi_dev csi_dev_t;
#ifdef CONFIG_PM
typedef enum {
PM_DEV_SUSPEND,
PM_DEV_RESUME,
} csi_pm_dev_action_t;
typedef enum {
PM_MODE_RUN = 0, ///< Running mode
PM_MODE_SLEEP_1, ///< Sleep LV1 mode
PM_MODE_SLEEP_2, ///< Sleep LV2 mode
PM_MODE_DEEP_SLEEP_1, ///< Deep sleep LV1 mode
PM_MODE_DEEP_SLEEP_2, ///< Deep sleep LV2 mode
PM_MODE_DEEP_SLEEP_3, ///< Deep sleep LV3 mode
} csi_pm_mode_t;
typedef struct {
slist_t next;
csi_error_t (*pm_action)(csi_dev_t *dev, csi_pm_dev_action_t action);
uint32_t *reten_mem;
uint32_t size;
} csi_pm_dev_t;
#include <drv/pm.h>
#endif
struct csi_dev {
unsigned long reg_base;
uint8_t irq_num;
uint8_t idx;
uint16_t dev_tag;
void (*irq_handler)(void *);
#ifdef CONFIG_PM
csi_pm_dev_t pm_dev;
#endif
};
#define HANDLE_REG_BASE(handle) (handle->dev.reg_base)
#define HANDLE_IRQ_NUM(handle) (handle->dev.irq_num)
#define HANDLE_DEV_IDX(handle) (handle->dev.idx)
#define HANDLE_IRQ_HANDLER(handle) (handle->dev.irq_handler)
typedef struct {
unsigned long reg_base;
uint8_t irq_num;
uint8_t idx;
uint16_t dev_tag;
} csi_perip_info_t;
csi_error_t target_get(csi_dev_tag_t dev_tag, uint32_t idx, csi_dev_t *dev);
csi_error_t target_get_optimal_dma_channel(void *dma_list, uint32_t ctrl_num, csi_dev_t *parent_dev, void *ch_info);
//void mdelay(uint32_t ms);
//void udelay(uint32_t us);
//void msleep(uint32_t ms);
#ifdef __cplusplus
}
#endif
#endif /* _DRV_COMMON_H_ */

1
lib/sec_library/include/core/README.txt Normal file
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@@ -0,0 +1 @@
Just include csi_core.h!

126
lib/sec_library/include/core/cmsis/ARMCM0.h Normal file
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@@ -0,0 +1,126 @@
/**************************************************************************//**
* @file ARMCM0.h
* @brief CMSIS Core Peripheral Access Layer Header File for
* ARMCM0 Device
* @version V5.3.1
* @date 09. July 2018
******************************************************************************/
/*
* Copyright (c) 2009-2018 Arm Limited. All rights reserved.
*
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the License); you may
* not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#ifndef ARMCM0_H
#define ARMCM0_H
#ifdef __cplusplus
extern "C" {
#endif
/* ------------------------- Interrupt Number Definition ------------------------ */
typedef enum IRQn
{
/* ------------------- Processor Exceptions Numbers ----------------------------- */
NonMaskableInt_IRQn = -14, /* 2 Non Maskable Interrupt */
HardFault_IRQn = -13, /* 3 HardFault Interrupt */
SVCall_IRQn = -5, /* 11 SV Call Interrupt */
PendSV_IRQn = -2, /* 14 Pend SV Interrupt */
SysTick_IRQn = -1, /* 15 System Tick Interrupt */
/* ------------------- Processor Interrupt Numbers ------------------------------ */
Interrupt0_IRQn = 0,
Interrupt1_IRQn = 1,
Interrupt2_IRQn = 2,
Interrupt3_IRQn = 3,
Interrupt4_IRQn = 4,
Interrupt5_IRQn = 5,
Interrupt6_IRQn = 6,
Interrupt7_IRQn = 7,
Interrupt8_IRQn = 8,
Interrupt9_IRQn = 9
/* Interrupts 10 .. 31 are left out */
} IRQn_Type;
/* ================================================================================ */
/* ================ Processor and Core Peripheral Section ================ */
/* ================================================================================ */
/* ------- Start of section using anonymous unions and disabling warnings ------- */
#if defined (__CC_ARM)
#pragma push
#pragma anon_unions
#elif defined (__ICCARM__)
#pragma language=extended
#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
#pragma clang diagnostic push
#pragma clang diagnostic ignored "-Wc11-extensions"
#pragma clang diagnostic ignored "-Wreserved-id-macro"
#elif defined (__GNUC__)
/* anonymous unions are enabled by default */
#elif defined (__TMS470__)
/* anonymous unions are enabled by default */
#elif defined (__TASKING__)
#pragma warning 586
#elif defined (__CSMC__)
/* anonymous unions are enabled by default */
#else
#warning Not supported compiler type
#endif
/* -------- Configuration of Core Peripherals ----------------------------------- */
#define __CM0_REV 0x0000U /* Core revision r0p0 */
#define __MPU_PRESENT 0U /* no MPU present */
#define __VTOR_PRESENT 0U /* no VTOR present */
#define __NVIC_PRIO_BITS 2U /* Number of Bits used for Priority Levels */
#define __Vendor_SysTickConfig 0U /* Set to 1 if different SysTick Config is used */
#include "core_cm0.h" /* Processor and core peripherals */
#include "system_ARMCM0.h" /* System Header */
/* -------- End of section using anonymous unions and disabling warnings -------- */
#if defined (__CC_ARM)
#pragma pop
#elif defined (__ICCARM__)
/* leave anonymous unions enabled */
#elif (defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050))
#pragma clang diagnostic pop
#elif defined (__GNUC__)
/* anonymous unions are enabled by default */
#elif defined (__TMS470__)
/* anonymous unions are enabled by default */
#elif defined (__TASKING__)
#pragma warning restore
#elif defined (__CSMC__)
/* anonymous unions are enabled by default */
#else
#warning Not supported compiler type
#endif
#ifdef __cplusplus
}
#endif
#endif /* ARMCM0_H */

271
lib/sec_library/include/core/cmsis/cmsis_compiler.h Normal file
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@@ -0,0 +1,271 @@
/**************************************************************************//**
* @file cmsis_compiler.h
* @brief CMSIS compiler generic header file
* @version V5.1.0
* @date 09. October 2018
******************************************************************************/
/*
* Copyright (c) 2009-2018 Arm Limited. All rights reserved.
*
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the License); you may
* not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#ifndef __CMSIS_COMPILER_H
#define __CMSIS_COMPILER_H
#include <stdint.h>
/*
* Arm Compiler 4/5
*/
#if defined ( __CC_ARM )
#include "cmsis_armcc.h"
/*
* Arm Compiler 6.6 LTM (armclang)
*/
#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) && (__ARMCC_VERSION < 6100100)
#include "cmsis_armclang_ltm.h"
/*
* Arm Compiler above 6.10.1 (armclang)
*/
#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6100100)
#include "cmsis_armclang.h"
/*
* GNU Compiler
*/
#elif defined ( __GNUC__ )
#include "cmsis_gcc.h"
/*
* IAR Compiler
*/
#elif defined ( __ICCARM__ )
#include <cmsis_iccarm.h>
/*
* TI Arm Compiler
*/
#elif defined ( __TI_ARM__ )
#include <cmsis_ccs.h>
#ifndef __ASM
#define __ASM __asm
#endif
#ifndef __INLINE
#define __INLINE inline
#endif
#ifndef __STATIC_INLINE
#define __STATIC_INLINE static inline
#endif
#ifndef __STATIC_FORCEINLINE
#define __STATIC_FORCEINLINE __STATIC_INLINE
#endif
#ifndef __NO_RETURN
#define __NO_RETURN __attribute__((noreturn))
#endif
#ifndef __USED
#define __USED __attribute__((used))
#endif
#ifndef __WEAK
#define __WEAK __attribute__((weak))
#endif
#ifndef __PACKED
#define __PACKED __attribute__((packed))
#endif
#ifndef __PACKED_STRUCT
#define __PACKED_STRUCT struct __attribute__((packed))
#endif
#ifndef __PACKED_UNION
#define __PACKED_UNION union __attribute__((packed))
#endif
#ifndef __UNALIGNED_UINT32 /* deprecated */
struct __attribute__((packed)) T_UINT32 { uint32_t v; };
#define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v)
#endif
#ifndef __UNALIGNED_UINT16_WRITE
__PACKED_STRUCT T_UINT16_WRITE { uint16_t v; };
#define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void*)(addr))->v) = (val))
#endif
#ifndef __UNALIGNED_UINT16_READ
__PACKED_STRUCT T_UINT16_READ { uint16_t v; };
#define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(addr))->v)
#endif
#ifndef __UNALIGNED_UINT32_WRITE
__PACKED_STRUCT T_UINT32_WRITE { uint32_t v; };
#define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val))
#endif
#ifndef __UNALIGNED_UINT32_READ
__PACKED_STRUCT T_UINT32_READ { uint32_t v; };
#define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(addr))->v)
#endif
#ifndef __ALIGNED
#define __ALIGNED(x) __attribute__((aligned(x)))
#endif
#ifndef __RESTRICT
#define __RESTRICT __restrict
#endif
/*
* TASKING Compiler
*/
#elif defined ( __TASKING__ )
/*
* The CMSIS functions have been implemented as intrinsics in the compiler.
* Please use "carm -?i" to get an up to date list of all intrinsics,
* Including the CMSIS ones.
*/
#ifndef __ASM
#define __ASM __asm
#endif
#ifndef __INLINE
#define __INLINE inline
#endif
#ifndef __STATIC_INLINE
#define __STATIC_INLINE static inline
#endif
#ifndef __STATIC_FORCEINLINE
#define __STATIC_FORCEINLINE __STATIC_INLINE
#endif
#ifndef __NO_RETURN
#define __NO_RETURN __attribute__((noreturn))
#endif
#ifndef __USED
#define __USED __attribute__((used))
#endif
#ifndef __WEAK
#define __WEAK __attribute__((weak))
#endif
#ifndef __PACKED
#define __PACKED __packed__
#endif
#ifndef __PACKED_STRUCT
#define __PACKED_STRUCT struct __packed__
#endif
#ifndef __PACKED_UNION
#define __PACKED_UNION union __packed__
#endif
#ifndef __UNALIGNED_UINT32 /* deprecated */
struct __packed__ T_UINT32 { uint32_t v; };
#define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v)
#endif
#ifndef __UNALIGNED_UINT16_WRITE
__PACKED_STRUCT T_UINT16_WRITE { uint16_t v; };
#define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void *)(addr))->v) = (val))
#endif
#ifndef __UNALIGNED_UINT16_READ
__PACKED_STRUCT T_UINT16_READ { uint16_t v; };
#define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(addr))->v)
#endif
#ifndef __UNALIGNED_UINT32_WRITE
__PACKED_STRUCT T_UINT32_WRITE { uint32_t v; };
#define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val))
#endif
#ifndef __UNALIGNED_UINT32_READ
__PACKED_STRUCT T_UINT32_READ { uint32_t v; };
#define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(addr))->v)
#endif
#ifndef __ALIGNED
#define __ALIGNED(x) __align(x)
#endif
#ifndef __RESTRICT
#warning No compiler specific solution for __RESTRICT. __RESTRICT is ignored.
#define __RESTRICT
#endif
/*
* COSMIC Compiler
*/
#elif defined ( __CSMC__ )
#include <cmsis_csm.h>
#ifndef __ASM
#define __ASM _asm
#endif
#ifndef __INLINE
#define __INLINE inline
#endif
#ifndef __STATIC_INLINE
#define __STATIC_INLINE static inline
#endif
#ifndef __STATIC_FORCEINLINE
#define __STATIC_FORCEINLINE __STATIC_INLINE
#endif
#ifndef __NO_RETURN
// NO RETURN is automatically detected hence no warning here
#define __NO_RETURN
#endif
#ifndef __USED
#warning No compiler specific solution for __USED. __USED is ignored.
#define __USED
#endif
#ifndef __WEAK
#define __WEAK __weak
#endif
#ifndef __PACKED
#define __PACKED @packed
#endif
#ifndef __PACKED_STRUCT
#define __PACKED_STRUCT @packed struct
#endif
#ifndef __PACKED_UNION
#define __PACKED_UNION @packed union
#endif
#ifndef __UNALIGNED_UINT32 /* deprecated */
@packed struct T_UINT32 { uint32_t v; };
#define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v)
#endif
#ifndef __UNALIGNED_UINT16_WRITE
__PACKED_STRUCT T_UINT16_WRITE { uint16_t v; };
#define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void *)(addr))->v) = (val))
#endif
#ifndef __UNALIGNED_UINT16_READ
__PACKED_STRUCT T_UINT16_READ { uint16_t v; };
#define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(addr))->v)
#endif
#ifndef __UNALIGNED_UINT32_WRITE
__PACKED_STRUCT T_UINT32_WRITE { uint32_t v; };
#define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val))
#endif
#ifndef __UNALIGNED_UINT32_READ
__PACKED_STRUCT T_UINT32_READ { uint32_t v; };
#define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(addr))->v)
#endif
#ifndef __ALIGNED
#warning No compiler specific solution for __ALIGNED. __ALIGNED is ignored.
#define __ALIGNED(x)
#endif
#ifndef __RESTRICT
#warning No compiler specific solution for __RESTRICT. __RESTRICT is ignored.
#define __RESTRICT
#endif
#else
#error Unknown compiler.
#endif
#endif /* __CMSIS_COMPILER_H */

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/**************************************************************************//**
* @file cmsis_version.h
* @brief CMSIS Core(M) Version definitions
* @version V5.0.2
* @date 19. April 2017
******************************************************************************/
/*
* Copyright (c) 2009-2017 ARM Limited. All rights reserved.
*
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the License); you may
* not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#if defined ( __ICCARM__ )
#pragma system_include /* treat file as system include file for MISRA check */
#elif defined (__clang__)
#pragma clang system_header /* treat file as system include file */
#endif
#ifndef __CMSIS_VERSION_H
#define __CMSIS_VERSION_H
/* CMSIS Version definitions */
#define __CM_CMSIS_VERSION_MAIN ( 5U) /*!< [31:16] CMSIS Core(M) main version */
#define __CM_CMSIS_VERSION_SUB ( 1U) /*!< [15:0] CMSIS Core(M) sub version */
#define __CM_CMSIS_VERSION ((__CM_CMSIS_VERSION_MAIN << 16U) | \
__CM_CMSIS_VERSION_SUB ) /*!< CMSIS Core(M) version number */
#endif

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/**************************************************************************//**
* @file core_cm0.h
* @brief CMSIS Cortex-M0 Core Peripheral Access Layer Header File
* @version V5.0.6
* @date 13. March 2019
******************************************************************************/
/*
* Copyright (c) 2009-2019 Arm Limited. All rights reserved.
*
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the License); you may
* not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#if defined ( __ICCARM__ )
#pragma system_include /* treat file as system include file for MISRA check */
#elif defined (__clang__)
#pragma clang system_header /* treat file as system include file */
#endif
#ifndef __CORE_CM0_H_GENERIC
#define __CORE_CM0_H_GENERIC
#include <stdint.h>
#ifdef __cplusplus
extern "C" {
#endif
/**
\page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions
CMSIS violates the following MISRA-C:2004 rules:
\li Required Rule 8.5, object/function definition in header file.<br>
Function definitions in header files are used to allow 'inlining'.
\li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br>
Unions are used for effective representation of core registers.
\li Advisory Rule 19.7, Function-like macro defined.<br>
Function-like macros are used to allow more efficient code.
*/
/*******************************************************************************
* CMSIS definitions
******************************************************************************/
/**
\ingroup Cortex_M0
@{
*/
#include "cmsis_version.h"
/* CMSIS CM0 definitions */
#define __CM0_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */
#define __CM0_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */
#define __CM0_CMSIS_VERSION ((__CM0_CMSIS_VERSION_MAIN << 16U) | \
__CM0_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL version number */
#define __CORTEX_M (0U) /*!< Cortex-M Core */
/** __FPU_USED indicates whether an FPU is used or not.
This core does not support an FPU at all
*/
#define __FPU_USED 0U
#if defined ( __CC_ARM )
#if defined __TARGET_FPU_VFP
#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
#endif
#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
#if defined __ARM_FP
#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
#endif
#elif defined ( __GNUC__ )
#if defined (__VFP_FP__) && !defined(__SOFTFP__)
#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
#endif
#elif defined ( __ICCARM__ )
#if defined __ARMVFP__
#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
#endif
#elif defined ( __TI_ARM__ )
#if defined __TI_VFP_SUPPORT__
#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
#endif
#elif defined ( __TASKING__ )
#if defined __FPU_VFP__
#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
#endif
#elif defined ( __CSMC__ )
#if ( __CSMC__ & 0x400U)
#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
#endif
#endif
#include "cmsis_compiler.h" /* CMSIS compiler specific defines */
#ifdef __cplusplus
}
#endif
#endif /* __CORE_CM0_H_GENERIC */
#ifndef __CMSIS_GENERIC
#ifndef __CORE_CM0_H_DEPENDANT
#define __CORE_CM0_H_DEPENDANT
#ifdef __cplusplus
extern "C" {
#endif
/* check device defines and use defaults */
#if defined __CHECK_DEVICE_DEFINES
#ifndef __CM0_REV
#define __CM0_REV 0x0000U
#warning "__CM0_REV not defined in device header file; using default!"
#endif
#ifndef __NVIC_PRIO_BITS
#define __NVIC_PRIO_BITS 2U
#warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
#endif
#ifndef __Vendor_SysTickConfig
#define __Vendor_SysTickConfig 0U
#warning "__Vendor_SysTickConfig not defined in device header file; using default!"
#endif
#endif
/* IO definitions (access restrictions to peripheral registers) */
/**
\defgroup CMSIS_glob_defs CMSIS Global Defines
<strong>IO Type Qualifiers</strong> are used
\li to specify the access to peripheral variables.
\li for automatic generation of peripheral register debug information.
*/
#ifdef __cplusplus
#define __I volatile /*!< Defines 'read only' permissions */
#else
#define __I volatile const /*!< Defines 'read only' permissions */
#endif
#define __O volatile /*!< Defines 'write only' permissions */
#define __IO volatile /*!< Defines 'read / write' permissions */
/* following defines should be used for structure members */
#define __IM volatile const /*! Defines 'read only' structure member permissions */
#define __OM volatile /*! Defines 'write only' structure member permissions */
#define __IOM volatile /*! Defines 'read / write' structure member permissions */
/*@} end of group Cortex_M0 */
/*******************************************************************************
* Register Abstraction
Core Register contain:
- Core Register
- Core NVIC Register
- Core SCB Register
- Core SysTick Register
******************************************************************************/
/**
\defgroup CMSIS_core_register Defines and Type Definitions
\brief Type definitions and defines for Cortex-M processor based devices.
*/
/**
\ingroup CMSIS_core_register
\defgroup CMSIS_CORE Status and Control Registers
\brief Core Register type definitions.
@{
*/
/**
\brief Union type to access the Application Program Status Register (APSR).
*/
typedef union
{
struct
{
uint32_t _reserved0:28; /*!< bit: 0..27 Reserved */
uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
uint32_t C:1; /*!< bit: 29 Carry condition code flag */
uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
uint32_t N:1; /*!< bit: 31 Negative condition code flag */
} b; /*!< Structure used for bit access */
uint32_t w; /*!< Type used for word access */
} APSR_Type;
/* APSR Register Definitions */
#define APSR_N_Pos 31U /*!< APSR: N Position */
#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */
#define APSR_Z_Pos 30U /*!< APSR: Z Position */
#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */
#define APSR_C_Pos 29U /*!< APSR: C Position */
#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */
#define APSR_V_Pos 28U /*!< APSR: V Position */
#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */
/**
\brief Union type to access the Interrupt Program Status Register (IPSR).
*/
typedef union
{
struct
{
uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */
} b; /*!< Structure used for bit access */
uint32_t w; /*!< Type used for word access */
} IPSR_Type;
/* IPSR Register Definitions */
#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */
#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */
/**
\brief Union type to access the Special-Purpose Program Status Registers (xPSR).
*/
typedef union
{
struct
{
uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */
uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */
uint32_t _reserved1:3; /*!< bit: 25..27 Reserved */
uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
uint32_t C:1; /*!< bit: 29 Carry condition code flag */
uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
uint32_t N:1; /*!< bit: 31 Negative condition code flag */
} b; /*!< Structure used for bit access */
uint32_t w; /*!< Type used for word access */
} xPSR_Type;
/* xPSR Register Definitions */
#define xPSR_N_Pos 31U /*!< xPSR: N Position */
#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */
#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */
#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */
#define xPSR_C_Pos 29U /*!< xPSR: C Position */
#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */
#define xPSR_V_Pos 28U /*!< xPSR: V Position */
#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */
#define xPSR_T_Pos 24U /*!< xPSR: T Position */
#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */
#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */
#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */
/**
\brief Union type to access the Control Registers (CONTROL).
*/
typedef union
{
struct
{
uint32_t _reserved0:1; /*!< bit: 0 Reserved */
uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */
uint32_t _reserved1:30; /*!< bit: 2..31 Reserved */
} b; /*!< Structure used for bit access */
uint32_t w; /*!< Type used for word access */
} CONTROL_Type;
/* CONTROL Register Definitions */
#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */
#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */
/*@} end of group CMSIS_CORE */
/**
\ingroup CMSIS_core_register
\defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC)
\brief Type definitions for the NVIC Registers
@{
*/
/**
\brief Structure type to access the Nested Vectored Interrupt Controller (NVIC).
*/
typedef struct
{
__IOM uint32_t ISER[1U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */
uint32_t RESERVED0[31U];
__IOM uint32_t ICER[1U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */
uint32_t RESERVED1[31U];
__IOM uint32_t ISPR[1U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */
uint32_t RESERVED2[31U];
__IOM uint32_t ICPR[1U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */
uint32_t RESERVED3[31U];
uint32_t RESERVED4[64U];
__IOM uint32_t IP[8U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register */
} NVIC_Type;
/*@} end of group CMSIS_NVIC */
/**
\ingroup CMSIS_core_register
\defgroup CMSIS_SCB System Control Block (SCB)
\brief Type definitions for the System Control Block Registers
@{
*/
/**
\brief Structure type to access the System Control Block (SCB).
*/
typedef struct
{
__IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */
__IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */
uint32_t RESERVED0;
__IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */
__IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */
__IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */
uint32_t RESERVED1;
__IOM uint32_t SHP[2U]; /*!< Offset: 0x01C (R/W) System Handlers Priority Registers. [0] is RESERVED */
__IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */
} SCB_Type;
/* SCB CPUID Register Definitions */
#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */
#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */
#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */
#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */
#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */
#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */
#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */
#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */
#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */
#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */
/* SCB Interrupt Control State Register Definitions */
#define SCB_ICSR_NMIPENDSET_Pos 31U /*!< SCB ICSR: NMIPENDSET Position */
#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */
#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */
#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */
#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */
#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */
#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */
#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */
#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */
#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */
#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */
#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */
#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */
#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */
#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */
#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */
#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */
#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */
/* SCB Application Interrupt and Reset Control Register Definitions */
#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */
#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */
#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */
#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */
#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */
#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */
#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */
#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */
#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */
#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */
/* SCB System Control Register Definitions */
#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */
#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */
#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */
#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */
#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */
#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */
/* SCB Configuration Control Register Definitions */
#define SCB_CCR_STKALIGN_Pos 9U /*!< SCB CCR: STKALIGN Position */
#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */
#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */
#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */
/* SCB System Handler Control and State Register Definitions */
#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */
#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */
/*@} end of group CMSIS_SCB */
/**
\ingroup CMSIS_core_register
\defgroup CMSIS_SysTick System Tick Timer (SysTick)
\brief Type definitions for the System Timer Registers.
@{
*/
/**
\brief Structure type to access the System Timer (SysTick).
*/
typedef struct
{
__IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */
__IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */
__IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */
__IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */
} SysTick_Type;
/* SysTick Control / Status Register Definitions */
#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */
#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */
#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */
#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */
#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */
#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */
#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */
#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */
/* SysTick Reload Register Definitions */
#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */
#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */
/* SysTick Current Register Definitions */
#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */
#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */
/* SysTick Calibration Register Definitions */
#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */
#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */
#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */
#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */
#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */
#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */
/*@} end of group CMSIS_SysTick */
/**
\ingroup CMSIS_core_register
\defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug)
\brief Cortex-M0 Core Debug Registers (DCB registers, SHCSR, and DFSR) are only accessible over DAP and not via processor.
Therefore they are not covered by the Cortex-M0 header file.
@{
*/
/*@} end of group CMSIS_CoreDebug */
/**
\ingroup CMSIS_core_register
\defgroup CMSIS_core_bitfield Core register bit field macros
\brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk).
@{
*/
/**
\brief Mask and shift a bit field value for use in a register bit range.
\param[in] field Name of the register bit field.
\param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type.
\return Masked and shifted value.
*/
#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk)
/**
\brief Mask and shift a register value to extract a bit filed value.
\param[in] field Name of the register bit field.
\param[in] value Value of register. This parameter is interpreted as an uint32_t type.
\return Masked and shifted bit field value.
*/
#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos)
/*@} end of group CMSIS_core_bitfield */
/**
\ingroup CMSIS_core_register
\defgroup CMSIS_core_base Core Definitions
\brief Definitions for base addresses, unions, and structures.
@{
*/
/* Memory mapping of Core Hardware */
#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */
#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */
#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */
#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */
#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */
#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */
#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */
/*@} */
/*******************************************************************************
* Hardware Abstraction Layer
Core Function Interface contains:
- Core NVIC Functions
- Core SysTick Functions
- Core Register Access Functions
******************************************************************************/
/**
\defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference
*/
/* ########################## NVIC functions #################################### */
/**
\ingroup CMSIS_Core_FunctionInterface
\defgroup CMSIS_Core_NVICFunctions NVIC Functions
\brief Functions that manage interrupts and exceptions via the NVIC.
@{
*/
#ifdef CMSIS_NVIC_VIRTUAL
#ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE
#define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h"
#endif
#include CMSIS_NVIC_VIRTUAL_HEADER_FILE
#else
#define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping
#define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping
#define NVIC_EnableIRQ __NVIC_EnableIRQ
#define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ
#define NVIC_DisableIRQ __NVIC_DisableIRQ
#define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ
#define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ
#define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ
/*#define NVIC_GetActive __NVIC_GetActive not available for Cortex-M0 */
#define NVIC_SetPriority __NVIC_SetPriority
#define NVIC_GetPriority __NVIC_GetPriority
#define NVIC_SystemReset __NVIC_SystemReset
#endif /* CMSIS_NVIC_VIRTUAL */
#ifdef CMSIS_VECTAB_VIRTUAL
#ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE
#define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h"
#endif
#include CMSIS_VECTAB_VIRTUAL_HEADER_FILE
#else
#define NVIC_SetVector __NVIC_SetVector
#define NVIC_GetVector __NVIC_GetVector
#endif /* (CMSIS_VECTAB_VIRTUAL) */
#define NVIC_USER_IRQ_OFFSET 16
/* The following EXC_RETURN values are saved the LR on exception entry */
#define EXC_RETURN_HANDLER (0xFFFFFFF1UL) /* return to Handler mode, uses MSP after return */
#define EXC_RETURN_THREAD_MSP (0xFFFFFFF9UL) /* return to Thread mode, uses MSP after return */
#define EXC_RETURN_THREAD_PSP (0xFFFFFFFDUL) /* return to Thread mode, uses PSP after return */
/* Interrupt Priorities are WORD accessible only under Armv6-M */
/* The following MACROS handle generation of the register offset and byte masks */
#define _BIT_SHIFT(IRQn) ( ((((uint32_t)(int32_t)(IRQn)) ) & 0x03UL) * 8UL)
#define _SHP_IDX(IRQn) ( (((((uint32_t)(int32_t)(IRQn)) & 0x0FUL)-8UL) >> 2UL) )
#define _IP_IDX(IRQn) ( (((uint32_t)(int32_t)(IRQn)) >> 2UL) )
#define __NVIC_SetPriorityGrouping(X) (void)(X)
#define __NVIC_GetPriorityGrouping() (0U)
/**
\brief Enable Interrupt
\details Enables a device specific interrupt in the NVIC interrupt controller.
\param [in] IRQn Device specific interrupt number.
\note IRQn must not be negative.
*/
__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn)
{
if ((int32_t)(IRQn) >= 0)
{
NVIC->ISER[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
}
}
/**
\brief Get Interrupt Enable status
\details Returns a device specific interrupt enable status from the NVIC interrupt controller.
\param [in] IRQn Device specific interrupt number.
\return 0 Interrupt is not enabled.
\return 1 Interrupt is enabled.
\note IRQn must not be negative.
*/
__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn)
{
if ((int32_t)(IRQn) >= 0)
{
return((uint32_t)(((NVIC->ISER[0U] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
}
else
{
return(0U);
}
}
/**
\brief Disable Interrupt
\details Disables a device specific interrupt in the NVIC interrupt controller.
\param [in] IRQn Device specific interrupt number.
\note IRQn must not be negative.
*/
__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn)
{
if ((int32_t)(IRQn) >= 0)
{
NVIC->ICER[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
__DSB();
__ISB();
}
}
/**
\brief Get Pending Interrupt
\details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt.
\param [in] IRQn Device specific interrupt number.
\return 0 Interrupt status is not pending.
\return 1 Interrupt status is pending.
\note IRQn must not be negative.
*/
__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn)
{
if ((int32_t)(IRQn) >= 0)
{
return((uint32_t)(((NVIC->ISPR[0U] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
}
else
{
return(0U);
}
}
/**
\brief Set Pending Interrupt
\details Sets the pending bit of a device specific interrupt in the NVIC pending register.
\param [in] IRQn Device specific interrupt number.
\note IRQn must not be negative.
*/
__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn)
{
if ((int32_t)(IRQn) >= 0)
{
NVIC->ISPR[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
}
}
/**
\brief Clear Pending Interrupt
\details Clears the pending bit of a device specific interrupt in the NVIC pending register.
\param [in] IRQn Device specific interrupt number.
\note IRQn must not be negative.
*/
__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn)
{
if ((int32_t)(IRQn) >= 0)
{
NVIC->ICPR[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
}
}
/**
\brief Set Interrupt Priority
\details Sets the priority of a device specific interrupt or a processor exception.
The interrupt number can be positive to specify a device specific interrupt,
or negative to specify a processor exception.
\param [in] IRQn Interrupt number.
\param [in] priority Priority to set.
\note The priority cannot be set for every processor exception.
*/
__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
{
if ((int32_t)(IRQn) >= 0)
{
NVIC->IP[_IP_IDX(IRQn)] = ((uint32_t)(NVIC->IP[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
(((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
}
else
{
SCB->SHP[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
(((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
}
}
/**
\brief Get Interrupt Priority
\details Reads the priority of a device specific interrupt or a processor exception.
The interrupt number can be positive to specify a device specific interrupt,
or negative to specify a processor exception.
\param [in] IRQn Interrupt number.
\return Interrupt Priority.
Value is aligned automatically to the implemented priority bits of the microcontroller.
*/
__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn)
{
if ((int32_t)(IRQn) >= 0)
{
return((uint32_t)(((NVIC->IP[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS)));
}
else
{
return((uint32_t)(((SCB->SHP[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS)));
}
}
/**
\brief Encode Priority
\details Encodes the priority for an interrupt with the given priority group,
preemptive priority value, and subpriority value.
In case of a conflict between priority grouping and available
priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
\param [in] PriorityGroup Used priority group.
\param [in] PreemptPriority Preemptive priority value (starting from 0).
\param [in] SubPriority Subpriority value (starting from 0).
\return Encoded priority. Value can be used in the function \ref NVIC_SetPriority().
*/
__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)
{
uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
uint32_t PreemptPriorityBits;
uint32_t SubPriorityBits;
PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
return (
((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) |
((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL)))
);
}
/**
\brief Decode Priority
\details Decodes an interrupt priority value with a given priority group to
preemptive priority value and subpriority value.
In case of a conflict between priority grouping and available
priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set.
\param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority().
\param [in] PriorityGroup Used priority group.
\param [out] pPreemptPriority Preemptive priority value (starting from 0).
\param [out] pSubPriority Subpriority value (starting from 0).
*/
__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority)
{
uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
uint32_t PreemptPriorityBits;
uint32_t SubPriorityBits;
PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
*pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL);
*pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL);
}
/**
\brief Set Interrupt Vector
\details Sets an interrupt vector in SRAM based interrupt vector table.
The interrupt number can be positive to specify a device specific interrupt,
or negative to specify a processor exception.
Address 0 must be mapped to SRAM.
\param [in] IRQn Interrupt number
\param [in] vector Address of interrupt handler function
*/
__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector)
{
uint32_t vectors = 0x0U;
(* (int *) (vectors + ((int32_t)IRQn + NVIC_USER_IRQ_OFFSET) * 4)) = vector;
}
/**
\brief Get Interrupt Vector
\details Reads an interrupt vector from interrupt vector table.
The interrupt number can be positive to specify a device specific interrupt,
or negative to specify a processor exception.
\param [in] IRQn Interrupt number.
\return Address of interrupt handler function
*/
__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn)
{
uint32_t vectors = 0x0U;
return (uint32_t)(* (int *) (vectors + ((int32_t)IRQn + NVIC_USER_IRQ_OFFSET) * 4));
}
/**
\brief System Reset
\details Initiates a system reset request to reset the MCU.
*/
__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void)
{
__DSB(); /* Ensure all outstanding memory accesses included
buffered write are completed before reset */
SCB->AIRCR = ((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
SCB_AIRCR_SYSRESETREQ_Msk);
__DSB(); /* Ensure completion of memory access */
for(;;) /* wait until reset */
{
__NOP();
}
}
/*@} end of CMSIS_Core_NVICFunctions */
/* ########################## FPU functions #################################### */
/**
\ingroup CMSIS_Core_FunctionInterface
\defgroup CMSIS_Core_FpuFunctions FPU Functions
\brief Function that provides FPU type.
@{
*/
/**
\brief get FPU type
\details returns the FPU type
\returns
- \b 0: No FPU
- \b 1: Single precision FPU
- \b 2: Double + Single precision FPU
*/
__STATIC_INLINE uint32_t SCB_GetFPUType(void)
{
return 0U; /* No FPU */
}
/*@} end of CMSIS_Core_FpuFunctions */
/* ################################## SysTick function ############################################ */
/**
\ingroup CMSIS_Core_FunctionInterface
\defgroup CMSIS_Core_SysTickFunctions SysTick Functions
\brief Functions that configure the System.
@{
*/
#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U)
/**
\brief System Tick Configuration
\details Initializes the System Timer and its interrupt, and starts the System Tick Timer.
Counter is in free running mode to generate periodic interrupts.
\param [in] ticks Number of ticks between two interrupts.
\return 0 Function succeeded.
\return 1 Function failed.
\note When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>
must contain a vendor-specific implementation of this function.
*/
__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
{
if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk)
{
return (1UL); /* Reload value impossible */
}
SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */
NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */
SysTick->VAL = 0UL; /* Load the SysTick Counter Value */
SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk |
SysTick_CTRL_TICKINT_Msk |
SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */
return (0UL); /* Function successful */
}
#endif
/*@} end of CMSIS_Core_SysTickFunctions */
#ifdef __cplusplus
}
#endif
#endif /* __CORE_CM0_H_DEPENDANT */
#endif /* __CMSIS_GENERIC */

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/*
* Copyright (C) 2017-2019 Alibaba Group Holding Limited
*/
/******************************************************************************
* @file csi_core.h
* @brief Header File for csi_core
* @version V1.0
* @date 12. june 2019
******************************************************************************/
#ifndef _CSI_CORE_H_
#define _CSI_CORE_H_
#include <stddef.h>
#include <cmsis_gcc.h>
#ifdef __cplusplus
extern "C" {
#endif
#ifdef __GNUC__
__STATIC_INLINE size_t csi_irq_save(void)
{
uint32_t result;
result = __get_PRIMASK();
__disable_irq();
return (result);
}
__STATIC_INLINE void csi_irq_restore(size_t irq_state)
{
__set_PRIMASK(irq_state);
}
#else
static inline __asm size_t csi_irq_save(void)
{
MRS R0, PRIMASK
CPSID I
BX LR
return 0;
}
static inline __asm void csi_irq_restore(size_t irq_state)
{
MSR PRIMASK, R0
BX LR
}
#endif
#ifdef __cplusplus
}
#endif
#endif /* _CSI_CORE_H_ */

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/**************************************************************************//**
* @file system_ARMCM0.h
* @brief CMSIS Device System Header File for
* ARMCM0 Device
* @version V5.3.1
* @date 09. July 2018
******************************************************************************/
/*
* Copyright (c) 2009-2018 Arm Limited. All rights reserved.
*
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the License); you may
* not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#ifndef SYSTEM_ARMCM0_H
#define SYSTEM_ARMCM0_H
#ifdef __cplusplus
extern "C" {
#endif
extern uint32_t SystemCoreClock; /*!< System Clock Frequency (Core Clock) */
/**
\brief Setup the microcontroller system.
Initialize the System and update the SystemCoreClock variable.
*/
extern void SystemInit (void);
/**
\brief Update SystemCoreClock variable.
Updates the SystemCoreClock with current core Clock retrieved from cpu registers.
*/
extern void SystemCoreClockUpdate (void);
#ifdef __cplusplus
}
#endif
#endif /* SYSTEM_ARMCM0_H */

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/*
* Copyright (C) 2017-2019 Alibaba Group Holding Limited
*/
/******************************************************************************
* @file core_ck810.h
* @brief CSI CK810 Core Peripheral Access Layer Header File
* @version V1.0
* @date 26. Jan 2018
******************************************************************************/
#ifndef __CORE_CK810_H_GENERIC
#define __CORE_CK810_H_GENERIC
#include <stdint.h>
#ifdef __cplusplus
extern "C" {
#endif
/*******************************************************************************
* CSI definitions
******************************************************************************/
/**
\ingroup CK810
@{
*/
/* CSI CK810 definitions */
#define __CK810_CSI_VERSION_MAIN (0x04U) /*!< [31:16] CSI HAL main version */
#define __CK810_CSI_VERSION_SUB (0x1EU) /*!< [15:0] CSI HAL sub version */
#define __CK810_CSI_VERSION ((__CK810_CSI_VERSION_MAIN << 16U) | \
__CK810_CSI_VERSION_SUB ) /*!< CSI HAL version number */
#ifndef __CK810
#define __CK810 (0x0aU) /*!< CK810 Core */
#endif
/** __FPU_USED indicates whether an FPU is used or not.
*/
#define __FPU_USED 1U
#if defined ( __GNUC__ )
#if defined (__VFP_FP__) && !defined(__SOFTFP__)
#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
#endif
#endif
#ifdef __cplusplus
}
#endif
#endif /* __CORE_CK810_H_GENERIC */
#ifndef __CSI_GENERIC
#ifndef __CORE_CK810_H_DEPENDANT
#define __CORE_CK810_H_DEPENDANT
#ifdef __cplusplus
extern "C" {
#endif
/* check device defines and use defaults */
#ifndef __CK810_REV
#define __CK810_REV 0x0000U
#endif
#ifndef __GSR_GCR_PRESENT
#define __GSR_GCR_PRESENT 0U
#endif
#ifndef __ICACHE_PRESENT
#define __ICACHE_PRESENT 1U
#endif
#ifndef __DCACHE_PRESENT
#define __DCACHE_PRESENT 1U
#endif
#include <core/csi_gcc.h>
/* IO definitions (access restrictions to peripheral registers) */
/**
\defgroup CSI_glob_defs CSI Global Defines
<strong>IO Type Qualifiers</strong> are used
\li to specify the access to peripheral variables.
\li for automatic generation of peripheral register debug information.
*/
#ifdef __cplusplus
#define __I volatile /*!< Defines 'read only' permissions */
#else
#define __I volatile const /*!< Defines 'read only' permissions */
#endif
#define __O volatile /*!< Defines 'write only' permissions */
#define __IO volatile /*!< Defines 'read / write' permissions */
/* following defines should be used for structure members */
#define __IM volatile const /*! Defines 'read only' structure member permissions */
#define __OM volatile /*! Defines 'write only' structure member permissions */
#define __IOM volatile /*! Defines 'read / write' structure member permissions */
/*@} end of group CK810 */
/*******************************************************************************
* Register Abstraction
Core Register contain:
- Core Register
******************************************************************************/
/**
\defgroup CSI_core_register Defines and Type Definitions
\brief Type definitions and defines for CK810 processor based devices.
*/
/**
\ingroup CSI_core_register
\defgroup CSI_CORE Status and Control Registers
\brief Core Register type definitions.
@{
*/
/**
\brief Access Processor Status Register(PSR)struct definition.
*/
typedef union {
struct {
uint32_t C: 1; /*!< bit: 0 Conditional code/Carry flag */
uint32_t AF: 1; /*!< bit: 1 Alternate register valid control bit */
uint32_t _reserved0: 2; /*!< bit: 2.. 3 Reserved */
uint32_t FE: 1; /*!< bit: 4 Fast interrupt enable control bit */
uint32_t _reserved1: 1; /*!< bit: 5 Reserved */
uint32_t IE: 1; /*!< bit: 6 Interrupt effective control bit */
uint32_t IC: 1; /*!< bit: 7 Interrupt control bit */
uint32_t EE: 1; /*!< bit: 8 Abnormally effective control bit */
uint32_t MM: 1; /*!< bit: 9 Unsymmetrical masking bit */
uint32_t _reserved2: 2; /*!< bit: 10..11 Reserved */
uint32_t TE: 1; /*!< bit: 12 Trace transmission control bit */
uint32_t TP: 1; /*!< bit: 13 Pending trace exception set bit */
uint32_t TM: 2; /*!< bit: 14..15 Tracing mode bit */
uint32_t VEC: 8; /*!< bit: 16..23 Abnormal event vector value */
uint32_t _reserved3: 7; /*!< bit: 24..30 Reserved */
uint32_t S: 1; /*!< bit: 31 Superuser mode set bit */
} b; /*!< Structure Access by bit */
uint32_t w; /*!< Type Access by whole register */
} PSR_Type;
/* PSR Register Definitions */
#define PSR_S_Pos 31U /*!< PSR: S Position */
#define PSR_S_Msk (0x1UL << PSR_S_Pos) /*!< PSR: S Mask */
#define PSR_VEC_Pos 16U /*!< PSR: VEC Position */
#define PSR_VEC_Msk (0xFFUL << PSR_VEC_Pos) /*!< PSR: VEC Mask */
#define PSR_TM_Pos 14U /*!< PSR: TM Position */
#define PSR_TM_Msk (0x3UL << PSR_TM_Pos) /*!< PSR: TM Mask */
#define PSR_TP_Pos 13U /*!< PSR: TP Position */
#define PSR_TP_Msk (0x1UL << PSR_TM_Pos) /*!< PSR: TP Mask */
#define PSR_TE_Pos 12U /*!< PSR: TE Position */
#define PSR_TE_Msk (0x1UL << PSR_TE_Pos) /*!< PSR: TE Mask */
#define PSR_MM_Pos 9U /*!< PSR: MM Position */
#define PSR_MM_Msk (0x1UL << PSR_MM_Pos) /*!< PSR: MM Mask */
#define PSR_EE_Pos 8U /*!< PSR: EE Position */
#define PSR_EE_Msk (0x1UL << PSR_EE_Pos) /*!< PSR: EE Mask */
#define PSR_IC_Pos 7U /*!< PSR: IC Position */
#define PSR_IC_Msk (0x1UL << PSR_IC_Pos) /*!< PSR: IC Mask */
#define PSR_IE_Pos 6U /*!< PSR: IE Position */
#define PSR_IE_Msk (0x1UL << PSR_IE_Pos) /*!< PSR: IE Mask */
#define PSR_FE_Pos 4U /*!< PSR: FE Position */
#define PSR_FE_Msk (0x1UL << PSR_FE_Pos) /*!< PSR: FE Mask */
#define PSR_AF_Pos 1U /*!< PSR: AF Position */
#define PSR_AF_Msk (0x1UL << PSR_AF_Pos) /*!< PSR: AF Mask */
#define PSR_C_Pos 0U /*!< PSR: C Position */
#define PSR_C_Msk (0x1UL << PSR_C_Pos) /*!< PSR: C Mask */
/**
\brief Consortium definition for accessing Cache Configuration Registers(CCR, CR<18, 0>).
*/
typedef union {
struct {
uint32_t MP: 2; /*!< bit: 0.. 1 memory protection settings */
uint32_t IE: 1; /*!< bit: 2 Instruction cache enable */
uint32_t DE: 1; /*!< bit: 3 Data cache enable */
uint32_t WB: 1; /*!< bit: 4 Cache write back */
uint32_t RS: 1; /*!< bit: 5 Address return stack settings */
uint32_t Z: 1; /*!< bit: 6 Allow predictive jump bit */
uint32_t BE: 1; /*!< bit: 7 Endian mode */
uint32_t SCK: 3; /*!< bit: 8..10 the clock ratio of the system and the processor */
uint32_t _reserved0: 1; /*!< bit: 11 Reserved */
uint32_t WA: 1; /*!< bit: 12 Write allocate enable */
uint32_t E_V2: 1; /*!< bit: 13 V2 Endian mode */
uint32_t BSTE: 1; /*!< bit: 14 Burst transmit enable */
uint32_t IPE: 1; /*!< bit: 15 Indirect predict enable */
uint32_t _reserved1: 16; /*!< bit: 16..31 Reserved */
} b; /*!< Structure Access by bit */
uint32_t w; /*!< Type Access by whole register */
} CCR_Type;
/* CCR Register Definitions */
#define CCR_IPE_Pos 15u /*!< CCR: IPE Position */
#define CCR_IPE_Msk (0x1UL << CCR_IPE_Pos) /*!< CCR: IPE Mask */
#define CCR_BSTE_Pos 14u /*!< CCR: BSTE Position */
#define CCR_BSTE_Msk (0x1UL << CCR_BSTE_Pos) /*!< CCR: BSTE Mask */
#define CCR_E_V2_Pos 13U /*!< CCR: E_V2 Position */
#define CCR_E_V2_Msk (0x1UL << CCR_E_V2_Pos) /*!< CCR: E_V2 Mask */
#define CCR_WA_Pos 12u /*!< CCR: WA Position */
#define CCR_WA_Msk (0x1UL << CCR_WA_Pos) /*!< CCR: WA Mask */
#define CCR_SCK_Pos 8U /*!< CCR: SCK Position */
#define CCR_SCK_Msk (0x3UL << CCR_SCK_Pos) /*!< CCR: SCK Mask */
#define CCR_BE_Pos 7U /*!< CCR: BE Position */
#define CCR_BE_Msk (0x1UL << CCR_BE_Pos) /*!< CCR: BE Mask */
#define CCR_Z_Pos 6U /*!< CCR: Z Position */
#define CCR_Z_Msk (0x1UL << CCR_BE_Pos) /*!< CCR: Z Mask */
#define CCR_RS_Pos 5U /*!< CCR: RS Position */
#define CCR_RS_Msk (0x1UL << CCR_BE_Pos) /*!< CCR: RS Mask */
#define CCR_WB_Pos 4U /*!< CCR: WB Position */
#define CCR_WB_Msk (0x1UL << CCR_BE_Pos) /*!< CCR: WB Mask */
#define CCR_DE_Pos 3U /*!< CCR: DE Position */
#define CCR_DE_Msk (0x1UL << CCR_BE_Pos) /*!< CCR: DE Mask */
#define CCR_IE_Pos 2U /*!< CCR: IE Position */
#define CCR_IE_Msk (0x1UL << CCR_BE_Pos) /*!< CCR: IE Mask */
#define CCR_MP_Pos 0U /*!< CCR: MP Position */
#define CCR_MP_Msk (0x3UL << CCR_MP_Pos) /*!< CCR: MP Mask */
/**
\brief Consortium definition for accessing mmu index register(MIR,CR<0,15>).
*/
typedef union {
struct {
uint32_t Index: 10; /*!< bit: 0.. 9 TLB index */
uint32_t _reserved: 20; /*!< bit: 10.. 29 Reserved */
uint32_t TF: 1; /*!< bit: 30 TLB fatal error */
uint32_t P: 1; /*!< bit: 31 TLBP instruction */
} b;
uint32_t w;
} MIR_Type;
/* MIR Register Definitions */
#define MIR_P_Pos 31 /*!< PRSR: P(TLBP instruction) Position */
#define MIR_P_Msk (0x1UL << MIR_P_Pos) /*!< PRSR: P(TLBP instruction) Mask */
#define MIR_TF_Pos 30 /*!< PRSR: Tfatal Position */
#define MIR_TF_Msk (0x1UL << MIR_TF_Pos) /*!< PRSR: Tfatal Mask */
#define MIR_Index_Pos 0 /*!< PRSR: Index Position */
#define MIR_Index_Msk (0x3ffUL << MIR_Index_Pos) /*!< PRSR: Index Mask */
/**
\brief Consortium definition for accessing mmu entry of high physical address register(MEL, CR<2,15> and CR<3,15>).
*/
typedef union {
struct {
uint32_t G: 1; /*!< bit: 0 Global enbale bit */
uint32_t V: 1; /*!< bit: 1 TLB mapping valid bit */
uint32_t D: 1; /*!< bit: 2 TLB Page dirty bit */
uint32_t C: 1; /*!< bit: 3 TLB Page cacheable bit */
uint32_t SEC: 1; /*!< bit: 4 TLB Page security bit */
uint32_t SO: 1; /*!< bit: 2 Strong order enable bit */
uint32_t B: 1; /*!< bit: 2 TLB Page bufferable bit */
uint32_t _reserved: 5; /*!< bit: 7.. 11 Reserved */
uint32_t PFN: 20; /*!< bit: 12.. 31 Physical frame number */
} b;
uint32_t w;
} MEL_Type;
/* MEL Register Definitions */
#define MEL_PFN_Pos 12 /*!< MEL: PFN Position */
#define MEL_PFN_Msk (0xFFFFFUL << MEL_PFN_Pos) /*!< MEL: PFN Mask */
#define MEL_B_Pos 6 /*!< MEL: B Position */
#define MEL_B_Msk (0x1UL << MEL_B_Pos) /*!< MEL: B Mask */
#define MEL_SO_Pos 5 /*!< MEL: SO Position */
#define MEL_SO_Msk (0x1UL << MEL_SO_Pos) /*!< MEL: SO Mask */
#define MEL_SEC_Pos 4 /*!< MEL: SEC Position */
#define MEL_SEC_Msk (0x1UL << MEL_SEC_Pos) /*!< MEL: SEC Mask */
#define MEL_C_Pos 3 /*!< MEL: C Position */
#define MEL_C_Msk (0x1UL << MEL_C_Pos) /*!< MEL: C Mask */
#define MEL_D_Pos 2 /*!< MEL: D Position */
#define MEL_D_Msk (0x1UL << MIR_D_Pos) /*!< MEL: D Mask */
#define MEL_V_Pos 1 /*!< MEL: V Position */
#define MEL_V_Msk (0x1UL << MIR_V_Pos) /*!< MEL: V Mask */
#define MEL_G_Pos 0 /*!< MEL: G Position */
#define MEL_G_Msk (0x1UL << MIR_G_Pos) /*!< MEL: G Mask */
/**
\brief Consortium definition for accessing mmu entry of high physical address register(MEH, CR<4,15>).
*/
typedef union {
struct {
uint32_t ASID :8; /*!< bit: 0.. 7 ASID */
uint32_t _reserved :4; /*!< bit: 7.. 10 Reserved */
uint32_t VPN :20; /*!< bit: 11.. 31 Virtual page number */
} b;
uint32_t w;
} MEH_Type;
/* MEH Register Definitions */
#define MEH_VPN_Pos 12 /*!< MEH: VPN Position */
#define MEH_VPN_Msk (0xFFFFFUL << MEH_VPN_Pos) /*!< MEH: VPN Mask */
#define MEH_ASID_Pos 0 /*!< MEH: ASID Position */
#define MEH_ASID_Msk (0xFFUL << MEH_ASID_Pos) /*!< MEH: ASID Mask */
/**
\brief Consortium definition for accessing mmu entry of high physical address register(MPR, CR<6,15>).
*/
typedef union {
struct {
uint32_t _reserved0: 13; /*!< bit: 0.. 12 Reserved */
uint32_t page_mask: 12; /*!< bit: 13.. 24 Page mask */
uint32_t _reserved1: 7; /*!< bit: 25.. 31 Reserved */
} b;
uint32_t w;
} MPR_Type;
/* MPR Register Definitions */
#define MPR_PAGE_MASK_Pos 13 /*!< MPR: PAGE_MASK Position */
#define MPR_PAGE_MASK_Msk (0xFFFUL << MPR_PAGE_MASK_Pos) /*!< MPR: PAGE_MASK Mask */
/**
\brief Consortium definition for accessing mmu entry of high physical address register(CR<8,15>).
*/
typedef union {
struct {
uint32_t ASID: 8; /*!< bit: 0.. 7 ASID */
uint32_t _reserved: 17; /*!< bit: 8.. 24 Reserved */
uint32_t TLBINV_INDEX: 1; /*!< bit: 25 TLBINV_INDEX */
uint32_t TLBINV_ALL: 1; /*!< bit: 26 TLBINV_ALL */
uint32_t TLBINV: 1; /*!< bit: 27 TLBINV */
uint32_t TLBWR: 1; /*!< bit: 28 TLBWR */
uint32_t TLBWI: 1; /*!< bit: 29 TLBWI */
uint32_t TLBR: 1; /*!< bit: 30 TLBR */
uint32_t TLBP: 1; /*!< bit: 31 TLBP */
} b;
uint32_t w;
} MCIR_Type;
/* MCIR Register Definitions */
#define MCIR_TLBP_Pos 31 /*!< MCIR: TLBP Position */
#define MCIR_TLBP_Msk (0x1UL << MCIR_TLBP_Pos) /*!< MCIR: TLBP Mask */
#define MCIR_TLBR_Pos 30 /*!< MCIR: TLBR Position */
#define MCIR_TLBR_Msk (0x1UL << MCIR_TLBR_Pos) /*!< MCIR: TLBR Mask */
#define MCIR_TLBWI_Pos 29 /*!< MCIR: TLBWI Position */
#define MCIR_TLBWI_Msk (0x1UL << MCIR_TLBWI_Pos) /*!< MCIR: TLBWI Mask */
#define MCIR_TLBWR_Pos 28 /*!< MCIR: TLBWR Position */
#define MCIR_TLBWR_Msk (0x1UL << MCIR_TLBWR_Pos) /*!< MCIR: TLBWR Mask */
#define MCIR_TLBINV_Pos 27 /*!< MCIR: TLBINV Position */
#define MCIR_TLBINV_Msk (0x1UL << MCIR_TLBINV_Pos) /*!< MCIR: TLBINV Mask */
#define MCIR_TLBINV_ALL_Pos 26 /*!< MCIR: TLBINV_ALL Position */
#define MCIR_TLBINV_ALL_Msk (0x1UL << MCIR_TLBINV_ALL_Pos) /*!< MCIR: TLBINV_ALL Mask */
#define MCIR_TLBINV_INDEX_Pos 25 /*!< MCIR: TLBINV_INDEX Position */
#define MCIR_TLBINV_INDEX_Msk (0x1UL << MCIR_TLBINV_INDEX_Pos) /*!< MCIR: TLBINV_INDEX Mask */
#define MCIR_ASID_Pos 0 /*!< MCIR: ASID Position */
#define MCIR_ASID_Msk (0xFFUL << MCIR_ASID_Pos) /*!< MCIR: ASID Mask */
/*@} end of group CSI_CORE */
/**
\ingroup CSI_core_register
\defgroup CSI_CACHE
\brief Type definitions for the cache Registers
@{
*/
/**
\brief Consortium definition for accessing protection area selection register(CFR,CR<17,0>).
*/
typedef union {
struct {
uint32_t CACHE_SEL: 2; /*!< bit: 0..1 Instruction and data cache selection */
uint32_t _reserved0: 2; /*!< bit: 2..3 Reserved */
uint32_t INV: 1; /*!< bit: 4 Invalid data in cache */
uint32_t CLR: 1; /*!< bit: 5 Clear the dirty tlb table */
uint32_t OMS: 1; /*!< bit: 6 Cache invalid and clear operation mode (one line or all line)*/
uint32_t ITS: 1; /*!< bit: 7 Cache invalid and clear operation mode (CIR used as virtual index or SET/WAY/LEVE index)*/
uint32_t UNLOCK: 1; /*!< bit: 8 Unclock data cache line. */
uint32_t _reserved1: 7; /*!< bit: 9..15 Reserved */
uint32_t BHT_INV: 1; /*!< bit: 16 Invalid data in branch history table */
uint32_t BTB_INV: 1; /*!< bit: 17 Invalid data in branch table buffer */
uint32_t _reserved2: 13; /*!< bit: 18..30 Reserved */
uint32_t LICF: 1; /*!< bit: 31 Failure of clearing or invalid cache line */
} b; /*!< Structure Access by bit */
uint32_t w; /*!< Type Access by whole register */
} CFR_Type;
#define CFR_LICF_Pos 31U /*!< CFR: LICF Position */
#define CFR_LICF_Msk (0x1UL << CFR_LICF_Pos) /*!< CFR: LICF Mask */
#define CFR_BTB_INV_Pos 17U /*!< CFR: BTB Position */
#define CFR_BTB_INV_Msk (0x1UL << CFR_BTB_INV_Pos) /*!< CFR: BTB Mask */
#define CFR_BHT_INV_Pos 16U /*!< CFR: BHT Position */
#define CFR_BHT_INV_Msk (0x1UL << CFR_BHT_INV_Pos) /*!< CFR: BHT Mask */
#define CFR_UNLOCK_Pos 8U /*!< CFR: UNLOCK Position */
#define CFR_UNLOCK_Msk (0x1UL << CFR_UNLOCK_Pos) /*!< CFR: UNLOCK Mask */
#define CFR_ITS_Pos 7U /*!< CFR: ITS Position */
#define CFR_ITS_Msk (0x1UL << CFR_ITS_Pos) /*!< CFR: ITS Mask */
#define CFR_OMS_Pos 6U /*!< CFR: OMS Position */
#define CFR_OMS_Msk (0x1UL << CFR_OMS_Pos) /*!< CFR: OMS Mask */
#define CFR_CLR_Pos 5U /*!< CFR: CLR Position */
#define CFR_CLR_Msk (0x1UL << CFR_CLR_Pos) /*!< CFR: CLR Mask */
#define CFR_INV_Pos 4U /*!< CFR: INV Position */
#define CFR_INV_Msk (0x1UL << CFR_INV_Pos) /*!< CFR: INV Mask */
#define CFR_CACHE_SEL_Pos 0 /*!< CFR: CACHE_SEL Position */
#define CFR_CACHE_SEL_Msk (0x3UL << CFR_CACHE_SEL_Pos) /*!< CFR: CACHE_SEL Masok */
/* CFR Register Definitions */
/*@} end of group CSI_CACHE */
/**
\ingroup CSI_core_register
\defgroup CSI_CACHE
\brief Type definitions for the cache Registers
@{
*/
#define SSEG0_BASE_ADDR 0x80000000
#define CACHE_RANGE_MAX_SIZE 0x80000
#define INS_CACHE (1 << 0)
#define DATA_CACHE (1 << 1)
#define CACHE_INV (1 << 4)
#define CACHE_CLR (1 << 5)
#define CACHE_OMS (1 << 6)
#define CACHE_ITS (1 << 7)
#define CACHE_LICF (1 << 31)
#define L1_CACHE_SHIFT 4 /* 16 Bytes */
#define L1_CACHE_BYTES (1 << L1_CACHE_SHIFT)
/**
\brief Mask and shift a bit field value for use in a register bit range.
\param[in] field Name of the register bit field.
\param[in] value Value of the bit field.
\return Masked and shifted value.
*/
#define _VAL2FLD(field, value) ((value << field ## _Pos) & field ## _Msk)
/**
\brief Mask and shift a register value to extract a bit filed value.
\param[in] field Name of the register bit field.
\param[in] value Value of register.
\return Masked and shifted bit field value.
*/
#define _FLD2VAL(field, value) ((value & field ## _Msk) >> field ## _Pos)
/*@} end of group CSI_core_bitfield */
/*******************************************************************************
* Hardware Abstraction Layer
Core Function Interface contains:
- Core VIC Functions
- Core CORET Functions
- Core Register Access Functions
******************************************************************************/
/* The following MACROS handle generation of the register offset and byte masks */
#define _BIT_SHIFT(IRQn) ( ((((uint32_t)(int32_t)(IRQn)) ) & 0x03UL) * 8UL)
#define _IP_IDX(IRQn) ( (((uint32_t)(int32_t)(IRQn)) >> 2UL) )
/* ########################## Cache functions #################################### */
/**
\ingroup CSI_Core_FunctionInterface
\defgroup CSI_Core_CacheFunctions Cache Functions
\brief Functions that configure Instruction and Data cache.
@{
*/
/**
\brief Enable I-Cache
\details Turns on I-Cache
*/
__STATIC_INLINE void csi_icache_enable (void)
{
__set_CCR(__get_CCR() | 0x00000004);
}
/**
\brief Disable I-Cache
\details Turns off I-Cache
*/
__STATIC_INLINE void csi_icache_disable (void)
{
__set_CCR(__get_CCR() & 0xFFFFFFFB);
}
/**
\brief Invalidate I-Cache
\details Invalidates I-Cache
*/
__STATIC_INLINE void csi_icache_invalid (void)
{
__set_CFR(0x11);
__set_CFR(INS_CACHE | CACHE_INV);
}
/**
\brief Enable D-Cache
\details Turns on D-Cache
\note I-Cache also turns on.
*/
__STATIC_INLINE void csi_dcache_enable (void)
{
__set_CCR(__get_CCR() | 0x00000008);
}
/**
\brief Disable D-Cache
\details Turns off D-Cache
\note I-Cache also turns off.
*/
__STATIC_INLINE void csi_dcache_disable (void)
{
__set_CCR(__get_CCR() & 0xFFFFFFF7);
}
/**
\brief Invalidate D-Cache
\details Invalidates D-Cache
\note I-Cache also invalid
*/
__STATIC_INLINE void csi_dcache_invalid (void)
{
__set_CFR(DATA_CACHE | CACHE_INV);
}
/**
\brief Clean D-Cache
\details Cleans D-Cache
\note I-Cache also cleans
*/
__STATIC_INLINE void csi_dcache_clean (void)
{
__set_CFR(DATA_CACHE | CACHE_CLR);
}
/**
\brief Clean & Invalidate D-Cache
\details Cleans and Invalidates D-Cache
\note I-Cache also flush.
*/
__STATIC_INLINE void csi_dcache_clean_invalid (void)
{
__set_CFR(DATA_CACHE | CACHE_CLR | CACHE_INV);
}
__STATIC_INLINE void set_cache_range (uint32_t start, uint32_t end, uint32_t value)
{
if (!(start & SSEG0_BASE_ADDR) || (end - start) &~(CACHE_RANGE_MAX_SIZE - 1)) {
__set_CFR(value);
}
if (value & INS_CACHE) {
csi_icache_disable();
}
uint32_t i;
for (i = start; i < end; i += L1_CACHE_BYTES) {
__set_CIR(i);
__set_CFR(CACHE_OMS | value);
}
if (end & (L1_CACHE_BYTES-1)) {
__set_CIR(end);
__set_CFR(CACHE_OMS | value);
}
if (value & INS_CACHE) {
csi_icache_enable();
}
}
/**
\brief D-Cache Invalidate by address
\details Invalidates D-Cache for the given address
\param[in] addr address (aligned to 16-byte boundary)
\param[in] dsize size of memory block (aligned to 16-byte boundary)
*/
__STATIC_INLINE void csi_dcache_invalid_range (uint32_t *addr, int32_t dsize)
{
set_cache_range((uint32_t)addr, (uint32_t)addr + dsize, (DATA_CACHE | CACHE_INV));
}
/**
\brief D-Cache Clean by address
\details Cleans D-Cache for the given address
\param[in] addr address (aligned to 16-byte boundary)
\param[in] dsize size of memory block (aligned to 16-byte boundary)
*/
__STATIC_INLINE void csi_dcache_clean_range (uint32_t *addr, int32_t dsize)
{
set_cache_range((uint32_t)addr, (uint32_t)addr + dsize, (DATA_CACHE | CACHE_CLR));
}
/**
\brief D-Cache Clean and Invalidate by address
\details Cleans and invalidates D_Cache for the given address
\param[in] addr address (aligned to 16-byte boundary)
\param[in] dsize size of memory block (aligned to 16-byte boundary)
*/
__STATIC_INLINE void csi_dcache_clean_invalid_range (uint32_t *addr, int32_t dsize)
{
set_cache_range((uint32_t)addr, (uint32_t)addr + dsize, (DATA_CACHE | CACHE_CLR | CACHE_INV));
}
/*@} end of CSI_Core_CacheFunctions */
/* ########################## MMU functions #################################### */
/**
\ingroup CSI_Core_FunctionInterface
\defgroup CSI_Core_MMUFunctions MMU Functions
\brief Functions that configure MMU.
@{
*/
typedef struct {
uint32_t global: 1; /* tlb page global access. */
uint32_t valid: 1; /* tlb page valid */
uint32_t writeable: 1; /* tlb page writeable */
uint32_t cacheable: 1; /* tlb page cacheable*/
uint32_t is_secure: 1; /* tlb page security access */
uint32_t strong_order: 1; /* the sequence of accessing data on tlb page is corresponding to the program flow? */
uint32_t bufferable: 1; /* tlb page bufferable */
} page_attr_t;
typedef enum {
PAGE_SIZE_4KB = 0x000,
PAGE_SIZE_16KB = 0x003,
PAGE_SIZE_64KB = 0x00F,
PAGE_SIZE_256KB = 0x03F,
PAGE_SIZE_1MB = 0x0FF,
PAGE_SIZE_4MB = 0x3FF,
PAGE_SIZE_16MB = 0xFFF
} page_size_e;
/**
\brief enable mmu
\details
*/
__STATIC_INLINE void csi_mmu_enable(void)
{
__set_CCR(__get_CCR() | (1u << CCR_MP_Pos));
}
/**
\brief disable mmu
\details
*/
__STATIC_INLINE void csi_mmu_disable(void)
{
__set_CCR(__get_CCR() & (~(1u << CCR_MP_Pos)));
}
/**
\brief create page with feature.
\details
\param [in] vaddr virtual address.
\param [in] paddr physical address.
\param [in] asid address sapce id (default: 0).
\param [in] attr \ref page_attr_t. tlb page attribute.
*/
__STATIC_INLINE void csi_mmu_set_tlb(uint32_t vaddr, uint32_t paddr, uint32_t asid, page_attr_t attr)
{
MPR_Type pgmask;
MEH_Type meh;
MEL_Type mel;
uint32_t vaddr_bit;
uint32_t page_feature = 0;
page_feature |= attr.global << MEL_G_Pos | attr.valid << MEL_V_Pos |
attr.writeable << MEL_D_Pos | attr.cacheable << MEL_C_Pos |
attr.is_secure << MEL_SEC_Pos | attr.strong_order << MEL_SO_Pos |
attr.bufferable << MEL_B_Pos;
pgmask.w = __get_MPR();
vaddr_bit = 44 - __FF0(~((uint32_t)pgmask.b.page_mask));
meh.b.ASID = (uint8_t)asid;
meh.b.VPN = (vaddr & ((~pgmask.w | 0xFE000000) & 0xFFFFE000)) >> MEH_VPN_Pos;
__set_MEH(meh.w);
__set_MCIR(1u << MCIR_TLBP_Pos);
mel.w = ((paddr & ~(pgmask.b.page_mask << 12)) | page_feature);
if (vaddr & (1 << vaddr_bit)) {
__set_MEL1(mel.w);
}
else {
__set_MEL0(mel.w);
}
if (__get_MIR() & (1 << MIR_P_Pos)) {
__set_MCIR(1u << MCIR_TLBWR_Pos);
} else {
__set_MCIR(1u << MCIR_TLBWI_Pos);
}
}
/**
\brief enble mmu
\details
\param [in] size tlb page size.
*/
__STATIC_INLINE void csi_mmu_set_pagesize(page_size_e size)
{
MPR_Type pgmask;
pgmask.b.page_mask = size;
__set_MPR(pgmask.w);
}
/**
\brief read MEH, MEL0, MEL1 by tlb index.
\details
\param [in] index tlb index(0, 1, 2, ...)
\param [out] meh pointer to variable for retrieving MEH.
\param [out] mel0 pointer to variable for retrieving MEL0.
\param [out] mel1 pointer to variable for retrieving MEL1.
*/
__STATIC_INLINE void csi_mmu_read_by_index(uint32_t index, uint32_t *meh, uint32_t *mel0, uint32_t *mel1)
{
MIR_Type mir;
if (meh == NULL || mel0 == NULL || mel1 == NULL) {
return;
}
mir.b.Index = index;
__set_MIR(mir.w);
__set_MCIR(1u << MCIR_TLBR_Pos);
*meh = __get_MEH();
*mel0 = __get_MEL0();
*mel1 = __get_MEL1();
}
/**
\brief flush all mmu tlb.
\details
*/
__STATIC_INLINE void csi_mmu_invalid_tlb_all(void)
{
__set_MCIR(1u << MCIR_TLBINV_ALL_Pos);
}
/**
\brief flush mmu tlb by index.
\details
*/
__STATIC_INLINE void csi_mmu_invalid_tlb_by_index(uint32_t index)
{
MIR_Type mir;
mir.b.Index = index;
__set_MIR(mir.w);
__set_MCIR(1u << MCIR_TLBINV_INDEX_Pos);
}
/**
\brief flush mmu tlb by virtual address.
\details
*/
__STATIC_INLINE void csi_mmu_invalid_tlb_by_vaddr(uint32_t vaddr, uint32_t asid)
{
__set_MEH(vaddr | (asid & MEH_ASID_Msk));
__set_MCIR(1u << MCIR_TLBP_Pos);
if (__get_MIR() & (1 << MIR_P_Pos)) {
return;
} else {
__set_MCIR(1u << MCIR_TLBINV_INDEX_Pos);
}
}
/*@} end of CSI_Core_MMUFunctions */
/* ################################## IRQ Functions ############################################ */
/**
\brief Save the Irq context
\details save the psr result before disable irq.
\param [in] irq_num External interrupt number. Value cannot be negative.
*/
__STATIC_INLINE uint32_t csi_irq_save(void)
{
uint32_t result;
result = __get_PSR();
__disable_irq();
return(result);
}
/**
\brief Restore the Irq context
\details restore saved primask state.
\param [in] irq_state psr irq state.
*/
__STATIC_INLINE void csi_irq_restore(uint32_t irq_state)
{
__set_PSR(irq_state);
}
/*@} end of IRQ Functions */
#ifdef __cplusplus
}
#endif
#endif /* __CORE_CK810_H_DEPENDANT */
#endif /* __CSI_GENERIC */

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/*
* Copyright (C) 2017-2019 Alibaba Group Holding Limited
*/
/******************************************************************************
* @file core_ck610.h
* @brief CSI CK610 Core Peripheral Access Layer Header File
* @version V1.0
* @date 02. June 2017
******************************************************************************/
#ifndef __CORE_CK610_H_GENERIC
#define __CORE_CK610_H_GENERIC
#include <stdint.h>
#include <stdio.h>
#ifdef __cplusplus
extern "C" {
#endif
/*******************************************************************************
* CSI definitions
******************************************************************************/
/**
\ingroup Ck610
@{
*/
/* CSI CK610 definitions */
#define __CK610_CSI_VERSION_MAIN (0x01U) /*!< [31:16] CSI HAL main version */
#define __CK610_CSI_VERSION_SUB (0x1EU) /*!< [15:0] CSI HAL sub version */
#define __CK610_CSI_VERSION ((__CK610_CSI_VERSION_MAIN << 16U) | \
__CK610_CSI_VERSION_SUB ) /*!< CSI HAL version number */
#define __CK610 (0x01U) /*!< CK610 Core */
/** __FPU_USED indicates whether an FPU is used or not.
This core does not support an FPU at all
*/
#define __FPU_USED 1U
#if defined ( __GNUC__ )
#if defined (__VFP_FP__) && !defined(__SOFTFP__)
#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
#endif
#endif
#ifdef __cplusplus
}
#endif
#endif /* __CORE_CK610_H_GENERIC */
#ifndef __CSI_GENERIC
#ifndef __CORE_CK610_H_DEPENDANT
#define __CORE_CK610_H_DEPENDANT
#ifdef __cplusplus
extern "C" {
#endif
/* check device defines and use defaults */
#ifndef __CK610_REV
#define __CK610_REV 0x0000U
#endif
#ifndef __GSR_GCR_PRESENT
#define __GSR_GCR_PRESENT 0U
#endif
#ifndef __MPU_PRESENT
#define __MPU_PRESENT 0U
#endif
#ifndef __ICACHE_PRESENT
#define __ICACHE_PRESENT 1U
#endif
#ifndef __DCACHE_PRESENT
#define __DCACHE_PRESENT 1U
#endif
#include <csi_gcc.h>
/* IO definitions (access restrictions to peripheral registers) */
/**
\defgroup CSI_glob_defs CSI Global Defines
<strong>IO Type Qualifiers</strong> are used
\li to specify the access to peripheral variables.
\li for automatic generation of peripheral register debug information.
*/
#ifdef __cplusplus
#define __I volatile /*!< Defines 'read only' permissions */
#else
#define __I volatile const /*!< Defines 'read only' permissions */
#endif
#define __O volatile /*!< Defines 'write only' permissions */
#define __IO volatile /*!< Defines 'read / write' permissions */
/* following defines should be used for structure members */
#define __IM volatile const /*! Defines 'read only' structure member permissions */
#define __OM volatile /*! Defines 'write only' structure member permissions */
#define __IOM volatile /*! Defines 'read / write' structure member permissions */
/*@} end of group CK610 */
/*******************************************************************************
* Register Abstraction
Core Register contain:
- Core Register
- Core MGU Register
- Core MMU Register
******************************************************************************/
/**
\defgroup CSI_core_register Defines and Type Definitions
\brief Type definitions and defines for CK610 processor based devices.
*/
/**
\brief Access Processor Status Register(PSR)struct definition.
*/
typedef union {
struct {
uint32_t C: 1; /*!< bit: 0 Conditional code/Carry flag */
uint32_t AF: 1; /*!< bit: 1 Alternate register valid control bit */
uint32_t _reserved0: 2; /*!< bit: 2.. 3 Reserved */
uint32_t FE: 1; /*!< bit: 4 Fast interrupt enable control bit */
uint32_t _reserved1: 1; /*!< bit: 5 Reserved */
uint32_t IE: 1; /*!< bit: 6 Interrupt effective control bit */
uint32_t IC: 1; /*!< bit: 7 Interrupt control bit */
uint32_t EE: 1; /*!< bit: 8 Abnormally effective control bit */
uint32_t MM: 1; /*!< bit: 9 Unsymmetrical masking bit */
uint32_t _reserved2: 2; /*!< bit: 10..11 Reserved */
uint32_t TE: 1; /*!< bit: 12 Trace transmission control bit */
uint32_t TP: 1; /*!< bit: 13 Pending trace exception set bit */
uint32_t TM: 2; /*!< bit: 14..15 Tracing mode bit */
uint32_t VEC: 8; /*!< bit: 16..23 Abnormal event vector value */
uint32_t CPID: 4; /*!< bit: 24..27 Number of processor currently running */
uint32_t _reserved3: 3; /*!< bit: 28..30 Reserved */
uint32_t S: 1; /*!< bit: 31 Superuser mode set bit */
} b; /*!< Structure Access by bit */
uint32_t w; /*!< Type Access by whole register */
} PSR_Type;
/* PSR Register Definitions */
#define PSR_S_Pos 31U /*!< PSR: S Position */
#define PSR_S_Msk (0x1UL << PSR_S_Pos) /*!< PSR: S Mask */
#define PSR_CPID_Pos 24U /*!< PSR: CPID Position */
#define PSR_CPID_Msk (0xFUL << PSR_CPID_Pos) /*!< PSR: CPID Mask */
#define PSR_VEC_Pos 16U /*!< PSR: VEC Position */
#define PSR_VEC_Msk (0xFFUL << PSR_VEC_Pos) /*!< PSR: VEC Mask */
#define PSR_TM_Pos 14U /*!< PSR: TM Position */
#define PSR_TM_Msk (0x3UL << PSR_TM_Pos) /*!< PSR: TM Mask */
#define PSR_TP_Pos 13U /*!< PSR: TP Position */
#define PSR_TP_Msk (0x1UL << PSR_TM_Pos) /*!< PSR: TP Mask */
#define PSR_TE_Pos 12U /*!< PSR: TE Position */
#define PSR_TE_Msk (0x1UL << PSR_TE_Pos) /*!< PSR: TE Mask */
#define PSR_MM_Pos 9U /*!< PSR: MM Position */
#define PSR_MM_Msk (0x1UL << PSR_MM_Pos) /*!< PSR: MM Mask */
#define PSR_EE_Pos 8U /*!< PSR: EE Position */
#define PSR_EE_Msk (0x1UL << PSR_EE_Pos) /*!< PSR: EE Mask */
#define PSR_IC_Pos 7U /*!< PSR: IC Position */
#define PSR_IC_Msk (0x1UL << PSR_IC_Pos) /*!< PSR: IC Mask */
#define PSR_IE_Pos 6U /*!< PSR: IE Position */
#define PSR_IE_Msk (0x1UL << PSR_IE_Pos) /*!< PSR: IE Mask */
#define PSR_FE_Pos 4U /*!< PSR: FE Position */
#define PSR_FE_Msk (0x1UL << PSR_FE_Pos) /*!< PSR: FE Mask */
#define PSR_AF_Pos 1U /*!< PSR: AF Position */
#define PSR_AF_Msk (0x1UL << PSR_AF_Pos) /*!< PSR: AF Mask */
#define PSR_C_Pos 0U /*!< PSR: C Position */
#define PSR_C_Msk (0x1UL << PSR_C_Pos) /*!< PSR: C Mask */
/**
\brief Consortium definition for accessing Cache Configuration Registers(CCR, CR<18, 0>).
*/
typedef union {
struct {
uint32_t MP: 2; /*!< bit: 0..1 Memory protection settings */
uint32_t IE: 1; /*!< bit: 2 Endian mode */
uint32_t DE: 1; /*!< bit: 3 Endian mode */
uint32_t WB: 1; /*!< bit: 4 Endian mode */
uint32_t RS: 1; /*!< bit: 5 Endian mode */
uint32_t Z: 1; /*!< bit: 6 Endian mode */
uint32_t BE: 1; /*!< bit: 7 Endian mode */
uint32_t SCK: 3; /*!< bit: 8..10 The clock ratio of the system and the processor */
uint32_t _reserved0: 21; /*!< bit: 11..31 Reserved */
} b; /*!< Structure Access by bit */
uint32_t w; /*!< Type Access by whole register */
} CCR_Type;
/* CCR Register Definitions */
#define CCR_SCK_Pos 8U /*!< CCR: SCK Position */
#define CCR_SCK_Msk (0x7UL << CCR_SCK_Pos) /*!< CCR: SCK Mask */
#define CCR_BE_Pos 7U /*!< CCR: BE Position */
#define CCR_BE_Msk (0x1UL << CCR_BE_Pos) /*!< CCR: BE Mask */
#define CCR_Z_Pos 6U /*!< CCR: Z Position */
#define CCR_Z_Msk (0x1UL << CCR_Z_Pos) /*!< CCR: Z Mask */
#define CCR_RS_Pos 5U /*!< CCR: RS Position */
#define CCR_RS_Msk (0x1UL << CCR_RS_Pos) /*!< CCR: RS Mask */
#define CCR_WB_Pos 4U /*!< CCR: WB Position */
#define CCR_WB_Msk (0x1UL << CCR_WB_Pos) /*!< CCR: WB Mask */
#define CCR_DE_Pos 3U /*!< CCR: DE Position */
#define CCR_DE_Msk (0x1UL << CCR_DE_Pos) /*!< CCR: DE Mask */
#define CCR_IE_Pos 2U /*!< CCR: IE Position */
#define CCR_IE_Msk (0x1UL << CCR_IE_Pos) /*!< CCR: IE Mask */
#define CCR_MP_Pos 0U /*!< CCR: MP Position */
#define CCR_MP_Msk (0x3UL << CCR_MP_Pos) /*!< CCR: MP Mask */
/**
\brief Consortium definition for accessing high ease access permission configutation registers(CAPR, CR<19,0>)
*/
typedef union {
struct {
uint32_t C0: 1; /*!< bit: 0 Cacheable setting */
uint32_t C1: 1; /*!< bit: 1 Cacheable setting */
uint32_t C2: 1; /*!< bit: 2 Cacheable setting */
uint32_t C3: 1; /*!< bit: 3 Cacheable setting */
uint32_t _reserved0: 4; /*!< bit: 4.. 7 Reserved */
uint32_t AP0: 2; /*!< bit: 8.. 9 access permissions settings bit */
uint32_t AP1: 2; /*!< bit: 10..11 access permissions settings bit */
uint32_t AP2: 2; /*!< bit: 12..13 access permissions settings bit */
uint32_t AP3: 2; /*!< bit: 14..15 access permissions settings bit */
uint32_t _reserved1: 16; /*!< bit: 16..31 Reserved */
} b; /*!< Structure Access by bit */
uint32_t w; /*!< Type Access by whole register */
} CAPR_Type;
/* CAPR Register Definitions */
#define CAPR_AP3_Pos 14U /*!< CAPR: AP3 Position */
#define CAPR_AP3_Msk (0x3UL << CAPR_AP3_Pos) /*!< CAPR: AP3 Mask */
#define CAPR_AP2_Pos 12U /*!< CAPR: AP2 Position */
#define CAPR_AP2_Msk (0x3UL << CAPR_AP2_Pos) /*!< CAPR: AP2 Mask */
#define CAPR_AP1_Pos 10U /*!< CAPR: AP1 Position */
#define CAPR_AP1_Msk (0x3UL << CAPR_AP1_Pos) /*!< CAPR: AP1 Mask */
#define CAPR_AP0_Pos 8U /*!< CAPR: AP0 Position */
#define CAPR_AP0_Msk (0x3UL << CAPR_AP0_Pos) /*!< CAPR: AP0 Mask */
#define CAPR_X3_Pos 3U /*!< CAPR: X3 Position */
#define CAPR_X3_Msk (0x1UL << CAPR_X3_Pos) /*!< CAPR: X3 Mask */
#define CAPR_X2_Pos 2U /*!< CAPR: X2 Position */
#define CAPR_X2_Msk (0x1UL << CAPR_X2_Pos) /*!< CAPR: X2 Mask */
#define CAPR_X1_Pos 1U /*!< CAPR: X1 Position */
#define CAPR_X1_Msk (0x1UL << CAPR_X1_Pos) /*!< CAPR: X1 Mask */
#define CAPR_X0_Pos 0U /*!< CAPR: X0 Position */
#define CAPR_X0_Msk (0x1UL << CAPR_X0_Pos) /*!< CAPR: X0 Mask */
/**
\brief Consortium definition for accessing control register(PACR, CR<20,0>).
*/
typedef union {
struct {
uint32_t E: 1; /*!< bit: 0 Effective setting of protected area */
uint32_t size: 5; /*!< bit: 1.. 5 Size of protected area */
uint32_t _reserved0: 6; /*!< bit: 6.. 11 Reserved */
uint32_t base_addr: 20; /*!< bit: 10..31 The high position of the address of a protected area */
} b; /*!< Structure Access by bit */
uint32_t w; /*!< Type Access by whole register */
} PACR_Type;
/* PACR Register Definitions */
#define PACR_BASE_ADDR_Pos 12U /*!< PACR: base_addr Position */
#define PACR_BASE_ADDR_Msk (0xFFFFFUL << PACR_BASE_ADDR_Pos) /*!< PACR: base_addr Mask */
#define PACR_SIZE_Pos 1U /*!< PACR: Size Position */
#define PACR_SIZE_Msk (0x1FUL << PACR_SIZE_Pos) /*!< PACR: Size Mask */
#define PACR_E_Pos 0U /*!< PACR: E Position */
#define PACR_E_Msk (0x1UL << PACR_E_Pos) /*!< PACR: E Mask */
/**
\brief Consortium definition for accessing protection area selection register(PRSR,CR<21,0>).
*/
typedef union {
struct {
uint32_t RID: 2; /*!< bit: 0.. 1 Protected area index value */
uint32_t _reserved0: 30; /*!< bit: 2..31 Reserved */
} b; /*!< Structure Access by bit */
uint32_t w; /*!< Type Access by whole register */
} PRSR_Type;
/* PRSR Register Definitions */
#define PRSR_RID_Pos 0U /*!< PRSR: RID Position */
#define PRSR_RID_Msk (0x3UL << PRSR_RID_Pos) /*!< PRSR: RID Mask */
/**
\brief Consortium definition for accessing mmu index register(MIR,CP15_CR0).
*/
typedef union {
struct {
uint32_t Index: 10;
uint32_t _reserved: 20;
uint32_t TF: 1;
uint32_t P: 1;
} b;
uint32_t w;
} MIR_Type;
/* MIR Register Definitions */
#define MIR_P_Pos 31 /*!< PRSR: P(TLBP instruction) Position */
#define MIR_P_Msk (0x1UL << MIR_P_Pos) /*!< PRSR: P(TLBP instruction) Mask */
#define MIR_TF_Pos 30 /*!< PRSR: Tfatal Position */
#define MIR_TF_Msk (0x1UL << MIR_TF_Pos) /*!< PRSR: Tfatal Mask */
#define MIR_Index_Pos 0 /*!< PRSR: Index Position */
#define MIR_Index_Msk (0x3ffUL << MIR_Index_Pos) /*!< PRSR: Index Mask */
/**
\brief Consortium definition for accessing mmu entry of high physical address register(MEL, CP15_CR2 and CP15_CR3).
*/
typedef union {
struct {
uint32_t G: 1;
uint32_t V: 1;
uint32_t D: 1;
uint32_t C: 3;
uint32_t PFN: 20;
uint32_t _reserved: 6;
} b;
uint32_t w;
} MEL_Type;
/* MEL Register Definitions */
#define MEL_PFN_Pos 6 /*!< MEL: PFN Position */
#define MEL_PFN_Msk (0xFFFFFUL << MEL_PFN_Pos) /*!< MEL: PFN Mask */
#define MEL_C_Pos 3 /*!< MEL: C Position */
#define MEL_C_Msk (0x7UL << MEL_C_Pos) /*!< MEL: C Mask */
#define MEL_D_Pos 2 /*!< MEL: D Position */
#define MEL_D_Msk (0x1UL << MIR_D_Pos) /*!< MEL: D Mask */
#define MEL_V_Pos 1 /*!< MEL: V Position */
#define MEL_V_Msk (0x1UL << MIR_V_Pos) /*!< MEL: V Mask */
#define MEL_G_Pos 0 /*!< MEL: G Position */
#define MEL_G_Msk (0x1UL << MIR_G_Pos) /*!< MEL: G Mask */
/**
\brief Consortium definition for accessing mmu entry of high physical address register(MEH, CP15_CR4).
*/
typedef union {
struct {
uint32_t ASID :8;
uint32_t _reserved :4;
uint32_t VPN :20;
} b;
uint32_t w;
} MEH_Type;
/* MEH Register Definitions */
#define MEH_VPN_Pos 12 /*!< MEH: VPN Position */
#define MEH_VPN_Msk (0xFFFFFUL << MEH_VPN_Pos) /*!< MEH: VPN Mask */
#define MEH_ASID_Pos 0 /*!< MEH: ASID Position */
#define MEH_ASID_Msk (0xFFUL << MEH_ASID_Pos) /*!< MEH: ASID Mask */
/**
\brief Consortium definition for accessing mmu entry of high physical address register(MPR, CP15_CR6).
*/
typedef union {
struct {
uint32_t _reserved0: 13;
uint32_t page_mask: 12;
uint32_t _reserved1: 7;
} b;
uint32_t w;
} MPR_Type;
/* MPR Register Definitions */
#define MPR_PAGE_MASK_Pos 13 /*!< MPR: PAGE_MASK Position */
#define MPR_PAGE_MASK_Msk (0xFFFUL << MPR_PAGE_MASK_Pos) /*!< MPR: PAGE_MASK Mask */
/**
\brief Consortium definition for accessing mmu entry of high physical address register(MCIR, CP15_CR8).
*/
typedef union {
struct {
uint32_t ASID: 8;
uint32_t _reserved: 17;
uint32_t TLBINV_INDEX: 1;
uint32_t TLBINV_ALL: 1;
uint32_t TLBINV: 1;
uint32_t TLBWR: 1;
uint32_t TLBWI: 1;
uint32_t TLBR: 1;
uint32_t TLBP: 1;
} b;
uint32_t w;
} MCIR_Type;
/* MCIR Register Definitions */
#define MCIR_TLBP_Pos 31 /*!< MCIR: TLBP Position */
#define MCIR_TLBP_Msk (0x1UL << MCIR_TLBP_Pos) /*!< MCIR: TLBP Mask */
#define MCIR_TLBR_Pos 30 /*!< MCIR: TLBR Position */
#define MCIR_TLBR_Msk (0x1UL << MCIR_TLBR_Pos) /*!< MCIR: TLBR Mask */
#define MCIR_TLBWI_Pos 29 /*!< MCIR: TLBWI Position */
#define MCIR_TLBWI_Msk (0x1UL << MCIR_TLBWI_Pos) /*!< MCIR: TLBWI Mask */
#define MCIR_TLBWR_Pos 28 /*!< MCIR: TLBWR Position */
#define MCIR_TLBWR_Msk (0x1UL << MCIR_TLBWR_Pos) /*!< MCIR: TLBWR Mask */
#define MCIR_TLBINV_Pos 27 /*!< MCIR: TLBINV Position */
#define MCIR_TLBINV_Msk (0x1UL << MCIR_TLBINV_Pos) /*!< MCIR: TLBINV Mask */
#define MCIR_TLBINV_ALL_Pos 26 /*!< MCIR: TLBINV_ALL Position */
#define MCIR_TLBINV_ALL_Msk (0x1UL << MCIR_TLBINV_ALL_Pos) /*!< MCIR: TLBINV_ALL Mask */
#define MCIR_TLBINV_INDEX_Pos 25 /*!< MCIR: TLBINV_INDEX Position */
#define MCIR_TLBINV_INDEX_Msk (0x1UL << MCIR_TLBINV_INDEX_Pos) /*!< MCIR: TLBINV_INDEX Mask */
#define MCIR_ASID_Pos 0 /*!< MCIR: ASID Position */
#define MCIR_ASID_Msk (0xFFUL << MCIR_ASID_Pos) /*!< MCIR: ASID Mask */
/*@} end of group CSI_CORE */
/**
\ingroup CSI_core_register
\defgroup CSI_CACHE
\brief Type definitions for the cache Registers
@{
*/
#define SSEG0_BASE_ADDR 0x80000000
#define CACHE_RANGE_MAX_SIZE 0x80000
#define INS_CACHE (1 << 0)
#define DATA_CACHE (1 << 1)
#define CACHE_INV (1 << 4)
#define CACHE_CLR (1 << 5)
#define CACHE_OMS (1 << 6)
#define CACHE_ITS (1 << 7)
#define CACHE_LICF (1 << 31)
#define L1_CACHE_SHIFT 4 /* 16 Bytes */
#define L1_CACHE_BYTES (1 << L1_CACHE_SHIFT)
/**
\brief Mask and shift a bit field value for use in a register bit range.
\param[in] field Name of the register bit field.
\param[in] value Value of the bit field.
\return Masked and shifted value.
*/
#define _VAL2FLD(field, value) ((value << field ## _Pos) & field ## _Msk)
/**
\brief Mask and shift a register value to extract a bit filed value.
\param[in] field Name of the register bit field.
\param[in] value Value of register.
\return Masked and shifted bit field value.
*/
#define _FLD2VAL(field, value) ((value & field ## _Msk) >> field ## _Pos)
/*@} end of group CSI_core_bitfield */
/*******************************************************************************
* Hardware Abstraction Layer
Core Function Interface contains:
- Core VIC Functions
- Core CORET Functions
- Core Register Access Functions
******************************************************************************/
/* ########################## Cache functions #################################### */
/**
\ingroup CSI_Core_FunctionInterface
\defgroup CSI_Core_CacheFunctions Cache Functions
\brief Functions that configure Instruction and Data cache.
@{
*/
/**
\brief Enable I-Cache
\details Turns on I-Cache
*/
__STATIC_INLINE void csi_icache_enable (void)
{
__set_CCR(__get_CCR() | 0x00000004);
}
/**
\brief Disable I-Cache
\details Turns off I-Cache
*/
__STATIC_INLINE void csi_icache_disable (void)
{
__set_CCR(__get_CCR() & 0xFFFFFFFB);
}
/**
\brief Invalidate I-Cache
\details Invalidates I-Cache
*/
__STATIC_INLINE void csi_icache_invalid (void)
{
__set_CFR(0x11);
__set_CFR(INS_CACHE | CACHE_INV);
}
/**
\brief Enable D-Cache
\details Turns on D-Cache
\note I-Cache also turns on.
*/
__STATIC_INLINE void csi_dcache_enable (void)
{
__set_CCR(__get_CCR() | 0x00000008);
}
/**
\brief Disable D-Cache
\details Turns off D-Cache
\note I-Cache also turns off.
*/
__STATIC_INLINE void csi_dcache_disable (void)
{
__set_CCR(__get_CCR() & 0xFFFFFFF7);
}
/**
\brief Invalidate D-Cache
\details Invalidates D-Cache
\note I-Cache also invalid
*/
__STATIC_INLINE void csi_dcache_invalid (void)
{
__set_CFR(DATA_CACHE | CACHE_INV);
}
/**
\brief Clean D-Cache
\details Cleans D-Cache
\note I-Cache also cleans
*/
__STATIC_INLINE void csi_dcache_clean (void)
{
__set_CFR(DATA_CACHE | CACHE_CLR);
}
/**
\brief Clean & Invalidate D-Cache
\details Cleans and Invalidates D-Cache
\note I-Cache also flush.
*/
__STATIC_INLINE void csi_dcache_clean_invalid (void)
{
__set_CFR(DATA_CACHE | CACHE_CLR | CACHE_INV);
}
__STATIC_INLINE void set_cache_range (uint32_t start, uint32_t end, uint32_t value)
{
if (!(start & SSEG0_BASE_ADDR) || (end - start) &~(CACHE_RANGE_MAX_SIZE - 1)) {
__set_CFR(value);
}
if (value & INS_CACHE) {
csi_icache_disable();
}
uint32_t i;
for (i = start; i < end; i += L1_CACHE_BYTES) {
__set_CIR(i);
__set_CFR(CACHE_OMS | value);
}
if (end & (L1_CACHE_BYTES-1)) {
__set_CIR(end);
__set_CFR(CACHE_OMS | value);
}
if (value & INS_CACHE) {
csi_icache_enable();
}
}
/**
\brief D-Cache Invalidate by address
\details Invalidates D-Cache for the given address
\param[in] addr address (aligned to 16-byte boundary)
\param[in] dsize size of memory block (in number of bytes)
*/
__STATIC_INLINE void csi_dcache_invalid_range (uint32_t *addr, int32_t dsize)
{
set_cache_range((uint32_t)addr, (uint32_t)addr + dsize, (DATA_CACHE | CACHE_INV));
}
/**
\brief D-Cache Clean by address
\details Cleans D-Cache for the given address
\param[in] addr address (aligned to 16-byte boundary)
\param[in] dsize size of memory block (in number of bytes)
*/
__STATIC_INLINE void csi_dcache_clean_range (uint32_t *addr, int32_t dsize)
{
set_cache_range((uint32_t)addr, (uint32_t)addr + dsize, (DATA_CACHE | CACHE_CLR));
}
/**
\brief D-Cache Clean and Invalidate by address
\details Cleans and invalidates D_Cache for the given address
\param[in] addr address (aligned to 16-byte boundary)
\param[in] dsize size of memory block (in number of bytes)
*/
__STATIC_INLINE void csi_dcache_clean_invalid_range (uint32_t *addr, int32_t dsize)
{
set_cache_range((uint32_t)addr, (uint32_t)addr + dsize, (DATA_CACHE | CACHE_CLR | CACHE_INV));
}
/*@} end of CSI_Core_CacheFunctions */
/* ########################## MMU functions #################################### */
/**
\ingroup CSI_Core_FunctionInterface
\defgroup CSI_Core_MMUFunctions MMU Functions
\brief Functions that configure MMU.
@{
*/
typedef struct {
uint32_t global: 1; /* tlb page global access. */
uint32_t valid: 1; /* tlb page valid */
uint32_t writeable: 1; /* tlb page writeable */
uint32_t cacheable: 1; /* tlb page cacheable*/
} page_attr_t;
typedef enum {
PAGE_SIZE_4KB = 0x000,
PAGE_SIZE_16KB = 0x003,
PAGE_SIZE_64KB = 0x00F,
PAGE_SIZE_256KB = 0x03F,
PAGE_SIZE_1MB = 0x0FF,
PAGE_SIZE_4MB = 0x3FF,
PAGE_SIZE_16MB = 0xFFF
} page_size_e;
/**
\brief enable mmu
\details
*/
__STATIC_INLINE void csi_mmu_enable(void)
{
__set_CCR(__get_CCR() | (1u << CCR_MP_Pos));
}
/**
\brief disable mmu
\details
*/
__STATIC_INLINE void csi_mmu_disable(void)
{
__set_CCR(__get_CCR() & (~(1u << CCR_MP_Pos)));
}
/**
\brief create page with feature.
\details
\param [in] vaddr virtual address.
\param [in] paddr physical address.
\param [in] asid address sapce id (default: 0).
\param [in] attr \ref page_attr_t. tlb page attribute.
*/
__STATIC_INLINE void csi_mmu_set_tlb(uint32_t vaddr, uint32_t paddr, uint32_t asid, page_attr_t attr)
{
MPR_Type pgmask;
MEL_Type mel;
MEH_Type meh;
uint32_t vaddr_bit = 0;
uint32_t page_feature = 0;
page_feature |= attr.global << MEL_G_Pos | attr.valid << MEL_V_Pos |
attr.writeable << MEL_D_Pos | (attr.cacheable | 0x2) << MEL_C_Pos;
pgmask.w = __FF1(__get_MPR());
vaddr_bit = (pgmask.w == 32 ? 12 : (31 - pgmask.w));
meh.b.ASID = asid;
meh.b.VPN = (vaddr & ((~pgmask.w | 0xFE000000) & 0xFFFFE000)) >> MEH_VPN_Pos;
__set_MEH(meh.w);
__set_MCIR(1u << MCIR_TLBP_Pos);
mel.w = (((paddr >> 6) & ~(pgmask.b.page_mask << 6)) | page_feature);
if (vaddr & (1 << vaddr_bit)) {
__set_MEL1(mel.w);
} else {
__set_MEL0(mel.w);
}
if (__get_MIR() & (1 << MIR_P_Pos)) {
__set_MCIR(1u << MCIR_TLBWR_Pos);
} else {
__set_MCIR(1u << MCIR_TLBWI_Pos);
}
}
/**
\brief enble mmu
\details
\param [in] size tlb page size.
*/
__STATIC_INLINE void csi_mmu_set_pagesize(page_size_e size)
{
MPR_Type mpr;
mpr.w = __get_MPR();
mpr.b.page_mask = size;
__set_MPR(mpr.w);
}
/**
\brief read MEH, MEL0, MEL1 by tlb index.
\details
\param [in] index tlb index(0, 1, 2, ...)
\param [out] meh pointer to variable for retrieving MEH.
\param [out] mel0 pointer to variable for retrieving MEL0.
\param [out] mel1 pointer to variable for retrieving MEL1.
*/
__STATIC_INLINE void csi_mmu_read_by_index(uint32_t index, uint32_t *meh, uint32_t *mel0, uint32_t *mel1)
{
MIR_Type mir;
if (meh == NULL || mel0 == NULL || mel1 == NULL) {
return;
}
mir.b.Index = index;
__set_MIR(mir.w);
__set_MCIR(1u << MCIR_TLBR_Pos);
*meh = __get_MEH();
*mel0 = __get_MEL0();
*mel1 = __get_MEL1();
}
/**
\brief flush all mmu tlb.
\details
*/
__STATIC_INLINE void csi_mmu_invalid_tlb_all(void)
{
__set_MCIR(1u << MCIR_TLBINV_ALL_Pos);
}
/**
\brief flush mmu tlb by index.
\details
*/
__STATIC_INLINE void csi_mmu_invalid_tlb_by_index(uint32_t index)
{
MIR_Type mir;
mir.b.Index = index;
__set_MIR(mir.w);
__set_MCIR(1u << MCIR_TLBINV_INDEX_Pos);
}
/**
\brief flush mmu tlb by virtual address.
\details
*/
__STATIC_INLINE void csi_mmu_invalid_tlb_by_vaddr(uint32_t vaddr, uint32_t asid)
{
__set_MEH(vaddr | (asid & MEH_ASID_Msk));
__set_MCIR(__get_MCIR() | (1 << MCIR_TLBP_Pos));
if (__get_MIR() & (1 << MIR_P_Pos)) {
return;
} else {
__set_MCIR(__get_MCIR() | (1 << MCIR_TLBINV_INDEX_Pos));
}
}
/*@} end of CSI_Core_MMUFunctions */
/* ########################## MPU functions #################################### */
/**
\ingroup CSI_Core_FunctionInterface
\defgroup CSI_Core_MPUFunctions MPU Functions
\brief Functions that configure MPU.
@{
*/
typedef enum {
REGION_SIZE_4KB = 0xB,
REGION_SIZE_8KB = 0xC,
REGION_SIZE_16KB = 0xD,
REGION_SIZE_32KB = 0xE,
REGION_SIZE_64KB = 0xF,
REGION_SIZE_128KB = 0x10,
REGION_SIZE_256KB = 0x11,
REGION_SIZE_512KB = 0x12,
REGION_SIZE_1MB = 0x13,
REGION_SIZE_2MB = 0x14,
REGION_SIZE_4MB = 0x15,
REGION_SIZE_8MB = 0x16,
REGION_SIZE_16MB = 0x17,
REGION_SIZE_32MB = 0x18,
REGION_SIZE_64MB = 0x19,
REGION_SIZE_128MB = 0x1A,
REGION_SIZE_256MB = 0x1B,
REGION_SIZE_512MB = 0x1C,
REGION_SIZE_1GB = 0x1D,
REGION_SIZE_2GB = 0x1E,
REGION_SIZE_4GB = 0x1F
} region_size_e;
typedef enum {
AP_BOTH_INACCESSIBLE = 0,
AP_SUPER_RW_USER_INACCESSIBLE,
AP_SUPER_RW_USER_RDONLY,
AP_BOTH_RW
} access_permission_e;
typedef struct {
access_permission_e ap: 2; /* super user and normal user access.*/
uint32_t c: 1; /* cacheable */
} mpu_region_attr_t;
/**
\brief enable mpu
\details
*/
__STATIC_INLINE void csi_mpu_enable(void)
{
__set_CCR(__get_CCR() | CCR_MP_Msk);
}
/**
\brief disable mpu
\details
*/
__STATIC_INLINE void csi_mpu_disable(void)
{
__set_CCR(__get_CCR() & (~CCR_MP_Msk));
}
/**
\brief configure memory protected region.
\details
\param [in] idx memory protected region (0, 1, 2, 3.).
\param [in] base_addr base address must be aligned with page size.
\param [in] size \ref region_size_e. memory protected region size.
\param [in] attr \ref region_size_t. memory protected region attribute.
\param [in] enable enable or disable memory protected region.
*/
__STATIC_INLINE void csi_mpu_config_region(uint32_t idx, uint32_t base_addr, region_size_e size,
mpu_region_attr_t attr, uint32_t enable)
{
if (idx > 3) {
return;
}
CAPR_Type capr;
PACR_Type pacr;
PRSR_Type prsr;
capr.w = __get_CAPR();
pacr.w = __get_PACR();
prsr.w = __get_PRSR();
pacr.b.base_addr = (base_addr >> PACR_BASE_ADDR_Pos) & (0xFFFFF);
prsr.b.RID = idx;
__set_PRSR(prsr.w);
if (size != REGION_SIZE_4KB) {
pacr.w &= ~(((1u << (size -11)) - 1) << 12);
}
pacr.b.size = size;
capr.w = (0xFFFFFFFE & capr.w) | (attr.c << idx);
capr.w = ((~((0x3) << (2*idx + 8))) & capr.w) | (attr.ap << (2*idx + 8));
__set_CAPR(capr.w);
pacr.b.E = enable;
__set_PACR(pacr.w);
}
/**
\brief enable mpu region by idx.
\details
\param [in] idx memory protected region (0, 1, 2, 3.).
*/
__STATIC_INLINE void csi_mpu_enable_region(uint32_t idx)
{
if (idx > 3) {
return;
}
__set_PRSR((__get_PRSR() & (~PRSR_RID_Msk)) | idx);
__set_PACR(__get_PACR() | PACR_E_Msk);
}
/**
\brief disable mpu region by idx.
\details
\param [in] idx memory protected region (0, 1, 2, 3.).
*/
__STATIC_INLINE void csi_mpu_disable_region(uint32_t idx)
{
if (idx > 3) {
return;
}
__set_PRSR((__get_PRSR() & (~PRSR_RID_Msk)) | idx);
__set_PACR(__get_PACR() & (~PACR_E_Msk));
}
/*@} end of CSI_Core_MMUFunctions */
/*@} */
#ifdef __cplusplus
}
#endif
#endif /* __CORE_CK610_H_DEPENDANT */
#endif /* __CSI_GENERIC */

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/*
* Copyright (C) 2017-2019 Alibaba Group Holding Limited
*/
/******************************************************************************
* @file core_ck801.h
* @brief CSI CK801 Core Peripheral Access Layer Header File
* @version V1.0
* @date 02. June 2017
******************************************************************************/
#ifndef __CORE_CK801_H_GENERIC
#define __CORE_CK801_H_GENERIC
#include <core_801.h>
#endif /* __CORE_CK801_H_DEPENDANT */

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/*
* Copyright (C) 2017-2019 Alibaba Group Holding Limited
*/
/******************************************************************************
* @file core_ck802.h
* @brief CSI CK802 Core Peripheral Access Layer Header File
* @version V1.0
* @date 02. June 2017
******************************************************************************/
#ifndef __CORE_CK802_H_GENERIC
#define __CORE_CK802_H_GENERIC
#include <core_802.h>
#endif /* __CORE_CK802_H_DEPENDANT */

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/*
* Copyright (C) 2017-2019 Alibaba Group Holding Limited
*/
/******************************************************************************
* @file core_ck803.h
* @brief CSI CK803 Core Peripheral Access Layer Header File
* @version V1.0
* @date 02. June 2017
******************************************************************************/
#ifndef __CORE_CK803_H_GENERIC
#define __CORE_CK803_H_GENERIC
#include <core_803.h>
#endif /* __CORE_CK803_H_DEPENDANT */

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/*
* Copyright (C) 2017-2019 Alibaba Group Holding Limited
*/
/******************************************************************************
* @file core_ck807.h
* @brief CSI CK807 Core Peripheral Access Layer Header File
* @version V1.0
* @date 26. Jan 2018
******************************************************************************/
#ifndef __CORE_CK807_H_GENERIC
#define __CORE_CK807_H_GENERIC
#include <stdint.h>
#ifdef __cplusplus
extern "C" {
#endif
/*******************************************************************************
* CSI definitions
******************************************************************************/
/**
\ingroup CK807
@{
*/
/* CSI CK807 definitions */
#define __CK807_CSI_VERSION_MAIN (0x04U) /*!< [31:16] CSI HAL main version */
#define __CK807_CSI_VERSION_SUB (0x1EU) /*!< [15:0] CSI HAL sub version */
#define __CK807_CSI_VERSION ((__CK807_CSI_VERSION_MAIN << 16U) | \
__CK807_CSI_VERSION_SUB ) /*!< CSI HAL version number */
#ifndef __CK807
#define __CK807 (0x07U) /*!< CK807 Core */
#endif
/** __FPU_USED indicates whether an FPU is used or not.
*/
#define __FPU_USED 1U
#if defined ( __GNUC__ )
#if defined (__VFP_FP__) && !defined(__SOFTFP__)
#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
#endif
#endif
#ifdef __cplusplus
}
#endif
#endif /* __CORE_CK807_H_GENERIC */
#ifndef __CSI_GENERIC
#ifndef __CORE_CK807_H_DEPENDANT
#define __CORE_CK807_H_DEPENDANT
#ifdef __cplusplus
extern "C" {
#endif
/* check device defines and use defaults */
#ifndef __CK807_REV
#define __CK807_REV 0x0000U
#endif
#ifndef __GSR_GCR_PRESENT
#define __GSR_GCR_PRESENT 0U
#endif
#ifndef __ICACHE_PRESENT
#define __ICACHE_PRESENT 1U
#endif
#ifndef __DCACHE_PRESENT
#define __DCACHE_PRESENT 1U
#endif
#include <csi_gcc.h>
/* IO definitions (access restrictions to peripheral registers) */
/**
\defgroup CSI_glob_defs CSI Global Defines
<strong>IO Type Qualifiers</strong> are used
\li to specify the access to peripheral variables.
\li for automatic generation of peripheral register debug information.
*/
#ifdef __cplusplus
#define __I volatile /*!< Defines 'read only' permissions */
#else
#define __I volatile const /*!< Defines 'read only' permissions */
#endif
#define __O volatile /*!< Defines 'write only' permissions */
#define __IO volatile /*!< Defines 'read / write' permissions */
/* following defines should be used for structure members */
#define __IM volatile const /*! Defines 'read only' structure member permissions */
#define __OM volatile /*! Defines 'write only' structure member permissions */
#define __IOM volatile /*! Defines 'read / write' structure member permissions */
/*@} end of group CK807 */
/*******************************************************************************
* Register Abstraction
Core Register contain:
- Core Register
******************************************************************************/
/**
\defgroup CSI_core_register Defines and Type Definitions
\brief Type definitions and defines for CK807 processor based devices.
*/
/**
\ingroup CSI_core_register
\defgroup CSI_CORE Status and Control Registers
\brief Core Register type definitions.
@{
*/
/**
\brief Access Processor Status Register(PSR)struct definition.
*/
typedef union {
struct {
uint32_t C: 1; /*!< bit: 0 Conditional code/Carry flag */
uint32_t _reserved0: 5; /*!< bit: 2.. 5 Reserved */
uint32_t IE: 1; /*!< bit: 6 Interrupt effective control bit */
uint32_t IC: 1; /*!< bit: 7 Interrupt control bit */
uint32_t EE: 1; /*!< bit: 8 Abnormally effective control bit */
uint32_t MM: 1; /*!< bit: 9 Unsymmetrical masking bit */
uint32_t _reserved1: 6; /*!< bit: 10..15 Reserved */
uint32_t VEC: 8; /*!< bit: 16..23 Abnormal event vector value */
uint32_t _reserved2: 5; /*!< bit: 24..28 Reserved */
uint32_t SP: 1; /*!< bit: 29 Secure pedning bit */
uint32_t T: 1; /*!< bit: 30 TEE mode bit */
uint32_t S: 1; /*!< bit: 31 Superuser mode set bit */
} b; /*!< Structure Access by bit */
uint32_t w; /*!< Type Access by whole register */
} PSR_Type;
/* PSR Register Definitions */
#define PSR_S_Pos 31U /*!< PSR: S Position */
#define PSR_S_Msk (1UL << PSR_S_Pos) /*!< PSR: S Mask */
#define PSR_VEC_Pos 16U /*!< PSR: VEC Position */
#define PSR_VEC_Msk (0x7FUL << PSR_VEC_Pos) /*!< PSR: VEC Mask */
#define PSR_MM_Pos 9U /*!< PSR: MM Position */
#define PSR_MM_Msk (1UL << PSR_MM_Pos) /*!< PSR: MM Mask */
#define PSR_EE_Pos 8U /*!< PSR: EE Position */
#define PSR_EE_Msk (1UL << PSR_EE_Pos) /*!< PSR: EE Mask */
#define PSR_IC_Pos 7U /*!< PSR: IC Position */
#define PSR_IC_Msk (1UL << PSR_IC_Pos) /*!< PSR: IC Mask */
#define PSR_IE_Pos 6U /*!< PSR: IE Position */
#define PSR_IE_Msk (1UL << PSR_IE_Pos) /*!< PSR: IE Mask */
#define PSR_C_Pos 0U /*!< PSR: C Position */
#define PSR_C_Msk (1UL << PSR_C_Pos) /*!< PSR: C Mask */
/**
\brief Consortium definition for accessing Cache Configuration Registers(CCR, CR<18, 0>).
*/
typedef union {
struct {
uint32_t MP: 2; /*!< bit: 0.. 1 memory protection settings */
uint32_t IE: 1; /*!< bit: 2 Instruction cache enable */
uint32_t DE: 1; /*!< bit: 3 Data cache enable */
uint32_t WB: 1; /*!< bit: 4 Cache write back */
uint32_t RS: 1; /*!< bit: 5 Address return stack settings */
uint32_t Z: 1; /*!< bit: 6 Allow predictive jump bit */
uint32_t BE: 1; /*!< bit: 7 Endian mode */
uint32_t SCK: 3; /*!< bit: 8..10 the clock ratio of the system and the processor */
uint32_t _reserved0: 1; /*!< bit: 11 Reserved */
uint32_t WA: 1; /*!< bit: 12 Write allocate enable */
uint32_t E_V2: 1; /*!< bit: 13 V2 Endian mode */
uint32_t BSTE: 1; /*!< bit: 14 Burst transmit enable */
uint32_t IPE: 1; /*!< bit: 15 Indirect predict enable */
uint32_t _reserved1: 16; /*!< bit: 16..31 Reserved */
} b; /*!< Structure Access by bit */
uint32_t w; /*!< Type Access by whole register */
} CCR_Type;
/* CCR Register Definitions */
#define CCR_IPE_Pos 15u /*!< CCR: IPE Position */
#define CCR_IPE_Msk (0x1UL << CCR_IPE_Pos) /*!< CCR: IPE Mask */
#define CCR_BSTE_Pos 14u /*!< CCR: BSTE Position */
#define CCR_BSTE_Msk (0x1UL << CCR_BSTE_Pos) /*!< CCR: BSTE Mask */
#define CCR_E_V2_Pos 13U /*!< CCR: E_V2 Position */
#define CCR_E_V2_Msk (0x1UL << CCR_E_V2_Pos) /*!< CCR: E_V2 Mask */
#define CCR_WA_Pos 12u /*!< CCR: WA Position */
#define CCR_WA_Msk (0x1UL << CCR_WA_Pos) /*!< CCR: WA Mask */
#define CCR_SCK_Pos 8U /*!< CCR: SCK Position */
#define CCR_SCK_Msk (0x3UL << CCR_SCK_Pos) /*!< CCR: SCK Mask */
#define CCR_BE_Pos 7U /*!< CCR: BE Position */
#define CCR_BE_Msk (0x1UL << CCR_BE_Pos) /*!< CCR: BE Mask */
#define CCR_Z_Pos 6U /*!< CCR: Z Position */
#define CCR_Z_Msk (0x1UL << CCR_BE_Pos) /*!< CCR: Z Mask */
#define CCR_RS_Pos 5U /*!< CCR: RS Position */
#define CCR_RS_Msk (0x1UL << CCR_BE_Pos) /*!< CCR: RS Mask */
#define CCR_WB_Pos 4U /*!< CCR: WB Position */
#define CCR_WB_Msk (0x1UL << CCR_BE_Pos) /*!< CCR: WB Mask */
#define CCR_DE_Pos 3U /*!< CCR: DE Position */
#define CCR_DE_Msk (0x1UL << CCR_BE_Pos) /*!< CCR: DE Mask */
#define CCR_IE_Pos 2U /*!< CCR: IE Position */
#define CCR_IE_Msk (0x1UL << CCR_BE_Pos) /*!< CCR: IE Mask */
#define CCR_MP_Pos 0U /*!< CCR: MP Position */
#define CCR_MP_Msk (0x3UL << CCR_MP_Pos) /*!< CCR: MP Mask */
/**
\brief Consortium definition for accessing mmu index register(MIR,CR<0,15>).
*/
typedef union {
struct {
uint32_t Index: 10; /*!< bit: 0.. 9 TLB index */
uint32_t _reserved: 20; /*!< bit: 10.. 29 Reserved */
uint32_t TF: 1; /*!< bit: 30 TLB fatal error */
uint32_t P: 1; /*!< bit: 31 TLBP instruction */
} b;
uint32_t w;
} MIR_Type;
/* MIR Register Definitions */
#define MIR_P_Pos 31 /*!< PRSR: P(TLBP instruction) Position */
#define MIR_P_Msk (0x1UL << MIR_P_Pos) /*!< PRSR: P(TLBP instruction) Mask */
#define MIR_TF_Pos 30 /*!< PRSR: Tfatal Position */
#define MIR_TF_Msk (0x1UL << MIR_TF_Pos) /*!< PRSR: Tfatal Mask */
#define MIR_Index_Pos 0 /*!< PRSR: Index Position */
#define MIR_Index_Msk (0x3ffUL << MIR_Index_Pos) /*!< PRSR: Index Mask */
/**
\brief Consortium definition for accessing mmu entry of high physical address register(MEL, CR<2,15> and CR<3,15>).
*/
typedef union {
struct {
uint32_t G: 1; /*!< bit: 0 Global enbale bit */
uint32_t V: 1; /*!< bit: 1 TLB mapping valid bit */
uint32_t D: 1; /*!< bit: 2 TLB Page dirty bit */
uint32_t C: 1; /*!< bit: 3 TLB Page cacheable bit */
uint32_t SEC: 1; /*!< bit: 4 TLB Page security bit */
uint32_t SO: 1; /*!< bit: 2 Strong order enable bit */
uint32_t B: 1; /*!< bit: 2 TLB Page bufferable bit */
uint32_t _reserved: 5; /*!< bit: 7.. 11 Reserved */
uint32_t PFN: 20; /*!< bit: 12.. 31 Physical frame number */
} b;
uint32_t w;
} MEL_Type;
/* MEL Register Definitions */
#define MEL_PFN_Pos 12 /*!< MEL: PFN Position */
#define MEL_PFN_Msk (0xFFFFFUL << MEL_PFN_Pos) /*!< MEL: PFN Mask */
#define MEL_B_Pos 6 /*!< MEL: B Position */
#define MEL_B_Msk (0x1UL << MEL_B_Pos) /*!< MEL: B Mask */
#define MEL_SO_Pos 5 /*!< MEL: SO Position */
#define MEL_SO_Msk (0x1UL << MEL_SO_Pos) /*!< MEL: SO Mask */
#define MEL_SEC_Pos 4 /*!< MEL: SEC Position */
#define MEL_SEC_Msk (0x1UL << MEL_SEC_Pos) /*!< MEL: SEC Mask */
#define MEL_C_Pos 3 /*!< MEL: C Position */
#define MEL_C_Msk (0x1UL << MEL_C_Pos) /*!< MEL: C Mask */
#define MEL_D_Pos 2 /*!< MEL: D Position */
#define MEL_D_Msk (0x1UL << MIR_D_Pos) /*!< MEL: D Mask */
#define MEL_V_Pos 1 /*!< MEL: V Position */
#define MEL_V_Msk (0x1UL << MIR_V_Pos) /*!< MEL: V Mask */
#define MEL_G_Pos 0 /*!< MEL: G Position */
#define MEL_G_Msk (0x1UL << MIR_G_Pos) /*!< MEL: G Mask */
/**
\brief Consortium definition for accessing mmu entry of high physical address register(MEH, CR<4,15>).
*/
typedef union {
struct {
uint32_t ASID :8; /*!< bit: 0.. 7 ASID */
uint32_t _reserved :4; /*!< bit: 7.. 10 Reserved */
uint32_t VPN :20; /*!< bit: 11.. 31 Virtual page number */
} b;
uint32_t w;
} MEH_Type;
/* MEH Register Definitions */
#define MEH_VPN_Pos 12 /*!< MEH: VPN Position */
#define MEH_VPN_Msk (0xFFFFFUL << MEH_VPN_Pos) /*!< MEH: VPN Mask */
#define MEH_ASID_Pos 0 /*!< MEH: ASID Position */
#define MEH_ASID_Msk (0xFFUL << MEH_ASID_Pos) /*!< MEH: ASID Mask */
/**
\brief Consortium definition for accessing mmu entry of high physical address register(MPR, CR<6,15>).
*/
typedef union {
struct {
uint32_t _reserved0: 13; /*!< bit: 0.. 12 Reserved */
uint32_t page_mask: 12; /*!< bit: 13.. 24 Page mask */
uint32_t _reserved1: 7; /*!< bit: 25.. 31 Reserved */
} b;
uint32_t w;
} MPR_Type;
/* MPR Register Definitions */
#define MPR_PAGE_MASK_Pos 13 /*!< MPR: PAGE_MASK Position */
#define MPR_PAGE_MASK_Msk (0xFFFUL << MPR_PAGE_MASK_Pos) /*!< MPR: PAGE_MASK Mask */
/**
\brief Consortium definition for accessing mmu entry of high physical address register(CR<8,15>).
*/
typedef union {
struct {
uint32_t ASID: 8; /*!< bit: 0.. 7 ASID */
uint32_t _reserved: 17; /*!< bit: 8.. 24 Reserved */
uint32_t TLBINV_INDEX: 1; /*!< bit: 25 TLBINV_INDEX */
uint32_t TLBINV_ALL: 1; /*!< bit: 26 TLBINV_ALL */
uint32_t TLBINV: 1; /*!< bit: 27 TLBINV */
uint32_t TLBWR: 1; /*!< bit: 28 TLBWR */
uint32_t TLBWI: 1; /*!< bit: 29 TLBWI */
uint32_t TLBR: 1; /*!< bit: 30 TLBR */
uint32_t TLBP: 1; /*!< bit: 31 TLBP */
} b;
uint32_t w;
} MCIR_Type;
/* MCIR Register Definitions */
#define MCIR_TLBP_Pos 31 /*!< MCIR: TLBP Position */
#define MCIR_TLBP_Msk (0x1UL << MCIR_TLBP_Pos) /*!< MCIR: TLBP Mask */
#define MCIR_TLBR_Pos 30 /*!< MCIR: TLBR Position */
#define MCIR_TLBR_Msk (0x1UL << MCIR_TLBR_Pos) /*!< MCIR: TLBR Mask */
#define MCIR_TLBWI_Pos 29 /*!< MCIR: TLBWI Position */
#define MCIR_TLBWI_Msk (0x1UL << MCIR_TLBWI_Pos) /*!< MCIR: TLBWI Mask */
#define MCIR_TLBWR_Pos 28 /*!< MCIR: TLBWR Position */
#define MCIR_TLBWR_Msk (0x1UL << MCIR_TLBWR_Pos) /*!< MCIR: TLBWR Mask */
#define MCIR_TLBINV_Pos 27 /*!< MCIR: TLBINV Position */
#define MCIR_TLBINV_Msk (0x1UL << MCIR_TLBINV_Pos) /*!< MCIR: TLBINV Mask */
#define MCIR_TLBINV_ALL_Pos 26 /*!< MCIR: TLBINV_ALL Position */
#define MCIR_TLBINV_ALL_Msk (0x1UL << MCIR_TLBINV_ALL_Pos) /*!< MCIR: TLBINV_ALL Mask */
#define MCIR_TLBINV_INDEX_Pos 25 /*!< MCIR: TLBINV_INDEX Position */
#define MCIR_TLBINV_INDEX_Msk (0x1UL << MCIR_TLBINV_INDEX_Pos) /*!< MCIR: TLBINV_INDEX Mask */
#define MCIR_ASID_Pos 0 /*!< MCIR: ASID Position */
#define MCIR_ASID_Msk (0xFFUL << MCIR_ASID_Pos) /*!< MCIR: ASID Mask */
/*@} end of group CSI_CORE */
/**
\ingroup CSI_core_register
\defgroup CSI_CACHE
\brief Type definitions for the cache Registers
@{
*/
/**
\brief Consortium definition for accessing protection area selection register(CFR,CR<17,0>).
*/
typedef union {
struct {
uint32_t CACHE_SEL: 2; /*!< bit: 0..1 Instruction and data cache selection */
uint32_t _reserved0: 2; /*!< bit: 2..3 Reserved */
uint32_t INV: 1; /*!< bit: 4 Invalid data in cache */
uint32_t CLR: 1; /*!< bit: 5 Clear the dirty tlb table */
uint32_t OMS: 1; /*!< bit: 6 Cache invalid and clear operation mode (one line or all line)*/
uint32_t ITS: 1; /*!< bit: 7 Cache invalid and clear operation mode (CIR used as virtual index or SET/WAY/LEVE index)*/
uint32_t _reserved1: 8; /*!< bit: 8..15 Reserved */
uint32_t BHT_INV: 1; /*!< bit: 16 Invalid data in branch history table */
uint32_t _reserved2: 14; /*!< bit: 17..30 Reserved */
uint32_t LICF: 1; /*!< bit: 31 Failure of clearing or invalid cache line */
} b; /*!< Structure Access by bit */
uint32_t w; /*!< Type Access by whole register */
} CFR_Type;
#define CFR_LICF_Pos 31U /*!< CFR: LICF Position */
#define CFR_LICF_Msk (0x1UL << CFR_LICF_Pos) /*!< CFR: LICF Mask */
#define CFR_BHT_INV_Pos 16U /*!< CFR: BHT Position */
#define CFR_BHT_INV_Msk (0x1UL << CFR_BHT_INV_Pos) /*!< CFR: BHT Mask */
#define CFR_ITS_Pos 7U /*!< CFR: ITS Position */
#define CFR_ITS_Msk (0x1UL << CFR_ITS_Pos) /*!< CFR: ITS Mask */
#define CFR_OMS_Pos 6U /*!< CFR: OMS Position */
#define CFR_OMS_Msk (0x1UL << CFR_OMS_Pos) /*!< CFR: OMS Mask */
#define CFR_CLR_Pos 5U /*!< CFR: CLR Position */
#define CFR_CLR_Msk (0x1UL << CFR_CLR_Pos) /*!< CFR: CLR Mask */
#define CFR_INV_Pos 4U /*!< CFR: INV Position */
#define CFR_INV_Msk (0x1UL << CFR_INV_Pos) /*!< CFR: INV Mask */
#define CFR_CACHE_SEL_Pos 0 /*!< CFR: CACHE_SEL Position */
#define CFR_CACHE_SEL_Msk (0x3UL << CFR_CACHE_SEL_Pos) /*!< CFR: CACHE_SEL Masok */
/* CFR Register Definitions */
/*@} end of group CSI_CACHE */
/**
\ingroup CSI_core_register
\defgroup CSI_CACHE
\brief Type definitions for the cache Registers
@{
*/
#define SSEG0_BASE_ADDR 0x80000000
#define CACHE_RANGE_MAX_SIZE 0x80000
#define INS_CACHE (1 << 0)
#define DATA_CACHE (1 << 1)
#define CACHE_INV (1 << 4)
#define CACHE_CLR (1 << 5)
#define CACHE_OMS (1 << 6)
#define CACHE_ITS (1 << 7)
#define CACHE_LICF (1 << 31)
#define L1_CACHE_SHIFT 4 /* 16 Bytes */
#define L1_CACHE_BYTES (1 << L1_CACHE_SHIFT)
/**
\brief Mask and shift a bit field value for use in a register bit range.
\param[in] field Name of the register bit field.
\param[in] value Value of the bit field.
\return Masked and shifted value.
*/
#define _VAL2FLD(field, value) ((value << field ## _Pos) & field ## _Msk)
/**
\brief Mask and shift a register value to extract a bit filed value.
\param[in] field Name of the register bit field.
\param[in] value Value of register.
\return Masked and shifted bit field value.
*/
#define _FLD2VAL(field, value) ((value & field ## _Msk) >> field ## _Pos)
/*@} end of group CSI_core_bitfield */
/*******************************************************************************
* Hardware Abstraction Layer
Core Function Interface contains:
- Core VIC Functions
- Core CORET Functions
- Core Register Access Functions
******************************************************************************/
/* The following MACROS handle generation of the register offset and byte masks */
#define _BIT_SHIFT(IRQn) ( ((((uint32_t)(int32_t)(IRQn)) ) & 0x03UL) * 8UL)
#define _IP_IDX(IRQn) ( (((uint32_t)(int32_t)(IRQn)) >> 2UL) )
/* ########################## Cache functions #################################### */
/**
\ingroup CSI_Core_FunctionInterface
\defgroup CSI_Core_CacheFunctions Cache Functions
\brief Functions that configure Instruction and Data cache.
@{
*/
/**
\brief Enable I-Cache
\details Turns on I-Cache
*/
__STATIC_INLINE void csi_icache_enable (void)
{
__set_CCR(__get_CCR() | 0x00000004);
}
/**
\brief Disable I-Cache
\details Turns off I-Cache
*/
__STATIC_INLINE void csi_icache_disable (void)
{
__set_CCR(__get_CCR() & 0xFFFFFFFB);
}
/**
\brief Invalidate I-Cache
\details Invalidates I-Cache
*/
__STATIC_INLINE void csi_icache_invalid (void)
{
__set_CFR(0x11);
__set_CFR(INS_CACHE | CACHE_INV);
}
/**
\brief Enable D-Cache
\details Turns on D-Cache
\note I-Cache also turns on.
*/
__STATIC_INLINE void csi_dcache_enable (void)
{
__set_CCR(__get_CCR() | 0x00000008);
}
/**
\brief Disable D-Cache
\details Turns off D-Cache
\note I-Cache also turns off.
*/
__STATIC_INLINE void csi_dcache_disable (void)
{
__set_CCR(__get_CCR() & 0xFFFFFFF7);
}
/**
\brief Invalidate D-Cache
\details Invalidates D-Cache
\note I-Cache also invalid
*/
__STATIC_INLINE void csi_dcache_invalid (void)
{
__set_CFR(DATA_CACHE | CACHE_INV);
}
/**
\brief Clean D-Cache
\details Cleans D-Cache
\note I-Cache also cleans
*/
__STATIC_INLINE void csi_dcache_clean (void)
{
__set_CFR(DATA_CACHE | CACHE_CLR);
}
/**
\brief Clean & Invalidate D-Cache
\details Cleans and Invalidates D-Cache
\note I-Cache also flush.
*/
__STATIC_INLINE void csi_dcache_clean_invalid (void)
{
__set_CFR(DATA_CACHE | CACHE_CLR | CACHE_INV);
}
__STATIC_INLINE void set_cache_range (uint32_t start, uint32_t end, uint32_t value)
{
if (!(start & SSEG0_BASE_ADDR) || (end - start) &~(CACHE_RANGE_MAX_SIZE - 1)) {
__set_CFR(value);
}
if (value & INS_CACHE) {
csi_icache_disable();
}
uint32_t i;
for (i = start; i < end; i += L1_CACHE_BYTES) {
__set_CIR(i);
__set_CFR(CACHE_OMS | value);
}
if (end & (L1_CACHE_BYTES-1)) {
__set_CIR(end);
__set_CFR(CACHE_OMS | value);
}
if (value & INS_CACHE) {
csi_icache_enable();
}
}
/**
\brief D-Cache Invalidate by address
\details Invalidates D-Cache for the given address
\param[in] addr address (aligned to 16-byte boundary)
\param[in] dsize size of memory block (in number of bytes)
*/
__STATIC_INLINE void csi_dcache_invalid_range (uint32_t *addr, int32_t dsize)
{
set_cache_range((uint32_t)addr, (uint32_t)addr + dsize, (DATA_CACHE | CACHE_INV));
}
/**
\brief D-Cache Clean by address
\details Cleans D-Cache for the given address
\param[in] addr address (aligned to 16-byte boundary)
\param[in] dsize size of memory block (in number of bytes)
*/
__STATIC_INLINE void csi_dcache_clean_range (uint32_t *addr, int32_t dsize)
{
set_cache_range((uint32_t)addr, (uint32_t)addr + dsize, (DATA_CACHE | CACHE_CLR));
}
/**
\brief D-Cache Clean and Invalidate by address
\details Cleans and invalidates D_Cache for the given address
\param[in] addr address (aligned to 16-byte boundary)
\param[in] dsize size of memory block (in number of bytes)
*/
__STATIC_INLINE void csi_dcache_clean_invalid_range (uint32_t *addr, int32_t dsize)
{
set_cache_range((uint32_t)addr, (uint32_t)addr + dsize, (DATA_CACHE | CACHE_CLR | CACHE_INV));
}
/*@} end of CSI_Core_CacheFunctions */
/* ########################## MMU functions #################################### */
/**
\ingroup CSI_Core_FunctionInterface
\defgroup CSI_Core_MMUFunctions MMU Functions
\brief Functions that configure MMU.
@{
*/
typedef struct {
uint32_t global: 1; /* tlb page global access. */
uint32_t valid: 1; /* tlb page valid */
uint32_t writeable: 1; /* tlb page writeable */
uint32_t cacheable: 1; /* tlb page cacheable*/
uint32_t is_secure: 1; /* tlb page security access */
uint32_t strong_order: 1; /* the sequence of accessing data on tlb page is corresponding to the program flow? */
uint32_t bufferable: 1; /* tlb page bufferable */
} page_attr_t;
typedef enum {
PAGE_SIZE_4KB = 0x000,
PAGE_SIZE_16KB = 0x003,
PAGE_SIZE_64KB = 0x00F,
PAGE_SIZE_256KB = 0x03F,
PAGE_SIZE_1MB = 0x0FF,
PAGE_SIZE_4MB = 0x3FF,
PAGE_SIZE_16MB = 0xFFF
} page_size_e;
/**
\brief enable mmu
\details
*/
__STATIC_INLINE void csi_mmu_enable(void)
{
__set_CCR(__get_CCR() | (1u << CCR_MP_Pos));
}
/**
\brief disable mmu
\details
*/
__STATIC_INLINE void csi_mmu_disable(void)
{
__set_CCR(__get_CCR() & (~(1u << CCR_MP_Pos)));
}
/**
\brief create page with feature.
\details
\param [in] vaddr virtual address.
\param [in] paddr physical address.
\param [in] asid address sapce id (default: 0).
\param [in] attr \ref page_attr_t. tlb page attribute.
*/
__STATIC_INLINE void csi_mmu_set_tlb(uint32_t vaddr, uint32_t paddr, uint32_t asid, page_attr_t attr)
{
MPR_Type pgmask;
MEH_Type meh;
MEL_Type mel;
uint32_t vaddr_bit;
uint32_t page_feature = 0;
page_feature |= attr.global << MEL_G_Pos | attr.valid << MEL_V_Pos |
attr.writeable << MEL_D_Pos | attr.cacheable << MEL_C_Pos |
attr.is_secure << MEL_SEC_Pos | attr.strong_order << MEL_SO_Pos |
attr.bufferable << MEL_B_Pos;
pgmask.w = __get_MPR();
vaddr_bit = 44 - __FF0(~((uint32_t)pgmask.b.page_mask));
meh.b.ASID = (uint8_t)asid;
meh.b.VPN = (vaddr & ((~pgmask.w | 0xFE000000) & 0xFFFFE000)) >> MEH_VPN_Pos;
__set_MEH(meh.w);
__set_MCIR(1u << MCIR_TLBP_Pos);
mel.w = ((paddr & ~(pgmask.b.page_mask << 12)) | page_feature);
if (vaddr & (1 << vaddr_bit)) {
__set_MEL1(mel.w);
}
else {
__set_MEL0(mel.w);
}
if (__get_MIR() & (1 << MIR_P_Pos)) {
__set_MCIR(1u << MCIR_TLBWR_Pos);
} else {
__set_MCIR(1u << MCIR_TLBWI_Pos);
}
}
/**
\brief enble mmu
\details
\param [in] size tlb page size.
*/
__STATIC_INLINE void csi_mmu_set_pagesize(page_size_e size)
{
MPR_Type pgmask;
pgmask.b.page_mask = size;
__set_MPR(pgmask.w);
}
/**
\brief read MEH, MEL0, MEL1 by tlb index.
\details
\param [in] index tlb index(0, 1, 2, ...)
\param [out] meh pointer to variable for retrieving MEH.
\param [out] mel0 pointer to variable for retrieving MEL0.
\param [out] mel1 pointer to variable for retrieving MEL1.
*/
__STATIC_INLINE void csi_mmu_read_by_index(uint32_t index, uint32_t *meh, uint32_t *mel0, uint32_t *mel1)
{
MIR_Type mir;
if (meh == NULL || mel0 == NULL || mel1 == NULL) {
return;
}
mir.b.Index = index;
__set_MIR(mir.w);
__set_MCIR(1u << MCIR_TLBR_Pos);
*meh = __get_MEH();
*mel0 = __get_MEL0();
*mel1 = __get_MEL1();
}
/**
\brief flush all mmu tlb.
\details
*/
__STATIC_INLINE void csi_mmu_invalid_tlb_all(void)
{
__set_MCIR(1u << MCIR_TLBINV_ALL_Pos);
}
/**
\brief flush mmu tlb by index.
\details
*/
__STATIC_INLINE void csi_mmu_invalid_tlb_by_index(uint32_t index)
{
MIR_Type mir;
mir.b.Index = index;
__set_MIR(mir.w);
__set_MCIR(1u << MCIR_TLBINV_INDEX_Pos);
}
/**
\brief flush mmu tlb by virtual address.
\details
*/
__STATIC_INLINE void csi_mmu_invalid_tlb_by_vaddr(uint32_t vaddr, uint32_t asid)
{
__set_MEH(vaddr | (asid & MEH_ASID_Msk));
__set_MCIR(1u << MCIR_TLBP_Pos);
if (__get_MIR() & (1 << MIR_P_Pos)) {
return;
} else {
__set_MCIR(1u << MCIR_TLBINV_INDEX_Pos);
}
}
/*@} end of CSI_Core_MMUFunctions */
/* ################################## IRQ Functions ############################################ */
/**
\brief Save the Irq context
\details save the psr result before disable irq.
\param [in] irq_num External interrupt number. Value cannot be negative.
*/
__STATIC_INLINE uint32_t csi_irq_save(void)
{
uint32_t result;
result = __get_PSR();
__disable_irq();
return(result);
}
/**
\brief Restore the Irq context
\details restore saved primask state.
\param [in] irq_state psr irq state.
*/
__STATIC_INLINE void csi_irq_restore(uint32_t irq_state)
{
__set_PSR(irq_state);
}
/*@} end of IRQ Functions */
#ifdef __cplusplus
}
#endif
#endif /* __CORE_CK807_H_DEPENDANT */
#endif /* __CSI_GENERIC */

854
lib/sec_library/include/core/core_ck810.h Normal file
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@@ -0,0 +1,854 @@
/*
* Copyright (C) 2017-2019 Alibaba Group Holding Limited
*/
/******************************************************************************
* @file core_ck810.h
* @brief CSI CK810 Core Peripheral Access Layer Header File
* @version V1.0
* @date 26. Jan 2018
******************************************************************************/
#ifndef __CORE_CK810_H_GENERIC
#define __CORE_CK810_H_GENERIC
#include <stdint.h>
#ifdef __cplusplus
extern "C" {
#endif
/*******************************************************************************
* CSI definitions
******************************************************************************/
/**
\ingroup CK810
@{
*/
/* CSI CK810 definitions */
#define __CK810_CSI_VERSION_MAIN (0x04U) /*!< [31:16] CSI HAL main version */
#define __CK810_CSI_VERSION_SUB (0x1EU) /*!< [15:0] CSI HAL sub version */
#define __CK810_CSI_VERSION ((__CK810_CSI_VERSION_MAIN << 16U) | \
__CK810_CSI_VERSION_SUB ) /*!< CSI HAL version number */
#ifndef __CK810
#define __CK810 (0x0aU) /*!< CK810 Core */
#endif
/** __FPU_USED indicates whether an FPU is used or not.
*/
#define __FPU_USED 1U
#if defined ( __GNUC__ )
#if defined (__VFP_FP__) && !defined(__SOFTFP__)
#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
#endif
#endif
#ifdef __cplusplus
}
#endif
#endif /* __CORE_CK810_H_GENERIC */
#ifndef __CSI_GENERIC
#ifndef __CORE_CK810_H_DEPENDANT
#define __CORE_CK810_H_DEPENDANT
#ifdef __cplusplus
extern "C" {
#endif
/* check device defines and use defaults */
#ifndef __CK810_REV
#define __CK810_REV 0x0000U
#endif
#ifndef __GSR_GCR_PRESENT
#define __GSR_GCR_PRESENT 0U
#endif
#ifndef __ICACHE_PRESENT
#define __ICACHE_PRESENT 1U
#endif
#ifndef __DCACHE_PRESENT
#define __DCACHE_PRESENT 1U
#endif
#include <csi_gcc.h>
/* IO definitions (access restrictions to peripheral registers) */
/**
\defgroup CSI_glob_defs CSI Global Defines
<strong>IO Type Qualifiers</strong> are used
\li to specify the access to peripheral variables.
\li for automatic generation of peripheral register debug information.
*/
#ifdef __cplusplus
#define __I volatile /*!< Defines 'read only' permissions */
#else
#define __I volatile const /*!< Defines 'read only' permissions */
#endif
#define __O volatile /*!< Defines 'write only' permissions */
#define __IO volatile /*!< Defines 'read / write' permissions */
/* following defines should be used for structure members */
#define __IM volatile const /*! Defines 'read only' structure member permissions */
#define __OM volatile /*! Defines 'write only' structure member permissions */
#define __IOM volatile /*! Defines 'read / write' structure member permissions */
/*@} end of group CK810 */
/*******************************************************************************
* Register Abstraction
Core Register contain:
- Core Register
******************************************************************************/
/**
\defgroup CSI_core_register Defines and Type Definitions
\brief Type definitions and defines for CK810 processor based devices.
*/
/**
\ingroup CSI_core_register
\defgroup CSI_CORE Status and Control Registers
\brief Core Register type definitions.
@{
*/
/**
\brief Access Processor Status Register(PSR)struct definition.
*/
typedef union {
struct {
uint32_t C: 1; /*!< bit: 0 Conditional code/Carry flag */
uint32_t _reserved0: 5; /*!< bit: 2.. 5 Reserved */
uint32_t IE: 1; /*!< bit: 6 Interrupt effective control bit */
uint32_t IC: 1; /*!< bit: 7 Interrupt control bit */
uint32_t EE: 1; /*!< bit: 8 Abnormally effective control bit */
uint32_t MM: 1; /*!< bit: 9 Unsymmetrical masking bit */
uint32_t _reserved1: 6; /*!< bit: 10..15 Reserved */
uint32_t VEC: 8; /*!< bit: 16..23 Abnormal event vector value */
uint32_t _reserved2: 5; /*!< bit: 24..28 Reserved */
uint32_t SP: 1; /*!< bit: 29 Secure pedning bit */
uint32_t T: 1; /*!< bit: 30 TEE mode bit */
uint32_t S: 1; /*!< bit: 31 Superuser mode set bit */
} b; /*!< Structure Access by bit */
uint32_t w; /*!< Type Access by whole register */
} PSR_Type;
/* PSR Register Definitions */
#define PSR_S_Pos 31U /*!< PSR: S Position */
#define PSR_S_Msk (1UL << PSR_S_Pos) /*!< PSR: S Mask */
#define PSR_VEC_Pos 16U /*!< PSR: VEC Position */
#define PSR_VEC_Msk (0x7FUL << PSR_VEC_Pos) /*!< PSR: VEC Mask */
#define PSR_MM_Pos 9U /*!< PSR: MM Position */
#define PSR_MM_Msk (1UL << PSR_MM_Pos) /*!< PSR: MM Mask */
#define PSR_EE_Pos 8U /*!< PSR: EE Position */
#define PSR_EE_Msk (1UL << PSR_EE_Pos) /*!< PSR: EE Mask */
#define PSR_IC_Pos 7U /*!< PSR: IC Position */
#define PSR_IC_Msk (1UL << PSR_IC_Pos) /*!< PSR: IC Mask */
#define PSR_IE_Pos 6U /*!< PSR: IE Position */
#define PSR_IE_Msk (1UL << PSR_IE_Pos) /*!< PSR: IE Mask */
#define PSR_C_Pos 0U /*!< PSR: C Position */
#define PSR_C_Msk (1UL << PSR_C_Pos) /*!< PSR: C Mask */
/**
\brief Consortium definition for accessing Cache Configuration Registers(CCR, CR<18, 0>).
*/
typedef union {
struct {
uint32_t MP: 2; /*!< bit: 0.. 1 memory protection settings */
uint32_t IE: 1; /*!< bit: 2 Instruction cache enable */
uint32_t DE: 1; /*!< bit: 3 Data cache enable */
uint32_t WB: 1; /*!< bit: 4 Cache write back */
uint32_t RS: 1; /*!< bit: 5 Address return stack settings */
uint32_t Z: 1; /*!< bit: 6 Allow predictive jump bit */
uint32_t BE: 1; /*!< bit: 7 Endian mode */
uint32_t SCK: 3; /*!< bit: 8..10 the clock ratio of the system and the processor */
uint32_t _reserved0: 1; /*!< bit: 11 Reserved */
uint32_t WA: 1; /*!< bit: 12 Write allocate enable */
uint32_t E_V2: 1; /*!< bit: 13 V2 Endian mode */
uint32_t BSTE: 1; /*!< bit: 14 Burst transmit enable */
uint32_t IPE: 1; /*!< bit: 15 Indirect predict enable */
uint32_t _reserved1: 16; /*!< bit: 16..31 Reserved */
} b; /*!< Structure Access by bit */
uint32_t w; /*!< Type Access by whole register */
} CCR_Type;
/* CCR Register Definitions */
#define CCR_IPE_Pos 15u /*!< CCR: IPE Position */
#define CCR_IPE_Msk (0x1UL << CCR_IPE_Pos) /*!< CCR: IPE Mask */
#define CCR_BSTE_Pos 14u /*!< CCR: BSTE Position */
#define CCR_BSTE_Msk (0x1UL << CCR_BSTE_Pos) /*!< CCR: BSTE Mask */
#define CCR_E_V2_Pos 13U /*!< CCR: E_V2 Position */
#define CCR_E_V2_Msk (0x1UL << CCR_E_V2_Pos) /*!< CCR: E_V2 Mask */
#define CCR_WA_Pos 12u /*!< CCR: WA Position */
#define CCR_WA_Msk (0x1UL << CCR_WA_Pos) /*!< CCR: WA Mask */
#define CCR_SCK_Pos 8U /*!< CCR: SCK Position */
#define CCR_SCK_Msk (0x3UL << CCR_SCK_Pos) /*!< CCR: SCK Mask */
#define CCR_BE_Pos 7U /*!< CCR: BE Position */
#define CCR_BE_Msk (0x1UL << CCR_BE_Pos) /*!< CCR: BE Mask */
#define CCR_Z_Pos 6U /*!< CCR: Z Position */
#define CCR_Z_Msk (0x1UL << CCR_BE_Pos) /*!< CCR: Z Mask */
#define CCR_RS_Pos 5U /*!< CCR: RS Position */
#define CCR_RS_Msk (0x1UL << CCR_BE_Pos) /*!< CCR: RS Mask */
#define CCR_WB_Pos 4U /*!< CCR: WB Position */
#define CCR_WB_Msk (0x1UL << CCR_BE_Pos) /*!< CCR: WB Mask */
#define CCR_DE_Pos 3U /*!< CCR: DE Position */
#define CCR_DE_Msk (0x1UL << CCR_BE_Pos) /*!< CCR: DE Mask */
#define CCR_IE_Pos 2U /*!< CCR: IE Position */
#define CCR_IE_Msk (0x1UL << CCR_BE_Pos) /*!< CCR: IE Mask */
#define CCR_MP_Pos 0U /*!< CCR: MP Position */
#define CCR_MP_Msk (0x3UL << CCR_MP_Pos) /*!< CCR: MP Mask */
/**
\brief Consortium definition for accessing mmu index register(MIR,CR<0,15>).
*/
typedef union {
struct {
uint32_t Index: 10; /*!< bit: 0.. 9 TLB index */
uint32_t _reserved: 20; /*!< bit: 10.. 29 Reserved */
uint32_t TF: 1; /*!< bit: 30 TLB fatal error */
uint32_t P: 1; /*!< bit: 31 TLBP instruction */
} b;
uint32_t w;
} MIR_Type;
/* MIR Register Definitions */
#define MIR_P_Pos 31 /*!< PRSR: P(TLBP instruction) Position */
#define MIR_P_Msk (0x1UL << MIR_P_Pos) /*!< PRSR: P(TLBP instruction) Mask */
#define MIR_TF_Pos 30 /*!< PRSR: Tfatal Position */
#define MIR_TF_Msk (0x1UL << MIR_TF_Pos) /*!< PRSR: Tfatal Mask */
#define MIR_Index_Pos 0 /*!< PRSR: Index Position */
#define MIR_Index_Msk (0x3ffUL << MIR_Index_Pos) /*!< PRSR: Index Mask */
/**
\brief Consortium definition for accessing mmu entry of high physical address register(MEL, CR<2,15> and CR<3,15>).
*/
typedef union {
struct {
uint32_t G: 1; /*!< bit: 0 Global enbale bit */
uint32_t V: 1; /*!< bit: 1 TLB mapping valid bit */
uint32_t D: 1; /*!< bit: 2 TLB Page dirty bit */
uint32_t C: 1; /*!< bit: 3 TLB Page cacheable bit */
uint32_t SEC: 1; /*!< bit: 4 TLB Page security bit */
uint32_t SO: 1; /*!< bit: 2 Strong order enable bit */
uint32_t B: 1; /*!< bit: 2 TLB Page bufferable bit */
uint32_t _reserved: 5; /*!< bit: 7.. 11 Reserved */
uint32_t PFN: 20; /*!< bit: 12.. 31 Physical frame number */
} b;
uint32_t w;
} MEL_Type;
/* MEL Register Definitions */
#define MEL_PFN_Pos 12 /*!< MEL: PFN Position */
#define MEL_PFN_Msk (0xFFFFFUL << MEL_PFN_Pos) /*!< MEL: PFN Mask */
#define MEL_B_Pos 6 /*!< MEL: B Position */
#define MEL_B_Msk (0x1UL << MEL_B_Pos) /*!< MEL: B Mask */
#define MEL_SO_Pos 5 /*!< MEL: SO Position */
#define MEL_SO_Msk (0x1UL << MEL_SO_Pos) /*!< MEL: SO Mask */
#define MEL_SEC_Pos 4 /*!< MEL: SEC Position */
#define MEL_SEC_Msk (0x1UL << MEL_SEC_Pos) /*!< MEL: SEC Mask */
#define MEL_C_Pos 3 /*!< MEL: C Position */
#define MEL_C_Msk (0x1UL << MEL_C_Pos) /*!< MEL: C Mask */
#define MEL_D_Pos 2 /*!< MEL: D Position */
#define MEL_D_Msk (0x1UL << MIR_D_Pos) /*!< MEL: D Mask */
#define MEL_V_Pos 1 /*!< MEL: V Position */
#define MEL_V_Msk (0x1UL << MIR_V_Pos) /*!< MEL: V Mask */
#define MEL_G_Pos 0 /*!< MEL: G Position */
#define MEL_G_Msk (0x1UL << MIR_G_Pos) /*!< MEL: G Mask */
/**
\brief Consortium definition for accessing mmu entry of high physical address register(MEH, CR<4,15>).
*/
typedef union {
struct {
uint32_t ASID :8; /*!< bit: 0.. 7 ASID */
uint32_t _reserved :4; /*!< bit: 7.. 10 Reserved */
uint32_t VPN :20; /*!< bit: 11.. 31 Virtual page number */
} b;
uint32_t w;
} MEH_Type;
/* MEH Register Definitions */
#define MEH_VPN_Pos 12 /*!< MEH: VPN Position */
#define MEH_VPN_Msk (0xFFFFFUL << MEH_VPN_Pos) /*!< MEH: VPN Mask */
#define MEH_ASID_Pos 0 /*!< MEH: ASID Position */
#define MEH_ASID_Msk (0xFFUL << MEH_ASID_Pos) /*!< MEH: ASID Mask */
/**
\brief Consortium definition for accessing mmu entry of high physical address register(MPR, CR<6,15>).
*/
typedef union {
struct {
uint32_t _reserved0: 13; /*!< bit: 0.. 12 Reserved */
uint32_t page_mask: 12; /*!< bit: 13.. 24 Page mask */
uint32_t _reserved1: 7; /*!< bit: 25.. 31 Reserved */
} b;
uint32_t w;
} MPR_Type;
/* MPR Register Definitions */
#define MPR_PAGE_MASK_Pos 13 /*!< MPR: PAGE_MASK Position */
#define MPR_PAGE_MASK_Msk (0xFFFUL << MPR_PAGE_MASK_Pos) /*!< MPR: PAGE_MASK Mask */
/**
\brief Consortium definition for accessing mmu entry of high physical address register(CR<8,15>).
*/
typedef union {
struct {
uint32_t ASID: 8; /*!< bit: 0.. 7 ASID */
uint32_t _reserved: 17; /*!< bit: 8.. 24 Reserved */
uint32_t TLBINV_INDEX: 1; /*!< bit: 25 TLBINV_INDEX */
uint32_t TLBINV_ALL: 1; /*!< bit: 26 TLBINV_ALL */
uint32_t TLBINV: 1; /*!< bit: 27 TLBINV */
uint32_t TLBWR: 1; /*!< bit: 28 TLBWR */
uint32_t TLBWI: 1; /*!< bit: 29 TLBWI */
uint32_t TLBR: 1; /*!< bit: 30 TLBR */
uint32_t TLBP: 1; /*!< bit: 31 TLBP */
} b;
uint32_t w;
} MCIR_Type;
/* MCIR Register Definitions */
#define MCIR_TLBP_Pos 31 /*!< MCIR: TLBP Position */
#define MCIR_TLBP_Msk (0x1UL << MCIR_TLBP_Pos) /*!< MCIR: TLBP Mask */
#define MCIR_TLBR_Pos 30 /*!< MCIR: TLBR Position */
#define MCIR_TLBR_Msk (0x1UL << MCIR_TLBR_Pos) /*!< MCIR: TLBR Mask */
#define MCIR_TLBWI_Pos 29 /*!< MCIR: TLBWI Position */
#define MCIR_TLBWI_Msk (0x1UL << MCIR_TLBWI_Pos) /*!< MCIR: TLBWI Mask */
#define MCIR_TLBWR_Pos 28 /*!< MCIR: TLBWR Position */
#define MCIR_TLBWR_Msk (0x1UL << MCIR_TLBWR_Pos) /*!< MCIR: TLBWR Mask */
#define MCIR_TLBINV_Pos 27 /*!< MCIR: TLBINV Position */
#define MCIR_TLBINV_Msk (0x1UL << MCIR_TLBINV_Pos) /*!< MCIR: TLBINV Mask */
#define MCIR_TLBINV_ALL_Pos 26 /*!< MCIR: TLBINV_ALL Position */
#define MCIR_TLBINV_ALL_Msk (0x1UL << MCIR_TLBINV_ALL_Pos) /*!< MCIR: TLBINV_ALL Mask */
#define MCIR_TLBINV_INDEX_Pos 25 /*!< MCIR: TLBINV_INDEX Position */
#define MCIR_TLBINV_INDEX_Msk (0x1UL << MCIR_TLBINV_INDEX_Pos) /*!< MCIR: TLBINV_INDEX Mask */
#define MCIR_ASID_Pos 0 /*!< MCIR: ASID Position */
#define MCIR_ASID_Msk (0xFFUL << MCIR_ASID_Pos) /*!< MCIR: ASID Mask */
/*@} end of group CSI_CORE */
/**
\ingroup CSI_core_register
\defgroup CSI_CACHE
\brief Type definitions for the cache Registers
@{
*/
/**
\brief Consortium definition for accessing protection area selection register(CFR,CR<17,0>).
*/
typedef union {
struct {
uint32_t CACHE_SEL: 2; /*!< bit: 0..1 Instruction and data cache selection */
uint32_t _reserved0: 2; /*!< bit: 2..3 Reserved */
uint32_t INV: 1; /*!< bit: 4 Invalid data in cache */
uint32_t CLR: 1; /*!< bit: 5 Clear the dirty tlb table */
uint32_t OMS: 1; /*!< bit: 6 Cache invalid and clear operation mode (one line or all line)*/
uint32_t ITS: 1; /*!< bit: 7 Cache invalid and clear operation mode (CIR used as virtual index or SET/WAY/LEVE index)*/
uint32_t UNLOCK: 1; /*!< bit: 8 Unclock data cache line. */
uint32_t _reserved1: 7; /*!< bit: 9..15 Reserved */
uint32_t BHT_INV: 1; /*!< bit: 16 Invalid data in branch history table */
uint32_t BTB_INV: 1; /*!< bit: 17 Invalid data in branch table buffer */
uint32_t _reserved2: 13; /*!< bit: 18..30 Reserved */
uint32_t LICF: 1; /*!< bit: 31 Failure of clearing or invalid cache line */
} b; /*!< Structure Access by bit */
uint32_t w; /*!< Type Access by whole register */
} CFR_Type;
#define CFR_LICF_Pos 31U /*!< CFR: LICF Position */
#define CFR_LICF_Msk (0x1UL << CFR_LICF_Pos) /*!< CFR: LICF Mask */
#define CFR_BTB_INV_Pos 17U /*!< CFR: BTB Position */
#define CFR_BTB_INV_Msk (0x1UL << CFR_BTB_INV_Pos) /*!< CFR: BTB Mask */
#define CFR_BHT_INV_Pos 16U /*!< CFR: BHT Position */
#define CFR_BHT_INV_Msk (0x1UL << CFR_BHT_INV_Pos) /*!< CFR: BHT Mask */
#define CFR_UNLOCK_Pos 8U /*!< CFR: UNLOCK Position */
#define CFR_UNLOCK_Msk (0x1UL << CFR_UNLOCK_Pos) /*!< CFR: UNLOCK Mask */
#define CFR_ITS_Pos 7U /*!< CFR: ITS Position */
#define CFR_ITS_Msk (0x1UL << CFR_ITS_Pos) /*!< CFR: ITS Mask */
#define CFR_OMS_Pos 6U /*!< CFR: OMS Position */
#define CFR_OMS_Msk (0x1UL << CFR_OMS_Pos) /*!< CFR: OMS Mask */
#define CFR_CLR_Pos 5U /*!< CFR: CLR Position */
#define CFR_CLR_Msk (0x1UL << CFR_CLR_Pos) /*!< CFR: CLR Mask */
#define CFR_INV_Pos 4U /*!< CFR: INV Position */
#define CFR_INV_Msk (0x1UL << CFR_INV_Pos) /*!< CFR: INV Mask */
#define CFR_CACHE_SEL_Pos 0 /*!< CFR: CACHE_SEL Position */
#define CFR_CACHE_SEL_Msk (0x3UL << CFR_CACHE_SEL_Pos) /*!< CFR: CACHE_SEL Masok */
/* CFR Register Definitions */
/*@} end of group CSI_CACHE */
/**
\ingroup CSI_core_register
\defgroup CSI_CACHE
\brief Type definitions for the cache Registers
@{
*/
#define SSEG0_BASE_ADDR 0x80000000
#define CACHE_RANGE_MAX_SIZE 0x80000
#define INS_CACHE (1 << 0)
#define DATA_CACHE (1 << 1)
#define CACHE_INV (1 << 4)
#define CACHE_CLR (1 << 5)
#define CACHE_OMS (1 << 6)
#define CACHE_ITS (1 << 7)
#define CACHE_LICF (1 << 31)
#define L1_CACHE_SHIFT 4 /* 16 Bytes */
#define L1_CACHE_BYTES (1 << L1_CACHE_SHIFT)
/**
\brief Mask and shift a bit field value for use in a register bit range.
\param[in] field Name of the register bit field.
\param[in] value Value of the bit field.
\return Masked and shifted value.
*/
#define _VAL2FLD(field, value) ((value << field ## _Pos) & field ## _Msk)
/**
\brief Mask and shift a register value to extract a bit filed value.
\param[in] field Name of the register bit field.
\param[in] value Value of register.
\return Masked and shifted bit field value.
*/
#define _FLD2VAL(field, value) ((value & field ## _Msk) >> field ## _Pos)
/*@} end of group CSI_core_bitfield */
/*******************************************************************************
* Hardware Abstraction Layer
Core Function Interface contains:
- Core VIC Functions
- Core CORET Functions
- Core Register Access Functions
******************************************************************************/
/* The following MACROS handle generation of the register offset and byte masks */
#define _BIT_SHIFT(IRQn) ( ((((uint32_t)(int32_t)(IRQn)) ) & 0x03UL) * 8UL)
#define _IP_IDX(IRQn) ( (((uint32_t)(int32_t)(IRQn)) >> 2UL) )
/* ########################## Cache functions #################################### */
/**
\ingroup CSI_Core_FunctionInterface
\defgroup CSI_Core_CacheFunctions Cache Functions
\brief Functions that configure Instruction and Data cache.
@{
*/
/**
\brief Enable I-Cache
\details Turns on I-Cache
*/
__STATIC_INLINE void csi_icache_enable (void)
{
__set_CCR(__get_CCR() | 0x00000004);
}
/**
\brief Disable I-Cache
\details Turns off I-Cache
*/
__STATIC_INLINE void csi_icache_disable (void)
{
__set_CCR(__get_CCR() & 0xFFFFFFFB);
}
/**
\brief Invalidate I-Cache
\details Invalidates I-Cache
*/
__STATIC_INLINE void csi_icache_invalid (void)
{
__set_CFR(0x11);
__set_CFR(INS_CACHE | CACHE_INV);
}
/**
\brief Enable D-Cache
\details Turns on D-Cache
\note I-Cache also turns on.
*/
__STATIC_INLINE void csi_dcache_enable (void)
{
__set_CCR(__get_CCR() | 0x00000008);
}
/**
\brief Disable D-Cache
\details Turns off D-Cache
\note I-Cache also turns off.
*/
__STATIC_INLINE void csi_dcache_disable (void)
{
__set_CCR(__get_CCR() & 0xFFFFFFF7);
}
/**
\brief Invalidate D-Cache
\details Invalidates D-Cache
\note I-Cache also invalid
*/
__STATIC_INLINE void csi_dcache_invalid (void)
{
__set_CFR(DATA_CACHE | CACHE_INV);
}
/**
\brief Clean D-Cache
\details Cleans D-Cache
\note I-Cache also cleans
*/
__STATIC_INLINE void csi_dcache_clean (void)
{
__set_CFR(DATA_CACHE | CACHE_CLR);
}
/**
\brief Clean & Invalidate D-Cache
\details Cleans and Invalidates D-Cache
\note I-Cache also flush.
*/
__STATIC_INLINE void csi_dcache_clean_invalid (void)
{
__set_CFR(DATA_CACHE | CACHE_CLR | CACHE_INV);
}
__STATIC_INLINE void set_cache_range (uint32_t start, uint32_t end, uint32_t value)
{
if (!(start & SSEG0_BASE_ADDR) || (end - start) &~(CACHE_RANGE_MAX_SIZE - 1)) {
__set_CFR(value);
}
if (value & INS_CACHE) {
csi_icache_disable();
}
uint32_t i;
for (i = start; i < end; i += L1_CACHE_BYTES) {
__set_CIR(i);
__set_CFR(CACHE_OMS | value);
}
if (end & (L1_CACHE_BYTES-1)) {
__set_CIR(end);
__set_CFR(CACHE_OMS | value);
}
if (value & INS_CACHE) {
csi_icache_enable();
}
}
/**
\brief D-Cache Invalidate by address
\details Invalidates D-Cache for the given address
\param[in] addr address (aligned to 16-byte boundary)
\param[in] dsize size of memory block (in number of bytes)
*/
__STATIC_INLINE void csi_dcache_invalid_range (uint32_t *addr, int32_t dsize)
{
set_cache_range((uint32_t)addr, (uint32_t)addr + dsize, (DATA_CACHE | CACHE_INV));
}
/**
\brief D-Cache Clean by address
\details Cleans D-Cache for the given address
\param[in] addr address (aligned to 16-byte boundary)
\param[in] dsize size of memory block (in number of bytes)
*/
__STATIC_INLINE void csi_dcache_clean_range (uint32_t *addr, int32_t dsize)
{
set_cache_range((uint32_t)addr, (uint32_t)addr + dsize, (DATA_CACHE | CACHE_CLR));
}
/**
\brief D-Cache Clean and Invalidate by address
\details Cleans and invalidates D_Cache for the given address
\param[in] addr address (aligned to 16-byte boundary)
\param[in] dsize size of memory block (in number of bytes)
*/
__STATIC_INLINE void csi_dcache_clean_invalid_range (uint32_t *addr, int32_t dsize)
{
set_cache_range((uint32_t)addr, (uint32_t)addr + dsize, (DATA_CACHE | CACHE_CLR | CACHE_INV));
}
/*@} end of CSI_Core_CacheFunctions */
/* ########################## MMU functions #################################### */
/**
\ingroup CSI_Core_FunctionInterface
\defgroup CSI_Core_MMUFunctions MMU Functions
\brief Functions that configure MMU.
@{
*/
typedef struct {
uint32_t global: 1; /* tlb page global access. */
uint32_t valid: 1; /* tlb page valid */
uint32_t writeable: 1; /* tlb page writeable */
uint32_t cacheable: 1; /* tlb page cacheable*/
uint32_t is_secure: 1; /* tlb page security access */
uint32_t strong_order: 1; /* the sequence of accessing data on tlb page is corresponding to the program flow? */
uint32_t bufferable: 1; /* tlb page bufferable */
} page_attr_t;
typedef enum {
PAGE_SIZE_4KB = 0x000,
PAGE_SIZE_16KB = 0x003,
PAGE_SIZE_64KB = 0x00F,
PAGE_SIZE_256KB = 0x03F,
PAGE_SIZE_1MB = 0x0FF,
PAGE_SIZE_4MB = 0x3FF,
PAGE_SIZE_16MB = 0xFFF
} page_size_e;
/**
\brief enable mmu
\details
*/
__STATIC_INLINE void csi_mmu_enable(void)
{
__set_CCR(__get_CCR() | (1u << CCR_MP_Pos));
}
/**
\brief disable mmu
\details
*/
__STATIC_INLINE void csi_mmu_disable(void)
{
__set_CCR(__get_CCR() & (~(1u << CCR_MP_Pos)));
}
/**
\brief create page with feature.
\details
\param [in] vaddr virtual address.
\param [in] paddr physical address.
\param [in] asid address sapce id (default: 0).
\param [in] attr \ref page_attr_t. tlb page attribute.
*/
__STATIC_INLINE void csi_mmu_set_tlb(uint32_t vaddr, uint32_t paddr, uint32_t asid, page_attr_t attr)
{
MPR_Type pgmask;
MEH_Type meh;
MEL_Type mel;
uint32_t vaddr_bit;
uint32_t page_feature = 0;
page_feature |= attr.global << MEL_G_Pos | attr.valid << MEL_V_Pos |
attr.writeable << MEL_D_Pos | attr.cacheable << MEL_C_Pos |
attr.is_secure << MEL_SEC_Pos | attr.strong_order << MEL_SO_Pos |
attr.bufferable << MEL_B_Pos;
pgmask.w = __get_MPR();
vaddr_bit = 44 - __FF0(~((uint32_t)pgmask.b.page_mask));
meh.b.ASID = (uint8_t)asid;
meh.b.VPN = (vaddr & ((~pgmask.w | 0xFE000000) & 0xFFFFE000)) >> MEH_VPN_Pos;
__set_MEH(meh.w);
__set_MCIR(1u << MCIR_TLBP_Pos);
mel.w = ((paddr & ~(pgmask.b.page_mask << 12)) | page_feature);
if (vaddr & (1 << vaddr_bit)) {
__set_MEL1(mel.w);
}
else {
__set_MEL0(mel.w);
}
if (__get_MIR() & (1 << MIR_P_Pos)) {
__set_MCIR(1u << MCIR_TLBWR_Pos);
} else {
__set_MCIR(1u << MCIR_TLBWI_Pos);
}
}
/**
\brief enble mmu
\details
\param [in] size tlb page size.
*/
__STATIC_INLINE void csi_mmu_set_pagesize(page_size_e size)
{
MPR_Type pgmask;
pgmask.b.page_mask = size;
__set_MPR(pgmask.w);
}
/**
\brief read MEH, MEL0, MEL1 by tlb index.
\details
\param [in] index tlb index(0, 1, 2, ...)
\param [out] meh pointer to variable for retrieving MEH.
\param [out] mel0 pointer to variable for retrieving MEL0.
\param [out] mel1 pointer to variable for retrieving MEL1.
*/
__STATIC_INLINE void csi_mmu_read_by_index(uint32_t index, uint32_t *meh, uint32_t *mel0, uint32_t *mel1)
{
MIR_Type mir;
if (meh == NULL || mel0 == NULL || mel1 == NULL) {
return;
}
mir.b.Index = index;
__set_MIR(mir.w);
__set_MCIR(1u << MCIR_TLBR_Pos);
*meh = __get_MEH();
*mel0 = __get_MEL0();
*mel1 = __get_MEL1();
}
/**
\brief flush all mmu tlb.
\details
*/
__STATIC_INLINE void csi_mmu_invalid_tlb_all(void)
{
__set_MCIR(1u << MCIR_TLBINV_ALL_Pos);
}
/**
\brief flush mmu tlb by index.
\details
*/
__STATIC_INLINE void csi_mmu_invalid_tlb_by_index(uint32_t index)
{
MIR_Type mir;
mir.b.Index = index;
__set_MIR(mir.w);
__set_MCIR(1u << MCIR_TLBINV_INDEX_Pos);
}
/**
\brief flush mmu tlb by virtual address.
\details
*/
__STATIC_INLINE void csi_mmu_invalid_tlb_by_vaddr(uint32_t vaddr, uint32_t asid)
{
__set_MEH(vaddr | (asid & MEH_ASID_Msk));
__set_MCIR(1u << MCIR_TLBP_Pos);
if (__get_MIR() & (1 << MIR_P_Pos)) {
return;
} else {
__set_MCIR(1u << MCIR_TLBINV_INDEX_Pos);
}
}
/*@} end of CSI_Core_MMUFunctions */
/* ################################## IRQ Functions ############################################ */
/**
\brief Save the Irq context
\details save the psr result before disable irq.
\param [in] irq_num External interrupt number. Value cannot be negative.
*/
__STATIC_INLINE uint32_t csi_irq_save(void)
{
uint32_t result;
result = __get_PSR();
__disable_irq();
return(result);
}
/**
\brief Restore the Irq context
\details restore saved primask state.
\param [in] irq_state psr irq state.
*/
__STATIC_INLINE void csi_irq_restore(uint32_t irq_state)
{
__set_PSR(irq_state);
}
/*@} end of IRQ Functions */
#ifdef __cplusplus
}
#endif
#endif /* __CORE_CK810_H_DEPENDANT */
#endif /* __CSI_GENERIC */

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@@ -0,0 +1,62 @@
/*
* Copyright (C) 2017-2019 Alibaba Group Holding Limited
*/
/******************************************************************************
* @file csi_core.h
* @brief CSI Core Layer Header File
* @version V1.0
* @date 02. June 2017
******************************************************************************/
#ifndef _CORE_H_
#define _CORE_H_
#include <stdint.h>
#if defined(__CK801__) || defined(__E801__)
#include "core/core_801.h"
#elif defined(__CK802__) || defined(__E802__) || defined(__E802T__) || defined(__S802__) || defined(__S802T__)
#include "core/core_802.h"
#elif defined(__CK804__) || defined(__E804D__) || defined(__E804DT__) || defined(__E804F__) || defined(__E804FT__) || defined (__E804DF__) || defined(__E804DFT__)
#include "core/core_804.h"
#elif defined(__CK803__) || defined(__E803__) || defined(__E803T__) || defined(__S803__) || defined(__S803T__)
#include "core/core_803.h"
#elif defined(__CK805__) || defined(__I805__) || defined(__I805F__)
#include "core/core_805.h"
#elif defined(__CK610__)
#include "core/core_ck610.h"
#elif defined(__CK810__) || defined(__C810__) || defined(__C810T__) || defined(__C810V__) || defined(__C810VT__)
#include "core/core_810.h"
#elif defined(__CK807__) || defined(__C807__) || defined(__C807F__) || defined(__C807FV__) || defined(__R807__)
#include "core/core_807.h"
#elif defined(__riscv) && defined(CONFIG_CSKY_CORETIM)
#include "core/core_rv32_old.h"
#elif defined(__riscv) && (__riscv_xlen == 32)
#include "core/core_rv32.h"
#elif defined(__riscv) && (__riscv_xlen == 64)
#include "core/core_rv64.h"
#endif
#if defined(__riscv) && (__riscv_xlen == 32)
#include "core/csi_rv32_gcc.h"
#elif defined(__riscv) && (__riscv_xlen == 64)
#include "core/csi_rv64_gcc.h"
#elif defined(__csky__)
#include "core/csi_gcc.h"
#endif
#ifdef __arm__
#include "csi_core_cmsis.h"
#endif
#ifdef __cplusplus
extern "C" {
#endif
#ifdef __cplusplus
}
#endif
#endif /* _CORE_H_ */

7
lib/sec_library/include/csi_efuse_api.h
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@@ -1,5 +1,5 @@
/*
* Copyright (C) 2019-2021 Alibaba Group Holding Limited
* Copyright (C) 2019-2020 Alibaba Group Holding Limited
*/
#ifndef __CSI_EFUSE_API_H__
#define __CSI_EFUSE_API_H__
@@ -22,8 +22,7 @@ typedef enum {
} img_encrypt_st_t;
int csi_efuse_api_int(void);
int csi_efuse_api_uninit(void);
void csi_efuse_api_uninit(void);
int csi_efuse_get_secure_boot_st(sboot_st_t *sboot_st);
@@ -53,4 +52,4 @@ int csi_efuse_write_raw(uint32_t addr, const void *data, uint32_t cnt);
}
#endif
#endif /* __CSI_EFUSE_API_H__ */
#endif /* __CSI_EFUSE_API_H__ */

4
lib/sec_library/include/csi_sec_img_verify.h
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@@ -1,5 +1,5 @@
/*
* Copyright (C) 2019-2021 Alibaba Group Holding Limited
* Copyright (C) 2019-2020 Alibaba Group Holding Limited
*/
#ifndef __CSI_SEC_IMG_VERIFY_H__
#define __CSI_SEC_IMG_VERIFY_H__
@@ -28,4 +28,4 @@ int csi_sec_get_lib_version(char ** p_version);
}
#endif
#endif /* __CSI_SEC_IMG_VERIFY_H__ */
#endif /* __CSI_SEC_IMG_VERIFY_H__ */

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@@ -0,0 +1,87 @@
/*
* Copyright (C) 2017-2020 Alibaba Group Holding Limited
*/
/******************************************************************************
* @file drv/dev_tag.h
* @brief Header File for DEV TAG Driver
* @version V1.0
* @date 31. March 2020
* @model common
******************************************************************************/
#ifndef _DRV_DEV_TAG_H_
#define _DRV_DEV_TAG_H_
#include <stdint.h>
#include <stdio.h>
#include <string.h>
#include <stdbool.h>
#ifdef __cplusplus
extern "C" {
#endif
typedef enum {
DEV_BLANK_TAG = 0U,
DEV_DW_UART_TAG,
DEV_DW_DMA_TAG,
DEV_DW_GPIO_TAG,
DEV_DW_IIC_TAG,
DEV_DW_QSPI_TAG,
DEV_DW_SDMMC_TAG,
DEV_DW_SDHCI_TAG,
DEV_DW_SPI_TAG,
DEV_DW_TIMER_TAG,
DEV_DW_WDT_TAG,
DEV_WJ_ADC_TAG,
DEV_WJ_AES_TAG,
DEV_WJ_CODEC_TAG,
DEV_WJ_CRC_TAG,
DEV_WJ_DMA_TAG,
DEV_WJ_EFLASH_TAG,
DEV_WJ_EFUSE_TAG,
DEV_WJ_ETB_TAG,
DEV_WJ_FFT_TAG,
DEV_WJ_I2S_TAG,
DEV_WJ_MBOX_TAG,
DEV_WJ_PADREG_TAG,
DEV_WJ_PDM_TAG,
DEV_WJ_PINMUX_TAG,
DEV_WJ_PMU_TAG,
DEV_WJ_PWM_TAG,
DEV_WJ_PWMR_TAG,
DEV_WJ_RNG_TAG,
DEV_WJ_ROM_TAG,
DEV_WJ_RSA_TAG,
DEV_WJ_RTC_TAG,
DEV_WJ_SASC_TAG,
DEV_WJ_SHA_TAG,
DEV_WJ_SPDIF_TAG,
DEV_WJ_SPIDF_TAG,
DEV_WJ_TDM_TAG,
DEV_WJ_TIPC_TAG,
DEV_WJ_USB_TAG,
DEV_WJ_USI_TAG,
DEV_WJ_VAD_TAG,
DEV_CD_QSPI_TAG,
DEV_DCD_ISO7816_TAG,
DEV_OSR_RNG_TAG,
DEV_QX_RTC_TAG,
DEV_RCHBAND_CODEC_TAG,
DEV_CMSDK_UART_TAG,
DEV_RAMBUS_150B_PKA_TAG,
DEV_RAMBUS_150B_TRNG_TAG,
DEV_RAMBUS_120SI_TAG,
DEV_RAMBUS_120SII_TAG,
DEV_RAMBUS_120SIII_TAG,
DEV_WJ_AVFS_TAG,
DEV_WJ_BMU_TAG,
} csi_dev_tag_t;
#ifdef __cplusplus
}
#endif
#endif /* _DRV_TAG_H_ */

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@@ -0,0 +1,73 @@
/*
* Copyright (C) 2017-2020 Alibaba Group Holding Limited
*/
/* device_types.h
*
* Driver Framework, Device API, Type Definitions
*
* The document "Driver Framework Porting Guide" contains the detailed
* specification of this API. The information contained in this header file
* is for reference only.
*/
#ifndef INCLUDE_GUARD_DEVICE_TYPES_H
#define INCLUDE_GUARD_DEVICE_TYPES_H
/*----------------------------------------------------------------------------
* Device_Handle_t
*
* This handle represents a device, typically one hardware block instance.
*
* The Device API can access the static device resources (registers and RAM
* inside the device) using offsets inside the device. This abstracts memory
* map knowledge and simplifies device instantiation.
*
* Each device has its own configuration, including the endianness swapping
* need for the words transferred. Endianness swapping can thus be performed
* on the fly and transparent to the caller.
*
* The details of the handle are implementation specific and must not be
* relied on, with one exception: NULL is guaranteed to be a non-existing
* handle.
*/
typedef void * Device_Handle_t;
/*----------------------------------------------------------------------------
* Device_Reference_t
*
* This is an implementation-specific reference for the device. It can
* be passed from the implementation of the Device API to other modules
* for use, for example, with OS services that require such a reference.
*
* The details of the handle are implementation specific and must not be
* relied on, with one exception: NULL is guaranteed to be a non-existing
* handle.
*/
typedef void * Device_Reference_t;
/*----------------------------------------------------------------------------
* Device_Data_t
*
* This is an implementation-specific reference for the device. It can
* be passed from the implementation of the Device API to other modules
* for use, for example, with OS services that require such a reference.
*/
typedef struct
{
// Physical address of the device mapped in memory
void * PhysAddr;
} Device_Data_t;
#endif /* Include Guard */
/* end of file device_types.h */

285
lib/sec_library/include/ecc.h Normal file
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@@ -0,0 +1,285 @@
/*
* Copyright (C) 2017-2022 Alibaba Group Holding Limited
*/
/******************************************************************************
* @file drv/ecc.h
* @brief Header File for ECC Driver
* @version V3.3
* @date 30. May 2022
* @model ECC
******************************************************************************/
#ifndef _DRV_ECC_H_
#define _DRV_ECC_H_
#include <stdint.h>
#include "common.h"
#ifdef __cplusplus
extern "C" {
#endif
#define ECC_PRIME_CURVE_G_BYTES 64
#define ECC_PRIME_CURVE_P_BYTES 70
typedef struct {
uint32_t ecc_curve : 1; ///< supports 256bits curve
} ecc_capabilities_t;
/**
\brief ECC ciphertext order
*/
typedef enum {
ECC_C1C3C2 = 0,
ECC_C1C2C3,
} ecc_cipher_order_e;
typedef enum {
ECC_ENDIAN_LITTLE = 0, ///< Little Endian
ECC_ENDIAN_BIG ///< Big Endian
} ecc_endian_mode_e;
typedef enum {
ECC_PRIME256V1 = 0,
} ecc_prime_curve_type;
/**
\brief ECC key exchange role
*/
typedef enum { ECC_Role_Sponsor = 0, ECC_Role_Responsor } ecc_exchange_role_e;
/****** ECC Event *****/
typedef enum {
ECC_EVENT_MAKE_KEY_COMPLETE = 0, ///< Make key completed
ECC_EVENT_ENCRYPT_COMPLETE, ///< Encrypt completed
ECC_EVENT_DECRYPT_COMPLETE, ///< Decrypt completed
ECC_EVENT_SIGN_COMPLETE, ///< Sign completed
ECC_EVENT_VERIFY_COMPLETE, ///< Verify completed
ECC_EVENT_EXCHANGE_KEY_COMPLETE, ///< Exchange key completed
} ecc_event_e;
typedef struct {
ecc_prime_curve_type type;
uint32_t *p;
} csi_ecc_prime_curve_t;
typedef struct {
ecc_prime_curve_type type;
uint8_t *G;
uint8_t *n;
} csi_ecc_curve_g_t;
/**
\brief ECC status
*/
typedef struct {
uint32_t busy : 1; ///< Calculate busy flag
} csi_ecc_state_t;
typedef struct {
csi_dev_t dev;
void * cb;
void * arg;
csi_ecc_state_t state;
ecc_prime_curve_type type;
} csi_ecc_t;
///< Pointer to \ref csi_ecc_callback_t : ECC Event call back.
typedef void (*csi_ecc_callback_t)(ecc_event_e event);
/**
\brief Initialize ECC.
\param[in] ecc ecc handle to operate.
\param[in] idx device id
\return \ref uint32_t
*/
csi_error_t csi_ecc_init(csi_ecc_t *ecc, uint32_t idx);
/**
\brief De-initialize ECC Interface. stops operation and releases the software resources used by the interface
\param[in] ecc ecc handle to operate.
\return none
*/
void csi_ecc_uninit(csi_ecc_t *ecc);
/**
\brief ecc get capability.
\param[in] ecc Operate handle.
\return \ref uint32_t
*/
csi_error_t csi_ecc_config(csi_ecc_t *ecc, ecc_cipher_order_e co,
ecc_endian_mode_e endian);
/**
\brief Attach the callback handler to ECC
\param[in] ecc Operate handle.
\param[in] cb Callback function
\param[in] arg User can define it by himself as callback's param
\return Error code \ref csi_error_t
*/
csi_error_t csi_ecc_attach_callback(csi_ecc_t *ecc, csi_ecc_callback_t cb,
void *arg);
/**
\brief Detach the callback handler
\param[in] ecc Operate handle.
*/
csi_error_t csi_ecc_detach_callback(csi_ecc_t *ecc);
/**
\brief ecc get capability.
\param[in] ecc Operate handle.
\param[out] cap Pointer of ecc_capabilities_t.
\return \ref uint32_t
*/
csi_error_t csi_ecc_get_capabilities(csi_ecc_t *ecc, ecc_capabilities_t *cap);
csi_error_t csi_ecc_check_keypair(csi_ecc_t *ecc, uint8_t pubkey[65], uint8_t prikey[32]);
/**
\brief generate ecc key.
\param[in] ecc ecc handle to operate.
\param[out] private Pointer to the ecc private key, alloc by caller.
\param[out] public Pointer to the ecc public key, alloc by caller.
\return \ref uint32_t
*/
csi_error_t csi_ecc_gen_key(csi_ecc_t *ecc, uint8_t pubkey[65],
uint8_t prikey[32]);
/**
\brief generate ecc pubkey by privkey.
\param[in] ecc ecc handle to operate.
\param[in] private Pointer to the ecc private key, alloc by caller.
\param[out] public Pointer to the ecc public key, alloc by caller.
\return \ref uint32_t
*/
csi_error_t csi_ecc_gen_pubkey(csi_ecc_t *ecc, uint8_t pubkey[65],
uint8_t prikey[32]);
/**
\brief ecc sign
\param[in] ecc ecc handle to operate.
\param[in] d Pointer to the digest.
\param[out] privkey Pointer to the private key
\param[out] s Pointer to the signature
\return \ref uint32_t
*/
csi_error_t csi_ecc_sign(csi_ecc_t *ecc, uint8_t d[32], uint8_t prikey[32],
uint8_t s[64]);
/**
\brief ecc sign
\param[in] ecc ecc handle to operate.
\param[in] d Pointer to the digest.
\param[out] privkey Pointer to the private key
\param[out] s Pointer to the signature
\return \ref uint32_t
*/
csi_error_t csi_ecc_sign_async(csi_ecc_t *ecc, uint8_t d[32],
uint8_t prikey[32], uint8_t s[64]);
/* TODO */
/**
\brief ecc verify
\param[in] ecc ecc handle to operate.
\param[in] d Pointer to the digest.
\param[out] privkey Pointer to the private key
\param[out] s Pointer to the signature
\return verify result
*/
bool csi_ecc_verify(csi_ecc_t *ecc, uint8_t d[32], uint8_t pubkey[65],
uint8_t s[64]);
/**
\brief ecc verify
\param[in] ecc ecc handle to operate.
\param[in] d Pointer to the digest.
\param[out] privkey Pointer to the private key
\param[out] s Pointer to the signature
\return verify result
*/
bool csi_ecc_verify_async(csi_ecc_t *ecc, uint8_t d[32], uint8_t pubkey[65],
uint8_t s[64]);
/**
\brief ecc encrypto
\param[in] ecc ecc handle to operate.
\param[in] Plain Pointer to the plaintext.
\param[in] PlainByteLen plaintext len
\param[in] pubKey public key.
\param[out] Cipher Pointer to the chipher
\param[out] CipherByteLen Pointer to the chipher len.
\return uint32_t
*/
csi_error_t csi_ecc_encrypt(csi_ecc_t *ecc, uint8_t *Plain,
uint32_t PlainByteLen, uint8_t pubKey[65],
uint8_t *Cipher, uint32_t *CipherByteLen);
/**
\brief ecc encrypto
\param[in] ecc ecc handle to operate.
\param[in] Cipher Pointer to the chipher
\param[in] CipherByteLen chipher len.
\param[in] prikey private key.
\param[out] Plain Pointer to the plaintext.
\param[out] PlainByteLen plaintext len
\return uint32_t
*/
csi_error_t csi_ecc_decrypt(csi_ecc_t *ecc, uint8_t *Cipher,
uint32_t CipherByteLen, uint8_t prikey[32],
uint8_t *Plain, uint32_t *PlainByteLen);
/**
\brief ecc key exchange
\param[in] ecc ecc handle to operate.
\return uint32_t
*/
csi_error_t csi_ecc_exchangekey(csi_ecc_t *ecc, ecc_exchange_role_e role,
uint8_t *dA, uint8_t *PB, uint8_t *rA,
uint8_t *RA, uint8_t *RB, uint8_t *ZA,
uint8_t *ZB, uint32_t kByteLen, uint8_t *KA,
uint8_t *S1, uint8_t *SA);
/**
\brief ecc key exchange get Z.
\param[in] ecc ecc handle to operate.
\return uint32_t
*/
csi_error_t csi_ecc_getZ(csi_ecc_t *ecc, uint8_t *ID, uint32_t byteLenofID,
uint8_t pubKey[65], uint8_t Z[32]);
/**
\brief ecc key exchange get E
\param[in] ecc ecc handle to operate.
\return uint32_t
*/
csi_error_t csi_ecc_getE(csi_ecc_t *ecc, uint8_t *M, uint32_t byteLen,
uint8_t Z[32], uint8_t E[32]);
/**
\brief Get ECC state.
\param[in] ecc ECC handle to operate.
\param[out] state ECC state \ref csi_ecc_state_t.
\return Error code \ref csi_error_t
*/
csi_error_t csi_ecc_get_state(csi_ecc_t *ecc, csi_ecc_state_t *state);
/**
\brief Enable ecc power manage
\param[in] ecc ECC handle to operate.
\return Error code \ref csi_error_t
*/
csi_error_t csi_ecc_enable_pm(csi_ecc_t *ecc);
/**
\brief Disable ecc power manage
\param[in] ecc ECC handle to operate.
*/
void csi_ecc_disable_pm(csi_ecc_t *ecc);
#ifdef __cplusplus
extern "C" {
#endif
#endif

41
lib/sec_library/include/ecdh.h Normal file
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@@ -0,0 +1,41 @@
/*
* Copyright (C) 2017-2022 Alibaba Group Holding Limited
*/
/******************************************************************************
* @file drv/ecdh.h
* @brief Header File for ECDH Driver
* @version V3.3
* @date 10.June 2022
* @model ECC
******************************************************************************/
#ifndef _DRV_ECDH_H_
#define _DRV_ECDH_H_
#include <stdint.h>
#include "common.h"
#ifdef __cplusplus
extern "C" {
#endif
/**
\brief ecdh cacl share secret
\param[in] ecc ecc handle to operate.
\param[in] pubkey Pointer to the A public key.
\param[in] privkey Pointer to the B private key.
\param[out] shareKey Pointer to the share secret.
\param[out] len length of the share secret.
\return \ref uint32_t
*/
csi_error_t csi_ecdh_calc_secret(csi_ecc_t *ecc, uint8_t privkey[32],
uint8_t pubkey[65], uint8_t shareKey[32],
uint32_t *len);
#ifdef __cplusplus
extern "C" {
#endif
#endif

23
lib/sec_library/include/kdf.h
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@@ -1,12 +1,19 @@
/*
* Copyright (C) 2019-2021 Alibaba Group Holding Limited
* Copyright (C) 2019-2020 Alibaba Group Holding Limited
*/
#ifndef __KDF_H__
#define __KDF_H__
#ifdef SEC_LIB_VERSION
#include "drv/aes.h"
#include "drv/sm4.h"
#include "drv/common.h"
#else
#include "aes.h"
#include "sm4.h"
#include "common.h"
#endif
#include <stdint.h>
typedef enum {
@@ -50,6 +57,9 @@ typedef enum {
KDF_KEY_TYPE_TDES_192,
KDF_KEY_TYPE_TDES_128,
KDF_KEY_TYPE_DES,
/* for rpmb, str */
/* KDF_KEY_TYPE_HMAC_SHA256,
*/
KDF_KEY_TYPE_MAX,
} csi_kdf_key_type_t;
@@ -113,12 +123,12 @@ csi_error_t csi_kdf_destory_key(csi_kdf_t *kdf, csi_kdf_derived_key_t dkey);
/**
\brief Set key to algorithim engine.
\param[in] handle Handle to cipher.
\param[in] kdf Handle to operate.
\param[in] handle Handle to cipher.
\param[in] dkey derived key type.
\return error code
*/
csi_error_t csi_kdf_set_key(csi_kdf_key_handle_t *handle, csi_kdf_t *kdf,
csi_error_t csi_kdf_set_key(csi_kdf_t *kdf, csi_kdf_key_handle_t *handle,
csi_kdf_derived_key_t dkey);
/**
@@ -139,4 +149,11 @@ csi_error_t csi_kdf_clear_key(csi_kdf_t *kdf, csi_kdf_derived_key_t dkey);
csi_error_t csi_kdf_get_key_attr(csi_kdf_t *kdf, csi_kdf_derived_key_t dkey,
csi_kdf_key_attr_t *attr);
/**
\brief kdf generate hmac key.
\param[in] kdf Handle to operate
*/
csi_error_t csi_kdf_gen_hmac_key(uint8_t* key,uint32_t * length);
#endif

10
lib/sec_library/include/keyram.h
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@@ -1,5 +1,5 @@
/*
* Copyright (C) 2017-2021 Alibaba Group Holding Limited
* Copyright (C) 2017-2020 Alibaba Group Holding Limited
*/
/******************************************************************************
@@ -9,7 +9,7 @@
* @date 12. MAR 2021
******************************************************************************/
#include "drv/kdf.h"
#include "kdf.h"
#include <stdio.h>
#include <string.h>
@@ -45,7 +45,7 @@
*
* @return uint32_t
*/
uint32_t keyram_init();
uint32_t keyram_init(void);
/**
* @brief keyram set key.
@@ -70,9 +70,9 @@ uint32_t keyram_get_key_addr(csi_kdf_derived_key_t key, uint64_t *addr);
*
* @return uint32_t
*/
uint32_t keyram_clear();
uint32_t keyram_clear(void);
/**
* @brief Uninit. This function will lock KDF.
*/
void keyram_uninit();
void keyram_uninit(void);

367
lib/sec_library/include/list.h Normal file
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@@ -0,0 +1,367 @@
/*
* Copyright (C) 2015-2020 Alibaba Group Holding Limited
*/
/******************************************************************************
* @file drv/list.h
* @brief Header File for LIST Driver
* @version V1.0
* @date 10. Oct 2020
* @model list
******************************************************************************/
#ifndef AOS_LIST_H
#define AOS_LIST_H
#ifdef __cplusplus
extern "C" {
#endif
/**
\brief Get offset of a member variable
\param[in] type The type of the struct this is embedded in
\param[in] member The name of the variable within the struct
\return None
*/
#define aos_offsetof(type, member) ((size_t)&(((type *)0)->member))
/**
\brief Get the struct for this entry
\param[in] ptr The list head to take the element from
\param[in] type The type of the struct this is embedded in
\param[in] member The name of the variable within the struct
\return None
*/
#define aos_container_of(ptr, type, member) \
((type *) ((char *) (ptr) - aos_offsetof(type, member)))
/* For double link list */
typedef struct dlist_s {
struct dlist_s *prev;
struct dlist_s *next;
} dlist_t;
static inline void __dlist_add(dlist_t *node, dlist_t *prev, dlist_t *next)
{
node->next = next;
node->prev = prev;
prev->next = node;
next->prev = node;
}
/**
\brief Get the struct for this entry
\param[in] addr The list head to take the element from
\param[in] type The type of the struct this is embedded in
\param[in] member The name of the dlist_t within the struct
\return None
*/
#define dlist_entry(addr, type, member) \
((type *)((long)addr - aos_offsetof(type, member)))
static inline void dlist_add(dlist_t *node, dlist_t *queue)
{
__dlist_add(node, queue, queue->next);
}
static inline void dlist_add_tail(dlist_t *node, dlist_t *queue)
{
__dlist_add(node, queue->prev, queue);
}
static inline void dlist_del(dlist_t *node)
{
dlist_t *prev = node->prev;
dlist_t *next = node->next;
prev->next = next;
next->prev = prev;
}
static inline void dlist_init(dlist_t *node)
{
node->next = (node->prev = node);
}
static inline void INIT_AOS_DLIST_HEAD(dlist_t *list)
{
list->next = list;
list->prev = list;
}
static inline int dlist_empty(const dlist_t *head)
{
return head->next == head;
}
/**
\brief Initialise the list
\param[in] list The list to be inited
\return None
*/
#define AOS_DLIST_INIT(list) {&(list), &(list)}
/**
\brief Get the first element from a list
\param[in] ptr The list head to take the element from
\param[in] type The type of the struct this is embedded in
\param[in] member The name of the dlist_t within the struct
\return None
*/
#define dlist_first_entry(ptr, type, member) \
dlist_entry((ptr)->next, type, member)
/**
\brief Iterate over a list
\param[in] pos The &struct dlist_t to use as a loop cursor
\param[in] head The head for your list
\return None
*/
#define dlist_for_each(pos, head) \
for (pos = (head)->next; pos != (head); pos = pos->next)
/**
\brief Iterate over a list safe against removal of list entry
\param[in] pos The &struct dlist_t to use as a loop cursor
\param[in] n Another &struct dlist_t to use as temporary storage
\param[in] head The head for your list
\return None
*/
#define dlist_for_each_safe(pos, n, head) \
for (pos = (head)->next, n = pos->next; pos != (head); \
pos = n, n = pos->next)
/**
\brief Iterate over list of given type
\param[in] queue The head for your list
\param[in] node The &struct dlist_t to use as a loop cursor
\param[in] type The type of the struct this is embedded in
\param[in] member The name of the dlist_t within the struct
\return None
*/
#define dlist_for_each_entry(queue, node, type, member) \
for (node = aos_container_of((queue)->next, type, member); \
&node->member != (queue); \
node = aos_container_of(node->member.next, type, member))
/**
\brief Iterate over list of given type safe against removal of list entry
\param[in] queue The head for your list
\param[in] n The type * to use as a temp
\param[in] node The type * to use as a loop cursor
\param[in] type The type of the struct this is embedded in
\param[in] member The name of the dlist_t within the struct
\return None
*/
#define dlist_for_each_entry_safe(queue, n, node, type, member) \
for (node = aos_container_of((queue)->next, type, member), \
n = (queue)->next ? (queue)->next->next : NULL; \
&node->member != (queue); \
node = aos_container_of(n, type, member), n = n ? n->next : NULL)
/**
\brief Get the struct for this entry
\param[in] ptr The list head to take the element from
\param[in] type The type of the struct this is embedded in
\param[in] member The name of the variable within the struct
\return None
*/
#define list_entry(ptr, type, member) \
aos_container_of(ptr, type, member)
/**
\brief Iterate backwards over list of given type
\param[in] pos The type * to use as a loop cursor
\param[in] head The head for your list
\param[in] member The name of the dlist_t within the struct
\param[in] type The type of the struct this is embedded in
\return None
*/
#define dlist_for_each_entry_reverse(pos, head, member, type) \
for (pos = list_entry((head)->prev, type, member); \
&pos->member != (head); \
pos = list_entry(pos->member.prev, type, member))
/**
\brief Get the list length
\param[in] queue The head for your list
\return None
*/
int dlist_entry_number(dlist_t *queue);
/**
\brief Initialise the list
\param[in] name The list to be initialized
\return None
*/
#define AOS_DLIST_HEAD_INIT(name) { &(name), &(name) }
/**
\brief Initialise the list
\param[in] name The list to be initialized
\return None
*/
#define AOS_DLIST_HEAD(name) \
dlist_t name = AOS_DLIST_HEAD_INIT(name)
/* For single link list */
typedef struct slist_s {
struct slist_s *next;
} slist_t;
static inline void slist_add(slist_t *node, slist_t *head)
{
node->next = head->next;
head->next = node;
}
void slist_add_tail(slist_t *node, slist_t *head);
static inline void slist_del(slist_t *node, slist_t *head)
{
while (head->next) {
if (head->next == node) {
head->next = node->next;
break;
}
head = head->next;
}
}
static inline int slist_empty(const slist_t *head)
{
return !head->next;
}
static inline void slist_init(slist_t *head)
{
head->next = 0;
}
static inline slist_t *slist_remove(slist_t *l, slist_t *n)
{
/* Remove slist head */
struct slist_s *node = l;
while (node->next && (node->next != n)) {
node = node->next;
}
/* Remove node */
if (node->next != (slist_t *)0) {
node->next = node->next->next;
}
return l;
}
static inline slist_t *slist_first(slist_t *l)
{
return l->next;
}
static inline slist_t *slist_tail(slist_t *l)
{
while (l->next) {
l = l->next;
}
return l;
}
static inline slist_t *slist_next(slist_t *n)
{
return n->next;
}
/**
\brief Iterate over list of given type
\param[in] node The type * to use as a loop cursor
\param[in] type The type of the struct this is embedded in
\param[in] member The name of the slist_t within the struct
\param[in] queue The head for your list
\return None
*/
#define slist_for_each_entry(queue, node, type, member) \
for (node = aos_container_of((queue)->next, type, member); \
&node->member; \
node = aos_container_of(node->member.next, type, member))
/**
\brief Iterate over list of given type safe against removal of list entry
\param[in] queue The head for your list
\param[in] tmp The type * to use as a temp
\param[in] node The type * to use as a loop cursor
\param[in] type The type of the struct this is embedded in
\param[in] member The name of the slist_t within the struct
\return None
*/
#define slist_for_each_entry_safe(queue, tmp, node, type, member) \
for (node = aos_container_of((queue)->next, type, member), \
tmp = (queue)->next ? (queue)->next->next : NULL; \
&node->member; \
node = aos_container_of(tmp, type, member), tmp = tmp ? tmp->next : tmp)
/**
\brief Initialise the list
\param[in] name The list to be initialized
\return None
*/
#define AOS_SLIST_HEAD_INIT(name) {0}
/**
\brief Initialise the list
\param[in] name The list to be initialized
\return None
*/
#define AOS_SLIST_HEAD(name) \
slist_t name = AOS_SLIST_HEAD_INIT(name)
/**
\brief Get the struct for this entry
\param[in] addr The list head to take the element from
\param[in] type The type of the struct this is embedded in
\param[in] member The name of the slist_t within the struct
\return None
*/
#define slist_entry(addr, type, member) ( \
addr ? (type *)((long)addr - aos_offsetof(type, member)) : (type *)addr \
)
/**
\brief Get the first element from a list
\param[in] ptr The list head to take the element from
\param[in] type The type of the struct this is embedded in
\param[in] member The name of the slist_t within the struct
\return None
*/
#define slist_first_entry(ptr, type, member) \
slist_entry((ptr)->next, type, member)
/**
\brief Slist_tail_entry - get the tail element from a slist
\param[in] ptr The slist head to take the element from
\param[in] type The type of the struct this is embedded in
\param[in] member The name of the slist_struct within the struct
\return None
\note That slist is expected to be not empty
*/
#define slist_tail_entry(ptr, type, member) \
slist_entry(slist_tail(ptr), type, member)
/**
\brief Get the list length
\param[in] queue The head for your list
\return None
*/
int slist_entry_number(slist_t *queue);
#ifdef __cplusplus
}
#endif
#endif /* AOS_LIST_H */

149
lib/sec_library/include/rambus.h Normal file
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@@ -0,0 +1,149 @@
/*
* Copyright (C) 2017-2020 Alibaba Group Holding Limited
*/
#ifndef INC_RAMBUS_H
#define INC_RAMBUS_H
#include "device_types.h"
#ifdef SEC_LIB_VERSION
#include "drv/common.h"
#include "device_rw.h"
#include "rambus_log.h"
#include "rambus_errcode.h"
#else
#include "common.h"
#endif
extern uint64_t g_freq_timer;
extern uint64_t g_freq_ip;
extern uint64_t g_start_ctr;
extern uint64_t g_end_ctr;
extern uint64_t g_data_len_in_bits;
extern uint32_t g_type;
enum rambus_cipher_padding_mode {
PADDING_ZERO,
PADDING_FF,
PADDING_RANDOM,
};
uint32_t rb_get_random_byte(uint8_t *buf, uint32_t count);
uint32_t rb_get_random_byte_nozero(uint8_t *buf, uint32_t count);
uint32_t kdf_get_mask(uint8_t *mask, uint32_t len);
/* 1 bpc, 2 tps, 3 bps */
void rb_perf_init(uint32_t data_len_in_bits, uint32_t type);
void rb_perf_start(void);
void rb_perf_end(void);
void rb_perf_get(char *ncase);
#define DEFAULT_TIMEOUT 1000U
#ifdef CONFIG_ALG_PERF_TEST
#define RB_PERF_INIT(bits, type) \
do { \
if (data_len_in_bits != 0) { \
g_data_len_in_bits = data_len_in_bits; \
} \
if (type != 0) { \
g_type = type; \
} \
} while (0)
#define RB_PERF_START_POINT() \
do { \
g_start_ctr = ((((uint64_t)csi_coret_get_valueh() << 32U) | \
csi_coret_get_value())); \
} while (0)
#define RB_PERF_END_POINT() \
do { \
g_end_ctr = ((((uint64_t)csi_coret_get_valueh() << 32U) | \
csi_coret_get_value())); \
} while (0)
#else
#define RB_PERF_INIT(...)
#define RB_PERF_START_POINT(...)
#define RB_PERF_END_POINT(...)
#endif
static inline void rb_xor(uint32_t *a, uint32_t *b, uint32_t *c, uint32_t len) {
for (int i = 0; i < (int)len; i++) {
c[i] = a[i] ^ b[i];
}
}
/**
* @brief Get the aes sca enable config
*
* @param is_en is enable
* @return uint32_t
*/
uint32_t rb_get_aes_sca(uint32_t *is_en);
/**
* @brief Get the sm4 sca enable config
*
* @param is_en is enable
* @return uint32_t
*/
uint32_t rb_get_sm4_sca(uint32_t *is_en);
/**
* @brief Get the pka sca enable config
*
* @param is_en is enable
* @return uint32_t
*/
uint32_t rb_get_pka_sca(uint32_t *is_en);
/**
* @brief rb_cache_en
* @return uint32_t enable: 1
*
*/
uint32_t rb_cache_en(void);
/**
* @brief trng init
*
* @return csi_error_t
*/
csi_error_t trng_init(void);
/**
* @brief rb wait status
*
* @param dev
* @param offset
* @param mask
* @param status
* @return uint32_t
*/
csi_error_t rb_wait_status(Device_Handle_t *dev, const uint32_t offset, uint32_t mask,
uint32_t status);
/**
* \brief rambus crypto init.
* \return 0 if successful, or error code
*/
uint32_t rambus_crypto_init(void);
/**
* @brief rambus crypto uninit.
*
*/
void rambus_crypto_uninit(void);
/**
* \brief rambus set cipher padding type.
* @param padding_mode cipher padding mode
* \return 0 if successful, or error code
*/
uint32_t rambus_enable_cipher_padding_type(enum rambus_cipher_padding_mode padding_mode);
#endif

4
lib/sec_library/include/rng.h
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@@ -1,5 +1,5 @@
/*
* Copyright (C) 2017-2021 Alibaba Group Holding Limited
* Copyright (C) 2017-2020 Alibaba Group Holding Limited
*/
/******************************************************************************
@@ -12,7 +12,7 @@
#ifndef _DRV_TNG_H_
#define _DRV_TNG_H_
#include "drv/common.h"
#include "common.h"
#include <stdint.h>
#ifdef __cplusplus

58
lib/sec_library/include/rsa.h
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@@ -1,5 +1,5 @@
/*
* Copyright (C) 2017-2021 Alibaba Group Holding Limited
* Copyright (C) 2017-2020 Alibaba Group Holding Limited
*/
/******************************************************************************
* @file drv/rsa.h
@@ -16,7 +16,29 @@ extern "C" {
#endif
#include <stdint.h>
#include <drv/common.h>
#include "common.h"
#define RSA_PRIME_256_BIT_LEN 128
#define RSA_PRIME_512_BIT_LEN 256
#define RSA_PRIME_1024_BIT_LEN 512
#define RSA_PRIME_2048_BIT_LEN 1024
#define RSA_PRIME_4096_BIT_LEN 2048
#define RSA_256_BYTE_LEN 32
#define RSA_512_BYTE_LEN 64
#define RSA_1024_BYTE_LEN 128
#define RSA_2048_BYTE_LEN 256
#define RSA_4096_BYTE_LEN 512
#define RSA_EM_BYTE_LEN RSA_4096_BYTE_LEN
#define SHA256_DIGEST_BYTE_LEN 32
#define RSA_PKCS1_PADDING_SIZE 11
#define RSA_MD5_OID_LEN (6 + 8 + 4)
#define RSA_SHA1_OID_LEN (6 + 5 + 4)
#define RSA_SHA224_OID_LEN (6 + 9 + 4)
#define RSA_SHA256_OID_LEN (6 + 9 + 4)
#define RSA_SHA384_OID_LEN (6 + 9 + 4)
#define RSA_SHA512_OID_LEN (6 + 9 + 4)
/*----- RSA Control Codes: Mode Parameters: Key Bits -----*/
typedef enum {
@@ -47,11 +69,17 @@ typedef enum {
RSA_HASH_TYPE_SHA512
} csi_rsa_hash_type_t;
typedef struct {
csi_rsa_hash_type_t hash_type;
uint32_t oid_len;
uint8_t *oid;
}RSA_OID;
typedef struct {
void *n; ///< Pointer to the public modulus
void *e; ///< Pointer to the public exponent
void *d; ///< Pointer to the private exponent
csi_rsa_key_bits_t key_bits; ///< RSA KEY BITS
csi_rsa_key_bits_t key_bits; ///< RSA KEY BITS
csi_rsa_padding_type_t padding_type; ///< RSA PADDING TYPE
} csi_rsa_context_t;
@@ -257,6 +285,30 @@ csi_error_t csi_rsa_enable_pm(csi_rsa_t *rsa);
*/
void csi_rsa_disable_pm(csi_rsa_t *rsa);
/**
\brief Get publickey by p q prime data
\param[in] rsa rsa handle to operate.
\param[in] p Pointer to the prime p
\param[in] p_byte_len Pointer to the prime p byte length
\param[in] q Pointer to the prime q
\param[in] q_byte_len Pointer to the prime q byte length
\param[in] out Pointer to the publickey
\param[in] keybits_len Pointer to the publickey bits length
\return \ref csi_error_t
*/
csi_error_t csi_rsa_get_publickey(csi_rsa_t *rsa, void *p, uint32_t p_byte_len, void *q, uint32_t q_byte_len, void *out, csi_rsa_key_bits_t keybits_len);
/**
\brief Generation rsa keyparis
\param[in] rsa rsa handle to operate.
\param[in] context Pointer to the rsa context
\param[in] keybits_len Pointer to the publickey bits length
\return \ref csi_error_t
*/
csi_error_t csi_rsa_gen_keypairs(csi_rsa_t *rsa, csi_rsa_context_t *context, csi_rsa_key_bits_t keybits_len);
void csi_rsa_set_ignore_decrypt_error(bool checked);
#ifdef __cplusplus
}
#endif

93
lib/sec_library/include/sec_crypto_aes.h
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@@ -1,5 +1,5 @@
/*
* Copyright (C) 2017-2021 Alibaba Group Holding Limited
* Copyright (C) 2017-2020 Alibaba Group Holding Limited
*/
/******************************************************************************
* @file seccrypt_aes.h
@@ -11,11 +11,16 @@
#ifndef _SC_AES_H_
#define _SC_AES_H_
#include "sec_include_config.h"
#include <stdint.h>
#include <sec_crypto_errcode.h>
#include "sec_crypto_errcode.h"
#ifdef CONFIG_SYSTEM_SECURE
#include "drv/aes.h"
#ifdef SEC_LIB_VERSION
#include <drv/aes.h>
#else
#include "aes.h"
#endif
#endif
#ifdef CONFIG_SEC_CRYPTO_AES_SW
@@ -187,8 +192,7 @@ uint32_t sc_aes_cfb8_decrypt(sc_aes_t *aes, void *in, void *out, uint32_t size,
\param[out] num the number of the 128-bit block we have used
\return error code \ref uint32_t
*/
uint32_t sc_aes_cfb128_decrypt(sc_aes_t *aes, void *in, void *out, uint32_t size, void *iv,
uint32_t *num);
uint32_t sc_aes_cfb128_decrypt(sc_aes_t *aes, void *in, void *out, uint32_t size, void *iv);
/**
\brief Aes cfb128 encrypt
@@ -200,8 +204,7 @@ uint32_t sc_aes_cfb128_decrypt(sc_aes_t *aes, void *in, void *out, uint32_t size
\param[out] num the number of the 128-bit block we have used
\return error code \ref uint32_t
*/
uint32_t sc_aes_cfb128_encrypt(sc_aes_t *aes, void *in, void *out, uint32_t size, void *iv,
uint32_t *num);
uint32_t sc_aes_cfb128_encrypt(sc_aes_t *aes, void *in, void *out, uint32_t size, void *iv);
/**
\brief Aes ofb encrypt
\param[in] aes handle to operate
@@ -209,11 +212,11 @@ uint32_t sc_aes_cfb128_encrypt(sc_aes_t *aes, void *in, void *out, uint32_t size
\param[out] out Pointer to the Result data
\param[in] size the Source data size
\param[in] iv init vector
\param[out] num the number of the 128-bit block we have used
\param[in] key_len key bits
\return error code \ref uint32_t
*/
uint32_t sc_aes_ofb_encrypt(sc_aes_t *aes, void *in, void *out, uint32_t size, void *iv,
uint32_t *num);
uint32_t sc_aes_ofb_encrypt(sc_aes_t *aes, void *in, void *out, uint32_t size, void *iv);
/**
\brief Aes ofb decrypt
\param[in] aes handle to operate
@@ -221,43 +224,83 @@ uint32_t sc_aes_ofb_encrypt(sc_aes_t *aes, void *in, void *out, uint32_t size, v
\param[out] out Pointer to the Result data
\param[in] size the Source data size
\param[in] iv init vector
\param[out] num the number of the 128-bit block we have used
\param[in] key_len key bits
\return error code \ref uint32_t
*/
uint32_t sc_aes_ofb_decrypt(sc_aes_t *aes, void *in, void *out, uint32_t size, void *iv,
uint32_t *num);
uint32_t sc_aes_ofb_decrypt(sc_aes_t *aes, void *in, void *out, uint32_t size, void *iv);
/**
\brief Aes ctr encrypt
\param[in] aes handle to operate
\param[in] in Pointer to the Source data
\param[out] out Pointer to the Result data
\param[in] size the Source data size
\param[in] nonce_counter Pointer to the 128-bit nonce and counter
\param[in] stream_block Pointer to the saved stream-block for resuming
\param[in] iv init vector
\param[out] num the number of the 128-bit block we have used
\return error code \ref uint32_t
*/
uint32_t sc_aes_ctr_encrypt(sc_aes_t *aes, void *in, void *out, uint32_t size,
uint8_t nonce_counter[16], uint8_t stream_block[16], void *iv,
uint32_t *num);
uint32_t sc_aes_ctr_encrypt(sc_aes_t *aes, void *in, void *out, uint32_t size,void *iv);
/**
\brief Aes ctr decrypt
\param[in] aes handle to operate
\param[in] in Pointer to the Source data
\param[out] out Pointer to the Result data
\param[in] size the Source data size
\param[in] nonce_counter Pointer to the 128-bit nonce and counter
\param[in] stream_block Pointer to the saved stream-block for resuming
\param[in] iv init vecotr
\param[out] num the number of the 128-bit block we have used
\return error code \ref uint32_t
*/
uint32_t sc_aes_ctr_decrypt(sc_aes_t *aes, void *in, void *out, uint32_t size,
uint8_t nonce_counter[16], uint8_t stream_block[16], void *iv,
uint32_t *num);
uint32_t sc_aes_ctr_decrypt(sc_aes_t *aes, void *in, void *out, uint32_t size,void *iv);
/**
\brief Aes gcm encrypt
\param[in] dev_aes dev_aes handle to operate
\param[in] in Pointer to the Source data.
\param[out] out Pointer to the Result data
\param[in] size the Source data size
\param[in] iv init vector
\return error code \ref csi_error_t
*/
uint32_t sc_aes_gcm_encrypt(sc_aes_t *aes, void *in, void *out,uint32_t size, uint32_t add_len, void *iv);
/**
\brief Aes gcm decrypt
\param[in] dev_aes dev_aes handle to operate
\param[in] in Pointer to the Source data.
\param[out] out Pointer to the Result data
\param[in] size the Source data size
\param[in] iv init vecotr
\return error code \ref csi_error_t
*/
uint32_t sc_aes_gcm_decrypt(sc_aes_t *aes, void *in, void *out,uint32_t size, uint32_t add_len, void *iv);
/**
\brief Aes gcm encrypt
\param[in] dev_aes dev_aes handle to operate
\param[in] in Pointer to the Source data.
\param[out] out Pointer to the Result data
\param[in] size the Source data size
\param[in] iv init vector
\param[in] tag_out tag output ,parse null if not needed
\return error code \ref csi_error_t
*/
uint32_t sc_aes_ccm_encrypt(sc_aes_t *aes, void *in, void *out,uint32_t size, uint32_t add_len, void *iv, uint8_t* tag_out);
/**
\brief Aes gcm decrypt
\param[in] dev_aes dev_aes handle to operate
\param[in] in Pointer to the Source data.
\param[out] out Pointer to the Result data
\param[in] size the Source data size
\param[in] iv init vecotr
\param[in] tag_out tag output,parse null if not needed
\return error code \ref csi_error_t
*/
uint32_t sc_aes_ccm_decrypt(sc_aes_t *aes, void *in, void *out,uint32_t size, uint32_t add_len, void *iv, uint8_t* tag_out);
void sc_aes_dma_enable(sc_aes_t *aes, uint8_t en);
#ifdef __cplusplus
}
#endif
#endif /* _SC_AES_H_ */

2
lib/sec_library/include/sec_crypto_common.h
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@@ -1,5 +1,5 @@
/*
* Copyright (C) 2019-2021 Alibaba Group Holding Limited
* Copyright (C) 2019-2020 Alibaba Group Holding Limited
*/

265
lib/sec_library/include/sec_crypto_ecc.h Normal file
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@@ -0,0 +1,265 @@
/*
* Copyright (C) 2017-2022 Alibaba Group Holding Limited
*/
/******************************************************************************
* @file sec_crypt_ecc.h
* @brief Header File for ECC
* @version V3.3
* @date 30. May 2022
* @model ecc
******************************************************************************/
#ifndef _SC_ECC_H_
#define _SC_ECC_H_
#include "sec_include_config.h"
#define CONFIG_SEC_CRYPTO_ECC
#ifdef CONFIG_SEC_CRYPTO_ECC
#ifdef __cplusplus
extern "C" {
#endif
#ifdef SEC_LIB_VERSION
#include "drv/ecc.h"
#else
#include "ecc.h"
#endif
typedef enum {
SC_ECC_PRIME256V1 = 0,
} sc_ecc_curve_type;
/**
\brief ECC ciphertext order
*/
typedef enum {
SC_ECC_C1C3C2 = 0,
SC_ECC_C1C2C3,
} sc_ecc_cipher_order_e;
typedef enum {
SC_ECC_ENDIAN_LITTLE = 0, ///< Little Endian
SC_ECC_ENDIAN_BIG ///< Big Endian
} sc_ecc_endian_mode_e;
/**
\brief ECC key exchange role
*/
typedef enum { SC_ECC_Role_Sponsor = 0, SC_ECC_Role_Responsor } sc_ecc_exchange_role_e;
/****** ECC Event *****/
typedef enum {
SC_ECC_EVENT_MAKE_KEY_COMPLETE = 0, ///< Make key completed
SC_ECC_EVENT_ENCRYPT_COMPLETE, ///< Encrypt completed
SC_ECC_EVENT_DECRYPT_COMPLETE, ///< Decrypt completed
SC_ECC_EVENT_SIGN_COMPLETE, ///< Sign completed
SC_ECC_EVENT_VERIFY_COMPLETE, ///< Verify completed
SC_ECC_EVENT_EXCHANGE_KEY_COMPLETE, ///< Exchange key completed
} sc_ecc_event_e;
typedef struct {
uint32_t ecc_curve : 1; ///< supports 256bits curve
} sc_ecc_capabilities_t;
/**
\brief ECC status
*/
typedef struct {
uint32_t busy : 1; ///< Calculate busy flag
} sc_ecc_state_t;
typedef struct {
#ifdef CONFIG_CSI_V2
csi_ecc_t ecc;
#endif
} sc_ecc_t;
///< Pointer to \ref sc_ecc_callback_t : ECC Event call back.
typedef void (*sc_ecc_callback_t)(sc_ecc_event_e event);
/**
\brief Initialize ECC.
\param[in] ecc ecc handle to operate.
\param[in] idx device id
\return \ref uint32_t
*/
uint32_t sc_ecc_init(sc_ecc_t *ecc, uint32_t idx);
/**
\brief De-initialize ECC Interface. stops operation and releases the
software resources used by the interface \param[in] ecc ecc handle to
operate. \return none
*/
void sc_ecc_uninit(sc_ecc_t *ecc);
/**
\brief ecc get capability.
\param[in] ecc Operate handle.
\return \ref uint32_t
*/
uint32_t sc_ecc_config(sc_ecc_t *ecc, sc_ecc_cipher_order_e co,
sc_ecc_endian_mode_e endian);
/**
\brief Attach the callback handler to ECC
\param[in] ecc Operate handle.
\param[in] cb Callback function
\param[in] arg User can define it by himself as callback's param
\return Error code \ref uint32_t
*/
uint32_t sc_ecc_attach_callback(sc_ecc_t *ecc, sc_ecc_callback_t cb, void *arg);
/**
\brief Detach the callback handler
\param[in] ecc Operate handle.
*/
uint32_t sc_ecc_detach_callback(sc_ecc_t *ecc);
/**
\brief ecc get capability.
\param[in] ecc Operate handle.
\param[out] cap Pointer of sc_ecc_capabilities_t.
\return \ref uint32_t
*/
uint32_t sc_ecc_get_capabilities(sc_ecc_t *ecc, sc_ecc_capabilities_t *cap);
uint32_t sc_ecc_check_keypair(sc_ecc_t *ecc, uint8_t pubkey[65],
uint8_t prikey[32]);
/**
\brief generate ecc key.
\param[in] ecc ecc handle to operate.
\param[out] private Pointer to the ecc private key, alloc by caller.
\param[out] public Pointer to the ecc public key, alloc by caller.
\return \ref uint32_t
*/
uint32_t sc_ecc_gen_key(sc_ecc_t *ecc, uint8_t pubkey[65], uint8_t prikey[32]);
/**
\brief generate ecc pubkey.
\param[in] ecc ecc handle to operate.
\param[in] prikey Pointer to the ecc private key, alloc by caller.
\param[out] pubkey Pointer to the ecc public key, alloc by caller.
\return \ref uint32_t
*/
uint32_t sc_ecc_gen_pubkey(sc_ecc_t *ecc, uint8_t pubkey[65],
uint8_t prikey[32], sc_ecc_curve_type type);
/**
\brief ecc sign
\param[in] ecc ecc handle to operate.
\param[in] d Pointer to the digest.
\param[out] privkey Pointer to the private key
\param[out] s Pointer to the signature
\return \ref uint32_t
*/
uint32_t sc_ecc_sign(sc_ecc_t *ecc, uint8_t d[32], uint8_t prikey[32],
uint8_t s[64], sc_ecc_curve_type type);
/**
\brief ecc sign
\param[in] ecc ecc handle to operate.
\param[in] d Pointer to the digest.
\param[out] privkey Pointer to the private key
\param[out] s Pointer to the signature
\return \ref uint32_t
*/
uint32_t sc_ecc_sign_async(sc_ecc_t *ecc, uint8_t d[32], uint8_t prikey[32],
uint8_t s[64], sc_ecc_curve_type type);
/* TODO */
/**
\brief ecc verify
\param[in] ecc ecc handle to operate.
\param[in] d Pointer to the digest.
\param[out] privkey Pointer to the private key
\param[out] s Pointer to the signature
\return verify result
*/
bool sc_ecc_verify(sc_ecc_t *ecc, uint8_t d[32], uint8_t pubkey[65],
uint8_t s[64], sc_ecc_curve_type type);
/**
\brief ecc verify
\param[in] ecc ecc handle to operate.
\param[in] d Pointer to the digest.
\param[out] privkey Pointer to the private key
\param[out] s Pointer to the signature
\return verify result
*/
bool sc_ecc_verify_async(sc_ecc_t *ecc, uint8_t d[32], uint8_t pubkey[65],
uint8_t s[64], sc_ecc_curve_type type);
/**
\brief ecc encrypto
\param[in] ecc ecc handle to operate.
\param[in] plain Pointer to the plaintext.
\param[in] PlainByteLen plaintext len
\param[in] pubKey public key.
\param[out] cipher Pointer to the chipher
\param[out] cipher_byte_len Pointer to the chipher len.
\return uint32_t
*/
uint32_t sc_ecc_encrypt(sc_ecc_t *ecc, uint8_t *plain, uint32_t plain_len,
uint8_t pubKey[65], uint8_t *cipher,
uint32_t *cipher_len);
/**
\brief ecc encrypto
\param[in] ecc ecc handle to operate.
\param[in] cipher Pointer to the chipher
\param[in] CipherByteLen chipher len.
\param[in] prikey private key.
\param[out] plain Pointer to the plaintext.
\param[out] PlainByteLen plaintext len
\return uint32_t
*/
uint32_t sc_ecc_decrypt(sc_ecc_t *ecc, uint8_t *cipher, uint32_t cipher_len,
uint8_t prikey[32], uint8_t *plain,
uint32_t *plain_len);
/**
\brief ecc key exchange
\param[in] ecc ecc handle to operate.
\return uint32_t
*/
uint32_t sc_ecc_exchangekey(sc_ecc_t *ecc, sc_ecc_exchange_role_e role,
uint8_t *da, uint8_t *pb, uint8_t *ra1, uint8_t *ra,
uint8_t *rb, uint8_t *za, uint8_t *zb,
uint32_t k_len, uint8_t *ka, uint8_t *s1,
uint8_t *sa);
/**
\brief ecc key exchange get Z.
\param[in] ecc ecc handle to operate.
\return uint32_t
*/
uint32_t sc_ecc_getZ(sc_ecc_t *ecc, uint8_t *id, uint32_t id_len,
uint8_t pubkey[65], uint8_t z[32]);
/**
\brief ecc key exchange get E
\param[in] ecc ecc handle to operate.
\return uint32_t
*/
uint32_t sc_ecc_getE(sc_ecc_t *ecc, uint8_t *m, uint32_t len, uint8_t z[32],
uint8_t e[32]);
/**
\brief Get ECC state.
\param[in] ecc ECC handle to operate.
\param[out] state ECC state \ref sc_ecc_state_t.
\return Error code \ref uint32_t
*/
uint32_t sc_ecc_get_state(sc_ecc_t *ecc, sc_ecc_state_t *state);
#ifdef __cplusplus
extern "C" {
#endif
#endif
#endif /* _SC_ECC_H_ */

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lib/sec_library/include/sec_crypto_ecdh.h Normal file
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@@ -0,0 +1,53 @@
/*
* Copyright (C) 2017-2022 Alibaba Group Holding Limited
*/
/******************************************************************************
* @file sec_crypto_ecdh.h
* @brief Header File for curve25519( a state-of-the-art Diffie-Hellman function)
* @version V3.3
* @date 10. June 2022
* @model ecdh
******************************************************************************/
#ifndef _SC_ECDH_H_
#define _SC_ECDH_H_
#include "sec_include_config.h"
#define CONFIG_SEC_CRYPTO_ECC
#ifdef CONFIG_SEC_CRYPTO_ECC
#ifdef __cplusplus
extern "C" {
#endif
#ifdef SEC_LIB_VERSION
#include "drv/ecdh.h"
#include "drv/ecc.h"
#include "sec_crypto_ecc.h"
#else
#include "ecdh.h"
#include "ecc.h"
#include "sec_crypto_ecc.h"
#endif
/**
\brief ecdh calc secret
\param[in] ecc ecc handle to operate.
\param[in] pubkey Pointer to the A(or B) public key.
\param[out] privkey Pointer to the B(or A) private key.
\param[out] out Pointer to the share secret.
\param[out] len length of the share secret.
\return \ref uint32_t.
*/
uint32_t sc_ecdh_calc_secret(sc_ecc_t *ecc, uint8_t privkey[32],
uint8_t pubkey[65], uint8_t out[32],
uint32_t *len, sc_ecc_curve_type type) ;
#ifdef __cplusplus
extern "C" {
#endif
#endif
#endif /* _SC_CURVE15519_H_ */

4
lib/sec_library/include/sec_crypto_errcode.h
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@@ -1,5 +1,5 @@
/*
* Copyright (C) 2019-2021 Alibaba Group Holding Limited
* Copyright (C) 2019-2020 Alibaba Group Holding Limited
*/
#ifndef _SC_ERRCODE_H
@@ -89,4 +89,4 @@
#define CHECK_PARAM CHECK_PARAM_RET
#endif
#endif
#endif

96
lib/sec_library/include/sec_crypto_kdf.h Normal file
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@@ -0,0 +1,96 @@
/*
* Copyright (C) 2019-2020 Alibaba Group Holding Limited
*/
#ifndef __SC_KDF_H__
#define __SC_KDF_H__
#include "sec_crypto_errcode.h"
#include "sec_crypto_aes.h"
#include "sec_crypto_sm4.h"
#include "sec_crypto_mac.h"
#include <stdint.h>
typedef enum {
SC_KDF_DERIVED_DFT_CHALLENGE_EK,
SC_KDF_DERIVED_C910TJTAG_CHALLENGE_EK,
SC_KDF_DERIVED_E902JTAG_CHALLENGE_EK,
SC_KDF_DERIVED_IMAGE_EK,
SC_KDF_DERIVED_SECURE_STORAGE_EK1,
SC_KDF_DERIVED_SECURE_STORAGE_EK2,
SC_KDF_DERIVED_SECURE_STORAGE_EK3,
SC_KDF_DERIVED_SECURE_STORAGE_EK4,
SC_KDF_DERIVED_SECURE_STORAGE_EK5,
SC_KDF_DERIVED_SECURE_STORAGE_EK6,
SC_KDF_DERIVED_SECURE_STORAGE_EK7,
SC_KDF_DERIVED_SECURE_STORAGE_EK8,
SC_KDF_DERIVED_SECURE_STORAGE_EK9,
SC_KDF_DERIVED_SECURE_STORAGE_EK10,
SC_KDF_DERIVED_SECURE_STORAGE_EK11,
SC_KDF_DERIVED_SECURE_STORAGE_EK12,
SC_KDF_DERIVED_SECURE_STORAGE_EK13,
SC_KDF_DERIVED_SECURE_STORAGE_EK14,
SC_KDF_DERIVED_SECURE_STORAGE_EK15,
SC_KDF_DERIVED_SECURE_STORAGE_EK16,
SC_KDF_DERIVED_RPMB_ACCESS_EK,
SC_KDF_DERIVED_MAX,
} sc_kdf_derived_key_t;
typedef enum {
SC_KDF_KEY_TYPE_AES_256,
SC_KDF_KEY_TYPE_AES_192,
SC_KDF_KEY_TYPE_AES_128,
SC_KDF_KEY_TYPE_SM4,
SC_KDF_KEY_TYPE_TDES_192,
SC_KDF_KEY_TYPE_TDES_128,
SC_KDF_KEY_TYPE_DES,
/* for rpmb, str */
/* SC_KDF_KEY_TYPE_HMAC_SHA256,
*/
SC_KDF_KEY_TYPE_MAX,
} sc_kdf_key_type_t;
/**
\brief KDF Ctrl Block
*/
typedef struct {
union {
sc_aes_t *aes;
sc_sm4_t *sm4;
sc_mac_t *mac;
};
sc_kdf_key_type_t type;
} sc_kdf_key_handle_t;
/**
\brief KDF Ctrl Block
*/
typedef struct {
void *priv;
} sc_kdf_t;
/**
\brief kdf initialiez.
\param[in] kdf Handle to operate.
\param[in] idx Device id.
\return error code
*/
uint32_t sc_kdf_init(sc_kdf_t *kdf, uint32_t idx);
/**
\brief kdf uninitialiez.
\param[in] kdf Handle to operate
*/
void sc_kdf_uninit(sc_kdf_t *kdf);
/**
\brief Set key to algorithim engine.
\param[in] handle Handle to cipher.
\param[in] kdf Handle to operate.
\param[in] dkey derived key type.
\return error code
*/
uint32_t sc_kdf_set_key(sc_kdf_t *kdf, sc_kdf_key_handle_t *handle,
sc_kdf_derived_key_t dkey);
#endif

117
lib/sec_library/include/sec_crypto_mac.h Normal file
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@@ -0,0 +1,117 @@
/*
* Copyright (C) 2017-2020 Alibaba Group Holding Limited
*/
/******************************************************************************
* @file seccrypt_mac.h
* @brief Header File for MAC
* @version V1.0
* @date 20. Jul 2020
* @model mac
******************************************************************************/
#ifndef _SC_MAC_H_
#define _SC_MAC_H_
#include "sec_include_config.h"
#include <stdint.h>
#include "sec_crypto_errcode.h"
#include "sec_crypto_sha.h"
#define SC_MAC_KEY_LEN_MAX 64
#define HMAC_SHA1_BLOCK_SIZE 64
#define HMAC_SHA224_BLOCK_SIZE 64
#define HMAC_SM3_BLOCK_SIZE 64
#define HMAC_SHA256_BLOCK_SIZE 64
#define HMAC_MD5_BLOCK_SIZE 64
#define HMAC_SHA384_BLOCK_SIZE 128
#define HMAC_SHA512_BLOCK_SIZE 128
#define HMAC_MAX_BLOCK_SIZE 128
#ifdef __cplusplus
extern "C" {
#endif
typedef struct sc_mac {
sc_sha_t sha;
uint8_t key[HMAC_MAX_BLOCK_SIZE];
sc_sha_mode_t mode;
} sc_mac_t;
#define MAC_CONTEXT_SIZE sizeof(sc_sha_context_t)
typedef struct {
uint8_t ctx[MAC_CONTEXT_SIZE];
} sc_mac_context_t;
/**
\brief Initialize MAC Interface. Initializes the resources needed for the MAC interface
\param[in] mac operate handle.
\param[in] idx index of mac
\return error code \ref uint32_t
*/
uint32_t sc_mac_init(sc_mac_t *mac, uint32_t idx);
/**
\brief De-initialize MAC Interface. stops operation and releases the software resources used by the interface
\param[in] mac mac handle to operate.
\return none
*/
void sc_mac_uninit(sc_mac_t *mac);
/**
\brief MAC set key function.
\param[in] mac mac handle to operate.
\param[in] key Pointer to the mac key.
\param[in] key_len Length of key.
\return error code
*/
uint32_t sc_mac_set_key(sc_mac_t *mac, uint8_t *key, uint32_t key_len);
/**
\brief MAC operation function.
\param[in] mac mac handle to operate.
\param[in] mode sc_sha_mode_t.
\param[in] msg Pointer to the mac input message.
\param[in] msg_len Length of msg.
\param[out] out mac buffer, malloc by caller.
\param[out] out_len, out mac length,
should 32 bytes if HMAC_SHA256 mode.
\return error code
*/
uint32_t sc_mac_calc(sc_mac_t *mac, sc_sha_mode_t mode, uint8_t *msg,
uint32_t msg_len, uint8_t *out, uint32_t *out_len);
/**
\brief MAC start operation function.
\param[in] mac mac handle to operate.
\param[in] context mac context pointer.
\param[in] mode sc_sha_mode_t.
\return error code
*/
uint32_t sc_mac_start(sc_mac_t *mac, sc_mac_context_t *context,
sc_sha_mode_t mode);
/**
\brief MAC start operation function.
\param[in] mac mac handle to operate.
\param[in] context mac context pointer.
\param[in] msg Pointer to the mac input message.
\param[in] msg_len Length of msg.
\return error code
*/
uint32_t sc_mac_update(sc_mac_t *mac, sc_mac_context_t *context, uint8_t *msg,
uint32_t msg_len);
/**
\brief MAC start operation function.
\param[in] mac mac handle to operate.
\param[in] context mac context pointer.
\param[out] out mac buffer, malloc by caller.
\param[out] out_len, out mac length,
\return error code
*/
uint32_t sc_mac_finish(sc_mac_t *mac, sc_mac_context_t *context, uint8_t *out,
uint32_t *out_len);
#ifdef __cplusplus
}
#endif
#endif /* _SC_MAC_H_ */

8
lib/sec_library/include/sec_crypto_rng.h
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@@ -1,5 +1,5 @@
/*
* Copyright (C) 2017-2021 Alibaba Group Holding Limited
* Copyright (C) 2017-2020 Alibaba Group Holding Limited
*/
/******************************************************************************
* @file seccrypt_rng.h
@@ -13,7 +13,7 @@
#include <stdint.h>
#include <sec_crypto_errcode.h>
#include "sec_crypto_errcode.h"
#ifdef __cplusplus
@@ -23,10 +23,10 @@ extern "C" {
/**
\brief Get data from the TRNG engine
\param[out] data Pointer to buffer with data get from TRNG
\param[in] num Number of data items,uinit in uint32
\param[in] num Number of data items in bytes
\return error code
*/
uint32_t sc_rng_get_multi_word(uint32_t *data, uint32_t num);
uint32_t sc_rng_get_multi_byte(uint8_t *data, uint32_t num);
/**
\brief Get data from the TRNG engine

40
lib/sec_library/include/sec_crypto_rsa.h
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@@ -1,5 +1,5 @@
/*
* Copyright (C) 2017-2021 Alibaba Group Holding Limited
* Copyright (C) 2017-2020 Alibaba Group Holding Limited
*/
/******************************************************************************
* @file seccrypt_rsa.h
@@ -10,13 +10,18 @@
******************************************************************************/
#ifndef _SC_RSA_H_
#define _SC_RSA_H_
#include "sec_include_config.h"
#ifdef __cplusplus
extern "C" {
#endif
#ifdef CONFIG_SYSTEM_SECURE
#ifdef SEC_LIB_VERSION
#include "drv/rsa.h"
#else
#include "rsa.h"
#endif
#endif
@@ -27,8 +32,12 @@ extern "C" {
#include <stdint.h>
#include <stdbool.h>
#include <drv/common.h>
#include <sec_crypto_errcode.h>
#ifdef SEC_LIB_VERSION
#include "drv/common.h"
#else
#include "common.h"
#endif
#include "sec_crypto_errcode.h"
//TODO Del this file after updating to sc2.0
@@ -286,6 +295,31 @@ uint32_t sc_rsa_enable_pm(sc_rsa_t *rsa);
*/
void sc_rsa_disable_pm(sc_rsa_t *rsa);
/**
\brief set if checked decrypt error.
\param[in] checked if checked error.
*/
void sc_rsa_set_ignore_decrypt_error(bool checked);
/**
\brief Get publickey by p q prime data
\param[in] rsa rsa handle to operate.
\param[in] context Pointer to the rsa context
\param[in] p Pointer to the prime p
\param[in] p_byte_len Pointer to the prime p byte length
\param[in] q Pointer to the prime q
\param[in] q_byte_len Pointer to the prime q byte length
\param[in] out Pointer to the publickey
*/
uint32_t sc_rsa_get_publickey(sc_rsa_t *rsa, sc_rsa_context_t *context, void *p, uint32_t p_byte_len,
void *q, uint32_t q_byte_len, void *out);
/**
\brief Generation rsa keyparis
\param[in] rsa rsa handle to operate.
\param[in] context Pointer to the rsa context
*/
uint32_t sc_rsa_gen_keypairs(sc_rsa_t *rsa, sc_rsa_context_t *context);
#ifdef __cplusplus
}
#endif

44
lib/sec_library/include/sec_crypto_sha.h
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@@ -1,5 +1,5 @@
/*
* Copyright (C) 2017-2021 Alibaba Group Holding Limited
* Copyright (C) 2017-2020 Alibaba Group Holding Limited
*/
/******************************************************************************
* @file seccrypt_sha.h
@@ -10,17 +10,26 @@
******************************************************************************/
#ifndef _SC_SHA_H_
#define _SC_SHA_H_
#include "sec_include_config.h"
#include <stdint.h>
#ifdef CONFIG_SYSTEM_SECURE
#ifdef SEC_LIB_VERSION
#include "drv/sha.h"
#else
#include "sha.h"
#endif
#include "soc.h"
#endif
#ifdef CONFIG_SEC_CRYPTO_SM3
#ifdef SEC_LIB_VERSION
#include "drv/sm3.h"
#else
#include "sm3.h"
#endif
#endif
#include <sec_crypto_errcode.h>
#include "sec_crypto_errcode.h"
#ifdef CONFIG_SEC_CRYPTO_SHA_SW
@@ -34,13 +43,14 @@ extern "C" {
/*----- SHA Control Codes: Mode -----*/
typedef enum {
SC_SHA_MODE_1 = 1U, ///< SHA_1 mode
SC_SHA_MODE_SHA1 = 1U, ///< SHA_1 mode
SC_SHA_MODE_256, ///< SHA_256 mode
SC_SHA_MODE_224, ///< SHA_224 mode
SC_SHA_MODE_512, ///< SHA_512 mode
SC_SHA_MODE_384, ///< SHA_384 mode
SC_SHA_MODE_512_256, ///< SHA_512_256 mode
SC_SHA_MODE_512_224, ///< SHA_512_224 mode
SC_SHA_MODE_512_224, ///< SHA_512_224 mode
SC_SHA_MODE_MD5, ///< MD5 mode
SC_SM3_MODE,
} sc_sha_mode_t;
@@ -60,6 +70,8 @@ uint8_t ctx[SHA_CONTEXT_SIZE];
#ifdef CONFIG_CSI_V2
csi_sha_context_t ctx;
csi_sm3_context_t sm3ctx;
csi_sha_state_t state;
csi_sm3_state_t sm3state;
#endif
#endif
#if defined(CONFIG_TEE_CA)
@@ -69,7 +81,7 @@ uint8_t ctx[SHA_CONTEXT_SIZE];
sc_mbedtls_sha1_context sha1_ctx;
sc_mbedtls_sha256_context sha2_ctx;
#endif
sc_sha_mode_t mode; ///< sha mode
sc_sha_mode_t mode; ///< sha mode
} sc_sha_context_t;
/****** SHA Event *****/
@@ -166,6 +178,28 @@ uint32_t sc_sha_update_async(sc_sha_t *sha, sc_sha_context_t *context, const voi
*/
uint32_t sc_sha_finish(sc_sha_t *sha, sc_sha_context_t *context, void *output, uint32_t *out_size);
/**
\brief calculate the digest
\param[in] sha sha handle to operate.
\param[in] idx index of sha
\param[in] context Pointer to the sha context \ref sc_sha_context_t
\param[in] mode sha mode \ref sc_sha_mode_t
\param[in] input Pointer to the Source data
\param[in] size the data size
\param[out] output Pointer to the result data
\param[out] out_size Pointer to the result data size(bytes)
\return error code \ref uint32_t
*/
uint32_t sc_sha_digest(sc_sha_t *sha, uint32_t idx, sc_sha_context_t *context, sc_sha_mode_t mode,
const void *input, uint32_t size, void *output, uint32_t out_size);
/**
\brief finish the engine
\param[in] sha sha handle to operate.
\param[in] context Pointer to the sha context \ref sc_sha_context_t
\return error code \ref uint32_t
*/
uint32_t sc_sha_get_state(sc_sha_t *sha,sc_sha_context_t *context);
#ifdef __cplusplus
}
#endif

8
lib/sec_library/include/sec_crypto_sm2.h
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@@ -1,5 +1,5 @@
/*
* Copyright (C) 2017-2021 Alibaba Group Holding Limited
* Copyright (C) 2017-2020 Alibaba Group Holding Limited
*/
/******************************************************************************
* @file sec_crypt_sm2.h
@@ -10,6 +10,7 @@
******************************************************************************/
#ifndef _SC_SM2_H_
#define _SC_SM2_H_
#include "sec_include_config.h"
#ifdef CONFIG_SEC_CRYPTO_SM2
@@ -17,7 +18,12 @@
extern "C" {
#endif
#ifdef SEC_LIB_VERSION
#include "drv/sm2.h"
#else
#include "sm2.h"
#endif
typedef struct {
uint32_t sm2_curve : 1; ///< supports 256bits curve

12
lib/sec_library/include/sec_crypto_sm4.h
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@@ -1,5 +1,5 @@
/*
* Copyright (C) 2017-2021 Alibaba Group Holding Limited
* Copyright (C) 2017-2020 Alibaba Group Holding Limited
*/
/******************************************************************************
* @file sec_crypt_sm4.h
@@ -11,10 +11,14 @@
#ifndef _SC_SM4_H_
#define _SC_SM4_H_
#include "sec_include_config.h"
#ifdef CONFIG_CSI_V2
#ifdef SEC_LIB_VERSION
#include "drv/sm4.h"
#else
#include "sm4.h"
#endif
#endif
#ifdef __cplusplus
@@ -51,7 +55,7 @@ void sc_sm4_uninit(sc_sm4_t *sm4);
\param[in] key Pointer to the key buf
\return error code \ref uint32_t
*/
uint32_t sc_sm4_set_encrypt_key(sc_sm4_t *sm4, uint8_t *key);
uint32_t sc_sm4_set_encrypt_key(sc_sm4_t *sm4, uint8_t *key, csi_sm4_key_bits_t key_len);
/**
\brief Set decrypt key
@@ -59,7 +63,7 @@ uint32_t sc_sm4_set_encrypt_key(sc_sm4_t *sm4, uint8_t *key);
\param[in] key Pointer to the key buf
\return error code \ref uint32_t
*/
uint32_t sc_sm4_set_decrypt_key(sc_sm4_t *sm4, uint8_t *key);
uint32_t sc_sm4_set_decrypt_key(sc_sm4_t *sm4, uint8_t *key, csi_sm4_key_bits_t key_len);
/**
\brief sm4 ecb encrypt

11
lib/sec_library/include/sec_include_config.h Normal file
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@@ -0,0 +1,11 @@
/*
* Copyright (C) 2019-2020 Alibaba Group Holding Limited
*/
#ifndef __SEC_INCLUDE_CONFIG__
#define __SEC_INCLUDE_CONFIG__
#define CONFIG_SYSTEM_SECURE 1
#define CONFIG_CSI_V2 1
#define CONFIG_SEC_CRYPTO_SM2 1
#define CONFIG_SEC_CRYPTO_SM3 1
#endif /* __SEC_INCLUDE_CONFIG__ */

16
lib/sec_library/include/sec_library.h
View File

@@ -1,5 +1,5 @@
/*
* Copyright (C) 2017-2021 Alibaba Group Holding Limited
* Copyright (C) 2017-2020 Alibaba Group Holding Limited
*/
/******************************************************************************
* @file sec_library.h
@@ -12,4 +12,18 @@
#ifndef _SL_H_
#define _SL_H_
#include "sec_crypto_errcode.h"
#include "sec_crypto_common.h"
#include "sec_crypto_aes.h"
#include "sec_crypto_rng.h"
#include "sec_crypto_rsa.h"
#include "sec_crypto_sha.h"
#include "sec_crypto_sm2.h"
#include "sec_crypto_sm4.h"
#include "sec_crypto_kdf.h"
#include "csi_efuse_api.h"
#include "csi_efuse_api.h"
#include "csi_sec_img_verify.h"
/* NOTE add more header */
#endif /* _SL_H_ */

25
lib/sec_library/include/sha.h
View File

@@ -1,5 +1,5 @@
/*
* Copyright (C) 2017-2021 Alibaba Group Holding Limited
* Copyright (C) 2017-2020 Alibaba Group Holding Limited
*/
/******************************************************************************
@@ -13,22 +13,31 @@
#ifndef _DRV_SHA_H_
#define _DRV_SHA_H_
#include <drv/common.h>
#include <drv/dma.h>
#include "common.h"
#ifdef __cplusplus
extern "C" {
#endif
#define HASH_DATAIN_BLOCK_SIZE 64
#define SHA1_DIGEST_OUT_SIZE 20
#define SHA224_DIGEST_OUT_SIZE 28
#define SHA256_DIGEST_OUT_SIZE 32
#define SHA384_DIGEST_OUT_SIZE 48
#define SHA512_DIGEST_OUT_SIZE 64
#define MD5_DIGEST_OUT_SIZE 16
/****** SHA mode ******/
typedef enum {
SHA_MODE_1 = 1U, ///< SHA_1 mode
SHA_MODE_SHA1 = 1U, ///< SHA_1 mode
SHA_MODE_256, ///< SHA_256 mode
SHA_MODE_224, ///< SHA_224 mode
SHA_MODE_512, ///< SHA_512 mode
SHA_MODE_384, ///< SHA_384 mode
SHA_MODE_512_256, ///< SHA_512_256 mode
SHA_MODE_512_224 ///< SHA_512_224 mode
SHA_MODE_512_224, ///< SHA_512_224 mode
SHA_MODE_MD5 ///< MD5 mode
} csi_sha_mode_t;
/****** SHA State ******/
@@ -42,11 +51,16 @@ typedef struct {
uint32_t total[2]; ///< Number of bytes processed
uint32_t state[16]; ///< Intermediate digest state
uint8_t buffer[128]; ///< Data block being processed
uint8_t result[64]; ///< Data block has processed
uint32_t process_len;
uint32_t digest_len;
} csi_sha_context_t;
/****** SHA Event ******/
typedef enum {
SHA_EVENT_COMPLETE = 0U, ///< Calculate completed
SHA_EVENT_UPDATE,
SHA_EVENT_START,
SHA_EVENT_ERROR ///< Calculate error
} csi_sha_event_t;
@@ -56,7 +70,6 @@ struct csi_sha {
csi_dev_t dev; ///< SHA hw-device info
void (*callback)(csi_sha_t *sha, csi_sha_event_t event, void *arg); ///< SHA event callback for user
void *arg; ///< SHA custom designed param passed to evt_cb
csi_dma_ch_t *dma_in; ///< SHA in dma handle param
csi_sha_state_t state; ///< SHA state
void *priv;
};

6
lib/sec_library/include/sm2.h
View File

@@ -1,5 +1,5 @@
/*
* Copyright (C) 2017-2021 Alibaba Group Holding Limited
* Copyright (C) 2017-2020 Alibaba Group Holding Limited
*/
/******************************************************************************
@@ -14,7 +14,7 @@
#define _DRV_SM2_H_
#include <stdint.h>
#include <drv/common.h>
#include "common.h"
#ifdef __cplusplus
extern "C" {
@@ -255,4 +255,4 @@ void csi_sm2_disable_pm(csi_sm2_t *sm2);
extern "C" {
#endif
#endif
#endif

36
lib/sec_library/include/sm3.h
View File

@@ -1,5 +1,5 @@
/*
* Copyright (C) 2017-2021 Alibaba Group Holding Limited
* Copyright (C) 2017-2020 Alibaba Group Holding Limited
*/
/******************************************************************************
@@ -14,17 +14,20 @@
#define _DRV_SM3_H_
#include <stdint.h>
#include <drv/common.h>
#include <drv/dma.h>
#include "common.h"
#ifdef __cplusplus
extern "C" {
#endif
#define SM3_DATAIN_BLOCK_SIZE 64
#define SM3_DIGEST_OUT_SIZE 32
typedef struct {
uint32_t total[2]; ///< Number of bytes processed
uint32_t state[16]; ///< Intermediate digest state
uint8_t buffer[64]; ///< Data block beingprocessed
uint32_t total[2]; ///< Number of bytes processed
uint32_t state[16]; ///< Intermediate digest state
uint8_t buffer[SM3_DATAIN_BLOCK_SIZE]; ///< Data block beingprocessed
uint8_t result[SM3_DIGEST_OUT_SIZE]; ///< Data block has processed
} csi_sm3_context_t;
/****** SM3 State ******/
@@ -36,20 +39,21 @@ typedef struct {
/****** SM3 Event ******/
typedef enum {
SM3_EVENT_COMPLETE = 0U, ///< Calculate completed
SM3_EVENT_ERROR ///< Calculate error
SM3_EVENT_COMPLETE = 0U, ///< Calculate completed
SM3_EVENT_UPDATE,
SM3_EVENT_START,
SM3_EVENT_ERROR ///< Calculate error
} csi_sm3_event_t;
typedef struct csi_sm3_t csi_sm3_t;
struct csi_sm3_t {
csi_dev_t dev; ///< SM3 hw-device info
void (*callback)(csi_sm3_t *sm3, csi_sm3_event_t event,
void *arg); ///< SM3 event callback for user
void * arg; ///< SM3 custom designed param passed to evt_cb
csi_dma_ch_t * dma_in; ///< SM3 in dma handle param
csi_sm3_state_t state; ///< SM3 state
void * priv;
csi_dev_t dev; ///< SM3 hw-device info
void (*callback)(csi_sm3_t *sm3, csi_sm3_event_t event,
void *arg); ///< SM3 event callback for user
void * arg; ///< SM3 custom designed param passed to evt_cb
csi_sm3_state_t state; ///< SM3 state
void * priv;
};
// Function documentation
@@ -152,4 +156,4 @@ void csi_sm3_disable_pm(csi_sm3_t *sm3);
extern "C" {
#endif
#endif //_DRV_SM3_H
#endif //_DRV_SM3_H

35
lib/sec_library/include/sm4.h
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@@ -1,5 +1,5 @@
/*
* Copyright (C) 2017-2021 Alibaba Group Holding Limited
* Copyright (C) 2017-2020 Alibaba Group Holding Limited
*/
/******************************************************************************
@@ -14,18 +14,41 @@
#define _DRV_SM4_H_
#include <stdint.h>
#include <drv/common.h>
#include "common.h"
#ifdef __cplusplus
extern "C" {
#endif
#define SM4_KEY_LEN_BYTES_32 32
#define SM4_KEY_LEN_BYTES_24 24
#define SM4_KEY_LEN_BYTES_16 16
typedef enum {
SM4_KEY_LEN_BITS_128 = 0, /*128 Data bits*/
SM4_KEY_LEN_BITS_256 /*256 Data bits*/
} csi_sm4_key_bits_t;
typedef struct {
uint32_t busy : 1; ///< Calculate busy flag
uint32_t error : 1; ///< Calculate error flag
} csi_sm4_state_t;
typedef struct {
uint32_t key_len_byte;
uint8_t key[32]; ///< Data block being processed
uint32_t sca;
} csi_sm4_context_t;
/**
\brief SM4 Ctrl Block
*/
typedef struct {
csi_dev_t dev;
void * priv;
csi_sm4_state_t state;
csi_sm4_context_t context;
csi_dev_t dev;
void * priv;
uint32_t is_kdf;
} csi_sm4_t;
// Function documentation
@@ -50,7 +73,7 @@ void csi_sm4_uninit(csi_sm4_t *sm4);
\param[in] key Pointer to the key buf
\return error code \ref uint32_t
*/
csi_error_t csi_sm4_set_encrypt_key(csi_sm4_t *sm4, uint8_t *key);
csi_error_t csi_sm4_set_encrypt_key(csi_sm4_t *sm4, uint8_t *key, csi_sm4_key_bits_t key_len);
/**
\brief Set decrypt key
@@ -58,7 +81,7 @@ csi_error_t csi_sm4_set_encrypt_key(csi_sm4_t *sm4, uint8_t *key);
\param[in] key Pointer to the key buf
\return error code \ref uint32_t
*/
csi_error_t csi_sm4_set_decrypt_key(csi_sm4_t *sm4, uint8_t *key);
csi_error_t csi_sm4_set_decrypt_key(csi_sm4_t *sm4, uint8_t *key, csi_sm4_key_bits_t key_len);
/**
\brief sm4 ecb encrypt

484
lib/sec_library/include/soc.h Normal file
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@@ -0,0 +1,484 @@
/*
* Copyright (C) 2017-2020 Alibaba Group Holding Limited
*/
/******************************************************************************
* @file soc.h
* @brief CSI Core Peripheral Access Layer Header File for
* CSKYSOC Device Series
* @version V1.0
* @date 7. April 2020
******************************************************************************/
#ifndef _SOC_H_
#define _SOC_H_
#include <stdint.h>
#include "csi_core.h"
#include "sys_clk.h"
#ifdef __cplusplus
extern "C" {
#endif
#ifndef EHS_VALUE
#define EHS_VALUE 20000000U
#endif
#ifndef ELS_VALUE
#define ELS_VALUE 32768U
#endif
#ifndef IHS_VALUE
#define IHS_VALUE 50000000U
#endif
#ifndef ILS_VALUE
#define ILS_VALUE 32768U
#endif
#define RISCV_CORE_TIM_FREQ 3000000
typedef enum {
Supervisor_Software_IRQn = 1U,
Machine_Software_IRQn = 3U,
Supervisor_Timer_IRQn = 5U,
CORET_IRQn = 7U,
Supervisor_External_IRQn = 9U,
Machine_External_IRQn = 11U,
DW_TIMER0_IRQn = 16U,
DW_TIMER1_IRQn = 17U,
DW_TIMER2_IRQn = 18U,
DW_TIMER3_IRQn = 19U,
DW_TIMER4_IRQn = 20U,
DW_TIMER5_IRQn = 21U,
DW_TIMER6_IRQn = 22U,
DW_TIMER7_IRQn = 23U,
WJ_MBOX_IRQn = 28U,
DW_UART0_IRQn = 36U,
DW_UART1_IRQn = 37U,
DW_UART2_IRQn = 38U,
DW_UART3_IRQn = 39U,
DW_UART4_IRQn = 40U,
DW_UART5_IRQn = 41U,
DW_I2C0_IRQn = 44U,
DW_I2C2_IRQn = 46U,
DW_QSPI0_IRQn = 52U,
DW_QSPI1_IRQn = 53U,
DW_SPI0_IRQn = 54U,
DW_GPIO0_IRQn = 56U,
DW_GPIO1_IRQn = 57U,
DW_GPIO2_IRQn = 58U,
DW_GPIO3_IRQn = 59U,
DW_EMMC_IRQn = 62U,
DW_SD_IRQn = 64U,
DW_USB_IRQn = 68U,
DW_DMA0_IRQn = 27U,
DCD_ISO7816_IRQn = 69U,
DW_DMA1_IRQn = 71U,
DW_DMA2_IRQn = 72U,
DW_DMA3_IRQn = 73U,
WJ_EFUSE_IRQn = 80U,
DW_WDT0_IRQn = 111U,
DW_WDT1_IRQn = 112U,
RB_120SI_AV_IRQn = 121U,
RB_120SII_AV_IRQn = 124U,
RB_120SIII_AV_IRQn = 127U,
RB_150B_AIC_IRQn = 128U,
RB_150B_PKA1_IRQn = 130U,
RB_150B_ERR_IRQn = 132U,
RB_150B_TRNG_IRQn = 133U,
} irqn_type_t;
typedef enum {
WJ_IOCTL_Wakeupn = 29U, /* IOCTOL wakeup */
} wakeupn_type_t;
typedef enum {
WJ_USB_CLK_MANAGERN = 28U,
} clk_manager_type_t;
typedef enum {
PAD_GRP_BASE1,
PAD_UART0_TXD = PAD_GRP_BASE1,
PAD_UART0_RXD,
PAD_QSPI0_SCLK,
PAD_QSPI0_CSN0,
PAD_QSPI0_CSN1,
PAD_QSPI0_D0_MOSI,
PAD_QSPI0_D1_MISO,
PAD_QSPI0_D2_WP,
PAD_QSPI0_D3_HOLD,
PAD_I2C2_SCL,
PAD_I2C2_SDA,
PAD_I2C3_SCL,
PAD_I2C3_SDA,
PAD_GPIO2_13,
PAD_SPI_SCLK,
PAD_SPI_CSN,
PAD_SPI_MOSI,
PAD_SPI_MISO,
PAD_GPIO2_18,
PAD_GPIO2_19,
PAD_GPIO2_20,
PAD_GPIO2_21,
PAD_GPIO2_22,
PAD_GPIO2_23,
PAD_GPIO2_24,
PAD_GPIO2_25,
PAD_SDIO0_WPRTN,
PAD_SDIO0_DETN,
PAD_SDIO1_WPRTN,
PAD_SDIO1_DETN,
PAD_GPIO2_30,
PAD_GPIO2_31,
PAD_GPIO3_0,
PAD_GPIO3_1,
PAD_GPIO3_2,
PAD_GPIO3_3,
PAD_HDMI_SCL,
PAD_HDMI_SDA,
PAD_HDMI_CEC,
PAD_GMAC0_TX_CLK,
PAD_GMAC0_RX_CLK,
PAD_GMAC0_TXEN,
PAD_GMAC0_TXD0,
PAD_GMAC0_TXD1,
PAD_GMAC0_TXD2,
PAD_GMAC0_TXD3,
PAD_GMAC0_RXDV,
PAD_GMAC0_RXD0,
PAD_GMAC0_RXD1,
PAD_GMAC0_RXD2,
PAD_GMAC0_RXD3,
PAD_GMAC0_MDC,
PAD_GMAC0_MDIO,
PAD_GMAC0_COL,
PAD_GMAC0_CRS,
PAD_GRP_BASE2,
PAD_QSPI1_SCLK = PAD_GRP_BASE2,
PAD_QSPI1_CSN0,
PAD_QSPI1_D0_MOSI,
PAD_QSPI1_D1_MISO,
PAD_QSPI1_D2_WP,
PAD_QSPI1_D3_HOLD,
PAD_I2C0_SCL,
PAD_I2C0_SDA,
PAD_I2C1_SCL,
PAD_I2C1_SDA,
PAD_UART1_TXD,
PAD_UART1_RXD,
PAD_UART4_TXD,
PAD_UART4_RXD,
PAD_UART4_CTSN,
PAD_UART4_RTSN,
PAD_UART3_TXD,
PAD_UART3_RXD,
PAD_GPIO0_18,
PAD_GPIO0_19,
PAD_GPIO0_20,
PAD_GPIO0_21,
PAD_GPIO0_22,
PAD_GPIO0_23,
PAD_GPIO0_24,
PAD_GPIO0_25,
PAD_GPIO0_26,
PAD_GPIO0_27,
PAD_GPIO0_28,
PAD_GPIO0_29,
PAD_GPIO0_30,
PAD_GPIO0_31,
PAD_GPIO1_0,
PAD_GPIO1_1,
PAD_GPIO1_2,
PAD_GPIO1_3,
PAD_GPIO1_4,
PAD_GPIO1_5,
PAD_GPIO1_6,
PAD_GPIO1_7,
PAD_GPIO1_8,
PAD_GPIO1_9,
PAD_GPIO1_10,
PAD_GPIO1_11,
PAD_GPIO1_12,
PAD_GPIO1_13,
PAD_GPIO1_14,
PAD_GPIO1_15,
PAD_GPIO1_16,
PAD_CLK_OUT_0,
PAD_CLK_OUT_1,
PAD_CLK_OUT_2,
PAD_CLK_OUT_3,
PAD_GPIO1_21,
PAD_GPIO1_22,
PAD_GPIO1_23,
PAD_GPIO1_24,
PAD_GPIO1_25,
PAD_GPIO1_26,
PAD_GPIO1_27,
PAD_GPIO1_28,
PAD_GPIO1_29,
PAD_GPIO1_30,
} pin_name_t;
typedef enum {
PAD_UART0_TXD_ALT_TXD =0,
PAD_UART0_TXD_ALT_GPIO2_0 =3,
PAD_UART0_RXD_ALT_RXD =0,
PAD_UART0_RXD_ALT_GPIO2_1 =3,
PAD_QSPI0_SCLK_ALT_QSPI0_SCK= 0,
PAD_QSPI0_SCLK_ALT_PWM0 = 1,
PAD_QSPI0_SCLK_ALT_I2S_SDA0 = 2,
PAD_QSPI0_SCLK_ALT_GPIO2_2 = 3,
PAD_QSPI0_CSN0_ALT_QSPI0_CSN0=0,
PAD_QSPI0_CSN0_ALT_PWM1 =1,
PAD_QSPI0_CSN0_ALT_I2S_SDA1 =2,
PAD_QSPI0_CSN0_ALT_GPIO2_3 =3,
PAD_QSPI0_CSN1_ALT_QSPI0_CSN1=0,
PAD_QSPI0_CSN1_ALT_PWM2 =1,
PAD_QSPI0_CSN1_ALT_I2S_SDA2 =2,
PAD_QSPI0_CSN1_ALT_GPIO2_4 =3,
PAD_QSPI0_D0_MOSI_ALT_QSPI0_MOSI=0,
PAD_QSPI0_D0_MOSI_ALT_PWM3 =1,
PAD_QSPI0_D0_MOSI_ALT_I2S_SDA3 =2,
PAD_QSPI0_D0_MOSI_ALT_GPIO2_5 =3,
PAD_QSPI0_D1_MISO_ALT_QSPI0_MISO=0,
PAD_QSPI0_D1_MISO_ALT_QSPI0_PWM4=1,
PAD_QSPI0_D1_MISO_ALT_I2S_MCLK =2,
PAD_QSPI0_D1_MISO_ALT_GPIO2_6 =3,
PAD_QSPI0_D2_WP_ALT_QSPI0_WP =0,
PAD_QSPI0_D2_WP_ALT_PWM5 =1,
PAD_QSPI0_D2_WP_ALT_I2S_SCK =2,
PAD_QSPI0_D2_WP_ALT_GIOP2_7 =3,
PAD_QSPI0_D3_HOLD_ALT_QSPI0_HOLD=0,
PAD_QSPI0_D3_HOLD_ALT_I2S_WS =2,
PAD_QSPI0_D3_HOLD_ALT_GPIO2_8 =3,
PAD_UART1_TXD_ALT_TXD =0,
PAD_UART1_TXD_ALT_GPIO0_10 =3,
PAD_UART1_RXD_ALT_RXD =0,
PAD_UART1_RXD_ALT_GPIO011 =3,
PIN_FUNC_GPIO = 3U,
} pin_func_t;
#define CONFIG_GPIO_NUM 3
#define CONFIG_IRQ_NUM 112
#define CONFIG_DMA_NUM 1
#define WJ_EFUSE_BASE 0xFFFF210000UL
#define WJ_EFUSE_SIZE 0x10000U
#define DW_USB_BASE 0xFFE7040000UL
#define DW_USB_SIZE 0x10000U
#define DW_TIMER0_BASE 0xFFEFC32000UL
#define DW_TIMER0_SIZE 0x14U
#define DW_TIMER1_BASE (DW_TIMER0_BASE+DW_TIMER0_SIZE)
#define DW_TIMER1_SIZE DW_TIMER0_SIZE
#define DW_TIMER2_BASE 0xFFFFC33000UL
#define DW_TIMER2_SIZE DW_TIMER1_SIZE
#define DW_TIMER3_BASE (DW_TIMER2_BASE+DW_TIMER2_SIZE)
#define DW_TIMER3_SIZE DW_TIMER2_SIZE
#define DW_UART0_BASE 0xFFE7014000UL
#define DW_UART0_SIZE 0x4000U
#define DW_UART1_BASE 0xFFE7F00000UL
#define DW_UART1_SIZE 0x4000U
#define DW_UART2_BASE 0xFFEC010000UL
#define DW_UART2_SIZE 0x4000U
#define DW_UART3_BASE 0xFFE7F04000UL
#define DW_UART3_SIZE 0x4000U
#define DW_UART4_BASE 0xFFF7F08000UL
#define DW_UART4_SIZE 0x4000U
#define DW_UART5_BASE 0xFFF7F0C000UL
#define DW_UART5_SIZE 0x4000U
#define DW_GPIO0_BASE 0xFFEC005000UL
#define DW_GPIO0_SIZE 0x1000U
#define DW_GPIO1_BASE 0xFFEC006000UL
#define DW_GPIO1_SIZE 0x1000U
#define DW_GPIO2_BASE 0xFFE7F34000UL
#define DW_GPIO2_SIZE 0x4000U
#define DW_GPIO3_BASE 0xFFE7F38000UL
#define DW_GPIO3_SIZE 0x4000U
#define DW_WDT_BASE 0xFFEFC30000UL
#define DW_WDT_BASE_SZIE 0x1000U
#define DW_DMA_BASE 0xFFEFC00000UL
#define DW_DMA_BASE_SZIE 0x4000U
#define WJ_IOC_BASE1 0xFFEC007000UL
#define WJ_IOC_SIZE 0x1000U
#define WJ_IOC_BASE2 0xFFE7F3C000UL
#define WJ_IOC_SIZE 0x1000U
#define WJ_CPR_BASE 0xFFCB000000UL
#define WJ_CPR_BASE_SIZE 0x1000000U
#define DW_SPI0_BASE 0xFFF700C000UL
#define DW_SPI0_BASE_SIZE 0x10000U
#define DW_QSPI0_BASE 0xFFEA000000UL
#define DW_QSPI0_BASE_SIZE 0x10000U
#define DW_QSPI1_BASE 0xFFE8000000UL
#define DW_QSPI1_BASE_SIZE 0x10000U
#define DW_I2C0_BASE 0xFFE701C000UL
#define DW_I2C0_BASE_SIZE 0x4000U
#define DW_I2C1_BASE 0xFFE7F24000UL
#define DW_I2C1_BASE_SIZE 0x4000U
#define DW_I2C2_BASE 0xFFEC00C000UL
#define DW_I2C2_BASE_SIZE 0x4000U
#define DW_I2C3_BASE 0xFFFC010000UL
#define DW_I2C3_BASE_SIZE 0x4000U
#define DW_I2C4_BASE 0xFFE7F28000UL
#define DW_I2C4_BASE_SIZE 0x4000U
#define DW_I2C5_BASE 0xFFE7F2C000UL
#define DW_I2C5_BASE_SIZE 0x4000U
#define WJ_MBOX_BASE 0xFFFFC38000UL
#define WJ_MBOX_SIZE 0x1000U
#define WJ_MBOX1_BASE 0xFFFFC48000UL
#define WJ_MBOX1_SIZE 0x1000U
#define DW_EMMC_BASE 0xFFE7080000UL
#define DW_EMMC_SIZE 0x1000U
#define DW_SD_BASE 0xFFE7090000UL
#define DW_SD_SIZE 0x1000U
#define DCD_ISO7816_BASE 0xFFF7F30000ULL
#define DCD_ISO7816_SIZE 0x4000UL
#define RB_RNG_BASE 0xFFFF300000UL
#define RB_RNG_SIZE 0x10000U
#define RB_EIP150B_BASE 0xFFFF300000UL
#define RB_EIP150B_SIZE 0x10000U
#define RB_EIP28_BASE (RB_EIP150B_BASE + 0x4000)
#define RB_EIP28_SIZE 0x3FFCU
#define RB_EIP120SI_BASE 0xFFFF310000UL
#define RB_EIP120SI_SIZE 0x10000U
#define RB_EIP120SII_BASE 0xFFFF320000UL
#define RB_EIP120SII_SIZE 0x10000U
#define RB_EIP120SIII_BASE 0xFFFF330000UL
#define RB_EIP120SIII_SIZE 0x10000U
#define TEE_SYS_BASE 0xFFFF200000UL
#define TEE_SYS_SIZE 0x10000U
#define PLIC_BASE 0xFFD8000000ULL
#define WJ_AON_SYSRST_GEN_BASE 0xFFFFF44000UL
#define WJ_AON_SYSRST_GEN_SIZE 0x2000U
#define KEYRAM_BASE 0xFFFF260000UL
#define KEYRAM_SIZE 0x10000U
#define TEE_SYS_BASE 0xFFFF200000UL
#define TEE_SYS_SIZE 0x10000U
#define TEE_SYS_EFUSE_LC_PRELD_OFF 0x64
#define TEE_SYS_EFUSE_LC_READ_OFF 0x68
#define TEE_SYS_EFUSE_DBG_KEY1_OFF 0x70
#define IOPMP_EIP120I_BASE 0xFFFF220000UL
#define IOPMP_EIP120I_SIZE 0x10000
#define IOPMP_EIP120II_BASE 0xFFFF230000UL
#define IOPMP_EIP120II_SIZE 0x10000
#define IOPMP_EIP120III_BASE 0xFFFF240000UL
#define IOPMP_EIP120III_SIZE 0x10000
#define IOPMP_TEE_DMAC_BASE 0xFFFF250000UL
#define IOPMP_TEE_DMAC_SIZE 0x10000
#define IOPMP_EMMC_BASE 0xFFFC028000UL
#define IOPMP_EMMC_SIZE 0x1000
#define IOPMP_SDIO0_BASE 0xFFFC029000UL
#define IOPMP_SDIO0_SIZE 0x1000
#define IOPMP_SDIO1_BASE 0xFFFC02a000UL
#define IOPMP_SDIO1_SIZE 0x1000
#define CONFIG_MAILBOX_CHANNEL_NUM 4U
#define CONFIG_RTC_FAMILY_D
#define CONFIG_DW_AXI_DMA_8CH_NUM_CHANNELS
#define SOC_OM_ADDRBASE 0xFFEF018010
#define SOC_OSC_BOOT_ADDRBASE 0xFFEF010314
#define SOC_INTERNAL_SRAM_BASEADDR 0xFFE0000000
#define SOC_INTERNAL_SRAM_SIZE (1536 * 1024) //1.5MB
#define SOC_BROM_BASE_ADDRESS 0xFFFFD00000
#define CONFIG_OTP_BASE_ADDR 0 // FIXME:
#define CONFIG_OTP_BANK_SIZE (8 * 1024)
#define AO_SYS_REG_BASE 0xFFFFF48000UL
#define AO_SYS_REG_SIZE 0x2000U
#define SPIFLASH_BASE (0x18000000UL)
#define bootsel() \
({ unsigned int __v = (*(volatile uint32_t *) (0xFFEF018010)); __v&0x7; })
#define osc_bootsel() \
({ unsigned int __v = (*(volatile uint32_t *) (0xFFEF010314)); __v&0x1; })
#define FULLMASK_APTEECLK_ADDRBASE 0xFFFF011000
#define FULLMASK_TEE_PLL_CFG0_OFF 0x60
#define FULLMASK_TEE_PLL_CFG1_OFF 0x64
#define FULLMASK_TEE_PLL_CFG3_OFF 0x6c
#define FULLMASK_PLL_STS_OFF 0x80
#define FULLMASK_TEESYS_CLK_TEECFG_OFF 0x1cc
#define FULLMASK_TEESYS_HCLK_SWITCH_SEL (0x2000U)
#define FULLMASK_PLL_STS_TEE_PLL_LOCK (0x400U)
#define FULLMASK_TEE_PLL_LOCK_TIMEOUT (0x3U) //unit: 10us
#define FULLMASK_TEE_PLL_CFG3_CALLOCK_CNT_EN (0x400)
#define FULLMASK_TEE_PLL_CFG3_DSKEWCAL_PULSE (0x200)
#define FULLMASK_TEE_PLL_CFG3_DSKEWCAL_SWEN (0x100)
#define FULLMASK_TEE_PLL_CFG3_DSKEWCAL_RDY (0x80)
#define FULLMASK_TEE_PLL_DSKEWCAL_RDY_TIMEOUT (200U) //unit: 10us
#define FULLMASK_TEE_PLL_CFG1_PWR_DOWN 0x21000000
#define FULLMASK_TEE_PLL_CFG1_PWR_ON 0x01000000
#define FULLMASK_TEE_PLL_CFG0_792M 0x01306301
#define FULLMASK_AONSYSREG_ADDRBASE 0xFFFFF48000
#define FULLMASK_AONSYSREG_PLL_DSKEW_LOCK_OFF 0x22c
#define FULLMASK_AONSYSREG_PLL_DSKEW_BYPASS (0x2U)
#define FULLMASK_AONSYSREG_RC_READY_OFF 0x7c
#define FULLMASK_AONSYSREG_RC_READY (0x1U)
#define FULLMASK_RC_READY_TIMEOUT (2U) //unit: 10us
#define FULLMASK_AONSYSREG_RC_OFF 0x74
#define FULLMASK_AONSYSREG_RC_VAL_POS 0
#define FULLMASK_AONSYSREG_RC_VAL_MSK 0xFFF
#ifdef __cplusplus
}
#endif
#endif /* _SOC_H_ */

211
lib/sec_library/include/sys_clk.h Normal file
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@@ -0,0 +1,211 @@
/*
* Copyright (C) 2017-2020 Alibaba Group Holding Limited
*/
/******************************************************************************
* @file sys_clk.h
* @brief header file for setting system frequency.
* @version V1.0
* @date 9. April 2020
******************************************************************************/
#ifndef _SYS_CLK_H_
#define _SYS_CLK_H_
#include <stdint.h>
#ifdef SEC_LIB_VERSION
#include "drv/common.h"
#else
#include "common.h"
#endif
#ifdef __cplusplus
extern "C" {
#endif
typedef enum {
IHS_CLK = 0U, /* internal high speed clock */
EHS_CLK, /* external high speed clock */
ILS_CLK, /* internal low speed clock */
ELS_CLK, /* external low speed clock */
PLL_CLK /* PLL clock */
} clk_src_t;
typedef enum {
CPU_300MHZ = 300000000U,
CPU_288MHZ = 288000000U,
CPU_276MHZ = 276000000U,
CPU_270MHZ = 270000000U,
CPU_264MHZ = 264000000U,
CPU_252MHZ = 252000000U,
CPU_245_76MHZ = 245760000U,
CPU_240MHZ = 240000000U,
CPU_228MHZ = 228000000U,
CPU_216MHZ = 216000000U,
CPU_204MHZ = 204000000U,
CPU_192MHZ = 192000000U,
CPU_180MHZ = 180000000U,
CPU_168MHZ = 168000000U,
CPU_156MHZ = 156000000U,
CPU_144MHZ = 144000000U,
CPU_135MHZ = 135000000U,
CPU_132MHZ = 132000000U,
CPU_120MHZ = 120000000U,
CPU_108MHZ = 108000000U,
CPU_96MHZ = 96000000U,
CPU_84MHZ = 84000000U,
CPU_72MHZ = 72000000U,
CPU_60MHZ = 60000000U,
CPU_48MHZ = 48000000U,
CPU_36MHZ = 36000000U,
CPU_30MHZ = 30000000U,
CPU_24MHZ = 24000000U,
CPU_20MHZ = 20000000U,
CPU_10MHZ = 10000000U,
} sys_freq_t;
/* pllclkout : ( pllclkin / 2)*( FN + Frac/4096 ) */
typedef struct {
uint32_t pll_is_used; /* pll is used */
uint32_t pll_source; /* select pll input source clock */
uint32_t pll_src_clk_divider; /* ratio between pll_srcclk clock and pll_clkin clock */
uint32_t fn; /* integer value of frequency division */
uint32_t frac; /* decimal value of frequency division */
} pll_config_t;
typedef struct {
uint32_t system_clk; /* system clock */
// pll_config_t pll_config; /* pll config struct */
uint32_t sys_clk_source; /* select sysclk source clock */
uint32_t rtc_clk_source; /* select rtcclk source clock */
uint32_t cpu_clk_divider; /* ratio between fs_mclk clock and mclk clock */
uint32_t sys_clk_divider; /* ratio between fs_mclk clock and mclk clock */
uint32_t ahb_clk_divider; /* ratio between mclk clock and ahb clock */
uint32_t apb_clk_divider; /* ratio between mclk clock and apb clock */
uint32_t uart_clk_divider; /* ratio between mclk clock and uart clock */
uint32_t audio_clk_divider; /* ratio between mclk clock and audio clock */
uint32_t vad_clk_divider; /* ratio between mclk clock and vad clock */
} system_clk_config_t;
typedef enum {
CLK_DIV1 = 0U,
CLK_DIV2,
CLK_DIV3,
CLK_DIV4,
CLK_DIV5,
CLK_DIV6,
CLK_DIV7,
CLK_DIV8,
CLK_DIV9,
CLK_DIV10,
CLK_DIV11,
CLK_DIV12,
CLK_DIV13,
CLK_DIV14,
CLK_DIV15,
CLK_DIV16
} apb_div_t;
typedef enum {
PLL_FN_18 = 0U,
PLL_FN_19,
PLL_FN_20,
PLL_FN_21,
PLL_FN_22,
PLL_FN_23,
PLL_FN_24,
PLL_FN_25,
PLL_FN_26,
PLL_FN_27,
PLL_FN_28,
PLL_FN_29,
PLL_FN_30,
PLL_FN_31,
PLL_FN_32,
PLL_FN_33,
PLL_FN_34,
PLL_FN_35,
PLL_FN_36,
PLL_FN_37,
PLL_FN_38,
PLL_FN_39,
PLL_FN_40,
PLL_FN_41,
PLL_FN_42,
PLL_FN_43,
PLL_FN_44,
PLL_FN_45,
PLL_FN_46,
PLL_FN_47,
PLL_FN_48,
PLL_FN_49
} pll_fn_t;
typedef enum {
TIM0_CLK = 0U,
TIM1_CLK,
RTC0_CLK,
WDT_CLK,
SPI0_CLK,
UART0_CLK,
IIC0_CLK,
PWM_CLK,
QSPI0_CLK,
PWMR_CLK,
EFUSE_CLK,
I2S0_CLK,
I2S1_CLK,
GPIO0_CLK,
TIM2_CLK = 32U,
TIM3_CLK,
SPI1_CLK,
UART1_CLK,
I2S567_CLK,
ADC_CLK,
ETB_CLK,
I2S2_CLK,
I2S3_CLK,
IOC_CLK,
CODEC_CLK
} clk_module_t;
/**
\brief Set the system clock according to the parameter
\param[in] config system clock config.
\return error code
*/
csi_error_t soc_sysclk_config(system_clk_config_t *config);
/**
\brief Set iic reset
\param[in] idx iic idx.
\return Null
*/
void soc_reset_iic(uint32_t idx);
#ifdef __cplusplus
}
#endif
#endif /* _SYS_CLK_H_ */

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lib/sec_library/libsec_library.a
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