From 2674ac70e4368456c9dadf92252fcfa40c8cf5f3 Mon Sep 17 00:00:00 2001 From: thead_admin Date: Fri, 26 Apr 2024 03:07:14 +0000 Subject: [PATCH] Linux_SDK_V1.5.4 Signed-off-by: thead_admin --- arch/riscv/cpu/c9xx/dram.c | 6 +- arch/riscv/cpu/cpu.c | 9 + arch/riscv/cpu/start.S | 28 +- arch/riscv/dts/light-a-val.dts | 441 +++++++ arch/riscv/dts/light-b-product.dts | 359 ++++++ arch/riscv/dts/light-lpi4a-laptop.dts | 1 + arch/riscv/dts/light-lpi4a.dts | 402 +++++- board/thead/light-c910/Kconfig | 8 +- board/thead/light-c910/Makefile | 2 + board/thead/light-c910/board.c | 146 ++- board/thead/light-c910/clock_config.c | 3 +- board/thead/light-c910/ddr.c | 14 + board/thead/light-c910/light.c | 216 +++- board/thead/light-c910/lpddr-regu/ddr_regu.c | 2 +- board/thead/light-c910/lpddr-regu/ddr_regu.h | 2 +- .../lpddr4/include/aonsys_reg_define.h | 218 ++++ .../lpddr4/include/aonsys_rstget_reg_define.h | 90 ++ .../light-c910/lpddr4/include/common_lib.h | 2 + .../lpddr4/include/ddr_common_func.h | 7 + .../light-c910/lpddr4/include/ddr_retention.h | 35 + .../light-c910/lpddr4/src/ddr_common_func.c | 571 +++++++-- .../light-c910/lpddr4/src/ddr_retention.c | 1076 +++++++++++++++++ .../thead/light-c910/lpddr4/src/lpddr4_init.c | 996 +-------------- board/thead/light-c910/spl.c | 131 +- cmd/net.c | 19 + common/image-fdt.c | 4 +- configs/light_a_val_android_defconfig | 1 + configs/light_a_val_defconfig | 8 +- configs/light_a_val_sec_defconfig | 8 +- configs/light_ant_ref_android_defconfig | 1 + configs/light_ant_ref_defconfig | 1 + configs/light_ant_ref_sec_defconfig | 1 + configs/light_b_product_android_defconfig | 1 + configs/light_b_product_defconfig | 3 + configs/light_b_product_sec_defconfig | 3 + configs/light_beagle_android_defconfig | 3 +- configs/light_lpi4a_android_defconfig | 1 + configs/light_lpi4a_defconfig | 12 +- configs/light_lpi4a_sec_defconfig | 12 +- drivers/fastboot/fb_command.c | 20 +- drivers/misc/Kconfig | 6 + drivers/misc/Makefile | 1 + drivers/misc/light_regu.c | 975 +++++++++++++++ drivers/misc/light_regu.h | 229 ++++ drivers/misc/misc-uclass.c | 1 - drivers/mmc/sdhci.c | 4 +- drivers/video/Kconfig | 9 +- drivers/video/Makefile | 1 + drivers/video/jadard-jd9365da-h3.c | 238 ++++ include/configs/light-c910.h | 11 +- include/dt-bindings/pmic/light_pmic.h | 55 + 51 files changed, 5272 insertions(+), 1121 deletions(-) create mode 100644 board/thead/light-c910/lpddr4/include/aonsys_reg_define.h create mode 100644 board/thead/light-c910/lpddr4/include/aonsys_rstget_reg_define.h create mode 100644 board/thead/light-c910/lpddr4/include/ddr_retention.h create mode 100644 board/thead/light-c910/lpddr4/src/ddr_retention.c create mode 100644 drivers/misc/light_regu.c create mode 100644 drivers/misc/light_regu.h create mode 100644 drivers/video/jadard-jd9365da-h3.c create mode 100644 include/dt-bindings/pmic/light_pmic.h diff --git a/arch/riscv/cpu/c9xx/dram.c b/arch/riscv/cpu/c9xx/dram.c index e725d306..7a404430 100644 --- a/arch/riscv/cpu/c9xx/dram.c +++ b/arch/riscv/cpu/c9xx/dram.c @@ -14,9 +14,9 @@ DECLARE_GLOBAL_DATA_PTR; int dram_init(void) { #ifdef CONFIG_DDR_BOARD_CONFIG -extern unsigned long get_ddr_density(void); - // update ram_size from board config info - gd->ram_size = get_ddr_density(); + // already setup during ddr initial flow + gd->bd->bi_memsize = gd->ram_size; + gd->bd->bi_memstart = CONFIG_SYS_SDRAM_BASE; return 0; #else return fdtdec_setup_mem_size_base(); diff --git a/arch/riscv/cpu/cpu.c b/arch/riscv/cpu/cpu.c index e457f6ac..501aa72d 100644 --- a/arch/riscv/cpu/cpu.c +++ b/arch/riscv/cpu/cpu.c @@ -27,6 +27,15 @@ u32 hart_lottery __attribute__((section(".data"))) = 0; u32 available_harts_lock = 1; #endif +void arch_setup_gd(struct global_data *gd_ptr) +{ + // sync specific info from spl + gd_ptr->ram_size = gd->ram_size; + + // setup gd ptr + gd = gd_ptr; +} + static inline bool supports_extension(char ext) { #ifdef CONFIG_CPU diff --git a/arch/riscv/cpu/start.S b/arch/riscv/cpu/start.S index a85e1b9c..590874b7 100644 --- a/arch/riscv/cpu/start.S +++ b/arch/riscv/cpu/start.S @@ -104,12 +104,6 @@ call_board_init_f_0: mv a0, sp jal board_init_f_alloc_reserve - /* - * Set global data pointer here for all harts, uninitialized at this - * point. - */ - mv gp, a0 - /* setup stack */ #ifdef CONFIG_SMP /* tp: hart id */ @@ -127,16 +121,34 @@ call_board_init_f_0: la t0, hart_lottery li s2, 1 amoswap.w s2, t1, 0(t0) - bnez s2, wait_for_gd_init + beqz s2, call_board_init_f_1 + + /* + * Set global data pointer here for secondary harts, uninitialized at this + * point. + */ + mv gp, a0 + + jal wait_for_gd_init #else - bnez tp, secondary_hart_loop + beqz tp, call_board_init_f_1 + + /* + * Set global data pointer here for secondary harts, uninitialized at this + * point. + */ + mv gp, a0 + + jal secondary_hart_loop #endif +call_board_init_f_1: #ifdef CONFIG_OF_PRIOR_STAGE la t0, prior_stage_fdt_address SREG s1, 0(t0) #endif + /* Set global data pointer here for main hart */ jal board_init_f_init_reserve /* save the boot hart id to global_data */ diff --git a/arch/riscv/dts/light-a-val.dts b/arch/riscv/dts/light-a-val.dts index 96ca43a6..a90a4917 100644 --- a/arch/riscv/dts/light-a-val.dts +++ b/arch/riscv/dts/light-a-val.dts @@ -1,4 +1,7 @@ /dts-v1/; + +#include + / { model = "T-HEAD c910 light"; compatible = "thead,c910_light"; @@ -359,6 +362,20 @@ }; }; + usb: usb@ffe7040000 { + compatible = "snps,dwc3"; + reg = <0xff 0xe7040000 0x0 0x10000>; + interrupts = <68>; + reg-shift = <2>; + reg-io-width = <4>; + maximum-speed = "super-speed"; + dr_mode = "host"; + dma-mask = <0xf 0xffffffff>; + snps,usb3_lpm_capable; + snps,usb_sofitpsync; + status = "okay"; + }; + pwm: pwm@ffec01c000 { compatible = "thead,pwm-light"; reg = <0xff 0xec01c000 0x0 0x4000>; @@ -479,6 +496,430 @@ lcd-en-gpios = <&pcal6408ahk_a 2 0>; /* active high */ lcd-bias-en-gpios = <&pcal6408ahk_a 4 0>;/* active high */ }; + + aon { + compatible = "thead,light-aon"; + status = "okay"; + + wakeup-by-gpio-on; + wakeup-by-rtc-on; + + pd: light-aon-pd { + compatible = "thead,light-aon-pd"; + #power-domain-cells = <1>; + }; + + light-regu-reg { + compatible = "thead,light-dialog-pmic"; + status = "okay"; + + + + soc_dvdd18_aon_reg: soc_dvdd18_aon { + regulator-name = "soc_dvdd18_aon"; + regulator-boot-on; + regulator-always-on; + }; + + soc_avdd33_usb3_reg: soc_avdd33_usb3 { + regulator-name = "soc_avdd33_usb3"; + regulator-boot-on; + regulator-always-on; + }; + + soc_dvdd08_aon_reg: soc_dvdd08_aon { + regulator-name = "soc_dvdd08_aon"; + regulator-boot-on; + regulator-always-on; + }; + + soc_apcpu_dvdd_dvddm_reg: soc_apcpu_dvdd_dvddm { + regulator-name = "soc_apcpu_dvdd_dvddm"; + regulator-min-microvolt = <300000>; + regulator-max-microvolt = <1570000>; + regulator-boot-on; + regulator-always-on; + }; + + soc_dvdd08_ddr_reg: soc_dvdd08_ddr { + regulator-name = "soc_dvdd08_ddr"; + regulator-boot-on; + regulator-always-on; + }; + + soc_vdd_ddr_1v8_reg: soc_vdd_ddr_1v8 { + regulator-name = "soc_vdd_ddr_1v8"; + regulator-boot-on; + regulator-always-on; + }; + + soc_vdd_ddr_1v1_reg: soc_vdd_ddr_1v1 { + regulator-name = "soc_vdd_ddr_1v1"; + regulator-boot-on; + regulator-always-on; + }; + + soc_vdd_ddr_0v6_reg: soc_vdd_ddr_0v6 { + regulator-name = "soc_vdd_ddr_0v6"; + regulator-boot-on; + regulator-always-on; + }; + + soc_dvdd18_ap_reg: soc_dvdd18_ap { + regulator-name = "soc_dvdd18_ap"; + regulator-boot-on; + regulator-always-on; + }; + + soc_dvdd08_ap_reg: soc_dvdd08_ap { + regulator-name = "soc_dvdd08_ap"; + regulator-boot-on; + regulator-always-on; + }; + + soc_avdd08_mipi_hdmi_reg: soc_avdd08_mipi_hdmi { + regulator-name = "soc_avdd08_mipi_hdmi"; + regulator-boot-on; + regulator-always-on; + }; + + soc_avdd18_mipi_hdmi_reg: soc_avdd18_mipi_hdmi { + regulator-name = "soc_avdd18_mipi_hdmi"; + regulator-boot-on; + regulator-always-on; + }; + + soc_dvdd33_emmc_reg: soc_dvdd33_emmc { + regulator-name = "soc_dvdd33_emmc"; + regulator-boot-on; + regulator-always-on; + }; + + soc_dvdd18_emmc_reg: soc_dvdd18_emmc { + regulator-name = "soc_vdd18_emmc"; + regulator-boot-on; + regulator-always-on; + }; + soc_dovdd18_scan_reg: soc_dovdd18_scan { + regulator-name = "soc_dovdd18_scan"; + regulator-min-microvolt = <900000>; + regulator-max-microvolt = <3600000>; + }; + soc_vext_2v8_reg: soc_vext_2v8 { + regulator-name = "soc_vext_2v8"; + regulator-boot-on; + regulator-always-on; + }; + soc_dvdd12_scan_reg: soc_dvdd12_scan { + regulator-name = "soc_dvdd12_scan"; + regulator-min-microvolt = <900000>; + regulator-max-microvolt = <3600000>; + }; + soc_avdd28_scan_en_reg: soc_avdd28_scan_en { + regulator-name = "soc_avdd28_scan_en"; + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <2800000>; + }; + soc_avdd28_rgb_reg: soc_avdd28_rgb { + regulator-name = "soc_avdd28_rgb"; + regulator-min-microvolt = <2200000>; + regulator-max-microvolt = <3475000>; + regulator-boot-on; + regulator-always-on; + }; + soc_dovdd18_rgb_reg: soc_dovdd18_rgb { + regulator-name = "soc_dovdd18_rgb"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <3600000>; + regulator-boot-on; + regulator-always-on; + }; + soc_dvdd12_rgb_reg: soc_dvdd12_rgb { + regulator-name = "soc_dvdd12_rgb"; + regulator-min-microvolt = <400000>; + regulator-max-microvolt = <1675000>; + regulator-boot-on; + regulator-always-on; + }; + soc_avdd25_ir_reg: soc_avdd25_ir { + regulator-name = "soc_avdd25_ir"; + regulator-min-microvolt = <2200000>; + regulator-max-microvolt = <3475000>; + regulator-boot-on; + regulator-always-on; + }; + soc_dovdd18_ir_reg: soc_dovdd18_ir { + regulator-name = "soc_dovdd18_ir"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <3600000>; + regulator-boot-on; + regulator-always-on; + }; + soc_dvdd12_ir_reg: soc_dvdd12_ir { + regulator-name = "soc_dvdd12_ir"; + regulator-min-microvolt = <400000>; + regulator-max-microvolt = <1675000>; + regulator-boot-on; + regulator-always-on; + }; + }; + + aon_pmic_config { + compatible = "thead,light-pmic-conf"; + status = "okay"; + #address-cells = <1>; + #size-cells = <0>; + pmic_dev_0: pmic-dev@0 { + pmic-name = "dialog,da9063,v1"; + pmic-addr = <0x5a 0x5b>; + pmic_wdt_on; + errio_gpio = <0 14 3>; + status = "okay"; + }; + + pmic_dev_1: pmic-dev@1 { + pmic-name = "dialog,da9121,v1"; + pmic-addr = <0x68>; + status = "okay"; + }; + + pmic_dev_2: pmic-dev@2 { + pmic-name = "dialog,slg51000,v1"; + pmic-addr = <0x75>; + status = "okay"; + }; + + regu_config_0 { + reg_info = <&soc_dvdd18_aon_reg>; + status = "okay"; + regu_id@0 { + pmic_dev = <&pmic_dev_0 DA9063_ID_LDO3>; + }; + }; + + regu_config_1 { + reg_info = <&soc_avdd33_usb3_reg>; + status = "okay"; + regu_id@0 { + pmic_dev = <&pmic_dev_0 DA9063_ID_LDO9>; + }; + }; + + regu_config_2 { + reg_info = <&soc_dvdd08_aon_reg>; + status = "okay"; + regu_id@0 { + pmic_dev = <&pmic_dev_0 DA9063_ID_LDO2>; + }; + }; + + regu_config_3 { + reg_info = <&soc_apcpu_dvdd_dvddm_reg>; + status = "okay"; + regu_id@0 { + pmic_dev = <&pmic_dev_0 DA9063_ID_BCORE1>; + auto_on_info = <0 0 800000>; + }; + + regu_id@1 { + pmic_dev = <&pmic_dev_0 DA9063_ID_BCORE2>; + auto_on_info = <1 0 800000>; + }; + + coupling_info@0 { + negative-min; + info = <0 1 5 30>; + }; + }; + + regu_config_4 { + reg_info = <&soc_dvdd08_ddr_reg>; + status = "okay"; + regu_id@0 { + pmic_dev = <&pmic_dev_0 DA9063_ID_BUCKPERI>; + }; + }; + + regu_config_5 { + reg_info = <&soc_vdd_ddr_1v8_reg>; + status = "okay"; + regu_id@0 { + pmic_dev = <&pmic_dev_0 DA9063_ID_LDO4>; + }; + }; + + regu_config_6 { + reg_info = <&soc_vdd_ddr_1v1_reg>; + status = "okay"; + regu_id@0 { + pmic_dev = <&pmic_dev_0 DA9063_ID_BUCKMEM>; + }; + regu_id@1 { + pmic_dev = <&pmic_dev_0 DA9063_ID_BUCKIO>; + }; + + }; + + regu_config_7 { + reg_info = <&soc_vdd_ddr_0v6_reg>; + status = "okay"; + regu_id@0 { + pmic_dev = <&pmic_dev_0 DA9063_ID_BUCKPRO>; + }; + }; + + regu_config_8 { + reg_info = <&soc_dvdd18_ap_reg>; + status = "okay"; + regu_id@0 { + pmic_dev = <&pmic_dev_0 DA9063_ID_LDO11>; + }; + }; + + regu_config_9 { + reg_info = <&soc_avdd08_mipi_hdmi_reg>; + status = "okay"; + regu_id@0 { + pmic_dev = <&pmic_dev_0 DA9063_ID_LDO1>; + }; + }; + + regu_config_10 { + reg_info = <&soc_avdd18_mipi_hdmi_reg>; + status = "okay"; + regu_id@0 { + pmic_dev = <&pmic_dev_0 DA9063_ID_LDO5>; + }; + }; + + regu_config_11 { + reg_info = <&soc_dvdd33_emmc_reg>; + status = "okay"; + regu_id@0 { + pmic_dev = <&pmic_dev_0 DA9063_ID_LDO10>; + }; + }; + + regu_config_12 { + reg_info = <&soc_dovdd18_scan_reg>; + status = "okay"; + regu_id@0 { + pmic_dev = <&pmic_dev_0 DA9063_ID_LDO6>; + auto_on_info = <2 1 1800000>; + auto_off_info = <7 1>; + }; + }; + + regu_config_13 { + reg_info = <&soc_vext_2v8_reg>; + status = "okay"; + regu_id@0 { + pmic_dev = <&pmic_dev_0 DA9063_ID_LDO7>; + auto_on_info = <3 1 2800000>; + auto_off_info = <8 1>; + }; + }; + + regu_config_14 { + reg_info = <&soc_dvdd12_scan_reg>; + status = "okay"; + regu_id@0 { + pmic_dev = <&pmic_dev_0 DA9063_ID_LDO8>; + auto_on_info = <4 1 1200000>; + auto_off_info = <9 1>; + }; + }; + + regu_config_15 { + reg_info = <&soc_avdd28_scan_en_reg>; + status = "okay"; + regu_id@0 { + pmic_dev = <&pmic_dev_0 DA9063_ID_GPIO4>; + auto_on_info = <5 1 2800000>; + auto_off_info = <6 1>; + }; + }; + + regu_config_16 { + reg_info = <&soc_dvdd08_ap_reg>; + status = "okay"; + regu_id@0 { + pmic_dev = <&pmic_dev_1 DA9121_ID_BUCK1>; + parent_pmic_dev = <&pmic_dev_0 2 0>; + }; + }; + + regu_config_17 { + reg_info = <&soc_avdd28_rgb_reg>; + status = "okay"; + regu_id@0 { + pmic_dev = <&pmic_dev_2 SLG51000_ID_LDO1>; + auto_on_info = <6 0 2800000>; + auto_off_info = <0 1>; + }; + }; + + regu_config_18 { + reg_info = <&soc_avdd25_ir_reg>; + status = "okay"; + regu_id@0 { + pmic_dev = <&pmic_dev_2 SLG51000_ID_LDO2>; + auto_on_info = <7 0 2500000>; + auto_off_info = <1 1>; + }; + }; + + regu_config_19 { + reg_info = <&soc_dvdd18_emmc_reg>; + status = "okay"; + regu_id@0 { + pmic_dev = <&pmic_dev_2 SLG51000_ID_LDO3>; + parent_pmic_dev = <&pmic_dev_0 7 0>; + }; + }; + + regu_config_20 { + reg_info = <&soc_dovdd18_rgb_reg>; + status = "okay"; + regu_id@0 { + pmic_dev = <&pmic_dev_2 SLG51000_ID_LDO4>; + auto_on_info = <8 0 1800000>; + auto_off_info = <2 1>; + }; + }; + + regu_config_21 { + reg_info = <&soc_dvdd12_rgb_reg>; + status = "okay"; + regu_id@0 { + pmic_dev = <&pmic_dev_2 SLG51000_ID_LDO5>; + auto_on_info = <9 0 1200000>; + auto_off_info = <3 1>; + }; + }; + + regu_config_22 { + reg_info = <&soc_dvdd12_ir_reg>; + status = "okay"; + regu_id@0 { + pmic_dev = <&pmic_dev_2 SLG51000_ID_LDO6>; + auto_on_info = <10 0 1200000>; + auto_off_info = <4 1>; + }; + }; + + regu_config_23 { + reg_info = <&soc_dovdd18_ir_reg>; + status = "okay"; + regu_id@0 { + pmic_dev = <&pmic_dev_2 SLG51000_ID_LDO7>; + auto_on_info = <11 0 1800000>; + auto_off_info = <5 1>; + }; + }; + }; + }; + }; chosen { diff --git a/arch/riscv/dts/light-b-product.dts b/arch/riscv/dts/light-b-product.dts index 134ade96..a932f5c9 100644 --- a/arch/riscv/dts/light-b-product.dts +++ b/arch/riscv/dts/light-b-product.dts @@ -1,4 +1,7 @@ /dts-v1/; + +#include + / { model = "T-HEAD c910 light"; compatible = "thead,c910_light"; @@ -469,6 +472,362 @@ lcd-en-gpios = <&gpio1_porta 9 0>; /* active high */ lcd-bias-en-gpios = <&gpio1_porta 10 0>;/* active high */ }; + + aon { + compatible = "thead,light-aon"; + status = "okay"; + + wakeup-by-gpio-on; + wakeup-by-rtc-on; + + pd: light-aon-pd { + compatible = "thead,light-aon-pd"; + #power-domain-cells = <1>; + }; + + light-regu-reg { + compatible = "thead,light-dialog-pmic"; + status = "okay"; + + + + soc_dvdd18_aon_reg: soc_dvdd18_aon { + regulator-name = "soc_dvdd18_aon"; + regulator-boot-on; + regulator-always-on; + }; + + soc_avdd33_usb3_reg: soc_avdd33_usb3 { + regulator-name = "soc_avdd33_usb3"; + regulator-boot-on; + regulator-always-on; + }; + + soc_dvdd08_aon_reg: soc_dvdd08_aon { + regulator-name = "soc_dvdd08_aon"; + regulator-boot-on; + regulator-always-on; + }; + + soc_apcpu_dvdd_dvddm_reg: soc_apcpu_dvdd_dvddm { + regulator-name = "soc_apcpu_dvdd_dvddm"; + regulator-min-microvolt = <300000>; + regulator-max-microvolt = <1570000>; + regulator-boot-on; + regulator-always-on; + }; + + soc_dvdd08_ddr_reg: soc_dvdd08_ddr { + regulator-name = "soc_dvdd08_ddr"; + regulator-boot-on; + regulator-always-on; + }; + + soc_vdd_ddr_1v8_reg: soc_vdd_ddr_1v8 { + regulator-name = "soc_vdd_ddr_1v8"; + regulator-boot-on; + regulator-always-on; + }; + + soc_vdd_ddr_1v1_reg: soc_vdd_ddr_1v1 { + regulator-name = "soc_vdd_ddr_1v1"; + regulator-boot-on; + regulator-always-on; + }; + + soc_vdd_ddr_0v6_reg: soc_vdd_ddr_0v6 { + regulator-name = "soc_vdd_ddr_0v6"; + regulator-boot-on; + regulator-always-on; + }; + + soc_dvdd18_ap_reg: soc_dvdd18_ap { + regulator-name = "soc_dvdd18_ap"; + regulator-boot-on; + regulator-always-on; + }; + + soc_dvdd08_ap_reg: soc_dvdd08_ap { + regulator-name = "soc_dvdd08_ap"; + regulator-boot-on; + regulator-always-on; + }; + + soc_avdd08_mipi_hdmi_reg: soc_avdd08_mipi_hdmi { + regulator-name = "soc_avdd08_mipi_hdmi"; + regulator-boot-on; + regulator-always-on; + }; + + soc_avdd18_mipi_hdmi_reg: soc_avdd18_mipi_hdmi { + regulator-name = "soc_avdd18_mipi_hdmi"; + regulator-boot-on; + regulator-always-on; + }; + + soc_dvdd33_emmc_reg: soc_dvdd33_emmc { + regulator-name = "soc_dvdd33_emmc"; + regulator-boot-on; + regulator-always-on; + }; + + soc_dvdd18_emmc_reg: soc_dvdd18_emmc { + regulator-name = "soc_vdd18_emmc"; + regulator-boot-on; + regulator-always-on; + }; + soc_dovdd18_scan_reg: soc_dovdd18_scan { + regulator-name = "soc_dovdd18_scan"; + regulator-min-microvolt = <900000>; + regulator-max-microvolt = <3600000>; + status = "disabled"; + }; + soc_vext_2v8_reg: soc_vext_2v8 { + regulator-name = "soc_vext_2v8"; + regulator-boot-on; + regulator-always-on; + status = "disabled"; + }; + soc_dvdd12_scan_reg: soc_dvdd12_scan { + regulator-name = "soc_dvdd12_scan"; + regulator-min-microvolt = <900000>; + regulator-max-microvolt = <3600000>; + status = "disabled"; + }; + soc_avdd28_scan_en_reg: soc_avdd28_scan_en { + regulator-name = "soc_avdd28_scan_en"; + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <2800000>; + status = "disabled"; + }; + soc_avdd28_rgb_reg: soc_avdd28_rgb { + regulator-name = "soc_avdd28_rgb"; + regulator-min-microvolt = <2200000>; + regulator-max-microvolt = <3475000>; + regulator-boot-on; + regulator-always-on; + status = "disabled"; + }; + soc_dovdd18_rgb_reg: soc_dovdd18_rgb { + regulator-name = "soc_dovdd18_rgb"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <3600000>; + regulator-boot-on; + regulator-always-on; + status = "disabled"; + }; + soc_dvdd12_rgb_reg: soc_dvdd12_rgb { + regulator-name = "soc_dvdd12_rgb"; + regulator-min-microvolt = <400000>; + regulator-max-microvolt = <1675000>; + regulator-boot-on; + regulator-always-on; + status = "disabled"; + }; + soc_avdd25_ir_reg: soc_avdd25_ir { + regulator-name = "soc_avdd25_ir"; + regulator-min-microvolt = <2200000>; + regulator-max-microvolt = <3475000>; + regulator-boot-on; + regulator-always-on; + status = "disabled"; + }; + soc_dovdd18_ir_reg: soc_dovdd18_ir { + regulator-name = "soc_dovdd18_ir"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <3600000>; + regulator-boot-on; + regulator-always-on; + status = "disabled"; + }; + soc_dvdd12_ir_reg: soc_dvdd12_ir { + regulator-name = "soc_dvdd12_ir"; + regulator-min-microvolt = <400000>; + regulator-max-microvolt = <1675000>; + regulator-boot-on; + regulator-always-on; + status = "disabled"; + }; + soc_adc_vref_reg: soc_adc_vref { + regulator-name = "soc_adc_vref"; + }; + soc_lcd0_en_reg: soc_lcd0_en { + regulator-name = "soc_lcd0_en"; + }; + soc_vext_1v8_reg: soc_vext_1v8 { + regulator-name = "soc_vext_1v8"; + }; + }; + + aon_pmic_config { + compatible = "thead,light-pmic-conf"; + status = "okay"; + #address-cells = <1>; + #size-cells = <0>; + + pmic_dev_0: pmic-dev@0 { + pmic-name = "ricoh,rn5t567,v0"; + pmic-addr = <0x31>; + pmic_wdt_on; + status = "okay"; + }; + + pmic_dev_1: pmic-dev@1 { + pmic-name = "ricoh,rn5t567,v1"; + pmic-addr = <0x32>; + status = "okay"; + }; + + regu_config_0 { + reg_info = <&soc_dvdd18_aon_reg>; + status = "okay"; + regu_id@0 { + pmic_dev = <&pmic_dev_0 RICOH567_ID_LDO4>; + }; + }; + + regu_config_1 { + reg_info = <&soc_avdd33_usb3_reg>; + status = "okay"; + regu_id@0 { + pmic_dev = <&pmic_dev_0 RICOH567_ID_LDO1>; + }; + }; + + regu_config_2 { + reg_info = <&soc_dvdd08_aon_reg>; + status = "okay"; + regu_id@0 { + pmic_dev = <&pmic_dev_0 RICOH567_ID_LDO3>; + }; + }; + + regu_config_3 { + reg_info = <&soc_apcpu_dvdd_dvddm_reg>; + status = "okay"; + regu_id@0 { + pmic_dev = <&pmic_dev_0 RICOH567_ID_DC3>; + auto_on_info = <2 0 800000>; + }; + + regu_id@1 { + pmic_dev = <&pmic_dev_0 RICOH567_ID_DC4>; + auto_on_info = <3 0 800000>; + }; + + coupling_info@0 { + negative-min; + info = <0 1 5 30>; + }; + }; + + regu_config_4 { + reg_info = <&soc_dvdd08_ddr_reg>; + status = "okay"; + regu_id@0 { + pmic_dev = <&pmic_dev_0 RICOH567_ID_DC1>; + }; + }; + + regu_config_5 { + reg_info = <&soc_vdd_ddr_1v8_reg>; + status = "okay"; + regu_id@0 { + pmic_dev = <&pmic_dev_0 RICOH567_ID_LDO2>; + }; + }; + + regu_config_6 { + reg_info = <&soc_vdd_ddr_1v1_reg>; + status = "okay"; + regu_id@0 { + pmic_dev = <&pmic_dev_1 RICOH567_ID_DC2>; + }; + }; + + regu_config_7 { + reg_info = <&soc_vdd_ddr_0v6_reg>; + status = "okay"; + regu_id@0 { + pmic_dev = <&pmic_dev_1 RICOH567_ID_DC1>; + }; + }; + + regu_config_8 { + reg_info = <&soc_dvdd18_ap_reg>; + status = "okay"; + regu_id@0 { + pmic_dev = <&pmic_dev_1 RICOH567_ID_LDO2>; + }; + }; + + regu_config_9 { + reg_info = <&soc_avdd08_mipi_hdmi_reg>; + status = "okay"; + regu_id@0 { + pmic_dev = <&pmic_dev_1 RICOH567_ID_LDO3>; + }; + }; + + regu_config_10 { + reg_info = <&soc_avdd18_mipi_hdmi_reg>; + status = "okay"; + regu_id@0 { + pmic_dev = <&pmic_dev_1 RICOH567_ID_LDO4>; + }; + }; + + regu_config_11 { + reg_info = <&soc_dvdd33_emmc_reg>; + status = "okay"; + regu_id@0 { + pmic_dev = <&pmic_dev_1 RICOH567_ID_LDO1>; + }; + }; + + regu_config_12 { + reg_info = <&soc_dvdd08_ap_reg>; + status = "okay"; + regu_id@0 { + pmic_dev = <&pmic_dev_1 RICOH567_ID_GPIO3>; + }; + }; + + regu_config_13 { + reg_info = <&soc_dvdd18_emmc_reg>; + status = "okay"; + regu_id@0 { + pmic_dev = <&pmic_dev_1 RICOH567_ID_DC3>; + }; + }; + + regu_config_14 { + reg_info = <&soc_adc_vref_reg>; + status = "okay"; + regu_id@0 { + pmic_dev = <&pmic_dev_1 RICOH567_ID_LDO5>; + }; + }; + + regu_config_15 { + reg_info = <&soc_lcd0_en_reg>; + status = "okay"; + regu_id@0 { + pmic_dev = <&pmic_dev_0 RICOH567_ID_LDO5>; + auto_on_info = <0 0 1800000>; + }; + }; + + regu_config_16 { + reg_info = <&soc_vext_1v8_reg>; + status = "okay"; + regu_id@0 { + pmic_dev = <&pmic_dev_1 RICOH567_ID_DC4>; + auto_on_info = <1 0 1800000>; + }; + }; + }; + }; }; chosen { diff --git a/arch/riscv/dts/light-lpi4a-laptop.dts b/arch/riscv/dts/light-lpi4a-laptop.dts index 3648c43b..92c121cc 100644 --- a/arch/riscv/dts/light-lpi4a-laptop.dts +++ b/arch/riscv/dts/light-lpi4a-laptop.dts @@ -35,6 +35,7 @@ }; &panel0 { + compatible = "ilitek,ili9881c"; status = "okay"; backlight = <&lcd_backlight>; // 5v power cycle diff --git a/arch/riscv/dts/light-lpi4a.dts b/arch/riscv/dts/light-lpi4a.dts index 9afad620..e252b462 100644 --- a/arch/riscv/dts/light-lpi4a.dts +++ b/arch/riscv/dts/light-lpi4a.dts @@ -1,4 +1,7 @@ /dts-v1/; + +#include + / { model = "T-HEAD c910 light"; compatible = "thead,c910_light"; @@ -147,6 +150,13 @@ #address-cells = <1>; #size-cells = <0>; + + pcal6408ahk_d: gpio@20 { + compatible = "nxp,pca9557"; + reg = <0x18>; + gpio-controller; + #gpio-cells = <2>; + }; }; i2c4: i2c@ffe7f28000{ @@ -157,13 +167,6 @@ #address-cells = <1>; #size-cells = <0>; - - pcal6408ahk_a: gpio@20 { - compatible = "nxp,pca9554"; - reg = <0x20>; - gpio-controller; - #gpio-cells = <2>; - }; }; i2c5: i2c@fff7f2c000{ @@ -382,6 +385,20 @@ reg = <0xff 0xef600000 0x0 0x100>; }; + usb: usb@ffe7040000 { + compatible = "snps,dwc3"; + reg = <0xff 0xe7040000 0x0 0x10000>; + interrupts = <68>; + reg-shift = <2>; + reg-io-width = <4>; + maximum-speed = "super-speed"; + dr_mode = "host"; + dma-mask = <0xf 0xffffffff>; + snps,usb3_lpm_capable; + snps,usb_sofitpsync; + status = "okay"; + }; + axiscr { compatible = "thead,axiscr"; reg = <0xff 0xff004000 0x0 0x1000>; @@ -473,12 +490,375 @@ }; panel0: dsi_panel0 { - compatible = "ilitek,ili9881c"; + compatible = "jadard,jd9365da-h3"; backlight = <&lcd_backlight>; - reset-gpios = <&gpio1_porta 5 1>; /* active low */ - lcd-en-gpios = <&pcal6408ahk_a 2 0>; /* active high */ - lcd-bias-en-gpios = <&pcal6408ahk_a 4 0>;/* active high */ + reset-gpio = <&pcal6408ahk_d 7 0>; + hsvcc-gpio = <&pcal6408ahk_d 6 1>; + vspn3v3-gpio = <&pcal6408ahk_d 5 1>; }; + + aon { + compatible = "thead,light-aon"; + status = "okay"; + + wakeup-by-gpio-on; + wakeup-by-rtc-on; + + pd: light-aon-pd { + compatible = "thead,light-aon-pd"; + #power-domain-cells = <1>; + }; + + light-regu-reg { + compatible = "thead,light-dialog-pmic"; + status = "okay"; + + + + soc_dvdd18_aon_reg: soc_dvdd18_aon { + regulator-name = "soc_dvdd18_aon"; + regulator-boot-on; + regulator-always-on; + }; + + soc_avdd33_usb3_reg: soc_avdd33_usb3 { + regulator-name = "soc_avdd33_usb3"; + regulator-boot-on; + regulator-always-on; + }; + + soc_dvdd08_aon_reg: soc_dvdd08_aon { + regulator-name = "soc_dvdd08_aon"; + regulator-boot-on; + regulator-always-on; + }; + + soc_apcpu_dvdd_dvddm_reg: soc_apcpu_dvdd_dvddm { + regulator-name = "soc_apcpu_dvdd_dvddm"; + regulator-min-microvolt = <300000>; + regulator-max-microvolt = <1570000>; + regulator-boot-on; + regulator-always-on; + }; + + soc_dvdd08_ddr_reg: soc_dvdd08_ddr { + regulator-name = "soc_dvdd08_ddr"; + regulator-boot-on; + regulator-always-on; + }; + + soc_vdd_ddr_1v8_reg: soc_vdd_ddr_1v8 { + regulator-name = "soc_vdd_ddr_1v8"; + regulator-boot-on; + regulator-always-on; + }; + + soc_vdd_ddr_1v1_reg: soc_vdd_ddr_1v1 { + regulator-name = "soc_vdd_ddr_1v1"; + regulator-boot-on; + regulator-always-on; + }; + + soc_vdd_ddr_0v6_reg: soc_vdd_ddr_0v6 { + regulator-name = "soc_vdd_ddr_0v6"; + regulator-boot-on; + regulator-always-on; + }; + + soc_dvdd18_ap_reg: soc_dvdd18_ap { + regulator-name = "soc_dvdd18_ap"; + regulator-boot-on; + regulator-always-on; + }; + + soc_dvdd08_ap_reg: soc_dvdd08_ap { + regulator-name = "soc_dvdd08_ap"; + regulator-boot-on; + regulator-always-on; + }; + + soc_avdd08_mipi_hdmi_reg: soc_avdd08_mipi_hdmi { + regulator-name = "soc_avdd08_mipi_hdmi"; + regulator-boot-on; + regulator-always-on; + }; + + soc_avdd18_mipi_hdmi_reg: soc_avdd18_mipi_hdmi { + regulator-name = "soc_avdd18_mipi_hdmi"; + regulator-boot-on; + regulator-always-on; + }; + + soc_dvdd33_emmc_reg: soc_dvdd33_emmc { + regulator-name = "soc_dvdd33_emmc"; + regulator-boot-on; + regulator-always-on; + }; + + soc_dvdd18_emmc_reg: soc_dvdd18_emmc { + regulator-name = "soc_vdd18_emmc"; + regulator-boot-on; + regulator-always-on; + }; + soc_dovdd18_scan_reg: soc_dovdd18_scan { + regulator-name = "soc_dovdd18_scan"; + regulator-min-microvolt = <900000>; + regulator-max-microvolt = <3600000>; + }; + soc_vext_2v8_reg: soc_vext_2v8 { + regulator-name = "soc_vext_2v8"; + regulator-boot-on; + regulator-always-on; + status = "disabled"; + }; + soc_dvdd12_scan_reg: soc_dvdd12_scan { + regulator-name = "soc_dvdd12_scan"; + regulator-min-microvolt = <900000>; + regulator-max-microvolt = <3600000>; + }; + soc_avdd28_scan_en_reg: soc_avdd28_scan_en { + regulator-name = "soc_avdd28_scan_en"; + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <2800000>; + }; + soc_avdd28_rgb_reg: soc_avdd28_rgb { + regulator-name = "soc_avdd28_rgb"; + regulator-min-microvolt = <2200000>; + regulator-max-microvolt = <3475000>; + regulator-boot-on; + regulator-always-on; + status = "disabled"; + }; + soc_dovdd18_rgb_reg: soc_dovdd18_rgb { + regulator-name = "soc_dovdd18_rgb"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <3600000>; + regulator-boot-on; + regulator-always-on; + status = "disabled"; + }; + soc_dvdd12_rgb_reg: soc_dvdd12_rgb { + regulator-name = "soc_dvdd12_rgb"; + regulator-min-microvolt = <400000>; + regulator-max-microvolt = <1675000>; + regulator-boot-on; + regulator-always-on; + status = "disabled"; + }; + soc_avdd25_ir_reg: soc_avdd25_ir { + regulator-name = "soc_avdd25_ir"; + regulator-min-microvolt = <2200000>; + regulator-max-microvolt = <3475000>; + regulator-boot-on; + regulator-always-on; + status = "disabled"; + }; + soc_dovdd18_ir_reg: soc_dovdd18_ir { + regulator-name = "soc_dovdd18_ir"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <3600000>; + regulator-boot-on; + regulator-always-on; + status = "disabled"; + }; + soc_dvdd12_ir_reg: soc_dvdd12_ir { + regulator-name = "soc_dvdd12_ir"; + regulator-min-microvolt = <400000>; + regulator-max-microvolt = <1675000>; + regulator-boot-on; + regulator-always-on; + status = "disabled"; + }; + }; + + aon_pmic_config { + compatible = "thead,light-pmic-conf"; + status = "okay"; + + #address-cells = <1>; + #size-cells = <0>; + + pmic_dev_0: pmic-dev@0 { + pmic-name = "dialog,da9063,v1"; + pmic-addr = <0x5a 0x5b>; + pmic_wdt_on; + status = "okay"; + }; + + pmic_dev_1: pmic-dev@1 { + pmic-name = "dialog,da9121,v1"; + pmic-addr = <0x68>; + status = "okay"; + }; + + regu_config_0 { + reg_info = <&soc_dvdd18_aon_reg>; + status = "okay"; + regu_id@0 { + pmic_dev = <&pmic_dev_0 DA9063_ID_LDO3>; + }; + }; + + regu_config_1 { + reg_info = <&soc_avdd33_usb3_reg>; + status = "okay"; + regu_id@0 { + pmic_dev = <&pmic_dev_0 DA9063_ID_LDO9>; + }; + }; + + regu_config_2 { + reg_info = <&soc_dvdd08_aon_reg>; + status = "okay"; + regu_id@0 { + pmic_dev = <&pmic_dev_0 DA9063_ID_LDO2>; + }; + }; + + regu_config_3 { + reg_info = <&soc_apcpu_dvdd_dvddm_reg>; + status = "okay"; + regu_id@0 { + pmic_dev = <&pmic_dev_0 DA9063_ID_BCORE1>; + auto_on_info = <0 0 800000>; + }; + + regu_id@1 { + pmic_dev = <&pmic_dev_0 DA9063_ID_BCORE2>; + auto_on_info = <1 0 800000>; + }; + + regu_id@2 { + pmic_dev = <&pmic_dev_0 DA9063_ID_BUCKIO>; + auto_on_info = <2 0 800000>; + }; + + coupling_info@0 { + negative-min; + info = <0 2 5 30>; + }; + + coupling_info@1 { + negative-min; + info = <1 2 5 30>; + }; + }; + + regu_config_4 { + reg_info = <&soc_dvdd08_ddr_reg>; + status = "okay"; + regu_id@0 { + pmic_dev = <&pmic_dev_0 DA9063_ID_BUCKPERI>; + }; + }; + + regu_config_5 { + reg_info = <&soc_vdd_ddr_1v8_reg>; + status = "okay"; + regu_id@0 { + pmic_dev = <&pmic_dev_0 DA9063_ID_LDO4>; + }; + }; + + regu_config_6 { + reg_info = <&soc_vdd_ddr_1v1_reg>; + status = "okay"; + regu_id@0 { + pmic_dev = <&pmic_dev_0 DA9063_ID_BUCKMEM>; + }; + }; + + regu_config_7 { + reg_info = <&soc_vdd_ddr_0v6_reg>; + status = "okay"; + regu_id@0 { + pmic_dev = <&pmic_dev_0 DA9063_ID_BUCKPRO>; + }; + }; + + regu_config_8 { + reg_info = <&soc_dvdd18_ap_reg>; + status = "okay"; + regu_id@0 { + pmic_dev = <&pmic_dev_0 DA9063_ID_LDO11>; + }; + }; + + regu_config_9 { + reg_info = <&soc_avdd08_mipi_hdmi_reg>; + status = "okay"; + regu_id@0 { + pmic_dev = <&pmic_dev_0 DA9063_ID_LDO1>; + }; + }; + + regu_config_10 { + reg_info = <&soc_avdd18_mipi_hdmi_reg>; + status = "okay"; + regu_id@0 { + pmic_dev = <&pmic_dev_0 DA9063_ID_LDO5>; + }; + }; + + regu_config_11 { + reg_info = <&soc_dvdd33_emmc_reg>; + status = "okay"; + regu_id@0 { + pmic_dev = <&pmic_dev_0 DA9063_ID_LDO10>; + }; + }; + + regu_config_12 { + reg_info = <&soc_dovdd18_scan_reg>; + status = "okay"; + regu_id@0 { + pmic_dev = <&pmic_dev_0 DA9063_ID_LDO6>; + auto_on_info = <3 1 1800000>; + auto_off_info = <1 1>; + }; + }; + + + regu_config_13 { + reg_info = <&soc_dvdd12_scan_reg>; + status = "okay"; + regu_id@0 { + pmic_dev = <&pmic_dev_0 DA9063_ID_LDO8>; + auto_on_info = <4 1 1200000>; + auto_off_info = <2 1>; + }; + }; + + regu_config_14 { + reg_info = <&soc_avdd28_scan_en_reg>; + status = "okay"; + regu_id@0 { + pmic_dev = <&pmic_dev_0 DA9063_ID_LDO7>; + auto_on_info = <5 1 2800000>; + auto_off_info = <0 1>; + }; + }; + + regu_config_15 { + reg_info = <&soc_dvdd08_ap_reg>; + status = "okay"; + regu_id@0 { + pmic_dev = <&pmic_dev_1 DA9121_ID_BUCK1>; + parent_pmic_dev = <&pmic_dev_0 2 0>; + }; + }; + + regu_config_16 { + reg_info = <&soc_dvdd18_emmc_reg>; + status = "okay"; + regu_id@0 { + pmic_dev = <&pmic_dev_0 DA9063_ID_GPIO7>; + parent_pmic_dev = <&pmic_dev_0 7 0>; + }; + }; + }; + }; + }; chosen { diff --git a/board/thead/light-c910/Kconfig b/board/thead/light-c910/Kconfig index e860e293..246ac108 100644 --- a/board/thead/light-c910/Kconfig +++ b/board/thead/light-c910/Kconfig @@ -140,8 +140,7 @@ config SYS_TEXT_BASE config SPL_TEXT_BASE hex - default 0xffe0000800 if LIGHT_SEC_BOOT_WITH_VERIFY_VAL_A || LIGHT_SEC_BOOT_WITH_VERIFY_VAL_B || LIGHT_SEC_BOOT_WITH_VERIFY_ANT_REF || LIGHT_SEC_BOOT_WITH_VERIFY_LPI4A - default 0xffe0000000 if !(LIGHT_SEC_BOOT_WITH_VERIFY_VAL_A || LIGHT_SEC_BOOT_WITH_VERIFY_VAL_B || LIGHT_SEC_BOOT_WITH_VERIFY_ANT_REF || LIGHT_SEC_BOOT_WITH_VERIFY_LPI4A) + default 0xffe0000800 config SPL_MAX_SIZE hex @@ -258,6 +257,11 @@ config DDR_DDP Enabling this will support ddr Dual Die Package configuration. e.g. to support 8GB ddr device with 17-bit row address (16:0) +config FIXUP_MEMORY_REGION + bool "self-adapt to query and fixup memory region" + help + Enabling this will support self-adapt to query and fixup memory region + config DDR_H32_MODE bool "LPDDR4/4X 32bit mode configuration" help diff --git a/board/thead/light-c910/Makefile b/board/thead/light-c910/Makefile index 404b9c12..38f4ace9 100644 --- a/board/thead/light-c910/Makefile +++ b/board/thead/light-c910/Makefile @@ -23,6 +23,7 @@ obj-$(CONFIG_LPDDR) += $(DDR_SRC_PATH)/init_ddr.o obj-$(CONFIG_LPDDR) += $(DDR_SRC_PATH)/pinmux.o obj-$(CONFIG_LPDDR) += $(DDR_SRC_PATH)/waitfwdone.o obj-$(CONFIG_LPDDR) += $(DDR_SRC_PATH)/ddr_common_func.o +obj-$(CONFIG_LPDDR) += $(DDR_SRC_PATH)/ddr_retention.o obj-$(CONFIG_LPDDR) += $(DDR_SRC_PATH)/common_lib.o obj-$(CONFIG_LPDDR) += $(DDR_SRC_PATH)/lpddr4_init.o ifdef CONFIG_DDR_DBI_OFF @@ -63,6 +64,7 @@ obj-y += boot.o obj-y += sbmeta/sbmeta.o ifndef CONFIG_TARGET_LIGHT_FPGA_FM_C910 obj-$(CONFIG_LPDDR) += $(DDR_SRC_PATH)/ddr_common_func.o +obj-$(CONFIG_LPDDR) += $(DDR_SRC_PATH)/ddr_retention.o obj-$(CONFIG_LPDDR) += $(DDR_SRC_PATH)/common_lib.o endif diff --git a/board/thead/light-c910/board.c b/board/thead/light-c910/board.c index 7d705b48..91fd9e58 100644 --- a/board/thead/light-c910/board.c +++ b/board/thead/light-c910/board.c @@ -8,11 +8,17 @@ #include #include #include +#include #include #include #include #include "sec_library.h" +#ifdef CONFIG_LIGHT_AON_CONF +#include "../../../drivers/misc/light_regu.h" +#include "dm/device.h" +#endif + #ifdef CONFIG_USB_DWC3 static struct dwc3_device dwc3_device_data = { .maximum_speed = USB_SPEED_SUPER, @@ -29,6 +35,13 @@ int usb_gadget_handle_interrupts(int index) int board_usb_init(int index, enum usb_init_type init) { dwc3_device_data.base = 0xFFE7040000UL; + + if (init == USB_INIT_DEVICE) { + dwc3_device_data.dr_mode = USB_DR_MODE_PERIPHERAL; + } else { + dwc3_device_data.dr_mode = USB_DR_MODE_HOST; + } + return dwc3_uboot_init(&dwc3_device_data); } @@ -38,6 +51,28 @@ int board_usb_cleanup(int index, enum usb_init_type init) return 0; } +int xhci_hcd_init(int index, struct xhci_hccr **hccr, struct xhci_hcor **hcor) +{ + + + int ret = board_usb_init(index, USB_INIT_HOST); + if (ret != 0) { + puts("Failed to initialize board for USB\n"); + return ret; + } + + *hccr = (struct xhci_hccr *)dwc3_device_data.base; + *hcor = (struct xhci_hcor *)(dwc3_device_data.base + + HC_LENGTH(xhci_readl(&(*hccr)->cr_capbase)));; + + return ret; +} + +void xhci_hcd_stop(int index) +{ + board_usb_cleanup(index, USB_INIT_HOST); +} + int g_dnl_board_usb_cable_connected(void) { return 1; @@ -45,9 +80,14 @@ int g_dnl_board_usb_cable_connected(void) #endif #ifdef CONFIG_CMD_BOOT_SLAVE +#ifdef CONFIG_LIGHT_AON_CONF +#define E902_AON_CONFIG_SIZE 0xC00 +#else +#define E902_AON_CONFIG_SIZE 0x000 +#endif #define E902_SYSREG_START 0xfffff48044 #define E902_SYSREG_RESET 0xfffff44024 -#define E902_START_ADDRESS 0xFFEF8000 +#define E902_START_ADDRESS (0xFFEF8000 + E902_AON_CONFIG_SIZE) #define C910_E902_START_ADDRESS 0xFFFFEF8000 #define E902_IOPMP_BASE 0xFFFFC21000 @@ -87,31 +127,115 @@ void set_c906_cpu_entry(phys_addr_t entry_h, phys_addr_t entry_l) void boot_audio(void) { - writel(0x37, (volatile void *)C906_RESET_REG); + writel(0x37, (volatile void *)C906_RESET_REG); - set_c906_cpu_entry(C906_START_ADDRESS_H, C906_START_ADDRESS_L); - flush_cache((uintptr_t)C910_C906_START_ADDRESS, 0x20000); + set_c906_cpu_entry(C906_START_ADDRESS_H, C906_START_ADDRESS_L); + flush_cache((uintptr_t)C910_C906_START_ADDRESS, 0x20000); - writel(0x7ffff1f, (volatile void *)C906_CPR_IPCG_ADDRESS); - writel((1<<23) | (1<<24), (volatile void *)C906_IOCTL_GPIO_SEL_ADDRESS); - writel(0, (volatile void *)C906_IOCTL_AF_SELH_ADDRESS); + writel(0x7ffff1f, (volatile void *)C906_CPR_IPCG_ADDRESS); + writel((1<<23) | (1<<24), (volatile void *)C906_IOCTL_GPIO_SEL_ADDRESS); + writel(0, (volatile void *)C906_IOCTL_AF_SELH_ADDRESS); - writel(0x3f, (volatile void *)C906_RESET_REG); + writel(0x3f, (volatile void *)C906_RESET_REG); } -void boot_aon(void) +#ifdef CONFIG_LIGHT_AON_CONF + +int get_and_set_aon_config_data() { + int ret =0; + struct udevice *dev; + struct mic_regu_platdata *config_data =NULL; + + ret = uclass_first_device_err(UCLASS_MISC, &dev); + if(ret){ + printf("get light aon config faild %d\n", ret); + return ret; + } + + config_data = (struct mic_regu_platdata *)(dev->platdata); + + volatile aon_config_t* read_config = (aon_config_t* )C910_E902_START_ADDRESS; + if(strncmp(read_config->magic , AON_CONFIG_MAGIC, strlen(AON_CONFIG_MAGIC))) { + printf("No aon config magic found in aon bin, please check the aon bin\n"); + return -1; + } + + if(strncmp(read_config->version, AON_CONFIG_VERSION, strlen(AON_CONFIG_VERSION))) { + printf("Err aon config version, aon bin is:%s, u-boot is:%s\n", read_config->version, AON_CONFIG_VERSION); + return -1; + } + + if(PMIC_MAX_HW_ID_NUM > read_config->max_hw_id_num) { + printf("Invald max hw id num, aon bin support %d , u-boot is %d\n",read_config->max_hw_id_num, PMIC_MAX_HW_ID_NUM); + return -1; + } + + /*set pmic dev info */ + int pmic_dev_num = config_data->pmic_list.pmic_num; + int pmic_dev_list_offset = sizeof(aon_config_t); + uintptr_t pmic_dev_start_addr = C910_E902_START_ADDRESS + pmic_dev_list_offset; + + int regu_num = config_data->regu_id_list.regu_id_num; + int regu_id_list_offset = pmic_dev_list_offset + pmic_dev_num * sizeof(pmic_dev_info_t); + uintptr_t regu_start_addr = C910_E902_START_ADDRESS + regu_id_list_offset; + int aon_bin_size = regu_id_list_offset + regu_num* sizeof(csi_regu_id_t); + if( aon_bin_size > read_config->aon_config_partition_size) { + printf("Invalid aon partition size, aon bin support:%d, u-boot is %d\n", read_config->aon_config_partition_size, aon_bin_size); + return -1; + } + + printf("pmic_dev_num:%d offset:%d addr:0x%10x\n",pmic_dev_num, pmic_dev_list_offset, pmic_dev_start_addr); + + memcpy(pmic_dev_start_addr, config_data->pmic_list.pmic_list, pmic_dev_num * sizeof(pmic_dev_info_t)); + printf("regu_num:%d offset:%d addr:0x%10x\n",regu_num,regu_id_list_offset, regu_start_addr); + + memcpy(regu_start_addr, config_data->regu_id_list.regu_id_list, regu_num * sizeof(csi_regu_id_t)); + + read_config->wakeup_flag = config_data->wakeup_flag; + read_config->aon_pmic.pmic_dev_num = pmic_dev_num; + read_config->aon_pmic.pmic_dev_list_offset = pmic_dev_list_offset; + + /*set regu list info*/ + read_config->aon_pmic.regu_num = regu_num; + read_config->aon_pmic.regu_id_list_offset = regu_id_list_offset; + + flush_cache((uintptr_t)C910_E902_START_ADDRESS, aon_bin_size); + + printf("-->pmic_dev_num:%d offset:%d\n",read_config->aon_pmic.pmic_dev_num, read_config->aon_pmic.pmic_dev_list_offset); + printf("-->regu_num:%d offset:%d\n",read_config->aon_pmic.regu_num,read_config->aon_pmic.regu_id_list_offset); + + return 0; +} +#endif + +int do_boot_aon(cmd_tbl_t * cmdtp, int flag, int argc, char * const argv[]) +{ +#ifdef CONFIG_LIGHT_AON_CONF + int ret = 0; + ret = get_and_set_aon_config_data(); + if(ret) { + printf("aon config and set faild %d", ret); + hang(); + return ret; + } +#endif writel(0xffffffff, (void *)(E902_IOPMP_BASE + 0xc0)); disable_slave_cpu(); set_slave_cpu_entry(E902_START_ADDRESS); flush_cache((uintptr_t)C910_E902_START_ADDRESS, 0x10000); enable_slave_cpu(); + return 0; } +U_BOOT_CMD( + bootaon, CONFIG_SYS_MAXARGS, 0, do_boot_aon, + "Boot aon from memory ", + " " +); + int do_bootslave(cmd_tbl_t * cmdtp, int flag, int argc, char * const argv[]) { - boot_aon(); - mdelay(100); boot_audio(); return 0; } diff --git a/board/thead/light-c910/clock_config.c b/board/thead/light-c910/clock_config.c index 543eafeb..8d15ea78 100644 --- a/board/thead/light-c910/clock_config.c +++ b/board/thead/light-c910/clock_config.c @@ -1220,7 +1220,7 @@ int clk_config(void) return -EINVAL; printf("C910 CPU FREQ: %ldMHz\n", rate / 1000000); - +#ifdef PERI_BUS_PLL_FREQ_PRINT rate = clk_light_get_rate("ahb2_cpusys_hclk", CLK_DEV_MUX); if (!rate) return -EINVAL; @@ -1262,6 +1262,7 @@ int clk_config(void) return -EINVAL; printf("DPU1 PLL POSTDIV FREQ: %ldMHZ\n", rate / 1000000); +#endif #ifdef AUDIO_PLL_FREQ_PRINT rate = clk_light_get_rate("audio_pll_foutpostdiv", CLK_DEV_PLL); diff --git a/board/thead/light-c910/ddr.c b/board/thead/light-c910/ddr.c index 0da99ddd..824a7785 100644 --- a/board/thead/light-c910/ddr.c +++ b/board/thead/light-c910/ddr.c @@ -12,3 +12,17 @@ void init_ddr(void) { writel(0x1ff << 4, (void *)0xffff005000); } + +int fixup_ddr_addrmap(unsigned long size) +{ + return 0; +} + +int query_ddr_boundary(unsigned long size) +{ + return 0; +} +unsigned long get_ddr_density(void) +{ + return 0x100000000; +} diff --git a/board/thead/light-c910/light.c b/board/thead/light-c910/light.c index 62cd553e..85395026 100644 --- a/board/thead/light-c910/light.c +++ b/board/thead/light-c910/light.c @@ -11,6 +11,10 @@ #include #include #include +#include +#include +#include +#include #define SOC_PIN_AP_RIGHT_TOP (0x0) #define SOC_PIN_AP_LEFT_TOP (0x1) @@ -1438,7 +1442,7 @@ static void light_iopin_init(void) // light_pin_mux(AOGPIO_15,0); light_pin_cfg(AOGPIO_7, PIN_SPEED_NORMAL, PIN_PN, 2); ///NC light_pin_cfg(AOGPIO_8, PIN_SPEED_NORMAL, PIN_PN, 2); ///NC - // light_pin_cfg(AOGPIO_9,PIN_SPEED_NORMAL,PIN_PN,2); + light_pin_cfg(AOGPIO_9,PIN_SPEED_NORMAL,PIN_PN,2); light_pin_cfg(AOGPIO_10, PIN_SPEED_NORMAL, PIN_PN, 2); light_pin_cfg(AOGPIO_11, PIN_SPEED_NORMAL, PIN_PN, 2); light_pin_cfg(AOGPIO_12, PIN_SPEED_NORMAL, PIN_PN, 2); @@ -1472,6 +1476,8 @@ static void light_iopin_init(void) light_pin_cfg(AUDIO_PA29, PIN_SPEED_NORMAL, PIN_PN, 2); light_pin_mux(AUDIO_PA30, 0); light_pin_cfg(AUDIO_PA30, PIN_SPEED_NORMAL, PIN_PN, 2); + #warning "aon set to 3" + light_pin_mux(AUDIO_PA30, 3); // light_pin_mux(AUDIO_PA9,3); ///AUDIO-PA-RESET // light_pin_cfg(AUDIO_PA9,PIN_SPEED_NORMAL,PIN_PN,2); @@ -2247,16 +2253,19 @@ static void light_iopin_init(void) } #else + static void light_iopin_init(void) { light_pin_cfg(I2C_AON_SCL,PIN_SPEED_NORMAL,PIN_PN,4); light_pin_cfg(I2C_AON_SDA,PIN_SPEED_NORMAL,PIN_PN,4); light_pin_cfg(AOGPIO_8,PIN_SPEED_NORMAL,PIN_PN,2); light_pin_cfg(AOGPIO_9,PIN_SPEED_NORMAL,PIN_PN,2); + light_pin_cfg(AOGPIO_14, PIN_SPEED_NORMAL, PIN_PN, 2); light_pin_mux(AOGPIO_10,1); light_pin_mux(AOGPIO_11,1); light_pin_mux(AOGPIO_12,1); light_pin_mux(AOGPIO_13,1); + light_pin_mux(AOGPIO_14, 0); light_pin_mux(AUDIO_PA30,3); /*qspi1 cs0 gpio0-1 pad strength and pin-pull mode*/ @@ -2525,3 +2534,208 @@ U_BOOT_CMD( "check ethaddrs in environment variables is valid", "" ); + + +#define PAGE_SIZE 4096 +#define HIBERNATE_SIG "S1SUSPEND" +#define HIBERNATE_SIG2 "S1SUSPEN2" //sign for 2nd time load image + +static inline int fdt_disabled_node(void *blob,const char *path) +{ + int offset; + offset = fdt_path_offset(blob,path); + if (offset < 0) { + printf("ERROR:failed to find %s node in dtb (ret %d)\n",path,offset); + return offset; + } + return fdt_status_disabled(blob,offset); +} + +static int do_board_check_hibernate(cmd_tbl_t *cmdtp, int flag, int argc, + char * const argv[]) +{ + int ret; + char runcmd[128]; + ulong addr; + void *blob = NULL; + ulong mask = 0; + int mmc_parts; + int resume_part; + bool fastresume = 0; + #define ON_RET_ERROR(str) if(ret < 0) printf("set node %s status failed %d\n",str,ret) + ALLOC_CACHE_ALIGN_BUFFER(u8,swsusp_header_buf,PAGE_SIZE); + u8 *header = &swsusp_header_buf[0]; + + mmc_parts = env_get_hex("mmcpart",3); + resume_part = mmc_parts - 2; + + if(argc >= 4) { // is user pass in ,use that + sprintf(runcmd, "read %s %s %s 0 8", + argv[1],argv[2],argv[3]); + header = (u8 *)simple_strtoul(argv[3],NULL,16); + if(argc >= 5) + mask = simple_strtoul(argv[4],NULL,16); + printf("read swsusp_header to %p,dtb disbale mask 0x%lx\n",header,mask); + } else { + sprintf(runcmd, "read mmc 0:%d 0x%lx 0 8", + resume_part,(unsigned long)&header[0]); + } + + ret = run_command(runcmd, 0); + if(ret != CMD_RET_SUCCESS) + goto failed; + if(!memcmp(HIBERNATE_SIG, &header[PAGE_SIZE-10], 10) || + !memcmp(HIBERNATE_SIG2, &header[PAGE_SIZE-10], 10) ) { + printf("found sign\n"); + } + else { + sprintf(runcmd, "0:%s",env_get("mmcbootpart")); + if(file_exists("mmc",runcmd,"no_fastresume",FS_TYPE_EXT)) { + printf("do not fastresume\n"); + goto default_set; + } + + sprintf(runcmd, "read mmc 0:%d 0x%lx 0 8", + resume_part+1,(unsigned long)&header[0]); + ret = run_command(runcmd, 0); + if(ret != CMD_RET_SUCCESS) + goto failed; + if(!memcmp(HIBERNATE_SIG, &header[PAGE_SIZE-10], 10) || + !memcmp(HIBERNATE_SIG2, &header[PAGE_SIZE-10], 10) ) { + printf("found fastresume sign\n"); + resume_part = resume_part+1; + fastresume = true; + } + else { + printf(" not find hibernate sign\n"); + goto default_set; + } + } + + /*get dtb address*/ + if(env_get("dtb_addr") == NULL) + { + printf("Cannot get dtb_addr,check flow !\n"); + goto failed; + } + addr = env_get_hex("dtb_addr",0); + sprintf(runcmd, "fdt addr 0x%lx", env_get_hex("dtb_addr",0)); + ret = run_command(runcmd, 0); + if(ret != CMD_RET_SUCCESS) + goto failed; + sprintf(runcmd, "fdt resize"); + ret = run_command(runcmd, 0); + if(ret != CMD_RET_SUCCESS) + goto failed; + + /*set unneed devices node disabled for hibernate resume in kernel dtb*/ + blob = (void *)addr; + ret = fdt_status_disabled_by_alias(blob,"i2c0"); + ON_RET_ERROR("i2c0"); + ret = fdt_status_disabled_by_alias(blob,"i2c1"); + ON_RET_ERROR("i2c1"); + ret = fdt_status_disabled_by_alias(blob,"i2c2"); + ON_RET_ERROR("i2c2"); + + ret = fdt_status_disabled_by_alias(blob,"audio_i2c0"); + ON_RET_ERROR("audio_i2c0"); + ret = fdt_status_disabled_by_alias(blob,"audio_i2c1"); + ON_RET_ERROR("audio_i2c1"); + ret = fdt_status_disabled_by_alias(blob,"ethernet0"); + ON_RET_ERROR("ethernet0"); + ret = fdt_status_disabled_by_alias(blob,"ethernet1"); + ON_RET_ERROR("ethernet1"); + ret = fdt_status_disabled_by_alias(blob,"spi0"); + ON_RET_ERROR("spi0"); + ret = fdt_status_disabled_by_alias(blob,"spi1"); + ON_RET_ERROR("spi1"); + ret = fdt_status_disabled_by_alias(blob,"spi2"); + ON_RET_ERROR("spi2"); + + ret = fdt_disabled_node(blob,"/soc/adc"); + ON_RET_ERROR("/soc/adc"); + + //default mask is 0, need set this node disbaled + if(0 == (mask & 0x01)) { + ret = fdt_disabled_node(blob,"/soc/light_i2s"); + ON_RET_ERROR("/soc/light_i2s"); + ret = fdt_disabled_node(blob,"/soc/audio_i2s0"); + ON_RET_ERROR("/soc/audio_i2s0"); + ret = fdt_disabled_node(blob,"/soc/audio_i2s1"); + ON_RET_ERROR("/soc/audio_i2s1"); + ret = fdt_disabled_node(blob,"/soc/audio_i2s2"); + ON_RET_ERROR("/soc/audio_i2s2"); + } + if(0 == (mask & 0x02)) { + ret = fdt_disabled_node(blob,"/soc/audio_i2s_8ch_sd0"); + ON_RET_ERROR("/soc/audio_i2s_8ch_sd0"); + ret = fdt_disabled_node(blob,"/soc/audio_i2s_8ch_sd1"); + ON_RET_ERROR("/soc/audio_i2s_8ch_sd1"); + ret = fdt_disabled_node(blob,"/soc/audio_i2s_8ch_sd2"); + ON_RET_ERROR("/soc/audio_i2s_8ch_sd2"); + ret = fdt_disabled_node(blob,"/soc/audio_i2s_8ch_sd3"); + ON_RET_ERROR("/soc/audio_i2s_8ch_sd3"); + } + /*set resume_bootargs for kernel do fast bootup */ + sprintf(runcmd,"resume=/dev/mmcblk0p%d notrace noftrace nopty noclkdebug ",resume_part); + env_set("resume_bootargs",runcmd); + + return CMD_RET_SUCCESS; + +default_set: + sprintf(runcmd,"resume=/dev/mmcblk0p%d",resume_part); + env_set("resume_bootargs",runcmd); + return CMD_RET_SUCCESS; + +failed: + printf("ERROR:runcmd %s failed!\n",runcmd); + sprintf(runcmd,"resume=/dev/mmcblk0p%d",resume_part); + env_set("resume_bootargs",runcmd); + return CMD_RET_FAILURE; +} + +U_BOOT_CMD( + chk_hibernate, 6, 0, do_board_check_hibernate, + "check hibernate image sign,if valid set dtb nodes and bootargs for fast boot resume", + " [ ] [mask]" +); + +#ifdef CONFIG_FIXUP_MEMORY_REGION +static int do_fixup_memory_region(cmd_tbl_t *cmdtp, int flag, int argc, + char * const argv[]) +{ + ulong addr; + void *blob = NULL; + DECLARE_GLOBAL_DATA_PTR; + u64 base, size; + + base = gd->ram_base; + size = gd->ram_size; + + /*get dtb address*/ + if(env_get("dtb_addr") == NULL) + { + printf("Cannot get dtb_addr,check flow !\n"); + return CMD_RET_FAILURE; + } + addr = env_get_hex("dtb_addr",0); + + /*set unneed devices node disabled for hibernate resume in kernel dtb*/ + blob = (void *)addr; + fdtdec_setup_mem_size_base_fdt(blob); + size -= gd->ram_base; + + if (size != gd->ram_size) { + printf("fixup memory region from [0x%09lx ~ 0x%09lx] to [0x%09lx ~ 0x%09lx]\n", + gd->ram_base, gd->ram_base+gd->ram_size, gd->ram_base, gd->ram_base+size); + gd->ram_size = size; + fdt_fixup_memory(blob, gd->ram_base, gd->ram_size); + } + return CMD_RET_SUCCESS; +} +U_BOOT_CMD( + fixup_memory_region, 2, 0, do_fixup_memory_region, + "modify linux memory region via gd->ram_size", + "" +); +#endif diff --git a/board/thead/light-c910/lpddr-regu/ddr_regu.c b/board/thead/light-c910/lpddr-regu/ddr_regu.c index 1f5a8b6a..b075b797 100644 --- a/board/thead/light-c910/lpddr-regu/ddr_regu.c +++ b/board/thead/light-c910/lpddr-regu/ddr_regu.c @@ -794,7 +794,7 @@ static void light_iopmp_config(void) } } -int pmic_ddr_regu_init(void) +int aon_local_init(void) { #define AON_PADMUX_BASE (0xfffff4a000) int ret; diff --git a/board/thead/light-c910/lpddr-regu/ddr_regu.h b/board/thead/light-c910/lpddr-regu/ddr_regu.h index 9f7c1570..1da3252e 100644 --- a/board/thead/light-c910/lpddr-regu/ddr_regu.h +++ b/board/thead/light-c910/lpddr-regu/ddr_regu.h @@ -9,5 +9,5 @@ #define __DDR_REGU_H__ int pmic_ddr_set_voltage(void); -int pmic_ddr_regu_init(void); +int aon_local_init(void); #endif diff --git a/board/thead/light-c910/lpddr4/include/aonsys_reg_define.h b/board/thead/light-c910/lpddr4/include/aonsys_reg_define.h new file mode 100644 index 00000000..8531c5a2 --- /dev/null +++ b/board/thead/light-c910/lpddr4/include/aonsys_reg_define.h @@ -0,0 +1,218 @@ +//------------------------------------------------------------ +// DONOT MODIFY THIS FILE +// generated by JISHENGJU automatically +//------------------------------------------------------------ + +#ifndef AONSYS_SYSREG_REG_OFFSET_DEFINE_H +#define AONSYS_SYSREG_REG_OFFSET_DEFINE_H + +#define AONSYS_REG_BASE 0xFFFFF48000 + +#define REG_AON_CPU_LP_MODE (AONSYS_REG_BASE + 0x0 ) +#define REG_AON_CHIP_LP_MODE (AONSYS_REG_BASE + 0x4 ) +#define REG_AON_AO_SERAM_TRN (AONSYS_REG_BASE + 0x10 ) +#define REG_AON_AO_SERAM_INT (AONSYS_REG_BASE + 0x14 ) +#define REG_AON_STR_SERAM_TRN (AONSYS_REG_BASE + 0x18 ) +#define REG_AON_STR_SERAM_INT (AONSYS_REG_BASE + 0x1c ) +#define REG_AON_STR_INDICATOR_0 (AONSYS_REG_BASE + 0x20 ) +#define REG_AON_STR_INDICATOR_1 (AONSYS_REG_BASE + 0x24 ) +#define REG_AON_STR_INDICATOR_2 (AONSYS_REG_BASE + 0x28 ) +#define REG_AON_STR_INDICATOR_3 (AONSYS_REG_BASE + 0x2c ) +#define REG_AON_PVTC_WR_LOCK (AONSYS_REG_BASE + 0x30 ) +#define REG_AON_PVTC_TS_ALARM (AONSYS_REG_BASE + 0x34 ) +#define REG_AON_PVTC_VM_ALARM (AONSYS_REG_BASE + 0x38 ) +#define REG_AON_PVTC_PD_ALARM (AONSYS_REG_BASE + 0x3c ) +#define REG_AON_E902_CNT_CLR (AONSYS_REG_BASE + 0x40 ) +#define REG_AON_E902_RST_ADDR (AONSYS_REG_BASE + 0x44 ) +#define REG_AON_C906_RST_ADDR_L (AONSYS_REG_BASE + 0x48 ) +#define REG_AON_C906_RST_ADDR_H (AONSYS_REG_BASE + 0x4c ) +#define REG_AON_RESERVED_REG_0 (AONSYS_REG_BASE + 0x50 ) +#define REG_AON_RESERVED_REG_1 (AONSYS_REG_BASE + 0x54 ) +#define REG_AON_RESERVED_REG_2 (AONSYS_REG_BASE + 0x58 ) +#define REG_AON_RESERVED_REG_3 (AONSYS_REG_BASE + 0x5c ) +#define REG_AON_AON_AHB_ADEXT (AONSYS_REG_BASE + 0x60 ) +#define REG_AON_RC_EN (AONSYS_REG_BASE + 0x70 ) +#define REG_AON_RC_FCAL (AONSYS_REG_BASE + 0x74 ) +#define REG_AON_RC_MODE (AONSYS_REG_BASE + 0x78 ) +#define REG_AON_RC_READY (AONSYS_REG_BASE + 0x7c ) +#define REG_AON_ISO_CFG (AONSYS_REG_BASE + 0x80 ) +#define REG_AON_OCRAM_ERR (AONSYS_REG_BASE + 0x90 ) +#define REG_AON_TIMER_LINK (AONSYS_REG_BASE + 0x100) +#define REG_AON_PD_REQ (AONSYS_REG_BASE + 0x110) +#define REG_AON_PD_ISO_EN_SET (AONSYS_REG_BASE + 0x114) +#define REG_AON_PD_ISO_EN_CLR (AONSYS_REG_BASE + 0x118) +#define REG_AON_PD_SW_EN_SET (AONSYS_REG_BASE + 0x11c) +#define REG_AON_PD_SW_EN_CLR (AONSYS_REG_BASE + 0x120) +#define REG_AON_PD_SW_ACK (AONSYS_REG_BASE + 0x124) +#define REG_AON_PD_SW_CNT_EN (AONSYS_REG_BASE + 0x128) +#define REG_AON_PD_FSM_RST (AONSYS_REG_BASE + 0x12c) +#define REG_AON_PD_INT_MASK (AONSYS_REG_BASE + 0x130) +#define REG_AON_PD_FSM_STS_L (AONSYS_REG_BASE + 0x134) +#define REG_AON_PD_FSM_STS_H (AONSYS_REG_BASE + 0x138) +#define REG_AON_PD_INT_STS (AONSYS_REG_BASE + 0x13c) +#define REG_AON_PD_INT_CLR (AONSYS_REG_BASE + 0x140) +#define REG_AON_PD_BLK0_SW_CNT (AONSYS_REG_BASE + 0x144) +#define REG_AON_PD_BLK1_SW_CNT (AONSYS_REG_BASE + 0x148) +#define REG_AON_PD_BLK2_SW_CNT (AONSYS_REG_BASE + 0x14c) +#define REG_AON_PD_BLK3_SW_CNT (AONSYS_REG_BASE + 0x150) +#define REG_AON_PD_BLK4_SW_CNT (AONSYS_REG_BASE + 0x154) +#define REG_AON_PD_BLK5_SW_CNT (AONSYS_REG_BASE + 0x158) +#define REG_AON_PD_BLK6_SW_CNT (AONSYS_REG_BASE + 0x15c) +#define REG_AON_PD_BLK7_SW_CNT (AONSYS_REG_BASE + 0x160) +#define REG_AON_PD_BLK8_SW_CNT (AONSYS_REG_BASE + 0x164) +#define REG_AON_PD_BLK9_SW_CNT (AONSYS_REG_BASE + 0x168) +#define REG_AON_PD_BLK10_SW_CNT (AONSYS_REG_BASE + 0x16c) +#define REG_AON_PD_BLK0_INTV_CNT (AONSYS_REG_BASE + 0x180) +#define REG_AON_PD_BLK1_INTV_CNT (AONSYS_REG_BASE + 0x184) +#define REG_AON_PD_BLK2_INTV_CNT (AONSYS_REG_BASE + 0x188) +#define REG_AON_PD_BLK3_INTV_CNT (AONSYS_REG_BASE + 0x18c) +#define REG_AON_PD_BLK4_INTV_CNT (AONSYS_REG_BASE + 0x190) +#define REG_AON_PD_BLK5_INTV_CNT (AONSYS_REG_BASE + 0x194) +#define REG_AON_PD_BLK6_INTV_CNT (AONSYS_REG_BASE + 0x198) +#define REG_AON_PD_BLK7_INTV_CNT (AONSYS_REG_BASE + 0x19c) +#define REG_AON_PD_BLK8_INTV_CNT (AONSYS_REG_BASE + 0x1a0) +#define REG_AON_PD_BLK9_INTV_CNT (AONSYS_REG_BASE + 0x1a4) +#define REG_AON_PD_BLK10_INTV_CNT (AONSYS_REG_BASE + 0x1a8) +#define REG_AON_AUDIO_PMU_REQ (AONSYS_REG_BASE + 0x1f8) +#define REG_AON_AUDIO_PMU_STS (AONSYS_REG_BASE + 0x1fc) +#define REG_AON_AUDIO_PMU_INTR (AONSYS_REG_BASE + 0x204) +#define REG_AON_PMU_AUDIO_REQ (AONSYS_REG_BASE + 0x208) +#define REG_AON_PMU_AUDIO_STS (AONSYS_REG_BASE + 0x20c) +#define REG_AON_MEM_LP_MODE (AONSYS_REG_BASE + 0x210) +#define REG_AON_C910_DBG_MASK (AONSYS_REG_BASE + 0x214) +#define REG_AON_C910_L2CACHE (AONSYS_REG_BASE + 0x218) +#define REG_AON_BISR_CTRL (AONSYS_REG_BASE + 0x220) +#define REG_AON_EFUSE_PRELOAD_DONE (AONSYS_REG_BASE + 0x224) +#define REG_AON_GPIO_RTE (AONSYS_REG_BASE + 0x228) +#define REG_AON_PLL_DSKEW_LOCK (AONSYS_REG_BASE + 0x22c) +#define REG_AON_SRAM_AXI_CFG (AONSYS_REG_BASE + 0x230) +#define REG_AON_SRAM_AXI_ST (AONSYS_REG_BASE + 0x234) +#define REG_AON_SRAM_AXI_ERR_STS_0 (AONSYS_REG_BASE + 0x238) +#define REG_AON_SRAM_AXI_ERR_STS_1 (AONSYS_REG_BASE + 0x23c) +#define REG_AON_SRAM_AXI_ERR_STS_2 (AONSYS_REG_BASE + 0x240) +#define REG_AON_SRAM_AXI_ERR_STS_3 (AONSYS_REG_BASE + 0x244) +#define REG_AON_SRAM_AXI_ERR_STS_4 (AONSYS_REG_BASE + 0x248) +#define REG_AON_SE_MUX_LOCK (AONSYS_REG_BASE + 0x24c) +#define REG_AON_CPU_DBG_DIS_LOCK (AONSYS_REG_BASE + 0x270) +#define REG_AON_RESERVED_REG_4 (AONSYS_REG_BASE + 0x300) +#define REG_AON_RESERVED_REG_5 (AONSYS_REG_BASE + 0x304) +#define REG_AON_RESERVED_REG_6 (AONSYS_REG_BASE + 0x308) +#define REG_AON_RESERVED_REG_7 (AONSYS_REG_BASE + 0x30c) +#define REG_AON_RESERVED_REG_8 (AONSYS_REG_BASE + 0x400) +#define REG_AON_RESERVED_REG_9 (AONSYS_REG_BASE + 0x404) +#define REG_AON_RESERVED_REG_10 (AONSYS_REG_BASE + 0x408) +#define REG_AON_RESERVED_REG_11 (AONSYS_REG_BASE + 0x40c) +#define REG_AON_RESERVED_REG_12 (AONSYS_REG_BASE + 0x500) +#define REG_AON_RESERVED_REG_13 (AONSYS_REG_BASE + 0x504) +#define REG_AON_RESERVED_REG_14 (AONSYS_REG_BASE + 0x508) +#define REG_AON_RESERVED_REG_15 (AONSYS_REG_BASE + 0x50c) +#define REG_AON_RESERVED_REG_16 (AONSYS_REG_BASE + 0x600) +#define REG_AON_RESERVED_REG_17 (AONSYS_REG_BASE + 0x604) +#define REG_AON_RESERVED_REG_18 (AONSYS_REG_BASE + 0x608) +#define REG_AON_RESERVED_REG_19 (AONSYS_REG_BASE + 0x60c) + +#define CPU_LP_MODE_DFLT_VAL 0x3ff +#define CHIP_LP_MODE_DFLT_VAL 0x0 +#define AO_SERAM_TRN_DFLT_VAL 0x0 +#define AO_SERAM_INT_DFLT_VAL 0x0 +#define STR_SERAM_TRN_DFLT_VAL 0x0 +#define STR_SERAM_INT_DFLT_VAL 0x0 +#define STR_INDICATOR_0_DFLT_VAL 0x0 +#define STR_INDICATOR_1_DFLT_VAL 0x0 +#define STR_INDICATOR_2_DFLT_VAL 0x0 +#define STR_INDICATOR_3_DFLT_VAL 0x0 +#define PVTC_WR_LOCK_DFLT_VAL 0x0 +#define PVTC_TS_ALARM_DFLT_VAL 0x0 +#define PVTC_VM_ALARM_DFLT_VAL 0x0 +#define PVTC_PD_ALARM_DFLT_VAL 0x0 +#define E902_CNT_CLR_DFLT_VAL 0x0 +#define E902_RST_ADDR_DFLT_VAL 0xffef8000 +#define C906_RST_ADDR_L_DFLT_VAL 0xc0000000 +#define C906_RST_ADDR_H_DFLT_VAL 0xff +#define RESERVED_REG_0_DFLT_VAL 0x0 +#define RESERVED_REG_1_DFLT_VAL 0x0 +#define RESERVED_REG_2_DFLT_VAL 0x0 +#define RESERVED_REG_3_DFLT_VAL 0x0 +#define AON_AHB_ADEXT_DFLT_VAL 0x0 +#define RC_EN_DFLT_VAL 0x1 +#define RC_FCAL_DFLT_VAL 0x77f +#define RC_MODE_DFLT_VAL 0x1 +#define RC_READY_DFLT_VAL 0x0 +#define ISO_CFG_DFLT_VAL 0x0 +#define OCRAM_ERR_DFLT_VAL 0x0 +#define TIMER_LINK_DFLT_VAL 0x0 +#define PD_REQ_DFLT_VAL 0x0 +#define PD_ISO_EN_SET_DFLT_VAL 0x0 +#define PD_ISO_EN_CLR_DFLT_VAL 0x0 +#define PD_SW_EN_SET_DFLT_VAL 0x0 +#define PD_SW_EN_CLR_DFLT_VAL 0x0 +#define PD_SW_ACK_DFLT_VAL 0x3fffff +#define PD_SW_CNT_EN_DFLT_VAL 0x0 +#define PD_FSM_RST_DFLT_VAL 0x0 +#define PD_INT_MASK_DFLT_VAL 0x3fffff +#define PD_FSM_STS_L_DFLT_VAL 0x0 +#define PD_FSM_STS_H_DFLT_VAL 0x0 +#define PD_INT_STS_DFLT_VAL 0x0 +#define PD_INT_CLR_DFLT_VAL 0x0 +#define PD_BLK0_SW_CNT_DFLT_VAL 0xff00ff +#define PD_BLK1_SW_CNT_DFLT_VAL 0xff00ff +#define PD_BLK2_SW_CNT_DFLT_VAL 0xff00ff +#define PD_BLK3_SW_CNT_DFLT_VAL 0xff00ff +#define PD_BLK4_SW_CNT_DFLT_VAL 0xff00ff +#define PD_BLK5_SW_CNT_DFLT_VAL 0xff00ff +#define PD_BLK6_SW_CNT_DFLT_VAL 0xff00ff +#define PD_BLK7_SW_CNT_DFLT_VAL 0xff00ff +#define PD_BLK8_SW_CNT_DFLT_VAL 0xff00ff +#define PD_BLK9_SW_CNT_DFLT_VAL 0xff00ff +#define PD_BLK10_SW_CNT_DFLT_VAL 0xff00ff +#define PD_BLK0_INTV_CNT_DFLT_VAL 0xff0ffff +#define PD_BLK1_INTV_CNT_DFLT_VAL 0xff0ffff +#define PD_BLK2_INTV_CNT_DFLT_VAL 0xff0ffff +#define PD_BLK3_INTV_CNT_DFLT_VAL 0xff0ffff +#define PD_BLK4_INTV_CNT_DFLT_VAL 0xff0ffff +#define PD_BLK5_INTV_CNT_DFLT_VAL 0xff0ffff +#define PD_BLK6_INTV_CNT_DFLT_VAL 0xff0ffff +#define PD_BLK7_INTV_CNT_DFLT_VAL 0xff0ffff +#define PD_BLK8_INTV_CNT_DFLT_VAL 0xff0ffff +#define PD_BLK9_INTV_CNT_DFLT_VAL 0xff0ffff +#define PD_BLK10_INTV_CNT_DFLT_VAL 0xff0ffff +#define AUDIO_PMU_REQ_DFLT_VAL 0x0 +#define AUDIO_PMU_STS_DFLT_VAL 0x0 +#define AUDIO_PMU_INTR_DFLT_VAL 0x0 +#define PMU_AUDIO_REQ_DFLT_VAL 0x0 +#define PMU_AUDIO_STS_DFLT_VAL 0x0 +#define MEM_LP_MODE_DFLT_VAL 0x0 +#define C910_DBG_MASK_DFLT_VAL 0x0 +#define C910_L2CACHE_DFLT_VAL 0x0 +#define BISR_CTRL_DFLT_VAL 0x0 +#define EFUSE_PRELOAD_DONE_DFLT_VAL 0x0 +#define GPIO_RTE_DFLT_VAL 0x0 +#define PLL_DSKEW_LOCK_DFLT_VAL 0x0 +#define SRAM_AXI_CFG_DFLT_VAL 0x0 +#define SRAM_AXI_ST_DFLT_VAL 0x0 +#define SRAM_AXI_ERR_STS_0_DFLT_VAL 0x0 +#define SRAM_AXI_ERR_STS_1_DFLT_VAL 0x0 +#define SRAM_AXI_ERR_STS_2_DFLT_VAL 0x0 +#define SRAM_AXI_ERR_STS_3_DFLT_VAL 0x0 +#define SRAM_AXI_ERR_STS_4_DFLT_VAL 0x0 +#define SE_MUX_LOCK_DFLT_VAL 0x0 +#define CPU_DBG_DIS_LOCK_DFLT_VAL 0x0 +#define RESERVED_REG_4_DFLT_VAL 0x0 +#define RESERVED_REG_5_DFLT_VAL 0x0 +#define RESERVED_REG_6_DFLT_VAL 0x0 +#define RESERVED_REG_7_DFLT_VAL 0x0 +#define RESERVED_REG_8_DFLT_VAL 0x0 +#define RESERVED_REG_9_DFLT_VAL 0x0 +#define RESERVED_REG_10_DFLT_VAL 0x0 +#define RESERVED_REG_11_DFLT_VAL 0x0 +#define RESERVED_REG_12_DFLT_VAL 0x0 +#define RESERVED_REG_13_DFLT_VAL 0x0 +#define RESERVED_REG_14_DFLT_VAL 0x0 +#define RESERVED_REG_15_DFLT_VAL 0x0 +#define RESERVED_REG_16_DFLT_VAL 0x0 +#define RESERVED_REG_17_DFLT_VAL 0x0 +#define RESERVED_REG_18_DFLT_VAL 0x0 +#define RESERVED_REG_19_DFLT_VAL 0x0 + + +#endif diff --git a/board/thead/light-c910/lpddr4/include/aonsys_rstget_reg_define.h b/board/thead/light-c910/lpddr4/include/aonsys_rstget_reg_define.h new file mode 100644 index 00000000..f5662b3b --- /dev/null +++ b/board/thead/light-c910/lpddr4/include/aonsys_rstget_reg_define.h @@ -0,0 +1,90 @@ +//------------------------------------------------------------ +// DONOT MODIFY THIS FILE +// generated by JISHENGJU automatically +//------------------------------------------------------------ + +#ifndef AONSYS_RSTGEN_REG_OFFSET_DEFINE_H +#define AONSYS_RSTGEN_REG_OFFSET_DEFINE_H + +#define AONSYS_RSTGEN_REG_BASE 0xFFFFF44000 + +#define REG_AON_RST_CNT (AONSYS_RSTGEN_REG_BASE + 0x0 ) +#define REG_AON_SYS_RST_CFG (AONSYS_RSTGEN_REG_BASE + 0x10 ) +#define REG_AON_RTC_RST_CFG (AONSYS_RSTGEN_REG_BASE + 0x14 ) +#define REG_AON_AOGPIO_RST_CFG (AONSYS_RSTGEN_REG_BASE + 0x18 ) +#define REG_AON_AOI2C_RST_CFG (AONSYS_RSTGEN_REG_BASE + 0x1c ) +#define REG_AON_PVTC_RST_CFG (AONSYS_RSTGEN_REG_BASE + 0x20 ) +#define REG_AON_E902_RST_CFG (AONSYS_RSTGEN_REG_BASE + 0x24 ) +#define REG_AON_AOTIMER_RST_CFG (AONSYS_RSTGEN_REG_BASE + 0x28 ) +#define REG_AON_AOWDT_RST_CFG (AONSYS_RSTGEN_REG_BASE + 0x2c ) +#define REG_AON_APSYS_RST_CFG (AONSYS_RSTGEN_REG_BASE + 0x30 ) +#define REG_AON_NPUSYS_RST_CFG (AONSYS_RSTGEN_REG_BASE + 0x34 ) +#define REG_AON_DDRSYS_RST_CFG (AONSYS_RSTGEN_REG_BASE + 0x38 ) +#define REG_AON_AUDIO_RST_CFG (AONSYS_RSTGEN_REG_BASE + 0x3c ) +#define REG_AON_BISR_RST_CFG (AONSYS_RSTGEN_REG_BASE + 0x50 ) +#define REG_AON_DSP0_RST_CFG (AONSYS_RSTGEN_REG_BASE + 0x54 ) +#define REG_AON_DSP1_RST_CFG (AONSYS_RSTGEN_REG_BASE + 0x58 ) +#define REG_AON_GPU_RST_CFG (AONSYS_RSTGEN_REG_BASE + 0x5c ) +#define REG_AON_VDEC_RST_CFG (AONSYS_RSTGEN_REG_BASE + 0x60 ) +#define REG_AON_VENC_RST_CFG (AONSYS_RSTGEN_REG_BASE + 0x64 ) +#define REG_AON_ADC_RST_CFG (AONSYS_RSTGEN_REG_BASE + 0x70 ) +#define REG_AON_AUDGPIO_RST_CFG (AONSYS_RSTGEN_REG_BASE + 0x74 ) +#define REG_AON_AOUART_RST_CFG (AONSYS_RSTGEN_REG_BASE + 0x78 ) +#define REG_AON_RST_CLR_0 (AONSYS_RSTGEN_REG_BASE + 0x100 ) +#define REG_AON_RST_CLR_1 (AONSYS_RSTGEN_REG_BASE + 0x104 ) +#define REG_AON_RST_CLR_2 (AONSYS_RSTGEN_REG_BASE + 0x108 ) +#define REG_AON_RST_CLR_3 (AONSYS_RSTGEN_REG_BASE + 0x10c ) +#define REG_AON_RST_CLR_4 (AONSYS_RSTGEN_REG_BASE + 0x110 ) +#define REG_AON_RST_STS_0 (AONSYS_RSTGEN_REG_BASE + 0x120 ) +#define REG_AON_RST_STS_1 (AONSYS_RSTGEN_REG_BASE + 0x124 ) +#define REG_AON_RST_STS_2 (AONSYS_RSTGEN_REG_BASE + 0x128 ) +#define REG_AON_RST_STS_3 (AONSYS_RSTGEN_REG_BASE + 0x12c ) +#define REG_AON_RST_STS_4 (AONSYS_RSTGEN_REG_BASE + 0x130 ) +#define REG_AON_RST_REQ_EN_0 (AONSYS_RSTGEN_REG_BASE + 0x140 ) +#define REG_AON_RST_REQ_EN_1 (AONSYS_RSTGEN_REG_BASE + 0x144 ) +#define REG_AON_RST_REQ_EN_2 (AONSYS_RSTGEN_REG_BASE + 0x148 ) +#define REG_AON_RST_REQ_EN_3 (AONSYS_RSTGEN_REG_BASE + 0x14c ) +#define REG_AON_SRAM_AXI_RST_CFG (AONSYS_RSTGEN_REG_BASE + 0x11f4) +#define REG_AON_SE_RST_CFG (AONSYS_RSTGEN_REG_BASE + 0x160 ) + +#define RST_CNT_DFLT_VAL 0xf0f +#define SYS_RST_CFG_DFLT_VAL 0x0 +#define RTC_RST_CFG_DFLT_VAL 0x3 +#define AOGPIO_RST_CFG_DFLT_VAL 0x3 +#define AOI2C_RST_CFG_DFLT_VAL 0x1 +#define PVTC_RST_CFG_DFLT_VAL 0x1 +#define E902_RST_CFG_DFLT_VAL 0x2 +#define AOTIMER_RST_CFG_DFLT_VAL 0x3 +#define AOWDT_RST_CFG_DFLT_VAL 0x1 +#define APSYS_RST_CFG_DFLT_VAL 0x1 +#define NPUSYS_RST_CFG_DFLT_VAL 0x1 +#define DDRSYS_RST_CFG_DFLT_VAL 0x1 +#define AUDIO_RST_CFG_DFLT_VAL 0x0 +#define BISR_RST_CFG_DFLT_VAL 0x3 +#define DSP0_RST_CFG_DFLT_VAL 0x1 +#define DSP1_RST_CFG_DFLT_VAL 0x1 +#define GPU_RST_CFG_DFLT_VAL 0x1 +#define VDEC_RST_GEN_RST_CFG_DFLT_VAL 0x1 +#define VENC_RST_CFG_DFLT_VAL 0x1 +#define ADC_RST_CFG_DFLT_VAL 0x1 +#define AUDGPIO_RST_CFG_DFLT_VAL 0x3 +#define AOUART_RST_CFG_DFLT_VAL 0x3 +#define RST_CLR_0_DFLT_VAL 0x0 +#define RST_CLR_1_DFLT_VAL 0x0 +#define RST_CLR_2_DFLT_VAL 0x0 +#define RST_CLR_3_DFLT_VAL 0x0 +#define RST_CLR_4_DFLT_VAL 0x0 +#define RST_STS_0_DFLT_VAL 0x0 +#define RST_STS_1_DFLT_VAL 0x0 +#define RST_STS_2_DFLT_VAL 0x0 +#define RST_STS_3_DFLT_VAL 0x0 +#define RST_STS_4_DFLT_VAL 0x0 +#define RST_REQ_EN_0_DFLT_VAL 0x11100 +#define RST_REQ_EN_1_DFLT_VAL 0xbb000000 +#define RST_REQ_EN_2_DFLT_VAL 0x0 +#define RST_REQ_EN_3_DFLT_VAL 0x0 +#define SRAM_AXI_RST_CFG_DFLT_VAL 0x5f +#define SE_RST_CFG_DFLT_VAL 0x1 + + +#endif diff --git a/board/thead/light-c910/lpddr4/include/common_lib.h b/board/thead/light-c910/lpddr4/include/common_lib.h index b82a3c1f..90ac48ab 100644 --- a/board/thead/light-c910/lpddr4/include/common_lib.h +++ b/board/thead/light-c910/lpddr4/include/common_lib.h @@ -7,6 +7,8 @@ #include "ddr_reg_define.h" #include "ddr_sysreg_registers_struct.h" #include "ddr_sysreg_registers.h" +#include "aonsys_reg_define.h" +#include "aonsys_rstget_reg_define.h" #include "define_ddr.h" #include "DWC_ddr_umctl2_c_struct.h" #include "DWC_ddr_umctl2_header.h" diff --git a/board/thead/light-c910/lpddr4/include/ddr_common_func.h b/board/thead/light-c910/lpddr4/include/ddr_common_func.h index de600b32..b7ca1529 100644 --- a/board/thead/light-c910/lpddr4/include/ddr_common_func.h +++ b/board/thead/light-c910/lpddr4/include/ddr_common_func.h @@ -15,6 +15,9 @@ enum DDR_BITWIDTH { unsigned long get_ddr_density(void); enum DDR_TYPE get_ddr_type(void); +int get_ddr_rank_number(void); +int get_ddr_freq(void); +enum DDR_BITWIDTH get_ddr_bitwidth(void); void ddr_sysreg_wr(unsigned long int addr,unsigned int wr_data); unsigned int ddr_sysreg_rd(unsigned long int addr); @@ -49,4 +52,8 @@ void addrmap(int rank_num, enum DDR_BITWIDTH bits); void ctrl_en(enum DDR_BITWIDTH bits); void enable_auto_refresh(void); void lpddr4_auto_selref(void); +int lpddr4_query_boundary(enum DDR_TYPE type, int rank_num, int speed, + enum DDR_BITWIDTH bits, unsigned long size); +int lpddr4_reinit_ctrl(enum DDR_TYPE type, int rank_num, int speed, + enum DDR_BITWIDTH bits, unsigned long size); #endif // DDR_COMMON_FUNCE_H diff --git a/board/thead/light-c910/lpddr4/include/ddr_retention.h b/board/thead/light-c910/lpddr4/include/ddr_retention.h new file mode 100644 index 00000000..0268bd38 --- /dev/null +++ b/board/thead/light-c910/lpddr4/include/ddr_retention.h @@ -0,0 +1,35 @@ +#ifndef DDR_RETENTION_H +#define DDR_RETENTION_H + +///data structure to store ddr misc register address, value +typedef struct Reg_Misc_Addr_Val { + uint32_t Address; ///< register address + uint32_t Value; ///< register value +} Reg_Misc_Addr_Val_t; + +///data structure to store register address, value pairs +typedef struct Reg_Phy_Addr_Val { + uint32_t Address; ///< register address + uint16_t Value0; ///< register value phy0 + uint16_t Value1; ///< register value phy1 +} Reg_Phy_Addr_Val_t; + +/// enumeration of instructions for PhyInit Register Interface +typedef enum { + saveRegs, ///< save(read) tracked register values + restoreRegs, ///< restore (write) saved register values +} regInstr; + +// typedef struct Reg_Addr_Value { +// uint32_t reg_num; +// Reg_Addr_Val_t reg[0]; +// } Reg_Addr_Value_t; + +typedef struct Ddr_Reg_Config { + uint32_t misc_reg_num; + uint32_t phy_reg_num; +} Ddr_Reg_Config_t; + +int dwc_ddrphy_phyinit_regInterface(regInstr myRegInstr); + +#endif diff --git a/board/thead/light-c910/lpddr4/src/ddr_common_func.c b/board/thead/light-c910/lpddr4/src/ddr_common_func.c index a9073310..5d127008 100644 --- a/board/thead/light-c910/lpddr4/src/ddr_common_func.c +++ b/board/thead/light-c910/lpddr4/src/ddr_common_func.c @@ -2,9 +2,14 @@ #include #include "../include/common_lib.h" #include "../include/ddr_common_func.h" +#include "../include/ddr_retention.h" DDR_SYSREG_REG_SW_REG_S ddr_sysreg; +#ifdef CONFIG_DDR_MSG +#define DDR_DEBUG(x) printf(x) +#endif + #ifndef CONFIG_DDR_RANK_SIZE #define CONFIG_DDR_RANK_SIZE SZ_4G #endif @@ -34,6 +39,44 @@ enum DDR_TYPE get_ddr_type() { #endif // #ifdef CONFIG_LPDDR4X } +int get_ddr_rank_number() { +#ifdef CONFIG_DDR_SINGLE_RANK + return 1; +#elif defined CONFIG_DDR_DUAL_RANK + return 2; +#else +#ifdef CONFIG_DDR_MSG + DDR_DEBUG("unsupported ddr rank type!!!\n"); +#endif + return NULL; +#endif +} + +int get_ddr_freq() { +#ifdef CONFIG_DDR_4266 + return 4266; +#elif CONFIG_DDR_3733 + return 3733; +#elif CONFIG_DDR_3200 + return 3200; +#elif CONFIG_DDR_2133 + return 2133; +#else + printf("unsupport lpddr4 freq!!!\n"); + return -1; +#endif +} + +enum DDR_BITWIDTH get_ddr_bitwidth() { +#ifdef CONFIG_DDR_H32_MODE + return DDR_BITWIDTH_32; +#elif CONFIG_DDR_H16_MODE + return DDR_BITWIDTH_16; +#else + return DDR_BITWIDTH_64; +#endif +} + void ddr_sysreg_wr(unsigned long int addr,unsigned int wr_data) { wr(addr+DDR_SYSREG_BADDR,wr_data); } @@ -104,75 +147,114 @@ unsigned int ddr_phy_reg_rd(unsigned long int addr) { void lp4_mrw(int addr, int wdata,int dch,int rank) { DWC_DDR_UMCTL2_C_STRUCT_REG_S umctl2_reg; + uint32_t val_t0,val_t1; if(dch==0) { - umctl2_reg.dwc_ddr_umctl2_c_struct_mrctrl0.u32 = rd(MRCTRL0); - //umctl2_reg.dwc_ddr_umctl2_c_struct_mrctrl0.mr_addr = addr; //do not care for lp4 - umctl2_reg.dwc_ddr_umctl2_c_struct_mrctrl0.mr_rank = rank;//rank0 only - umctl2_reg.dwc_ddr_umctl2_c_struct_mrctrl0.mr_type = 0;//write - wr(MRCTRL0,umctl2_reg.dwc_ddr_umctl2_c_struct_mrctrl0.u32); + while ((rd(MRSTAT) & 0x1) == 0x1); + umctl2_reg.dwc_ddr_umctl2_c_struct_mrctrl0.u32 = rd(MRCTRL0); + //umctl2_reg.dwc_ddr_umctl2_c_struct_mrctrl0.mr_addr = addr; //do not care for lp4 + umctl2_reg.dwc_ddr_umctl2_c_struct_mrctrl0.mr_rank = rank;//rank0 only + umctl2_reg.dwc_ddr_umctl2_c_struct_mrctrl0.mr_type = 0;//write + wr(MRCTRL0, umctl2_reg.dwc_ddr_umctl2_c_struct_mrctrl0.u32); - umctl2_reg.dwc_ddr_umctl2_c_struct_mrctrl1.u32 = rd(MRCTRL1); - umctl2_reg.dwc_ddr_umctl2_c_struct_mrctrl1.mr_data = (addr<<8) | (wdata&0xFF); - wr(MRCTRL1,umctl2_reg.dwc_ddr_umctl2_c_struct_mrctrl1.u32); - - umctl2_reg.dwc_ddr_umctl2_c_struct_mrctrl0.u32 = rd(MRCTRL0); - umctl2_reg.dwc_ddr_umctl2_c_struct_mrctrl0.mr_wr = 1;//trigger wr/rd - wr(MRCTRL0,umctl2_reg.dwc_ddr_umctl2_c_struct_mrctrl0.u32); + umctl2_reg.dwc_ddr_umctl2_c_struct_mrctrl1.u32 = rd(MRCTRL1); + umctl2_reg.dwc_ddr_umctl2_c_struct_mrctrl1.mr_data = (addr << 8) | (wdata & 0xFF); + wr(MRCTRL1, umctl2_reg.dwc_ddr_umctl2_c_struct_mrctrl1.u32); + + umctl2_reg.dwc_ddr_umctl2_c_struct_mrctrl1.u32 = rd(MRCTRL1); + umctl2_reg.dwc_ddr_umctl2_c_struct_mrctrl1.mr_data = (addr << 8) | (wdata & 0xFF); + wr(MRCTRL1, umctl2_reg.dwc_ddr_umctl2_c_struct_mrctrl1.u32); + + umctl2_reg.dwc_ddr_umctl2_c_struct_mrctrl0.u32 = rd(MRCTRL0); + umctl2_reg.dwc_ddr_umctl2_c_struct_mrctrl0.mr_wr = 1;//trigger wr/rd + wr(MRCTRL0, umctl2_reg.dwc_ddr_umctl2_c_struct_mrctrl0.u32); + + //udelay(10); + //delay 5us + val_t0=rd(0xFFF4D004); + val_t1=rd(0xFFF4D004); + while((val_t0-val_t1)<200){val_t1=rd(0xFFF4D004);}; + + while ((rd(MRSTAT) & 0x1) == 0x1); } else { - umctl2_reg.dwc_ddr_umctl2_c_struct_mrctrl0.u32 = rd(MRCTRL0_DCH1); - //umctl2_reg.dwc_ddr_umctl2_c_struct_mrctrl0.mr_addr = addr; //do not care for lp4 - umctl2_reg.dwc_ddr_umctl2_c_struct_mrctrl0.mr_rank = rank;//rank0 only - umctl2_reg.dwc_ddr_umctl2_c_struct_mrctrl0.mr_type = 0;//write - wr(MRCTRL0_DCH1,umctl2_reg.dwc_ddr_umctl2_c_struct_mrctrl0.u32); + while ((rd(MRSTAT_DCH1) & 0x1) == 0x1); + umctl2_reg.dwc_ddr_umctl2_c_struct_mrctrl0.u32 = rd(MRCTRL0_DCH1); + //umctl2_reg.dwc_ddr_umctl2_c_struct_mrctrl0.mr_addr = addr; //do not care for lp4 + umctl2_reg.dwc_ddr_umctl2_c_struct_mrctrl0.mr_rank = rank;//rank0 only + umctl2_reg.dwc_ddr_umctl2_c_struct_mrctrl0.mr_type = 0;//write + wr(MRCTRL0_DCH1, umctl2_reg.dwc_ddr_umctl2_c_struct_mrctrl0.u32); - umctl2_reg.dwc_ddr_umctl2_c_struct_mrctrl1.u32 = rd(MRCTRL1_DCH1); - umctl2_reg.dwc_ddr_umctl2_c_struct_mrctrl1.mr_data = (addr<<8) | (wdata&0xFF); - wr(MRCTRL1_DCH1,umctl2_reg.dwc_ddr_umctl2_c_struct_mrctrl1.u32); - - umctl2_reg.dwc_ddr_umctl2_c_struct_mrctrl0.u32 = rd(MRCTRL0_DCH1); - umctl2_reg.dwc_ddr_umctl2_c_struct_mrctrl0.mr_wr = 1;//trigger wr/rd - wr(MRCTRL0_DCH1,umctl2_reg.dwc_ddr_umctl2_c_struct_mrctrl0.u32); - } + umctl2_reg.dwc_ddr_umctl2_c_struct_mrctrl1.u32 = rd(MRCTRL1_DCH1); + umctl2_reg.dwc_ddr_umctl2_c_struct_mrctrl1.mr_data = (addr << 8) | (wdata & 0xFF); + wr(MRCTRL1_DCH1, umctl2_reg.dwc_ddr_umctl2_c_struct_mrctrl1.u32); + + + umctl2_reg.dwc_ddr_umctl2_c_struct_mrctrl1.u32 = rd(MRCTRL1_DCH1); + umctl2_reg.dwc_ddr_umctl2_c_struct_mrctrl1.mr_data = (addr << 8) | (wdata & 0xFF); + wr(MRCTRL1_DCH1, umctl2_reg.dwc_ddr_umctl2_c_struct_mrctrl1.u32); + + umctl2_reg.dwc_ddr_umctl2_c_struct_mrctrl0.u32 = rd(MRCTRL0_DCH1); + umctl2_reg.dwc_ddr_umctl2_c_struct_mrctrl0.mr_wr = 1;//trigger wr/rd + wr(MRCTRL0_DCH1, umctl2_reg.dwc_ddr_umctl2_c_struct_mrctrl0.u32); + + //udelay(10); + //delay 5us + val_t0=rd(0xFFF4D004); + val_t1=rd(0xFFF4D004); + while((val_t0-val_t1)<200){val_t1=rd(0xFFF4D004);}; + while ((rd(MRSTAT_DCH1) & 0x1) == 0x1); } +} int lp4_mrr(int addr,int dch,int rank) { DWC_DDR_UMCTL2_C_STRUCT_REG_S umctl2_reg; if(dch==0) { - umctl2_reg.dwc_ddr_umctl2_c_struct_mrctrl0.u32 = rd(MRCTRL0); - //umctl2_reg.dwc_ddr_umctl2_c_struct_mrctrl0.mr_addr = addr; //do not care for lp4 - umctl2_reg.dwc_ddr_umctl2_c_struct_mrctrl0.mr_rank = rank;//rank0 only - umctl2_reg.dwc_ddr_umctl2_c_struct_mrctrl0.mr_type = 1;//read - wr(MRCTRL0,umctl2_reg.dwc_ddr_umctl2_c_struct_mrctrl0.u32); + umctl2_reg.dwc_ddr_umctl2_c_struct_mrctrl0.u32 = rd(MRCTRL0); + //umctl2_reg.dwc_ddr_umctl2_c_struct_mrctrl0.mr_addr = addr; //do not care for lp4 + umctl2_reg.dwc_ddr_umctl2_c_struct_mrctrl0.mr_rank = rank;//rank0 only + umctl2_reg.dwc_ddr_umctl2_c_struct_mrctrl0.mr_type = 1;//read + wr(MRCTRL0, umctl2_reg.dwc_ddr_umctl2_c_struct_mrctrl0.u32); - umctl2_reg.dwc_ddr_umctl2_c_struct_mrctrl1.u32 = rd(MRCTRL1); - umctl2_reg.dwc_ddr_umctl2_c_struct_mrctrl1.mr_data = addr<<8; - wr(MRCTRL1,umctl2_reg.dwc_ddr_umctl2_c_struct_mrctrl1.u32); - - umctl2_reg.dwc_ddr_umctl2_c_struct_mrctrl0.u32 = rd(MRCTRL0); - umctl2_reg.dwc_ddr_umctl2_c_struct_mrctrl0.mr_wr = 1;//trigger wr/rd - wr(MRCTRL0,umctl2_reg.dwc_ddr_umctl2_c_struct_mrctrl0.u32); + umctl2_reg.dwc_ddr_umctl2_c_struct_mrctrl1.u32 = rd(MRCTRL1); + umctl2_reg.dwc_ddr_umctl2_c_struct_mrctrl1.mr_data = addr << 8; + wr(MRCTRL1, umctl2_reg.dwc_ddr_umctl2_c_struct_mrctrl1.u32); - umctl2_reg.dwc_ddr_umctl2_c_struct_mrctrl1.u32 = rd(MRCTRL1); - return (umctl2_reg.dwc_ddr_umctl2_c_struct_mrctrl1.mr_data & 0xFF); + umctl2_reg.dwc_ddr_umctl2_c_struct_mrctrl1.u32 = rd(MRCTRL1); + umctl2_reg.dwc_ddr_umctl2_c_struct_mrctrl1.mr_data = addr << 8; + wr(MRCTRL1, umctl2_reg.dwc_ddr_umctl2_c_struct_mrctrl1.u32); + + + umctl2_reg.dwc_ddr_umctl2_c_struct_mrctrl0.u32 = rd(MRCTRL0); + umctl2_reg.dwc_ddr_umctl2_c_struct_mrctrl0.mr_wr = 1;//trigger wr/rd + wr(MRCTRL0, umctl2_reg.dwc_ddr_umctl2_c_struct_mrctrl0.u32); + + udelay(20); + while ((rd(MRSTAT) & 0x1) == 0x1); + return ddr_sysreg_rd(MRR_STS_CH0); } else { - umctl2_reg.dwc_ddr_umctl2_c_struct_mrctrl0.u32 = rd(MRCTRL0_DCH1); - //umctl2_reg.dwc_ddr_umctl2_c_struct_mrctrl0.mr_addr = addr; //do not care for lp4 - umctl2_reg.dwc_ddr_umctl2_c_struct_mrctrl0.mr_rank = rank;//rank0 only - umctl2_reg.dwc_ddr_umctl2_c_struct_mrctrl0.mr_type = 1;//read - wr(MRCTRL0_DCH1,umctl2_reg.dwc_ddr_umctl2_c_struct_mrctrl0.u32); + umctl2_reg.dwc_ddr_umctl2_c_struct_mrctrl0.u32 = rd(MRCTRL0_DCH1); + //umctl2_reg.dwc_ddr_umctl2_c_struct_mrctrl0.mr_addr = addr; //do not care for lp4 + umctl2_reg.dwc_ddr_umctl2_c_struct_mrctrl0.mr_rank = rank;//rank0 only + umctl2_reg.dwc_ddr_umctl2_c_struct_mrctrl0.mr_type = 1;//read + wr(MRCTRL0_DCH1, umctl2_reg.dwc_ddr_umctl2_c_struct_mrctrl0.u32); - umctl2_reg.dwc_ddr_umctl2_c_struct_mrctrl1.u32 = rd(MRCTRL1_DCH1); - umctl2_reg.dwc_ddr_umctl2_c_struct_mrctrl1.mr_data = addr<<8; - wr(MRCTRL1_DCH1,umctl2_reg.dwc_ddr_umctl2_c_struct_mrctrl1.u32); - - umctl2_reg.dwc_ddr_umctl2_c_struct_mrctrl0.u32 = rd(MRCTRL0_DCH1); - umctl2_reg.dwc_ddr_umctl2_c_struct_mrctrl0.mr_wr = 1;//trigger wr/rd - wr(MRCTRL0_DCH1,umctl2_reg.dwc_ddr_umctl2_c_struct_mrctrl0.u32); + umctl2_reg.dwc_ddr_umctl2_c_struct_mrctrl1.u32 = rd(MRCTRL1_DCH1); + umctl2_reg.dwc_ddr_umctl2_c_struct_mrctrl1.mr_data = addr << 8; + wr(MRCTRL1_DCH1, umctl2_reg.dwc_ddr_umctl2_c_struct_mrctrl1.u32); - umctl2_reg.dwc_ddr_umctl2_c_struct_mrctrl1.u32 = rd(MRCTRL1_DCH1); - return (umctl2_reg.dwc_ddr_umctl2_c_struct_mrctrl1.mr_data & 0xFF); + + umctl2_reg.dwc_ddr_umctl2_c_struct_mrctrl1.u32 = rd(MRCTRL1_DCH1); + umctl2_reg.dwc_ddr_umctl2_c_struct_mrctrl1.mr_data = addr << 8; + wr(MRCTRL1_DCH1, umctl2_reg.dwc_ddr_umctl2_c_struct_mrctrl1.u32); + + umctl2_reg.dwc_ddr_umctl2_c_struct_mrctrl0.u32 = rd(MRCTRL0_DCH1); + umctl2_reg.dwc_ddr_umctl2_c_struct_mrctrl0.mr_wr = 1;//trigger wr/rd + wr(MRCTRL0_DCH1, umctl2_reg.dwc_ddr_umctl2_c_struct_mrctrl0.u32); + + udelay(20); + while ((rd(MRSTAT_DCH1) & 0x1) == 0x1); + return ddr_sysreg_rd(MRR_STS_CH1); } } @@ -236,15 +318,15 @@ unsigned int ddr_phy_reg_rd(unsigned long int addr) { if(port & 0x4) wr(PCTRL_2,0); if(port & 0x8) wr(PCTRL_3,0); if(port & 0x10) wr(PCTRL_4,0); - if(port & 0x1F) { //at least one port is not disabled - wr(DBG1,0); - wr(DBG1_DCH1,0); + while (rd(PSTAT) != 0x0); + if ((port & 0x1F) == 0x1F) { //all ports are disabled + wr(DBG1, 2); + wr(DBG1_DCH1, 2); } - else { //all ports are disabled - wr(DBG1,3); - wr(DBG1_DCH1,3); + else { //at least one port is not disabled + wr(DBG1, 0); + wr(DBG1_DCH1, 0); } - } void enable_axi_port(int port) { @@ -457,7 +539,7 @@ if(bits==64) { wr(DFITMG0,0x05a3820e);//[28:24] dft_t_ctrl_delay [22:16] dfi_t_rddate_en=RL-5 #endif wr(DFITMG1,0x000c0303); - wr(DFILPCFG0,0x0351a001); + wr(DFILPCFG0,0x0351a101); //[8]=1: enable dfi lp mode during selfref //wr(DFIUPD0,0x00400018); //[31:30]=0 use ctrlupd enable //wr(DFIUPD1,0x00b700c4); //wr(DFIUPD2,0x00000000);//[31]=0 disable phy ctrlupdate @@ -557,7 +639,7 @@ if(bits==64) { wr(DFITMG0,0x059f820c);//[28:24] dfi_t_ctrl_delay #endif wr(DFITMG1,0x000c0303);//dfi_t_wrdata_delay=tctrl+6+BL/2+trainedTdqsdly=24, may need take care cmd pipe - wr(DFILPCFG0,0x0351a001); + wr(DFILPCFG0,0x0351a101); //[8]=1: enable dfi lp mode during selfref //wr(DFIUPD0,0xc0400018); //wr(DFIUPD1,0x00b700c4); //wr(DFIUPD2,0x80000000); @@ -645,7 +727,7 @@ if(bits==64) { wr(DFITMG0,0x059b820a); //[22:16] dfi_t_rddate_en=RL-5 #endif wr(DFITMG1,0x000b0303); - wr(DFILPCFG0,0x0351a001); + wr(DFILPCFG0,0x0351a101); //[8]=1: enable dfi lp mode during selfref //wr(DFIUPD0,0xc0400018); //wr(DFIUPD1,0x00b700c4); //wr(DFIUPD2,0x80000000); @@ -730,7 +812,7 @@ if(bits==64) { wr(ZQCTL2,0x00000000); wr(DFITMG0,0x048f8206); wr(DFITMG1,0x000b0303); - wr(DFILPCFG0,0x0351a001); + wr(DFILPCFG0,0x0351a101); //[8]=1: enable dfi lp mode during selfref //wr(DFIUPD0,0xc0400018); //wr(DFIUPD1,0x00b700c4); //wr(DFIUPD2,0x80000000); @@ -856,17 +938,28 @@ if(bits==64) { #ifdef CONFIG_DDR_MSG printf("DDR 32bit mode\n"); #endif - wr(ADDRMAP0,0x001f001f); // if(rank_num==2) { - wr(ADDRMAP0,0x001f0017);//4GB +#ifdef CONFIG_DDR_DDP + wr(ADDRMAP0,0x001f0018);//max 8GB +#else + wr(ADDRMAP0,0x001f0017); //4GB +#endif + } + else { + wr(ADDRMAP0,0x001f001f); //cs_bit0: NULL } wr(ADDRMAP1,0x00080808); //bank +2 wr(ADDRMAP2,0x00000000); //col b5+5 ~ col b2 +2 wr(ADDRMAP3,0x00000000); //col b9 ~ col b6 wr(ADDRMAP4,0x00001f1f); //col b11~ col b10 wr(ADDRMAP5,0x070f0707); //row_b11 row b2_10 row b1 row b0 +6 - wr(ADDRMAP6,0x07070707); //max row 15 - wr(ADDRMAP7,0x00000f0f); + wr(ADDRMAP6,0x07070707); //row 15 + wr(ADDRMAP7,0x00000f0f); //row16: NULL +#ifdef CONFIG_DDR_DDP + if(rank_num==2) { + wr(ADDRMAP7,0x00000f07); //max row16 + } +#endif wr(ADDRMAP9,0x07070707); wr(ADDRMAP10,0x07070707); wr(ADDRMAP11,0x00000007); @@ -874,12 +967,12 @@ if(bits==64) { #ifdef CONFIG_DDR_MSG printf("DDR 64bit mode, 256B interleaving\n"); #endif - wr(ADDRMAP0,0x0004001f); // +2 + wr(ADDRMAP0,0x0004001f); //cs_bit0: NULL if(rank_num==2) { #ifdef CONFIG_DDR_DDP - wr(ADDRMAP0,0x00040019);//16GB + wr(ADDRMAP0,0x00040019);//max 16GB #else - wr(ADDRMAP0,0x00040018);//8GB + wr(ADDRMAP0,0x00040018);//8GB #endif } wr(ADDRMAP1,0x00090909); //bank +2 @@ -887,11 +980,11 @@ if(bits==64) { wr(ADDRMAP3,0x01010101); //col b9 ~ col b6 wr(ADDRMAP4,0x00001f1f); //col b11~ col b10 wr(ADDRMAP5,0x080f0808); //row_b11 row b2_10 row b1 row b0 +6 - wr(ADDRMAP6,0x08080808); + wr(ADDRMAP6,0x08080808); //row15 #ifdef CONFIG_DDR_DDP - wr(ADDRMAP7,0x00000f08); + wr(ADDRMAP7,0x00000f08); //row16 #else - wr(ADDRMAP7,0x00000f0f); + wr(ADDRMAP7,0x00000f0f); //row16: NULL #endif wr(ADDRMAP9,0x08080808); wr(ADDRMAP10,0x08080808); @@ -901,6 +994,130 @@ if(bits==64) { } } +#define MEMSIZE_MIN_MB (2*1024) +#define MEMSIZE_MAX_MB (16*1024) +#define UNIT_MB (1024*1024) +int lpddr4_query_boundary(enum DDR_TYPE type, int rank_num, int speed, + enum DDR_BITWIDTH bits, unsigned long size) +{ + if ((size < (unsigned long)MEMSIZE_MIN_MB*UNIT_MB) || + (size > (unsigned long)MEMSIZE_MAX_MB*UNIT_MB)) + goto err_ret; + + if (bits == DDR_BITWIDTH_32) {// only phy0 + if (rank_num == 2) { + if (size == 0x80000000) //2GB + goto err_ret; + else if (size == 0x100000000) //4GB + goto ret_ok; + else if (size == 0x200000000) //8GB + goto ret_ok; + else if (size == 0x400000000) //16GB + goto err_ret; + else + goto err_ret; + } + else { // single rank + if (size == 0x80000000) //2GB + goto ret_ok; + else if (size == 0x100000000) //4GB + goto err_ret; + else if (size == 0x200000000) //8GB + goto err_ret; + else if (size == 0x400000000) //16GB + goto err_ret; + else + goto err_ret; + } + } + else if (bits == DDR_BITWIDTH_64) { // phy0+phy1 + if (rank_num == 2) { + if (size == 0x80000000) //2GB + goto err_ret; + else if (size == 0x100000000) //4GB + goto err_ret; + else if (size == 0x200000000) //8GB + goto ret_ok; + else if (size == 0x400000000) //16GB + goto ret_ok; + else + goto err_ret; + } + else { // single rank + if (size == 0x80000000) //2GB + goto err_ret; + else if (size == 0x100000000) //4GB + goto ret_ok; + else if (size == 0x200000000) //8GB + goto err_ret; + else if (size == 0x400000000) //16GB + goto err_ret; + else + goto err_ret; + } + } + else { + goto err_ret; + } + +ret_ok: + return 0; + +err_ret: + return -1; +} + +int adjust_ddr_addrmap(enum DDR_TYPE type, int rank_num, int speed, + enum DDR_BITWIDTH bits, unsigned long size) +{ + if (lpddr4_query_boundary(type, rank_num, speed, bits, size) < 0) + goto err_ret; + + if (bits == DDR_BITWIDTH_32) {// only phy0 + if (rank_num == 2) { + if (size == 0x100000000) {//4GB + wr(ADDRMAP0,0x001f0017); // cs_bit0: HIF[29] + wr(ADDRMAP7,0x00000f0f); // row16: NULL + } + else if (size == 0x200000000) {//8GB + wr(ADDRMAP0,0x001f0018); // cs_bit0: HIF[30] + wr(ADDRMAP7,0x00000f07); // row16: HIF[29] + } + } + else { // single rank + if (size == 0x80000000) //2GB + wr(ADDRMAP0,0x001f001f); // cs_bit0: NULL + } + } + else if (bits == DDR_BITWIDTH_64) { // phy0+phy1 + if (rank_num == 2) { + if (size == 0x200000000) {//8GB + wr(ADDRMAP0,0x00040018); // cs_bit0: HIF[30] + wr(ADDRMAP7,0x00000f0f); // row16: NULL + } + else if (size == 0x400000000) {//16GB + wr(ADDRMAP0,0x00040019); // cs_bit0: HIF[31] + wr(ADDRMAP7,0x00000f08); // row16: HIF[30] + } + } + else { // single rank + if (size == 0x100000000) {//4GB + wr(ADDRMAP0,0x0004001f); // cs_bit0: NULL + wr(ADDRMAP7,0x00000f0f); // row16: NULL + } + } + } + else { + // nothing + } + + return 0; + +err_ret: + printf("unsupport memsize %ld\n", size); + return -1; +} + void quasi_reg_write(unsigned long int reg,int wdata) { DWC_DDR_UMCTL2_C_STRUCT_REG_S umctl2_reg; @@ -1015,11 +1232,11 @@ void lpddr4_enter_selfrefresh(int pwdn_en,int dis_dram_clk,int mode) { umctl2_reg.dwc_ddr_umctl2_c_struct_stat.u32 = rd(STAT_DCH1); if(pwdn_en) { while( umctl2_reg.dwc_ddr_umctl2_c_struct_stat.selfref_state != 2) //wait sdram enter selfrefresh-powerdown state - umctl2_reg.dwc_ddr_umctl2_c_struct_stat.u32 = rd(STAT); + umctl2_reg.dwc_ddr_umctl2_c_struct_stat.u32 = rd(STAT_DCH1); } else { while( umctl2_reg.dwc_ddr_umctl2_c_struct_stat.selfref_state != 1) //wait sdram enter selfrefresh state - umctl2_reg.dwc_ddr_umctl2_c_struct_stat.u32 = rd(STAT); + umctl2_reg.dwc_ddr_umctl2_c_struct_stat.u32 = rd(STAT_DCH1); } #ifdef CONFIG_DDR_MSG printf("[lpddr4_enter_selfrefresh]: CH1 STAT is :%x after enter selfrefresh state\n",umctl2_reg.dwc_ddr_umctl2_c_struct_stat.u32); @@ -1055,7 +1272,8 @@ void lpddr4_auto_ps_en(int pwdn_en,int selfref_en,int clock_auto_disable ) { //ddr_sysreg_wr(DDR_CFG0,0x1ff0); //ddr_sysreg_wr(DDR_CFG0,0x1ff0); ddr_sysreg.ddr_sysreg_registers_struct_ddr_cfg0.u32 = ddr_sysreg_rd(DDR_CFG0); - ddr_sysreg.ddr_sysreg_registers_struct_ddr_cfg0.rg_ctl_ddr_usw_rst_reg |= 0x1F2; + //ddr_sysreg.ddr_sysreg_registers_struct_ddr_cfg0.rg_ctl_ddr_usw_rst_reg |= 0x1F2; + ddr_sysreg.ddr_sysreg_registers_struct_ddr_cfg0.rg_ctl_ddr_usw_rst_reg |= 0x1FA; ddr_sysreg_wr(DDR_CFG0,ddr_sysreg.ddr_sysreg_registers_struct_ddr_cfg0.u32); } @@ -1075,7 +1293,7 @@ void dfi_freq_change(int dfi_freq,int skip_dram_init) { #ifdef CONFIG_DDR_MSG printf("[dfi_freq_change]: start dfi_freq_change, target dfi_freq is %x \n",dfi_freq); #endif - wr(DBG1,3); + //wr(DBG1,3); umctl2_reg.dwc_ddr_umctl2_c_struct_swctl.u32 = rd(SWCTL); umctl2_reg.dwc_ddr_umctl2_c_struct_swctl.sw_done = 0; wr(SWCTL,umctl2_reg.dwc_ddr_umctl2_c_struct_swctl.u32); @@ -1086,7 +1304,6 @@ void dfi_freq_change(int dfi_freq,int skip_dram_init) { umctl2_reg.dwc_ddr_umctl2_c_struct_dfimisc.u32 = rd(DFIMISC); umctl2_reg.dwc_ddr_umctl2_c_struct_dfimisc.dfi_frequency = dfi_freq; - umctl2_reg.dwc_ddr_umctl2_c_struct_dfimisc.dfi_init_start = 0x1; umctl2_reg.dwc_ddr_umctl2_c_struct_dfimisc.dfi_init_complete_en = 0; wr(DFIMISC,umctl2_reg.dwc_ddr_umctl2_c_struct_dfimisc.u32); @@ -1097,15 +1314,28 @@ void dfi_freq_change(int dfi_freq,int skip_dram_init) { while( umctl2_reg.dwc_ddr_umctl2_c_struct_swstat.sw_done_ack == 0) umctl2_reg.dwc_ddr_umctl2_c_struct_swctl.u32 = rd(SWSTAT); + wr(SWCTL,0x0); + umctl2_reg.dwc_ddr_umctl2_c_struct_dfimisc.u32 = rd(DFIMISC); + umctl2_reg.dwc_ddr_umctl2_c_struct_dfimisc.dfi_init_start = 0x1; + wr(DFIMISC,umctl2_reg.dwc_ddr_umctl2_c_struct_dfimisc.u32); + wr(SWCTL,0x1); + while(rd(SWSTAT)!=0x00000001); rdata = rd(DFISTAT); + while ((rdata & 0x1) != 0) //wait dfi_init_complete = 0 + rdata = rd(DFISTAT); + +#ifndef CONFIG_DDR_H32_MODE + rdata = rd(DCH1_DFISTAT); while((rdata & 0x1) != 0) //wait dfi_init_complete = 0 - rdata = rd(DFISTAT); + rdata = rd(DCH1_DFISTAT); +#endif + //change dfi clk freq here //pull down dfi_init_start umctl2_reg.dwc_ddr_umctl2_c_struct_swctl.u32 = rd(SWCTL); umctl2_reg.dwc_ddr_umctl2_c_struct_swctl.sw_done = 0; - wr(SWCTL,umctl2_reg.dwc_ddr_umctl2_c_struct_swctl.u32); - + wr(SWCTL, umctl2_reg.dwc_ddr_umctl2_c_struct_swctl.u32); + umctl2_reg.dwc_ddr_umctl2_c_struct_dfimisc.u32 = rd(DFIMISC); umctl2_reg.dwc_ddr_umctl2_c_struct_dfimisc.dfi_init_start = 0; wr(DFIMISC,umctl2_reg.dwc_ddr_umctl2_c_struct_dfimisc.u32); @@ -1119,9 +1349,17 @@ void dfi_freq_change(int dfi_freq,int skip_dram_init) { umctl2_reg.dwc_ddr_umctl2_c_struct_dfistat.u32 = rd(DFISTAT); while(umctl2_reg.dwc_ddr_umctl2_c_struct_dfistat.dfi_init_complete == 0) umctl2_reg.dwc_ddr_umctl2_c_struct_dfistat.u32 = rd(DFISTAT); - wr(DBG1,0); + + //wait dfi_init_complete = 1 +#ifndef CONFIG_DDR_H32_MODE + umctl2_reg.dwc_ddr_umctl2_c_struct_dfistat.u32 = rd(DCH1_DFISTAT); + while(umctl2_reg.dwc_ddr_umctl2_c_struct_dfistat.dfi_init_complete == 0) + umctl2_reg.dwc_ddr_umctl2_c_struct_dfistat.u32 = rd(DCH1_DFISTAT); +#endif + + //wr(DBG1,0); #ifdef CONFIG_DDR_MSG - printf("[dfi_freq_change]: dfi_freq_change, end \n",dfi_freq); + printf("[dfi_freq_change]: dfi_freq_change, end \n"); #endif } @@ -1146,3 +1384,168 @@ void lpddr4_auto_selref(void) wr(PWRCTL,0x0000000b); //[3] dfi_dram_clk_disable [1] powerdown_en [0]serref_en wr(DCH1_PWRCTL,0x0000000b); } + +void ctrl_en_lp3_exit(enum DDR_BITWIDTH bits) { + //skip DRAM init, because this has done + wr(SWCTL,0x00000000); + wr(INIT0,0xc0020002); + wr(SWCTL,0x00000001); + while(rd(SWSTAT)!=0x00000001); + + //dfi frequency change proto ,to PS0 + wr(SWCTL,0x00000000); + wr(DFIMISC,0x00000000);// [5]dfi_freq=0x0 + wr(SWCTL,0x00000001); + while(rd(SWSTAT)!=0x00000001); + + wr(SWCTL,0x00000000); + wr(DFIMISC,0x00000020);// [5]dfi_init_start=0x1 + wr(SWCTL,0x00000001); + while(rd(SWSTAT)!=0x00000001); + + + while(rd(DFISTAT)!=0x00000001); //polling dfi_init_complete +if(bits==64) { + while(rd(DCH1_DFISTAT)!=0x00000001); + } + wr(SWCTL,0x00000000); + wr(DFIMISC,0x00000000); + wr(SWCTL,0x00000001); + while(rd(SWSTAT)!=0x00000001); + + + wr(SWCTL,0x00000000); + wr(DFIMISC,0x00000001); + wr(SWCTL,0x00000001); + while(rd(SWSTAT)!=0x00000001); + + //for low power, + wr(SWCTL,0x00000000); + wr(PWRCTL,0x0000000a); //[3] dfi_dram_clk_disable [1] powerdown_en + wr(DCH1_PWRCTL,0x0000000a); + wr(SWCTL,0x00000001); + while (rd(SWSTAT) != 0x00000001); + //detect until umctrl into normal state + while (rd(STAT) != 0x00000001); + if(bits==64) { + while(rd(DCH1_STAT) != 0x00000001); + } + + //en phy master proto + wr(DFIPHYMSTR,0x14000001); + +#ifdef CONFIG_DDR_MSG + DDR_DEBUG("DFIPHYMSTR is %0x \n", rd(DFIPHYMSTR)); + DDR_DEBUG("DFIUPD0 is %0x \n", rd(DFIUPD0)); + DDR_DEBUG("DFIUPD1 is %0x \n", rd(DFIUPD1)); + DDR_DEBUG("ZQCTL0 is %0x \n", rd(ZQCTL0)); + DDR_DEBUG("ADDRMAP0 is %0x \n", rd(ADDRMAP0)); + DDR_DEBUG("ADDRMAP1 is %0x \n", rd(ADDRMAP1)); +#endif +} + +int lpddr4_reinit_ctrl(enum DDR_TYPE type, int rank_num, int speed, + enum DDR_BITWIDTH bits, unsigned long size) +{ + int ret; + unsigned int rdata; + + //a. + ddr_sysreg_wr(DDR_CFG1, 0xa000011f); //remove core clock after xx + wr(PWRCTL, 0x00000000); //[3] dfi_dram_clk_disable [1] powerdown_en [0]serref_en + wr(DCH1_PWRCTL, 0x00000000); + + // use phy value stored in spl + //dwc_ddrphy_phyinit_regInterface(saveRegs); + + //b.dis axi port + disable_axi_port(0x1f); + while (rd(PSTAT) != 0x0); + +#ifdef CONFIG_DDR_MSG + DDR_DEBUG("Axi prot idle\n"); +#endif + wr(DFIPHYMSTR, 0x14000000); + //check status. + while ((rd(STAT) & 0x3) == 0x03); + +#ifndef CONFIG_DDR_H32_MODE + while ((rd(STAT_DCH1) & 0x3) == 0x03); +#endif + //c.poll cam empty flag + while ((rd(DBGCAM) & 0x36000000) != 0x36000000); + //d.save phy regs + //e.SRE + lpddr4_enter_selfrefresh(1, 0, 0); + //f.LP3 enter + dfi_freq_change(0x1f, 0x3); + //g.PwrOk disassert + rdata = ddr_sysreg_rd(DDR_CFG0); + rdata &= ~(0x1 << 6); + ddr_sysreg_wr(DDR_CFG0, rdata); //Pwrokin dessert + + //p.phy reset + rdata = ddr_sysreg_rd(DDR_CFG0); + rdata &= ~(0x1 << 7); + rdata &= 0x0; + ddr_sysreg_wr(DDR_CFG0, rdata); //Phy reset .DDR_CFG0 ALL reset + + //r.ddr core reset + rdata = ddr_sysreg_rd(DDR_CFG0); + rdata &= ~(0x1 << 5); + ddr_sysreg_wr(DDR_CFG0, rdata); //ctrl sw reset + + //s.pwr ok assert + rdata = ddr_sysreg_rd(DDR_CFG0); + rdata |= (0x1 << 6); + ddr_sysreg_wr(DDR_CFG0, rdata); //Pwrokin dessert + + //t.ctrl init + //dwc_umctl_init_skip_traing(type, rank_num, speed, bits); + ddr_sysreg_wr(DDR_CFG0, 0x50); // release apb presetn + ddr_sysreg_wr(DDR_CFG0, 0x50); + ddr_sysreg_wr(DDR_CFG0, 0x50); + if (bits == 32) { + ddr_sysreg_wr(DDR_CFG0, 0x52); + } + ctrl_init(rank_num, speed); + addrmap(rank_num, bits); + ret = adjust_ddr_addrmap(type, rank_num, speed, bits, size); + + // msic regu restore for str + dwc_ddr_misc_regu_save(); + + de_assert_other_reset_ddr(); //after this step, only PwrOk is staill low + + dq_pinmux(bits); + + //u.phy restor + dwc_ddrphy_phyinit_regInterface(restoreRegs); + + //v.ctrl en ,hs + ctrl_en_lp3_exit(bits); + + //w.SRE + lpddr4_selfrefresh_exit(0); + + //y.en auto refresh + enable_auto_refresh(); + + //x.en axi port + enable_axi_port(0x1f); + wr(DFIPHYMSTR, 0x14000001); + lpddr4_auto_selref(); + + if(rd(PSTAT)) + { +#ifdef CONFIG_DDR_MSG + DDR_DEBUG("***** DDR busy in LP3 Mode *****\n"); +#endif + }else{ +#ifdef CONFIG_DDR_MSG + DDR_DEBUG("***** AXI port idle *****\n"); +#endif + } + return ret; + } + diff --git a/board/thead/light-c910/lpddr4/src/ddr_retention.c b/board/thead/light-c910/lpddr4/src/ddr_retention.c new file mode 100644 index 00000000..fb628369 --- /dev/null +++ b/board/thead/light-c910/lpddr4/src/ddr_retention.c @@ -0,0 +1,1076 @@ +#include "../include/common_lib.h" +#include "../include/ddr_common_func.h" +#include "../include/ddr_retention.h" + +/* +/// data structure to store register address, value pairs +typedef struct Reg_Addr_Val { + + uint32_t Address; ///< register address + uint16_t Value; ///< register value +} Reg_Addr_Val_t; + +/// enumeration of instructions for PhyInit Register Interface +typedef enum { + saveRegs, ///< save(read) tracked register values + restoreRegs, ///< restore (write) saved register values +} regInstr; +*/ + +/*! \def MAX_NUM_RET_REGS + * \brief default Max number of retention registers + * + * This define is only used by the PhyInit Register interface to define the max + * amount of registered that can be saved. The user may increase this variable + * as desired if a larger number of registers need to be restored. +*/ +#define MAX_NUM_RET_REGS 5000 + +//int NumRegSaved = 934; ///< Current Number of registers saved. +#define SRAM_E902_BASEADDR 0xFFE0170000 +#define DDR_PHY_REG_SAVEADDR (SRAM_E902_BASEADDR) +Ddr_Reg_Config_t *ddr_Regu_Config = (Ddr_Reg_Config_t *)DDR_PHY_REG_SAVEADDR; + +#ifndef ARRAY_SIZE +#define ARRAY_SIZE(x) (sizeof(x) / sizeof(x[0])) +#endif + +static const uint64_t MiscRegList[] = { + DFILPCFG0, + ADDRMAP0, + ADDRMAP1, + ADDRMAP2, + ADDRMAP3, + ADDRMAP4, + ADDRMAP5, + ADDRMAP6, + ADDRMAP7, + ADDRMAP9, + ADDRMAP10, + ADDRMAP11, +}; + +static const uint32_t RetRegList_addr[934] = +{ + 0x1005f, + 0x1015f, + 0x1105f, + 0x1115f, + 0x1205f, + 0x1215f, + 0x1305f, + 0x1315f, + 0x55, + 0x1055, + 0x2055, + 0x3055, + 0x4055, + 0x5055, + 0x200c5, + 0x2002e, + 0x90204, + 0x20024, + 0x2003a, + 0x2007d, + 0x2007c, + 0x20056, + 0x1004d, + 0x1014d, + 0x1104d, + 0x1114d, + 0x1204d, + 0x1214d, + 0x1304d, + 0x1314d, + 0x10049, + 0x10149, + 0x11049, + 0x11149, + 0x12049, + 0x12149, + 0x13049, + 0x13149, + 0x43, + 0x1043, + 0x2043, + 0x3043, + 0x4043, + 0x5043, + 0x20018, + 0x20075, + 0x20050, + 0x2009b, + 0x20008, + 0x20088, + 0x200b2, + 0x10043, + 0x10143, + 0x11043, + 0x11143, + 0x12043, + 0x12143, + 0x13043, + 0x13143, + 0x200fa, + 0x20019, + 0x200f0, + 0x200f1, + 0x200f2, + 0x200f3, + 0x200f4, + 0x200f5, + 0x200f6, + 0x200f7, + 0x20025, + 0x2002d, + 0x20021, + 0x2002c, + 0xd0000, + 0x90000, + 0x90001, + 0x90002, + 0x90003, + 0x90004, + 0x90005, + 0x90029, + 0x9002a, + 0x9002b, + 0x9002c, + 0x9002d, + 0x9002e, + 0x9002f, + 0x90030, + 0x90031, + 0x90032, + 0x90033, + 0x90034, + 0x90035, + 0x90036, + 0x90037, + 0x90038, + 0x90039, + 0x9003a, + 0x9003b, + 0x9003c, + 0x9003d, + 0x9003e, + 0x9003f, + 0x90040, + 0x90041, + 0x90042, + 0x90043, + 0x90044, + 0x90045, + 0x90046, + 0x90047, + 0x90048, + 0x90049, + 0x9004a, + 0x9004b, + 0x9004c, + 0x9004d, + 0x9004e, + 0x9004f, + 0x90050, + 0x90051, + 0x90052, + 0x90053, + 0x90054, + 0x90055, + 0x90056, + 0x90057, + 0x90058, + 0x90059, + 0x9005a, + 0x9005b, + 0x9005c, + 0x9005d, + 0x9005e, + 0x9005f, + 0x90060, + 0x90061, + 0x90062, + 0x90063, + 0x90064, + 0x90065, + 0x90066, + 0x90067, + 0x90068, + 0x90069, + 0x9006a, + 0x9006b, + 0x9006c, + 0x9006d, + 0x9006e, + 0x9006f, + 0x90070, + 0x90071, + 0x90072, + 0x90073, + 0x90074, + 0x90075, + 0x90076, + 0x90077, + 0x90078, + 0x90079, + 0x9007a, + 0x9007b, + 0x9007c, + 0x9007d, + 0x9007e, + 0x9007f, + 0x90080, + 0x90081, + 0x90082, + 0x90083, + 0x90084, + 0x90085, + 0x90086, + 0x90087, + 0x90088, + 0x90089, + 0x9008a, + 0x9008b, + 0x9008c, + 0x9008d, + 0x9008e, + 0x9008f, + 0x90090, + 0x90091, + 0x90092, + 0x90093, + 0x90094, + 0x90095, + 0x90096, + 0x90097, + 0x90098, + 0x90099, + 0x9009a, + 0x9009b, + 0x9009c, + 0x9009d, + 0x9009e, + 0x9009f, + 0x900a0, + 0x900a1, + 0x900a2, + 0x900a3, + 0x40000, + 0x40020, + 0x40040, + 0x40060, + 0x40001, + 0x40021, + 0x40041, + 0x40061, + 0x40002, + 0x40022, + 0x40042, + 0x40062, + 0x40003, + 0x40023, + 0x40043, + 0x40063, + 0x40004, + 0x40024, + 0x40044, + 0x40064, + 0x40005, + 0x40025, + 0x40045, + 0x40065, + 0x40006, + 0x40026, + 0x40046, + 0x40066, + 0x40007, + 0x40027, + 0x40047, + 0x40067, + 0x40008, + 0x40028, + 0x40048, + 0x40068, + 0x40009, + 0x40029, + 0x40049, + 0x40069, + 0x4000a, + 0x4002a, + 0x4004a, + 0x4006a, + 0x4000b, + 0x4002b, + 0x4004b, + 0x4006b, + 0x4000c, + 0x4002c, + 0x4004c, + 0x4006c, + 0x4000d, + 0x4002d, + 0x4004d, + 0x4006d, + 0x4000e, + 0x4002e, + 0x4004e, + 0x4006e, + 0x4000f, + 0x4002f, + 0x4004f, + 0x4006f, + 0x40010, + 0x40030, + 0x40050, + 0x40070, + 0x40011, + 0x40031, + 0x40051, + 0x40071, + 0x40012, + 0x40032, + 0x40052, + 0x40072, + 0x40013, + 0x40033, + 0x40053, + 0x40073, + 0x40014, + 0x40034, + 0x40054, + 0x40074, + 0x40015, + 0x40035, + 0x40055, + 0x40075, + 0x40016, + 0x40036, + 0x40056, + 0x40076, + 0x40017, + 0x40037, + 0x40057, + 0x40077, + 0x40018, + 0x40038, + 0x40058, + 0x40078, + 0x40019, + 0x40039, + 0x40059, + 0x40079, + 0x4001a, + 0x4003a, + 0x4005a, + 0x4007a, + 0x900a4, + 0x900a5, + 0x900a6, + 0x900a7, + 0x900a8, + 0x900a9, + 0x900aa, + 0x900ab, + 0x900ac, + 0x900ad, + 0x900ae, + 0x900af, + 0x900b0, + 0x900b1, + 0x900b2, + 0x900b3, + 0x900b4, + 0x900b5, + 0x900b6, + 0x900b7, + 0x900b8, + 0x900b9, + 0x900ba, + 0x900bb, + 0x900bc, + 0x900bd, + 0x900be, + 0x900bf, + 0x900c0, + 0x900c1, + 0x900c2, + 0x900c3, + 0x900c4, + 0x900c5, + 0x900c6, + 0x900c7, + 0x900c8, + 0x900c9, + 0x900ca, + 0x900cb, + 0x900cc, + 0x900cd, + 0x900ce, + 0x900cf, + 0x900d0, + 0x900d1, + 0x900d2, + 0x900d3, + 0x900d4, + 0x900d5, + 0x900d6, + 0x900d7, + 0x900d8, + 0x900d9, + 0x900da, + 0x900db, + 0x900dc, + 0x900dd, + 0x900de, + 0x900df, + 0x900e0, + 0x900e1, + 0x900e2, + 0x900e3, + 0x900e4, + 0x900e5, + 0x900e6, + 0x900e7, + 0x900e8, + 0x900e9, + 0x900ea, + 0x900eb, + 0x900ec, + 0x900ed, + 0x900ee, + 0x900ef, + 0x900f0, + 0x900f1, + 0x900f2, + 0x900f3, + 0x900f4, + 0x900f5, + 0x900f6, + 0x900f7, + 0x900f8, + 0x900f9, + 0x900fa, + 0x900fb, + 0x900fc, + 0x900fd, + 0x900fe, + 0x900ff, + 0x90100, + 0x90101, + 0x90102, + 0x90103, + 0x90104, + 0x90105, + 0x90106, + 0x90107, + 0x90108, + 0x90109, + 0x9010a, + 0x9010b, + 0x9010c, + 0x9010d, + 0x9010e, + 0x9010f, + 0x90110, + 0x90111, + 0x90112, + 0x90113, + 0x90114, + 0x90115, + 0x90116, + 0x90117, + 0x90118, + 0x90119, + 0x9011a, + 0x9011b, + 0x9011c, + 0x9011d, + 0x9011e, + 0x9011f, + 0x90120, + 0x90121, + 0x90122, + 0x90123, + 0x90124, + 0x90125, + 0x90126, + 0x90127, + 0x90128, + 0x90129, + 0x9012a, + 0x9012b, + 0x9012c, + 0x9012d, + 0x9012e, + 0x9012f, + 0x90130, + 0x90131, + 0x90132, + 0x90133, + 0x90134, + 0x90135, + 0x90136, + 0x90137, + 0x90138, + 0x90139, + 0x9013a, + 0x9013b, + 0x9013c, + 0x9013d, + 0x9013e, + 0x9013f, + 0x90140, + 0x90141, + 0x90142, + 0x90143, + 0x90144, + 0x90145, + 0x90146, + 0x90147, + 0x90148, + 0x90149, + 0x9014a, + 0x9014b, + 0x9014c, + 0x9014d, + 0x9014e, + 0x9014f, + 0x90150, + 0x90151, + 0x90152, + 0x90153, + 0x90154, + 0x90155, + 0x90156, + 0x90157, + 0x90158, + 0x90159, + 0x9015a, + 0x9015b, + 0x9015c, + 0x9015d, + 0x9015e, + 0x9015f, + 0x90160, + 0x90161, + 0x90162, + 0x90163, + 0x90164, + 0x90165, + 0x90166, + 0x90167, + 0x90168, + 0x90169, + 0x9016a, + 0x9016b, + 0x9016c, + 0x9016d, + 0x9016e, + 0x9016f, + 0x90170, + 0x90171, + 0x90172, + 0x90173, + 0x90174, + 0x90175, + 0x90176, + 0x90177, + 0x90178, + 0x90179, + 0x9017a, + 0x9017b, + 0x9017c, + 0x9017d, + 0x9017e, + 0x9017f, + 0x90180, + 0x90181, + 0x90006, + 0x90007, + 0x90008, + 0x90009, + 0x9000a, + 0x9000b, + 0xd00e7, + 0x90017, + 0x9001f, + 0x90026, + 0x400d0, + 0x400d1, + 0x400d2, + 0x400d3, + 0x400d4, + 0x400d5, + 0x400d6, + 0x400d7, + 0x200be, + 0x2000b, + 0x2000c, + 0x2000d, + 0x2000e, + 0x9000c, + 0x9000d, + 0x9000e, + 0x9000f, + 0x90010, + 0x90011, + 0x90012, + 0x90013, + 0x20010, + 0x20011, + 0x40080, + 0x40081, + 0x40082, + 0x40083, + 0x40084, + 0x40085, + 0x400fd, + 0x10011, + 0x10012, + 0x10013, + 0x10018, + 0x10002, + 0x100b2, + 0x101b4, + 0x102b4, + 0x103b4, + 0x104b4, + 0x105b4, + 0x106b4, + 0x107b4, + 0x108b4, + 0x11011, + 0x11012, + 0x11013, + 0x11018, + 0x11002, + 0x110b2, + 0x111b4, + 0x112b4, + 0x113b4, + 0x114b4, + 0x115b4, + 0x116b4, + 0x117b4, + 0x118b4, + 0x12011, + 0x12012, + 0x12013, + 0x12018, + 0x12002, + 0x120b2, + 0x121b4, + 0x122b4, + 0x123b4, + 0x124b4, + 0x125b4, + 0x126b4, + 0x127b4, + 0x128b4, + 0x13011, + 0x13012, + 0x13013, + 0x13018, + 0x13002, + 0x130b2, + 0x131b4, + 0x132b4, + 0x133b4, + 0x134b4, + 0x135b4, + 0x136b4, + 0x137b4, + 0x138b4, + 0x20089, + 0xc0080, + 0x200cb, + 0x10068, + 0x10069, + 0x10168, + 0x10169, + 0x10268, + 0x10269, + 0x10368, + 0x10369, + 0x10468, + 0x10469, + 0x10568, + 0x10569, + 0x10668, + 0x10669, + 0x10768, + 0x10769, + 0x10868, + 0x10869, + 0x100aa, + 0x10062, + 0x10001, + 0x100a0, + 0x100a1, + 0x100a2, + 0x100a3, + 0x100a4, + 0x100a5, + 0x100a6, + 0x100a7, + 0x11068, + 0x11069, + 0x11168, + 0x11169, + 0x11268, + 0x11269, + 0x11368, + 0x11369, + 0x11468, + 0x11469, + 0x11568, + 0x11569, + 0x11668, + 0x11669, + 0x11768, + 0x11769, + 0x11868, + 0x11869, + 0x110aa, + 0x11062, + 0x11001, + 0x110a0, + 0x110a1, + 0x110a2, + 0x110a3, + 0x110a4, + 0x110a5, + 0x110a6, + 0x110a7, + 0x12068, + 0x12069, + 0x12168, + 0x12169, + 0x12268, + 0x12269, + 0x12368, + 0x12369, + 0x12468, + 0x12469, + 0x12568, + 0x12569, + 0x12668, + 0x12669, + 0x12768, + 0x12769, + 0x12868, + 0x12869, + 0x120aa, + 0x12062, + 0x12001, + 0x120a0, + 0x120a1, + 0x120a2, + 0x120a3, + 0x120a4, + 0x120a5, + 0x120a6, + 0x120a7, + 0x13068, + 0x13069, + 0x13168, + 0x13169, + 0x13268, + 0x13269, + 0x13368, + 0x13369, + 0x13468, + 0x13469, + 0x13568, + 0x13569, + 0x13668, + 0x13669, + 0x13768, + 0x13769, + 0x13868, + 0x13869, + 0x130aa, + 0x13062, + 0x13001, + 0x130a0, + 0x130a1, + 0x130a2, + 0x130a3, + 0x130a4, + 0x130a5, + 0x130a6, + 0x130a7, + 0x80, + 0x1080, + 0x2080, + 0x3080, + 0x4080, + 0x5080, + 0x10020, + 0x10080, + 0x10081, + 0x100d0, + 0x100d1, + 0x1008c, + 0x1008d, + 0x10180, + 0x10181, + 0x101d0, + 0x101d1, + 0x1018c, + 0x1018d, + 0x100c0, + 0x100c1, + 0x101c0, + 0x101c1, + 0x102c0, + 0x102c1, + 0x103c0, + 0x103c1, + 0x104c0, + 0x104c1, + 0x105c0, + 0x105c1, + 0x106c0, + 0x106c1, + 0x107c0, + 0x107c1, + 0x108c0, + 0x108c1, + 0x100ae, + 0x100af, + 0x11020, + 0x11080, + 0x11081, + 0x110d0, + 0x110d1, + 0x1108c, + 0x1108d, + 0x11180, + 0x11181, + 0x111d0, + 0x111d1, + 0x1118c, + 0x1118d, + 0x110c0, + 0x110c1, + 0x111c0, + 0x111c1, + 0x112c0, + 0x112c1, + 0x113c0, + 0x113c1, + 0x114c0, + 0x114c1, + 0x115c0, + 0x115c1, + 0x116c0, + 0x116c1, + 0x117c0, + 0x117c1, + 0x118c0, + 0x118c1, + 0x110ae, + 0x110af, + 0x12020, + 0x12080, + 0x12081, + 0x120d0, + 0x120d1, + 0x1208c, + 0x1208d, + 0x12180, + 0x12181, + 0x121d0, + 0x121d1, + 0x1218c, + 0x1218d, + 0x120c0, + 0x120c1, + 0x121c0, + 0x121c1, + 0x122c0, + 0x122c1, + 0x123c0, + 0x123c1, + 0x124c0, + 0x124c1, + 0x125c0, + 0x125c1, + 0x126c0, + 0x126c1, + 0x127c0, + 0x127c1, + 0x128c0, + 0x128c1, + 0x120ae, + 0x120af, + 0x13020, + 0x13080, + 0x13081, + 0x130d0, + 0x130d1, + 0x1308c, + 0x1308d, + 0x13180, + 0x13181, + 0x131d0, + 0x131d1, + 0x1318c, + 0x1318d, + 0x130c0, + 0x130c1, + 0x131c0, + 0x131c1, + 0x132c0, + 0x132c1, + 0x133c0, + 0x133c1, + 0x134c0, + 0x134c1, + 0x135c0, + 0x135c1, + 0x136c0, + 0x136c1, + 0x137c0, + 0x137c1, + 0x138c0, + 0x138c1, + 0x130ae, + 0x130af, + 0x90201, + 0x90202, + 0x90203, + 0x90205, + 0x90206, + 0x90207, + 0x90208, + 0x20020, + 0x20077, + 0x20072, + 0x20073, + 0x400c0, + 0x10040, + 0x10140, + 0x10240, + 0x10340, + 0x10440, + 0x10540, + 0x10640, + 0x10740, + 0x10840, + 0x11040, + 0x11140, + 0x11240, + 0x11340, + 0x11440, + 0x11540, + 0x11640, + 0x11740, + 0x11840, + 0x12040, + 0x12140, + 0x12240, + 0x12340, + 0x12440, + 0x12540, + 0x12640, + 0x12740, + 0x12840, + 0x13040, + 0x13140, + 0x13240, + 0x13340, + 0x13440, + 0x13540, + 0x13640, + 0x13740, + 0x13840, +}; + +void dwc_ddr_misc_regu_save() +{ + uint32_t data = 0; + ddr_Regu_Config->misc_reg_num = ARRAY_SIZE(MiscRegList); + Reg_Misc_Addr_Val_t* misc_addr_t = (Reg_Misc_Addr_Val_t*)((char*)ddr_Regu_Config + 64); + for(int i = 0; i < ddr_Regu_Config->misc_reg_num; i++) { + misc_addr_t[i].Address = MiscRegList[i] & 0xffffffff; + misc_addr_t[i].Value = rd(MiscRegList[i]); +#ifdef CONFIG_DDR_MSG + DDR_DEBUG("misc_reg_addr_value:%d data:%d\n", misc_addr_t[i].Address, misc_addr_t[i].Value); +#endif + } +} + +int dwc_ddrphy_phyinit_regInterface(regInstr myRegInstr) { + int regIndx=0; + uint16_t data; + ddr_phy_reg_wr(0xd0000, 0x0); + ddr_phy_reg_wr(0xc0080, 0x3); + + uint32_t phy_reg_num = ARRAY_SIZE(RetRegList_addr); + ddr_Regu_Config->phy_reg_num = phy_reg_num; + Reg_Phy_Addr_Val_t* phy_addr_t = (Reg_Phy_Addr_Val_t*)((char*)ddr_Regu_Config + 64 + sizeof(Reg_Misc_Addr_Val_t) * ARRAY_SIZE(MiscRegList)); + +#ifdef CONFIG_DDR_MSG + DDR_DEBUG("pReg_Addr_Value %p\n", pReg_Addr_Value); +#endif + if (myRegInstr == saveRegs) + { + // go through all the tracked registers, issue a register read and place + // the result in the data structure for future recovery. + for (regIndx = 0; regIndx < phy_reg_num; regIndx++) + { + data = ddr_phy0_reg_rd(RetRegList_addr[regIndx]); + phy_addr_t[regIndx].Value0 = data; + phy_addr_t[regIndx].Address = RetRegList_addr[regIndx]; + } +#ifndef CONFIG_DDR_H32_MODE + for (regIndx = 0; regIndx < phy_reg_num; regIndx++) + { + data = ddr_phy1_reg_rd(RetRegList_addr[regIndx]); + phy_addr_t[regIndx].Value1 = data; + } +#endif + } + else if (myRegInstr == restoreRegs) + { + // write PHY registers based on Address, Data value pairs stores in + // RetRegList + ddr_phy0_reg_wr(0x20089, 0x1); + for (regIndx = 0; regIndx < phy_reg_num; regIndx++) + { + ddr_phy0_reg_wr(phy_addr_t[regIndx].Address, phy_addr_t[regIndx].Value0); + } + +#ifndef CONFIG_DDR_H32_MODE + ddr_phy1_reg_wr(0x20089, 0x1); + for (regIndx = 0; regIndx < phy_reg_num; regIndx++) + { + ddr_phy1_reg_wr(phy_addr_t[regIndx].Address, phy_addr_t[regIndx].Value1); + } +#endif + } + ddr_phy_reg_wr(0xc0080, 0x2); + ddr_phy_reg_wr(0xd0000, 0x1); + return 1; +} + +void dwc_umctl_init_skip_traing(enum DDR_TYPE type, int rank_num, int speed, enum DDR_BITWIDTH bits) +{ + ddr_sysreg_wr(DDR_CFG0, 0x50); // release apb presetn + ddr_sysreg_wr(DDR_CFG0, 0x50); + ddr_sysreg_wr(DDR_CFG0, 0x50); + if (bits == 32) { + ddr_sysreg_wr(DDR_CFG0, 0x52); + } + ctrl_init(rank_num, speed); + addrmap(rank_num, bits); + + de_assert_other_reset_ddr(); //after this step, only PwrOk is staill low + + dq_pinmux(bits); + + +} + diff --git a/board/thead/light-c910/lpddr4/src/lpddr4_init.c b/board/thead/light-c910/lpddr4/src/lpddr4_init.c index 0c5ba407..29b7d07a 100755 --- a/board/thead/light-c910/lpddr4/src/lpddr4_init.c +++ b/board/thead/light-c910/lpddr4/src/lpddr4_init.c @@ -1,6 +1,7 @@ #include "../include/common_lib.h" #include "../include/pinmux.h" #include "../include/ddr_common_func.h" +#include "../include/ddr_retention.h" #include "../include/lpddr4_init.h" extern void lp4_phy_train1d2d(enum DDR_TYPE type, int speed, enum DDR_BITWIDTH bits); @@ -26,7 +27,7 @@ void lpddr4_init(enum DDR_TYPE type, int rank_num, int speed, enum DDR_BITWIDTH lp4_phy_train1d2d(type, speed, bits); - dwc_ddrphy_phyinit_regInterface(); + dwc_ddrphy_phyinit_regInterface(saveRegs); ctrl_en(bits); @@ -37,982 +38,23 @@ void lpddr4_init(enum DDR_TYPE type, int rank_num, int speed, enum DDR_BITWIDTH lpddr4_auto_selref(); } -static const uint32_t RetRegList_addr[934] = +int fixup_ddr_addrmap(unsigned long size) { - 0x1005f, - 0x1015f, - 0x1105f, - 0x1115f, - 0x1205f, - 0x1215f, - 0x1305f, - 0x1315f, - 0x55, - 0x1055, - 0x2055, - 0x3055, - 0x4055, - 0x5055, - 0x200c5, - 0x2002e, - 0x90204, - 0x20024, - 0x2003a, - 0x2007d, - 0x2007c, - 0x20056, - 0x1004d, - 0x1014d, - 0x1104d, - 0x1114d, - 0x1204d, - 0x1214d, - 0x1304d, - 0x1314d, - 0x10049, - 0x10149, - 0x11049, - 0x11149, - 0x12049, - 0x12149, - 0x13049, - 0x13149, - 0x43, - 0x1043, - 0x2043, - 0x3043, - 0x4043, - 0x5043, - 0x20018, - 0x20075, - 0x20050, - 0x2009b, - 0x20008, - 0x20088, - 0x200b2, - 0x10043, - 0x10143, - 0x11043, - 0x11143, - 0x12043, - 0x12143, - 0x13043, - 0x13143, - 0x200fa, - 0x20019, - 0x200f0, - 0x200f1, - 0x200f2, - 0x200f3, - 0x200f4, - 0x200f5, - 0x200f6, - 0x200f7, - 0x20025, - 0x2002d, - 0x20021, - 0x2002c, - 0xd0000, - 0x90000, - 0x90001, - 0x90002, - 0x90003, - 0x90004, - 0x90005, - 0x90029, - 0x9002a, - 0x9002b, - 0x9002c, - 0x9002d, - 0x9002e, - 0x9002f, - 0x90030, - 0x90031, - 0x90032, - 0x90033, - 0x90034, - 0x90035, - 0x90036, - 0x90037, - 0x90038, - 0x90039, - 0x9003a, - 0x9003b, - 0x9003c, - 0x9003d, - 0x9003e, - 0x9003f, - 0x90040, - 0x90041, - 0x90042, - 0x90043, - 0x90044, - 0x90045, - 0x90046, - 0x90047, - 0x90048, - 0x90049, - 0x9004a, - 0x9004b, - 0x9004c, - 0x9004d, - 0x9004e, - 0x9004f, - 0x90050, - 0x90051, - 0x90052, - 0x90053, - 0x90054, - 0x90055, - 0x90056, - 0x90057, - 0x90058, - 0x90059, - 0x9005a, - 0x9005b, - 0x9005c, - 0x9005d, - 0x9005e, - 0x9005f, - 0x90060, - 0x90061, - 0x90062, - 0x90063, - 0x90064, - 0x90065, - 0x90066, - 0x90067, - 0x90068, - 0x90069, - 0x9006a, - 0x9006b, - 0x9006c, - 0x9006d, - 0x9006e, - 0x9006f, - 0x90070, - 0x90071, - 0x90072, - 0x90073, - 0x90074, - 0x90075, - 0x90076, - 0x90077, - 0x90078, - 0x90079, - 0x9007a, - 0x9007b, - 0x9007c, - 0x9007d, - 0x9007e, - 0x9007f, - 0x90080, - 0x90081, - 0x90082, - 0x90083, - 0x90084, - 0x90085, - 0x90086, - 0x90087, - 0x90088, - 0x90089, - 0x9008a, - 0x9008b, - 0x9008c, - 0x9008d, - 0x9008e, - 0x9008f, - 0x90090, - 0x90091, - 0x90092, - 0x90093, - 0x90094, - 0x90095, - 0x90096, - 0x90097, - 0x90098, - 0x90099, - 0x9009a, - 0x9009b, - 0x9009c, - 0x9009d, - 0x9009e, - 0x9009f, - 0x900a0, - 0x900a1, - 0x900a2, - 0x900a3, - 0x40000, - 0x40020, - 0x40040, - 0x40060, - 0x40001, - 0x40021, - 0x40041, - 0x40061, - 0x40002, - 0x40022, - 0x40042, - 0x40062, - 0x40003, - 0x40023, - 0x40043, - 0x40063, - 0x40004, - 0x40024, - 0x40044, - 0x40064, - 0x40005, - 0x40025, - 0x40045, - 0x40065, - 0x40006, - 0x40026, - 0x40046, - 0x40066, - 0x40007, - 0x40027, - 0x40047, - 0x40067, - 0x40008, - 0x40028, - 0x40048, - 0x40068, - 0x40009, - 0x40029, - 0x40049, - 0x40069, - 0x4000a, - 0x4002a, - 0x4004a, - 0x4006a, - 0x4000b, - 0x4002b, - 0x4004b, - 0x4006b, - 0x4000c, - 0x4002c, - 0x4004c, - 0x4006c, - 0x4000d, - 0x4002d, - 0x4004d, - 0x4006d, - 0x4000e, - 0x4002e, - 0x4004e, - 0x4006e, - 0x4000f, - 0x4002f, - 0x4004f, - 0x4006f, - 0x40010, - 0x40030, - 0x40050, - 0x40070, - 0x40011, - 0x40031, - 0x40051, - 0x40071, - 0x40012, - 0x40032, - 0x40052, - 0x40072, - 0x40013, - 0x40033, - 0x40053, - 0x40073, - 0x40014, - 0x40034, - 0x40054, - 0x40074, - 0x40015, - 0x40035, - 0x40055, - 0x40075, - 0x40016, - 0x40036, - 0x40056, - 0x40076, - 0x40017, - 0x40037, - 0x40057, - 0x40077, - 0x40018, - 0x40038, - 0x40058, - 0x40078, - 0x40019, - 0x40039, - 0x40059, - 0x40079, - 0x4001a, - 0x4003a, - 0x4005a, - 0x4007a, - 0x900a4, - 0x900a5, - 0x900a6, - 0x900a7, - 0x900a8, - 0x900a9, - 0x900aa, - 0x900ab, - 0x900ac, - 0x900ad, - 0x900ae, - 0x900af, - 0x900b0, - 0x900b1, - 0x900b2, - 0x900b3, - 0x900b4, - 0x900b5, - 0x900b6, - 0x900b7, - 0x900b8, - 0x900b9, - 0x900ba, - 0x900bb, - 0x900bc, - 0x900bd, - 0x900be, - 0x900bf, - 0x900c0, - 0x900c1, - 0x900c2, - 0x900c3, - 0x900c4, - 0x900c5, - 0x900c6, - 0x900c7, - 0x900c8, - 0x900c9, - 0x900ca, - 0x900cb, - 0x900cc, - 0x900cd, - 0x900ce, - 0x900cf, - 0x900d0, - 0x900d1, - 0x900d2, - 0x900d3, - 0x900d4, - 0x900d5, - 0x900d6, - 0x900d7, - 0x900d8, - 0x900d9, - 0x900da, - 0x900db, - 0x900dc, - 0x900dd, - 0x900de, - 0x900df, - 0x900e0, - 0x900e1, - 0x900e2, - 0x900e3, - 0x900e4, - 0x900e5, - 0x900e6, - 0x900e7, - 0x900e8, - 0x900e9, - 0x900ea, - 0x900eb, - 0x900ec, - 0x900ed, - 0x900ee, - 0x900ef, - 0x900f0, - 0x900f1, - 0x900f2, - 0x900f3, - 0x900f4, - 0x900f5, - 0x900f6, - 0x900f7, - 0x900f8, - 0x900f9, - 0x900fa, - 0x900fb, - 0x900fc, - 0x900fd, - 0x900fe, - 0x900ff, - 0x90100, - 0x90101, - 0x90102, - 0x90103, - 0x90104, - 0x90105, - 0x90106, - 0x90107, - 0x90108, - 0x90109, - 0x9010a, - 0x9010b, - 0x9010c, - 0x9010d, - 0x9010e, - 0x9010f, - 0x90110, - 0x90111, - 0x90112, - 0x90113, - 0x90114, - 0x90115, - 0x90116, - 0x90117, - 0x90118, - 0x90119, - 0x9011a, - 0x9011b, - 0x9011c, - 0x9011d, - 0x9011e, - 0x9011f, - 0x90120, - 0x90121, - 0x90122, - 0x90123, - 0x90124, - 0x90125, - 0x90126, - 0x90127, - 0x90128, - 0x90129, - 0x9012a, - 0x9012b, - 0x9012c, - 0x9012d, - 0x9012e, - 0x9012f, - 0x90130, - 0x90131, - 0x90132, - 0x90133, - 0x90134, - 0x90135, - 0x90136, - 0x90137, - 0x90138, - 0x90139, - 0x9013a, - 0x9013b, - 0x9013c, - 0x9013d, - 0x9013e, - 0x9013f, - 0x90140, - 0x90141, - 0x90142, - 0x90143, - 0x90144, - 0x90145, - 0x90146, - 0x90147, - 0x90148, - 0x90149, - 0x9014a, - 0x9014b, - 0x9014c, - 0x9014d, - 0x9014e, - 0x9014f, - 0x90150, - 0x90151, - 0x90152, - 0x90153, - 0x90154, - 0x90155, - 0x90156, - 0x90157, - 0x90158, - 0x90159, - 0x9015a, - 0x9015b, - 0x9015c, - 0x9015d, - 0x9015e, - 0x9015f, - 0x90160, - 0x90161, - 0x90162, - 0x90163, - 0x90164, - 0x90165, - 0x90166, - 0x90167, - 0x90168, - 0x90169, - 0x9016a, - 0x9016b, - 0x9016c, - 0x9016d, - 0x9016e, - 0x9016f, - 0x90170, - 0x90171, - 0x90172, - 0x90173, - 0x90174, - 0x90175, - 0x90176, - 0x90177, - 0x90178, - 0x90179, - 0x9017a, - 0x9017b, - 0x9017c, - 0x9017d, - 0x9017e, - 0x9017f, - 0x90180, - 0x90181, - 0x90006, - 0x90007, - 0x90008, - 0x90009, - 0x9000a, - 0x9000b, - 0xd00e7, - 0x90017, - 0x9001f, - 0x90026, - 0x400d0, - 0x400d1, - 0x400d2, - 0x400d3, - 0x400d4, - 0x400d5, - 0x400d6, - 0x400d7, - 0x200be, - 0x2000b, - 0x2000c, - 0x2000d, - 0x2000e, - 0x9000c, - 0x9000d, - 0x9000e, - 0x9000f, - 0x90010, - 0x90011, - 0x90012, - 0x90013, - 0x20010, - 0x20011, - 0x40080, - 0x40081, - 0x40082, - 0x40083, - 0x40084, - 0x40085, - 0x400fd, - 0x10011, - 0x10012, - 0x10013, - 0x10018, - 0x10002, - 0x100b2, - 0x101b4, - 0x102b4, - 0x103b4, - 0x104b4, - 0x105b4, - 0x106b4, - 0x107b4, - 0x108b4, - 0x11011, - 0x11012, - 0x11013, - 0x11018, - 0x11002, - 0x110b2, - 0x111b4, - 0x112b4, - 0x113b4, - 0x114b4, - 0x115b4, - 0x116b4, - 0x117b4, - 0x118b4, - 0x12011, - 0x12012, - 0x12013, - 0x12018, - 0x12002, - 0x120b2, - 0x121b4, - 0x122b4, - 0x123b4, - 0x124b4, - 0x125b4, - 0x126b4, - 0x127b4, - 0x128b4, - 0x13011, - 0x13012, - 0x13013, - 0x13018, - 0x13002, - 0x130b2, - 0x131b4, - 0x132b4, - 0x133b4, - 0x134b4, - 0x135b4, - 0x136b4, - 0x137b4, - 0x138b4, - 0x20089, - 0xc0080, - 0x200cb, - 0x10068, - 0x10069, - 0x10168, - 0x10169, - 0x10268, - 0x10269, - 0x10368, - 0x10369, - 0x10468, - 0x10469, - 0x10568, - 0x10569, - 0x10668, - 0x10669, - 0x10768, - 0x10769, - 0x10868, - 0x10869, - 0x100aa, - 0x10062, - 0x10001, - 0x100a0, - 0x100a1, - 0x100a2, - 0x100a3, - 0x100a4, - 0x100a5, - 0x100a6, - 0x100a7, - 0x11068, - 0x11069, - 0x11168, - 0x11169, - 0x11268, - 0x11269, - 0x11368, - 0x11369, - 0x11468, - 0x11469, - 0x11568, - 0x11569, - 0x11668, - 0x11669, - 0x11768, - 0x11769, - 0x11868, - 0x11869, - 0x110aa, - 0x11062, - 0x11001, - 0x110a0, - 0x110a1, - 0x110a2, - 0x110a3, - 0x110a4, - 0x110a5, - 0x110a6, - 0x110a7, - 0x12068, - 0x12069, - 0x12168, - 0x12169, - 0x12268, - 0x12269, - 0x12368, - 0x12369, - 0x12468, - 0x12469, - 0x12568, - 0x12569, - 0x12668, - 0x12669, - 0x12768, - 0x12769, - 0x12868, - 0x12869, - 0x120aa, - 0x12062, - 0x12001, - 0x120a0, - 0x120a1, - 0x120a2, - 0x120a3, - 0x120a4, - 0x120a5, - 0x120a6, - 0x120a7, - 0x13068, - 0x13069, - 0x13168, - 0x13169, - 0x13268, - 0x13269, - 0x13368, - 0x13369, - 0x13468, - 0x13469, - 0x13568, - 0x13569, - 0x13668, - 0x13669, - 0x13768, - 0x13769, - 0x13868, - 0x13869, - 0x130aa, - 0x13062, - 0x13001, - 0x130a0, - 0x130a1, - 0x130a2, - 0x130a3, - 0x130a4, - 0x130a5, - 0x130a6, - 0x130a7, - 0x80, - 0x1080, - 0x2080, - 0x3080, - 0x4080, - 0x5080, - 0x10020, - 0x10080, - 0x10081, - 0x100d0, - 0x100d1, - 0x1008c, - 0x1008d, - 0x10180, - 0x10181, - 0x101d0, - 0x101d1, - 0x1018c, - 0x1018d, - 0x100c0, - 0x100c1, - 0x101c0, - 0x101c1, - 0x102c0, - 0x102c1, - 0x103c0, - 0x103c1, - 0x104c0, - 0x104c1, - 0x105c0, - 0x105c1, - 0x106c0, - 0x106c1, - 0x107c0, - 0x107c1, - 0x108c0, - 0x108c1, - 0x100ae, - 0x100af, - 0x11020, - 0x11080, - 0x11081, - 0x110d0, - 0x110d1, - 0x1108c, - 0x1108d, - 0x11180, - 0x11181, - 0x111d0, - 0x111d1, - 0x1118c, - 0x1118d, - 0x110c0, - 0x110c1, - 0x111c0, - 0x111c1, - 0x112c0, - 0x112c1, - 0x113c0, - 0x113c1, - 0x114c0, - 0x114c1, - 0x115c0, - 0x115c1, - 0x116c0, - 0x116c1, - 0x117c0, - 0x117c1, - 0x118c0, - 0x118c1, - 0x110ae, - 0x110af, - 0x12020, - 0x12080, - 0x12081, - 0x120d0, - 0x120d1, - 0x1208c, - 0x1208d, - 0x12180, - 0x12181, - 0x121d0, - 0x121d1, - 0x1218c, - 0x1218d, - 0x120c0, - 0x120c1, - 0x121c0, - 0x121c1, - 0x122c0, - 0x122c1, - 0x123c0, - 0x123c1, - 0x124c0, - 0x124c1, - 0x125c0, - 0x125c1, - 0x126c0, - 0x126c1, - 0x127c0, - 0x127c1, - 0x128c0, - 0x128c1, - 0x120ae, - 0x120af, - 0x13020, - 0x13080, - 0x13081, - 0x130d0, - 0x130d1, - 0x1308c, - 0x1308d, - 0x13180, - 0x13181, - 0x131d0, - 0x131d1, - 0x1318c, - 0x1318d, - 0x130c0, - 0x130c1, - 0x131c0, - 0x131c1, - 0x132c0, - 0x132c1, - 0x133c0, - 0x133c1, - 0x134c0, - 0x134c1, - 0x135c0, - 0x135c1, - 0x136c0, - 0x136c1, - 0x137c0, - 0x137c1, - 0x138c0, - 0x138c1, - 0x130ae, - 0x130af, - 0x90201, - 0x90202, - 0x90203, - 0x90205, - 0x90206, - 0x90207, - 0x90208, - 0x20020, - 0x20077, - 0x20072, - 0x20073, - 0x400c0, - 0x10040, - 0x10140, - 0x10240, - 0x10340, - 0x10440, - 0x10540, - 0x10640, - 0x10740, - 0x10840, - 0x11040, - 0x11140, - 0x11240, - 0x11340, - 0x11440, - 0x11540, - 0x11640, - 0x11740, - 0x11840, - 0x12040, - 0x12140, - 0x12240, - 0x12340, - 0x12440, - 0x12540, - 0x12640, - 0x12740, - 0x12840, - 0x13040, - 0x13140, - 0x13240, - 0x13340, - 0x13440, - 0x13540, - 0x13640, - 0x13740, - 0x13840, -}; + enum DDR_TYPE type = get_ddr_type(); + int rank_num = get_ddr_rank_number(); + int speed = get_ddr_freq(); + enum DDR_BITWIDTH bits = get_ddr_bitwidth(); -typedef struct Reg_Addr_Val { - uint32_t Address; ///< register address - uint16_t Value0; ///< register value phy0 - uint16_t Value1; ///< register value phy1 -} Reg_Addr_Val_t; - -typedef struct Reg_Addr_Value { - uint32_t reg_num; - Reg_Addr_Val_t reg[0]; -} Reg_Addr_Value_t; - -int NumRegSaved = 934; ///< Current Number of registers saved. -#define SRAM_E902_BASEADDR 0xFFFFEF8000 -#define DDR_PHY_REG_SAVEADDR (SRAM_E902_BASEADDR + 0xDF00) -Reg_Addr_Value_t *pRetRegList = (Reg_Addr_Value_t *)DDR_PHY_REG_SAVEADDR; - -int dwc_ddrphy_phyinit_regInterface() { - ddr_phy_reg_wr(0xd0000, 0x0); - ddr_phy_reg_wr(0xc0080, 0x3); - pRetRegList->reg_num = NumRegSaved; - // go through all the tracked registers, issue a register read and place - // the result in the data structure for future recovery. - int regIndx = 0; - uint16_t data; - for (regIndx = 0; regIndx < NumRegSaved; regIndx++) - { - data = ddr_phy0_reg_rd(RetRegList_addr[regIndx]); - pRetRegList->reg[regIndx].Value0 = data; - pRetRegList->reg[regIndx].Address = RetRegList_addr[regIndx]; - } -#ifndef CONFIG_DDR_H32_MODE - for (regIndx = 0; regIndx < NumRegSaved; regIndx++) - { - data = ddr_phy1_reg_rd(RetRegList_addr[regIndx]); - pRetRegList->reg[regIndx].Value1 = data; - } -#endif - ddr_phy_reg_wr(0xc0080, 0x2); - ddr_phy_reg_wr(0xd0000, 0x1); - return 1; + return lpddr4_reinit_ctrl(type, rank_num, speed, bits, size); } + +int query_ddr_boundary(unsigned long size) +{ + enum DDR_TYPE type = get_ddr_type(); + int rank_num = get_ddr_rank_number(); + int speed = get_ddr_freq(); + enum DDR_BITWIDTH bits = get_ddr_bitwidth(); + + return lpddr4_query_boundary(type, rank_num, speed, bits, size); +} + diff --git a/board/thead/light-c910/spl.c b/board/thead/light-c910/spl.c index 66e3e07d..7d9fa418 100644 --- a/board/thead/light-c910/spl.c +++ b/board/thead/light-c910/spl.c @@ -26,6 +26,11 @@ DECLARE_GLOBAL_DATA_PTR; extern void init_ddr(void); +#ifdef CONFIG_FIXUP_MEMORY_REGION +extern int fixup_ddr_addrmap(unsigned long size); +extern int query_ddr_boundary(unsigned long size); +#endif +extern unsigned long get_ddr_density(void); extern void cpu_clk_config(int cpu_freq); extern void sys_clk_config(void); extern void ddr_clk_config(int ddr_freq); @@ -93,6 +98,25 @@ void setup_ddr_pmp(void) sync_is(); } +void clear_ddr_pmp(void) +{ + /* restore pmp entry0,entry1 setting in bootrom */ + writel(0x0400000000 >> 12, (void *)(PMP_BASE_ADDR + 0x104)); + writel(0x0 >> 12, (void *)(PMP_BASE_ADDR + 0x100)); + writel(0xffe1000000 >> 12, (void *)(PMP_BASE_ADDR + 0x10c)); + writel(0xffe0180000 >> 12, (void *)(PMP_BASE_ADDR + 0x108)); + + writel(0x4040, (void *)(PMP_BASE_ADDR + 0x000)); + + sync_is(); +} + +static inline void _l2cache_ciall(void) +{ + asm volatile (".long 0x0170000b"); +} + + int get_rng(unsigned int *rng, int cnt) { int i; @@ -297,6 +321,101 @@ void setup_ddr_parity(void) } } +#ifdef CONFIG_FIXUP_MEMORY_REGION + +#define MAGIC_DATA (0xF4240) +#define MAGIC_DATA2 (0x5AA5) +#define MAGIC_DATA3 (0x3C3C) +#define MAGIC_DATA4 (0xF0F0) + +/* +return: 0: found boundary; +*/ +int boundary_verify(unsigned long boundary) { + phys_addr_t verify_addr = (phys_addr_t)CONFIG_SYS_SDRAM_BASE; + phys_addr_t verify_addr2 = ((phys_addr_t)boundary + CONFIG_SYS_SDRAM_BASE)/4; + phys_addr_t verify_addr3 = ((phys_addr_t)boundary + CONFIG_SYS_SDRAM_BASE)/2; + phys_addr_t verify_addr4 = (phys_addr_t)boundary + CONFIG_SYS_SDRAM_BASE; + + // verify data accessing result firstly + writel(MAGIC_DATA2, verify_addr); + invalidate_dcache_range(verify_addr, verify_addr + CONFIG_SYS_CACHELINE_SIZE); + if (readl(verify_addr) != MAGIC_DATA2) { + printf("ddr rw test failed\n"); + return -1; + } + writel(MAGIC_DATA, verify_addr); // writing at beginning + invalidate_dcache_range(verify_addr, verify_addr + CONFIG_SYS_CACHELINE_SIZE); + if (readl(verify_addr) != MAGIC_DATA) { + printf("ddr rw test failed\n"); + return -1; + } + writel(MAGIC_DATA2, verify_addr2); // writing at one-quarter addr + writel(MAGIC_DATA3, verify_addr3); // writing at half addr + invalidate_dcache_range(verify_addr, verify_addr + CONFIG_SYS_CACHELINE_SIZE); + invalidate_dcache_range(verify_addr2, verify_addr2 + CONFIG_SYS_CACHELINE_SIZE); + invalidate_dcache_range(verify_addr3, verify_addr3 + CONFIG_SYS_CACHELINE_SIZE); + + if (boundary == (unsigned long)MAXIMAL_DDR_DENSITY_MB * UNIT_MB) { // boundary by design + if ((readl(verify_addr) == MAGIC_DATA) && + (readl(verify_addr2) == MAGIC_DATA2) && + (readl(verify_addr3) == MAGIC_DATA3)) + return 0; + } + else { + writel(MAGIC_DATA4, verify_addr4); // writing out of boundary + invalidate_dcache_range(verify_addr4, verify_addr4 + CONFIG_SYS_CACHELINE_SIZE); + if ((readl(verify_addr) == MAGIC_DATA4) && // overwrite by verify_addr4 + (readl(verify_addr2) == MAGIC_DATA2) && + (readl(verify_addr3) == MAGIC_DATA3) && + (readl(verify_addr4) == MAGIC_DATA4)) + return 0; + } + + return -1; +} + +int setup_ddr_addrmap(void) +{ + int ret; + unsigned long boundary = (unsigned long)MAXIMAL_DDR_DENSITY_MB * UNIT_MB; + + // verify data accessing result firstly + writel(MAGIC_DATA, (phys_addr_t)CONFIG_SYS_SDRAM_BASE); + invalidate_dcache_range(CONFIG_SYS_SDRAM_BASE, CONFIG_SYS_SDRAM_BASE + CONFIG_SYS_CACHELINE_SIZE); + if (readl((phys_addr_t)CONFIG_SYS_SDRAM_BASE) != MAGIC_DATA) { + printf("ddr rw test failed\n"); + goto addrmap_err; + } + writel(MAGIC_DATA2, (phys_addr_t)CONFIG_SYS_SDRAM_BASE); + invalidate_dcache_range(CONFIG_SYS_SDRAM_BASE, CONFIG_SYS_SDRAM_BASE + CONFIG_SYS_CACHELINE_SIZE); + if (readl((phys_addr_t)CONFIG_SYS_SDRAM_BASE) != MAGIC_DATA2) { + printf("ddr rw test failed\n"); + goto addrmap_err; + } + + // try to find memory boundary + while (boundary >= (unsigned long)MINIMAL_DDR_DENSITY_MB * UNIT_MB) { + if (query_ddr_boundary(boundary) == 0) { + clear_ddr_pmp(); + fixup_ddr_addrmap(boundary); + setup_ddr_pmp(); + if (boundary_verify(boundary) == 0) { + gd->ram_size = boundary; + printf("found ddr boundary <0x%lx>\n", boundary); + return 0; + } + } + boundary = boundary >> 1; + } + + gd->ram_size = get_ddr_density(); +addrmap_err: + printf("failed to setup ddr addrmap\n"); + return -1; +} +#endif + void cpu_performance_enable(void) { #define CSR_MHINT2_E 0x7cc @@ -308,7 +427,6 @@ void cpu_performance_enable(void) csr_write(CSR_MCCR2, 0xe2490009); // FIXME: Clear bit[12] to disable L0BTB. csr_write(CSR_MHCR, 0x17f); // clear bit7 to disable indirect brantch prediction - csr_write(CSR_MXSTATUS, 0x638000); csr_write(CSR_MHINT, 0x6e30c | (1<<21) | (1<<22)); // set bit21 & bit 22 to close tlb & fence broadcast mdelay(50); // workaround } @@ -372,9 +490,9 @@ void board_init_f(ulong dummy) preloader_console_init(); #ifdef CONFIG_PMIC_VOL_INIT - ret = pmic_ddr_regu_init(); + ret = aon_local_init(); if (ret) { - printf("%s pmic init failed %d \n",__func__,ret); + printf("%s aon local init failed %d \n",__func__,ret); hang(); } @@ -389,7 +507,6 @@ void board_init_f(ulong dummy) printf("%s set apcpu voltage failed \n",__func__); hang(); } - #endif ddr_clk_config(0); cpu_clk_config(0); @@ -398,6 +515,12 @@ void board_init_f(ulong dummy) setup_ddr_scramble(); setup_ddr_parity(); setup_ddr_pmp(); +#ifdef CONFIG_FIXUP_MEMORY_REGION + setup_ddr_addrmap(); +#else + // update ram_size from board config + gd->ram_size = get_ddr_density(); +#endif printf("ddr initialized, jump to uboot\n"); light_board_init_r(NULL, 0); diff --git a/cmd/net.c b/cmd/net.c index 23740397..6e2c5dea 100644 --- a/cmd/net.c +++ b/cmd/net.c @@ -458,3 +458,22 @@ U_BOOT_CMD( ); #endif /* CONFIG_CMD_LINK_LOCAL */ + +/* moved from board_init_r sequence here to save normal boot time */ +static int do_eth_init(cmd_tbl_t *cmdtp, int flag, int argc, + char * const argv[]) +{ + puts("Net: "); + eth_initialize(); +#if defined(CONFIG_RESET_PHY_R) + debug("Reset Ethernet PHY\n"); + reset_phy(); +#endif + return 0; +} + +U_BOOT_CMD( + eth, 6, 1, do_eth_init, + "eth initialize", + "" +); diff --git a/common/image-fdt.c b/common/image-fdt.c index 48388488..c8e902a1 100644 --- a/common/image-fdt.c +++ b/common/image-fdt.c @@ -416,7 +416,7 @@ int boot_get_fdt(int flag, int argc, char * const argv[], uint8_t arch, * FDT blob */ debug("* fdt: raw FDT blob\n"); - printf("## Flattened Device Tree blob at %08lx\n", + debug("## Flattened Device Tree blob at %08lx\n", (long)fdt_addr); } break; @@ -425,7 +425,7 @@ int boot_get_fdt(int flag, int argc, char * const argv[], uint8_t arch, goto no_fdt; } - printf(" Booting using the fdt blob at %#08lx\n", fdt_addr); + debug(" Booting using the fdt blob at %#08lx\n", fdt_addr); fdt_blob = map_sysmem(fdt_addr, 0); } else if (images->legacy_hdr_valid && image_check_type(&images->legacy_hdr_os_copy, diff --git a/configs/light_a_val_android_defconfig b/configs/light_a_val_android_defconfig index 7e3098ef..3e7109c0 100644 --- a/configs/light_a_val_android_defconfig +++ b/configs/light_a_val_android_defconfig @@ -18,6 +18,7 @@ CONFIG_SYS_PROMPT="C910 Light# " CONFIG_DDR_LP4X_3733_SINGLERANK=y # CONFIG_DDR_LP4_3733_DUALRANK is not set CONFIG_DDR_BOARD_CONFIG=y +CONFIG_FIXUP_MEMORY_REGION=n CONFIG_CMD_BOOT_SLAVE=y CONFIG_CMD_ERASEENV=y CONFIG_CMD_GPT=y diff --git a/configs/light_a_val_defconfig b/configs/light_a_val_defconfig index 83ed1dd1..e94ca99f 100644 --- a/configs/light_a_val_defconfig +++ b/configs/light_a_val_defconfig @@ -22,17 +22,18 @@ CONFIG_SYS_PROMPT="Light VAL-A# " CONFIG_DDR_LP4X_3733_SINGLERANK=y # CONFIG_DDR_LP4_3733_DUALRANK is not set CONFIG_DDR_BOARD_CONFIG=y +CONFIG_FIXUP_MEMORY_REGION=y CONFIG_CMD_BOOT_SLAVE=y CONFIG_CMD_ERASEENV=y CONFIG_CMD_GPT=y CONFIG_CMD_MTD=y +CONFIG_CMD_USB=y CONFIG_CMD_EXT4_WRITE=y CONFIG_CMD_SPI=y CONFIG_CMD_I2C=y CONFIG_CMD_MEMTEST=y CONFIG_DDR_SCAN=y CONFIG_DDR_PRBS_TEST=n -# CONFIG_DOS_PARTITION is not set # CONFIG_ISO_PARTITION is not set CONFIG_PARTITION_TYPE_GUID=y CONFIG_OF_EMBED=y @@ -78,6 +79,9 @@ CONFIG_SPI=y CONFIG_DESIGNWARE_SPI=y CONFIG_DESIGNWARE_QSPI=y CONFIG_USB=y +CONFIG_DM_USB=y +CONFIG_USB_XHCI_HCD=y +CONFIG_USB_XHCI_DWC3=y CONFIG_USB_DWC3=y CONFIG_USB_GADGET=y CONFIG_USB_GADGET_MANUFACTURER="U-Boot-THEAD" @@ -108,3 +112,5 @@ CONFIG_DDR_REGU_0V6=600000 CONFIG_DDR_REGU_0V8=800000 CONFIG_DDR_REGU_1V1=1100000 CONFIG_BOARD_RNG_SEED=y +CONFIG_MISC=y +CONFIG_LIGHT_AON_CONF=y diff --git a/configs/light_a_val_sec_defconfig b/configs/light_a_val_sec_defconfig index 08372c5a..17628629 100644 --- a/configs/light_a_val_sec_defconfig +++ b/configs/light_a_val_sec_defconfig @@ -18,6 +18,7 @@ CONFIG_SYS_PROMPT="C910 Light# " CONFIG_DDR_LP4X_3733_SINGLERANK=y # CONFIG_DDR_LP4_3733_DUALRANK is not set CONFIG_DDR_BOARD_CONFIG=y +CONFIG_FIXUP_MEMORY_REGION=y # CONFIG_TPM is not set # CONFIG_TPM_Z32H330TC_SPI is not set # CONFIG_TPM_V2 is not set @@ -34,7 +35,6 @@ CONFIG_CMD_I2C=y CONFIG_CMD_MEMTEST=y CONFIG_DDR_SCAN=y CONFIG_DDR_PRBS_TEST=n -# CONFIG_DOS_PARTITION is not set # CONFIG_ISO_PARTITION is not set CONFIG_PARTITION_TYPE_GUID=y CONFIG_OF_EMBED=y @@ -79,6 +79,9 @@ CONFIG_SPI=y CONFIG_DESIGNWARE_SPI=y CONFIG_DESIGNWARE_QSPI=y CONFIG_USB=y +CONFIG_DM_USB=y +CONFIG_USB_XHCI_HCD=y +CONFIG_USB_XHCI_DWC3=y CONFIG_USB_DWC3=y CONFIG_USB_GADGET=y CONFIG_USB_GADGET_MANUFACTURER="U-Boot-THEAD" @@ -96,6 +99,7 @@ CONFIG_PHY=y CONFIG_REGMAP=y CONFIG_SYSCON=y CONFIG_CMD_BMP=y +CONFIG_CMD_USB=y CONFIG_VIDEO_BRIDGE=y CONFIG_DM_PCA953X=y CONFIG_VIDEO_VS_DPU=y @@ -108,3 +112,5 @@ CONFIG_PMIC_VOL_INIT=y CONFIG_DDR_REGU_0V6=600000 CONFIG_DDR_REGU_0V8=800000 CONFIG_DDR_REGU_1V1=1100000 +CONFIG_MISC=y +CONFIG_LIGHT_AON_CONF=y diff --git a/configs/light_ant_ref_android_defconfig b/configs/light_ant_ref_android_defconfig index 3af11f1d..d20c324a 100644 --- a/configs/light_ant_ref_android_defconfig +++ b/configs/light_ant_ref_android_defconfig @@ -20,6 +20,7 @@ CONFIG_DDR_LP4X_3200_SINGLERANK=y CONFIG_DDR_H32_MODE=y # CONFIG_DDR_LP4_3733_DUALRANK is not set CONFIG_DDR_BOARD_CONFIG=y +CONFIG_FIXUP_MEMORY_REGION=n CONFIG_CMD_BOOT_SLAVE=y CONFIG_CMD_ERASEENV=y CONFIG_CMD_GPT=y diff --git a/configs/light_ant_ref_defconfig b/configs/light_ant_ref_defconfig index 236e7c29..508d1736 100644 --- a/configs/light_ant_ref_defconfig +++ b/configs/light_ant_ref_defconfig @@ -20,6 +20,7 @@ CONFIG_DDR_LP4X_3200_SINGLERANK=y CONFIG_DDR_H32_MODE=y # CONFIG_DDR_LP4_3733_DUALRANK is not set CONFIG_DDR_BOARD_CONFIG=y +CONFIG_FIXUP_MEMORY_REGION=y CONFIG_CMD_BOOT_SLAVE=y CONFIG_CMD_ERASEENV=y CONFIG_CMD_GPT=y diff --git a/configs/light_ant_ref_sec_defconfig b/configs/light_ant_ref_sec_defconfig index 236e7c29..508d1736 100644 --- a/configs/light_ant_ref_sec_defconfig +++ b/configs/light_ant_ref_sec_defconfig @@ -20,6 +20,7 @@ CONFIG_DDR_LP4X_3200_SINGLERANK=y CONFIG_DDR_H32_MODE=y # CONFIG_DDR_LP4_3733_DUALRANK is not set CONFIG_DDR_BOARD_CONFIG=y +CONFIG_FIXUP_MEMORY_REGION=y CONFIG_CMD_BOOT_SLAVE=y CONFIG_CMD_ERASEENV=y CONFIG_CMD_GPT=y diff --git a/configs/light_b_product_android_defconfig b/configs/light_b_product_android_defconfig index c46a8ec4..c46a57a9 100644 --- a/configs/light_b_product_android_defconfig +++ b/configs/light_b_product_android_defconfig @@ -20,6 +20,7 @@ CONFIG_DDR_LP4X_3200_SINGLERANK=y CONFIG_DDR_H32_MODE=y # CONFIG_DDR_LP4_3733_DUALRANK is not set CONFIG_DDR_BOARD_CONFIG=y +CONFIG_FIXUP_MEMORY_REGION=n CONFIG_CMD_BOOT_SLAVE=y CONFIG_CMD_ERASEENV=y CONFIG_CMD_GPT=y diff --git a/configs/light_b_product_defconfig b/configs/light_b_product_defconfig index f4388adc..f921ea74 100644 --- a/configs/light_b_product_defconfig +++ b/configs/light_b_product_defconfig @@ -20,6 +20,7 @@ CONFIG_DDR_LP4X_3200_SINGLERANK=y CONFIG_DDR_H32_MODE=y # CONFIG_DDR_LP4_3733_DUALRANK is not set CONFIG_DDR_BOARD_CONFIG=y +CONFIG_FIXUP_MEMORY_REGION=y CONFIG_CMD_BOOT_SLAVE=y CONFIG_CMD_ERASEENV=y CONFIG_CMD_GPT=y @@ -104,3 +105,5 @@ CONFIG_PMIC_VOL_INIT=y CONFIG_DDR_REGU_0V6=600000 CONFIG_DDR_REGU_0V8=800000 CONFIG_DDR_REGU_1V1=1100000 +CONFIG_MISC=y +CONFIG_LIGHT_AON_CONF=y diff --git a/configs/light_b_product_sec_defconfig b/configs/light_b_product_sec_defconfig index c9b6fb83..f57e0676 100644 --- a/configs/light_b_product_sec_defconfig +++ b/configs/light_b_product_sec_defconfig @@ -20,6 +20,7 @@ CONFIG_DDR_LP4X_3200_SINGLERANK=y CONFIG_DDR_H32_MODE=y # CONFIG_DDR_LP4_3733_DUALRANK is not set CONFIG_DDR_BOARD_CONFIG=y +CONFIG_FIXUP_MEMORY_REGION=y CONFIG_CMD_BOOT_SLAVE=y CONFIG_CMD_ERASEENV=y CONFIG_CMD_GPT=y @@ -104,3 +105,5 @@ CONFIG_PMIC_VOL_INIT=y CONFIG_DDR_REGU_0V6=600000 CONFIG_DDR_REGU_0V8=800000 CONFIG_DDR_REGU_1V1=1100000 +CONFIG_MISC=y +CONFIG_LIGHT_AON_CONF=y diff --git a/configs/light_beagle_android_defconfig b/configs/light_beagle_android_defconfig index 48942561..4ec3dea3 100644 --- a/configs/light_beagle_android_defconfig +++ b/configs/light_beagle_android_defconfig @@ -19,6 +19,7 @@ CONFIG_SYS_PROMPT="C910 Light# " CONFIG_DDR_LP4X_3733_SINGLERANK=y # CONFIG_DDR_LP4_3733_DUALRANK is not set CONFIG_DDR_BOARD_CONFIG=y +CONFIG_FIXUP_MEMORY_REGION=n CONFIG_CMD_BOOT_SLAVE=y CONFIG_CMD_ERASEENV=y CONFIG_CMD_GPT=y @@ -114,4 +115,4 @@ CONFIG_ANDROID_AB=y CONFIG_CMD_AB_SELECT=y CONFIG_XBC=y CONFIG_BOARD_RNG_SEED=y -CONFIG_SPL_TEXT_BASE=0xffe0000800 \ No newline at end of file +CONFIG_SPL_TEXT_BASE=0xffe0000800 diff --git a/configs/light_lpi4a_android_defconfig b/configs/light_lpi4a_android_defconfig index bbf91a86..8a6db720 100644 --- a/configs/light_lpi4a_android_defconfig +++ b/configs/light_lpi4a_android_defconfig @@ -19,6 +19,7 @@ CONFIG_SYS_PROMPT="C910 Light# " CONFIG_DDR_LP4X_3733_DUALRANK=y # CONFIG_DDR_LP4_3733_DUALRANK is not set CONFIG_DDR_BOARD_CONFIG=y +CONFIG_FIXUP_MEMORY_REGION=n CONFIG_CMD_BOOT_SLAVE=y CONFIG_CMD_ERASEENV=y CONFIG_CMD_GPT=y diff --git a/configs/light_lpi4a_defconfig b/configs/light_lpi4a_defconfig index 3e09c3e7..683540c7 100644 --- a/configs/light_lpi4a_defconfig +++ b/configs/light_lpi4a_defconfig @@ -22,6 +22,7 @@ CONFIG_SYS_PROMPT="Light LPI4A# " CONFIG_DDR_LP4X_3733_DUALRANK=y # CONFIG_DDR_LP4_3733_DUALRANK is not set CONFIG_DDR_BOARD_CONFIG=y +CONFIG_FIXUP_MEMORY_REGION=y CONFIG_CMD_BOOT_SLAVE=y CONFIG_CMD_ERASEENV=y CONFIG_CMD_GPT=y @@ -32,7 +33,6 @@ CONFIG_CMD_I2C=y CONFIG_CMD_MEMTEST=y CONFIG_DDR_SCAN=y CONFIG_DDR_PRBS_TEST=n -# CONFIG_DOS_PARTITION is not set # CONFIG_ISO_PARTITION is not set CONFIG_PARTITION_TYPE_GUID=y CONFIG_OF_EMBED=y @@ -78,6 +78,9 @@ CONFIG_SPI=y CONFIG_DESIGNWARE_SPI=y CONFIG_DESIGNWARE_QSPI=y CONFIG_USB=y +CONFIG_DM_USB=y +CONFIG_USB_XHCI_HCD=y +CONFIG_USB_XHCI_DWC3=y CONFIG_USB_DWC3=y CONFIG_USB_GADGET=y CONFIG_USB_GADGET_MANUFACTURER="U-Boot-THEAD" @@ -95,10 +98,13 @@ CONFIG_PHY=y CONFIG_REGMAP=y CONFIG_SYSCON=y CONFIG_CMD_BMP=y +CONFIG_CMD_USB=y CONFIG_VIDEO_BRIDGE=y CONFIG_DM_PCA953X=y CONFIG_VIDEO_VS_DPU=y -CONFIG_VIDEO_LCD_ILITEK_ILI9881C=y +CONFIG_VIDEO_LCD_ILITEK_ILI9881C=n +CONFIG_VIDEO_LCD_JD9365DA=y +#CONFIG_VIDEO_LCD_CUSTOM_LOGO=y CONFIG_VIDEO_DW_DSI_LIGHT=y CONFIG_VIDEO_DW_DPHY=y CONFIG_VIDEO_DW_DSI_HOST=y @@ -108,3 +114,5 @@ CONFIG_DDR_REGU_0V6=600000 CONFIG_DDR_REGU_0V8=800000 CONFIG_DDR_REGU_1V1=1100000 CONFIG_BOARD_RNG_SEED=y +CONFIG_MISC=y +CONFIG_LIGHT_AON_CONF=y diff --git a/configs/light_lpi4a_sec_defconfig b/configs/light_lpi4a_sec_defconfig index 27a100bf..37190ffc 100644 --- a/configs/light_lpi4a_sec_defconfig +++ b/configs/light_lpi4a_sec_defconfig @@ -22,6 +22,7 @@ CONFIG_SYS_PROMPT="C910 Light# " CONFIG_DDR_LP4X_3733_DUALRANK=y # CONFIG_DDR_LP4_3733_DUALRANK is not set CONFIG_DDR_BOARD_CONFIG=y +CONFIG_FIXUP_MEMORY_REGION=y CONFIG_CMD_BOOT_SLAVE=y CONFIG_CMD_ERASEENV=y CONFIG_CMD_GPT=y @@ -32,7 +33,6 @@ CONFIG_CMD_I2C=y CONFIG_CMD_MEMTEST=y CONFIG_DDR_SCAN=y CONFIG_DDR_PRBS_TEST=n -# CONFIG_DOS_PARTITION is not set # CONFIG_ISO_PARTITION is not set CONFIG_PARTITION_TYPE_GUID=y CONFIG_OF_EMBED=y @@ -77,6 +77,9 @@ CONFIG_SPI=y CONFIG_DESIGNWARE_SPI=y CONFIG_DESIGNWARE_QSPI=y CONFIG_USB=y +CONFIG_DM_USB=y +CONFIG_USB_XHCI_HCD=y +CONFIG_USB_XHCI_DWC3=y CONFIG_USB_DWC3=y CONFIG_USB_GADGET=y CONFIG_USB_GADGET_MANUFACTURER="U-Boot-THEAD" @@ -93,10 +96,13 @@ CONFIG_PHY=y CONFIG_REGMAP=y CONFIG_SYSCON=y CONFIG_CMD_BMP=y +CONFIG_CMD_USB=y CONFIG_VIDEO_BRIDGE=y CONFIG_DM_PCA953X=y CONFIG_VIDEO_VS_DPU=y -CONFIG_VIDEO_LCD_ILITEK_ILI9881C=y +CONFIG_VIDEO_LCD_ILITEK_ILI9881C=n +CONFIG_VIDEO_LCD_JD9365DA=y +#CONFIG_VIDEO_LCD_CUSTOM_LOGO=y CONFIG_VIDEO_DW_DSI_LIGHT=y CONFIG_VIDEO_DW_DPHY=y CONFIG_VIDEO_DW_DSI_HOST=y @@ -105,3 +111,5 @@ CONFIG_PMIC_VOL_INIT=y CONFIG_DDR_REGU_0V6=600000 CONFIG_DDR_REGU_0V8=800000 CONFIG_DDR_REGU_1V1=1100000 +CONFIG_MISC=y +CONFIG_LIGHT_AON_CONF=y diff --git a/drivers/fastboot/fb_command.c b/drivers/fastboot/fb_command.c index 4b5a7a13..92b33b89 100644 --- a/drivers/fastboot/fb_command.c +++ b/drivers/fastboot/fb_command.c @@ -310,6 +310,7 @@ static void flash(char *cmd_parameter, char *response) char cmdbuf[32]; u32 block_cnt; struct blk_desc *dev_desc; + disk_partition_t info; int ret = 0; if (strcmp(cmd_parameter, "uboot") == 0) { @@ -351,8 +352,25 @@ static void flash(char *cmd_parameter, char *response) memcpy((void *)LIGHT_TF_FW_ADDR, fastboot_buf_addr, image_size); } else if ((strcmp(cmd_parameter, TEE_PART_NAME) == 0)) { memcpy((void *)LIGHT_TEE_FW_ADDR, fastboot_buf_addr, image_size); + } else if ((strcmp(cmd_parameter, "boot") == 0)) { + dev_desc = blk_get_dev("mmc", CONFIG_FASTBOOT_FLASH_MMC_DEV); + if (!dev_desc || dev_desc->type == DEV_TYPE_UNKNOWN) { + fastboot_fail("invalid mmc device", response); + return; + } + /* if fastresume partition exists, earse the old image header */ + if(part_get_info_by_name(dev_desc, "fastresume", &info)) { + printf(" find fastresume partition , erase the header:\n"); + char * buf = memalign(CONFIG_SYS_CACHELINE_SIZE,4096); + if(!buf) { + printf(" fastresume partition header mem alloc failed\n"); + return; + } + memset(buf,0xff,4096); + blk_dwrite(dev_desc, info.start, 4096/info.blksz, buf); + free(buf); + } } - if(strcmp(cmd_parameter, "uboot") == 0 || (strcmp(cmd_parameter, "fw") == 0) || (strcmp(cmd_parameter, "uImage") == 0) || (strcmp(cmd_parameter, "dtb") == 0) || (strcmp(cmd_parameter, "rootfs") == 0) || (strcmp(cmd_parameter, "aon") == 0)) { diff --git a/drivers/misc/Kconfig b/drivers/misc/Kconfig index 82bb093c..a19cdec7 100644 --- a/drivers/misc/Kconfig +++ b/drivers/misc/Kconfig @@ -439,4 +439,10 @@ config K3_AVS0 optimized voltage from the efuse, so that it can be programmed to the PMIC on board. +config LIGHT_AON_CONF + bool "Light aon config support" + depends on MISC + help + Select this to enable aon config by dts. + endmenu diff --git a/drivers/misc/Makefile b/drivers/misc/Makefile index 55976d6b..548be165 100644 --- a/drivers/misc/Makefile +++ b/drivers/misc/Makefile @@ -68,3 +68,4 @@ obj-$(CONFIG_WINBOND_W83627) += winbond_w83627.o obj-$(CONFIG_JZ4780_EFUSE) += jz4780_efuse.o obj-$(CONFIG_MICROCHIP_FLEXCOM) += microchip_flexcom.o obj-$(CONFIG_K3_AVS0) += k3_avs.o +obj-$(CONFIG_LIGHT_AON_CONF) += light_regu.o diff --git a/drivers/misc/light_regu.c b/drivers/misc/light_regu.c new file mode 100644 index 00000000..7d93a583 --- /dev/null +++ b/drivers/misc/light_regu.c @@ -0,0 +1,975 @@ +#include +#include +#include +#include +#include +#include +#include +#include "light_regu.h" + +#define FDT32_TO_CPU(x) (fdt32_to_cpu(x)) + +#ifndef ARRAY_SIZE +#define ARRAY_SIZE(x) (szieof(x) / sizeof(x[0])) +#endif + +#ifndef MIN +#define MIN(x, y) ((x) < (y) ? (x) : (y)) +#endif + +#ifdef AON_CONF_DEBUG +#define AON_CONF_D(fmt, args...) printf(fmt,##args) +#else +#define AON_CONF_D(fmt, args...) +#endif + +#define SOC_VIRTUAL_ID(virtual_id) \ + { \ + .id = virtual_id, \ + .virtual_id_name = #virtual_id, \ + } + +soc_virtual_id_t soc_base_virtual_id_list[] = { + SOC_VIRTUAL_ID(SOC_DVDD18_AON), /*da9063: ldo-3 */ + SOC_VIRTUAL_ID(SOC_AVDD33_USB3), /*da9063: ldo-9 */ + SOC_VIRTUAL_ID(SOC_DVDD08_AON), /*da9063: ldo-2 */ + SOC_VIRTUAL_ID(SOC_APCPU_DVDD_DVDDM), /*da9063: vbcore1 & vbcore2*/ + SOC_VIRTUAL_ID(SOC_DVDD08_DDR), /*da9063: buckperi */ + SOC_VIRTUAL_ID(SOC_VDD_DDR_1V8), /*da9063: ldo-4 */ + SOC_VIRTUAL_ID(SOC_VDD_DDR_1V1), /*da9063: buckmem & buckio */ + SOC_VIRTUAL_ID(SOC_VDD_DDR_0V6), /*da9063: buckpro */ + SOC_VIRTUAL_ID(SOC_DVDD18_AP), /*da9063: ldo-11 */ + SOC_VIRTUAL_ID(SOC_DVDD08_AP), /*da9121: da9121_ex */ + SOC_VIRTUAL_ID(SOC_AVDD08_MIPI_HDMI), /*da9063: ldo-1 */ + SOC_VIRTUAL_ID(SOC_AVDD18_MIPI_HDMI), /*da9063: ldo-5 */ + SOC_VIRTUAL_ID(SOC_DVDD33_EMMC), /*da9063: ldo-10 */ + SOC_VIRTUAL_ID(SOC_DVDD18_EMMC), /*slg51000:ldo-3 */ + SOC_VIRTUAL_ID(SOC_DOVDD18_SCAN), /*da9063: ldo-6 */ + SOC_VIRTUAL_ID(SOC_VEXT_2V8), /*da9063: ldo-7 */ + SOC_VIRTUAL_ID(SOC_DVDD12_SCAN), /*da9063: ldo-8 */ + SOC_VIRTUAL_ID(SOC_AVDD28_SCAN_EN), /*da9063: gpio-4),SGM2019-ADJ */ + SOC_VIRTUAL_ID(SOC_AVDD28_RGB), /*slg51000:ldo-1 */ + SOC_VIRTUAL_ID(SOC_DOVDD18_RGB), /*slg51000:ldo-4 */ + SOC_VIRTUAL_ID(SOC_DVDD12_RGB), /*slg51000:ldo-5 */ + SOC_VIRTUAL_ID(SOC_AVDD25_IR), /*slg51000:ldo-2 */ + SOC_VIRTUAL_ID(SOC_DOVDD18_IR), /*slg51000:ldo-7 */ + SOC_VIRTUAL_ID(SOC_DVDD12_IR), /*slg51000:ldo-6 */ + SOC_VIRTUAL_ID(SOC_ADC_VREF), + SOC_VIRTUAL_ID(SOC_LCD0_EN), + SOC_VIRTUAL_ID(SOC_VEXT_1V8), +}; + +static int misc_regu_probe(struct udevice *dev) +{ + return 0; +} + +static int misc_regu_remove(struct udevice *dev) +{ + return 0; +} + +static soc_virtual_id_t *found_base_virtual_id(char *name) +{ + for (int i = 0; i < ARRAY_SIZE(soc_base_virtual_id_list); i++) + { + if (!strcasecmp(soc_base_virtual_id_list[i].virtual_id_name, name)) + { + return &soc_base_virtual_id_list[i]; + } + } + return NULL; +} + +static inline char toupper(char str1) +{ + if (str1 >= 'a' && str1 <= 'z') + { + return str1 - 'a' + 'A'; + } + return str1; +} + +void string_to_upper(char *str) +{ + if (str == NULL) + return; + + while (*str) + { + *str = toupper((unsigned char)*str); + str++; + } +} + +static int misc_regu_get_virtual_regu_config(struct udevice *dev, ofnode parent_node, virtual_regu_list_t *regu_list) +{ + int regu_num = 0; + int ret; + ofnode child_node; + soc_virtual_id_t *id_list; + soc_virtual_id_t *soc_base_id; + ofnode_for_each_subnode(child_node, parent_node) + { + //printf("sub node name: %s\n", ofnode_get_name(child_node)); + regu_num++; + } + + if (!regu_num) + { + printf("regu list not found in dts\n"); + return -1; + } + + id_list = devm_kcalloc(dev, 1, regu_num * sizeof(soc_virtual_id_t), GFP_KERNEL); + if (!id_list) + { + printf("regu id malloc faild\n"); + return -ENOMEM; + } + + int index = 0; + int new_regu_index = ARRAY_SIZE(soc_base_virtual_id_list); + + ofnode_for_each_subnode(child_node, parent_node) + { + const char *virtual_id_name = ofnode_get_name(child_node); + int min_uv; + int max_uv; + soc_base_id = found_base_virtual_id(virtual_id_name); + if (soc_base_id) + { + id_list[index].id = soc_base_id->id; + } + else + { + id_list[index].id = new_regu_index++; + } + + int copy_size = MIN(sizeof(id_list[index].virtual_id_name) - 1, strlen(virtual_id_name)); + memcpy(id_list[index].virtual_id_name, virtual_id_name, copy_size); + id_list[index].virtual_id_name[copy_size] = '\0'; + + string_to_upper(id_list[index].virtual_id_name); + + ret = ofnode_read_u32(child_node, "regulator-min-microvolt", &min_uv); + if (ret) + { + // printf("%s :regulator-min-microvolt not set, min_uv set to -1", virtual_id_name); + id_list[index].min_uv = -1; + } + else + { + id_list[index].min_uv = min_uv; + } + + ret = ofnode_read_u32(child_node, "regulator-max-microvolt", &max_uv); + if (ret) + { + // printf("%s :regulator-max-microvolt not set, max_uv set to -1", virtual_id_name); + id_list[index].max_uv = -1; + } + else + { + id_list[index].max_uv = max_uv; + } +#warning "check double" + // printf("Get virtual regu_id:[%d]:%s min_uv:%dmv max_uv:%dmv\n", id_list[index].id, id_list[index].virtual_id_name, + // id_list[index].min_uv, id_list[index].max_uv); + index++; + } + + (*regu_list).regu_num = regu_num; + (*regu_list).regu_list = id_list; + + return 0; +} + +static int misc_grep_pmic_dev_name_info(char *dev_name, pmic_dev_info_t *dev) +{ + int flag_num = 0; + int version_flag = 0; + int index = 0; + char *dev_name_orig = dev_name; + while (*dev_name) + { + if (*dev_name == ',') + { + flag_num++; + if (flag_num == 2) + { + version_flag = index; + } + } + index++; + dev_name++; + } + + if (flag_num != 2 || *(dev_name - 1) == ',') + { + printf("pmic-name should set as pmic-name = \"vendor,type,version"); + return -1; + } + + int len = MIN((version_flag), sizeof(dev->device_name) - 1); + memcpy(dev->device_name, dev_name_orig, len); + dev->device_name[len] = '\0'; + len = MIN((index - version_flag - 1), sizeof(dev->device_name) - 1); + memcpy(dev->version_name, dev_name_orig + version_flag + 1, len); + dev->version_name[len] = '\0'; + return 0; +} + +static int get_node_index(const char *name) +{ + while (*name && *name != '@') + { + name++; + } + + if (strlen(name) == 0) + { + return -1; + } + name++; + return strtoul(name, NULL, 10); +} + +static int misc_regu_get_pmic_dev_config(ofnode parent_node, pmic_dev_info_t *pmic_dev_info_list) +{ + int ret = 0; + ofnode child_node, errio_node; + fdt_addr_t index; + char *pmic_name; + int pmic_wdt_flag = 0; + int pmic_index = 0; + int pmic_addr_len = 0, pmic_addr_size; + int gpio_addr_len = 0, gpio_addr_size; + char err_io_str[40] = "NOT_SUPPORT"; + char lpm_io_str[40] = "NOT_SUPPORT"; + uint32_t port, pin, trigger_mode; + uint32_t phandle; + const uint32_t *prop_val; + + ofnode_for_each_subnode(child_node, parent_node) + { + pmic_dev_info_t *dev = &(pmic_dev_info_list[pmic_index]); + const char *node_name = ofnode_get_name(child_node); + if (!strncmp(node_name, PMIC_DEV_DTS_NAME, strlen(PMIC_DEV_DTS_NAME))) + { + index = get_node_index(node_name); + if (index < 0) + { + printf("get pmic_dev id faild"); + return -1; + } + pmic_name = ofnode_read_string(child_node, "pmic-name"); + if (!pmic_name) + { + printf("pmic_name property not set for %s%d", PMIC_DEV_DTS_NAME, index); + return -1; + } + + if (ofnode_read_bool(child_node, "pmic_wdt_on")) + { + if (pmic_wdt_flag) + { + printf("only one pmic dev support wdt\n"); + return -1; + } + dev->flag |= PMIC_DEV_ENABLE_WDT; + pmic_wdt_flag = 1; + } + + prop_val = ofnode_get_property(child_node, "pmic-addr", &pmic_addr_len); + if (!prop_val) + { + printf("pmic-addr property not found\n"); + return -1; + } + pmic_addr_size = pmic_addr_len / sizeof(uint32_t); + + if (pmic_addr_size != 2 && pmic_addr_size!= 1) + { + printf("invalid pmic-addr cell size %d\n", pmic_addr_size); + return -1; + } + + dev->addr1 = FDT32_TO_CPU(prop_val[0]); + dev->addr2 = pmic_addr_size == 2 ? FDT32_TO_CPU(prop_val[1]) : dev->addr1; + + prop_val = ofnode_get_property(child_node, "errio_gpio", &gpio_addr_len); + if (prop_val) + { + gpio_addr_size = gpio_addr_len / sizeof(uint32_t); + if (gpio_addr_size != 3) + { + printf("invalid errio_gpio cell size %d\n", gpio_addr_size); + return -1; + } + else + { + port = FDT32_TO_CPU(prop_val[0]); + pin = 1 << FDT32_TO_CPU(prop_val[1]); + trigger_mode = FDT32_TO_CPU(prop_val[2]); + dev->flag |= PMIC_DEV_ENABLE_ERR_IO; + dev->err_io_info.gpio_port = port; + dev->err_io_info.pin = pin; + dev->err_io_info.trigger_mode = trigger_mode; + sprintf(err_io_str, "port:%d pin:%d trigger:%d", port, pin, trigger_mode); + } + } else { + sprintf(err_io_str, "NOT_SUPPORT"); + } + + prop_val = ofnode_get_property(child_node, "lpm_gpio", &gpio_addr_len); + if (prop_val) + { + gpio_addr_size = gpio_addr_len / sizeof(uint32_t); + if (gpio_addr_size != 3) + { + printf("invalid lpm_gpio cell size %d\n", gpio_addr_size); + return -1; + } + else + { + port = FDT32_TO_CPU(prop_val[0]); + pin = 1 << FDT32_TO_CPU(prop_val[1]); + trigger_mode = FDT32_TO_CPU(prop_val[2]); + dev->flag |= PMIC_DEV_ENABLE_LPM_IO; + dev->lpm_io_info.gpio_port = port; + dev->lpm_io_info.pin = pin; + dev->lpm_io_info.trigger_mode = trigger_mode; + sprintf(lpm_io_str, "port:%d pin:%d trigger:%d", port, pin, trigger_mode); + } + } else { + sprintf(lpm_io_str,"NOT_SUPPORT"); + } + + dev->pmic_id = index; + ret = misc_grep_pmic_dev_name_info(pmic_name, dev); + pmic_index++; + AON_CONF_D("Get pmic dev:[%d]:%s|%s addr1:0x%02x addr2:0x%02x wdt:{%s} errio:{%s} lpm_io:{%s}\n", index, dev->device_name, dev->version_name, dev->addr1, dev->addr2, (dev->flag & PMIC_DEV_ENABLE_WDT ? "SUPPORT" : "NOT_SUPPORT"), err_io_str, lpm_io_str); + } + } + return 0; +} + +static int misc_regu_get_pmic_dev_by_name(const char *name, int pmic_dev_num, pmic_dev_info_t *pmic_dev_info_list) +{ + int pmic_id = get_node_index(name); + if (pmic_id < 0) + { + return -1; + } + + int pmic_index = 0; + for (; pmic_index < pmic_dev_num; pmic_index++) + { + if (pmic_dev_info_list[pmic_index].pmic_id == pmic_id) + { + break; + } + } + + if (pmic_index == pmic_dev_num) + { + printf("%s not found in pmic list\n", name); + return -1; + } + + return pmic_index; +} + +static int misc_regu_get_each_regu_hw_id_config(ofnode regu_id_node, int pmic_dev_num, pmic_dev_info_t *pmic_dev_info_list, soc_virtual_id_t *virtual_id_info, pmic_hw_info_t *id) +{ + uint32_t phandle; + ofnode pmic_node, pmic_parent_node; + + char *pmic_name; + + int prop_len, prop_size; + int on_order, on_delay_ms; + int off_order, off_delay_ms; + int pmic_index, parent_pmic_index; + const uint32_t *prop_val; + + /*get pmic_dev = <&pmic_dev_0 DA9063_ID_BCORE1>*/ + prop_val = ofnode_get_property(regu_id_node, "pmic_dev", &prop_len); + if (!prop_val) + { + printf("pmic-addr property not found\n"); + return -1; + } + + prop_size = prop_len / sizeof(uint32_t); + if (prop_size != 2) + { + printf("pmic_dev property should set in format as pmic_dev = <&pmic_dev_num HW_ID>;\n"); + return -1; + } + + pmic_node = ofnode_get_by_phandle(FDT32_TO_CPU(prop_val[0])); + if (!ofnode_valid(pmic_node)) + { + printf("pmic node not found\n"); + return -1; + } + + pmic_index = misc_regu_get_pmic_dev_by_name(ofnode_get_name(pmic_node), pmic_dev_num, pmic_dev_info_list); + if (pmic_index < 0) + { + return -1; + } + + (*id).pmic_id = pmic_dev_info_list[pmic_index].pmic_id; + (*id).hw_id = FDT32_TO_CPU(prop_val[1]); + + /*get auto_on_info = <0 1 800000>*/ + prop_val = ofnode_get_property(regu_id_node, "auto_on_info", &prop_len); + if (!prop_val) + { + (*id).soft_power_ctrl_info.on_info.on_order = HW_ID_NO_SOFT_AUTO_ON; + } + else + { + prop_size = prop_len / sizeof(uint32_t); + if (prop_size != 3 && prop_size != 2) + { + printf("auto_on_info property should set in format as auto_on_info = \n"); + return -1; + } + if (virtual_id_info->min_uv != -1 && FDT32_TO_CPU(prop_val[2]) < virtual_id_info->min_uv) + { + printf("virtual regu %s voltage shoud larger than %dmv, it is %dmv\n", virtual_id_info->virtual_id_name, virtual_id_info->min_uv, FDT32_TO_CPU(prop_val[2])); + return -1; + } + if (virtual_id_info->max_uv != -1 && FDT32_TO_CPU(prop_val[2]) > virtual_id_info->max_uv) + { + printf("virtual regu %s voltage shoud less than %dmv, it is %dmv\n", virtual_id_info->virtual_id_name, virtual_id_info->max_uv, FDT32_TO_CPU(prop_val[2])); + return -1; + } + (*id).soft_power_ctrl_info.on_info.on_order = FDT32_TO_CPU(prop_val[0]); + (*id).soft_power_ctrl_info.on_info.on_delay_ms = FDT32_TO_CPU(prop_val[1]); + if(prop_size == 3) { + (*id).soft_power_ctrl_info.on_info.init_target_uv = FDT32_TO_CPU(prop_val[2]); + } else { + (*id).soft_power_ctrl_info.on_info.init_target_uv = 0; + } + + } + + /*get auto_off_info = <1 1>*/ + prop_val = ofnode_get_property(regu_id_node, "auto_off_info", &prop_len); + if (!prop_val) + { + (*id).soft_power_ctrl_info.off_info.off_order = HW_ID_NO_SOFT_AUTO_OFF; + } + else + { + prop_size = prop_len / sizeof(uint32_t); + if (prop_size != 2) + { + printf("auto_off_info property should set in format as auto_off_info = \n"); + return -1; + } + (*id).soft_power_ctrl_info.off_info.off_order = FDT32_TO_CPU(prop_val[0]); + (*id).soft_power_ctrl_info.off_info.off_delay_ms = FDT32_TO_CPU(prop_val[1]); + } + + /*get parent_pmic_dev = <&pmic_dev_0 2 1>*/ + prop_val = ofnode_get_property(regu_id_node, "parent_pmic_dev", &prop_len); + if (!prop_val) + { + (*id).parent_hw_info.pmic_id = PMIC_ID_INVALID; + } + else + { + prop_size = prop_len / sizeof(uint32_t); + if (prop_size != 3) + { + printf("parent_pmic_dev property should set in format as parent_pmic_dev = <&pmic_dev_num IO_ID ACTIVATE_STATUS>;\n"); + return -1; + } + + pmic_parent_node = ofnode_get_by_phandle(FDT32_TO_CPU(prop_val[0])); + if (!ofnode_valid(pmic_parent_node)) + { + printf("pmic_parent node not found\n"); + return -1; + } + + pmic_index = misc_regu_get_pmic_dev_by_name(ofnode_get_name(pmic_parent_node), pmic_dev_num, pmic_dev_info_list); + if (pmic_index < 0) + { + return -1; + } + + (*id).parent_hw_info.pmic_id = pmic_dev_info_list[pmic_index].pmic_id; + (*id).parent_hw_info.io_hw_id = FDT32_TO_CPU(prop_val[1]); +#warning "check status" + (*id).parent_hw_info.activate_status = FDT32_TO_CPU(prop_val[2]); + } + + return 0; +} + +static int misc_regu_get_each_regu_config(ofnode regu_config_node, int pmic_dev_num, pmic_dev_info_t *pmic_dev_info_list, soc_virtual_id_t *regu_info, csi_regu_id_t *pmic_regu_id_info) +{ + int ret = 0; + ofnode hw_id_node; + ofnode coupling_node; + uint32_t phandle = 0; + int index = 0; + char *regu_id_name; + const uint32_t *prop_val; + int prop_len = 0; + int prop_size = 0; + int coupling_num = 0; + uint16_t hw_id_used_flag = 0x0; + + ofnode_for_each_subnode(hw_id_node, regu_config_node) + { + const char *node_name = ofnode_get_name(hw_id_node); + if (!strncmp(node_name, REGU_ID_NAME, strlen(REGU_ID_NAME))) + { + index = get_node_index(node_name); + if (index < 0) + { + printf("get hw_id faild"); + return -1; + } + + if (index >= PMIC_MAX_HW_ID_NUM || index >= 8 * sizeof(uint16_t)) + { + printf("regu_id index should less than %d\n", MIN(PMIC_MAX_HW_ID_NUM, 8 * sizeof(uint16_t))); + return -1; + } + + if ((hw_id_used_flag >> index) & 0x01) + { + printf("%s@%d already exist\n", REGU_ID_NAME, index); + return -1; + } + else + { + hw_id_used_flag |= 0x01 << index; + } + + ret = misc_regu_get_each_regu_hw_id_config(hw_id_node, pmic_dev_num, pmic_dev_info_list, regu_info, &pmic_regu_id_info->sub.id[index]); + if (ret) + { + printf("get hw_id@%d config faild %d\n", ret); + return -1; + } + } + + } + + for (int i = PMIC_MAX_HW_ID_NUM - 1; i >= 0; i--) + { + if ((hw_id_used_flag & (0x01 << i)) == 0x0) + { + (*pmic_regu_id_info).sub.id[i].pmic_id = PMIC_ID_INVALID; + } + } + + ofnode_for_each_subnode(coupling_node, regu_config_node) + { + const char *node_name = ofnode_get_name(coupling_node); + + if (!strncmp(node_name, COUPLING_ID_INFO_NAME, strlen(COUPLING_ID_INFO_NAME))) + { + /*get info = <0 1 -5 30>;*/ + prop_val = ofnode_get_property(coupling_node, "info", &prop_len); + if (!prop_val) + { + printf("no info property set for %s", node_name); + return -1; + } else + { + prop_size = prop_len / sizeof(uint32_t); + if (prop_size != 4) + { + printf("coupling info property should set in format as info = \n"); + return -1; + } + + int id0 = FDT32_TO_CPU(prop_val[0]); + int id1 = FDT32_TO_CPU(prop_val[1]); + int8_t max_spread = FDT32_TO_CPU(prop_val[2]); + int8_t min_spread = FDT32_TO_CPU(prop_val[3]); + + if(ofnode_read_bool(coupling_node, "negative-min")) { + min_spread = -min_spread; + } + if(ofnode_read_bool(coupling_node, "negative-max")) { + max_spread = -max_spread; + } + if(id0 == id1) { + printf("coupling info: id0 id1 should not be equal"); + return -1; + } + if(min_spread > max_spread) { + printf("coupling info: min_spread:%d is higher than max_spread:%d", min_spread, max_spread); + return -1; + } + if(id0 >= PMIC_MAX_HW_ID_NUM || id1 >= PMIC_MAX_HW_ID_NUM) { + printf("coupling info: id0:%d id1:%d is higher than max_id:%d", id0, id1, PMIC_MAX_HW_ID_NUM -1); + return -1; + } + + if((*pmic_regu_id_info).sub.id[id0].pmic_id == PMIC_ID_INVALID || (*pmic_regu_id_info).sub.id[id1].pmic_id == PMIC_ID_INVALID) { + printf("coupling info:id0:%d id1:%d is invalid", id0, id1); + return -1; + } + (*pmic_regu_id_info).sub.coupling_list[coupling_num].id0 = id0; + (*pmic_regu_id_info).sub.coupling_list[coupling_num].id1 = id1; + (*pmic_regu_id_info).sub.coupling_list[coupling_num].max_spread = max_spread; + (*pmic_regu_id_info).sub.coupling_list[coupling_num].min_spread = min_spread; + coupling_num++; + if(coupling_num > PMIC_MAX_COUPLING_NUM) { + printf("coupling info should no more than %d\n", coupling_num); + return -1; + } + } + } + + } + + for(int i = PMIC_MAX_COUPLING_NUM - 1; i >= coupling_num; i--) + { + (*pmic_regu_id_info).sub.coupling_list[i].id0 = REGU_SUB_ID_INVALID; + (*pmic_regu_id_info).sub.coupling_list[i].id1 = REGU_SUB_ID_INVALID; + } + + return 0; +} + +static int misc_regu_get_regu_config(ofnode parent_node, int pmic_dev_num, pmic_dev_info_t *pmic_dev_info_list, int virtual_id_num, soc_virtual_id_t *regu_list, csi_regu_id_t *pmic_regu_id_list) +{ + ofnode child_node; + int index = 0; + uint32_t phandle = 0; + int ret = 0; + ofnode regu_virtual_node; + char *regu_id_name; + int virtual_id_index = 0; + uint16_t virtual_id_config_flag = 0; + int regu_config_index = 0; + + ofnode_for_each_subnode(child_node, parent_node) + { + virtual_id_index = 0; + char *node_name = ofnode_get_name(child_node); + if (!strncmp(node_name, REGU_ID_CONF_NAME, strlen(REGU_ID_CONF_NAME))) + { + + if (ofnode_read_u32(child_node, "reg_info", &phandle)) + { + printf("reg_info property not found\n"); + return -1; + } + + regu_virtual_node = ofnode_get_by_phandle(phandle); + if (!ofnode_valid(regu_virtual_node)) + { + printf("virtual_regu_node not found\n"); + return -1; + } + + regu_id_name = ofnode_get_name(regu_virtual_node); + + for (; virtual_id_index < virtual_id_num; virtual_id_index++) + { + if (!strcasecmp(regu_list[virtual_id_index].virtual_id_name, regu_id_name)) + { + break; + } + } + + if (virtual_id_index == virtual_id_num) + { + printf("virtual regu id %s not found\n", regu_id_name); + return -1; + } + + int virtual_id = regu_list[virtual_id_index].id; + + if ((virtual_id_config_flag >> virtual_id) & 0x01) + { + printf("%s config for %s already exist\n!", REGU_ID_CONF_NAME, regu_list[virtual_id_index].virtual_id_name); + return -1; + } + else + { + virtual_id_config_flag |= 0x01 << virtual_id; + } + + csi_regu_id_t *regu_conf = &pmic_regu_id_list[regu_config_index]; + + regu_conf->regu_ext_id = virtual_id; + int copy_size = MIN(sizeof(regu_conf->regu_ext_id_name) - 1, strlen(regu_list[virtual_id_index].virtual_id_name)); + memcpy(regu_conf->regu_ext_id_name, regu_list[virtual_id_index].virtual_id_name, copy_size); + + ret = misc_regu_get_each_regu_config(child_node, pmic_dev_num, pmic_dev_info_list, ®u_list[virtual_id_index], regu_conf); + if (ret) + { + return -1; + } + + AON_CONF_D("Get regu config, virtual_regu_id:[%d]:%s min_uv:%dmv max_uv:%dmv\n", virtual_id, regu_list[virtual_id_index].virtual_id_name, regu_list[virtual_id_index].min_uv,regu_list[virtual_id_index].max_uv); + for (int i = 0; i < ARRAY_SIZE(regu_conf->sub.id); i++) + { + pmic_hw_info_t *sub = ®u_conf->sub.id[i]; + if (sub->pmic_id != PMIC_ID_INVALID) + { + char parent_info[50]; + char auto_on_info[50]; + char auto_off_info[50]; + + if (sub->parent_hw_info.pmic_id == PMIC_ID_INVALID) + { + sprintf(parent_info, "{NO_PARENT_PMIC}"); + } + else + { + sprintf(parent_info, "{parent_pmic_dev:%d io_hw_id:%d activate_status:%d}", sub->parent_hw_info.pmic_id, sub->parent_hw_info.io_hw_id, sub->parent_hw_info.activate_status); + } + + if (sub->soft_power_ctrl_info.on_info.on_order == HW_ID_NO_SOFT_AUTO_ON) + { + sprintf(auto_on_info, "{NOT_SUPPORT}"); + } + else + { + sprintf(auto_on_info, "{on_order:%d on_delay:%d on_uv:%dmv}", sub->soft_power_ctrl_info.on_info.on_order, sub->soft_power_ctrl_info.on_info.on_delay_ms, sub->soft_power_ctrl_info.on_info.init_target_uv); + } + if (sub->soft_power_ctrl_info.off_info.off_order == HW_ID_NO_SOFT_AUTO_OFF) + { + sprintf(auto_off_info, "{NOT_SUPPORT}"); + } + else + { + sprintf(auto_off_info, "{off_order:%d off_delay:%d}", sub->soft_power_ctrl_info.off_info.off_order, sub->soft_power_ctrl_info.off_info.off_delay_ms); + } + + AON_CONF_D(">>>>>>%s@%d:{pmic_dev:%d hw_id:%d} parent_info:%s auto_on_info:%s auto_off_info:%s\n", REGU_ID_NAME, i, sub->pmic_id, sub->hw_id, parent_info, auto_on_info, auto_off_info); + } + } + int temp_flag = 0; + for(int i = 0; i < ARRAY_SIZE(regu_conf->sub.coupling_list); i++) { + coupling_desc_t* coupling_info = ®u_conf->sub.coupling_list[i]; + if(coupling_info->id0 != REGU_SUB_ID_INVALID) { + if(!temp_flag) { + AON_CONF_D(">>>>>>"); + temp_flag = 1; + } + AON_CONF_D("%s@%d:{id0:%d id1:%d max_spreed:%dmv min_spreed:%dmv} ", COUPLING_ID_INFO_NAME, i,coupling_info->id0, coupling_info->id1, coupling_info->max_spread *10 , coupling_info->min_spread * 10); + } + } + if(temp_flag) { + AON_CONF_D("\n"); + } + regu_config_index++; + } + } + +#warning "add no config check" + return 0; +} + +static int misc_regu_get_aon_pmic_config(struct udevice *dev, ofnode parent_node, int virtual_id_num, soc_virtual_id_t *regu_list, pmic_dev_list_t *pmic_list, regu_id_list_t *regu_id_list) +{ + ofnode child_node; + int pmic_dev_num = 0; + int regu_id_conf_num = 0; + pmic_dev_info_t *pmic_dev_info_list; + csi_regu_id_t *pmic_regu_id_list; + + const char *node_name; + int ret = 0; + + ofnode_for_each_subnode(child_node, parent_node) + { + node_name = ofnode_get_name(child_node); + if (!strncmp(node_name, PMIC_DEV_DTS_NAME, strlen(PMIC_DEV_DTS_NAME))) + { + pmic_dev_num++; + } + } + + if (!pmic_dev_num) + { + printf("No %s node in dts\n", PMIC_DEV_DTS_NAME); + return -1; + } + + pmic_dev_info_list = devm_kcalloc(dev, 1, pmic_dev_num * sizeof(pmic_dev_info_t), GFP_KERNEL); + if (!pmic_dev_info_list) + { + printf("pmic dev list malloc faild\n"); + return -ENOMEM; + } + + ret = misc_regu_get_pmic_dev_config(parent_node, pmic_dev_info_list); + if (ret) + { + printf("pmic dev config get faild %d", ret); +#warning "free" + return -1; + } + + ofnode_for_each_subnode(child_node, parent_node) + { + node_name = ofnode_get_name(child_node); + if (!strncmp(node_name, REGU_ID_CONF_NAME, strlen(REGU_ID_CONF_NAME))) + { + regu_id_conf_num++; + } + } + + if (!regu_id_conf_num) + { + printf("No %s node in dts\n", REGU_ID_CONF_NAME); + return -1; + } + + pmic_regu_id_list = devm_kcalloc(dev, 1, regu_id_conf_num * sizeof(csi_regu_id_t), GFP_KERNEL); + if (!pmic_regu_id_list) + { + printf("pmic regu list malloc faild\n"); + return -ENOMEM; + } + + ret = misc_regu_get_regu_config(parent_node, pmic_dev_num, pmic_dev_info_list, virtual_id_num, regu_list, pmic_regu_id_list); + if (ret) + { + printf("get regu config faild %d\n", ret); +#warning "free" + return -1; + } + + (*pmic_list).pmic_num = pmic_dev_num; + (*pmic_list).pmic_list = pmic_dev_info_list; + + (*regu_id_list).regu_id_num = regu_id_conf_num; + (*regu_id_list).regu_id_list = pmic_regu_id_list; + + return 0; +} + +static int misc_regu_bind(struct udevice *dev) +{ + struct mic_regu_platdata *plat = dev_get_platdata(dev); + ofnode parent_node = dev->node; + + int ret; + ofnode child_node, node, regu_node, aon_conf_node; + const void *blob = gd->fdt_blob; + int subnode; + struct udevice *dev_1; + + /* If this is a child device, there is nothing to do here */ + if (plat) + { + return 0; + } + + if (!ofnode_valid(parent_node)) + { + printf("aon node not ok\n"); + return -1; + } + + int get_regu_dts_flag = 0; + int get_aon_conf_dst_flag = 0; + + ofnode_for_each_subnode(child_node, parent_node) + { + /* Increment base_id for all subnodes, also the disabled ones */ + //printf("sub node name: %s\n", ofnode_get_name(child_node)); + if (!strncmp(ofnode_get_name(child_node), REGU_DTS_NAME, strlen(REGU_DTS_NAME))) + { + regu_node = child_node; + get_regu_dts_flag = 1; + } + if (!strncmp(ofnode_get_name(child_node), AON_CONF_NAME, strlen(AON_CONF_NAME))) + { + aon_conf_node = child_node; + get_aon_conf_dst_flag = 1; + } + } + + + + if (!get_regu_dts_flag) + { + printf("No %s node in dts\n", REGU_DTS_NAME); + return -1; + } + + if (!get_aon_conf_dst_flag) + { + printf("No %s node in dts\n", AON_CONF_NAME); + return -1; + } + + plat = devm_kcalloc(dev, 1, sizeof(struct mic_regu_platdata), GFP_KERNEL); + if (!plat) + { + return -ENOMEM; + } + + plat->wakeup_flag = 0; + + if (ofnode_read_bool(parent_node, "wakeup-by-gpio-on")) { + plat->wakeup_flag |= AON_WAKEUP_BY_GPIO; + printf("aon wakeup by gpio enabled\n"); + } + + if (ofnode_read_bool(parent_node, "wakeup-by-rtc-on")) { + plat->wakeup_flag |= AON_WAKEUP_BY_RTC; + printf("aon wakeup by rtc enabled\n"); + } + + ret = misc_regu_get_virtual_regu_config(dev, regu_node, &plat->regu_list); + if (ret) + { + printf("get virtual regu config failed %d\n", ret); + return -1; + } + + ret = misc_regu_get_aon_pmic_config(dev, aon_conf_node, plat->regu_list.regu_num, plat->regu_list.regu_list, &plat->pmic_list, &plat->regu_id_list); + if (ret) + { + printf("get aon config failed %d\n", ret); + return -1; + } + + plat->name = ofnode_get_name(parent_node); + + ret = device_bind_ofnode(dev, dev->driver, plat->name, plat, parent_node, &dev_1); + if (ret) + { + printf("bind device faild %d", ret); + return ret; + } + /*fix me err usage*/ + dev->platdata = plat; + + return 0; +} + +static const struct udevice_id misc_regu_ids[] = { + {.compatible = "thead,light-aon"}, + {}}; + +U_BOOT_DRIVER(light_regu) = { + .name = "light_regu,misc", + .id = UCLASS_MISC, + .of_match = misc_regu_ids, + .probe = misc_regu_probe, + .bind = misc_regu_bind, + .remove = misc_regu_remove, +}; diff --git a/drivers/misc/light_regu.h b/drivers/misc/light_regu.h new file mode 100644 index 00000000..c383ffa5 --- /dev/null +++ b/drivers/misc/light_regu.h @@ -0,0 +1,229 @@ +#ifndef __LIGHT_REGU_H__ +#define __LIGHT_REGU_H__ + + +typedef enum +{ + SOC_DVDD18_AON, /*da9063: ldo-3 */ + SOC_AVDD33_USB3, /*da9063: ldo-9 */ + SOC_DVDD08_AON, /*da9063: ldo-2 */ + SOC_APCPU_DVDD_DVDDM, /*da9063: vbcore1 & vbcore2*/ + SOC_DVDD08_DDR, /*da9063: buckperi */ + SOC_VDD_DDR_1V8, /*da9063: ldo-4 */ + SOC_VDD_DDR_1V1, /*da9063: buckmem & buckio */ + SOC_VDD_DDR_0V6, /*da9063: buckpro */ + SOC_DVDD18_AP, /*da9063: ldo-11 */ + SOC_DVDD08_AP, /*da9121: da9121_ex */ + SOC_AVDD08_MIPI_HDMI, /*da9063: ldo-1 */ + SOC_AVDD18_MIPI_HDMI, /*da9063: ldo-5 */ + SOC_DVDD33_EMMC, /*da9063: ldo-10 */ + SOC_DVDD18_EMMC, /*slg51000:ldo-3 */ + SOC_DOVDD18_SCAN, /*da9063: ldo-6 */ + SOC_VEXT_2V8, /*da9063: ldo-7 */ + SOC_DVDD12_SCAN, /*da9063: ldo-8 */ + SOC_AVDD28_SCAN_EN, /*da9063: gpio-4,SGM2019-ADJ */ + SOC_AVDD28_RGB, /*slg51000:ldo-1 */ + SOC_DOVDD18_RGB, /*slg51000:ldo-4 */ + SOC_DVDD12_RGB, /*slg51000:ldo-5 */ + SOC_AVDD25_IR, /*slg51000:ldo-2 */ + SOC_DOVDD18_IR, /*slg51000:ldo-7 */ + SOC_DVDD12_IR, /*slg51000:ldo-6 */ + SOC_ADC_VREF, + SOC_LCD0_EN, + SOC_VEXT_1V8, + + SOC_REGU_INVALID = 0xFF +} soc_virtual_id_en; + + +#define REGU_DTS_NAME "light-regu-reg" +#define AON_CONF_NAME "aon_pmic_config" +#define PMIC_DEV_DTS_NAME "pmic-dev" +#define REGU_ID_CONF_NAME "regu_config" +#define REGU_ID_NAME "regu_id" +#define COUPLING_ID_INFO_NAME "coupling_info" + + + +#define PMIC_DEV_ENABLE_WDT (1U << 0) +#define PMIC_DEV_ENABLE_ERR_IO (1U << 1) +#define PMIC_DEV_ENABLE_LPM_IO (1U << 2) + +#define HW_ID_NO_SOFT_AUTO_ON (0xff) +#define HW_ID_NO_SOFT_AUTO_OFF (0xff) +#define HW_ID_INVALID (0xff) +#define PMIC_ID_INVALID (0xff) +#define REGU_SUB_ID_INVALID (0xff) + +#define REGU_EXT_ID_NAME_LEN 30 +#define PMIC_DEV_NAME_LEN 20 +#define PMIC_DEV_VERSION_LEN 20 + +#define PMIC_MAX_HW_ID_NUM 3 +#define PMIC_MAX_COUPLING_NUM 3 + +#define AON_WAKEUP_BY_GPIO (1 << 0) +#define AON_WAKEUP_BY_RTC (1 << 1) + +typedef enum { + HW_ID_ACTIVATE_HIGH = 0U, + HW_ID_ACTIVATE_LOW = 1U, +} hw_activate_status_en; + +typedef struct __packed { + uint8_t pmic_id; + uint8_t io_hw_id; + uint8_t activate_status; +} pmic_parent_hw_io_ctrl_info_t; + +typedef struct __packed { + uint8_t on_order; + uint8_t on_delay_ms; + uint32_t init_target_uv; +} regu_soft_power_ctrl_on_t; + +typedef struct __packed { + uint8_t off_order; + uint8_t off_delay_ms; +} regu_soft_power_ctrl_off_t; + +typedef struct __packed { + regu_soft_power_ctrl_on_t on_info; + regu_soft_power_ctrl_off_t off_info; +} regu_soft_power_ctrl_t; + + +typedef struct __packed { + uint8_t id0; + uint8_t id1; + int8_t max_spread; // mv/10 + int8_t min_spread; // mv/10 +}coupling_desc_t; + + +typedef struct __packed { + uint8_t pmic_id; + uint8_t hw_id; + uint8_t benable; + pmic_parent_hw_io_ctrl_info_t parent_hw_info; + regu_soft_power_ctrl_t soft_power_ctrl_info; +} pmic_hw_info_t; + + +typedef struct __packed{ + coupling_desc_t coupling_list[PMIC_MAX_COUPLING_NUM]; + pmic_hw_info_t id[PMIC_MAX_HW_ID_NUM]; ///< sub id1 for single-rail or first src of dual-rail +}pmic_hw_id_t; + +typedef struct __packed { + uint8_t regu_ext_id; ///< virtual global regulator id + char regu_ext_id_name[REGU_EXT_ID_NAME_LEN]; ///< vitual regu-id name + pmic_hw_id_t sub; ///< sub id set for dual-rail/single-rail regulator +}csi_regu_id_t; + +typedef enum { + PMIC_CTRL_BY_AON_GPIO = 0U, + PMIC_CTRL_BY_PMIC_GPIO = 1U, + PMIC_CTRL_BY_NOTHINTG = 0xFF, +} pmic_ctrl_info_en; + +typedef struct __packed { + uint8_t port; + uint8_t pin; + uint8_t activate_status; +} pmic_ctrl_by_aon_info_t; + +typedef struct __packed { + uint8_t pmic_id; + uint8_t io_hw_id; + uint8_t activate_status; +} pmic_ctrl_by_pmic_info_t; + +typedef struct __packed { + uint8_t pmic_ctrl_type; + union { + pmic_ctrl_by_aon_info_t aon_io_info; + pmic_ctrl_by_pmic_info_t pmic_io_info; + }; +} pmic_parent_ctrl_info_t; + +typedef struct __packed{ + uint16_t gpio_port; + uint16_t pin; + uint8_t trigger_mode; +} pmic_interrupt_io_info_t; + +typedef struct __packed { + char device_name[PMIC_DEV_NAME_LEN]; + char version_name[PMIC_DEV_VERSION_LEN]; + uint8_t pmic_id; + uint8_t addr1; + uint8_t addr2; + uint8_t flag; /*support wdt|errio| lpm io*/ + uint8_t slew_rate; + uint32_t wdt_len; + pmic_interrupt_io_info_t err_io_info; + pmic_interrupt_io_info_t lpm_io_info; + pmic_parent_ctrl_info_t ctrl_info; +} pmic_dev_info_t; + +typedef struct +{ + soc_virtual_id_en id; + char virtual_id_name[REGU_EXT_ID_NAME_LEN]; + int min_uv; + int max_uv; +} soc_virtual_id_t; + +typedef struct +{ + int regu_num; + soc_virtual_id_t *regu_list; +} virtual_regu_list_t; + +typedef struct +{ + int pmic_num; + pmic_dev_info_t *pmic_list; +} pmic_dev_list_t; + +typedef struct +{ + int regu_id_num; + csi_regu_id_t *regu_id_list; +} regu_id_list_t; + +struct mic_regu_platdata +{ + const char *name; + uint32_t wakeup_flag; + virtual_regu_list_t regu_list; + pmic_dev_list_t pmic_list; + regu_id_list_t regu_id_list; +}; + + +#define AON_CONFIG_MAGIC "AON_CONFIG" +#define AON_CONFIG_VERSION "1.0.0" + +typedef struct __packed{ + uint8_t iic_id; + uint8_t pmic_dev_num; + uint8_t regu_num; + int pmic_dev_list_offset; + int regu_id_list_offset; +}aon_pmic_config_t; + +typedef struct __packed{ + const char magic[11]; + const char version[11]; + uint8_t max_hw_id_num; + uint64_t aon_config_partition_size; + uint32_t wakeup_flag; + aon_pmic_config_t aon_pmic; +} aon_config_t; + + + + +#endif \ No newline at end of file diff --git a/drivers/misc/misc-uclass.c b/drivers/misc/misc-uclass.c index 55381edc..92335287 100644 --- a/drivers/misc/misc-uclass.c +++ b/drivers/misc/misc-uclass.c @@ -13,7 +13,6 @@ * general classes. A set of generic read, write and ioctl methods may * be used to access the device. */ - int misc_read(struct udevice *dev, int offset, void *buf, int size) { const struct misc_ops *ops = device_get_ops(dev); diff --git a/drivers/mmc/sdhci.c b/drivers/mmc/sdhci.c index 5cc70cda..7d88320b 100644 --- a/drivers/mmc/sdhci.c +++ b/drivers/mmc/sdhci.c @@ -38,9 +38,7 @@ static void sdhci_reset(struct sdhci_host *host, u8 mask) timeout--; udelay(1000); } -#ifdef CONFIG_TARGET_LIGHT_C910 - mdelay(50); -#endif + } static void sdhci_cmd_done(struct sdhci_host *host, struct mmc_cmd *cmd) diff --git a/drivers/video/Kconfig b/drivers/video/Kconfig index 5a85ce6e..a637c233 100644 --- a/drivers/video/Kconfig +++ b/drivers/video/Kconfig @@ -357,7 +357,14 @@ config VIDEO_LCD_MINGJUN_070BI30IA2 select VIDEO_MIPI_DSI help Say Y here if you want to enable support for Mingjun 070BI30IA2 - 800x1280 DSI video mode panel. + 800x1280 DSI video mode panel. + +config VIDEO_LCD_JD9365DA + bool "JD9365DA DSI LCD panel support" + depends on DM_VIDEO + select VIDEO_MIPI_DSI + help + Say Y here if you want to enable support for JD9365DA config VIDEO_LCD_CUSTOM_LOGO bool "LCD CUSTOM logo support" diff --git a/drivers/video/Makefile b/drivers/video/Makefile index 42885a6c..8bc9d99f 100644 --- a/drivers/video/Makefile +++ b/drivers/video/Makefile @@ -70,6 +70,7 @@ obj-$(CONFIG_VIDEO_SIMPLE) += simplefb.o obj-$(CONFIG_VIDEO_TEGRA20) += tegra.o obj-$(CONFIG_VIDEO_VCXK) += bus_vcxk.o obj-$(CONFIG_VIDEO_VESA) += vesa.o +obj-$(CONFIG_VIDEO_LCD_JD9365DA) += jadard-jd9365da-h3.o obj-y += bridge/ obj-y += sunxi/ diff --git a/drivers/video/jadard-jd9365da-h3.c b/drivers/video/jadard-jd9365da-h3.c new file mode 100644 index 00000000..fd1978b7 --- /dev/null +++ b/drivers/video/jadard-jd9365da-h3.c @@ -0,0 +1,238 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (c) 2019 Radxa Limited + * Copyright (c) 2022 Edgeble AI Technologies Pvt. Ltd. + * + * Author: + * - Jagan Teki + * - Stephen Chen + */ + +#include +#include +#include +#include +#include +#include + +struct jadard_panel_desc { + const struct display_timing *timing; + unsigned long mode_flags; + enum mipi_dsi_pixel_format format; + unsigned int lanes; +}; + +struct panel_info { + const struct jadard_panel_desc *desc; + struct gpio_desc reset; + struct gpio_desc hsvcc; + struct gpio_desc vspn3v3; + bool prepared; + bool enabled; +}; + +static int jd9365_get_display_timing(struct udevice *dev, + struct display_timing *timings) +{ + struct mipi_dsi_panel_plat *plat = dev_get_platdata(dev); + struct mipi_dsi_device *device = plat->device; + struct panel_info *pinfo = dev_get_priv(dev); + + memcpy(timings, pinfo->desc->timing, sizeof(*timings)); + + device->lanes = pinfo->desc->lanes; + device->format = pinfo->desc->format; + device->mode_flags = pinfo->desc->mode_flags; + + return 0; +} + +static int jadard_prepare(struct udevice *panel) +{ + struct panel_info *pinfo = dev_get_priv(panel); + int ret; + + if (pinfo->prepared) + return 0; + dm_gpio_set_value(&pinfo->reset, false); + + /* Power the panel */ + ret = dm_gpio_set_value(&pinfo->hsvcc, true); + if (ret) { + return ret; + } + + mdelay(1); + ret = dm_gpio_set_value(&pinfo->vspn3v3, true); + if (ret) { + return ret; + } + mdelay(1); + + dm_gpio_set_value(&pinfo->reset, true); + mdelay(10); + + pinfo->prepared = true; + + return 0; +} + +static int jadard_enable(struct udevice *panel) +{ + struct mipi_dsi_panel_plat *plat = dev_get_platdata(panel); + struct mipi_dsi_device *dsi = plat->device; + struct panel_info *pinfo = dev_get_priv(panel); + u8 power_mode; + int ret; + + if (pinfo->enabled) + return 0; + + dsi->mode_flags |= MIPI_DSI_MODE_LPM; + + /* sanity test for connection */ + ret = mipi_dsi_dcs_get_power_mode(dsi, &power_mode); + if (ret) { + dev_warn(dsi->dev, "%s: failed to get power mode: %d\n", __func__, ret); + return ret; + } + + ret = mipi_dsi_dcs_set_tear_on(dsi, MIPI_DSI_DCS_TEAR_MODE_VBLANK); + if (ret) + return ret; + + ret = mipi_dsi_dcs_exit_sleep_mode(dsi); + if (ret) + { + return ret; + } + + mdelay(10); + + ret = mipi_dsi_dcs_set_display_on(dsi); + if (ret){ + return ret; + } + + pinfo->enabled = true; + + return 0; +} + +static int jd9365_panel_enable(struct udevice *dev) +{ + struct mipi_dsi_panel_plat *plat = dev_get_platdata(dev); + struct mipi_dsi_device *device = plat->device; + int ret; + + ret = mipi_dsi_attach(device); + if (ret < 0) + return ret; + + ret = jadard_enable(dev); + if (ret) + return ret; + + return 0; +} + +static const struct display_timing txd_jd9365_timing = { + .pixelclock.typ = 74250000, + .hactive.typ = 800, + .hfront_porch.typ = 60, + .hback_porch.typ = 60, + .hsync_len.typ = 40, + .vactive.typ = 1280, + .vfront_porch.typ = 16, + .vback_porch.typ = 16, + .vsync_len.typ = 8, + .flags = DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW, +}; + +static const struct jadard_panel_desc jd9365_panel_desc = { + .timing = &txd_jd9365_timing, + .mode_flags = MIPI_DSI_MODE_VIDEO | MIPI_DSI_MODE_VIDEO_BURST, + .format = MIPI_DSI_FMT_RGB888, + .lanes = 4, +}; + +static int jd9365_panel_ofdata_to_platdata(struct udevice *dev) +{ + struct panel_info *pinfo = dev_get_priv(dev); + int ret; + + ret = gpio_request_by_name(dev, "reset-gpio", 0, + &pinfo->reset, GPIOD_IS_OUT); + if (ret) { + dev_err(dev, "Warning: cannot get reset GPIO\n"); + if (ret != -ENOENT) + return ret; + } + + ret = gpio_request_by_name(dev, "hsvcc-gpio", 0, + &pinfo->hsvcc, GPIOD_IS_OUT); + if (ret) { + dev_err(dev, "Warning: cannot get hsvcc GPIO\n"); + if (ret != -ENOENT) + return ret; + } + + ret = gpio_request_by_name(dev, "vspn3v3-gpio", 0, + &pinfo->vspn3v3, GPIOD_IS_OUT); + if (ret) { + dev_err(dev, "Warning: cannot get vspn3v3 GPIO\n"); + if (ret != -ENOENT) + return ret; + } + + return 0; +} + +static int jadard_dsi_probe(struct udevice *panel) +{ + int ret; + struct panel_info *pinfo = dev_get_priv(panel); + + pinfo->desc = (const struct jadard_panel_desc*)dev_get_driver_data(panel); + + ret = jadard_prepare(panel); + if (ret) { + dev_err(panel, "failed to prepare panel : %d\n", ret); + return ret; + } + + return 0; +} + +static int jadard_dsi_remove(struct udevice *panel) +{ + return 0; +} + +static const struct panel_ops jd9365_panel_ops = { + .enable_backlight = jd9365_panel_enable, + .get_display_timing = jd9365_get_display_timing, +}; + +static const struct udevice_id panel_of_match[] = { + { + .compatible = "jadard,jd9365da-h3", + .data = (ulong)&jd9365_panel_desc, + }, + { + /* sentinel */ + } +}; + +U_BOOT_DRIVER(jadard_jd9365da) = { + .name = "jadard_jd9365da", + .id = UCLASS_PANEL, + .of_match = panel_of_match, + .ops = &jd9365_panel_ops, + .ofdata_to_platdata = jd9365_panel_ofdata_to_platdata, + .probe = jadard_dsi_probe, + .remove = jadard_dsi_remove, + .platdata_auto_alloc_size = sizeof(struct mipi_dsi_panel_plat), + .priv_auto_alloc_size = sizeof(struct panel_info), +}; + diff --git a/include/configs/light-c910.h b/include/configs/light-c910.h index 628981f9..03b02057 100644 --- a/include/configs/light-c910.h +++ b/include/configs/light-c910.h @@ -30,10 +30,15 @@ #define CONFIG_SYS_BOOTM_LEN SZ_64M #define CONFIG_SYS_CACHELINE_SIZE 64 +#define CONFIG_CMD_READ 1 + #define SRAM_BASE_ADDR 0xffe0000000 #define PLIC_BASE_ADDR 0xffd8000000 #define PMP_BASE_ADDR 0xffdc020000 +#define MINIMAL_DDR_DENSITY_MB (1*1024) +#define MAXIMAL_DDR_DENSITY_MB (16*1024) +#define UNIT_MB (1024*1024) /* Network Configuration */ #define CONFIG_DW_ALTDESCRIPTOR @@ -127,6 +132,8 @@ #define ENV_STR_SERIAL "serial#=\0" #define ENV_KERNEL_KDUMP "kdump_buf=0M\0" #endif +/*public bootargs in mostly boards, make env 'set_booargs' shorter and clean */ +#define ENV_PUBLIC_BOOTARGS "pub_bootargs=rootfstype=ext4 rdinit=/sbin/init rootwait rw earlycon clk_ignore_unused\0" #define CONFIG_MISC_INIT_R @@ -163,12 +170,12 @@ "partitions=name=table,size=2031KB;name=boot,size=500MiB,type=boot;name=swap,size=4096MiB,type=swap,uuid=${uuid_swap};name=root,size=-,type=linux,uuid=${uuid_rootfsA}\0" \ "gpt_partition=gpt write mmc ${emmc_dev} $partitions\0" \ "sdcard_gpt_partition=gpt write mmc ${sdcard_dev} $partitions\0" \ - "load_aon=load mmc ${mmcdev}:${mmcbootpart} $fwaddr light_aon_fpga.bin;cp.b $fwaddr $aon_ram_addr $filesize\0" \ + "load_aon=load mmc ${mmcdev}:${mmcbootpart} $fwaddr light_aon_fpga.bin;cp.b $fwaddr $aon_ram_addr $filesize;bootaon\0" \ "load_c906_audio=load mmc ${mmcdev}:${mmcbootpart} $fwaddr light_c906_audio.bin;cp.b $fwaddr $audio_ram_addr $filesize\0" \ "load_str=load mmc ${mmcdev}:${mmcbootpart} $fwaddr str.bin;cp.b $fwaddr $str_ram_addr $filesize\0" \ "load_opensbi=load mmc ${mmcdev}:${mmcbootpart} $opensbi_addr fw_dynamic.bin\0" \ "bootcmd_load=run mmc_select; run load_aon; run load_c906_audio; run load_str; run load_opensbi\0" \ - "bootcmd=run bootcmd_load; bootslave; sysboot mmc ${mmcdev}:${mmcbootpart} any $boot_conf_addr_r $boot_conf_file;\0" \ + "bootcmd=run bootcmd_load; chk_hibernate; fixup_memory_region; bootslave; sysboot mmc ${mmcdev}:${mmcbootpart} any $boot_conf_addr_r $boot_conf_file;\0" \ "fdtfile=" CONFIG_DEFAULT_FDT_FILE "\0" \ "\0" diff --git a/include/dt-bindings/pmic/light_pmic.h b/include/dt-bindings/pmic/light_pmic.h new file mode 100644 index 00000000..71c58548 --- /dev/null +++ b/include/dt-bindings/pmic/light_pmic.h @@ -0,0 +1,55 @@ +#ifndef __LIGHT_PMIC_H_ +#define __LIGHT_PMIC_H_ + +/*for da9063*/ +#define DA9063_ID_BCORE1 0 +#define DA9063_ID_BCORE2 1 +#define DA9063_ID_BUCKPRO 2 +#define DA9063_ID_BUCKMEM 3 +#define DA9063_ID_BUCKIO 4 +#define DA9063_ID_BUCKPERI 5 +#define DA9063_ID_LDO1 6 +#define DA9063_ID_LDO2 7 +#define DA9063_ID_LDO3 8 +#define DA9063_ID_LDO4 9 +#define DA9063_ID_LDO5 10 +#define DA9063_ID_LDO9 11 +#define DA9063_ID_LDO10 12 +#define DA9063_ID_LDO11 13 +#define DA9063_ID_LDO6 14 +#define DA9063_ID_LDO7 15 +#define DA9063_ID_LDO8 16 +#define DA9063_ID_GPIO4 17 +#define DA9063_ID_GPIO7 18 + +/*for da9121*/ +#define DA9121_ID_BUCK1 0 + + +/* for slg51000*/ + +#define SLG51000_ID_LDO1 0 +#define SLG51000_ID_LDO2 1 +#define SLG51000_ID_LDO3 2 +#define SLG51000_ID_LDO4 3 +#define SLG51000_ID_LDO5 4 +#define SLG51000_ID_LDO6 5 +#define SLG51000_ID_LDO7 6 + + +/* for ricoh567*/ +#define RICOH567_ID_DC1 0 +#define RICOH567_ID_DC2 1 +#define RICOH567_ID_DC3 2 +#define RICOH567_ID_DC4 3 +#define RICOH567_ID_LDO1 4 +#define RICOH567_ID_LDO2 5 +#define RICOH567_ID_LDO3 6 +#define RICOH567_ID_LDO4 7 +#define RICOH567_ID_LDO5 8 +#define RICOH567_ID_LDORTC1 9 +#define RICOH567_ID_LDORTC2 10 +#define RICOH567_ID_GPIO3 11 + + +#endif \ No newline at end of file